WO2022100860A1

WO2022100860A1 - Detecting intensity modulated optical signal by low bandwidth receiving device

Info

Publication number: WO2022100860A1
Application number: PCT/EP2020/082187
Authority: WO
Inventors: Ivan Nicolas Cano Valadez
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2020-11-16
Filing date: 2020-11-16
Publication date: 2022-05-19
Also published as: CN115552813A

Abstract

A method for detecting an intensity modulated optical signal by a low bandwidth receiving device, includes receiving, by a processor, the intensity modulated optical signal. A first multilevel detection is performed at M levels on the intensity modulated optical signal, where M>1. Further, a second multilevel detection is performed at N levels on the intensity modulated optical signal, where N>M. The detected M level signal is transformed into an expected N level signal. Based on a comparison of the expected N level signal and the detected N level signal, an error is detected in the detected M level signal. Based on the detected error, the detected M level signal is corrected.

Description

DETECTING INTENSITY MODULATED OPTICAL SIGNAL BY LOW

BANDWIDTH RECEIVING DEVICE

TECHNICAL FIELD

The present disclosure relates generally to the field of optical communication; and more specifically, to methods and apparatus for detecting an intensity modulated optical signal by a low bandwidth receiving device.

BACKGROUND

Existing telecommunication infrastructure deploys various types of optical networks, e.g., from long-haul core networks to edge/regional/metro, and even short-haul transmission systems (such as access networks). However, due to ever increasing bandwidth demands, such infrastructure is facing strong stress to upgrade its transmission capacity and bandwidth in a cost-effective manner. Currently, the cost of optical components for data rate of lOGb/s, specifically for 25Gb/s and 50Gb/s, is very high as compared with the ones used for Gigabit Passive Optical Networks (GPON) (2.5 Gb/s). In particular, an optical network unit (ONU) receiver is based on avalanche photodiode (APD) which is mostly used in access networks, and thus cannot expect to use economies of scale from other applications. Furthermore, the ONU receiver requires to detect a complete signal and also, it must have a very low cost for it to be commercially attractive. In order to reduce the cost of an optical transceiver, lower bandwidth components, such as a low bandwidth receiver, may be used that aid a smooth interoperability with several bitrates.

Currently, one of the major challenges that arises in optical communication is to properly detect an intensity modulated signal (such as non-return to zero, NRZ signal) with the low bandwidth receiver. When detecting the NRZ signal with the low bandwidth optical receiver, if the photodiode bandwidth is low (<0.5*Bitrate), then multiple levels appear in the electrical signal. If the bandwidth is enough (>0.3* Bitrate), the signal can still be recovered with a conventional two-level detection based on a single threshold. However, at high bitrates (e.g. 50Gb/s) chromatic dispersion can cause a penalty higher than 1 dB. The chromatic dispersion can further cause intersymbol interference (ISI), which can be considered as a multilevel signal (e.g. 1 bit memory system). Currently, certain attempts have been made in order to detect the intensity modulated signal with a low bandwidth receiver and simple electronic processing to compensate for errors while the transmitter can optionally have a precoder. However, conventional methods and systems for such detection require a precoder that limits the interoperability and inherently penalize the receiver sensitivity, require power-hungry digital signal processors, and reduce gain for lower frequencies while compensating frequencies of higher data rate. For example, in some conventional methods such as electrical duobinary detection, a precoder is used in a transmitter, and a three-level is detected in case of transmitting the NRZ signal. However, the disadvantage is that it requires a precoder, which might limit the interoperability and there is an inherent penalty in the receiver sensitivity. In another example, some conventional methods, e.g., a complex digital signal processing (DSP) technique, such as Maximum Likelihood Sequence Estimation (MLSE) or decision feedback equalizer (DFE), may be employed. However, the main disadvantage of such approach is that it requires power-hungry DSP, and the computation of the coefficients can cause a problem. In yet another example, some conventional methods, e.g., a continuous time linear equalization (CTLE) may be used after the receiver to enhance high frequencies. While this can be useful for data rate of lOGb/s, it might not be the case for 25Gb/s or 50Gb/s as the frequencies to be compensated are very high and thus, the gain of lower frequencies is reduced.

Therefore, in light of the foregoing discussion, there exists a need to overcome the drawbacks associated with the conventional chromatic dispersion estimation and compensation techniques.

SUMMARY

The present disclosure seeks to provide a method, an apparatus, and a computer program product for detecting an intensity modulated optical signal by a low bandwidth receiver. The present disclosure seeks to provide a solution to the existing problems of detection that requires a precoder that limits the interoperability and inherently penalizes the receiver sensitivity, requires power-hungry digital signal processors, and reduces gain for lower frequencies while compensating frequencies of higher data rate. An aim of the present disclosure is to provide a solution that overcomes at least partially the problems encountered in the prior art, and provides an improved method and apparatus that is able to detect an intensity modulated signal with a low bandwidth receiver and compensate for errors while the transmitter can optionally have a precoder. Accordingly, the improved method and apparatus minimizes complexity to avoid a high cost and power consumption, and is operable with several transmitters from different vendors, thereby limiting the use of precoding techniques.

The object of the present disclosure is achieved by the solutions provided in the enclosed independent claims. Advantageous implementations of the present disclosure are further defined in the dependent claims.

In one aspect, the present disclosure provides a computer-implemented method for detecting an intensity modulated optical signal at a receiving device. The method comprises receiving, by a processor, an input optical signal. The method further comprises performing, by the processor, a first multilevel detection at M levels on the input signal, where M>1. The method further comprises performing, by the processor, a second multilevel detection at N levels on the input signal, where N>M. The method further comprises transforming, by the processor, the detected M level signal into an expected N level signal. The method further comprises detecting, by the processor, an error in the detected M level signal based on a comparison of the expected N level signal and the detected N level signal. The method further comprises correcting, by the processor, the detected M level signal based on the detected error.

The method enables an accurate detection of an intensity modulated optical signal by a low bandwidth receiving device. The method is based on detecting two and more levels simultaneously and combining the decision process electronically to detect and correct errors from the conventional detection (e.g. 2-levels) with the values from the multilevel detection (e.g. >2 levels). The method implements simple electronic processing to compensate for errors while the transmitter can optionally have a precoder. Thus, the method is very simple to implement digitally. The only computational elements are the ones that provide level threshold values. In one embodiment, simple feed-forward equalizer (FFE) filters may also be implemented to improve the performance. In addition, the results have shown that it is not constrained to a single value of the receiver bandwidth and performs even better than an electrical duobinary detection.

Moreover, the method can be implemented with low level of complexity and computational load as the only logical gates and slicers are used thereby avoiding analogue to digital converters (ADCs). Accordingly, the processing is simple and could be done with logical gates.

In an implementation form, the input optical signal includes a string of symbols. The use of the string of symbols leads to a more precise detection and correction of bit errors.

In a further implementation form, the string of symbols is a binary string or an amplitude- modulated string with a plurality of levels.

The disclosed method is applicable to an analogue as well as a digital signal. Therefore, the input optical signal includes a string of symbols, such as a binary string or an amplitude- modulated string with a plurality of levels. In an example, the string of symbols may be a sequence of “0”s and “l”s, like 111000110001. In another example, the string of symbols may correspond to an amplitude-modulated string with a plurality of levels.

In a further implementation form, the transforming includes generating a sum of a current symbol and an immediately preceding symbol.

The sum of the current symbol and the immediately preceding symbol results into an upper level transformation which results a more precise error detection and correction.

In a further implementation form, detecting the error in the detected M level signal includes detecting a disagreement between the expected N level signal and the detected N level signal for two consecutive symbols.

The disagreement is detected between the expected N level signal and the detected N level signal based on a comparison of the expected N level signal and the detected N level signal. One error in the M level detection translates into two consecutive errors in the N-level detection due to an addition of consecutive bits (a bit is added in the current and past symbol). Based on this information, consecutive error symbols are searched for error correction.

In a further implementation form, the comparison of the expected N level signal and the detected N level signal includes a further transformation of the expected N level signal and the detected N level signal, based on a two-symbol delay.

The comparison provides a signal difference before detecting the errors. Such companion enables to identify the bit locations of the error bits when the expected N level signal is compared (or XORed) with the detected N level symbol.

In a further implementation form, M = 2. By virtue of the fact that the value of M is 2, a conventional clock and data recovery (CDR) may be used for the 2-level signal. The power penalty for higher values of M increases substantially, thereby degrading the system performance.

In a further implementation form, N = 2M-1.

The value of N is based on the value of M, which indicates a higher level signal that may be used to correct any error in the M level signal.

In a further implementation form, receiving includes receiving the input optical signal using a photodiode, wherein the photodiode is limited in bandwidth.

Use of a single PD may detect several bitrates and may scale to higher bitrates as well. Further, the receiver sensitivity has a limited penalty as compared to a full bandwidth receiver.

In a further implementation form, receiving further incudes applying an electrical filter to the input optical signal.

The method facilitates several enhancements, such as using particular filters for each level detector in case an ADC is used. To detect the M levels, a simple electrical filter (or equalizer) may be added. To separate the N levels for making the N-levels more pronounced, another electrical filter (or equalizer) may be added.

In a further implementation form, performing the second multilevel detection includes applying a low-pass filter configured to separate the N levels.

The low-pass filter is used to improve the detection as well as separation of multiple levels of the input optical signal.

In a further implementation form, the method further comprises further including applying a technique to compensate for the low bandwidth to detect the M levels.

The disclosed method is applicable to a bandwidth range in spite of a single value of the bandwidth.

In another aspect, the present disclosure provides a receiving device for detecting an intensity modulated optical signal. The receiving device comprises a control circuitry that is configured to receive an input optical signal. The control circuitry is further configured to perform a first multilevel detection at M levels on the input signal, where M>1. The control circuitry is further configured to perform a second multilevel detection at N levels on the input signal, where N>M. The control circuitry is further configured to transform the detected M level signal into an expected N level signal. The control circuitry is further configured to detect an error in the detected M level signal based on a comparison of the expected N level signal and the detected N level signal. The control circuitry is further configured to correct the detected M level signal based on the detected error.

In further implementation forms, the control circuitry is configured to perform the features of the implementation forms of the method according to the first aspect. Hence, implementation forms of the receiving device comprise the feature(s) of the corresponding implementation form of the method of the first aspect.

The receiving device achieves all the advantages and effects of the method of the first aspect.

In yet another aspect, the present disclosure provides computer program product comprising a non-transitory computer-readable storage medium having computer-readable instructions stored thereon, the computer-readable instructions being executable by a computerised device comprising processing hardware to execute the aforementioned method of the first aspect.

The computer program product of the third aspect achieves all the advantages and effects of the method of the first aspect.

It has to be noted that all devices, elements, circuitry, units and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof. It will be appreciated that features of the present disclosure are susceptible to being combined in various combinations without departing from the scope of the present disclosure as defined by the appended claims. Additional aspects, advantages, features and objects of the present disclosure would be made apparent from the drawings and the detailed description of the illustrative implementations construed in conjunction with the appended claims that follow.

BRIEF DESCRIPTION OF THE DRAWINGS

The summary above, as well as the following detailed description of illustrative embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the present disclosure, exemplary constructions of the disclosure are shown in the drawings. However, the present disclosure is not limited to specific methods and instrumentalities disclosed herein. Moreover, those in the art will understand that the drawings are not to scale. Wherever possible, like elements have been indicated by identical numbers.

Embodiments of the present disclosure will now be described, by way of example only, with reference to the following diagrams wherein:

FIG. 1 is a flowchart of a method for detecting an intensity modulated optical signal by a receiving device, in accordance with an embodiment of the present disclosure;

FIG. 2A is a network environment of a system with a transmitting device and a receiving device, in accordance with an embodiment of the present disclosure;

FIG. 2B is a first block diagram that illustrates various exemplary components of a receiving device, in accordance with an embodiment of the present disclosure;

FIG. 2C is a second block diagram that illustrates various exemplary components of a receiving device, in accordance with an embodiment of the present disclosure;

FIG. 3A is an illustration of a first eye diagram of an NRZ signal at a high bandwidth optical frontend, in accordance with an embodiment of the present disclosure;

FIG. 3B is an illustration of a second eye diagram of an NRZ signal at a low bandwidth optical frontend, in accordance with an embodiment of the present disclosure;

FIG. 3 C is an illustration of a sampling instant and one threshold value provided by a middle level slicer, in accordance with an embodiment of the present disclosure; FIG. 3D is an illustration of a sampling instant and two threshold values provided by upper and lower level slicers, in accordance with an embodiment of the present disclosure;

FIG. 4A is a network environment of a first exemplary system for detection of intensity modulated optical signal, in accordance with an embodiment of the present disclosure;

FIG. 4B is a detailed diagram of various components in the processor, in accordance with an embodiment of the present disclosure;

FIG. 4C is a network environment of a second exemplary system for detection of intensity modulated optical signal, in accordance with another embodiment of the present disclosure;

FIGs. 5 A and 5B are graphical representations that illustrate comparative results of measurements for different target bit error rates (BERs) in an exemplary system for detection of intensity modulated optical signal, in accordance with an embodiment of the present disclosure;

FIGs. 5C and 5D are graphical representations that illustrate comparative results of measurements for BERs versus received optical power (RoP) for B2B and 20 km transmission for different detection techniques, in accordance with an embodiment of the present disclosure.

In the accompanying drawings, an underlined number is employed to represent an item over which the underlined number is positioned or an item to which the underlined number is adjacent. A non-underlined number relates to an item identified by a line linking the nonunderlined number to the item. When a number is non-underlined and accompanied by an associated arrow, the non-underlined number is used to identify a general item at which the arrow is pointing.

DETAILED DESCRIPTION OF EMBODIMENTS

The following detailed description illustrates embodiments of the present disclosure and ways in which they can be implemented. Although some modes of carrying out the present disclosure have been disclosed, those skilled in the art would recognize that other embodiments for carrying out or practicing the present disclosure are also possible. FIG. 1 is a flowchart of a method 100 for detecting an intensity modulated optical signal by a receiving device, in accordance with an embodiment of the present disclosure. The method 100 is executed at a receiving device described, e.g., in FIGs. 2A, 2C, 4A, 4B and 4C. The method 100 includes steps 102, 104, 106, 108, 110, 112 and 114

At step 102, the method 100 comprises receiving an input optical signal by a processor. The received input optical signal is detected by the processor at the receiving device. The optical signal is transmitted by a remotely located transmitting device. In an example, data (in form of optical signals) is potentially communicated between two remotely located points (e.g. data centres), e.g. the transmitting device and the receiving device in a metropolitan area network, via an optical link.

In accordance with an embodiment, the receiving includes receiving the input optical signal using a photodiode that is limited in bandwidth at an optical frontend of the receiving device. The photodiode converts the optical field in the input optical signal to current. In accordance with an additional embodiment, the receiving includes receiving applying an electrical filter to the input optical signal. The electrical filter has a cut-off frequency and outputs a filtered signal that corresponds to the electrical signal received from the photodiode.

It may be noted that the receiving device, as per the method 100, corresponds to a low bandwidth optical receiving device. Such low-bandwidth optical receiving device is low in cost, and can operate at a much lower level of optical input power than a high-speed receiving device, since the noise power decreases along with the optical receiving device bandwidth.

The input optical signal includes a string of symbols that may be one of a binary string or an amplitude-modulated string with a plurality of levels. For example, the input optical signal may have a multilevel amplitude modulated format in which, within a given clock cycle of the optical signal, multiple bits are represented by a given signal level, e.g. x[n].

At step 104, the method 100 further comprises performing a first multilevel detection at M levels on the input optical signal, where M>1. In accordance with an embodiment, M represents a digit that corresponds to the number of conditions, levels, or combinations possible for a given number of binary variables. For example, a digital optical signal with four possible conditions (voltage levels, frequencies, phases, and so on) is an M-ary system where M = 4. If there are eight possible conditions, M = 8 and so forth. The number of bits necessary to produce a given number of conditions may be expressed mathematically as 2“=M, where n = number of bits necessary, M = number of conditions, levels, or combinations possible with n bits. For example, with one bit, only 2¹ = 2 conditions are possible. With two bits, 2² = 4 conditions are possible, with three bits, 2³ = 8 conditions are possible, and so on. In an illustrative embodiment, as described in FIG. 3 A, a two-level signal is detected within a given clock cycle of an input optical signal at a high bandwidth optical frontend.

In accordance with an embodiment, the processor in the receiving device may comprise a middle level slicer that provides a threshold value, e.g. “ThO”. With respect to the threshold value, e.g. “ThO”, the two levels (or states) of the input optical signal is detected, as illustrated in FIG. 3C. Further, an example of a sampling instant, enclosed between two vertical dashed lines, is also illustrated in FIG. 3C. In an example, for a given input optical signal x[n], the detected two-level may be represented as y2[n]={0,l}. It may be noted that FIG. 3C shows example of a preferred sampling instant that corresponds to two samples per bit, however, a single sampling instant for such detections may also be employed, i.e. corresponding to 1 sample per bit.

At step 106, the method 100 further comprises performing, by the processor, a second multilevel detection at N levels on the input optical signal, where N>M. It may be noted that the method 100 performs step 106 in concurrence with step 104. Alternatively said, the method 100 detects the M level and the N level signal simultaneously, wherein the second one may be approximately half bit displaced from the decision time of the first one. In accordance with an embodiment, N represents a digit that corresponds to the number of conditions, levels, or combinations possible for a given number of binary variables, based on the first multilevel detection at M levels. Mathematically, the second multilevel detection at N levels may be represented as 2M-1 levels. For example, a digital optical signal with two possible conditions (voltage levels, frequencies, phases, and so on) is an M-ary system where M = 2. Accordingly, second multilevel detection may be determined to be as (2*2)-l levels, i.e. 3 levels.

As illustrated in FIG. 3B, a three-level signal is detected within a given clock cycle of an input optical signal at a low bandwidth optical frontend. However, it is to be appreciated that the use of two and three levels in the illustrative embodiment is by way of example only, and more levels can be used such that a given level represents more than two bits within a given cycle of the signal. The number of levels to detect may grow as (p*n-l), where p is the initial modulation order (e.g. p=2 for NRZ, and 4 for PAM4), and n starts from 1 for full bandwidth. It may be noted that the value of n may be limited to 2 for better performance, however such limitation depends on the bandwidth of the receiving device, without deviation from the scope of the disclosure. In accordance with an embodiment, the processor in the receiving device may comprise two level slicers, such as an upper slicer and a lower slicer, that provides two threshold values, e.g. “Th1” and “Th2” respectively. With respect to the two threshold values, e.g. “Th1” and “Th2”, three levels (or states) of the input optical signal is determined, as illustrated in FIG.3D. Further, an example of a sampling instant, enclosed between two vertical dashed lines, is also illustrated in FIG.3D. For a given input optical signal x[n], the detected three-level may be represented as ^̂[n]= ^^[n]+ ^^[n-1], as the three-level is an addition of consecutive two-level detected signal. In accordance with an embodiment, the second multilevel detection, which is performed at N levels, may include applying a low-pass filter configured to separate the N levels. At step 108, the method 100 further comprises transforming, by the processor, the detected M level signal into an expected N level signal. In accordance with an embodiment, the detected two-level signal may be transformed into an expected three-level signal. The detected two-level signal is transformed into a three-level signal by a delay and addition (1+D) using one-bit delay coding technique. Accordingly, for a given received optical signal x[n], if the two-level signal is detected as

then the expected three-level signal may be represented as

. The detected two-level signal is transformed into the three-level signal by a delay and addition (1+D). For example, for a given input optical signal x[n]= 110001110011, if the two-level is detected as

, then the expected three-level is ^_^[n]= 121001111012. The one bit, i.e. “0”, as underlined, indicates one error bit in

and as a result of the delay and addition operation, two consecutive error bits, i.e. “11”, are produced in the expected three-level is

[ ], as underlined. In another embodiment, for the given input optical signal x[n]= 110001110011, if the two-level signal is detected as

[ ] , then the expected three-level signal is

121001100012, whereas the detected three-level signal is ^_^[n]=121001221012. It may be observed that two consecutive errors in the two-level detected signal

are both “0” bits, as underlined. The two consecutive errors in the detected two-level signal, i.e. 110001000011, causes three consecutive errors when transformed into the three-level signal, i.e. 121001100012. In yet another embodiment, for the given input optical signal

[ ] , if the two- level signal is detected as

then the expected three-level signal is

whereas the detected three-level signal is

. It may be observed that two consecutive errors in the two-level detected signal are different, i.e. “1” and “0”. The two errors in the two-level detected signal, i.e. 110010110011, causes two non- consecutive errors when transformed into the three-level signal, i.e. 121011121012, as underlined. In accordance with such embodiment, the method 100 further comprises transformation of the expected N level signal, e.g. the expected three-level signal , and the detected N level signal, e.g. the detected three-level signal

121001221012, based on a two symbol delay. At step 110, the method 100 further comprises comparing, by the processor, the expected N level signal and the detected N level signal. In accordance with an embodiment, the expected three-level signal,

], as determined at step 108, is compared with the detected three- level signal i.e ^ [ ], as detected at step 106. The processor may provide a bit sequence of “0”

and “1” bits as a result of comparison, wherein the “1” bits correspond to error bits in the expected three-level signal, i.e with respect to the detected three-level signal i.e.

At step 112, the method 100 further comprises detecting, by the processor, an error in the detected M level signal based on the comparison of the expected N level signal and the detected N level signal. In accordance with an embodiment, the detecting a disagreement between the expected N level signal and the detected N level signal for two consecutive symbols. As indicated in step 110, the “ones” correspond to error bits in the expected three-level signal, i.e. ^_^[n] with respect to the detected three-level signal i.e. based on the comparison. The

number of “1” bits in the bit sequence corresponds to the number of error bits in the expected three-level signal,

which in turn indicates the number of error bits in the detected two-level signal,

At step 114, the method 100 further comprises correcting, by the processor, the detected M level signal based on the detected error. In accordance with an embodiment, as described in step 110, a single error detected in the two-level detected signal causes two errors in the three- level expected signal since the error bit is counted in the current and the next (i.e. the previous) decided bit. As a result, if the following condition

is satisfied, then y[n-1] is the detected error. Such detected error may be corrected based

on negation of the bit value. Referring to the above example for

conditio

is satisfied, then

is the error bit. Accordingly, the bit “0” in ^_^[n] = 110001010011, as underlined, is negated, i.e. converted to “1”. Thus, the error is corrected. In another embodiment, as described in step 110, there may be a case when two consecutive errors detected in the two-level detected signal causes further errors in the three-level expected signal based on the bit memory. As a result, when the following condition

y y

[ ] y[ ] y[ ] [ ] [ ] is satisfied, then y[n-1] is the detected error. Such detected error may be corrected based on negation of the bit value. Again referring to the above example, the condition

[ ] [ ] [ ] [ ] [ ] [ ] [ ] [ ] is satisfied, then is the error bit. Accordingly, the bits “ , as underlined,

is negated, i.e. converted to “11”. Thus, the error is corrected. In accordance with an embodiment, the method 100 further comprises applying, by the processor, a technique to compensate for the low bandwidth to detect the M levels. The technique takes into consideration the correlation between consecutive bits. By sampling at a different point(s) than the middle of the eye-diagram and using different thresholds or slicers, the current bit, as well as the sum of the current and previous bit(s), is determined. Thereafter, by decoding the relationship between the detected levels, errors appearing in the current bit (due to eye closure caused by the receiving device limited bandwidth or n-bit delay channel) is corrected. To detect the M levels, a simple electrical filter (or equalizer) may be added as the technique. To separate the N levels for making the N-levels more pronounced, another electrical filter (or equalizer) may be added. The steps 102, 104, 106, 108, 110, 112, and 114 are only illustrative and other alternatives can also be provided where one or more steps are added, one or more steps are removed, or one or more steps are provided in a different sequence without departing from the scope of the claims herein. FIG.2A is a network environment of a system 200 with a transmitting device and a receiving device, in accordance with an embodiment of the present disclosure. With reference to FIG.2A, there is shown a network environment of the system 200 that includes a transmitting device 202 and a receiving device 204. There is further shown an optical link 206 between the transmitting device 202 and the receiving device 204. The receiving device 204 is communicatively coupled to the transmitting device 202 via the optical link 206. The transmitting device 202 includes suitable logic, circuitry, interfaces and/or code that is configured to transmit information in the form of an optical signal to the receiving device 204 via the optical link 206. Examples of the transmitting device 202 include, but is not limited to an optical transmitter, a transceiver, or a fibre optic transmitter.

The receiving device 204 includes suitable logic, circuitry, interfaces and/or code that is configured to receive the optical signal (as the input optical signal) via the optical link 206 and convert the optical signal into the electric signal. Examples of the receiving device 204 include, but is not limited to an optical receiver, a transceiver, or a fibre optic receiver.

The optical link 206 is a communication link that comprises a single end-to-end optical circuit, which provides a data connection medium between two points. Examples of the optical link 206 include, but is not limited to an optical fibre (such as multimode optical fibre, a single mode optical fibre, or a plastic optical fibre), or an active optical cable (AOC), or a full duplex optical link.

In operation, the transmitting device 202 is configured to transmit input data in the form of an optical signal to the receiving device 204, via the optical link 206. Typically, the input data in a digital domain (represents an electrical signal) is converted to an analogue signal (e.g. using a digital-to-analogue converter), and modulated (e.g. into a carrier wave) to be propagated as an intensity modulated signal via the optical link 206. The system 200 including the transmitting device 202 and the receiving device 204 is suited to use any kind of modulation (e.g. WDM, O- OFDM, SDM, and the like).

In accordance with an embodiment, the receiving device 204 is configured to receive the input optical signal, e.g. the intensity modulated signal, via the optical link 206. The receiving device 204 receives such intensity modulated signal at a low bandwidth frontend, and detects various levels simultaneously by use of different threshold values. The receiving device 204 may further determine the current bit and the sum of the current and previous bit of the intensity modulated signal based on sampling performed at a different point(s) than the middle of the eye-diagram of the intensity modulated signal. Afterwards, electronic signal processing performed by one or more processors of the receiving device 204 may combine the detected intensity modulated signal to eliminate correlation between the consecutive bits. The one or more processors combine the detected intensity modulated signal using a conventional two-level signal (based on one threshold value as exemplified in FIG. 3C) and a three-level signal (based on two threshold values as exemplified in FIG. 3D). For example, if is the current detected two-

level signal, and

is the current detected three-level signal, the mathematical relationship between y[n] and , in accordance with the following equation, is:

Therefore, the one or more processors detect the errors by adding the current decided bit with the previous bit and compare with the value obtained from the three-level signal. As one error in the two-level signal may induce two errors in the three-level signal since the bit is counted in the current and the previous decided bit, the one or more processors detect and correct a single error, based on the condition satisfied by the following equations:

Once detected, the single error may be corrected by the one or more processors by negating the bit value of y[n-l].

In another embodiment, the one or more processors may further detect and correct two consecutive errors, that would depend on the memory that is to be used. In such embodiment, the one or more processors detect and correct two errors, based on the condition satisfied by the following equations:

Once detected, the two errors may be corrected by the one or more processors by negating the bit value of y[n-l].

In yet another embodiment, the one or more processors may further detect and correct “m” consecutive errors, that would depend on the memory that is to be used. In such embodiment, the one or more processors detect and correct “m” errors, based on the condition satisfied by the following equations:

Once detected, the m errors may be corrected by the one or more processors by negating the bit value of y[n-l].

In such manner, the electronic signal processing performed by the one or more processors of the receiving device 204 may decoding the relationship between the various detected levels to correct errors that appear in the current bit (due to eye closure caused by the limited bandwidth of the receiving device 204 or n-bit delay channel).

FIG. 2B is a first block diagram that illustrates various exemplary components of a receiving device, in accordance with an embodiment of the present disclosure. FIG. 2B is described in conjunction with elements from FIG. 2A. With reference to FIG. 2B, there is shown the transmitting device 202 that includes an optical light source (hereinafter, simply referred to as a light source 208), a pseudorandom binary sequence (PRBS) generator 210, a precoder 212, and a modulation circuit 214, and a control circuitry 216.

The light source 208 may correspond to a continuous wave light signal incoming from a laser source in the transmitting device 202.

The PRBS generator 210 may include suitable logic, circuitry, interfaces and/or code that is configured to generate a serial sequence of a binary test pattern corresponding to an NRZ electrical signal. The binary test pattern may be clocked by a clock signal having a specified base frequency. The size of the serial sequence of the binary test pattern may be indicated by a notation 2^k-l, where k indicates the size of the unique word of data in the serial sequence. In an exemplary embodiment, the PRBS generator 210 may generate 2¹⁵-1 bits in a sequence, having a bitrate of 50Gbps. However, this exemplary embodiment should not be construed to be limiting and other configurations may also be possible without any deviation from the scope of the disclosure.

The precoder 212 may include suitable logic, circuitry, interfaces and/or code that is configured to encode the NRZ electrical signal. The precoder 212 may be a conventional precoder that has a structure including an exclusive OR (XOR) gate and a time delay unit for delaying an output signal of the XOR gate by one data bit. However, it may be noted that the implementation of the precoder 212 is optional and thus, it may be omitted from the transmitting device 202 without any deviation from the scope of the disclosure. The modulation circuit 214 may include suitable logic, circuitry, interfaces and/or code that is configured to modulate the light intensity of the carrier outputted from a laser source (not shown). The NRZ electrical signal generated by the PRBS generator 210 may be optionally amplified by a pair of modulator-driving amplifiers and outputted as driving signals for the modulation circuit 214. According to the modulator driving signals inputted to modulation terminals of the modulation circuit 214, the modulation circuit 214 modulates the light intensity of the carrier outputted from the light source 208 and output the modulated signal (as intensity modulated optical signal) for transmission to the receiving device 204 via the optical link 206.

The control circuitry 216 is configured to transmit a signal to the receiving device 204, via the optical link 206. In an implementation, the control circuitry 216 may be a general-purpose processor. Examples of the control circuitry 216 include, but is not limited to a microprocessor, a microcontroller, a complex instruction set computing (CISC) processor, an applicationspecific integrated circuit (ASIC) processor, a reduced instruction set (RISC) processor, a very long instruction word (VLIW) processor, a central processing unit (CPU), a state machine, a data processing unit, and other processors or circuits. Moreover, the control circuitry 216 may refer to one or more individual processors, processing devices, a processing unit that is part of a machine. It will be appreciated that the operations performed at the transmitting device 202 is potentially performed by the control circuitry 216 of the transmitting device 202.

FIG. 2C is a second block diagram that illustrates various exemplary components of a receiving device, in accordance with an embodiment of the present disclosure. FIG. 2C is described in conjunction with elements from FIG. 2A. With reference to FIG. 2C, there is shown the receiving device 204 that includes a photodiode (PD) 218, a transimpedance amplifier (TIA) 220, an electrical filter 222, and a processor 224.

The PD 218 is a highly sensitive semiconductor photodiode that may be configured to receive the intensity modulated optical signal from the transmitting device 202 via the optical link 206. The PD 218 exploits the photoelectric effect of the intensity modulated optical signal and converts into electrical signals. In accordance with an embodiment, the PD 218 may be an avalanche photodiode (APD) that may amplify carriers by the avalanche breakdown mechanism. Examples of the PD 218 include, but is not limited to laser rangefinders, long range fibre optic telecommunication, and quantum sensing for control algorithms. The TIA 220 is a type of current-to-voltage converter that is configured to amplify the current output of the photodetectors, such as the PD 218, to a usable voltage. The configuration of the TIA 220, e.g. gain, bandwidth, input offset current, and input offset voltage of the TIA 220, may be based on the type of the PD 218 implemented in the receiving device 204.

The electrical filter 222 passes the electrical signal components below a cut-off frequency attributed thereof and may cut the other signal components over the cut-off frequency. The electrical filter 222 may be one of an analogue or a digital filter. An example of the electrical filter 222 may be a type of the Bessel-Thomson filter, and the like.

The processor 224 is configured to receive the optical signal transmitted by the transmitting device 202, via the optical link 206. In an implementation, the processor 224 may be a general- purpose processor. Examples of the processor 224 include, but is not limited to a microprocessor, a microcontroller, a complex instruction set computing (CISC) processor, an application-specific integrated circuit (ASIC) processor, a reduced instruction set (RISC) processor, a very long instruction word (VLIW) processor, a central processing unit (CPU), a state machine, a data processing unit, and other processors or circuits. Moreover, the processor 224 may refer to one or more individual processors, processing devices, a processing unit that is part of a machine, as further described in FIG. 4A. It will be appreciated that the operations performed at the receiving device 204 is potentially performed by the processor 224 of the receiving device 204.

FIG. 3A is an illustration of a first eye diagram of an NRZ signal at a high bandwidth optical frontend, in accordance with an embodiment of the present disclosure. Referring to FIG. 3A, there is shown a first eye diagram 300A for an NRZ electrical signal at a high bandwidth optical frontend, such as 0.75*Bitrate. In the first eye diagram 300A, as the high bandwidth optical frontend has enough bandwidth, the eye amplitude, marked by solid double-sided arrow is significant.

FIG. 3B is an illustration of a second eye diagram of an NRZ signal at a low bandwidth optical frontend, in accordance with an embodiment of the present disclosure. Referring to FIG. 3B, there is shown a second eye diagram 300B of an NRZ electrical signal at a low bandwidth optical frontend, such as 0.25*Bitrate, the eye amplitude reduces (marked by solid double-sided arrow) whereas the crossing point and the area above (marked by dashed double-sided arrow) increases.

FIG. 3 C is an illustration of a sampling instant and one threshold value provided by a middle level slicer, in accordance with an embodiment of the present disclosure. Referring to FIG. 3C, there is shown a third eye diagram 300C for an NRZ electrical signal, which indicates two levels (or states), such that a single bit of value 0 or 1, represented within a given clock cycle of the signal. Thus, a two-level signal, obtained based on a threshold value, e.g. “ThO” provided by a middle level slicer, is observed within a given clock cycle of an input optical signal at a high bandwidth optical frontend. It may be noted that the sampling instant, as illustrated in FIG. 3C, corresponds to 2 samples per bit, however, a single sampling instant for two-level detection may also be employed corresponding to 1 sample per bit, without deviation from the scope of the disclosure.

FIG. 3D is an illustration of a sampling instant and two threshold values provided by upper and lower level slicers, in accordance with an embodiment of the present disclosure. Referring to FIG. 3D, there is shown a fourth eye diagram 300D for an NRZ electrical signal, which indicates three levels (or states), such that a single bit of value 0, 1, and 2, represented within a given clock cycle of the signal. Thus, a three-level signal, obtained based on two threshold values, e.g. “Thl” and “Th2”, provided by the upper and lower level slicers, is observed within a given clock cycle of an input optical signal at a low bandwidth optical frontend. It may be noted that the sampling instant, as illustrated in FIG. 3D, corresponds to 2 samples per bit, however, a single sampling instant for three-level detection may also be employed corresponding to 1 sample per bit, without deviation from the scope of the disclosure.

FIG. 4A is a network environment of a first exemplary system for detection of intensity modulated optical signal, in accordance with an embodiment of the present disclosure. FIG. 4B is a detailed diagram of various components in the processor 224, in accordance with an embodiment of the present disclosure. FIG. 4A is described in conjunction with elements from FIG. 1, FIG. 2C, and FIG. 4B. With reference to FIG. 4A, there is shown the processor 224 in the receiving device 204 that includes a middle level slicer 402, a first bit delay unit 404, a first computation block 406, a second bit delay unit 408, an upper level slicer 410, a lower level slicer 412, a second computation block 414, a third bit delay unit 416, a third computation block 418, a comparator block 420, an error detection block 422, an error correction block 424, and a decoder 426. In operation, at the transmitting device 202, the PRBS generator 210 generates a serial sequence of a binary test pattern corresponding to an NRZ electrical signal, as described above. In an exemplary embodiment, the PRBS generator 210 may generate 2¹⁵-1 bits in a sequence, having a bitrate of 50Gbps. However, this exemplary embodiment should not be construed to be limiting and other configurations may also be possible without any deviation from the scope of the disclosure. The precoder 212 encodes the NRZ electrical signal and communicates the encoded NRZ electrical signal to the modulation circuit 214. In accordance with an embodiment, the modulation circuit 214 modulates the light intensity of the carrier outputted from the light source 208 based on the input received from the precoder 212. In accordance with another embodiment, the modulation circuit 214 modulates the light intensity of the carrier outputted from the light source 208 based on the input received from the PRBS generator 210 in absence of the precoder 212 in the transmitting device 202. The control circuitry 216 transmits the intensity modulated optical signal, as e.g. x[n], to the receiving device 204, via the optical link 206. In an implementation, the control circuitry 216 may be a general-purpose processor.

At the receiving device 204, the intensity modulated optical signal, e.g. x[n], is received and processed by an optical frontend, i.e. the PD 218 and the TIA 220, of the receiving device 204. In accordance with an embodiment of the present disclosure, the optical frontend of the receiving device 204 may have a low bandwidth, e.g. 0.25*Bitrate, due to which the received intensity modulated optical signal, e.g. x[n], exhibits multi-level signals, as illustrated in FIG. 3B. The PD 218, e.g. an APD, exploits the photoelectric effect of the intensity modulated optical signal, e.g. x[n], and converts into corresponding electrical signals. Based on amplification of carriers by the avalanche breakdown mechanism. Thereafter, the TIA 220 amplifies the current output of the PD 218 to an amplified voltage signal, which is further communicated to the middle level slicer 402 for two-level detection and the other two slicers, i.e. upper level slicer 410, a lower level slicer 412, for three-level detection.

The middle level slicer 402 provides a threshold value, e.g. “ThO”, based on which the two levels (or states) of the intensity modulated optical signal, hereinafter input optical signal e.g. x[n], is detected. As illustrated in FIG. 3C, the middle level slicer 402 detects the two levels (or states) of the input optical signal based on detection of the eye and crossing point in the eye diagram of the voltage signal that corresponds to the input optical signal. More specifically, the middle level slicer 402 detects a binary signal in eye-opening in the eye diagram of the voltage signal to detect the two levels (or states) of the input optical signal, which is hereinafter referred to as a two-level signal,

In accordance with an embodiment, the first bit delay unit 404 provides one-symbol delay (or one-bit delay) to the two-level signal, when the two-level signal has a single error to

be corrected. Thereafter, the first computation block 406 transforms the detected two-level signal,

, into an expected three-level signal, , The expected three-level signal,

is generated at the first computation block 406 based on addition of the delayed two-

level signal (by one symbol), , generated by the first bit delay unit 404, and the two-

level signal, , detected by the middle level slicer 402. In one embodiment, a XOR gate

may be implemented as an adder to realize the first computation block 406, as illustrated as a first modified block 406A of the first computation block 406 in FIG. 4B.

In accordance with another embodiment, the first bit delay unit 404 provides two-symbol delay (or two-bit delay) to the two-level signal,

when the two-level signal has two consecutive errors to be corrected. Thereafter, the first computation block 406 transforms the detected two-level signal,

, into an expected three-level signal,

The expected three-level signal, is generated at the first computation block 406 based

on subtraction of the delayed two-level signal (by two symbols), generated by the

first bit delay unit 404, and the two-level signal, detected by the middle level slicer

402, based on the following relation: .

In one embodiment, a XOR gate may be implemented as a subtractor to realize the first computation block 406, as illustrated as a second modified block 406B of the first computation block 406 in FIG. 4B.

Simultaneously, the other two slicers, such as the upper level slicer 410 and the lower level slicer 412, provide two threshold values, e.g. “Thl” and “Th2” respectively, based on which three levels (or states) of the input optical signal, e.g. x[n], is detected. As illustrated in FIG. 3D, the upper level slicer 410 and the lower level slicer 412 collectively detect the three levels (or states) of the input optical signal based on detection of the eye and crossing point in the eye diagram of the voltage signal that corresponds to the input optical signal. More specifically, the upper level slicer 410 detects an upper binary signal and the lower level slicer 412 detects a lower binary signal in eye-crossing in the eye diagram of the voltage signal. Based on the addition of the detected upper and lower binary signal by a XOR gate implemented in the second computation block 414 to detect the three levels (or states) of the input optical signal, hereinafter referred to as a three-level signal

, In accordance with an embodiment, the three-level signal,

may be around half bit displaced from the decision time of the two-level signal,

It may be noted that in general, a detected two-level signal and a three-level signal are related to each other based on the following relation as the detected three-level signal is an addition of consecutive two-level signals:

It may be appreciated that more than three-level detection may also be performed based on following relation:

relation may be simplified as:

In accordance with an embodiment, an optional set of computation units, e.g. the third bit delay unit 416 and the third computation block 418 enclosed in a dashed box in FIG. 4A, may be implemented when the two-level signal has two errors to be corrected. In such embodiment, the third bit delay unit 416 provides one-symbol delay (or one-bit delay) to the three-level signal,

Thereafter, the third computation block 418 transforms the detected three-level signal, e.g. z^[n], into a transformed three-level signal, based on the following

relation:

The transformed three-level signal is generated at the third computation block 418

based on the subtraction of the delayed three-level signal (by one symbol), and the

detected three-level signal, i.e. z^ [n]. In one embodiment, a XOR gate may be implemented as a subtractor to realize the third computation block 418. In accordance with an embodiment, when the two-level signal has a single error to be corrected, the comparator block 420 may be configured to compare the expected three-level signal, e.g. (generated by the first modified block 406A of the first computation block 406), and the

detected three-level signal, (generated by the second computation block 414). The

following relation must be satisfied at the comparator block 420 to determine a single error in the two-level signal,

In accordance with another embodiment, when the two-level signal has more than one errors, such as two errors, to be corrected, the comparator block 420 may be configured to compare the expected three-level signal,

(generated by the second modified block 406B of the first computation block 406), and the detected three-level signal, (generated by

the third computation block 418). The following relation must be satisfied at the comparator block 420 to determine a single error in the two-level signal,

In accordance with an embodiment, a XOR gate may be implemented as a comparator to realize the comparator block 420, as illustrated in FIG. 4B. Accordingly, the output of the comparator block 420 may correspond to a series of “0” and “1”. It may be noted that consecutive two “1” bits correspond to two consecutive error bits in the expected three-level signal,

or which in turn corresponds to a single error in the detected two-level signal,

Thereafter, the output of the comparator block 420 is communicated to the error detection block 422. The error detection block 422 may be realized based on an AND gate and a bit delay unit, as illustrated in FIG. 4B. More specifically, the output of the comparator block 420 is communicated directly to the first terminal of the AND gate. Further, the output of the comparator block 420 is communicated to the bit delay unit which is further connected to the second terminal of the AND gate. Accordingly, the error detection block 422 searches for and locates two consecutive errors in the output of the comparator block 420.

Based on the consecutive errors searched and located by the error detection block 422, the error correction block 424 may be configured to correct such consecutive errors. In general, the logic gate of the error correction block 424 is an XOR gate having as inputs the detected two-level signal with the proper delay (accounting for the processing time of the decoder 426). The output of the error detection 422 indicates if the detected bit needs to be corrected or not, i.e. a "1" changes the detected bit, and a "0" leaves it). More specifically, in accordance with an embodiment, the output of the error detection block 422 indicates an error bit in the y[n-l] signal, i.e. the two-level signal, ]. The error correction block 424 may be configured

to apply a technique to compensate for the low bandwidth to detect the M levels. According to the technique, the error correction block 424 determines a corrected y[n-l] signal, i.e. the two- level signal, based on the delayed input signal received from the second bit delay

unit 408 (that represents y[n-l], i.e. the two-level signal, e.g. y^ [n-1], with error bit) and the input signal received from the error detection block 422 (that represents error bits in the three- level signal, The error correction block 424 determines the corrected signal,

by use of a XOR gate that basically negates the error bit in the delayed input signal

received from the second bit delay unit 408. Once the corrected y[n-l] signal, is

determined by the error correction block 424, the decoder 426 in the receiving device 204 may be configured to decode the relationship between the various signals at detected levels, i.e. y[n], and correct the errors appearing in the current two-level

signal, (due to eye closure caused by the receiver limited bandwidth or n-bit delay

channel).

In accordance with an embodiment, when the given input optical signal, is not pe-

coded, the error detection block 422 may be configured to determine consecutive errors in the signal received from the comparator block 420. Based on the determined consecutive errors, the error correction block 424 may be configured to correct the three-level signal,

Once the corrected three-level signal, s determined by the error correction block 424,

the decoder 426 in the receiving device 204 may be configured to decode the relationship between the various signals at detected levels, and correct the errors

appearing in the current two-level signal, (due to eye closure caused by the receiver

limited bandwidth or n-bit delay channel).

FIG. 4C is a network environment of a second exemplary system for detection of intensity modulated optical signal, in accordance with another embodiment of the present disclosure. FIG. 4C is described in conjunction with elements from FIG. 1, FIG. 2C, FIG. 4A, and FIG. 4B. With reference to FIG. 4C, there is shown the processor 224 in the receiving device 204 that further includes electrical filters, such as a first electrical filter 428, and a second electrical filter 430 in addition to the middle level slicer 402, the first bit delay unit 404, the first computation block 406, the second bit delay unit 408, the upper level slicer 410, the lower level slicer 412, the second computation block 414, the third bit delay unit 416, the third computation block 418, the comparator block 420, the error detection block 422, the error correction block 424, and the decoder 426, as described in detail in FIG. 4A.

In case an ADC is used, the first electrical filter 428 is connected between the optical frontend of the receiving device 204 and the middle level slicer 402. Examples of the first electrical filter 428 may include, but not limited to, a feed-forward equalizer (FFE) and a continuous time linear equalizer (CTLE). The first electrical filter 428 may be an analogue or a digital filter (or an equalizer). The first electrical filter 428 receives the input optical signal, e.g. x[n], as the amplified voltage signal from the optical frontend and passes optical signals with a frequency lower than a selected cutoff frequency and attenuates signals with frequencies higher than the cutoff frequency. The first electrical filter 428 communicates the filtered optical signal to the middle level slicer 402 for further processing.

Similarly, the second electrical filter 430 is connected between the optical frontend of the receiving device 204 and the other two slicers, i.e. upper level slicer 410, a lower level slicer 412. The second electrical filter 430 receives the input optical signal, e.g. x[n], as the amplified voltage signal from the optical frontend and makes the N-levels more pronounced. Examples of the second electrical filter 430 may include, but not limited to, an FFE and a low-pass filter. The second electrical filter 430 communicates the filtered optical signal to the other two slicers for further processing. Afterwards, the working of the second exemplary system for detection and correction of intensity modulated optical signal is similar to the first exemplary system, as described in FIG. 4A.

FIGs. 5A and 5B are graphical representations that illustrate comparative results of measurements for different target BERs in an exemplary system for detection of intensity modulated optical signal, in accordance with an embodiment of the present disclosure. FIGs. 5A and 5B are described in conjunction with elements from FIGs. 1 to 4C. With reference to FIG. 5 A, there is shown a graphical representation 500A for a target BER 10'³. Similarly, with reference to FIG. 5B, there is shown another graphical representation 500B for a target BER 10'². In each of the FIGs. 5 A and 5B, an X-axis 502A represents values of bandwidth (BW)/Bitrate in percentage, and a Y-axis 502B represents power penalty in dB. The graphical representation in FIG. 5 A illustrates an increased power to achieve the same SNR or BER performance as that of an ideal system to compensate for the system degradation, i.e. power penalty, versus the bandwidth/bitrate percentage. The penalty is considering the best receiver sensitivity for the three cases (i.e. two-level, three-level, and two and three-level) and for a target BER 10'³. While the best receiver sensitivity is for full-bandwidth receiver, with the combination of two and three-level detection, represented by a third line 508, the penalty can be <1 dB in a range from 0.28*Rb to 0.75*Rb. The lower boundary at 50Gb/s corresponds to 14 GHz BW, for example. As illustrated in FIG. 5 A, the till three-level detection, represented by the first line 504 (for two-level detection) and second line 506 (for three level detection), is at best equal to the combination of two and three-level detection, represented by the third line 508, in all the bandwidth considered. However, FIG. 5A further illustrates that the performance with greater than three levels, for example five-level detection represented by the fourth line 510 and the combination of three and five-level detection, represented by the fifth line 512, is lower because the eye-diagrams are smaller. However, there may be an improvement for BW<0.2*Rb limiting the penalty to around 5dB. For example, in the case of the combination of two and three-level detection and the combination of three and five-level detection, the penalty is between the three-level and five-level receiver. Similar trend may be observed in the other graphical representation 500B of FIG. 5B with the target BER 10'².

FIGs. 5C and 5D are graphical representations that illustrate comparative results of measurements for BERs versus received optical power (RoP) for B2B and 20 km transmission for different detection techniques, in accordance with an embodiment of the present disclosure. The detection techniques may correspond to BER with finite impulse response (FIR) and the combination of two-level and three-level detection. With reference to FIG. 5C, there is shown a graphical representation 500C for a B2B transmission. Similarly, with reference to FIG. 5D, there is shown another graphical representation 500D for 20 km transmission. In each of the FIGs. 5C and 5D, an X-axis 520 A represents RoP in dBm, and a Y-axis 520B represents BER. As illustrated in FIG. 5C, for the B2B transmission, the BER for the combination of two and three-level detection, represented by the sixth line 522, is lower than the BERwFIR detection technique, represented by the seventh line 524. Similarly, as illustrated in FIG. 5D, for the 20 km transmission, the BER for the combination of two and three-level detection, represented by the sixth line 522, is lower than the BERwFIR detection technique, represented by the seventh line 524. Modifications to embodiments of the present disclosure described in the foregoing are possible without departing from the scope of the present disclosure as defined by the accompanying claims. Expressions such as "including", "comprising", "incorporating", "have", "is" used to describe and claim the present disclosure are intended to be construed in a non-exclusive manner, namely allowing for items, components or elements not explicitly described also to be present. Reference to the singular is also to be construed to relate to the plural. The word "exemplary" is used herein to mean "serving as an example, instance or illustration". Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments and/or to exclude the incorporation of features from other embodiments. The word "optionally" is used herein to mean "is provided in some embodiments and not provided in other embodiments". It is appreciated that certain features of the present disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable combination or as suitable in any other described embodiment of the disclosure.

Claims

1. A computer-implemented method (100) for detecting an intensity modulated optical signal, comprising: receiving, by a processor (224), an input optical signal; performing, by the processor (224), a first multilevel detection at M levels on the input signal, where M>1; performing, by the processor (224), a second multilevel detection at N levels on the input signal, where N>M; transforming, by the processor (224), the detected M level signal into an expected N level signal; detecting, by the processor (224), an error in the detected M level signal based on a comparison of the expected N level signal and the detected N level signal; and correcting, by the processor (224), the detected M level signal based on the detected error.

2. The method (100) of claim 1, wherein the input optical signal includes a string of symbols.

3. The method (100) of claim 2, wherein the string of symbols is a binary string or an amplitude-modulated string with a plurality of levels.

4. The method (100) of claim 2 or claim 3, wherein transforming includes generating a sum of a current symbol and an immediately preceding symbol.

5. The method (100) of any one of claims 2 to 4, wherein detecting the error in the detected M level signal includes detecting a disagreement between the expected N level signal and the detected N level signal for two consecutive symbols.

6. The method (100) of claim 4 or claim 5, wherein the comparison of the expected N level signal and the detected N level signal includes a further transformation of the expected N level signal and the detected N level signal, based on a two-symbol delay.

7. The method (100) of any preceding claim, wherein N = 2M-1.

8. The method (100) of any preceding claim, wherein M = 2.

9. The method (100) of any preceding claim, wherein receiving includes receiving the input optical signal using a photodiode (218), wherein the photodiode (218) is limited in bandwidth.

10. The method (100) of any preceding claim, wherein receiving further incudes applying an electrical filter (222) to the input optical signal.

11. The method (100) of any preceding claim, wherein performing the second multilevel detection includes applying a low-pass filter (430) configured to separate the N levels.

12. The method (100) of any preceding claim, further including applying a technique to compensate for the low bandwidth to detect the M levels.

13. A receiving device (204) comprising a processor (224) configured to implement the method (100) of any preceding claim.

14. A computer-readable medium configured to store instructions which, when executed by a processor (224), cause the processor (224) to perform the method (100) of any preceding claim.