WO2022095685A1 - Persistent memory key value system and operation method therefor - Google Patents

Abstract

Provided are a persistent memory key value system and an operation method therefor. The operation method comprises: searching for an index of a persistent memory key value system, so as to position key value pair metadata to be inserted; acquiring a write lock resource, corresponding to the key value pair metadata, in a dynamic random access memory; allocating a persistent memory to the key value pair metadata, and making the key value pair metadata persist; and atomically inserting the key value pair metadata into the persistent memory key value system. By means of the present invention, during an insertion operation process of a key value pair, no writing of a persistent memory is introduced into the operation of a write lock resource, and no log operation is needed, such that the insertion operation performance is improved, and the expansibility under a multi-core architecture is improved.

Description

Persistent memory key-value system and method of operation

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on the Chinese patent application CN202011218384.6 filed on November 04, 2020 with the title of "Persistent Memory Key-Value System and Its Operation Method", and claims the priority of the patent application, and the disclosure of the invention is hereby incorporated by reference. The contents are fully incorporated into this application.

technical field

Embodiments of the present invention relate to the technical field of persistent memory storage, and in particular, to a persistent memory key-value system and an operation method thereof.

Background technique

Persistent memory has similar performance to dynamic random access memory (DRAM) and supports byte granularity addressing; at the same time, persistent memory, like disk, can store data persistently. For example, existing persistent memory products with sub-microsecond latencies and single-slot capacities of up to 512GB present many opportunities for new memory storage systems. Existing persistent memory supports two modes: application direct mode and memory mode. The application direct access mode abstracts persistent memory into a special storage device that can be directly read and written through load and store instructions. In memory mode, DRAM acts as a cache for persistent memory, providing applications with an abstraction of bulk memory, but without storage capabilities.

Modern servers are mostly multi-core architectures, that is, a processor contains dozens or even hundreds of CPU cores to improve the concurrent performance of the entire system. However, multi-core architecture brings the problem of concurrency control, that is, how efficiently and correctly threads on different CPU cores can concurrently access data.

Existing persistent memory key-value systems are not designed for multi-core architectures, resulting in many problems. First, concurrency primitives (such as read-write locks) that ensure the correct execution of multiple threads cause data to jitter back and forth between caches of different CPU cores, frequently triggering inefficient cache coherency protocols, and seriously affecting CPU performance. Secondly, the write bandwidth of persistent memory is very low, and the single write bandwidth is only about 2.3GB/s, which is about 1/6 of DRAM, and the key-value system uses various consistency mechanisms (such as log files) to ensure crash consistency. ) will consume additional persistent memory write bandwidth; at the same time, read-write locks are usually embedded in data structures, and the cache jitter caused by them will also lead to a large number of persistent memory writebacks. Finally, due to the high read latency and persistence latency of persistent memory, the time of the critical section is stretched, causing conflicting operations between different threads to be severely blocked.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a persistent memory key-value system and an operation method thereof, so as to at least solve the problem in the related art that the existing persistent memory key-value system is not designed for a multi-core architecture, resulting in low operation performance.

According to an embodiment of the present invention, a method for operating a persistent memory key-value system is provided. The method includes: searching an index of the persistent memory key-value system to locate the metadata of the key-value pair to be inserted; obtaining a dynamic random memory Get the write lock resource corresponding to the key-value pair metadata in the storage; allocate persistent memory for the key-value pair metadata, and persist the key-value pair metadata; in the persistent memory key-value system The key-value pair metadata is inserted atomically, wherein the submission process of the key-value pair metadata insertion includes two stages. In the first stage, the persistent flag bit in the key-value pair metadata is cleared. , and call the CPU persistence instruction to flush it from the CPU cache to the persistent memory; in the second stage, set the persistence flag, and notify the read operation that the key-value pair metadata has been successfully persisted.

In an exemplary embodiment, before acquiring the write lock resource corresponding to the key-value pair metadata in the dynamic random access memory, the method further includes: extracting the write lock resource from the index of the persistent memory key-value system Detach and maintain the write lock resource in the dynamic random access memory.

In an exemplary embodiment, the write lock resource is maintained in the dynamic random access memory in a table structure, wherein the input of the table structure is the node address of the index, and the output of the table structure is the corresponding of the write lock resource.

In an exemplary embodiment, prior to atomically inserting the key-value pair metadata in the persistent memory key-value system, further comprising: storing the key-value pair metadata in an atomically modifiable format.

In one exemplary embodiment, the atomically modifiable format means that the key-value pair metadata is packed into a contiguous persistent memory space and supports atomic modification by the CPU.

In an exemplary embodiment, when a conflicting first insert operation and a second insert operation occur at the same time, the first insert operation is not allocated and written to persistent memory, and the first insert operation is returned .

In an exemplary embodiment, the key-value pair metadata includes at least one of the following: a key-value pair fingerprint, a key-value pair address, and a persistent flag; wherein the key-value pair fingerprint is a hash value of a key Several of the bits of the key-value pair address point to the key-value pair in the persistent memory, and the persistence flag bit indicates the persistent state of the metadata of the key-value pair.

In an exemplary embodiment, after atomically inserting the key-value pair metadata into the persistent memory key-value system, further comprising: querying the key-value system lock-free in the persistent memory key-value system Value pair metadata.

In an exemplary embodiment, the lock-free query of the key-value pair metadata includes: checking a persistence flag bit in the key-value pair metadata, and if the persistence flag bit is in a clear state, calling the CPU The persistence instruction persists the metadata of the target key-value pair; the atomic instruction is called to set the persistence flag, and the key-value pair pointed to by the metadata is read.

In an exemplary embodiment, the method further includes: periodically reclaiming persistent memory garbage through a background thread in a time-period-based memory reclamation manner.

According to another embodiment of the present invention, a persistent memory key-value system is provided, the system comprising: a search module configured to search for an index of the persistent memory key-value system to locate the key-value pair metadata to be inserted; obtain A module, configured to obtain the write lock resource corresponding to the metadata of the key-value pair in the dynamic random access memory; an allocation module, configured to allocate persistent memory for the metadata of the key-value pair, and to persist the key-value pair pair metadata; an inserting module, configured to atomically insert the key-value pair metadata in the persistent memory key-value system, wherein the submission process of the key-value pair metadata insertion includes two stages. In the first stage, the persistent flag bit in the metadata of the key-value pair is cleared, and the CPU persistence instruction is called to flush it from the CPU cache to the persistent memory; in the second stage, the persistent flag bit is set , and notify the read operation that the key-value pair metadata has been successfully persisted.

In an exemplary embodiment, the system further includes a maintenance module configured to separate the write lock resource from the index of the persistent memory key-value system and maintain the write lock in the dynamic random access memory Lock resources.

In an exemplary embodiment, the system further includes a storage module configured to store the key-value pair metadata in an atomically modifiable format.

In an exemplary embodiment, the system further includes a query module configured to query the key-value pair metadata in the persistent memory key-value system lock-free.

In an exemplary embodiment, the system further includes: a recycling module, configured as a memory recycling mode based on a time period, and periodically recycling persistent memory garbage through a background thread.

According to yet another embodiment of the present invention, a computer-readable storage medium is also provided, and a computer program is stored in the computer-readable storage medium, wherein the computer program is configured to execute any one of the above methods when running steps in the examples.

According to yet another embodiment of the present invention, there is also provided an electronic device comprising a memory and a processor, wherein the memory stores a computer program, the processor is configured to run the computer program to execute any of the above Steps in Method Examples.

Description of drawings

1 is a flowchart of an operation method of a persistent memory key-value system according to an embodiment of the present invention;

2 is a structural block diagram of a persistent memory key-value system according to an embodiment of the present invention;

3 is a structural block diagram of a persistent memory key-value system according to another embodiment of the present invention;

4 is a schematic diagram of a multi-core architecture-friendly persistent memory key-value system according to an embodiment of the present invention;

5 is a schematic structural diagram of key-value pair metadata according to an embodiment of the present invention;

6 is a flowchart of an insertion operation of a multi-core architecture-friendly persistent memory key-value system according to an embodiment of the present invention;

7 is a flowchart of a query operation of a multi-core architecture-friendly persistent memory key-value system according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of eliminating two concurrent conflict insertion operations according to an embodiment of the present invention.

Detailed ways

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in conjunction with the embodiments.

It should be noted that the terms "first", "second" and the like in the description and claims of the present invention and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence.

Example 1

This embodiment provides a method for operating a persistent memory key-value system. FIG. 1 is a flowchart according to an embodiment of the present invention. As shown in FIG. 1 , the flowchart includes the following steps:

Step S102, look up the index of the persistent memory key-value system to locate the key-value pair metadata to be inserted;

Step S104, obtaining the write lock resource corresponding to the key-value pair metadata in the dynamic random access memory;

Step S106: Allocate persistent memory for the key-value pair metadata, and persist the key-value pair metadata;

Step S108: Atomically insert the key-value pair metadata into the persistent memory key-value system, wherein the submission process of the key-value pair metadata insertion includes two stages. The persistent flag in the metadata of the key-value pair is cleared, and the CPU persistent instruction is called to flush it from the CPU cache to the persistent memory; in the second stage, the persistent flag is set, and the read operation is notified. The key-value pair metadata has been successfully persisted.

Through the above-mentioned embodiments of the present invention, in the process of inserting a key-value pair, the operation of the write lock resource does not introduce any writing to the persistent memory, and no log operation is required, which improves the performance of the insert operation and improves the multi-core Extensibility under architecture.

Before step S104 in this embodiment, the method may further include: separating the write lock resource from the index of the persistent memory key-value system, and maintaining the write lock resource in the dynamic random access memory.

In this embodiment, the write lock resource can be maintained in the dynamic random access memory in a table structure, wherein the input of the table structure is the node address of the index, and the output of the table structure is the corresponding the write lock resource.

Before step S108 in this embodiment, the method may further include: storing the key-value pair metadata in an atomically modifiable format.

In this embodiment, the atomically modifiable format means that the key-value pair metadata is packaged into a continuous persistent memory space and supports atomic modification by the CPU.

In this embodiment, when a conflicting first insert operation and a second insert operation occur simultaneously, the first insert operation is not allocated and written to persistent memory, and the first insert operation is returned.

In this embodiment, the key-value pair metadata includes at least one of the following: a key-value pair fingerprint, a key-value pair address, and a persistent flag; wherein, the key-value pair fingerprint is one of the hash values of the key. Several bits, the address of the key-value pair points to the key-value pair in the persistent memory, and the persistence flag bit indicates the persistent state of the metadata of the key-value pair.

After step S108 of this embodiment, the method may further include: querying the key-value pair metadata in the persistent memory key-value system without lock.

In this embodiment, the lock-free query of the key-value pair metadata may include: checking the persistence flag bit in the key-value pair metadata, and if the persistence flag bit is in a clear state, invoking the CPU persistence The atomization instruction persists the metadata of the target key-value pair; the atomic instruction is called to set the persistence flag, and the key-value pair pointed to by the metadata is read.

In this embodiment, the method may further include: a time period-based memory recycling manner, periodically recycling persistent memory garbage through a background thread.

From the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is better implementation. Based on this understanding, the technical solutions of the present invention can be embodied in the form of software products in essence or the parts that make contributions to the prior art, and the computer software products are stored in a storage medium (such as ROM/RAM, magnetic disk, CD-ROM), including several instructions to make a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present invention.

Example 2

In this embodiment, a persistent memory key-value system is also provided, and the system is used to implement the above-mentioned embodiments and preferred implementations, and what has been described will not be repeated. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, implementations in hardware, or a combination of software and hardware, are also possible and contemplated.

FIG. 2 is a structural block diagram of a persistent memory key-value system according to an embodiment of the present invention. As shown in FIG. 2 , the system includes a search module 10 , an acquisition module 20 , an allocation module 30 and an insertion module 40 .

The search module 10 is configured to search the index of the persistent memory key-value system to locate the metadata of the key-value pair to be inserted.

The acquiring module 20 is configured to acquire the write lock resource corresponding to the metadata of the key-value pair in the dynamic random access memory.

The allocation module 30 is configured to allocate persistent memory for the key-value pair metadata, and persist the key-value pair metadata.

The insertion module 40 is configured to atomically insert the key-value pair metadata in the persistent memory key-value system, wherein the submission process of the key-value pair metadata insertion includes two stages, in the first stage , clear the persistent flag bit in the metadata of the key-value pair, and call the CPU persistent instruction to flush it from the CPU cache to persistent memory; in the second stage, set the persistent flag bit, and notify The read operation of the key-value pair metadata has been successfully persisted.

FIG. 3 is a structural block diagram of a persistent memory key-value system according to another embodiment of the present invention. As shown in FIG. 3 , in addition to all the modules shown in FIG. 2 , the system also includes a maintenance module 50 , a storage module 60 , a Query module 70 and recycling module 80 .

The maintenance module 50 is configured to separate the write lock resource from the index of the persistent memory key-value system, and maintain the write lock resource in the dynamic random access memory.

The storage module 60 is configured to store the key-value pair metadata in an atomically modifiable format.

The query module 70 is configured to query the key-value pair metadata in the persistent memory key-value system without lock.

The recycling module 80 is set to a memory recycling method based on a time period, and periodically recycling persistent memory garbage through a background thread.

It should be noted that the above modules can be implemented by software or hardware, and the latter can be implemented in the following ways, but not limited to this: the above modules are all located in the same processor; or, the above modules can be combined in any combination The forms are located in different processors.

In order to facilitate the understanding of the technical solutions provided by the present invention, the following will describe in detail with reference to embodiments of specific scenarios.

Example 3

FIG. 4 is a schematic diagram of a multi-core architecture friendly persistent memory key-value system according to an embodiment of the present invention. As shown in FIG. 4 , based on the multi-core architecture-friendly persistent memory key-value system of this embodiment, the following insertion and query operations can be performed:

S1, separate the write lock resource from the index of the persistent memory key-value system and maintain it separately in the dynamic random access memory;

S2, store the key-value pair metadata in an atomically modifiable format, and use the atomic instructions of the CPU to atomically switch the system from one consistency state to another when an insertion operation occurs (two-stage atomic insertion);

S3, when two conflicting insert operations occur at the same time, let one of the operations return directly without any allocation and writing of persistent memory (eliminate concurrent inserts);

S4, when a query operation occurs, the key-value data is read without lock.

In this embodiment, the write lock resource is used to control multiple concurrent insert operations.

Further, in an embodiment of the present invention, the write lock resource in the dynamic random access memory is maintained in a table structure, the input of the table structure is the node address of the index, and the output is the corresponding lock resource.

Specifically, for example, the table structure of the write lock resource is an array of 4096 64-bit lock fields; since the lock table occupies only 32KB of space, it can be cached in the high-speed CPU second-level cache and hardly introduces TLB misses. It is worth noting that this table structure will introduce pseudo-conflicts, that is, different inodes compete for the same lock field. However, since the real load is mostly query-intensive, and the query operation is lock-free, the probability of false conflict is extremely low.

It should be noted that the traditional persistent memory key-value system embeds write locks into persistent indexes, which leads to various problems: first, the lock operation will bring additional persistent memory writes, which consumes limited persistent memory Second, when the key-value system crashes and restarts, the entire index needs to be scanned to clear the contents of the lock field. On the other hand, the present invention maintains the lock resource in the DRAM, reduces the bandwidth consumption of the persistent memory and improves the recovery performance.

Further, in an embodiment of the present invention, the metadata of the key-value pair includes a key-value pair fingerprint, a key-value pair address, and a persistent flag bit, wherein the key-value pair fingerprint is several bits of the hash value of the key, The key-value pair address points to the key-value pair in the persistent memory, and the persistence flag indicates the persistent state of the metadata of the key-value pair.

Specifically, key-value pair fingerprints are used to accelerate the location of key-value pairs. When the fingerprints do not match, the query operation can directly skip the corresponding key-value pair metadata, avoiding an extra read of the key-value pair in the persistent memory. When the persistence flag is 0, it means that the metadata of the key-value pair has not been persisted; otherwise, it means that it has been successfully persisted. Key-value metadata is generally stored in indexes, including hash tables, B+ trees, dictionary trees, and so on.

Further, in one embodiment of the present invention, the atomically modifiable format means that the key-value pair metadata is packed into a contiguous persistent memory space and supports atomic modification by the CPU.

Specifically, FIG. 5 is a schematic structural diagram of key-value pair metadata according to an embodiment of the present invention. As shown in Figure 5, the key-value pair metadata is 64 bits, of which the highest 16 bits store the key-value pair fingerprint, the middle 47 bits store the key-value pair address, and the lowest 1 bit stores the persistence flag bit. The reasons why the highest 16 bits and the lowest bits can store extra information are: first, the virtual address space of Intel processors is only the lower 48 bits, and second, the persistent memory address allocated by the key-value system is 8-byte aligned (that is, the lowest 3 bits of the address are 0). The CPU can atomically manipulate 64-bit key-value metadata.

Further, in an embodiment of the present invention, the consistency state means that the metadata of the key-value system and the inserted key-value pair can be in one-to-one correspondence and are permanently stored in the persistent memory.

Further, in an embodiment of the present invention, the submission process of the insert operation includes two stages, wherein the first stage clears the persistence flag bit in the metadata of the key-value pair, and calls the CPU persistence instruction to change it from the key-value pair. The CPU cache is flushed to the persistent memory; in the second stage, the persistence flag is set to notify the read operation that the metadata of the key-value pair has been successfully persisted.

FIG. 6 is a flowchart of an insertion operation of a multi-core architecture-friendly persistent memory key-value system according to an embodiment of the present invention. As shown in FIG. 6 , the insertion operation may include the following steps:

Step S601, look up the index, locate the key-value pair metadata;

Step S602, obtaining the corresponding lock resource in the DRAM;

Step S603, allocating persistent memory, and persisting key-value pairs;

Step S604, the submission process of the key-value pair metadata insertion includes two stages, wherein the first stage clears the persistence flag bit in the key-value pair metadata, and calls the CPU persistence instruction to cache it from the CPU. flush to persistent memory;

Step S605, in the second stage of committing the insert operation, set the persistence flag, and notify the read operation that the metadata of the key-value pair has been successfully persisted.

As shown in Figure 6, before the commit process, the insert operation successfully acquires the corresponding lock resource in DRAM, allocates persistent memory, and persists the inserted key-value pair. For example, on Intel CPUs, persistent instructions include CLFLUSH, CLWB, and CLFLUSHOPT. Assignments to key-value metadata are atomic in both phases of commit; in the first phase, the entire new key-value metadata value is written and persisted. Relying on the atomic write provided by the CPU, the insert operation does not require a mechanism such as a log to protect the consistency.

Further, in an embodiment of the present invention, in the lock-free query process of the query operation, the persistence flag bit in the metadata of the target key-value pair is checked, and if the persistence flag bit is in a clear state, the CPU persistence is called. The instruction persists the key-value pair metadata and then calls the atomic instruction to set the persistence flag.

FIG. 7 is a flowchart of a query operation of a multi-core architecture-friendly persistent memory key-value system according to an embodiment of the present invention. As shown in FIG. 7 , the query operation may include the following steps:

Step S701, look up the index, locate the target key-value pair metadata;

Step S702, judging whether the persistence flag of the target key-value pair metadata is in a clear state, if so, execute step S703, if not, execute step S705;

Step S703, calling the CPU persistence instruction to persist the target key-value pair metadata;

Step S704, calling the atomic instruction CAS (compare-and-swap) to set the persistence flag;

Step S705, read the target key-value pair pointed to by the metadata.

As shown in Figure 7, during the query operation, when the persistence flag of the metadata of the target key-value pair is cleared, it means that the metadata has not been successfully persisted. Submitted data, the query operation actively persists the metadata, and calls the atomic instruction to set the persistence flag. This active persistence mechanism ensures that there is no need to traverse all the key-value pair metadata to set the persistence flag after the system crashes and restarts.

FIG. 8 is a schematic diagram of eliminating two concurrent conflict insertion operations according to an embodiment of the present invention. As shown in FIG. 8 , in this embodiment, when two concurrent conflicting insert operations occur, one of the operations returns directly without any allocation and modification of persistent memory. This mechanism for eliminating operations does not violate correct concurrency semantics, because in the definition of linearizability, the result of executing two operations that overlap in time is equivalent to executing in a certain serial order. result.

Further, in an embodiment of the present invention, for the problem of lock-free reading in query operations, a memory recycling method based on Epoch (time period) is used, and background threads are used to periodically recycle memory garbage.

Specifically, the key-value system maintains a global counter, while each thread maintains a local counter. At the beginning of each key-value operation, update the local counter to the global counter. When the persistent memory space needs to be released, <local counter value, released memory address> will be recorded in the recycle linked list. At the same time, a background thread periodically increments the global counter by 1, collects the local counter values of all threads, and calculates the minimum value, which is recorded as Safe-Epoch; at this time, all memory less than Safe-Epoch in the linked list can be recovered. was released safely.

During the insertion operation of the above-mentioned embodiment of the present invention, the operation of the write lock resource does not introduce any writing to the persistent memory, and no log operation is required, thereby improving the performance of the insertion operation. Additionally, persistent memory allocations and writes are further reduced when multiple concurrent conflicting insert operations occur. For query operations, its lock-free process greatly improves the concurrent query performance of the key-value system under the multi-core architecture while ensuring correct semantics.

Embodiments of the present invention further provide a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, wherein the computer program is configured to execute the steps in any of the above method embodiments when running.

In an exemplary embodiment, the above-mentioned computer-readable storage medium may include, but is not limited to, a USB flash drive, a read-only memory (Read-Only Memory, referred to as ROM for short), and a random access memory (Random Access Memory, referred to as RAM for short) , mobile hard disk, magnetic disk or CD-ROM and other media that can store computer programs.

An embodiment of the present invention also provides an electronic device, comprising a memory and a processor, where a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any of the above method embodiments.

In an exemplary embodiment, the above-mentioned electronic device may further include a transmission device and an input-output device, wherein the transmission device is connected to the above-mentioned processor, and the input-output device is connected to the above-mentioned processor.

For specific examples in this embodiment, reference may be made to the examples described in the foregoing embodiments and exemplary implementation manners, and details are not described herein again in this embodiment.

Obviously, those skilled in the art should understand that the above-mentioned modules or steps of the present invention can be implemented by a general-purpose computing device, which can be centralized on a single computing device, or distributed in a network composed of multiple computing devices On the other hand, they can be implemented in program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, can be performed in a different order than shown here. Or the described steps, or they are respectively made into individual integrated circuit modules, or a plurality of modules or steps in them are made into a single integrated circuit module to realize. As such, the present invention is not limited to any particular combination of hardware and software.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention shall be included within the protection scope of the present invention.

Claims (17)

1. A method of operation of a persistent memory key-value system, comprising:

   Look up the index of the persistent memory key-value system to locate the key-value pair metadata to be inserted;

   obtaining the write lock resource corresponding to the key-value pair metadata in the dynamic random access memory;

   Allocating persistent memory for the key-value pair metadata, and persisting the key-value pair metadata;

   The key-value pair metadata is atomically inserted into the persistent memory key-value system, wherein the commit process of the key-value pair metadata insertion includes two stages. Clear the persistent flag bit in the metadata, and call the CPU persistent instruction to flush it from the CPU cache to persistent memory; in the second stage, set the persistent flag bit and notify the read operation of the key value The metadata has been successfully persisted.
2. The method according to claim 1, wherein before acquiring the write lock resource corresponding to the key-value pair metadata in the dynamic random access memory, the method further comprises:

   The write lock resource is decoupled from the index of the persistent memory key-value system, and the write lock resource is maintained in the dynamic random access memory.
3. The method of claim 2, wherein the write lock resource is maintained in the dynamic random access memory in a table structure, wherein the input of the table structure is the node address of the index, the The output is the corresponding write lock resource.
4. The method of claim 1, wherein prior to atomically inserting the key-value pair metadata in the persistent memory key-value system, further comprising:

   The key-value pair metadata is stored in an atomically modifiable format.
5. 5. The method of claim 4, wherein the atomically modifiable format means that the key-value pair metadata is packed into a contiguous persistent memory space and supports atomic modification by the CPU.
6. The method of claim 1, further comprising:

   When the conflicting first insert operation and the second insert operation occur at the same time, the persistent memory allocation and writing are not performed for the first insert operation, and the first insert operation is returned.
7. The method according to claim 1, wherein the key-value pair metadata includes at least one of the following: a key-value pair fingerprint, a key-value pair address, and a persistent flag; wherein the key-value pair fingerprint is a key-value pair fingerprint. Among several bits of the hash value, the address of the key-value pair points to the key-value pair in the persistent memory, and the persistence flag indicates the persistent state of the metadata of the key-value pair.
8. The method of claim 1, wherein after atomically inserting the key-value pair metadata into the persistent memory key-value system, further comprising:

   The key-value pair metadata is queried lock-free in the persistent memory key-value system.
9. The method of claim 8, wherein querying the key-value pair metadata lock-free comprises:

   Check the persistence flag bit in the key-value pair metadata, if the persistence flag bit is in a clear state, call the CPU persistence instruction to persist the target key-value pair metadata;

   Call the atomic instruction to set the persistent flag, and read the key-value pair pointed to by the metadata.
10. The method of claim 1, further comprising:

    A time-cycle-based memory recycling method that periodically recycles persistent memory garbage through background threads.
11. A persistent memory key-value system that includes:

    A lookup module, set to look up the index of the persistent memory key-value system to locate the key-value pair metadata to be inserted;

    an acquisition module, configured to acquire the write lock resource corresponding to the metadata of the key-value pair in the dynamic random access memory;

    an allocation module, configured to allocate persistent memory for the key-value pair metadata, and persist the key-value pair metadata;

    an insertion module, configured to atomically insert the key-value pair metadata in the persistent memory key-value system, wherein the submission process of the key-value pair metadata insertion includes two stages, wherein in the first stage , clear the persistent flag bit in the metadata of the key-value pair, and call the CPU persistent instruction to flush it from the CPU cache to persistent memory; in the second stage, set the persistent flag bit, and Notifies read operations that the key-value pair metadata has been successfully persisted.
12. The system of claim 11, further comprising;

    A maintenance module, configured to separate the write lock resource from the index of the persistent memory key-value system, and maintain the write lock resource in the dynamic random access memory.
13. The system of claim 11, further comprising:

    A storage module, configured to store the key-value pair metadata in an atomically modifiable format.
14. The system of claim 11, further comprising:

    A query module, configured to query the key-value pair metadata in the persistent memory key-value system without lock.
15. The system of claim 11, further comprising:

    The recycling module is set to the memory recycling method based on the time period, and the persistent memory garbage is periodically recycled through the background thread.
16. A computer-readable storage medium storing a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 10 when the computer program is executed by a processor .
17. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the claims 1 to 10 when executing the computer program The steps of the method of any one.

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