WO2022095179A1 - 数据处理系统、方法、电子设备及存储介质 - Google Patents

数据处理系统、方法、电子设备及存储介质 Download PDF

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Publication number
WO2022095179A1
WO2022095179A1 PCT/CN2020/133230 CN2020133230W WO2022095179A1 WO 2022095179 A1 WO2022095179 A1 WO 2022095179A1 CN 2020133230 W CN2020133230 W CN 2020133230W WO 2022095179 A1 WO2022095179 A1 WO 2022095179A1
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Prior art keywords
data
data processing
processed
processing
instruction
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PCT/CN2020/133230
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English (en)
French (fr)
Inventor
戴刘江
吴国锋
苏国彬
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辰芯科技有限公司
宸芯科技有限公司
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Publication of WO2022095179A1 publication Critical patent/WO2022095179A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/64—Protecting data integrity, e.g. using checksums, certificates or signatures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of communication technologies, for example, to a data processing system, method, electronic device and storage medium.
  • Data processing technology is an important part of the field of communication technology, and can be widely used in communication scenarios such as the field of Internet of Things communication, in-vehicle communication, and financial communication.
  • the process of data processing is usually based on data, that is, only one piece of data is processed at a time. For example, signature processing or signature verification processing is performed for one piece of data at a time.
  • This data processing method with single data as a unit has problems such as low data transmission efficiency, prolonged time, and excessive computing resources.
  • the present application provides a data processing system, method, electronic device, and storage medium, so as to improve the data transmission efficiency in the data processing process, reduce the data processing delay and computing resource occupancy, and further improve the data processing efficiency.
  • a data processing subsystem comprising: an interrupt processing module and a data processing module, the interrupt processing module is connected in communication with the data processing module, wherein:
  • the interrupt processing module is configured to send a plurality of data to be processed to the data processing module, and when it is determined that a target data processing instruction instruction is received, an interrupt instruction is generated, wherein the target data processing instruction instruction is used to indicate the plurality of pending data processing instructions. The last pending data in the data is processed;
  • the data processing module is set to receive a plurality of data to be processed, perform data processing on the plurality of data to be processed in sequence according to the receiving order of the data to be processed, and send each data to the interrupt processing module after the processing of each data to be processed is completed.
  • the data processing instruction instruction corresponding to the data to be processed.
  • Also provided is a data processing system comprising:
  • the data processing subsystem provided by any embodiment further includes a communication processor, a central processing unit CPU, and a data storage module, wherein:
  • the communication processor is connected in communication with the data storage module, and the communication processor is configured to send a plurality of data to be processed to the data storage module;
  • the data storage module is also connected in communication with the data processing subsystem and the CPU, and the data storage module is configured to store a plurality of data to be processed;
  • the CPU is connected in communication with the data processing subsystem, and the CPU is configured to receive communication data sent by the data processing subsystem, or the CPU is configured to send a plurality of data to be processed to the data storage module, wherein the communication data is the data processing subsystem for a plurality of to-be-processed data.
  • Process data The data obtained after data processing.
  • a data processing method is also provided, applied to the data processing module, including:
  • the data processing instruction instruction includes a target data processing instruction instruction, and the target data processing instruction instruction is used to instruct the generation of an interrupt instruction.
  • an electronic device comprising:
  • processors one or more processors
  • storage means arranged to store one or more programs
  • the one or more processors implement the data processing method provided by any embodiment of the present application.
  • a computer storage medium which stores a computer program, and when the computer program is executed by a processor, implements the data processing method provided by any embodiment of the present application.
  • FIG. 1 is a schematic diagram of a data processing subsystem provided in Embodiment 1 of the present application.
  • FIG. 2 is an example diagram of a communication connection of a data processing module provided in Embodiment 1 of the present application;
  • FIG. 3 is a schematic diagram of a data processing system provided in Embodiment 2 of the present application.
  • FIG. 4 is a schematic diagram of a configuration result of data to be processed corresponding to an interrupt provided in Embodiment 2 of the present application;
  • FIG. 5 is a flowchart of a data processing method provided in Embodiment 3 of the present application.
  • FIG. 6 is a schematic structural diagram of an electronic device according to Embodiment 4 of the present application.
  • FIG. 1 is a schematic diagram of a data processing subsystem provided in Embodiment 1 of the present application. This embodiment can be applied to a situation where an interrupt is generated after processing multiple data to be processed.
  • the data processing subsystem 100 includes: an interrupt processing module 110 and a data processing module 120, the interrupt processing module 110 is connected in communication with the data processing module 120, wherein: the interrupt processing module 110 is configured to The data processing module 120 sends a plurality of data to be processed, and generates an interrupt instruction when it is determined that the target data processing instruction instruction is received.
  • the data processing module 120 is configured to receive a plurality of data to be processed, perform data processing on the plurality of data to be processed in sequence according to the receiving sequence of the data to be processed, and send the data to the interrupt processing module 110 after the processing of each data to be processed is completed.
  • the target data processing instruction instruction is used to indicate that the last to-be-processed data processing is completed.
  • the target data processing instruction instruction is used to indicate that the processing of the last to-be-processed data in the plurality of to-be-processed data is completed.
  • the data to be processed may be the data to be processed by the data processing module 120.
  • the data to be processed may include the data to be signed or the data to be verified, wherein the data to be signed may need to be signed.
  • Data, the data to be processed for signature verification can be the data that needs to be processed for signature verification.
  • the data to be processed for signature verification may include the public key and the data to be verified.
  • the data to be signed may be data obtained from the sender through signature processing.
  • the data that needs to be signed can include the private key, signer information, and data to be signed.
  • the data to be signed may be original data that needs to be signed but has not yet been signed.
  • the data to be signed may include electronic files, transfer data, vehicle location data, etc., and the data content and type of the data to be signed are not limited in this embodiment of the present application.
  • the signer information may be information that can prove the identity of the signer.
  • the signer information may include the signer's ID number or the signer's phone number.
  • the interrupt instruction may be an instruction for instructing to generate an interrupt operation. In this embodiment of the present application, one interrupt instruction may correspond to multiple processing procedures of data to be processed.
  • the data processing instruction instruction may be a data instruction sent by the data processing module 120, and the data processing instruction instruction may be used to indicate that the processing of the data to be processed is completed. Each data processing instruction instruction can be used to indicate that the corresponding data to be processed has been processed.
  • the last data to be processed may be the last data to be processed received by the data processing module 120 .
  • the target data processing instruction instruction may be a data processing instruction instruction sent by the data processing module 120 when the processing of the last to-be-processed
  • the interrupt processing module 110 may sequentially send a plurality of data to be processed to the data processing module 120, and the data processing module 120 sequentially performs data processing on the data to be processed according to the receiving order of the data to be processed.
  • the data processing module 120 processes the first received data to be processed, and after the processing of the data to be processed is completed, sends a data processing instruction instruction corresponding to the data to be processed to the interrupt processing module 110, that is, indicates the data to be processed. Processing data has finished processing.
  • the interrupt processing module 110 After receiving the data processing instruction instruction corresponding to the first data to be processed, the interrupt processing module 110 sends the second data to be processed to the data processing module 120, and the data processing module 120 completes the data processing corresponding to the second data to be processed.
  • the second data processing instruction instruction of the data to be processed is sent to the interrupt processing module 110, and so on.
  • the data processing module 120 sends a target data processing instruction instruction to the interrupt processing module 110 when the last pending data processing is completed, that is, indicating that the last pending data processing is completed, and the interrupt processing module 110 generates an interrupt after receiving the target data processing instruction instruction. instruction.
  • the related technology when a vehicle sends signature-processed data of itself and also needs to perform signature verification processing on the signature-processed data sent by multiple other vehicles, the related technology will perform data processing for one piece of data at a time. And an interruption is generated, which will cause the related technology to fail to meet the requirements for data processing efficiency and data transmission efficiency in the field of vehicle communication.
  • the data processing subsystem 100 provided by the embodiment of the present application can realize that only one interrupt instruction is generated for multiple data processing, which will effectively reduce the data processing delay.
  • the data processing subsystem 100 can enable the vehicle location information to be received and processed by roadside equipment and surrounding vehicles in a timely manner, thereby effectively reducing the incidence of vehicle accidents .
  • the data processing module 120 is configured to perform signature processing and/or signature verification processing on the data to be processed.
  • Signature processing can perform data processing for the data to be signed.
  • the digest calculation is performed on the data to be signed to obtain the digest of the data to be signed
  • the signature calculation is performed on the digest of the data to be signed by using the private key.
  • the signature verification processing can perform signature verification processing for the data to be processed for signature verification.
  • a signature verification algorithm is used to perform digest calculation on the data to be processed for signature verification to obtain a digest of the processed data to be signature verified, and the signature verification calculation is performed using the public key for the digest of the processed data to be verified signature.
  • the data processing module 120 performs signature verification processing on the received data to be processed for signature verification, and may also perform signature processing on the received data to be processed for signature processing. If the data to be processed for signature verification is processed and the signature verification passes, it proves the integrity and non-repudiation of the received information; otherwise, it proves that the received information has been tampered with.
  • the data processing module 120 supports signature and verification operations based on Elliptic Curve Digital Signature Algorithm (ECDSA) and State Secret Asymmetric Encryption Algorithm (SM2); supports Secure Hash Algorithm 2 (Secure Hash Algorithm 2, SHA2) and digest algorithm (SM3) hash calculation function; support Advanced Encryption Standard (Advanced Encryption Standard, AES) and national secret symmetric encryption algorithm (SM4) and other encryption operation functions.
  • EDSA Elliptic Curve Digital Signature Algorithm
  • SM2 State Secret Asymmetric Encryption Algorithm
  • SM3 Secure Hash Algorithm 2
  • SHA2 Secure Hash Algorithm 2
  • SM3 digest algorithm
  • AES Advanced Encryption Standard
  • SM4 national secret symmetric encryption algorithm
  • the interrupt processing module 110 may include a configuration parameter storage module; the configuration parameter storage module is configured to store a plurality of configuration parameters of the data to be processed; the interrupt processing module 110 is configured to process the data according to the configuration parameters Module 120 sends a plurality of data to be processed.
  • Configuration parameters can be used to configure the data to be processed. For example, the source address information and destination address information of the data to be processed, etc. can be determined.
  • the interrupt processing module 110 may read the data to be processed according to the configuration parameters of the data to be processed stored in the configuration parameter storage module, and send the data to be processed to the data processing module 120 .
  • the interrupt processing module 110 sends one piece of data to be processed to the data processing module 120 at a time, and after multiple transmissions of the data to be processed, the data processing module 120 finally sends multiple pieces of data to be processed.
  • the configuration parameters may include source configuration parameters and destination configuration parameters; the source configuration parameters may include the source address and the number of registers corresponding to multiple sources at the destination; the destination configuration parameters may include Including the destination address and the data lengths corresponding to multiple destinations.
  • the configuration parameters of the source end may be related parameters of the end sending the data to be processed, and the configuration parameters of the destination end may be the relevant parameters of the end receiving the data to be processed.
  • the interrupt processing module 110 can read the data to be processed according to the configuration parameters of the source end, and can send the data to be processed to the data processing module 120 according to the configuration parameters of the destination end.
  • the source address may be a memory address where the data to be processed is located, and the interrupt processing module 110 reads the to-be-processed data according to the source address in the source configuration parameter.
  • the destination address may be the memory address of the data to be processed in the data processing module 120 .
  • the number of registers of the source end corresponding to the destination end may be the number of registers occupied by the data to be processed in the data processing module 120 , which is used to configure the registers of the data processing module 120 .
  • the data length corresponding to the destination can be the number of bytes occupied by the data to be processed.
  • the interrupt processing module 110 After reading the data to be processed according to the source address, the interrupt processing module 110 sends the data to be processed to a corresponding register of the data processing module 120 for storing the data to be processed according to the address of the destination.
  • the interrupt processing module 110 needs to transmit two data to be processed to the data processing module 120, that is, the number of registers corresponding to the source end corresponding to the destination end is two. If each data to be processed occupies 1 byte, the data length corresponding to the destination end is 2 bytes. Because one interrupt instruction corresponds to the processing of multiple data to be processed, the source address, destination address, number of registers, and number of bytes occupied by the data to be processed corresponding to each interrupt instruction may be different. Before the interrupt processing module 110 reads and sends the data to be processed, it needs to configure the source address, the number of registers corresponding to the multiple sources corresponding to the destination, the address of the destination, and the data length corresponding to the multiple destinations.
  • FIG. 2 is an example diagram of a communication connection of a data processing module provided in Embodiment 1 of the present application.
  • the data processing module 120 may include a data processing unit 121, a data processing result register 122, and a data status register 123.
  • the data processing unit 121 is connected in communication with the interrupt processing module 110, wherein: the data processing unit 121 is configured to receive a plurality of pending data sent by the interrupt processing module 110 according to the configuration parameters and perform data processing to obtain the data processing result; the data processing result register 122 Communication connection with the data processing unit 121, the data processing result register 122 is set to receive and store the data processing result; the data status register 123 is communicatively connected with the data processing unit 121, and the data status register 123 is set to determine the data processing unit 121 to obtain the data processing result After that, update the data processing status of multiple data to be processed.
  • the interrupt processing module 110 sends a piece of data that needs signature verification processing to the data processing unit 121, and the data processing unit 121 stores and performs signature verification processing on the received data that needs signature verification processing.
  • the data processing result register 122 receives and stores the data after signature verification processing sent by the data processing unit 121 .
  • the data status register 123 updates the data processing status of the data that needs signature verification processing to a completed status. If the data to be subjected to signature verification processing has not been subjected to signature verification processing, the data processing status corresponding to the data to be subjected to signature verification processing that has not been subjected to signature verification processing is the pending status.
  • the interrupt processing module 110 may be further configured to: generate a data processing identifier for each data to be processed; the data processing identifier is used to instruct the data processing module 120 to start data processing.
  • the data processing identifier can be a data identifier, for example, the data processing identifier can be a flag bit, and the flag bit can be set after each data to be processed.
  • a flag bit that is, a data processing identifier
  • the data processing module 120 starts to perform data processing after reading the flag bit of the data to be processed.
  • the interrupt processing module sends a plurality of data to be processed to the data processing module, so that the data processing module sequentially performs data processing on the data to be processed according to the receiving order of the data to be processed, and after the processing of each data to be processed is completed , and send a data processing instruction instruction corresponding to each data to be processed to the interrupt processing module.
  • the interrupt processing module receives the target data processing instruction instruction, it generates an interrupt instruction to instruct the batch pending data processing to be completed.
  • the data transmission efficiency in the data processing process is reduced, the data processing delay and the occupation of computing resources are reduced, and the data processing efficiency is improved.
  • FIG. 3 is a schematic diagram of a data processing system provided in Embodiment 2 of the present application.
  • the data processing system includes the data processing subsystem 100 in any embodiment of the present application, and further includes a communication processor 130 and a central processing unit.
  • the communication processor 130 is connected in communication with the data storage module 150, and the communication processor 130 is configured to send a plurality of data to be processed to the data storage module 150;
  • the data storage module 150 is also communicatively connected with the data processing subsystem 100 and the CPU 140, and the data storage module 150 is set to store a plurality of data to be processed;
  • the CPU 140 is communicatively connected with the data processing subsystem 100, and the CPU 140 is set to receive the communication data sent by the data processing subsystem 100, Or the CPU 140 is configured to send a plurality of data to be processed to the data storage module 150, wherein the communication data is data obtained after the data processing subsystem 100 performs data processing on the plurality of data to be processed.
  • the communication data may include data obtained by performing data processing on the data to be processed for signature verification.
  • the data storage module 150 receives and stores a plurality of data to be processed for signature verification sent by the communication processor 130 .
  • the interrupt processing module 110 reads a plurality of data to be processed for signature verification stored in the data storage module 150, and sends the data to be processed for signature verification to the data processing module 120, and the data processing module 120 processes the received signature verification data.
  • the data is subjected to signature verification processing, and after the processing of a plurality of data to be signature verification processing is completed, the interrupt processing module 110 generates an interrupt instruction.
  • the CPU 140 generates an interrupt according to the interrupt instruction to prepare for the next multiple data processing or other program calls to be processed for signature verification.
  • the CPU 140 sends the data to be signed to the data storage module 150, and the data processing subsystem 100 reads the data to be signed stored in the data storage module 150 and performs Signature processing.
  • the data storage module 150 may be integrated into the data processing module 120 .
  • FIG. 4 is a schematic diagram of a configuration result of data to be processed corresponding to an interrupt provided in Embodiment 2 of the present application.
  • the black area represents the memory space of the data storage module 150
  • the white area represents data processing
  • the interrupt processing module 110 reads the data to be processed from the memory space of the data storage module 150 and sends it to the data processing unit 121 of the data processing module 120 .
  • the data to be processed stored in the data storage module 150 all have data processing identifiers.
  • the interrupt handling module 110 is also arranged to send the data processing result in the data processing result register 122 and the data processing status in the data status register 123 to the data storage module 150.
  • the data processing unit 121 starts to perform data processing on the first data to be processed according to the data processing identifier, and after completing the processing of the first data to be processed, the data processing module 120 stores the corresponding data processing results in the data.
  • the data processing state corresponding to the data to be processed is stored in the memory space of the data state register 123 , and the data processing module 120 sends a data processing instruction instruction to the interrupt processing module 110 .
  • the interrupt processing module 110 sends the data processing result to the data processing result storage area of the data storage module 150 , and sends the data processing status to the data status storage area of the data storage module 150 .
  • the interrupt processing module 110 After receiving the data processing instruction instruction corresponding to the first data to be processed, the interrupt processing module 110 sends the second data to be processed to the data processing unit 121 .
  • the data processing unit 121 performs the second data processing, and sends the data processing result and the data processing status to the data processing result register 122 and the data status register 123 respectively.
  • the data processing module 120 sends a data processing instruction instruction to the interrupt processing module 110 .
  • the interrupt processing module 110 sends the data processing result and the data processing status to the data processing result storage area and the data status storage area, respectively.
  • the interrupt processing module 110 After receiving the data processing instruction instruction corresponding to the second data to be processed, the interrupt processing module 110 sends the third data to be processed to the data processing unit 121 .
  • the data processing subsystem 100 can complete the processing of N pieces of data to be processed. After the processing of a plurality of data to be processed is completed, the CPU 140 generates an interrupt according to the interrupt instruction sent by the interrupt processing module 110 .
  • the data processing system may further include a radio frequency interface 160, the radio frequency interface 160 is communicatively connected to the communication processor 130, and the radio frequency interface 160 is configured to receive raw data to be processed, and The original data to be processed is sent to the communication processor 130; the communication processor 130 is configured to perform data preprocessing on the original data to be processed to generate the data to be processed.
  • the radio frequency interface 160 is communicatively connected to the communication processor 130, and the radio frequency interface 160 is configured to receive raw data to be processed, and The original data to be processed is sent to the communication processor 130; the communication processor 130 is configured to perform data preprocessing on the original data to be processed to generate the data to be processed.
  • the raw data to be processed may be raw data without any data processing.
  • the original data to be processed may include data to be processed for signature verification and received by the radio frequency interface 160 without data preprocessing.
  • the radio frequency interface 160 may include a radio frontend and baseband digital parallel (Radiofrontend-Baseband Digital Parallel, RBDP) interface or a standard/non-standard high-speed interface and the like.
  • Data preprocessing may include performing data processing on the original data to be processed or on the data that has completed signature processing.
  • the radio frequency interface 160 receives the data requiring signature verification processing without data preprocessing, and sends the data requiring signature verification processing without data preprocessing to the communication processor 130, and the communication processor 130 receives the data.
  • the received data that has not undergone data preprocessing and needs to be processed for signature verification is decoded, accelerated, and unpacked.
  • the communication processor 130 can also perform processing such as encoding, acceleration and packaging on the data that has completed the signature processing, and send the data obtained after data preprocessing to the radio frequency interface 160, and the radio frequency interface 160 sends the data to other devices for signature verification processing. .
  • the CPU 140 may also be configured to perform configuration parameter initialization processing on the data storage module 150 before the data processing subsystem 100 performs data processing.
  • the configuration parameter initialization processing may include initialization of the memory unit corresponding to the to-be-processed data stored in the data storage module 150 , such as setting the start address, destination address, occupied memory space and the number of bytes of the memory unit of the to-be-processed data.
  • the CPU 140 opens up a memory space for the data storage module 150, and processes the data to be processed according to the start address, destination address and the number of bytes of the memory unit corresponding to the data to be processed. of storage.
  • the CPU 140 may also generate an interrupt in response to the interrupt instruction sent by the interrupt processing module 110 .
  • the CPU 140 may also respond to data requests from other devices, for example, to the device that sent the data request.
  • the response request may be a response from device A to a data request from device B.
  • device B needs the location information of device A, device B sends a request for location information to device A, and device A responds to the request by sending its own location information to device B or not responding to the request.
  • the CPU 140 can determine whether to perform the signature verification processing of the data to be verified for signature processing and/or the signature processing of the data to be signed and perform corresponding program scheduling. For example, the CPU 140 can determine whether to perform signature verification of the data to be verified for signature. Processing and/or signature processing of data to be signed and scheduling of corresponding programs, etc.
  • the data processing subsystem processes the data to be processed, and sends the communication data to the CPU.
  • the CPU can also send the data to be processed to the data storage module, and the data processing subsystem processes the data to be processed and sends the processed data to the communication processor.
  • This embodiment realizes the two-way communication between the data processing subsystem and the CPU, as well as the data processing subsystem and the communication processor, and the data processing subsystem can realize that only one interrupt instruction is generated after the data processing of multiple data to be processed is completed, which solves the problem of solving the problem.
  • the problem of excessive computer resource occupation during data processing improves data processing efficiency and reduces data transmission delay and computer occupancy.
  • Embodiment 5 is a flowchart of a data processing method provided in Embodiment 3 of the present application. This embodiment is applicable to a high-speed signature/verification scenario, and the method can be executed by a data processing module, which can be executed by software and/or or hardware, and can be integrated in an electronic device, as shown in FIG. 5 , the method includes the following operations.
  • S310 Receive multiple pieces of data to be processed.
  • S320 Perform data processing on the plurality of data to be processed in sequence according to the receiving sequence of the plurality of data to be processed.
  • the data processing instruction instruction includes a target data processing instruction instruction, and the target data processing instruction instruction is used to instruct the generation of an interrupt instruction.
  • performing data processing on the plurality of data to be processed in sequence according to the receiving order of the plurality of data to be processed includes: sequentially processing the plurality of data to be processed according to the receiving order of the plurality of data to be processed.
  • Process data for signature processing and/or signature verification processing includes: sequentially processing the plurality of data to be processed according to the receiving order of the plurality of data to be processed.
  • the method before receiving a plurality of data to be processed, the method further includes: storing the configuration parameters of the plurality of data to be processed through the configuration parameter storage module of the interrupt processing module; sending the data to the data through the interrupt processing module according to the configuration parameters.
  • the processing module sends a plurality of data to be processed.
  • the configuration parameters include source configuration parameters and destination configuration parameters; the source configuration parameters include the source address and the number of registers corresponding to the multiple sources at the destination; the destination configuration parameters include the destination address.
  • the data processing module includes a data processing unit, a data processing result register and a data status register, the data processing unit is communicatively connected to the interrupt processing module, and the data processing unit is in accordance with the receiving order of the plurality of data to be processed.
  • Performing data processing on the plurality of data to be processed in sequence further comprising: receiving, by a data processing unit, the plurality of data to be processed sent by the interrupt processing module according to the configuration parameters, and performing data processing to obtain a data processing result;
  • the data processing result is received and stored through the data processing result register; after it is determined that the data processing unit obtains the data processing result, the data processing status of the plurality of data to be processed is updated through the data status register.
  • the method further includes: generating a data processing identifier for each data to be processed; the data processing identifier is used to instruct the data processing module to start data processing.
  • the method before receiving the multiple data to be processed, further includes: sending the multiple data to be processed to the data storage module through the communication processor; storing the multiple pending data through the data storage module; using the CPU Receive communication data, or send the plurality of data to be processed to the data storage module through the CPU, wherein the communication data is data obtained by performing data processing on the plurality of data to be processed.
  • the method further includes: receiving original data to be processed through a radio frequency interface, and sending the original data to be processed to the communication processor; the communication processor is set to Data preprocessing is performed on the original data to be processed to generate the data to be processed.
  • the method before performing data processing on the plurality of data to be processed in sequence according to the receiving order of the plurality of data to be processed, the method further includes: performing configuration parameter initialization processing on the data storage module by the CPU.
  • the method further includes: sending the data processing result in the data processing result register and the data processing status in the data status register to the data storage module through the interrupt processing module.
  • This embodiment of the present application sends a plurality of data to be processed to the data processing module through the interrupt processing module, so that the data processing module sequentially performs data processing on the plurality of data to be processed according to the receiving order of the plurality of data to be processed, and performs data processing on each data to be processed.
  • a data processing instruction instruction corresponding to each data to be processed is sent to the interrupt processing module.
  • the interrupt processing module receives the target data processing instruction instruction, it generates an interrupt instruction to instruct the batch pending data processing to be completed.
  • the data transmission efficiency in the data processing process is reduced, the data processing delay and the occupation of computing resources are reduced, and the data processing efficiency is improved.
  • FIG. 6 is a schematic structural diagram of an electronic device according to Embodiment 4 of the present application.
  • FIG. 6 shows a block diagram of an electronic device 412 suitable for implementing embodiments of the present application.
  • the electronic device 412 shown in FIG. 6 is only an example, and should not impose any limitations on the functions and scope of use of the embodiments of the present application.
  • electronic device 412 takes the form of a general-purpose computing device.
  • Components of electronic device 412 may include: one or more processors 416, storage 428, and a bus 418 connecting various system components including storage 428 and processor 416.
  • Bus 418 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of a variety of bus structures.
  • these architectures include Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) ) local bus and peripheral component interconnect (Peripheral Component Interconnect, PCI) bus.
  • ISA Industry Standard Architecture
  • MCA Micro Channel Architecture
  • VESA Video Electronics Standards Association
  • PCI peripheral component interconnect
  • Electronic device 412 includes a variety of computer system readable media. These media can be any available media that can be accessed by electronic device 412, including both volatile and nonvolatile media, removable and non-removable media.
  • Storage 428 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 430 and/or cache 432 .
  • Electronic device 412 may include other removable/non-removable, volatile/non-volatile computer system storage media.
  • storage system 434 may be configured to read and write to non-removable, non-volatile magnetic media (not shown in FIG. 6, commonly referred to as a "hard drive”).
  • disk drives for reading and writing to removable non-volatile magnetic disks (eg, "floppy disks") and removable non-volatile optical disks (eg, portable compact disk read-only memory) may be provided.
  • Storage 428 may include at least one program product having a set (eg, at least one) of program modules configured to perform the functions of various embodiments of the present application.
  • a program 436 having a set (at least one) of program modules 426 which may be stored, for example, in a storage device 428, such program modules 426 including an operating system, one or more application programs, other program modules, and program data, in these examples
  • Program modules 426 generally perform the functions and/or methods of the embodiments described herein.
  • the electronic device 412 may also communicate with one or more external devices 414 (eg, keyboards, pointing devices, cameras, and displays 424, etc.), and may also communicate with one or more devices that enable a user to interact with the electronic device 412, and/or Or any device (eg, network card, modem, etc.) that enables the electronic device 412 to communicate with one or more other computing devices. Such communication may take place through Input/Output (I/O) interface 422 . Also, the electronic device 412 may communicate with one or more networks (eg, a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network such as the Internet) through a network adapter 420. As shown in FIG.
  • LAN Local Area Network
  • WAN Wide Area Network
  • public network such as the Internet
  • network adapter 420 communicates with other modules of electronic device 412 via bus 418 .
  • other hardware and/or software modules may be used in conjunction with electronic device 412, including: microcode, device drivers, redundant processing units, external disk drive arrays, Redundant Arrays of Independent Disks (RAID) systems, tape drives, and data backup storage systems.
  • the processor 416 executes a variety of functional applications and data processing by running the programs stored in the storage device 428, for example, implementing the data processing method provided by the above embodiments of the present application, including: receiving a plurality of data to be processed; The receiving sequence of the plurality of data to be processed sequentially performs data processing on the plurality of data to be processed; after the processing of each data to be processed is completed, a data processing instruction instruction corresponding to each data to be processed is generated; wherein, the data processing The instruction instruction includes a target data processing instruction instruction, and the target data processing instruction instruction is used to instruct the generation of an interrupt instruction.
  • the interrupt processing module sends a plurality of data to be processed to the data processing module, so that the data processing module sequentially performs data processing on the data to be processed according to the receiving order of the data to be processed, and after the processing of each data to be processed is completed , and send a data processing instruction instruction corresponding to each data to be processed to the interrupt processing module.
  • the interrupt processing module receives the target data processing instruction instruction, it generates an interrupt instruction to instruct the batch pending data processing to be completed.
  • the data transmission efficiency in the data processing process is reduced, the data processing delay and the occupation of computing resources are reduced, and the data processing efficiency is improved.
  • the fifth embodiment of the present application further provides a computer storage medium storing a computer program, the computer program being used to execute the data processing method described in any one of the above-mentioned embodiments of the present application when executed by a computer processor, including: receiving a plurality of data to be processed; data processing is performed on the plurality of data to be processed in sequence according to the receiving order of the plurality of data to be processed; after the processing of each data to be processed is completed, a data processing instruction instruction corresponding to each data to be processed is generated ; wherein, the data processing instruction instruction includes a target data processing instruction instruction, and the target data processing instruction instruction is used to instruct the generation of an interrupt instruction.
  • the computer storage medium of the embodiments of the present application may adopt any combination of one or more computer-readable media.
  • the computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium.
  • the computer-readable storage medium can be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or a combination of any of the above.
  • Computer-readable storage media include: electrical connections with one or more wires, portable computer disks, hard disks, RAM, Read Only Memory (ROM), Erasable Programmable Read Only Memory (Erasable Programmable Read Only Memory) , EPROM) or flash memory, optical fiber, CD-ROM, optical storage devices, magnetic storage devices, or any suitable combination of the above.
  • a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.
  • a computer-readable signal medium may include a propagated data signal in baseband or as part of a carrier wave, with computer-readable program code embodied thereon. Such propagated data signals may take a variety of forms, including electromagnetic signals, optical signals, or any suitable combination of the foregoing.
  • a computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device .
  • Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including wireless, wire, optical fiber cable, radio frequency (RF), etc., or any suitable combination of the foregoing.
  • RF radio frequency
  • Computer program code for performing the operations of the present application may be written in one or more programming languages, including object-oriented programming languages—such as Java, Smalltalk, C++, but also conventional A procedural programming language, such as the "C" language or similar programming language.
  • the program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server.
  • the remote computer may be connected to the user's computer through any kind of network, including a LAN or WAN, or may be connected to an external computer (eg, using an Internet service provider to connect through the Internet).

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Abstract

一种数据处理系统、方法、电子设备及存储介质。其中，数据处理子系统，包括：中断处理模块和数据处理模块，中断处理模块与数据处理模块通信连接，其中：中断处理模块设置为向数据处理模块发送多个待处理数据，并在确定接收到目标数据处理指示指令的情况下，生成中断指令；数据处理模块设置为接收多个待处理数据，按照多个待处理数据的接收顺序依次对多个待处理数据进行数据处理，并在每个待处理数据处理完成后，向中断处理模块发送每个待处理数据对应的数据处理指示指令。

Description

数据处理系统、方法、电子设备及存储介质
本申请要求在2020年11月06日提交中国专利局、申请号为202011233285.5的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，例如涉及一种数据处理系统、方法、电子设备及存储介质。
背景技术
数据处理技术是通信技术领域的一个重要组成部分，可以广泛应用于物联网通信领域、车载通信领域和金融通信领域等通信场景。
数据处理的过程通常以数据为单位，即每次仅针对一条数据进行数据处理。例如，每次针对一条数据进行签名处理或验签处理等。这种以单次数据为单位的数据处理方式存在数据传输效率低、时延长且占用过多计算资源等问题。
发明内容
本申请提供一种数据处理系统、方法、电子设备及存储介质，以提高数据处理过程中的数据传输效率，降低数据处理时延和计算资源占用量，进而提高数据处理效率。
提供了一种数据处理子系统，包括：中断处理模块和数据处理模块，中断处理模块与数据处理模块通信连接，其中：
中断处理模块设置为向数据处理模块发送多个待处理数据，并在确定接收到目标数据处理指示指令的情况下，生成中断指令，其中，目标数据处理指示指令用于指示所述多个待处理数据中的最后一个待处理数据处理完成；
数据处理模块设置为接收多个待处理数据，按照多个待处理数据的接收顺序依次对多个待处理数据进行数据处理，并在每个待处理数据处理完成后，向中断处理模块发送每个待处理数据对应的数据处理指示指令。
还提供了一种数据处理系统，包括：
任意实施例所提供的数据处理子系统，还包括通信处理器、中央处理器CPU和数据存储模块，其中：
通信处理器与数据存储模块通信连接，通信处理器设置为向数据存储模块 发送多个待处理数据；
数据存储模块还与数据处理子系统和CPU通信连接，数据存储模块设置为存储多个待处理数据；
CPU与数据处理子系统通信连接，CPU设置为接收数据处理子系统发送的通信数据，或CPU设置为向数据存储模块发送多个待处理数据，其中，通信数据为数据处理子系统对多个待处理数据进行数据处理后得到的数据。
还提供了一种数据处理方法，应用于数据处理模块，包括：
接收多个待处理数据；
按照多个待处理数据的接收顺序依次对多个待处理数据进行数据处理；
在每个待处理数据处理完成后，生成每个待处理数据对应的数据处理指示指令；
其中，数据处理指示指令包括目标数据处理指示指令，目标数据处理指示指令用于指示生成中断指令。
还提供了一种电子设备，包括：
一个或多个处理器；
存储装置，设置为存储一个或多个程序；
当一个或多个程序被一个或多个处理器执行，使得一个或多个处理器实现本申请任意实施例所提供的数据处理方法。
还提供了一种计算机存储介质，存储有计算机程序，该计算机程序被处理器执行时实现本申请任意实施例所提供的数据处理方法。
附图说明
图1是本申请实施例一提供的一种数据处理子系统的示意图；
图2是本申请实施例一提供的一种数据处理模块的通信连接的示例图；
图3是本申请实施例二提供的一种数据处理系统的示意图；
图4是本申请实施例二提供的一种一次中断对应的待处理数据的配置结果的示意图；
图5为本申请实施例三提供的一种数据处理方法的流程图；
图6为本申请实施例四提供的一种电子设备的结构示意图。
具体实施方式
下面结合附图和实施例对本申请进行说明。此处所描述的实施例仅仅用于解释本申请，而非对本申请的限定。
附图中仅示出了与本申请相关的部分而非全部内容。一些示例性实施例被描述成作为流程图描绘的处理或方法。虽然流程图将多项操作(或步骤)描述成顺序的处理，但是其中的许多操作可以被并行地、并发地或者同时实施。此外，多项操作的顺序可以被重新安排。当其操作完成时所述处理可以被终止，但是还可以具有未包括在附图中的附加步骤。所述处理可以对应于方法、函数、规程、子例程和子程序等等。
实施例一
图1是本申请实施例一提供的一种数据处理子系统的示意图，本实施例可适用于处理多个待处理数据后产生一次中断的情况。如图1所示，该数据处理子系统100，包括：中断处理模块110和数据处理模块120，所述中断处理模块110与所述数据处理模块120通信连接，其中：中断处理模块110设置为向数据处理模块120发送多个待处理数据，并在确定接收到目标数据处理指示指令的情况下，生成中断指令。数据处理模块120设置为接收多个待处理数据，按照多个待处理数据的接收顺序依次对多个待处理数据进行数据处理，并在每个待处理数据处理完成后，向中断处理模块110发送每个待处理数据对应的数据处理指示指令。其中，目标数据处理指示指令用于指示末次待处理数据处理完成。目标数据处理指示指令用于指示所述多个待处理数据中的最后一个待处理数据处理完成。
待处理数据可以是数据处理模块120需要处理的数据，示例性的，待处理数据可以包括待签名处理的数据或待验签处理的数据，其中，待签名处理的数据可以是需要做签名处理的数据，待验签处理的数据可以是需要做验签处理的数据。在一实施例中，需要做验签处理的数据可以包括公钥以及待验签数据。待验签数据可以是来自发送方的经过签名处理得到的数据。需要做签名处理的数据可以包括私钥、签名者信息以及待签名数据。待签名数据可以是需要进行签名处理但是还未进行签名处理的原始数据。示例性的，待签名数据可以包括 电子文件、转账数据或者车辆位置数据等，本申请实施例对待签名数据的数据内容和类型不做限定。签名者信息可以是能够证明签名者身份的信息，例如签名者信息可以包括签名者身份证号或者签名者电话号码等。中断指令可以是用于指示生成中断操作的指令。在本申请实施例中，一个中断指令可以对应多个待处理数据的处理过程。数据处理指示指令可以是数据处理模块120发送的一种数据指令，数据处理指示指令可以用于指示待处理数据处理完成。每一个数据处理指示指令可以用来指示对应的待处理数据已完成处理。末次待处理数据可以是数据处理模块120接收到的最后一个待处理数据。目标数据处理指示指令可以是数据处理模块120在最后一个待处理数据处理完成时发送的数据处理指示指令。
中断处理模块110可以将多个待处理数据依次发送至数据处理模块120，数据处理模块120按照待处理数据的接收顺序依次对待处理数据进行数据处理。例如，数据处理模块120将接收到的第一个待处理数据进行处理，并在该待处理数据处理完成后，向中断处理模块110发送该待处理数据对应的数据处理指示指令，即指示该待处理数据已完成处理。中断处理模块110在收到第一个待处理数据对应的数据处理指示指令后，向数据处理模块120发送第二个待处理数据，数据处理模块120在完成第二个待处理数据对应的数据处理后向中断处理模块110发送第二个待处理数据的数据处理指示指令，以此类推。数据处理模块120在最后一个待处理数据处理完成时向中断处理模块110发送目标数据处理指示指令，即指示最后一个待处理数据处理完成，中断处理模块110在接收到目标数据处理指示指令后生成中断指令。
在一个例子中，当车辆在发送自身已完成签名处理的数据的同时又要对多个其他车辆发送的已完成签名处理的数据进行验签处理时，相关技术会每次针对一条数据进行数据处理并产生一次中断，这将导致相关技术不能满足车辆通信领域对数据处理效率以及数据传输效率的要求。而本申请实施例提供的数据处理子系统100可以实现针对多次数据处理只产生一个中断指令，这将有效降低数据处理时延。如果接收到的已经完成签名处理的数据包括车辆位置信息，通过本申请实施例提供的数据处理子系统100可以使得车辆位置信息能够被路侧设备以及周边车辆及时接收处理，有效降低车辆事故发生率。
在本申请的一个可选实施例中，数据处理模块120是设置为对待处理数据进行签名处理和/或验签处理。
签名处理可以为对待签名处理的数据进行数据处理。例如，对待签名处理的数据进行摘要计算，得到待签名处理数据的摘要，通过私钥对待签名处理数据的摘要进行签名计算。验签处理可以为对待验签处理的数据进行验签处理。 例如，通过验签算法对待验签处理的数据进行摘要计算，得到待验签处理数据的摘要，通过公钥对待验签处理数据的摘要进行验签计算。
在本申请实施例中，数据处理模块120对接收到的待验签处理的数据进行验签处理，还可以对接收到的待签名处理的数据进行签名处理。如果待验签处理的数据进行验签处理后，验签通过，则证明接收到的信息的完整性以及不可否认性，否则证明接收到的信息被篡改。
可选的，数据处理模块120支持基于椭圆曲线数字签名算法(Elliptic Curve Digital Signature Algorithm，ECDSA)以及国密非对称加密算法(SM2)的签名和验签运算；支持安全散列算法2(Secure Hash Algorithm 2，SHA2)和摘要算法(SM3)的哈希计算功能；支持高级加密标准(Advanced Encryption Standard，AES)以及国密对称加密算法(SM4)等加密运算功能。
在本申请的一个可选实施例中，中断处理模块110可以包括配置参数存储模块；配置参数存储模块设置为存储多个待处理数据的配置参数；中断处理模块110设置为根据配置参数向数据处理模块120发送多个待处理数据。
配置参数可以用于对待处理数据进行配置。例如，可以确定待处理数据的源地址信息和目的地址信息等。
中断处理模块110可以根据配置参数存储模块中存储的待处理数据的配置参数读取待处理数据，并将待处理数据发送至数据处理模块120。中断处理模块110每次向数据处理模块120发送一个待处理数据，经过多次的待处理数据的传输，最终实现向数据处理模块120发送多个待处理数据。
在本申请的一个可选实施例中，配置参数可以包括源端配置参数和目的端配置参数；源端配置参数可以包括源端地址和多个源端对应目的端的寄存器数量；目的端配置参数可以包括目的端地址和多个目的端对应的数据长度。
源端配置参数可以是发送待处理数据端的相关参数，目的端配置参数可以是接收待处理数据端的相关参数。中断处理模块110根据源端配置参数可以读取待处理数据，根据目的端配置参数可以将待处理数据发送至数据处理模块120。源端地址可以是待处理数据所在内存地址，中断处理模块110根据源端配置参数中的源端地址进行待处理数据的读取。目的端地址可以是待处理数据在数据处理模块120中的内存地址。源端对应目的端的寄存器数量可以是待处理数据在数据处理模块120所占用的寄存器数量，用于对数据处理模块120的寄存器进行配置。目的端对应的数据长度可以为待处理数据占用的字节数。
中断处理模块110根据源端地址读取待处理数据后，根据目的端地址将待处理数据发送至数据处理模块120相应的用于存储待处理数据的寄存器中。
示例性的，中断处理模块110需要向数据处理模块120传输2个待处理数据，即源端对应目的端的寄存器数量为2。如果每个待处理数据占用1个字节，则目的端对应的数据长度为2个字节。因为一个中断指令对应多个待处理数据的处理过程，所以每条中断指令对应的待处理数据的源端地址、目的端地址、寄存器个数以及所占字节数可能不同。中断处理模块110在读取和发送待处理数据之前，需要对源端地址、多个源端对应目的端的寄存器数量、目的端地址以及多个目的端对应的数据长度进行配置。
图2是本申请实施例一提供的一种数据处理模块的通信连接的示例图，如图2所示，数据处理模块120可以包括数据处理单元121、数据处理结果寄存器122和数据状态寄存器123，数据处理单元121与中断处理模块110通信连接，其中：数据处理单元121设置为接收中断处理模块110根据配置参数发送的多个待处理数据并进行数据处理，得到数据处理结果；数据处理结果寄存器122与数据处理单元121通信连接，数据处理结果寄存器122设置为接收并存储数据处理结果；数据状态寄存器123与数据处理单元121通信连接，数据状态寄存器123设置为在确定数据处理单元121得到数据处理结果后，更新多个待处理数据的数据处理状态。
示例性的，中断处理模块110将一个需要做验签处理的数据发送至数据处理单元121，数据处理单元121将接收到的需要做验签处理的数据进行存储以及验签处理。数据处理结果寄存器122接收并存储数据处理单元121发送的验签处理后的数据。在数据处理单元121发出该验签处理后的数据的同时，数据状态寄存器123更新该需要做验签处理的数据的数据处理状态为完成状态。如果需要做验签处理的数据还未进行验签处理，则未进行验签处理的需要做验签处理的数据对应的数据处理状态为待处理状态。
在本申请的一个可选实施例中，中断处理模块110还可以设置为：针对每个待处理数据生成数据处理标识；数据处理标识用于指示数据处理模块120开始进行数据处理。
数据处理标识可以是一种数据标识，例如，数据处理标识可以是一种标志位，该标志位可以设置于每个待处理数据之后。
示例性的，标志位即数据处理标识可以添加于每个待处理数据的最后，当数据处理模块120读取到待处理数据的标志位后开始进行数据处理。
本申请实施例通过中断处理模块将多个待处理数据发送至数据处理模块，以使数据处理模块按照待处理数据的接收顺序依次对待处理数据进行数据处理，并在每个待处理数据处理完成后，向中断处理模块发送每个待处理数据对应的数据处理指示指令。中断处理模块接收到目标数据处理指示指令时，生成 中断指令，以指示批量待处理数据处理完成，解决了数据处理过程中存在的数据传输效率低、时延长且占用过多计算资源等问题，提高了数据处理过程中的数据传输效率，降低了数据处理时延和计算资源占用量，进而提高了数据处理效率。
实施例二
图3是本申请实施例二提供的一种数据处理系统的示意图，如图3所示，数据处理系统包括本申请任意实施例中的数据处理子系统100，还包括通信处理器130、中央处理器(Central Processing Unit，CPU)140和数据存储模块150，其中：通信处理器130与数据存储模块150通信连接，通信处理器130设置为向数据存储模块150发送多个待处理数据；数据存储模块150还与数据处理子系统100和CPU140通信连接，数据存储模块150设置为存储多个待处理数据；CPU140与数据处理子系统100通信连接，CPU140设置为接收数据处理子系统100发送的通信数据，或CPU140设置为向数据存储模块150发送多个待处理数据，其中，通信数据为数据处理子系统100对多个待处理数据进行数据处理后得到的数据。
通信数据可以包括对待验签处理的数据进行数据处理后得到的数据。
数据存储模块150接收并存储通信处理器130发送的多个待验签处理的数据。中断处理模块110读取数据存储模块150所存储的多个待验签处理的数据，并将待验签处理的数据发送至数据处理模块120，数据处理模块120对接收到的待验签处理的数据进行验签处理，在将多个待验签处理的数据处理完成后，由中断处理模块110生成中断指令。CPU140根据中断指令产生中断为下一次多个待验签处理的数据处理或者其他程序调用做准备。当有至少一个待签名处理的数据需要进行签名处理时，CPU140将待签名处理的数据发送至数据存储模块150，数据处理子系统100读取数据存储模块150所存储的待签名处理的数据并进行签名处理。可选的，数据存储模块150可以集成于数据处理模块120中。
图4是本申请实施例二提供的一种一次中断对应的待处理数据的配置结果的示意图，如图3和图4所示，黑色区域代表数据存储模块150的内存空间，白色区域代表数据处理模块120的内存空间，中断处理模块110将待处理数据从数据存储模块150的内存空间读取之后发送至数据处理模块120的数据处理单元121中。其中，数据存储模块150所存储的多个待处理数据均具有数据处理标识。
中断处理模块110还设置为将数据处理结果寄存器122中的数据处理结果 和数据状态寄存器123中的数据处理状态发送至数据存储模块150。
示例性的，数据处理单元121根据数据处理标识开始对第一个待处理数据进行数据处理，在完成对第一个待处理数据的处理后，数据处理模块120将对应的数据处理结果存储在数据处理结果寄存器122的内存空间中，并将该待处理数据对应的数据处理状态存储在数据状态寄存器123的内存空间中，同时数据处理模块120向中断处理模块110发送数据处理指示指令。中断处理模块110将数据处理结果发送至数据存储模块150的数据处理结果存放区，并将数据处理状态发送至数据存储模块150的数据状态存放区。中断处理模块110接收到第一个待处理数据对应的数据处理指示指令后，将第二个待处理数据发送至数据处理单元121。数据处理单元121进行第二次数据处理，并将数据处理结果和数据处理状态分别发送至数据处理结果寄存器122和数据状态寄存器123。同时数据处理模块120向中断处理模块110发送数据处理指示指令。中断处理模块110将数据处理结果以及数据处理状态分别发送至数据处理结果存放区和数据状态存放区。中断处理模块110接收到第二个待处理数据对应的数据处理指示指令后，将第三个待处理数据发送至数据处理单元121。以此类推，数据处理子系统100可以完成N个待处理数据的处理。多个待处理数据处理完成后，CPU140根据中断处理模块110发出的中断指令产生中断。
在本申请的一个可选实施例中，如图3所示，数据处理系统还可以包括射频接口160，射频接口160与通信处理器130通信连接，射频接口160设置为接收原始待处理数据，并将原始待处理数据发送至通信处理器130；通信处理器130设置为对原始待处理数据进行数据预处理，生成待处理数据。
原始待处理数据可以是原始的未经过任何数据处理的数据。示例性的，原始待处理数据可以包括射频接口160接收的未经过数据预处理的待验签处理的数据。射频接口160可以包括无线前端与基带数字并行(Radiofrontend-Baseband Digital Parallel，RBDP)接口或者标准/非标准高速接口等。数据预处理可以包括对原始待处理数据或者对已完成签名处理的数据进行数据处理。
示例性的，射频接口160接收未经过数据预处理的需要做验签处理的数据，并将未经过数据预处理的需要做验签处理的数据发送至通信处理器130，通信处理器130将接收到的未经过数据预处理的需要做验签处理的数据进行译码、加速以及解包等处理。通信处理器130还可以将已完成签名处理的数据进行编码、加速以及打包等处理，并将数据预处理后所得数据发送至射频接口160，由射频接口160将数据发送给其他设备进行验签处理。
在本申请的一个可选实施例中，如图3所示，CPU140还可以设置为在数据处理子系统100进行数据处理之前，对数据存储模块150进行配置参数初始化 处理。
配置参数初始化处理可以包括对数据存储模块150所存储的待处理数据对应的内存单元的初始化，例如待处理数据的起始地址、目的地址、所占内存空间以及内存单元字节数的设置。
如图3所示，在数据处理子系统100进行数据处理之前，CPU140为数据存储模块150开辟内存空间，并根据待处理数据对应的起始地址、目的地址以及内存单元字节数进行待处理数据的存储。CPU140还可以根据中断处理模块110发送的中断指令进行响应即产生中断。CPU140还可以对其它设备的数据请求进行应答，例如，向发送数据请求的设备进行应答。其中，应答请求可以是设备A对设备B的数据请求的应答。例如，设备B需要设备A的位置信息，设备B对设备A发送位置信息请求，设备A对该请求做出应答即向设备B发送自身位置信息或者不响应请求。另外，CPU140可以判断是否进行待验签处理的数据的验签处理和/或待签名处理的数据的签名处理并进行相应程序的调度等，例如，CPU140可以判断是否进行待验签数据的验签处理和/或待签名数据的签名处理并进行相应程序的调度等。
本申请实施例在通过数据存储模块接收并存储通信处理器发送的待处理数据后，数据处理子系统对待处理数据进行处理，并将通信数据发送至CPU。同时CPU也可以发送待处理数据至数据存储模块，数据处理子系统对待处理数据进行处理并将处理后的数据发送至通信处理器。本实施例实现了数据处理子系统与CPU，以及数据处理子系统与通信处理器的双向通信，并且数据处理子系统可以实现对多个待处理数据完成数据处理后仅产生一次中断指令，解决了数据处理过程中的计算机资源占用过多的问题，提高了数据处理效率，降低了数据传输时延和计算机占用量。
实施例三
图5为本申请实施例三提供的一种数据处理方法的流程图，本实施例可适用于高速签名/验签的场景，该方法可以由数据处理模块来执行，该模块可以由软件和/或硬件方式来实现，并可集成在电子设备中，如图5所示，该方法包括如下操作。
S310、接收多个待处理数据。
S320、按照多个待处理数据的接收顺序依次对多个待处理数据进行数据处理。
S330、在每个待处理数据处理完成后，生成每个待处理数据对应的数据处 理指示指令。
数据处理指示指令包括目标数据处理指示指令，目标数据处理指示指令用于指示生成中断指令。
可选的，所述按照所述多个待处理数据的接收顺序依次对所述多个待处理数据进行数据处理，包括：按照所述多个待处理数据的接收顺序依次对所述多个待处理数据进行签名处理和/或验签处理。
可选的，在接收多个待处理数据之前，还包括：通过中断处理模块的配置参数存储模块存储所述多个待处理数据的配置参数；通过中断处理模块根据所述配置参数向所述数据处理模块发送多个待处理数据。
可选的，所述配置参数包括源端配置参数和目的端配置参数；所述源端配置参数包括源端地址和多个源端对应目的端的寄存器数量；所述目的端配置参数包括目的端地址和多个目的端对应的数据长度。
可选的，所述数据处理模块包括数据处理单元、数据处理结果寄存器和数据状态寄存器，所述数据处理单元与所述中断处理模块通信连接，所述按照所述多个待处理数据的接收顺序依次对所述多个待处理数据进行数据处理，还包括：通过数据处理单元接收所述中断处理模块根据所述配置参数发送的所述多个待处理数据并进行数据处理，得到数据处理结果；通过数据处理结果寄存器接收并存储所述数据处理结果；在确定所述数据处理单元得到所述数据处理结果后，通过数据状态寄存器更新所述多个待处理数据的数据处理状态。
可选的，在接收多个待处理数据之后，还包括：针对每个待处理数据生成数据处理标识；所述数据处理标识用于指示所述数据处理模块开始进行数据处理。
可选的，在所述接收多个待处理数据之前，还包括：通过通信处理器向数据存储模块发送所述多个待处理数据；通过数据存储模块存储所述多个待处理数据；通过CPU接收通信数据，或通过CPU向所述数据存储模块发送所述多个待处理数据，其中，所述通信数据为对所述多个待处理数据进行数据处理后得到的数据。
可选的，在所述接收多个待处理数据之前，还包括：通过射频接口接收原始待处理数据，并将所述原始待处理数据发送至所述通信处理器；所述通信处理器设置为对所述原始待处理数据进行数据预处理，生成所述待处理数据。
可选的，在所述按照多个待处理数据的接收顺序依次对多个待处理数据进行数据处理之前，还包括：通过CPU对所述数据存储模块进行配置参数初始化处理。
可选的，还包括：通过所述中断处理模块将数据处理结果寄存器中的数据处理结果和数据状态寄存器中的数据处理状态发送至所述数据存储模块。
本申请实施例通过中断处理模块将多个待处理数据发送至数据处理模块，以使数据处理模块按照多个待处理数据的接收顺序依次对多个待处理数据进行数据处理，并在每个待处理数据处理完成后，向中断处理模块发送每个待处理数据对应的数据处理指示指令。中断处理模块接收到目标数据处理指示指令时，生成中断指令，以指示批量待处理数据处理完成，解决了数据处理过程中存在的数据传输效率低、时延长且占用过多计算资源等问题，提高了数据处理过程中的数据传输效率，降低了数据处理时延和计算资源占用量，进而提高了数据处理效率。
实施例四
图6为本申请实施例四提供的一种电子设备的结构示意图。图6示出了适于用来实现本申请实施方式的电子设备412的框图。图6显示的电子设备412仅仅是一个示例，不应对本申请实施例的功能和使用范围带来任何限制。
如图6所示，电子设备412以通用计算设备的形式表现。电子设备412的组件可以包括：一个或者多个处理器416，存储装置428，连接不同系统组件(包括存储装置428和处理器416)的总线418。
总线418表示几类总线结构中的一种或多种，包括存储器总线或者存储器控制器，外围总线，图形加速端口，处理器或者使用多种总线结构中的任意总线结构的局域总线。举例来说，这些体系结构包括工业标准体系结构(Industry Standard Architecture，ISA)总线，微通道体系结构(Micro Channel Architecture，MCA)总线，增强型ISA总线、视频电子标准协会(Video Electronics Standards Association，VESA)局域总线以及外围组件互连(Peripheral Component Interconnect，PCI)总线。
电子设备412包括多种计算机系统可读介质。这些介质可以是任何能够被电子设备412访问的可用介质，包括易失性和非易失性介质，可移动的和不可移动的介质。
存储装置428可以包括易失性存储器形式的计算机系统可读介质，例如随机存取存储器(Random Access Memory，RAM)430和/或高速缓存432。电子设备412可以包括其它可移动/不可移动的、易失性/非易失性计算机系统存储介质。仅作为举例，存储系统434可以设置为读写不可移动的、非易失性磁介质(图6未显示，通常称为“硬盘驱动器”)。尽管图6中未示出，可以提供用 于对可移动非易失性磁盘(例如“软盘”)读写的磁盘驱动器，以及对可移动非易失性光盘(例如便携式紧凑磁盘只读存储器(Compact Disc-Read Only Memory，CD-ROM)、数字视盘(Digital Video Disc-Read Only Memory，DVD-ROM)或者其它光介质)读写的光盘驱动器。在这些情况下，每个驱动器可以通过一个或者多个数据介质接口与总线418相连。存储装置428可以包括至少一个程序产品，该程序产品具有一组(例如至少一个)程序模块，这些程序模块被配置以执行本申请多个实施例的功能。
具有一组(至少一个)程序模块426的程序436，可以存储在例如存储装置428中，这样的程序模块426包括操作系统、一个或者多个应用程序、其它程序模块以及程序数据，这些示例中的每一个或一种组合中可能包括网络环境的实现。程序模块426通常执行本申请所描述的实施例中的功能和/或方法。
电子设备412也可以与一个或多个外部设备414(例如键盘、指向设备、摄像头和显示器424等)通信，还可与一个或者多个使得用户能与该电子设备412交互的设备通信，和/或与使得该电子设备412能与一个或多个其它计算设备进行通信的任何设备(例如网卡和调制解调器等等)通信。这种通信可以通过输入/输出(Input/Output，I/O)接口422进行。并且，电子设备412还可以通过网络适配器420与一个或者多个网络(例如局域网(Local Area Network，LAN)，广域网(Wide Area Network，WAN)和/或公共网络，例如因特网)通信。如图6所示，网络适配器420通过总线418与电子设备412的其它模块通信。尽管图中未示出，可以结合电子设备412使用其它硬件和/或软件模块，包括：微代码、设备驱动器、冗余处理单元、外部磁盘驱动阵列、磁盘阵列(Redundant Arrays of Independent Disks，RAID)系统、磁带驱动器以及数据备份存储系统等。
处理器416通过运行存储在存储装置428中的程序，从而执行多种功能应用以及数据处理，例如实现本申请上述实施例所提供的数据处理方法，包括：接收多个待处理数据；按照所述多个待处理数据的接收顺序依次对所述多个待处理数据进行数据处理；在每个待处理数据处理完成后，生成每个待处理数据对应的数据处理指示指令；其中，所述数据处理指示指令包括目标数据处理指示指令，所述目标数据处理指示指令用于指示生成中断指令。
本申请实施例通过中断处理模块将多个待处理数据发送至数据处理模块，以使数据处理模块按照待处理数据的接收顺序依次对待处理数据进行数据处理，并在每个待处理数据处理完成后，向中断处理模块发送每个待处理数据对应的数据处理指示指令。中断处理模块接收到目标数据处理指示指令时，生成中断指令，以指示批量待处理数据处理完成，解决了数据处理过程中存在的数据传输效率低、时延长且占用过多计算资源等问题，提高了数据处理过程中的 数据传输效率，降低了数据处理时延和计算资源占用量，进而提高了数据处理效率。
实施例五
本申请实施例五还提供一种存储计算机程序的计算机存储介质，所述计算机程序在由计算机处理器执行时用于执行本申请上述实施例任一所述的数据处理方法，包括：接收多个待处理数据；按照所述多个待处理数据的接收顺序依次对所述多个待处理数据进行数据处理；在每个待处理数据处理完成后，生成每个待处理数据对应的数据处理指示指令；其中，所述数据处理指示指令包括目标数据处理指示指令，所述目标数据处理指示指令用于指示生成中断指令。
本申请实施例的计算机存储介质，可以采用一个或多个计算机可读的介质的任意组合。计算机可读介质可以是计算机可读信号介质或者计算机可读存储介质。计算机可读存储介质例如可以是电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。计算机可读存储介质包括：具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、RAM、只读存储器(Read Only Memory，ROM)、可擦式可编程只读存储器(Erasable Programmable Read Only Memory，EPROM)或闪存、光纤、CD-ROM、光存储器件、磁存储器件、或者上述的任意合适的组合。在本文件中，计算机可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。
计算机可读的信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了计算机可读的程序代码。这种传播的数据信号可以采用多种形式，包括电磁信号、光信号或上述的任意合适的组合。计算机可读的信号介质还可以是计算机可读存储介质以外的任何计算机可读介质，该计算机可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。
计算机可读介质上包含的程序代码可以用任何适当的介质传输，包括无线、电线、光缆、射频(Radio Frequency，RF)等等，或者上述的任意合适的组合。
可以以一种或多种程序设计语言或其组合来编写用于执行本申请操作的计算机程序代码，所述程序设计语言包括面向对象的程序设计语言—诸如Java、Smalltalk、C++，还包括常规的过程式程序设计语言，诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算机上执行、部分地在用户计算机上执行、作为一个独立的软件包执行、部分在用户计算机上部分在远程计算 机上执行、或者完全在远程计算机或服务器上执行。在涉及远程计算机的情形中，远程计算机可以通过任意种类的网络，包括LAN或WAN连接到用户计算机，或者，可以连接到外部计算机(例如利用因特网服务提供商来通过因特网连接)。

Claims (13)

  1. 一种数据处理子系统，包括中断处理模块和数据处理模块，所述中断处理模块与所述数据处理模块通信连接，其中：
    所述中断处理模块设置为向所述数据处理模块发送多个待处理数据，并在确定接收到目标数据处理指示指令的情况下，生成中断指令，其中，所述目标数据处理指示指令用于指示所述多个待处理数据中的最后一个待处理数据处理完成；
    所述数据处理模块设置为接收所述多个待处理数据，按照所述多个待处理数据的接收顺序依次对所述多个待处理数据进行数据处理，并在每个待处理数据处理完成后，向所述中断处理模块发送每个待处理数据对应的数据处理指示指令。
  2. 根据权利要求1所述的系统，其中，所述数据处理模块是设置为对待处理数据进行以下至少之一：签名处理、或验签处理。
  3. 根据权利要求1所述的系统，其中，所述中断处理模块包括配置参数存储模块；
    所述配置参数存储模块设置为存储所述多个待处理数据的配置参数；
    所述中断处理模块设置为根据所述配置参数向所述数据处理模块发送所述多个待处理数据。
  4. 根据权利要求3所述的系统，其中，所述配置参数包括源端配置参数和目的端配置参数；
    所述源端配置参数包括源端地址和多个源端对应目的端的寄存器数量；
    所述目的端配置参数包括目的端地址和多个目的端对应的数据长度。
  5. 根据权利要求3所述的系统，其中，所述数据处理模块包括数据处理单元、数据处理结果寄存器和数据状态寄存器，所述数据处理单元与所述中断处理模块通信连接，其中：
    所述数据处理单元设置为接收所述中断处理模块根据所述配置参数发送的所述多个待处理数据并进行数据处理，得到数据处理结果；
    所述数据处理结果寄存器与所述数据处理单元通信连接，所述数据处理结果寄存器设置为接收并存储所述数据处理结果；
    所述数据状态寄存器与所述数据处理单元通信连接，所述数据状态寄存器设置为在确定所述数据处理单元得到所述数据处理结果后，更新所述多个待处理数据的数据处理状态。
  6. 根据权利要求1所述的系统，其中，所述中断处理模块还设置为：
    针对每个待处理数据生成数据处理标识；所述数据处理标识用于指示所述数据处理模块开始进行数据处理。
  7. 一种数据处理系统，包括权利要求1-6中任一项所述的数据处理子系统，还包括通信处理器、中央处理器CPU和数据存储模块，其中：
    所述通信处理器与所述数据存储模块通信连接，所述通信处理器设置为向所述数据存储模块发送所述多个待处理数据；
    所述数据存储模块还与所述数据处理子系统和所述CPU通信连接，所述数据存储模块设置为存储所述多个待处理数据；
    所述CPU与所述数据处理子系统通信连接，所述CPU设置为接收所述数据处理子系统发送的通信数据，或所述CPU设置为向所述数据存储模块发送所述多个待处理数据，其中，所述通信数据为所述数据处理子系统对所述多个待处理数据进行数据处理后得到的数据。
  8. 根据权利要求7所述的系统，还包括射频接口，所述射频接口与所述通信处理器通信连接，所述射频接口设置为接收原始待处理数据，并将所述原始待处理数据发送至所述通信处理器；
    所述通信处理器设置为对所述原始待处理数据进行数据预处理，生成所述多个待处理数据。
  9. 根据权利要求7所述的系统，其中，所述CPU还设置为在所述数据处理子系统进行数据处理之前，对所述数据存储模块进行配置参数初始化处理。
  10. 根据权利要求7所述的系统，所述中断处理模块还设置为将数据处理结果寄存器中的数据处理结果和数据状态寄存器中的数据处理状态发送至所述数据存储模块。
  11. 一种数据处理方法，应用于数据处理模块，包括：
    接收多个待处理数据；
    按照所述多个待处理数据的接收顺序依次对所述多个待处理数据进行数据处理；
    在每个待处理数据处理完成后，生成每个待处理数据对应的数据处理指示指令；
    其中，所述数据处理指示指令包括目标数据处理指示指令，所述目标数据处理指示指令用于指示生成中断指令。
  12. 一种电子设备，包括：
    一个或多个处理器；
    存储装置，设置为存储一个或多个程序；
    所述一个或多个程序被所述一个或多个处理器执行，使得所述一个或多个处理器实现如权利要求11所述的数据处理方法。
  13. 一种计算机存储介质，存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求11所述的数据处理方法。
PCT/CN2020/133230 2020-11-06 2020-12-02 数据处理系统、方法、电子设备及存储介质 WO2022095179A1 (zh)

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