WO2022095162A1 - Method for manufacturing power semiconductor device having split-gate structure - Google Patents

Method for manufacturing power semiconductor device having split-gate structure Download PDF

Info

Publication number
WO2022095162A1
WO2022095162A1 PCT/CN2020/132106 CN2020132106W WO2022095162A1 WO 2022095162 A1 WO2022095162 A1 WO 2022095162A1 CN 2020132106 W CN2020132106 W CN 2020132106W WO 2022095162 A1 WO2022095162 A1 WO 2022095162A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
trench
shield plate
plate element
epitaxial layer
Prior art date
Application number
PCT/CN2020/132106
Other languages
French (fr)
Inventor
Zhi He
Paolo ORGANTINI
Mahmoud Shehab Mohammad Al-Sa'di
Alessandro MONTAGNA
Junjie AN
Original Assignee
Wuxi Xichanweixin Semiconductor Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuxi Xichanweixin Semiconductor Ltd. filed Critical Wuxi Xichanweixin Semiconductor Ltd.
Publication of WO2022095162A1 publication Critical patent/WO2022095162A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

Definitions

  • the present invention relates to a method for manufacturing a power semiconductor device, in particular a field-plate trench power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device.
  • a field-plate trench power MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • Field plate or shielded-gate (or split-gate) trench (or vertical) power MOSFET devices are known, wherein the gate conductive material, generally polysilicon, in a gate trench is separated into a plurality of portions: one or more top portions formed at a channel region and acting as the control gate; and one or more bottom portions, formed at a drift region and capacitively shielding the top gate portion from the drain region.
  • the gate conductive material generally polysilicon
  • split-gate trench power MOSFET devices such as breakdown voltage BV DS , on-state resistance R ON , max drain current I DMAX and gate charge Q gd , Q gs are strongly dependent on the split-gate bias conditions, which determine a modulation of the electric potential in the drift region; generally, proper biasing of the split-gate top and bottom portions allows to optimize switching performances of the power MOSFET device.
  • Figure 1 shows a known and exemplary split-gate trench power MOSFET device 1, as disclosed e.g. in Kyoung II Na et al., “Electrical Characteristics of Triple-Gate RSO Power MOSFET (TGRMOS) with Various Gate Configurations and Bias Conditions” , ETRI Journal, Volume 35, Number 3, June 2013; the power MOSFET device 1 has in this case a gate split in three portions, two separated top portions and one bottom portion.
  • TGRMOS Gate Configurations and Bias Conditions
  • the power MOSFET device 1 comprises a substrate 2 of a heavily doped semiconductor material (for example, of an N + type) , and an epitaxial layer 3 formed on the substrate 2, the epitaxial layer 3 being made of semiconductor material with the same type of conductivity as the substrate 2 and with lighter doping (in the example, of N - type) .
  • a heavily doped semiconductor material for example, of an N + type
  • an epitaxial layer 3 formed on the substrate 2
  • the epitaxial layer 3 being made of semiconductor material with the same type of conductivity as the substrate 2 and with lighter doping (in the example, of N - type) .
  • cells 5 of the power MOSFET device 1 are formed, each comprising a body well 6 having a conductivity opposite to that of the epitaxial layer 3 (in the example, of a P type) , and a source region 8, within the body well 6, having the same type of conductivity as the substrate 2 (in the example, of an N + type) .
  • the portion of the epitaxial layer 3 beneath the body well 6 represents a drift region for the power MOSFET device 1.
  • the power MOSFET device 1 further comprises a split-gate structure 10 formed in a deep trench 12 extending vertically through the epitaxial layer 3, in the portion of the same epitaxial layer 3 laterally arranged between body wells 6 and source regions 8 belonging to adjacent cells 5.
  • the split-gate structure 10 comprises: a bottom gate portion 13, acting as a shield or field plate, arranged in a lower part of the trench 12, centrally thereto and extending at a lower level than the body wells 6; and, in the example, two separated top gate portions 14a, 14b arranged in a top part of the trench 12, at the same level as the body well 6, laterally to respective source regions 8.
  • the bottom gate portion 12 is separated from the trench inner surface via a dielectric stack 15 formed by silicon oxide (SiO 2 ) , silicon nitride (SiN x ) and Tetraethyl orthosilicate (TEOS) deposition; the top gate portions 14a, 14b are separated one from the other and moreover from the trench inner surface via a dielectric region 15', in particular made of silicon oxide.
  • a dielectric stack 15 formed by silicon oxide (SiO 2 ) , silicon nitride (SiN x ) and Tetraethyl orthosilicate (TEOS) deposition; the top gate portions 14a, 14b are separated one from the other and moreover from the trench inner surface via a dielectric region 15', in particular made of silicon oxide.
  • the power MOSFET device 1 further comprises: a body/source metallization 16, formed on the epitaxial layer 3, separated from the top gate portions 14a, 14b by a top portion of the dielectric region 15' and contacting the source regions 8 and moreover the body regions 6 via a body contact 17, i.e. a highly doped region (of a P + type) of the body well 6 arranged at the surface of the epitaxial layer 3; and a drain electrode 18 formed at the back of the substrate 2, contacting the same substrate 2.
  • a gate electrode arrangement here not shown, is provided to contact the split-gate structure 10 (the top gate portions 14a, 14b and the bottom gate portion 13 thereof) .
  • the substrate 2 acts as the drain for the power MOSFET device 1, and the epitaxial layer 3 represents a surface extension thereof.
  • the channel of each cell 5 is constituted by the portion of the corresponding body well 6 arranged laterally to the top gate portions 14a, 14b, and is delimited by the junction between the source region 8 and the body well 6 on the one hand, and by the junction between the body well 6 and the drift region, on the other hand.
  • the gate electrode arrangement is capacitively coupled to the channel for modulating the type of conductivity thereof.
  • an appropriate voltage to the gate electrode arrangement, it is possible to cause an inversion of the conductivity of the channel and thus create a conductive path for the majority charge-carriers between the source region 8 and the substrate 2, through the channel and the drift region.
  • the resulting current flow is affected by the resistance of the channel and drift regions.
  • biasing of the split-gate structure 10 determines a modulation of the electric potential in the drift region allowing to optimize switching performances of the power device.
  • a top surface, here denoted with 3a, of the epitaxial layer 3 is etched in order to form the deep trench 12, extending vertically to the same top surface 3a.
  • the dielectric stack 15 of silicon oxide (SiO 2 ) , silicon nitride (SiN x ) and Tetraethyl orthosilicate (TEOS) is deposited above the top surface 3a of the epitaxial layer 3 and inside the trench 12, coating the internal walls thereof.
  • the first conductive layer 20 and the dielectric stack 15 are etched-back.
  • the first conductive layer 20 is etched back to remove it from the top surface 3a of the epitaxial layer 3 and leave a trench portion 20' thereof within the trench 12, having a top end at the level of the top surface 3a of the epitaxial layer 3 (so called “MESA level” ) ; and the dielectric stack 15 is etched back to channel length, i.e. for a depth in the trench 12, below the top surface 3a, corresponding to a desired length for the channel of the power MOSFET device 1.
  • the process then comprises, Figure 2E, a specific step of thermal oxidation (in particular, via steam oxidation) of the upper part of the trench portion 20' (having side walls not covered by the dielectric stack 14) , which is completely oxidized in order to form a separation region 19 (for separation of the top gate portions 14a, 14b of the split-gate structure 10, in a subsequent step of the manufacturing process) .
  • the above oxidation also defines the bottom gate portion 13 of the same split-gate structure 10 (which corresponds to the remaining part of the trench portion 20') and forms gate oxide regions 15' of the power MOSFET device 1 at the side walls of the upper portion of the trench 12.
  • a second conductive layer 22, of a conductive material, in particular polysilicon, is deposited above the top surface 3a of the epitaxial layer 3, defining within the upper portion of the trench 12 the top gate portions 14a, 14b of the split-gate structure 10, separated by the above discussed separation region 19.
  • the manufacturing process then continues with standard steps of implantation and metallization, in order to form (see also previous Figure 1) the body regions 6, the source regions 8, the body contacts 16 and the drain, source and gate metallizations (in particular, the body/source metallization 16 and the drain electrode 18) .
  • the gate oxide is formed concurrently to the step of thermal oxidation of the upper part of the trench portion 20' of the first conductive layer 20. Since the characteristics of the gate oxide (in particular its thickness) determine the desired performance of the power MOSFET device 1, it follows that the height and the width of the trench portion 20', which are dependent on the gate oxide thickness (based on the different oxidation rates of silicon and polysilicon) , cannot exceed a certain value; otherwise, the same trench portion 20' is not fully oxidized and the desired separation between the top gate portions 14a, 14b of the split-gate structure 10 cannot be guaranteed.
  • the aim of the present invention is consequently to provide a manufacturing method allowing to solve the above discussed issues afflicting known manufacturing processes.
  • a method for manufacturing a power semiconductor device is consequently provided.
  • FIG. 1 is a cross-sectional view of a known split-gate trench power MOSFET device
  • FIGS. 2A-2F are cross-sectional views of the known power MOSFET device in subsequent steps of a corresponding manufacturing process.
  • FIGS. 3A-3K are cross-sectional views of a power MOSFET device in subsequent steps of a manufacturing process, according to an embodiment of the present solution.
  • FIG. 3A refers, for sake of simplicity, to an exemplary unit cell of the device (it is clear, however, that what is shown and discussed applies to all cells of the power MOSFET device) .
  • an epitaxial layer 23 has already been formed on a substrate 22 of a heavily doped semiconductor material (in the example, of an N + type) ; the epitaxial layer 23 is made of semiconductor material with the same type of conductivity as the substrate 22 and with lighter doping (in the example, of an N - type) .
  • the epitaxial layer 23 can be a single epitaxial layer or multiple epitaxial layers.
  • a screen oxide layer 24 has been grown by wet oxidation on a top surface 23a of the epitaxial layer 23, followed by LPCVD deposition of a nitride layer 25, overlying the same screen oxide layer 24.
  • a thick oxide layer 27 is thermally grown on the inner surface of the deep trench 26, followed by deposition above the top surface 23a of the epitaxial layer 23 of a highly doped N-type shield (or field-plate) polysilicon layer 28.
  • the shield polysilicon layer 28 fills completely the deep trench 26, being arranged internally to the thick oxide layer 27.
  • the thick oxide layer could be a thermal oxide layer, a CVD oxide layer (CVD: Chemical Vapour Deposition) or a combination of both.
  • the surface of the shield polysilicon layer 28 is planarized by a CMP process and etched-back to the desired depth, to leave a shield plate (or field plate) element 28' extending vertically inside the deep trench 26, centrally thereto.
  • the level of the etched-back shield polysilicon layer 28 (i.e. the top level of the upper portion of the shield plate element 28') can be controlled to be: at the same level as the top surface 23a of the epitaxial layer 23 (as shown in Figure 3C) , or, in a manner here not shown, at a level lower than the top surface 23a of the epitaxial layer 23; in any case, the etched-back shield polysilicon layer 28 is etched back to a level not higher than the top surface 23a.
  • a single top gate portion or two separated top gate portions can be defined in the split-gate structure of the power MOSFET device.
  • the screen oxide layer 24 and the nitride layer 25 are removed by a wet etching process.
  • the thick oxide layer 27 in the deep trench 26 is wet etched to a desired depth below the level of the top surface 23a of the epitaxial layer 23 to allow forming of the top gate portions of the split gate structure of the power MOSFET device in later processing steps (as will be discussed in the following) ; the desired depth will correspond to the channel length of the power semiconductor device.
  • the upper portion of the shield plate element 28' (protruding from the underlying thick oxide layer 27) is then oxidized, in the example partially oxidized, using a wet oxidation process to form a sacrificial oxide ( “SacOx” ) region 29 coating a remaining portion of the same upper portion of the shield plate element 28'; it is noted, however, that the sacrificial oxidation may cause complete oxidation of the upper portion of the shield plate element 28'.
  • a sacrificial oxide “SacOx”
  • the sacrificial oxide region 29 also grows on the internal walls of the deep trench 26, at the top of the same deep trench 26 (it is noted that the sacrificial oxide growth is faster in the polysilicon of the upper portion of the shield plate element 28' than in the silicon of the epitaxial layer 23) .
  • the grown sacrificial oxide region 29 is then wet etched to completely remove it from the internal walls of the deep trench 26 and, in the shown example, from the remaining portion of the upper portion of the shield plate element 28'.
  • this step reduces the thickness (or width) of the upper portion of the shield plate element 28' (in a direction parallel to the top surface 23a) before the subsequent gate oxidation step, ensuring that a complete oxidation of the same upper portion later occurs (in other words, this step assures that a critical lower thickness of the upper portion of the shield plate element 28' is in any case reached, allowing complete oxidation thereof in the following processing steps) .
  • a gate insulating film, of a desired (or target) thickness is formed using a dry oxidation process.
  • a gate oxide region 30 grows on the internal surface of the deep trench 26, at the top of the same deep trench 26; the remaining upper portion of the shield plate element 28' is fully oxidized during the dry oxidation process, so as to define a dielectric separation region 31, at the top of an underlying shield plate 32 (constituted by the remaining bottom portion of the above defined shield plate element 28') .
  • the upper portion of the shield plate element 28' may already be fully oxidized during the sacrificial oxidation proces s; in this case, the dry oxidation process contributes to definition of the dielectric separation region 31.
  • the steps of growing and then removal of the sacrificial oxide thus assure complete oxidation of the upper portion of the shield plate element 28', independently from the gate film thickness (i.e. the thickness of the gate oxide region 30 can be controlled in a separate and independent manner) .
  • the gate N-type polysilicon is then deposited in the empty upper portion of the deep trench 26.
  • a N-type doped gate polysilicon layer is deposited above the epitaxial layer 23, in particular filling the upper part of the deep trench 26.
  • the gate polysilicon layer is then planarized by a CMP process and etched-back to the desired depth, as shown in Figure 3H, in particular until it is recessed to a level slightly below the top surface 23a of the epitaxial layer 23, so as to form top gate portions 34 of the split-gate structure, here denoted with 36 (further comprising the above discussed shield plate 32) .
  • the top gate portions 34 are arranged laterally to the dielectric separation region 31, in this case being dielectrically separated by the same dielectric separation region 31, and are arranged at the side of the gate oxide region 30.
  • Oxidation of the top gate portions 34 of the split-gate structure 36 is then performed, as shown in Figure 3I, forming top oxide regions 38 on the same top gate portions 34.
  • body regions 40 are formed in the epitaxial layer 23, laterally to the top gate portions 34 of the split-gate structure 36, from which the same body regions 40 are separated by the gate oxide regions 30.
  • Source regions 42, with N + type doping, are formed in the body regions 40, at the top surface 23a of the epitaxial layer 23.
  • a dielectric layer 44 is deposited above the top surface 23a of the epitaxial layer 23.
  • the same dielectric layer 44, and an underlying portion of the source regions 42, are then etched to form contact openings 45, through which body contacts 46 are then formed in the body regions 40.
  • Drain, source and gate metallizations are subsequently formed, in a per se known manner, here not shown in detail.
  • the height and width of the upper portion of the shield plate element 28', as well as the thickness of the sacrificial oxide region 29 can be controlled to achieve two connected top gate portions 34 (i.e. with the upper portion of the shield plate element 28' and later formed dielectric separation region 31 made to be lower than the top surface 23a of the epitaxial layer 23, the so called MESA level) or two separated top gate portions 34 (i.e. with the upper portion of the shield plate element 28' and later formed dielectric separation region 31 made to be at the same level as the top surface 23a of the epitaxial layer 23) .
  • the gate oxide thickness (i.e. the thickness of the gate oxide region 30) can be controlled to the target thickness regardless of the thickness of the upper portion of the shield plate element 28'; this approach provides an additional degree of freedom for designing the split-gate trench power MOSFET device, according to the requirements of the specific applications.
  • the step of etching back of the shield polysilicon layer 28 does not represent a critical step, since separation of the top gate portions 34 of the split-gate structure 36 is later assured by the subsequent steps of the manufacturing process (in particular, by the complete oxidation of the upper portion of the shield plate element 28', remaining after sacrificial oxide deposition and removal thereof) . Accordingly, etch back of the shield polysilicon layer 28 can be made at a level not higher than the top surface 23a of the epitaxial layer 23, so that it is assured that no portion of the gate polysilicon layer later remains on the same top surface 23a.
  • the proposed solution allows to achieve low gate-source charge Qgs field-plate trench power semiconductor devices.
  • a single top gate portion can be achieved (instead of two separated top gate portions, as in the embodiment shown) simply by adjusting the level of the upper portion of the shield plate element 28' and later formed dielectric separation region 31 to be lower than the top surface 23a of the epitaxial layer 23.
  • the disclosed manufacturing process can be used for the manufacturing of other semiconductor power devices, such as IGBT devices, where the emitter-gate charge can be reduced.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method for manufacturing a power semiconductor device having a split-gate structure (36) provides: forming a single epitaxial layer or multiple epitaxial layers (23) on a substrate (22); forming a trench (26) through the epitaxial layer (23) extending from a top surface (23a) thereof in a vertical direction, transverse to the top surface (23a); filling the trench (26) with a dielectric region (27) and a conductive shield plate element (28'), the shield plate element (28') comprising an upper portion protruding from the underlying dielectric region (27) and a bottom potion extending vertically internally to the dielectric region (27); oxidizing the upper portion of the shield plate element (28') to form a separation region (31) in the trench (26) at the top surface (23a) of the epitaxial layer (23), a bottom portion of the shield plate element (28') defining a bottom part of the split-gate structure (36) of the power semiconductor device; forming a gate oxide region (30) on an inner surface of the trench (26), at an upper part of the same trench (26), above the dielectric region (27); forming top gate portions (34) of the split-gate structure (36), filling the trench (26) at the top surface (23a) of the epitaxial layer (23), laterally to the separation region (31). Before forming the gate-oxide region (30), the method provides forming a sacrificial oxide region (29) starting from the upper portion of the shield plate element (28') and subsequently etching the sacrificial oxide region (29).

Description

[Title established by the ISA under Rule 37.2] METHOD FOR MANUFACTURING POWER SEMICONDUCTOR DEVICE HAVING SPLIT-GATE STRUCTURE TECHNICAL FIELD
The present invention relates to a method for manufacturing a power semiconductor device, in particular a field-plate trench power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device.
BACKGROUND ART
Field plate or shielded-gate (or split-gate) trench (or vertical) power MOSFET devices are known, wherein the gate conductive material, generally polysilicon, in a gate trench is separated into a plurality of portions: one or more top portions formed at a channel region and acting as the control gate; and one or more bottom portions, formed at a drift region and capacitively shielding the top gate portion from the drain region.
The electrical characteristics of split-gate trench power MOSFET devices, such as breakdown voltage BV DS, on-state resistance R ON, max drain current I DMAX and gate charge Q gd, Q gs are strongly dependent on the split-gate bias conditions, which determine a modulation of the electric potential in the drift region; generally, proper biasing of the split-gate top and bottom portions allows to optimize switching performances of the power MOSFET device.
Figure 1 shows a known and exemplary split-gate trench power MOSFET device 1, as disclosed e.g. in Kyoung II Na et al., “Electrical Characteristics of Triple-Gate RSO Power MOSFET (TGRMOS) with Various Gate Configurations and Bias Conditions” , ETRI Journal, Volume 35, Number 3, June 2013; the power MOSFET device 1 has in this case a gate split in three portions, two separated top portions and one bottom  portion.
The power MOSFET device 1 comprises a substrate 2 of a heavily doped semiconductor material (for example, of an N + type) , and an epitaxial layer 3 formed on the substrate 2, the epitaxial layer 3 being made of semiconductor material with the same type of conductivity as the substrate 2 and with lighter doping (in the example, of N - type) .
Within a surface portion of the epitaxial layer 3, cells 5 of the power MOSFET device 1 are formed, each comprising a body well 6 having a conductivity opposite to that of the epitaxial layer 3 (in the example, of a P type) , and a source region 8, within the body well 6, having the same type of conductivity as the substrate 2 (in the example, of an N + type) . The portion of the epitaxial layer 3 beneath the body well 6 represents a drift region for the power MOSFET device 1.
The power MOSFET device 1 further comprises a split-gate structure 10 formed in a deep trench 12 extending vertically through the epitaxial layer 3, in the portion of the same epitaxial layer 3 laterally arranged between body wells 6 and source regions 8 belonging to adjacent cells 5.
The split-gate structure 10 comprises: a bottom gate portion 13, acting as a shield or field plate, arranged in a lower part of the trench 12, centrally thereto and extending at a lower level than the body wells 6; and, in the example, two separated  top gate portions  14a, 14b arranged in a top part of the trench 12, at the same level as the body well 6, laterally to respective source regions 8.
The bottom gate portion 12 is separated from the trench inner surface via a dielectric stack 15 formed by silicon oxide (SiO 2) , silicon nitride (SiN x) and Tetraethyl orthosilicate (TEOS) deposition; the  top gate portions  14a,  14b are separated one from the other and moreover from the trench inner surface via a dielectric region 15', in particular made of silicon oxide.
The power MOSFET device 1 further comprises: a body/source metallization 16, formed on the epitaxial layer 3, separated from the  top gate portions  14a, 14b by a top portion of the dielectric region 15' and contacting the source regions 8 and moreover the body regions 6 via a body contact 17, i.e. a highly doped region (of a P + type) of the body well 6 arranged at the surface of the epitaxial layer 3; and a drain electrode 18 formed at the back of the substrate 2, contacting the same substrate 2. A gate electrode arrangement, here not shown, is provided to contact the split-gate structure 10 (the  top gate portions  14a, 14b and the bottom gate portion 13 thereof) .
The substrate 2 acts as the drain for the power MOSFET device 1, and the epitaxial layer 3 represents a surface extension thereof. The channel of each cell 5 is constituted by the portion of the corresponding body well 6 arranged laterally to the  top gate portions  14a, 14b, and is delimited by the junction between the source region 8 and the body well 6 on the one hand, and by the junction between the body well 6 and the drift region, on the other hand.
The gate electrode arrangement is capacitively coupled to the channel for modulating the type of conductivity thereof. In particular, via the application of an appropriate voltage to the gate electrode arrangement, it is possible to cause an inversion of the conductivity of the channel and thus create a conductive path for the majority charge-carriers between the source region 8 and the substrate 2, through the channel and the drift region. The resulting current flow is affected by the resistance of  the channel and drift regions.
As previously discussed, biasing of the split-gate structure 10 determines a modulation of the electric potential in the drift region allowing to optimize switching performances of the power device.
A known manufacturing process for the power MOSFET device 1 is now discussed with reference to Figures 2A-2F, with particular focus on the formation of the split-gate structure 10.
As shown in Figure 2A, a top surface, here denoted with 3a, of the epitaxial layer 3 is etched in order to form the deep trench 12, extending vertically to the same top surface 3a.
Subsequently, as shown in Figure 2B, the dielectric stack 15 of silicon oxide (SiO 2) , silicon nitride (SiN x) and Tetraethyl orthosilicate (TEOS) is deposited above the top surface 3a of the epitaxial layer 3 and inside the trench 12, coating the internal walls thereof.
A first conductive layer 20, of a conductive material, in particular polysilicon, is then formed, as shown in Figure 2C, above the epitaxial layer 3 and inside the trench 12, completely filling the same trench 12 (internally with respect to the dielectric stack 15) .
Afterwards, as shown in Figure 2D, the first conductive layer 20 and the dielectric stack 15 are etched-back. In particular, the first conductive layer 20 is etched back to remove it from the top surface 3a of the epitaxial layer 3 and leave a trench portion 20' thereof within the trench 12, having a top end at the level of the top surface 3a of the epitaxial layer 3 (so called “MESA level” ) ; and the dielectric stack 15 is etched back to channel length, i.e. for a depth in the trench 12, below the top surface 3a, corresponding to a desired length for  the channel of the power MOSFET device 1.
The process then comprises, Figure 2E, a specific step of thermal oxidation (in particular, via steam oxidation) of the upper part of the trench portion 20' (having side walls not covered by the dielectric stack 14) , which is completely oxidized in order to form a separation region 19 (for separation of the  top gate portions  14a, 14b of the split-gate structure 10, in a subsequent step of the manufacturing process) . The above oxidation also defines the bottom gate portion 13 of the same split-gate structure 10 (which corresponds to the remaining part of the trench portion 20') and forms gate oxide regions 15' of the power MOSFET device 1 at the side walls of the upper portion of the trench 12.
Subsequently, as shown in Figure 2F, a second conductive layer 22, of a conductive material, in particular polysilicon, is deposited above the top surface 3a of the epitaxial layer 3, defining within the upper portion of the trench 12 the  top gate portions  14a, 14b of the split-gate structure 10, separated by the above discussed separation region 19.
In a manner not shown here in detail, the manufacturing process then continues with standard steps of implantation and metallization, in order to form (see also previous Figure 1) the body regions 6, the source regions 8, the body contacts 16 and the drain, source and gate metallizations (in particular, the body/source metallization 16 and the drain electrode 18) .
The present Applicant has realized that the above-discussed known manufacturing process, although generally satisfactory, has some issues.
In particular, as previously discussed (see Figure 2E) , the gate oxide is formed concurrently to the step of  thermal oxidation of the upper part of the trench portion 20' of the first conductive layer 20. Since the characteristics of the gate oxide (in particular its thickness) determine the desired performance of the power MOSFET device 1, it follows that the height and the width of the trench portion 20', which are dependent on the gate oxide thickness (based on the different oxidation rates of silicon and polysilicon) , cannot exceed a certain value; otherwise, the same trench portion 20' is not fully oxidized and the desired separation between the  top gate portions  14a, 14b of the split-gate structure 10 cannot be guaranteed.
It follows that the characteristics of the gate oxide and of the above trench portion 20', and consequently also of the bottom gate portion 13 of the split-gate structure 10 cannot be controlled independently.
Moreover, during etching back of the first conductive layer 20 (see Figure 2D) , assuring a desired height for the remaining trench portion 20' may prove to be difficult, particularly so if a CMP (Chemical Mechanical Polishing) is implemented. If the trench portion 20' has a resulting height that is lower than the top surface 3a of the epitaxial layer 3 (i.e. the MESA level) , the separation between the top gate portions 14 of the split-gate structure 10 may not be guaranteed. Conversely, if the same trench portion 20' has a resulting height that is higher than the top surface 3a of the epitaxial layer 3, an unwanted portion of the first conductive layer 20 may remain on the same top surface 3a of the epitaxial layer 3, again contrary to what would be desired.
DISCLOSURE OF INVENTION
The aim of the present invention is consequently to  provide a manufacturing method allowing to solve the above discussed issues afflicting known manufacturing processes.
According to the present invention, a method for manufacturing a power semiconductor device is consequently provided.
BRIEF DESCRIPTION OF THE DRAWINGS
For a better understanding of the present invention, preferred embodiments thereof are now described purely by way of non-limiting example and with reference to the attached drawings, wherein:
- Figure 1 is a cross-sectional view of a known split-gate trench power MOSFET device;
- Figures 2A-2F are cross-sectional views of the known power MOSFET device in subsequent steps of a corresponding manufacturing process; and
- Figures 3A-3K are cross-sectional views of a power MOSFET device in subsequent steps of a manufacturing process, according to an embodiment of the present solution.
BEST MODE FOR CARRYING OUT THE INVENTION
A method for manufacturing a power semiconductor device, in particular a power MOSFET device, is now discussed starting from Figure 3A, which refers, for sake of simplicity, to an exemplary unit cell of the device (it is clear, however, that what is shown and discussed applies to all cells of the power MOSFET device) .
As shown in Figure 3A, an epitaxial layer 23 has already been formed on a substrate 22 of a heavily doped semiconductor material (in the example, of an N + type) ; the epitaxial layer 23 is made of semiconductor material with the same type of conductivity as the substrate 22 and with lighter doping (in the example, of an N - type) . Besides,  according to the present invention, the epitaxial layer 23 can be a single epitaxial layer or multiple epitaxial layers.
A screen oxide layer 24 has been grown by wet oxidation on a top surface 23a of the epitaxial layer 23, followed by LPCVD deposition of a nitride layer 25, overlying the same screen oxide layer 24.
Next, a deep trench 26, with the intended depth in the vertical direction (transverse to the top surface 23a of the epitaxial layer 23) , has been formed by silicon etching starting from the same top surface 23a.
Then, as shown in Figure 3B, a thick oxide layer 27 is thermally grown on the inner surface of the deep trench 26, followed by deposition above the top surface 23a of the epitaxial layer 23 of a highly doped N-type shield (or field-plate) polysilicon layer 28. In particular, the shield polysilicon layer 28 fills completely the deep trench 26, being arranged internally to the thick oxide layer 27. Besides, the thick oxide layer could be a thermal oxide layer, a CVD oxide layer (CVD: Chemical Vapour Deposition) or a combination of both.
As shown in Figure 3C, the surface of the shield polysilicon layer 28 is planarized by a CMP process and etched-back to the desired depth, to leave a shield plate (or field plate) element 28' extending vertically inside the deep trench 26, centrally thereto.
In particular, the level of the etched-back shield polysilicon layer 28 (i.e. the top level of the upper portion of the shield plate element 28') can be controlled to be: at the same level as the top surface 23a of the epitaxial layer 23 (as shown in Figure 3C) , or, in a manner here not shown, at a level lower than the top surface 23a of the epitaxial layer 23; in any case, the etched-back  shield polysilicon layer 28 is etched back to a level not higher than the top surface 23a.
As will be also discussed in the following, depending on the level of the etched-back shield polysilicon layer 28, a single top gate portion or two separated top gate portions can be defined in the split-gate structure of the power MOSFET device.
Afterwards, as shown in Figure 3D, the screen oxide layer 24 and the nitride layer 25 are removed by a wet etching process.
Next, the thick oxide layer 27 in the deep trench 26 is wet etched to a desired depth below the level of the top surface 23a of the epitaxial layer 23 to allow forming of the top gate portions of the split gate structure of the power MOSFET device in later processing steps (as will be discussed in the following) ; the desired depth will correspond to the channel length of the power semiconductor device.
According to a particular aspect of the present solution, as shown in Figure 3E, the upper portion of the shield plate element 28' (protruding from the underlying thick oxide layer 27) is then oxidized, in the example partially oxidized, using a wet oxidation process to form a sacrificial oxide ( “SacOx” ) region 29 coating a remaining portion of the same upper portion of the shield plate element 28'; it is noted, however, that the sacrificial oxidation may cause complete oxidation of the upper portion of the shield plate element 28'.
The sacrificial oxide region 29 also grows on the internal walls of the deep trench 26, at the top of the same deep trench 26 (it is noted that the sacrificial oxide growth is faster in the polysilicon of the upper portion of the shield plate element 28' than in the silicon of the  epitaxial layer 23) .
As shown in Figure 3F, the grown sacrificial oxide region 29 is then wet etched to completely remove it from the internal walls of the deep trench 26 and, in the shown example, from the remaining portion of the upper portion of the shield plate element 28'.
It is noted that this step reduces the thickness (or width) of the upper portion of the shield plate element 28' (in a direction parallel to the top surface 23a) before the subsequent gate oxidation step, ensuring that a complete oxidation of the same upper portion later occurs (in other words, this step assures that a critical lower thickness of the upper portion of the shield plate element 28' is in any case reached, allowing complete oxidation thereof in the following processing steps) . Next, as shown in Figure 3G, a gate insulating film, of a desired (or target) thickness, is formed using a dry oxidation process. In particular, a gate oxide region 30 grows on the internal surface of the deep trench 26, at the top of the same deep trench 26; the remaining upper portion of the shield plate element 28' is fully oxidized during the dry oxidation process, so as to define a dielectric separation region 31, at the top of an underlying shield plate 32 (constituted by the remaining bottom portion of the above defined shield plate element 28') .
It is noted that, as previously discussed, the upper portion of the shield plate element 28' may already be fully oxidized during the sacrificial oxidation proces s; in this case, the dry oxidation process contributes to definition of the dielectric separation region 31.
Advantageously, the steps of growing and then removal of the sacrificial oxide thus assure complete oxidation of the upper portion of the shield plate element 28',  independently from the gate film thickness (i.e. the thickness of the gate oxide region 30 can be controlled in a separate and independent manner) .
The gate N-type polysilicon is then deposited in the empty upper portion of the deep trench 26. A N-type doped gate polysilicon layer is deposited above the epitaxial layer 23, in particular filling the upper part of the deep trench 26. The gate polysilicon layer is then planarized by a CMP process and etched-back to the desired depth, as shown in Figure 3H, in particular until it is recessed to a level slightly below the top surface 23a of the epitaxial layer 23, so as to form top gate portions 34 of the split-gate structure, here denoted with 36 (further comprising the above discussed shield plate 32) . In particular, the top gate portions 34 are arranged laterally to the dielectric separation region 31, in this case being dielectrically separated by the same dielectric separation region 31, and are arranged at the side of the gate oxide region 30.
Oxidation of the top gate portions 34 of the split-gate structure 36 is then performed, as shown in Figure 3I, forming top oxide regions 38 on the same top gate portions 34.
The process then continues with standard steps for completing the manufacturing of the power MOSFET device, in particular, as shown in Figure 3J, with steps of source and channel implantation.
In particular, body regions 40 are formed in the epitaxial layer 23, laterally to the top gate portions 34 of the split-gate structure 36, from which the same body regions 40 are separated by the gate oxide regions 30. Source regions 42, with N + type doping, are formed in the body regions 40, at the top surface 23a of the epitaxial  layer 23.
Subsequently, as shown in Figure 3K, a dielectric layer 44 is deposited above the top surface 23a of the epitaxial layer 23. The same dielectric layer 44, and an underlying portion of the source regions 42, are then etched to form contact openings 45, through which body contacts 46 are then formed in the body regions 40.
Drain, source and gate metallizations are subsequently formed, in a per se known manner, here not shown in detail.
The advantages of the proposed solution are clear from the foregoing description.
In particular, it is again underlined that the height and width of the upper portion of the shield plate element 28', as well as the thickness of the sacrificial oxide region 29 (see Figures 3D and 3E) , can be controlled to achieve two connected top gate portions 34 (i.e. with the upper portion of the shield plate element 28' and later formed dielectric separation region 31 made to be lower than the top surface 23a of the epitaxial layer 23, the so called MESA level) or two separated top gate portions 34 (i.e. with the upper portion of the shield plate element 28' and later formed dielectric separation region 31 made to be at the same level as the top surface 23a of the epitaxial layer 23) .
Moreover, the gate oxide thickness (i.e. the thickness of the gate oxide region 30) can be controlled to the target thickness regardless of the thickness of the upper portion of the shield plate element 28'; this approach provides an additional degree of freedom for designing the split-gate trench power MOSFET device, according to the requirements of the specific applications.
Additionally, in the discussed manufacturing method, contrary to prior art solutions, the step of etching back  of the shield polysilicon layer 28 (to define the top level of the upper portion of the shield plate element 28') does not represent a critical step, since separation of the top gate portions 34 of the split-gate structure 36 is later assured by the subsequent steps of the manufacturing process (in particular, by the complete oxidation of the upper portion of the shield plate element 28', remaining after sacrificial oxide deposition and removal thereof) . Accordingly, etch back of the shield polysilicon layer 28 can be made at a level not higher than the top surface 23a of the epitaxial layer 23, so that it is assured that no portion of the gate polysilicon layer later remains on the same top surface 23a.
In general, the proposed solution allows to achieve low gate-source charge Qgs field-plate trench power semiconductor devices.
Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present invention, as defined in the annexed claims.
In particular, it is again underlined that with the same manufacturing method, a single top gate portion can be achieved (instead of two separated top gate portions, as in the embodiment shown) simply by adjusting the level of the upper portion of the shield plate element 28' and later formed dielectric separation region 31 to be lower than the top surface 23a of the epitaxial layer 23.
Moreover, it is underlined that the disclosed manufacturing process can be used for the manufacturing of other semiconductor power devices, such as IGBT devices, where the emitter-gate charge can be reduced.

Claims (16)

  1. A method for manufacturing a power semiconductor device having a split-gate structure (36) , the semiconductor material using in this power semiconductor device includes but is not limit to Si, SiC, GaN, diomand and Ga 2O 3, comprising:
    forming a single epitaxial layer or multiple epitaxial layers (23) on a substrate (22) ;
    forming a trench (26) through the epitaxial layer (23) extending from a top surface (23a) thereof in a vertical direction, transverse to the top surface (23a) ;
    filling the trench (26) with a dielectric region (27) and a conductive shield plate element (28') , the shield plate element (28') comprising an upper portion protruding from the underlying dielectric region (27) and a bottom potion extending vertically internally to the dielectric region (27) ;
    oxidizing the upper portion of the shield plate element (28') to form a separation region (31) at the top surface (23a) of the epitaxial layer (23) , a bottom portion of the shield plate element (28') defining a bottom part of the split-gate structure (36) of the power semiconductor device;
    forming a gate oxide region (30) on an inner surface of the trench (26) , at an upper part of the same trench (26) , above the dielectric region (27) ,
    forming top gate portions (34) of the split-gate structure (36) , filling the trench (26) at the top surface (23a) of the epitaxial layer (23) , laterally to the separation region (31) ,
    characterized by comprising, before forming the gate-oxide region (30) , forming a sacrificial oxide region (29) starting from the upper portion of the shield plate element  (28') and subsequently etching said sacrificial oxide region (29) .
  2. The method according to claim 1, wherein the step of forming a sacrificial oxide region (29) completely oxidizes the upper portion of the shield plate element (28') .
  3. The method according to claim 1, wherein the step of forming a sacrificial oxide region (29) includes partially oxidizing the upper portion of the shield plate element (28') , and the step of etching said sacrificial oxide region (29) includes reducing a thickness of the upper portion of the shield plate element (28') so that it is fully oxidized during subsequent oxidation.
  4. The method according to claim 3, wherein etching said sacrificial oxide region (29) includes removing the grown sacrificial oxide region (29) from the upper portion of the shield plate element (28') to leave a remaining part of the upper portion of the shield plate element (28') protruding from the underlying dielectric region (27) .
  5. The method according to claim 3 or 4, wherein reducing a thickness of the upper portion of the shield plate element (28') comprises reaching a critical lower thickness of the upper portion of the shield plate element (28') , allowing complete oxidation thereof during the subsequent oxidation.
  6. The method according to any of the preceding claims, wherein forming the gate oxide region (30) is concurrent to completely oxidizing the upper portion of the shield plate element (28') to form the separation region (31) .
  7. The method according to any of the preceding claims, wherein forming a sacrificial oxide region (29) uses a wet oxidation process; subsequently etching the sacrificial oxide region (29) uses a wet etching process; and forming  the gate-oxide region (30) and oxidizing the upper portion of the shield plate element (28') use a dry oxidation process.
  8. The method according to any of the preceding claims, wherein filling the trench (26) with a dielectric region (27) and a conductive shield plate element (28') comprises:
    growing an oxide layer (27) on an inner surface of the trench (26) ;
    depositing a shield polysilicon layer (28) above the top surface (23a) of the epitaxial layer (23) , filling the deep trench (26) , internally to the oxide layer (27) ;
    etching-back the shield polysilicon layer (28) to leave the shield plate element (28') extending vertically inside the trench (26) ; and
    etching-back the oxide layer (27) in the trench (26) to a desired depth below the level of the top surface (23a) of the epitaxial layer (23) leaving an upper part of the trench (26) empty, the desired depth corresponding to a channel length of the power semiconductor device.
  9. The method according to claim 8, wherein the level of the etched-back shield polysilicon layer (28) is controlled to be at a level not higher than the top surface (23a) of the epitaxial layer (23) .
  10. The method according to claim 8 or 9, wherein the level of the etched-back shield polysilicon layer (28) is controlled to be at a same level as the top surface (23a) of the epitaxial layer (23) .
  11. The method according to claim 8 or 9, wherein the level of the etched-back shield polysilicon layer (28) is controlled to be at a lower level than the top surface (23a) of the epitaxial layer (23) .
  12. The method according to any of the preceding claims, wherein forming the top gate portions (34) of the  split-gate structure (36) comprises:
    depositing a gate polysilicon layer (33) above the top surface (23a) of the epitaxial layer (23) , filling an upper part of the deep trench (26) , above the dielectric region (27) ;
    etching back the gate polysilicon layer (33) until it is recessed to a level below the top surface (23a) of the epitaxial layer (23) , so as to form the top gate portions (34) of the split-gate structure (36) , arranged laterally to the separation region (31) .
  13. The method according to claim 12, wherein the top gate portions (34) of the split-gate structure (36) are dielectrically separated by the separation region (31) .
  14. The method according to any of the preceding claims, wherein the power semiconductor device is a field-plate trench power MOSFET device.
  15. The method according to claim 14, wherein the substrate (22) is made of a heavily doped semiconductor material and the epitaxial layer (23) has a same first type of conductivity as the substrate (22) and with a lighter doping; further comprising:
    forming body regions (40) in the epitaxial layer (23) , having a second conductivity type, opposite to the first conductivity type, laterally to the top gate portions (34) of the split-gate structure (36) , separated from the top gate portions (34) by gate oxide regions (30) ;
    forming source regions (42) , with the first conductivity type, in the body regions (40) , at the top surface (23a) of the epitaxial layer (23) .
  16. The method according to claim 15, further comprising:
    depositing a dielectric layer (44) includes but is not limit to TEOS, HTO, BPSG, PSG, NSG and USG above the top  surface (23a) of the epitaxial layer (23) ; and
    etching the dielectric layer (44) and an underlying portion of the source regions (42) to form contact openings (45) , through which body contacts (46) are then formed in the body regions (40) .
PCT/CN2020/132106 2020-11-05 2020-11-27 Method for manufacturing power semiconductor device having split-gate structure WO2022095162A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011223885.3A CN114446791A (en) 2020-11-05 2020-11-05 Method for manufacturing power semiconductor device with split gate structure
CN202011223885.3 2020-11-05

Publications (1)

Publication Number Publication Date
WO2022095162A1 true WO2022095162A1 (en) 2022-05-12

Family

ID=81361370

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/132106 WO2022095162A1 (en) 2020-11-05 2020-11-27 Method for manufacturing power semiconductor device having split-gate structure

Country Status (2)

Country Link
CN (1) CN114446791A (en)
WO (1) WO2022095162A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115566074A (en) * 2022-12-06 2023-01-03 无锡新洁能股份有限公司 Shielded gate power device with silicon dioxide buried layer and manufacturing method thereof
CN117276330A (en) * 2023-11-22 2023-12-22 华羿微电子股份有限公司 Shielded gate MOSFET device structure and preparation method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118335778A (en) * 2024-06-11 2024-07-12 深圳市港祥辉电子有限公司 Diamond SGT device and preparation method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110070720A1 (en) * 2009-09-18 2011-03-24 Elpida Memory, Inc. Method of manufacturing semiconductor device
CN105118775A (en) * 2015-08-18 2015-12-02 上海华虹宏力半导体制造有限公司 A shield grid transistor formation method
US9281368B1 (en) * 2014-12-12 2016-03-08 Alpha And Omega Semiconductor Incorporated Split-gate trench power MOSFET with protected shield oxide
CN105742185A (en) * 2016-02-23 2016-07-06 深圳尚阳通科技有限公司 Shielding grid power device and fabrication method thereof
CN108010847A (en) * 2017-11-30 2018-05-08 上海华虹宏力半导体制造有限公司 Shield grid groove MOSFET and its manufacture method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110070720A1 (en) * 2009-09-18 2011-03-24 Elpida Memory, Inc. Method of manufacturing semiconductor device
US9281368B1 (en) * 2014-12-12 2016-03-08 Alpha And Omega Semiconductor Incorporated Split-gate trench power MOSFET with protected shield oxide
CN105118775A (en) * 2015-08-18 2015-12-02 上海华虹宏力半导体制造有限公司 A shield grid transistor formation method
CN105742185A (en) * 2016-02-23 2016-07-06 深圳尚阳通科技有限公司 Shielding grid power device and fabrication method thereof
CN108010847A (en) * 2017-11-30 2018-05-08 上海华虹宏力半导体制造有限公司 Shield grid groove MOSFET and its manufacture method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115566074A (en) * 2022-12-06 2023-01-03 无锡新洁能股份有限公司 Shielded gate power device with silicon dioxide buried layer and manufacturing method thereof
CN117276330A (en) * 2023-11-22 2023-12-22 华羿微电子股份有限公司 Shielded gate MOSFET device structure and preparation method
CN117276330B (en) * 2023-11-22 2024-02-13 华羿微电子股份有限公司 Shielded gate MOSFET device structure and preparation method

Also Published As

Publication number Publication date
CN114446791A (en) 2022-05-06

Similar Documents

Publication Publication Date Title
WO2022095162A1 (en) Method for manufacturing power semiconductor device having split-gate structure
US7301200B2 (en) Trench FET with self aligned source and contact
US6921697B2 (en) Method for making trench MIS device with reduced gate-to-drain capacitance
US9306018B2 (en) Trench shielding structure for semiconductor device and method
US7998808B2 (en) Semiconductor device fabrication using spacers
US20130153995A1 (en) Semiconductor device and method for manufacturing the same
US6921699B2 (en) Method for manufacturing a semiconductor device with a trench termination
US7842574B2 (en) Method of manufacturing a semiconductor power device
US7494876B1 (en) Trench-gated MIS device having thick polysilicon insulation layer at trench bottom and method of fabricating the same
US20070063272A1 (en) Semiconductor power device with insulated gate formed in a trench, and manufacturing process thereof
CN111092123A (en) Lateral double-diffused transistor and manufacturing method thereof
US20240339533A1 (en) Gate electrode extending into a shallow trench isolation structure in high voltage devices
JP3965027B2 (en) Method for manufacturing trench gate type MIS device having thick polysilicon insulating layer at bottom of trench
CN112582463B (en) Power semiconductor device and method for manufacturing the same
CN111180510B (en) Semiconductor power device structure and manufacturing method thereof
US20230100307A1 (en) Method for manufacturing trench-gate mosfet
CN113809148B (en) Power element and manufacturing method thereof
EP4300550A1 (en) Semiconductor device having split gate structure and manufacturing method therefor
EP3955316A2 (en) Transistor device with buried field electrode connection
CN115050823A (en) Semiconductor device including trench structures separated from each other
CN113594043A (en) Trench type MOSFET device and manufacturing method thereof
US20240178315A1 (en) Semiconductor device and methods for forming the same
US20230079309A1 (en) Field-effect transistor and method for manufacturing field-effect transistor
US20220376063A1 (en) Semiconductor die with a transistor device and method of manufacturing the same
KR100729016B1 (en) Trench type mosfet and method of making the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20960619

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20960619

Country of ref document: EP

Kind code of ref document: A1