WO2022094894A1

WO2022094894A1 - Testing method, control, electronic speed control, power apparatus, and movable platform for electric motor

Info

Publication number: WO2022094894A1
Application number: PCT/CN2020/126864
Authority: WO
Inventors: 马晨旭; 陈鸿滨; 陈旭
Original assignee: 深圳市大疆创新科技有限公司
Priority date: 2020-11-05
Filing date: 2020-11-05
Publication date: 2022-05-12
Also published as: CN114710972A

Abstract

Provided is a method for testing an electric motor, comprising: according to a preset control logic, controlling a switching state of first and second power tubes driven by three half-bridges (S110); obtaining the bus current outputted from a power supply to a drive circuit (S120); according to the bus current and a current threshold corresponding to a preset control logic, determining the fault status of the motor and/or drive circuit (S130). The present application enables the use of fewer resources to test an electric motor. The present application also provides a control device, an electronic speed control apparatus, a power apparatus, and a movable platform.

Description

Detection method, control, ESC, power device and movable platform of motor

technical field

The present application relates to the technical field of motors, and in particular, to a detection method, a control device, an ESC device, a power device, and a movable platform for a motor.

Background technique

In the field of motor control, it is often necessary to test the motor, power tube and power tube drive circuit to prevent losses and dangers caused by the failure of the motor, power tube or power tube drive circuit when some equipment such as unmanned aerial vehicles perform tasks.

Usually, whether there is a fault in the motor is determined by detecting the voltage and/or current of each phase of the motor, which requires more voltage and/or current to be detected, which occupies more hardware resources.

SUMMARY OF THE INVENTION

The present application provides a motor detection method, a control device, an ESC device, a power device and a movable platform, which can realize motor detection with less resources.

In a first aspect, an embodiment of the present application provides a method for detecting a motor. The motor is connected to a drive circuit, and the drive circuit includes three half-bridge drivers, each of which includes a first power transistor and a second half-bridge driver. a power tube, and the first power tube is used for connecting the positive pole of the power supply, and the second power tube is used for connecting the negative pole of the power supply;

The detection method includes:

controlling the switching states of the first power transistor and the second power transistor driven by the three half-bridges according to the preset control logic;

obtaining the bus current output by the power supply to the driving circuit;

The fault state of the motor and/or the drive circuit is determined according to the bus current and the current threshold corresponding to the preset control logic.

In a second aspect, an embodiment of the present application provides a control device for a motor, the motor is connected to a drive circuit, the drive circuit includes three half-bridge drivers, and each of the half-bridge drivers includes a first power transistor and a second a power tube, and the first power tube is used for connecting the positive pole of the power supply, and the second power tube is used for connecting the negative pole of the power supply;

The control device includes:

One or more processors, working individually or collectively, to perform:

obtaining the bus current output by the power supply to the driving circuit;

In a third aspect, an embodiment of the present application provides an ESC device, including:

A drive circuit can be connected to a motor, the drive circuit includes three half-bridge drivers, each of the half-bridge drivers includes a first power tube and a second power tube, and the first power tube is used to connect the positive pole of the power supply, so The second power tube is used to connect the negative pole of the power supply;

One or more processors, working individually or collectively, to perform:

obtaining the bus current output by the power supply to the driving circuit;

In a fourth aspect, an embodiment of the present application provides a power device, including:

motor;

a drive circuit, connected to the motor, the drive circuit includes three half-bridge drivers, each of the half-bridge drivers includes a first power tube and a second power tube, and the first power tube is used to connect the positive pole of the power supply, the second power tube is used for connecting the negative pole of the power supply;

One or more processors, working individually or collectively, to perform:

obtaining the bus current output by the power supply to the driving circuit;

In a fifth aspect, an embodiment of the present application provides a movable platform, including:

motor;

One or more processors, working individually or collectively, to perform:

obtaining the bus current output by the power supply to the driving circuit;

In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor implements the foregoing method.

The embodiments of the present application provide a motor detection method, a control device, an ESC device, a power device, and a movable platform, by controlling the first power tube and the second power tube driven by the three half-bridges according to a preset control logic The switch state of the tube, and the bus current output by the power supply to the drive circuit, so that the motor and/or the drive circuit can be determined according to the bus current and the current threshold corresponding to the preset control logic. The fault state can save processor resources, such as processor pins and resources for sampling voltage and/or current.

It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and do not limit the disclosure of the embodiments of the present application.

Description of drawings

In order to explain the technical solutions of the embodiments of the present application more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

1 is a schematic flowchart of a method for detecting a motor provided by an embodiment of the present application;

Fig. 2 is the circuit schematic diagram of the motor connection drive circuit;

Fig. 3 is the first circuit schematic diagram of the motor self-test;

Fig. 4 is the second circuit schematic diagram of the motor self-test;

FIG. 5 is a schematic circuit diagram of a motor self-checking by a detection method according to an embodiment of the present application;

FIG. 6 is a schematic circuit diagram of the self-test of the motor by the detection method according to another embodiment of the present application;

7 is a schematic block diagram of a control device for a motor provided by an embodiment of the present application;

FIG. 8 is a schematic block diagram of an ESC device provided by an embodiment of the present application;

9 is a schematic block diagram of a power plant provided by an embodiment of the present application;

FIG. 10 is a schematic block diagram of a movable platform provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

The flowcharts shown in the figures are for illustration only, and do not necessarily include all contents and operations/steps, nor do they have to be performed in the order described. For example, some operations/steps can also be decomposed, combined or partially combined, so the actual execution order may be changed according to the actual situation.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and features in the embodiments may be combined with each other without conflict.

Please refer to FIG. 1 , which is a schematic flowchart of a method for detecting a motor provided by an embodiment of the present application. The detection method can be applied to a control device of a motor, such as an electronic speed controller (Electronic Speed Control, ESC, also known as an ESC), to detect the motor and the driving device of the motor, etc.; Including permanent magnet synchronous motor (PMSM), brushless DC motor (BLDC), or including inner rotor motor or outer rotor motor, or including brush motor, brushless motor, etc. In some embodiments, the detection method may be applied to a movable platform. Exemplarily, the movable platform may include at least one of an unmanned aerial vehicle, a pan/tilt, and an unmanned vehicle. Further, the unmanned aerial vehicle can be a rotary-wing drone, such as a quad-rotor drone, a six-rotor drone, an eight-rotor drone, or a fixed-wing drone.

Exemplarily, the ESC is used to drive the driver of the brushless DC motor on the multi-rotor drone. The output end of the ESC may include three phase wires, and the ESC can adjust the voltage (frequency, phase, etc.) of each phase wire at the output end. ) to control the speed and/or direction of rotation of the motor to which it is connected.

Exemplarily, the flight control system of the unmanned aerial vehicle, namely the flight control, refers to a control system capable of stabilizing the flight attitude of the unmanned aerial vehicle and capable of controlling the autonomous or semi-autonomous flight of the unmanned aerial vehicle, and is the brain of the unmanned aerial vehicle. It can usually determine the current flight state of the UAV through various sensors (for example, gyroscopes, accelerometers, geomagnetic induction, air pressure sensors, GPS modules, etc.) The electronic governor and the corresponding motor control each rotor of the unmanned aerial vehicle.

As shown in FIG. 2 , the motor is connected to a drive circuit, the drive circuit includes three half-bridge drivers, each of the half-bridge drivers includes a first power transistor and a second power transistor, and the first power transistor is used to connect the power supply The positive pole of the power supply, the second power tube is used to connect the negative pole of the power supply. It can be understood that the drive circuit may include a three-phase full-bridge drive circuit, the first power tube may be referred to as a high-side power tube (also referred to as an upper-side power tube), and the second power tube may be referred to as a low-side power tube. Side power tubes (also called lower power tubes).

As shown in FIG. 2 to FIG. 6 , the first half-bridge driver includes a first power tube Q1 and a second power tube Q4, the second half-bridge driver includes a first power tube Q2 and a second power tube Q5, and the third half-bridge driver includes a first power tube Q2 and a second power tube Q5. The half-bridge driver includes a first power transistor Q3 and a second power transistor Q6.

The connection between the first power tube and the second power tube driven by the three half-bridges is used to connect the motor. As shown in Figure 2, the motor is connected to the drive circuit in a star connection. In other embodiments, the motor may be connected to the drive circuit in a star-delta connection.

In some embodiments, the motor and the drive circuit connected to the motor can be detected, for example, the ESC can detect the motor and the drive circuit connected to the motor when powered on, to prevent faults from expanding during motor operation and even cause safety hazards.

FIG. 3 is a schematic diagram of self-checking when a motor is controlled by a motor vector control (Fielded Oriented Control, FOC) method in a current embodiment. As shown in FIG. 3 , a sampling resistor R is connected to the loop of each half-bridge driver and the motor, and the processor can detect the current driven by each half-bridge through the sampling resistor R, which can be called a phase current. For example, the processor can pass a voltage signal across its own or an external analog-to-digital converter (ADC) resistor, and then divide the voltage signal by the resistance of the resistor to obtain the current through the resistor. The processor needs at least three current samples to get the self-test result.

FIG. 4 is a schematic diagram of performing self-checking when controlling a motor in another embodiment of the present invention. As shown in Figure 4, the connection between the first power tube and the second power tube driven by each half-bridge is connected to the processor through the voltage sampling circuit Rx, and the processor can detect the voltage at the corresponding position through the voltage sampling circuit Rx, and the voltage can be called is the phase voltage; the second power tube driven by each half-bridge is grounded through a resistor Rb, and the processor can detect the current output by the power supply to the driving circuit through the resistor Rb, and the current can be called the bus current. The processor needs at least three voltage samples and one current sample to get the self-test results.

The inventors of the present application have found that the current motor self-checking method needs to occupy more resources of the processor, such as the pins of the processor and the resources of sampling voltage and/or current. In response to this discovery, the inventors of the present application have improved the motor self-test method to save processor resources, such as processor pins and resources for sampling voltage and/or current.

As shown in FIG. 1 , the method for detecting a motor according to the embodiment of the present application includes steps S110 to S130 .

S110. Control the switching states of the first power transistors and the second power transistors driven by the three half-bridges according to preset control logic.

It can be understood that the first power transistor and the second power transistor include, for example, MOS transistors, and the switching states of the first power transistor and the second power transistor include on or off.

Exemplarily, the switching states of the first power transistors and the second power transistors driven by the three half-bridges may be controlled respectively. As shown in FIG. 5 , the processor can output six control signals PWM1 to PWM6, and the six control signals PWM1 to PWM6 are used to control the six control power tubes Q1 to Q6 in one-to-one correspondence.

In some embodiments, as shown in FIG. 5 and FIG. 6 , a power tube driver circuit (which may be referred to as a Driver) is connected between the processor and the driver circuit, and the power tube driver circuit includes, for example, a power tube driver chip. The power tube driving circuit can be understood as a kind of power amplifier, which can output the driving signal for driving the power tube according to the low-power signal generated by the processor.

In some embodiments, the processor may also output specific control instructions to the power tube drive circuit to control the power tube drive circuit to output six drive signals. For example, the processor may shake hands with the power tube drive circuit to establish a communication connection, and through the communication connection Output specific control commands to the power tube drive circuit.

In some embodiments, one control signal of the processor can control the first power transistor and the second power transistor driven by one half-bridge. Exemplarily, the power tube driving circuit may output two driving signals for driving the power tube according to one control signal PWM1.

Exemplarily, when controlling the driving of each of the half bridges, one of the first power transistor and the second power transistor driven by the half bridge is controlled to be turned on, and the other is turned off. As shown in FIG. 6 , the processor can output three control signals PWM1 to PWM3, and the three control signals PWM1 to PWM3 are used to control one half-bridge driver respectively, and specifically control the first power tube and the second power tube in each half-bridge driver. power tube. For example, the control signal PWM1 is used to control the two power tubes in the first half-bridge driver, the control signal PWM2 is used to control the two power tubes in the second half-bridge driver, and the control signal PWM3 is used to control the third half-bridge Two power tubes in the driver. Therefore, six power tubes can be controlled by three control signals output by three pins, which can save the resources of the processor, for example, three pins can be saved.

Exemplarily, the control signals PWM1 to PWM3 can control the power tube driving circuit to send out three pairs of complementary driving signals, and each pair of complementary driving signals includes two driving signals, and the two driving signals are used to control the driving of the half-bridge. One of the first power tube and the second power tube is turned on, and the other is turned off.

Exemplarily, as shown in FIG. 6 , the processor controls the power tube driving circuit to send out three pairs of complementary driving signals through three control signals PWM1 to PWM3, which can save the occupation of processor resources.

It can be understood that when one of the two complementary driving signals is at a high level, the other is at a low level, so that one of the two power transistors driven by the corresponding half-bridge can be controlled to be turned on and the other to be turned off.

In some embodiments, the detection method further includes: enabling the power tube driving circuit, so that the power tube driving circuit can send the driving signal.

As shown in FIG. 5 and FIG. 6 , the power tube drive circuit includes an enable terminal, and the processor can enable the power tube drive circuit by outputting an enable signal En to the enable terminal of the power tube drive circuit, so that the power A tube drive circuit can issue the drive signal. Specifically, when the processor outputs the enable signal En, the power transistor drive circuit can send the drive signal according to the control signal output by the processor; when the processor does not output the enable signal En, regardless of whether the processor outputs the control signal, the power transistor None of the drive circuits issue the drive signal.

Exemplarily, as shown in FIG. 3 and FIG. 4 , the power tube driving circuit includes an error reporting terminal for outputting an error reporting signal Fault, and the processor may determine that the power tube driving circuit is faulty according to the fault reporting signal Fault.

In some embodiments, the controlling the switching states of the first power transistors and the second power transistors driven by the three half-bridges includes: by setting the duty ratio of the driving signal sent by the power transistor driving circuit, The switching states of the first power transistor and the second power transistor are controlled.

Exemplarily, when the duty cycle of the driving signal for driving a certain power tube is 0%, the power tube is in an off state; when the duty ratio of the driving signal for driving a certain power tube is 100%, the power tube is in an off state. The power tube is in a conducting state.

Exemplarily, when the processor outputs a control signal PWM with a duty cycle of 0%, the power tube drive circuit sends out two corresponding drive signals, and one of the drive signals has a duty cycle of 0%, and the other drive The duty cycle of the signal is 100%. When the processor outputs a control signal PWM with a duty ratio of 100%, the power tube driving circuit sends out two corresponding driving signals, and the duty ratio of one of the driving signals is 100%, and the duty ratio of the other driving signal is 100%. ratio is 0%.

In some embodiments, the controlling the switching states of the first power transistors and the second power transistors driven by the three half-bridges includes: setting a high-level duration of the driving signal sent by the power transistor driving circuit , and/or enable the duration of the power tube drive circuit, and set the duration of the conduction of the first power tube or the second power tube.

Exemplarily, when the power tube drive circuit is enabled, the processor can control the power tube drive circuit to send out at least one high-level signal of a specific duration, and then the high-level signal can control the corresponding power tube to conduct the preset. duration.

Exemplarily, the processor may issue a control signal for controlling the power tube driving circuit to issue a high-level signal, such as a control signal with a duty cycle of 100% or 0%, by enabling the power tube driving circuit for a certain period of time. , the power tube driving circuit can be made to issue a high level for a specific duration, so as to control the corresponding power tube to be turned on for the preset duration.

S120. Obtain the bus current output by the power supply to the driving circuit.

Exemplarily, as shown in FIG. 5 and FIG. 6 , the bus current output by the power supply to the driving circuit can be obtained through the sampling resistor Rb. As shown in FIG. 5 , the sampling resistor Rb can be connected between the driving circuit and the negative pole of the power supply; as shown in FIG. 6 , the sampling resistor Rb can be connected between the driving circuit and the power supply between the positive poles. Of course, it is not limited to this method to obtain the bus current. For example, the power supply can detect the current output to the driving circuit, and the processor can obtain the current from the power supply as the bus current.

S130. Determine a fault state of the motor and/or the drive circuit according to the bus current and the current threshold corresponding to the preset control logic.

Specifically, when the motor and/or the drive circuit are in a fault state, it can be detected that the bus current is an abnormal value. Therefore, the fault state of the motor and/or the drive circuit can be determined according to the bus current.

When the first power transistor and the second power transistor driven by the three half-bridges have specific switching states, and the motor and/or the driving circuit are in different fault states, it can be detected that the bus current is the corresponding The abnormal value of the state of the switch. Therefore, the fault state of the motor and/or the driving circuit can be determined according to the bus current and the current threshold corresponding to the preset control logic.

In some embodiments, the fault state of the motor and/or the drive circuit includes: short circuit and/or failure of the circuit to connect.

Exemplarily, when the ESC is powered on, it can be detected whether the six power tubes are short-circuited or open-circuited, whether the three-phase permanent magnet synchronous motor is short-circuited between phases, whether the three-phase permanent-magnet synchronous motor is open-phase, and whether the power tube drive circuit is normal. .

Exemplarily, when the detected current is greater than a certain current threshold, it may be determined that the circuit is short-circuited; when the detected current is less than another current threshold, it may be determined that the circuit is not connected. It can be understood that the current threshold used to determine the short circuit fault state is greater than the current threshold used to determine the loop failure state.

In some embodiments, the possible faults of the motor and the control device of the motor, such as the ESC, include at least one of the following: one or more power tubes are short-circuited or open-circuited, and the drive circuit of one or more power tubes is open-circuited , Phase-to-phase short circuit occurs in three phases of the motor, phase failure occurs in three phases of the motor, the grid (G) poles of one or more first power tubes are short-circuited to the ground, and the grid (G) poles of one or more second power tubes are short-circuited to the power supply . Wherein, the short circuit of the power tube includes a gate-source (GS) pole short circuit, a gate-drain (GD) pole short circuit, or a drain-source (DS) pole short circuit of the power tube.

In some embodiments, the second power transistors driven by the three half-bridges are controlled to be turned on for a first preset period of time, and if the bus current is greater than or equal to a first current threshold, the second power transistors driven by at least one of the half-bridges are determined to be turned on for a first preset time period. A power tube is short-circuited.

Please refer to FIG. 5 and FIG. 6 , when the three second power tubes Q4 to Q6 are all turned on, if any one of the first power tubes is turned on in a short-circuit (uncontrolled turn-on), the positive pole of the power supply will pass through the short-circuited first power tube. If the power tube and the conductive second power tube are connected to the negative pole of the power supply, the busbar current is large, which can be understood as a short-circuit current, which is greater than or equal to the first current threshold. In order to prevent short-circuit current damage, the second power transistors driven by the three half-bridges may be controlled to be turned on for a short first preset time period, such as 0.2 to 3 microseconds.

Exemplarily, referring to FIG. 6 , the processor may turn off the output of the power tube driving circuit, for example, stop enabling the power tube driving circuit, then output the control signals PWM1 to PWM3 with a duty cycle of 0%, and issue the first control signal PWM1 to PWM3. A preset duration, such as 1 microsecond, enables the power tube drive circuit to turn on and output the first preset duration, and the bus current is sampled through the sampling resistor Rb within the first preset duration. If the busbar has a large current, it can be determined that the high- and low-side power tubes are connected directly, that is, the positive pole of the power supply is connected to the negative pole of the power supply through the first power tube and the second power tube, and does not pass through the motor. For example, it can be determined that at least one of the first power transistors driven by the half-bridge is short-circuited at the DS pole or the GD pole. Can end self-test and/or output fault message.

In some embodiments, the second power transistors driven by the three half-bridges are controlled to be turned on for a first preset duration, and if the bus current is less than a first current threshold, a subsequent self-checking step may be performed, or it may be determined that no occurrence of If it fails, it can also start to perform preset tasks, such as speed regulation, takeoff, etc.

In some embodiments, the first power transistor driven by one of the half bridges is controlled to be turned on for a second preset time period and the second power transistors driven by the remaining two half bridges are controlled to be turned on, if the bus current is greater than or equal to the second current The threshold value is used to determine that the circuit corresponding to the first power transistor driven by one of the half-bridges has a short-circuit fault.

For example, please refer to FIG. 5 and FIG. 6 , when the first power transistor Q1 driven by the first half-bridge is turned on, and the second power transistors Q5 and Q6 driven by the second and third half-bridges are turned on. , if the first power tube Q1 is abnormally short-circuited, the busbar current is relatively large, which can be understood as a short-circuit current, which is greater than or equal to the second current threshold. In order to prevent short-circuit current damage, the first power transistor driven by one of the half-bridges may be controlled to be turned on for a shorter second preset time period, such as 0.2 to 3 microseconds.

Exemplarily, the first power transistor driven by one half-bridge is controlled to be turned on for a second preset duration and the second power transistors driven by the remaining two half-bridges are controlled to be turned on, if the bus current is greater than or equal to the second current threshold, Then, it can be determined that the second power tube corresponding to the first power tube that is turned on is short-circuited, the second power tube is short-circuited with the power supply, and/or the motor is short-circuited between phases.

Exemplarily, the processor first turns on the output of the power tube driving circuit through the enable signal, and then uses the pin for outputting the control signal PWM1 to send out a second preset duration, such as a high-level pulse of 1 microsecond, to set the control. The duty cycle of the signals PWM2 and PWM3 is 0%, so that the first power tube Q1 can be controlled to be turned on for 1 microsecond, the second power tube Q4 can be turned off, and the first power tube Q2 and Q3 can be controlled to be turned off, and the second power tube can be turned off. Q5 and Q6 are turned on. The bus current is sampled through the sampling resistor Rb within the second preset time period. If the bus has a large current, it can be determined that the high- and low-side power tubes are connected directly, for example, the second power tube Q4 is short-circuited at the DS pole or the G pole is short-circuited with the power supply instead of controlled conduction, or the motor is short-circuited between phases. Can end self-test and/or output fault message.

Exemplarily, the processor first turns on the output of the power tube drive circuit through the enable signal, and then uses the pin for outputting the control signal PWM2 to issue a second preset duration, such as a high-level pulse of 1 microsecond, to set the control. The duty cycle of the signals PWM1 and PWM3 is 0%, so that the first power transistor Q2 can be controlled to be turned on for 1 microsecond, the second power transistor Q5 can be turned off, and the first power transistors Q1 and Q3 can be controlled to be turned off, and the second power transistor can be controlled to turn off. Q4 and Q6 are turned on. The bus current is sampled through the sampling resistor Rb within the second preset time period. If the bus has a large current, it can be determined that the high- and low-side power tubes are connected directly, for example, the second power tube Q5 is short-circuited at the DS pole or the G pole is short-circuited with the power supply instead of controlled conduction, or the motor is short-circuited between phases. Can end self-test and/or output fault message.

The processor first turns on the output of the power tube drive circuit through the enable signal, and then uses the pin used to output the control signal PWM3 to send out a second preset duration, such as a high-level pulse of 1 microsecond, to set the control signals PWM1, PWM2 The duty cycle is 0%, so that the first power tube Q3 can be controlled to be turned on for 1 microsecond, the second power tube Q6 can be turned off, and the first power tubes Q1 and Q2 can be controlled to be turned off, and the second power tubes Q4 and Q5 can be turned on. Pass. The bus current is sampled through the sampling resistor Rb within the second preset time period. If there is a large current in the bus, it can be determined that the high-side and low-side power tubes are connected directly. For example, the second power tube Q6 is short-circuited at the DS pole or the G pole is short-circuited with the power supply instead of controlled conduction, or the motor is short-circuited between phases. Can end self-test and/or output fault message.

In some embodiments, the first power transistor driven by one of the half bridges is controlled to be turned on for a second preset time period and the second power transistors driven by the remaining two half bridges are controlled to be turned on, if the bus current is less than the second current threshold, The subsequent self-test steps can then be performed, or it can be determined that no fault has occurred, and a preset task can be started.

In some embodiments, the first power transistor driven by one of the half bridges is controlled to be turned on for a third preset time period and the second power transistors driven by the remaining two half bridges are controlled to be turned on, if the bus current is less than or equal to the third current Threshold value, it is determined that the circuit of the motor and/or the drive circuit fails to connect.

For example, please refer to FIG. 5 and FIG. 6 , when the first power transistor Q1 driven by the first half-bridge is turned on, and the second power transistors Q5 and Q6 driven by the second and third half-bridges are turned on relatively When the third preset time period is long, if the loop between the positive pole of the power supply and the negative pole of the power supply cannot be connected, the bus current is small or 0, specifically less than or equal to the third current threshold, and the third current threshold is less than the aforementioned The first current threshold, the second current threshold, for example, the third preset duration is 3 to 10 microseconds.

Exemplarily, when it is determined that the motor and the drive circuit do not have a short-circuit fault, the first power transistor driven by one of the half-bridges is controlled to be turned on for a third preset duration and the second power transistors driven by the remaining two half-bridges Conduction to prevent damage caused by long-term short-circuit.

Exemplarily, the determining that the circuit of the motor and/or the driving circuit is not connected includes: determining that the first power tube driven by one of the half-bridges is not controlled to be turned on, and the remaining two half-bridges are not connected. The second power tube driven by the bridge is not turned on in a controlled manner, and/or the motor is out of phase.

It can be understood that the uncontrolled conduction of the first power tube includes: the driving resistor of the first power tube is disconnected, the gate and source of the first power tube are disconnected, and/or the first power tube is disconnected. The grid of the power tube is shorted to ground. As shown in FIG. 6 , the driving resistors of the first power tube include resistors R1 to R3, which can improve the accuracy of power tube control. The driving resistor can be set outside the power tube driving circuit, or can be set inside the power tube driving circuit.

It can be understood that the uncontrolled conduction of the second power tube includes: the driving resistor of the second power tube is disconnected, the gate and source of the second power tube are disconnected, and/or the second power tube is disconnected. The gate and drain of the power tube are shorted.

Exemplarily, the phase failure of the motor includes: a phase failure of the motor and the driving connection of one of the half-bridges, and/or two-phase driving connections of the motor and the remaining two half-bridges. out of phase.

Exemplarily, the processor first turns on the output of the power tube drive circuit through the enable signal, and then uses the pin for outputting the control signal PWM1 to send a third preset duration, such as a high-level pulse of 5 microseconds, to set the control. The duty cycle of the signals PWM2 and PWM3 is 0%, so that the first power transistor Q1 can be controlled to be turned on for 5 microseconds, the second power transistor Q4 can be turned off, and the first power transistors Q2 and Q3 can be controlled to be turned off, and the second power transistor can be controlled to turn off. Q5 and Q6 are turned on. The bus current is sampled through the sampling resistor Rb within the third preset time period. If the busbar current is less than or equal to the third current threshold, it can be determined that the motor and/or the loop of the driving circuit is not connected, for example, it can be determined that the first power transistor Q1 has a driving resistance open circuit, a GS pole short circuit, or a G pole short circuit. Short-circuit to ground, determine that the second power transistors Q5 and Q6 have drive resistance open circuit, GS pole short circuit or GD pole short circuit, or determine that the motor phase is open. Can end self-test and/or output fault message.

Exemplarily, the processor first turns on the output of the power tube driving circuit through the enable signal, and then uses the pin for outputting the control signal PWM2 to issue a third preset duration, such as a high-level pulse of 5 microseconds, to set the control. The duty cycle of the signals PWM1 and PWM3 is 0%, so that the first power transistor Q2 can be controlled to be turned on for 5 microseconds, the second power transistor Q5 can be turned off, and the first power transistors Q1 and Q3 can be controlled to be turned off, and the second power transistor can be controlled to be turned off. Q4 and Q6 are turned on. The bus current is sampled through the sampling resistor Rb within the third preset time period. If the busbar current is less than or equal to the third current threshold, it can be determined that the motor and/or the loop of the drive circuit is not connected, for example, it can be determined that the first power transistor Q2 has a drive resistance open circuit, a GS pole short circuit, or a G pole short circuit. Short-circuit to ground, determine that the second power transistors Q4 and Q6 have drive resistance open circuit, GS pole short circuit or GD pole short circuit, or determine that the motor phase is open. Can end self-test and/or output fault message.

Exemplarily, the processor first turns on the output of the power tube drive circuit through the enable signal, and then uses the pin for outputting the control signal PWM3 to send a third preset duration, such as a high-level pulse of 5 microseconds, to set the control. The duty cycle of the signals PWM1 and PWM2 is 0%, so that the first power transistor Q3 can be controlled to be turned on for 5 microseconds, the second power transistor Q6 can be turned off, and the first power transistors Q1 and Q2 can be controlled to be turned off, and the second power transistor can be controlled to turn off. Q4 and Q5 are turned on. The bus current is sampled through the sampling resistor Rb within the third preset time period. If the busbar current is less than or equal to the third current threshold, it can be determined that the motor and/or the loop of the driving circuit is not connected, for example, it can be determined that the first power transistor Q3 has a driving resistance open circuit, a GS pole short circuit, or a G pole short circuit. Short-circuit to ground, determine that the second power transistors Q4 and Q5 have drive resistance open circuit, GS pole short circuit or GD pole short circuit, or determine that the motor is out of phase. Can end self-test and/or output fault message.

In some embodiments, the first power transistor driven by one of the half bridges is controlled to be turned on for a third preset time period and the second power transistors driven by the remaining two half bridges are controlled to be turned on, if the bus current is greater than a third current threshold and If it is less than the second current threshold, subsequent self-checking steps can be performed, or it is determined that no fault has occurred, and the preset task can also be started.

In some embodiments, the first power transistors driven by two half-bridges are controlled to be turned on for a fourth preset time period and the second power transistors driven by the remaining one half-bridge are controlled to be turned on, if the bus current is less than or less than the fourth current Threshold value, it is determined that the circuit of the motor and/or the drive circuit fails to connect.

Exemplarily, please refer to FIG. 5 and FIG. 6 , when the first power transistors Q1 and Q2 driven by the first and second half bridges are turned on, and the second power transistor Q6 driven by the third half bridge is turned on, When the fourth preset duration is long, if the loop between the positive pole of the power supply and the negative pole of the power supply cannot be connected, the bus current is small or 0, specifically less than or equal to the fourth current threshold, and the third current threshold is less than the aforementioned The first current threshold, the second current threshold, for example, the fourth preset duration is 3 to 10 microseconds.

Exemplarily, when it is determined that the motor and the drive circuit do not have a short-circuit fault, the first power transistors driven by two half-bridges are controlled to be turned on for a fourth preset duration and the second power transistors driven by the remaining one half-bridge Conduction to prevent damage caused by long-term short-circuit.

Exemplarily, the determining that the circuits of the motor and/or the driving circuit are not connected includes: determining that the first power transistors driven by the two half-bridges are not controlled to be turned on, and the remaining one half-bridge The second power tube driven by the bridge is not turned on in a controlled manner, and/or the motor is out of phase.

It can be understood that the uncontrolled conduction of the first power tube includes: the driving resistor of the first power tube is disconnected, the gate and source of the first power tube are disconnected, and/or the first power tube is disconnected. The grid of the power tube is shorted to ground. The uncontrolled conduction of the second power transistor includes: the drive resistor of the second power transistor is disconnected, the gate and source of the second power transistor are disconnected, and/or the gate of the second power transistor is disconnected The pole and drain are shorted.

Exemplarily, the phase failure of the motor includes: the motor and the two phases drivingly connected to the two half-bridges are both out of phase, and/or the motor is drivingly connected to the remaining one half-bridge for one phase. out of phase.

Exemplarily, the processor first turns on the output of the power tube drive circuit through the enable signal, and then sends a fourth preset duration, such as a high-level pulse of 5 microseconds, to the pins used to output the control signals PWM1 and PWM2, set The duty cycle of the control signal PWM3 is set to 0%, so that the first power transistors Q1 and Q2 can be controlled to be turned on for 5 microseconds, the second power transistors Q4 and Q5 can be turned off, and the first power transistor Q3 can be controlled to turn off and the second power transistor Q3 to be turned off. The power tube Q6 is turned on. The bus current is sampled through the sampling resistor Rb within the fourth preset time period. If the busbar current is less than or equal to the fourth current threshold, it can be determined that the motor and/or the loop of the driving circuit cannot be connected, for example, it can be determined that the first power transistors Q1 and Q2 have a driving resistance open circuit, a GS pole short circuit, or The G pole is short-circuited to the ground, it is determined that the second power transistor Q6 has a drive resistor open circuit, the GS pole is short-circuited or the GD pole is short-circuited, or it is determined that the motor is out of phase. Can end self-test and/or output fault message.

Exemplarily, the processor first turns on the output of the power tube driving circuit through the enable signal, and then uses the pins for outputting the control signals PWM1 and PWM3 to send out a fourth preset duration, such as a high-level pulse of 5 microseconds, set The duty cycle of the control signal PWM2 is set to 0%, so that the first power transistors Q1 and Q3 can be controlled to be turned on for 5 microseconds, the second power transistors Q4 and Q6 can be turned off, and the first power transistor Q2 can be controlled to be turned off and the second The power tube Q5 is turned on. The bus current is sampled through the sampling resistor Rb within the fourth preset time period. If the busbar current is less than or equal to the fourth current threshold, it can be determined that the motor and/or the loop of the driving circuit is not connected, for example, it can be determined that the first power transistors Q1 and Q3 have a driving resistance open circuit, a GS pole short circuit or The G pole is short-circuited to the ground, it is determined that the second power transistor Q5 has a drive resistor open circuit, the GS pole is short-circuited or the GD pole is short-circuited, or it is determined that the motor is out of phase. Can end self-test and/or output fault message.

Exemplarily, the processor first turns on the output of the power tube drive circuit through the enable signal, and then uses the pins for outputting the control signals PWM2 and PWM3 to send out a fourth preset duration, such as a high-level pulse of 5 microseconds, set The duty cycle of the control signal PWM1 is set to 0%, so that the first power transistors Q2 and Q3 can be controlled to be turned on for 5 microseconds, the second power transistors Q5 and Q6 can be turned off, and the first power transistor Q1 can be The power tube Q4 is turned on. The bus current is sampled through the sampling resistor Rb within the fourth preset time period. If the busbar current is less than or equal to the fourth current threshold, it can be determined that the motor and/or the loop of the driving circuit is not connected, for example, it can be determined that the first power transistors Q2 and Q3 have a driving resistance open circuit, a GS pole short circuit or The G pole is short-circuited to the ground, it is determined that the second power transistor Q4 has a drive resistance open circuit, the GS pole is short-circuited or the GD pole is short-circuited, or it is determined that the motor phase is disconnected. Can end self-test and/or output fault message.

In some embodiments, the first power transistors driven by two half-bridges are controlled to be turned on for a fourth preset time period and the second power transistors driven by the remaining one half-bridge are controlled to be turned on, if the bus current is greater than the fourth current threshold and If it is less than the second current threshold, other self-test steps can be performed, or it is determined that no fault has occurred, and the preset task can also be started.

In some embodiments, the current threshold for determining the short circuit fault condition is greater than the current threshold for determining the loop failure condition. Exemplarily, the first current threshold and the second current threshold are greater than the third current threshold and the fourth current threshold.

In some embodiments, the preset duration of conduction of the power tube when the short-circuit fault state is determined is less than the preset duration of conduction of the power tube when it is determined that the circuit fails to connect to the fault state. Exemplarily, the first preset duration and the second preset duration are smaller than the third preset duration and the fourth preset duration. Can prevent damage caused by long-term short circuit.

In some embodiments, the second power transistors driven by the three half-bridges may be controlled to be turned on for a first preset period of time, so as to determine whether the first power transistors are short-circuited according to the bus current; and then one of the half-bridges may be controlled to drive The first power tube is turned on for a second preset duration and the second power tubes driven by the remaining two half-bridges are turned on, so as to determine whether the circuit corresponding to the first power tube has a short-circuit fault according to the bus current; if all the first power tubes are turned on If there is no short-circuit fault in the circuits corresponding to the power tube and the first power tube, the first power tube driven by one of the half-bridges can be controlled to be turned on for the third preset duration and the second power tubes driven by the remaining two half-bridges can be controlled to be turned on , so as to determine whether the circuit of the motor and/or the drive circuit can be connected according to the bus current; and/or control the first power tube driven by the two half-bridges to be turned on for a fourth preset duration and the remaining one half-bridge The second power tube driven by the bridge is turned on, so as to determine whether the circuit of the motor and/or the driving circuit can be connected according to the bus current. If it is determined that no short-circuit fault has occurred in all the first power tubes and the circuits corresponding to the first power tubes, and the circuits of the motor and/or the driving circuit can be connected, it can be determined that no failure has occurred, and the preset execution can be started. Task.

In the motor detection method provided by the embodiment of the present application, the switching states of the first power transistor and the second power transistor driven by the three half-bridges are controlled according to a preset control logic, and the output of the power supply to the driving circuit is obtained by obtaining the Therefore, the fault state of the motor and/or the drive circuit can be determined according to the bus current and the current threshold corresponding to the preset control logic, which can save the resources of the processor, such as the introduction of the processor. The resources of pin and sampling voltage and/or current can be applied to some processors with lower performance, which is beneficial to the miniaturization of circuit arrangement and device, and reduces the cost.

Exemplarily, when detecting a motor, the resource occupation of the processor includes: a pin for outputting three-way control signals PWM, a pin for enabling the power tube drive circuit, and a pin for collecting bus current. pin.

In some implementations, one processor can control multiple motors, and the multiple motors are connected to multiple driving circuits in a one-to-one correspondence, and the driving circuit is one of multiple driving circuits of the multiple motors. Exemplarily, the processor may perform time-division detection on a plurality of motors and/or the drive circuits of each motor, for example, when detecting one motor and the drive circuit of the one motor, stop enabling the power transistors corresponding to the remaining motors. The drive circuit also only needs one pin to collect the bus current, and the fault state of the one motor and/or the drive circuit of the one motor can be determined according to the bus current.

Please refer to FIG. 7 in conjunction with the above embodiment. FIG. 7 is a schematic block diagram of an apparatus 600 for controlling a motor provided by an embodiment of the present application. The control device 600 includes one or more processors 601, working individually or collectively, for carrying out the steps of the aforementioned motor detection method.

Specifically, the motor is connected to a drive circuit, the drive circuit includes three half-bridge drivers, each of the half-bridge drivers includes a first power transistor and a second power transistor, and the first power transistor is used to connect the power supply Positive pole, the second power tube is used to connect the negative pole of the power supply.

Exemplarily, the control device 600 further includes a memory 602 .

Exemplarily, the processor 601 and the memory 602 are connected through a bus 603, and the bus 603 is, for example, an I2C (Inter-integrated Circuit) bus.

Specifically, the processor 601 may be a micro-controller unit (Micro-controller Unit, MCU), a central processing unit (Central Processing Unit, CPU), or a digital signal processor (Digital Signal Processor, DSP) or the like.

Specifically, the memory 602 may be a Flash chip, a read-only memory (ROM, Read-Only Memory) magnetic disk, an optical disk, a U disk, a mobile hard disk, and the like.

Wherein, the processor 601 is configured to run a computer program stored in the memory 602, and implement the aforementioned motor detection method when the computer program is executed.

Exemplarily, the processor 601 is configured to run a computer program stored in the memory 602, and implement the following steps when executing the computer program:

obtaining the bus current output by the power supply to the driving circuit;

In some embodiments, when controlling the driving of each half-bridge, one of the first power transistor and the second power transistor of the half-bridge driving is controlled to be turned on, and the other is turned off.

Exemplarily, the control device includes a power tube drive circuit;

The processor is used to control the power tube drive circuit to send out three pairs of complementary drive signals, each pair of complementary drive signals includes two drive signals, and the two drive signals are used to control the first drive signal of the half-bridge drive. One of the power tube and the second power tube is turned on, and the other is turned off.

Exemplarily, the processor is configured to control the power tube driving circuit to send out three pairs of complementary driving signals through three control signals.

Exemplarily, the processor is also used for:

The power tube driving circuit is enabled, so that the power tube driving circuit can send the driving signal.

Exemplarily, when the processor controls the switching states of the first power transistor and the second power transistor, the processor is configured to execute:

By setting the high-level duration of the driving signal sent by the power tube driving circuit, and/or enabling the power tube driving circuit, the first power tube or the second power tube is set to be turned on length of time.

By setting the duty ratio of the driving signal sent by the power tube driving circuit, the switching states of the first power tube and the second power tube are controlled.

In some embodiments, the bus current output by the power supply to the drive circuit is obtained through a sampling resistor, and the sampling resistor is connected between the drive circuit and the positive or negative pole of the power supply.

In some embodiments, the fault state of the motor and/or the drive circuit includes: short circuit and/or failure of the circuit to connect;

The current threshold for determining the short circuit fault condition is greater than the current threshold for determining the loop failure condition.

In some embodiments, the processor is configured to perform:

The second power transistors driven by the three half-bridges are controlled to be turned on for a first preset duration, and if the bus current is greater than or equal to a first current threshold, it is determined that at least one of the first power transistors driven by the half-bridges is short-circuited.

In some embodiments, the processor is configured to perform:

Control the first power tube driven by one of the half-bridges to be turned on for a second preset duration and the second power tubes driven by the remaining two half-bridges to be turned on, if the bus current is greater than or equal to the second current threshold, determine the among A short circuit fault occurs in the circuit corresponding to the first power tube driven by a half-bridge.

Exemplarily, the determining that a circuit corresponding to the first power transistor driven by one of the half-bridges has a short-circuit fault includes:

It is determined that the second power tube corresponding to the first power tube that is turned on is short-circuited, the second power tube is short-circuited with the power supply, and/or the motor is short-circuited between phases.

In some embodiments, the processor is configured to perform:

Controlling the first power tube driven by one of the half-bridges to be turned on for a third preset duration and the second power tubes driven by the remaining two half-bridges being turned on, if the bus current is less than or equal to a third current threshold, determine the motor And/or the loop of the drive circuit fails to connect.

Exemplarily, the determining that the circuit of the motor and/or the driving circuit fails to communicate includes:

It is determined that the first power transistor driven by one of the half bridges is not turned on under control, the second power transistors driven by the remaining two half bridges are not turned on under control, and/or the motor is out of phase.

Exemplarily, the phase failure of the motor includes:

One phase of the motor connected to the one of the half bridges is disconnected, and/or both phases of the motor connected to the other two half bridges are disconnected.

In some embodiments, the processor is configured to perform:

The first power transistors driven by two half-bridges are controlled to be turned on for a fourth preset duration and the second power transistors driven by the remaining one half-bridge are turned on. If the bus current is less than or below a fourth current threshold, determine the motor And/or the loop of the drive circuit fails to connect.

It is determined that the first power transistors driven by the two half-bridges are not turned on in a controlled manner, the second power transistors driven by the remaining one half-bridge are not controlled to be turned on, and/or the motor is out of phase.

Exemplarily, the phase failure of the motor includes:

Both the motor and the two phases drivingly connected to the two half-bridges are out of phase, and/or one phase of the motor and the remaining one half-bridge driving connection is out of phase.

Exemplarily, the uncontrolled conduction of the first power transistor includes: the driving resistor of the first power transistor is disconnected, the gate and source of the first power transistor are disconnected, and/or the first power transistor is disconnected. The grid of the power tube is shorted to ground.

Exemplarily, the uncontrolled conduction of the second power transistor includes:

The driving resistor of the second power tube is disconnected, the gate and source of the second power tube are disconnected, and/or the gate and drain of the second power tube are short-circuited.

Exemplarily, the preset duration of conduction of the power tube when the short-circuit fault state is determined is less than the preset duration of conduction of the power tube when it is determined that the circuit fails to be connected to the fault state.

In some embodiments, the drive circuit is one of a plurality of drive circuits of a plurality of motors;

The processor is also used to execute:

Time-division detection of multiple motors and/or the drive circuits of each motor.

The specific principles and implementation manners of the control apparatus provided by the embodiments of the present application are similar to the detection methods of the motors in the foregoing embodiments, and details are not described herein again.

Please refer to FIG. 8 in conjunction with the above-mentioned embodiment. FIG. 8 is a schematic block diagram of an electrical regulation apparatus 700 provided by an embodiment of the present application. The ESC device 700 may be, for example, an ESC device for a movable platform. The movable platform may include at least one of an unmanned aerial vehicle, a gimbal, an unmanned vehicle, and the like. Further, the unmanned aerial vehicle may be a rotary-wing drone, such as a quad-rotor drone, a hexa-rotor drone, an octa-rotor drone, or a fixed-wing drone.

The ESC device 700 includes a driving circuit 10 and one or more processors 701 .

The driving circuit 10 can be connected to a motor, and can provide a driving signal to the motor to drive the motor to rotate. The drive circuit 10 includes three half-bridge drivers, each of which includes a first power tube and a second power tube, and the first power tube is used for connecting the positive pole of the power supply, and the second power tube is used for Connect the negative terminal of the power supply.

Specifically, one or more processors 701 work individually or collectively to execute the steps of the aforementioned motor detection method.

Exemplarily, the ESC device 700 further includes a memory 702 .

Exemplarily, the processor 701 and the memory 702 are connected through a bus 703, and the bus 703 is, for example, an I2C (Inter-integrated Circuit) bus.

Specifically, the processor 701 may be a micro-controller unit (Micro-controller Unit, MCU), a central processing unit (Central Processing Unit, CPU) or a digital signal processor (Digital Signal Processor, DSP) or the like.

Specifically, the memory 702 may be a Flash chip, a read-only memory (ROM, Read-Only Memory) magnetic disk, an optical disk, a U disk, a mobile hard disk, and the like.

Wherein, the processor 701 is configured to run the computer program stored in the memory 702, and implement the aforementioned motor detection method when the computer program is executed.

Exemplarily, the processor 701 is configured to run a computer program stored in the memory 702, and implement the following steps when executing the computer program:

obtaining the bus current output by the power supply to the driving circuit;

The specific principles and implementation manners of the ESC provided in the embodiments of the present application are similar to the detection methods of the motors in the foregoing embodiments, which will not be repeated here.

Please refer to FIG. 9 in conjunction with the above embodiment. FIG. 9 is a schematic block diagram of a power device 800 provided by an embodiment of the present application. The power plant 800 may be, for example, a power plant for a movable platform. The movable platform may include at least one of an unmanned aerial vehicle, a gimbal, an unmanned vehicle, and the like. Further, the unmanned aerial vehicle may be a rotary-wing drone, such as a quad-rotor drone, a hexa-rotor drone, an octa-rotor drone, or a fixed-wing drone.

The power plant includes a motor 20 , a drive circuit 10 , and one or more processors 801 . It can be understood that the driving circuit 10 and the one or more processors 801 can be the driving circuit and the processor in the ESC device, the ESC device and the motor 20 are integrally provided, or are detachably connected, and one ESC device can be connected One or more motors 20 .

Wherein, the driving circuit 10 is connected to the motor 20 and can provide a driving signal to the motor 20 to drive the motor 20 to rotate. For example, the motor can be connected to the propeller of the unmanned aerial vehicle, the hub of the unmanned vehicle, the friction wheel of the launching device of the unmanned vehicle, the rotating shaft of the gimbal, etc., of course, it is not limited thereto.

The drive circuit 10 includes three half-bridge drivers, each of which includes a first power tube and a second power tube, and the first power tube is used to connect the positive pole of the power supply, and the second power tube is used to connect all the power tubes. the negative pole of the power supply.

Specifically, one or more processors 801 work individually or collectively to execute the steps of the aforementioned motor detection method.

Illustratively, powerplant 800 also includes memory 802 .

Exemplarily, the processor 801 and the memory 802 are connected through a bus 803, and the bus 803 is, for example, an I2C (Inter-integrated Circuit) bus.

Specifically, the processor 801 may be a micro-controller unit (Micro-controller Unit, MCU), a central processing unit (Central Processing Unit, CPU) or a digital signal processor (Digital Signal Processor, DSP) or the like.

Specifically, the memory 802 may be a Flash chip, a read-only memory (ROM, Read-Only Memory) magnetic disk, an optical disk, a U disk, or a removable hard disk, or the like.

Wherein, the processor 801 is configured to run a computer program stored in the memory 802, and implement the aforementioned motor detection method when the computer program is executed.

Exemplarily, the processor 801 is configured to run a computer program stored in the memory 802, and implement the following steps when executing the computer program:

obtaining the bus current output by the power supply to the driving circuit;

The specific principles and implementation manners of the power device provided in the embodiments of the present application are similar to the detection methods of the motors in the foregoing embodiments, and details are not described herein again.

Please refer to FIG. 10 in conjunction with the above embodiment. FIG. 10 is a schematic block diagram of a movable platform 900 provided by an embodiment of the present application.

Exemplarily, the movable platform 900 may include at least one of an unmanned aerial vehicle, a gimbal, an unmanned vehicle, and the like. Further, the unmanned aerial vehicle may be a rotary-wing drone, such as a quad-rotor drone, a hexa-rotor drone, an octa-rotor drone, or a fixed-wing drone.

Specifically, the movable platform 900 includes a motor 20 , a driving circuit 10 , and one or more processors 901 . It can be understood that the driving circuit 10 and the one or more processors 901 can be the driving circuit and the processor in the ESC device. The ESC device and the motor 20 are integrally provided or detachably connected, and one ESC device can be connected to One or more motors 20 . It can be understood that the processor 901 may also be a flight control system of an unmanned aerial vehicle, that is, a processor in a flight control.

Wherein, the driving circuit 10 is connected to the motor 20 and can provide a driving signal to the motor 20 to drive the motor 20 to rotate. The drive circuit 10 includes three half-bridge drivers, each of which includes a first power tube and a second power tube, and the first power tube is used to connect the positive pole of the power supply, and the second power tube is used to connect all the power tubes. the negative pole of the power supply.

Specifically, one or more processors 901 work individually or collectively to execute the steps of the aforementioned motor detection method.

Illustratively, removable platform 900 also includes memory 902 .

Exemplarily, the processor 901 and the memory 902 are connected through a bus 903, and the bus 903 is, for example, an I2C (Inter-integrated Circuit) bus.

Specifically, the processor 901 may be a micro-controller unit (Micro-controller Unit, MCU), a central processing unit (Central Processing Unit, CPU), or a digital signal processor (Digital Signal Processor, DSP) or the like.

Specifically, the memory 902 may be a Flash chip, a read-only memory (ROM, Read-Only Memory) magnetic disk, an optical disk, a U disk, a mobile hard disk, and the like.

The processor 901 is configured to run a computer program stored in the memory 902, and implement the aforementioned motor detection method when the computer program is executed.

Exemplarily, the processor 901 is configured to run a computer program stored in the memory 902, and implement the following steps when executing the computer program:

obtaining the bus current output by the power supply to the driving circuit;

The specific principles and implementation manners of the movable platform provided by the embodiments of the present application are similar to the detection methods of the motors in the foregoing embodiments, and details are not described herein again.

Embodiments of the present application further provide a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the processor enables the processor to implement the motor detection method provided by the foregoing embodiments A step of.

The computer-readable storage medium may be the control device described in any of the foregoing embodiments, such as an internal storage unit of an ESC device, such as a hard disk or a memory of the control device. The computer-readable storage medium may also be an external storage device of the control device, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) equipped on the control device ) card, Flash Card, etc. Alternatively, the computer-readable storage medium may be an internal storage unit or an external storage device of the aforementioned power plant or removable platform.

It should be understood that the terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the application.

It will also be understood that, as used in this application and the appended claims, the term "and/or" refers to and including any and all possible combinations of one or more of the associated listed items.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of various equivalents within the technical scope disclosed in the present application. Modifications or substitutions shall be covered by the protection scope of this application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A detection method for a motor, characterized in that the motor is connected to a drive circuit, the drive circuit includes three half-bridge drivers, each of the half-bridge drivers includes a first power tube and a second power tube, and the The first power tube is used for connecting the positive pole of the power supply, and the second power tube is used for connecting the negative pole of the power supply;

The detection method includes:

controlling the switching states of the first power transistor and the second power transistor driven by the three half-bridges according to the preset control logic;

obtaining the bus current output by the power supply to the driving circuit;

The fault state of the motor and/or the drive circuit is determined according to the bus current and the current threshold corresponding to the preset control logic.
The detection method according to claim 1, wherein when controlling the driving of each of the half bridges, one of the first power transistor and the second power transistor driven by the half bridge is controlled to be turned on, and the other is turned off.
The detection method according to claim 2, wherein the control power tube driving circuit sends out three pairs of complementary driving signals, and each pair of complementary driving signals includes two driving signals, and the two driving signals are used to control all the driving signals. One of the first power tube and the second power tube driven by the half-bridge is turned on, and the other is turned off.
The detection method according to claim 3, wherein the power tube driving circuit is controlled to send out three pairs of complementary driving signals through three control signals.
The detection method according to claim 3 or 4, wherein the detection method further comprises:

The power tube driving circuit is enabled, so that the power tube driving circuit can send the driving signal.
The detection method according to any one of claims 3-5, wherein the controlling the switching states of the first power transistors and the second power transistors driven by the three half-bridges comprises:

By setting the high-level duration of the driving signal sent by the power tube driving circuit, and/or enabling the power tube driving circuit, the first power tube or the second power tube is set to be turned on length of time.
The detection method according to any one of claims 3-6, wherein the control of the switching states of the first power transistor and the second power transistor driven by the three half-bridges comprises:

By setting the duty ratio of the driving signal sent by the power tube driving circuit, the switching states of the first power tube and the second power tube are controlled.
The detection method according to any one of claims 1 to 7, wherein the bus current output by the power supply to the drive circuit is obtained through a sampling resistor, and the sampling resistor is connected to the drive circuit and the drive circuit. between the positive or negative poles of the power supply.
The detection method according to any one of claims 1-8, wherein the fault state of the motor and/or the drive circuit includes: a short circuit and/or a failure of a circuit to be connected;

The current threshold for determining the short circuit fault condition is greater than the current threshold for determining the loop failure condition.
The detection method according to any one of claims 1-9, wherein the second power transistors driven by the three half-bridges are controlled to be turned on for a first preset duration, if the bus current is greater than or equal to the third A current threshold, determining that at least one of the first power transistors driven by the half-bridge is short-circuited.
The detection method according to any one of claims 1-10, wherein the first power transistor driven by one half-bridge is controlled to be turned on for a second preset duration and the second power transistors driven by the remaining two half-bridges are controlled It is turned on, and if the bus current is greater than or equal to the second current threshold, it is determined that a short-circuit fault occurs in the circuit corresponding to the first power transistor driven by one of the half-bridges.
The detection method according to claim 11, wherein the determining that a circuit corresponding to the first power transistor driven by one of the half-bridges has a short-circuit fault comprises:

It is determined that the second power tube corresponding to the first power tube that is turned on is short-circuited, the second power tube is short-circuited with the power supply, and/or the motor is short-circuited between phases.
The detection method according to any one of claims 1-12, wherein the first power transistor driven by one half-bridge is controlled to conduct for a third preset duration and the second power transistors driven by the remaining two half-bridges are controlled Conduction, if the bus current is less than or equal to the third current threshold, it is determined that the circuit of the motor and/or the driving circuit is not connected.
The detection method according to claim 13, wherein the determining that the circuit of the motor and/or the driving circuit is not connected includes:

It is determined that the first power transistor driven by one of the half bridges is not turned on under control, the second power transistors driven by the remaining two half bridges are not turned on under control, and/or the motor is out of phase.
The detection method according to claim 14, wherein the phase failure of the motor comprises:

One phase of the motor connected to the one of the half bridges is disconnected, and/or both phases of the motor connected to the other two half bridges are disconnected.
The detection method according to any one of claims 1-15, wherein the first power transistors driven by two half-bridges are controlled to be turned on for a fourth preset duration and the second power transistors driven by the remaining one half-bridge are controlled On, if the bus current is less than or below the fourth current threshold, it is determined that the circuit of the motor and/or the driving circuit is not connected.
The detection method according to claim 16, wherein the determining that the circuit of the motor and/or the driving circuit is not connected includes:

It is determined that the first power transistors driven by the two half-bridges are not turned on in a controlled manner, the second power transistors driven by the remaining one half-bridge are not controlled to be turned on, and/or the motor is out of phase.
The detection method according to claim 16, wherein the phase failure of the motor comprises:

Both the motor and the two phases drivingly connected to the two half-bridges are out of phase, and/or one phase of the motor and the remaining one half-bridge driving connection is out of phase.
The detection method according to claim 14 or 17, wherein the uncontrolled conduction of the first power tube comprises: a driving resistor of the first power tube is disconnected, a grid of the first power tube is disconnected and the source is disconnected, and/or the gate of the first power transistor is short-circuited to ground.
The detection method according to claim 14 or 17, wherein the uncontrolled conduction of the second power tube comprises:

The driving resistor of the second power tube is disconnected, the gate and source of the second power tube are disconnected, and/or the gate and drain of the second power tube are short-circuited.
The detection method according to any one of claims 10-20, wherein the preset duration of the conduction of the power tube when the short-circuit fault state is determined is smaller than the preset duration of the conduction of the power tube when it is determined that the circuit fails to be connected to the fault state duration.
The detection method according to any one of claims 1-21, wherein the drive circuit is one of multiple drive circuits of multiple motors;

Time-division detection of multiple motors and/or the drive circuits of each motor.
A control device for a motor, characterized in that the motor is connected to a drive circuit, the drive circuit includes three half-bridge drivers, each of the half-bridge drivers includes a first power tube and a second power tube, and the The first power tube is used for connecting the positive pole of the power supply, and the second power tube is used for connecting the negative pole of the power supply;

The control device includes:

One or more processors, working individually or collectively, to perform:

controlling the switching states of the first power transistor and the second power transistor driven by the three half-bridges according to the preset control logic;

obtaining the bus current output by the power supply to the driving circuit;

The fault state of the motor and/or the drive circuit is determined according to the bus current and the current threshold corresponding to the preset control logic.
The control device according to claim 23, wherein when controlling the driving of each half-bridge, one of the first power transistor and the second power transistor of the half-bridge driving is controlled to be turned on, and the other is turned off.
The control device according to claim 24, wherein the control device comprises a power tube drive circuit;

The processor is used to control the power tube drive circuit to send out three pairs of complementary drive signals, each pair of complementary drive signals includes two drive signals, and the two drive signals are used to control the first drive signal of the half-bridge drive. One of the power tube and the second power tube is turned on, and the other is turned off.
The control device according to claim 25, wherein the processor is configured to control the power tube drive circuit to send out three pairs of complementary drive signals through three control signals.
The control device according to claim 25 or 26, wherein the processor is further configured to:

The power tube driving circuit is enabled, so that the power tube driving circuit can send the driving signal.
The control device according to any one of claims 25-27, wherein when the processor controls the switching states of the first power transistor and the second power transistor, the processor is configured to execute:

By setting the high-level duration of the driving signal sent by the power tube driving circuit, and/or enabling the power tube driving circuit, the first power tube or the second power tube is set to be turned on length of time.
The control device according to any one of claims 25-28, wherein when the processor controls the switching states of the first power transistor and the second power transistor, the processor is configured to execute:

By setting the duty ratio of the driving signal sent by the power tube driving circuit, the switching states of the first power tube and the second power tube are controlled.
The control device according to any one of claims 23-29, wherein the bus current output by the power supply to the drive circuit is obtained through a sampling resistor, and the sampling resistor is connected to the drive circuit and the drive circuit. between the positive or negative poles of the power supply.
The control device according to any one of claims 23-30, wherein the fault state of the motor and/or the drive circuit includes: short circuit and/or failure of the circuit to be connected;

The current threshold for determining the short circuit fault condition is greater than the current threshold for determining the loop failure condition.
The control device according to any one of claims 23-31, wherein the processor is configured to execute:

The second power transistors driven by the three half-bridges are controlled to be turned on for a first preset duration, and if the bus current is greater than or equal to a first current threshold, it is determined that at least one of the first power transistors driven by the half-bridges is short-circuited.
The control device according to any one of claims 23-32, wherein the processor is configured to execute:

Control the first power tube driven by one of the half-bridges to be turned on for a second preset duration and the second power tubes driven by the remaining two half-bridges to be turned on, if the bus current is greater than or equal to the second current threshold, determine the among A circuit corresponding to the first power tube driven by a half-bridge is short-circuited.
The control device according to claim 33, wherein the determining that a circuit corresponding to the first power transistor driven by one of the half-bridges has a short-circuit fault comprises:

It is determined that the second power tube corresponding to the first power tube that is turned on is short-circuited, the second power tube is short-circuited with the power supply, and/or the motor is short-circuited between phases.
The control device according to any one of claims 23-34, wherein the processor is configured to execute:

Controlling the first power tube driven by one of the half-bridges to be turned on for a third preset duration and the second power tubes driven by the remaining two half-bridges being turned on, if the bus current is less than or equal to a third current threshold, determine the motor And/or the loop of the drive circuit fails to connect.
The control device according to claim 35, wherein the determining that the circuit of the motor and/or the driving circuit fails to communicate comprises:

It is determined that the first power transistor driven by one of the half bridges is not turned on under control, the second power transistors driven by the remaining two half bridges are not turned on under control, and/or the motor is out of phase.
The control device according to claim 36, wherein the phase failure of the motor comprises:

One phase of the motor connected to the one of the half bridges is disconnected, and/or both phases of the motor connected to the other two half bridges are disconnected.
The control device according to any one of claims 23-37, wherein the processor is configured to execute:

The first power transistors driven by two half-bridges are controlled to be turned on for a fourth preset duration and the second power transistors driven by the remaining one half-bridge are turned on. If the bus current is less than or below a fourth current threshold, determine the motor And/or the loop of the drive circuit fails to connect.
The control device according to claim 38, wherein the determining that the circuit of the motor and/or the driving circuit fails to communicate comprises:

It is determined that the first power transistors driven by the two half-bridges are not turned on in a controlled manner, the second power transistors driven by the remaining one half-bridge are not controlled to be turned on, and/or the motor is out of phase.
The control device according to claim 38, wherein the phase failure of the motor comprises:

Both the motor and the two phases drivingly connected to the two half-bridges are out of phase, and/or one phase of the motor and the remaining one half-bridge driving connection is out of phase.
The control device according to claim 36 or 39, wherein the uncontrolled conduction of the first power tube comprises: the driving resistor of the first power tube is disconnected, the grid of the first power tube is disconnected and the source is disconnected, and/or the gate of the first power transistor is short-circuited to ground.
The control device according to claim 36 or 39, wherein the second power tube is not controlled to be turned on, comprising:

The driving resistor of the second power tube is disconnected, the gate and source of the second power tube are disconnected, and/or the gate and drain of the second power tube are short-circuited.
The control device according to any one of claims 32-42, wherein the preset duration of the conduction of the power tube when the short-circuit fault state is determined is smaller than the preset duration of the conduction of the power tube when it is determined that the circuit fails to be connected to the fault state duration.
The control device according to any one of claims 23-43, wherein the drive circuit is one of a plurality of drive circuits of a plurality of motors;

The processor is also used to execute:

Time-division detection of multiple motors and/or the drive circuits of each motor.
An ESC device, characterized in that it includes:

A drive circuit can be connected to a motor, the drive circuit includes three half-bridge drivers, each of the half-bridge drivers includes a first power tube and a second power tube, and the first power tube is used to connect the positive pole of the power supply, so The second power tube is used to connect the negative pole of the power supply;

One or more processors, working individually or collectively, to perform:

controlling the switching states of the first power transistor and the second power transistor driven by the three half-bridges according to the preset control logic;

obtaining the bus current output by the power supply to the driving circuit;

The fault state of the motor and/or the drive circuit is determined according to the bus current and the current threshold corresponding to the preset control logic.
A power plant, characterized in that it includes:

motor;

a drive circuit, connected to the motor, the drive circuit includes three half-bridge drivers, each of the half-bridge drivers includes a first power tube and a second power tube, and the first power tube is used to connect the positive pole of the power supply, the second power tube is used for connecting the negative pole of the power supply;

One or more processors, working individually or collectively, to perform:

controlling the switching states of the first power transistor and the second power transistor driven by the three half-bridges according to the preset control logic;

obtaining the bus current output by the power supply to the driving circuit;

The fault state of the motor and/or the drive circuit is determined according to the bus current and the current threshold corresponding to the preset control logic.
A movable platform, characterized in that, comprising:

motor;

a drive circuit, connected to the motor, the drive circuit includes three half-bridge drivers, each of the half-bridge drivers includes a first power tube and a second power tube, and the first power tube is used to connect the positive pole of the power supply, the second power tube is used for connecting the negative pole of the power supply;

One or more processors, working individually or collectively, to perform:

controlling the switching states of the first power transistor and the second power transistor driven by the three half-bridges according to the preset control logic;

obtaining the bus current output by the power supply to the driving circuit;

The fault state of the motor and/or the drive circuit is determined according to the bus current and the current threshold corresponding to the preset control logic.
The movable platform according to claim 47, wherein the movable platform comprises at least one of the following: an unmanned aerial vehicle, a cloud platform, and an unmanned vehicle.
A computer-readable storage medium, characterized in that, the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor implements the method described in any one of claims 1-22. The detection method of the motor described above.