WO2022087866A1

WO2022087866A1 - Control device and control method of artificial intelligence (ai) chip, and controller

Info

Publication number: WO2022087866A1
Application number: PCT/CN2020/124241
Authority: WO
Inventors: 马玉利; 杜严俊; 谢中顺
Original assignee: 华为技术有限公司
Priority date: 2020-10-28
Filing date: 2020-10-28
Publication date: 2022-05-05
Also published as: CN116406490A

Abstract

A control device and control method of an artificial intelligence (AI) chip, and a controller, used for achieving flexible control of artificial intelligence cores (AICs) in an AI chip and improving the utilization rate of the AICs in the AI chip, thereby improving user experience. In the control device of the AI chip, the AI chip comprises N AICs, N being an integer greater than one. The device comprises: a controller and a inhibit circuit connected to the controller. The controller is configured to determine that the number of AICs allowed to be enabled among the N AICs is a first number, and to generate a control command according to the first number and then send the control command to the inhibit circuit. The inhibit circuit is connected to the N AICs and is configured to enable or disable at least one of the N AICs according to the control command.

Description

Control device, control method and controller of artificial intelligence AI chip

technical field

The embodiments of the present application relate to the field of artificial intelligence AI, and in particular, to a control device, a control method, and a controller of an artificial intelligence AI chip.

Background technique

Artificial intelligence (AI) is a theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a branch of computer science that attempts to understand the essence of intelligence and produce a new kind of intelligent machine that responds in a similar way to human intelligence. Artificial intelligence is to study the design principles and implementation methods of various intelligent machines, so that the machines have the functions of perception, reasoning and decision-making. Research in the field of artificial intelligence includes robotics, natural language processing, computer vision, decision-making and reasoning, human-computer interaction, recommendation and search, and basic AI theory.

At present, there may be different computing power requirements in different application scenarios. Hardware manufacturers generally design an AI chip that can meet different application scenarios at the same time, and divide the chips into chips with different specifications for different application scenarios. Open computing project accelerator module (open compute project accelerator module, OAM or OCP acceleration module) and high-speed peripheral component interconnect express (PCI-Express or PCIE) card, two common AI basic hardware units in the industry , respectively as an example of a high-specification chip and a low-specification chip.

Among them, the PCIE card follows the traditional PCIE interface, which has good inheritance and can be directly inserted into existing servers and desktops to quickly provide AI acceleration with low cost. The disadvantage is that the power consumption is limited, and a single card has a maximum of 250 to 300 watts (W); and the number of interfaces is limited, with only one set of PCIE X16 interfaces; Channel (Gbps/lane), low computing power. In addition, OAM is specially tailored for AI and can support higher power consumption (such as 700W), more interfaces (such as 8 sets of X16 interfaces), wider speed (such as 112Gbps/lane), and higher computing power. force. The disadvantage is that it cannot be directly inserted into the existing server, the server needs to be redesigned, and the compatibility between various manufacturers is not as good as that of PCIE, and the cost is higher.

Generally, for sales strategy or other reasons (such as chip yield), chips need to be divided into high and low grades for the above two scenarios, which are respectively recorded as NPU_OAM and NPU_PCIE. As shown in Figure 1, when the AI chip is shipped from the factory, each AIC in the AI chip is set with an enable switch (Open). The AIC can be turned off by configuring Open=0, and the AIC can be turned on by configuring Open=1. In addition, a (pass) in each AIC indicates that the AIC is functionally intact. For the OAM of the high specification file that needs to use 36 AICs, the Open configuration of all AICs shown in Figure 1 is 1; for the low specification file NPU_PCIE that needs to use 25 AICs, the Open configuration of only a part of the AICs is 1, and the other The Open configuration of AIC is 0. For a terminal device using the AI chip, the terminal device reads the Open configuration (0 or 1) corresponding to each AIC in the AI chip, and controls each AIC to be turned on or off according to the configuration.

However, in the configuration mode shown in Figure 1, after the AI chip has been working for a period of time, if the AIC whose Open configuration is 1 is partially damaged, as shown in Figure 2 AIC_01 (fail), the performance of the AIC_01 chip is degraded or unavailable. , the terminal equipment using this AI chip must be disassembled to replace the entire AI chip. Although the AIC with the Open configuration of 0 in the AI chip is not damaged, the terminal device is limited to the factory configuration of the Open and cannot be used. As a result, the utilization rate of the AIC of the AI chip in this configuration is low, which affects the user experience.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a control device, a control method, and a controller for an artificial intelligence AI chip, which are used to achieve flexible control of the AIC in the AI chip and at the same time improve the utilization rate of the AIC in the AI chip, thereby improving user experience.

A first aspect of the embodiments of the present application provides a control device for an artificial intelligence AI chip. The AI chip includes N artificial intelligence cores AIC, where N is an integer greater than 1. The device includes: a controller, and a controller connected to the AI chip. The prohibition circuit of the controller; the controller is used to determine that the number of AICs allowed to be opened in the N AICs is the first number, and after generating a control command according to the first number, send the control command to the prohibition circuit; after that, the A prohibiting circuit is connected to the N AICs, and is used for turning on or off at least one AIC of the N AICs according to the control instruction.

Based on the above technical solution, in the control device of the AI chip, the controller uses the number of AICs allowed to be opened among the N AICs in the AI chip as the basis for generating a control command, and disables the circuit to perform opening or closing of at least one of the N AICs. an AIC. Compared with the way of controlling the opening or closing of each AIC by configuring the Open of each AIC to 1 or 0, the opening or closing of at least one of the N AICs can be flexibly controlled according to the number of AICs allowed to be opened in the N AICs. On or off. To avoid the situation that when part of the AIC whose Open configuration is 1 is damaged and the chip performance is degraded or unavailable, the entire AI chip must be disassembled and replaced, resulting in a low utilization rate of the AIC in the AI chip. While realizing the flexible control of the AIC in the AI chip , to improve the utilization of AIC in the AI chip, thereby improving the user experience.

In a specific implementation of the first aspect of the embodiment of the present application, the device further includes a quantity limiter connected to the controller; wherein the quantity limiter is used to limit the number of AICs allowed to be opened among the N AICs is the first quantity; at this time, the controller is specifically configured to determine the first quantity through the quantity limiter.

Based on the above technical solutions, in the AI control device, the number of AICs that are allowed to be opened in the N AICs can be limited by hardware, that is, in the control device of the AI chip, there is also a method for limiting the AICs that are allowed to be opened in the N AICs. The quantity of AICs is the quantity limiter of the first quantity, that is, the controller can specifically determine the first quantity through the quantity limiter. While providing a specific implementation manner for the controller to determine the first quantity, the security of limiting the first quantity can be improved by means of hardware limitation of the quantity controller.

In a specific implementation of the first aspect of the embodiment of the present application, the quantity limiter includes at least one electronic fuse efuse, and the quantity limiter is used to limit the allowable number of the N AICs through the output level of the at least one efuse The number of open AICs is the first number.

Based on the above technical solution, the quantity limiter can specifically limit the first quantity by burning at least one efuse, that is, limiting the number of AICs allowed to be opened among the N AICs by the output level of at least one efuse to be the A quantity, a specific implementation manner in which the quantity limiter limits the first quantity is provided, which improves the achievability of the solution.

In a specific implementation of the first aspect of the embodiment of the present application, when the blown state of the at least one efuse is blown, the output level of the at least one efuse is the first level; and/or, in the When the blown state of at least one efuse is not blown, the output level of the at least one efuse is a second level; wherein, the first level is different from the second level.

Based on the above technical solution, different fuse states of at least one efuse can correspond to different output levels, so that the quantity limiter can limit the first quantity through different output levels of the at least one efuse, providing the quantity limiter to pass at least one A specific implementation of efuse limiting the first number to improve the achievability of the solution.

In a specific implementation manner of the first aspect of the embodiment of the present application, the apparatus further includes an accumulator connected to the controller; wherein the accumulator is connected to the N AICs, and is used to count the opened AICs among the N AICs. The number of AICs is the second number; at this time, the controller is specifically configured to generate the control instruction according to the first number and the second number.

Based on the above technical solution, the control device of the AI chip may further include an accumulator for counting the number of opened AICs in the N AICs as the second number, that is, the controller can obtain the second number in real time through the accumulator , and based on the first quantity and the second quantity, a control instruction sent to the prohibiting circuit is generated. That is, the controller combines the number of AICs allowed to be opened and the number of AICs that have been opened in the N AICs to open or close at least one AIC of the N AICs, and further optimize the control of the N AICs during the use of the AI chip. .

In a specific implementation of the first aspect of the embodiment of the present application, the accumulator is specifically used to connect the non-faulty AICs in the N AICs, and the second number is used to indicate the opened AICs in the non-faulty AICs quantity.

Based on the above technical solution, the accumulator can specifically avoid the faulty AICs among the N AICs, that is, the number of the opened AICs among the non-faulty AICs among the N AICs is counted as the second number, thereby preventing the controller from issuing the open AICs. Instructions are sent to the failed AIC to further optimize the control of the AI chip.

In a specific implementation manner of the first aspect of the embodiment of the present application, the AI chip includes an image processing unit GPU, a neural processing unit NPU, or a tensor processing unit TPU.

Based on the above technical solutions, the AI chip can be applied to a variety of different application scenarios, such as CPU, NPU, TPU or other AI application scenarios, to improve the applicability of the solution.

A second aspect of the embodiments of the present application provides a method for controlling an artificial intelligence AI chip, wherein the method is applied to a controller in a control device for the AI chip, and the device further includes a prohibition circuit, wherein the AI chip It includes N artificial intelligence core AICs, where N is an integer greater than 1. The method includes: the controller first determines that the number of AICs allowed to be opened in the N AICs is a first number; then, the controller determines according to the first number of AICs. The number generates a control instruction, the control instruction is used to instruct to open or close at least one AIC of the N AICs; finally, the controller sends the control instruction to the prohibition circuit.

Based on the above technical solution, in the control device of the AI chip, the controller uses the number of AICs allowed to be opened among the N AICs in the AI chip as the basis for generating the control command, and sends the control command to the prohibition circuit, so that the prohibition circuit executes Turn on or off at least one AIC of the N AICs. Compared with the way of controlling the opening or closing of each AIC by configuring the Open of each AIC to 1 or 0, the opening or closing of at least one of the N AICs can be flexibly controlled according to the number of AICs allowed to be opened in the N AICs. On or off. To avoid the situation that when part of the AIC whose Open configuration is 1 is damaged and the chip performance is degraded or unavailable, the entire AI chip must be disassembled and replaced, resulting in a low utilization rate of the AIC in the AI chip. While realizing the flexible control of the AIC in the AI chip , to improve the utilization of AIC in the AI chip, thereby improving the user experience.

In a specific implementation of the second aspect of the embodiment of the present application, the device further includes a quantity limiter, and the quantity limiter is used to limit the number of AICs allowed to be opened among the N AICs to be the first number; The controller determining that the number of AICs allowed to be opened among the N AICs is the first number includes: the controller determines, through the number limiter, that the number of AICs that are allowed to be opened among the N AICs is the first number.

In a specific implementation of the second aspect of the embodiment of the present application, the apparatus further includes an accumulator, and the accumulator is used to count the number of opened AICs in the N AICs as the second number; Before the instruction, the method further includes: determining the second quantity through the accumulator; wherein, the controller generating the control instruction according to the first quantity includes: the controller generating the control instruction according to the first quantity and the second quantity.

In a specific implementation manner of the second aspect of the embodiment of the present application, the second number is used to indicate the number of AICs that have been opened in the non-faulty AICs of the N AICs.

In a specific implementation manner of the second aspect of the embodiment of the present application, the AI chip includes an image processing unit GPU, a neural processing unit NPU, or a tensor processing unit TPU.

A third aspect of the embodiments of the present application provides a controller of an artificial intelligence AI chip, the controller is included in a control device of the AI chip, and the control device further includes a prohibition circuit, wherein the AI chip includes N artificial intelligence cores AIC, where N is an integer greater than 1, and the controller includes:

determining unit, the number of AICs allowed to be opened in the N AICs is the first number;

a generating unit, configured to generate a control instruction according to the first number, the control instruction being used to instruct to open or close at least one AIC in the N AICs;

The sending unit is used for sending the control instruction to the prohibiting circuit.

In a specific implementation of the third aspect of the embodiment of the present application, the device further includes a quantity limiter, and the quantity limiter is used to limit the number of AICs allowed to be opened among the N AICs to a first number;

The determining unit is specifically configured to determine, through the quantity limiter, the number of AICs allowed to be opened among the N AICs as the first number.

In a specific implementation of the third aspect of the embodiment of the present application, the device further includes an accumulator, and the accumulator is used to count the number of AICs that have been opened in the N AICs to be the second number;

The determining unit is further configured to determine the second quantity through the accumulator;

The generating unit is specifically configured to generate the control instruction according to the first quantity and the second quantity.

In a specific implementation of the third aspect of the embodiment of the present application, the second number is used to indicate the number of AICs that have been opened in the non-faulty AICs of the N AICs.

In a specific implementation manner of the third aspect of the embodiment of the present application, the AI chip includes an image processing unit GPU, a neural processing unit NPU, or a tensor processing unit TPU.

In the third aspect of the embodiment of the present application, the component modules of the controller may also be used to perform the steps performed in each possible implementation manner of the second aspect. For details, refer to the second aspect, which will not be repeated here.

A fourth aspect of the embodiments of the present application provides a controller, the controller includes at least one processor, a memory, a communication port, and computer-executable instructions stored in the memory and executable on the processor, when the computer executes the instructions When executed by the processor, the processor executes the method described in the second aspect or any of the possible implementation manners of the second aspect.

A fifth aspect of the embodiments of the present application provides a computer-readable storage medium that stores one or more computer-executable instructions. When the computer-executable instructions are executed by a processor, the processor executes the above-mentioned second aspect or the second aspect. The method described in any possible implementation manner of the aspect.

A sixth aspect of the embodiments of the present application provides a computer program product that stores one or more computer-executable instructions. When the computer-executable instructions are executed by the processor, the processor executes the second aspect or the second aspect A method of any possible implementation.

A seventh aspect of the present application provides a chip system, where the chip system includes a processor for supporting the controller to implement the functions involved in the second aspect or any possible implementation manner of the second aspect. In a possible design, the chip system may further include a memory for storing necessary program instructions and data. The chip system may be composed of chips, or may include chips and other discrete devices.

Wherein, for the technical effects brought by the third aspect to the seventh aspect or any one of the possible implementation manners, reference may be made to the technical effects brought by the second aspect or different possible implementation manners of the second aspect, which will not be repeated here.

It can be seen from the above technical solutions that the embodiments of the present application have the following advantages: in the control device of the AI chip, the controller uses the number of AICs that are allowed to be opened among the N AICs in the AI chip as the basis for generating control instructions, and disables the circuit by prohibiting the circuit. Turning on or off at least one AIC of the N AICs is performed. Compared with the way of controlling the opening or closing of each AIC by configuring the Open of each AIC to 1 or 0, the opening or closing of at least one of the N AICs can be flexibly controlled according to the number of AICs allowed to be opened in the N AICs. On or off. To avoid the situation that when part of the AIC whose Open configuration is 1 is damaged and the chip performance is degraded or unavailable, the entire AI chip must be disassembled and replaced, resulting in a low utilization rate of the AIC in the AI chip. While realizing the flexible control of the AIC in the AI chip , to improve the utilization of AIC in the AI chip, thereby improving the user experience.

Description of drawings

Fig. 1 is a schematic diagram of AI chip implementation;

Fig. 2 is another schematic diagram of AI chip implementation;

3 is a schematic diagram of an artificial intelligence main body framework provided by an embodiment of the present application;

Fig. 4 is another schematic diagram of AI chip implementation;

5 is a schematic diagram of a control device for an AI chip provided by an embodiment of the present application;

6 is another schematic diagram of a control device for an AI chip provided by an embodiment of the present application;

7 is another schematic diagram of a control device for an AI chip provided by an embodiment of the present application;

8 is another schematic diagram of a control device for an AI chip provided by an embodiment of the present application;

9 is another schematic diagram of a control device for an AI chip provided by an embodiment of the present application;

FIG. 10-1 is a schematic diagram of a method for sieving an AI chip provided by an embodiment of the application;

10-2 is a schematic diagram of a usage flow of a control device for an AI chip provided by an embodiment of the application;

11-1 is a schematic diagram of an application of a control device for an AI chip provided by an embodiment of the application;

11-2 is another schematic diagram of the application of a control device for an AI chip provided by an embodiment of the application;

12 is another schematic diagram of a control method of an AI chip provided by an embodiment of the present application;

FIG. 13 is a schematic diagram of a controller according to an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application.

Figure 3 shows a schematic diagram of an artificial intelligence main frame, the main frame describes the overall workflow of the artificial intelligence system, and is suitable for general artificial intelligence field requirements.

The above artificial intelligence theme framework will be explained from the two dimensions of "intelligent information chain" (horizontal axis) and "IT value chain" (vertical axis).

The "intelligent information chain" reflects a series of processes from data acquisition to processing. For example, it can be the general process of intelligent information perception, intelligent information representation and formation, intelligent reasoning, intelligent decision-making, intelligent execution and output. In this process, data has gone through the process of "data-information-knowledge-wisdom".

The "IT value chain" reflects the value brought by artificial intelligence to the information technology industry from the underlying infrastructure of human intelligence, information (providing and processing technology implementation) to the industrial ecological process of the system.

(1) Infrastructure:

The infrastructure provides computing power support for artificial intelligence systems, realizes communication with the outside world, and supports through the basic platform. Communication with the outside world through sensors; computing power is provided by smart chips (hardware acceleration chips such as CPU, NPU, GPU, ASIC, FPGA); the basic platform includes distributed computing framework and network-related platform guarantee and support, which can include cloud storage and computing, interconnection networks, etc. For example, sensors communicate with external parties to obtain data, and these data are provided to the intelligent chips in the distributed computing system provided by the basic platform for calculation.

(2) Data

The data on the upper layer of the infrastructure is used to represent the data sources in the field of artificial intelligence. The data involves graphics, images, voice, and text, as well as IoT data from traditional devices, including business data from existing systems and sensory data such as force, displacement, liquid level, temperature, and humidity.

(3) Data processing

Data processing usually includes data training, machine learning, deep learning, search, reasoning, decision-making, etc.

Among them, machine learning and deep learning can perform symbolic and formalized intelligent information modeling, extraction, preprocessing, training, etc. on data.

Reasoning refers to the process of simulating human's intelligent reasoning method in a computer or intelligent system, using formalized information to carry out machine thinking and solving problems according to the reasoning control strategy, and the typical function is search and matching.

Decision-making refers to the process of making decisions after intelligent information is reasoned, usually providing functions such as classification, sorting, and prediction.

(4) General ability

After the above-mentioned data processing, some general capabilities can be formed based on the results of data processing, such as algorithms or a general system, such as translation, text analysis, computer vision processing, speech recognition, image identification, etc.

(5) Smart products and industry applications

Intelligent products and industry applications refer to the products and applications of artificial intelligence systems in various fields. They are the encapsulation of the overall artificial intelligence solution, and the productization of intelligent information decision-making and implementation of applications. Its application areas mainly include: intelligent manufacturing, intelligent transportation, Smart home, smart medical care, smart security, autonomous driving, safe city, smart terminals, etc.

In recent years, with the development of advanced technologies such as 7nm, the revolutionary innovation of NPU computing architecture, and the continuous introduction of new algorithm architectures, AI computing power has grown exponentially year by year, and AI has ushered in a new round of vigorous development. AI is used in safe cities, pharmaceutical research and development, weather forecasting, autonomous driving, e-commerce and other fields. Taking the schematic diagram of the main frame of artificial intelligence shown in Figure 3 as an example, there are many application scenarios in the current AI field, and different application scenarios may have different computing power requirements. AI chips are divided into chips of different specifications for different application scenarios. Open computing project accelerator module (open compute project accelerator module, OAM or OCP acceleration module) and high-speed peripheral component interconnect express (PCI-Express or PCIE) card, two common AI basic hardware units in the industry , respectively as an example of a high-specification chip and a low-specification chip.

It is expected that OAM and PCIE cards will coexist in the market for a long time. In addition, OAM can be further divided into liquid-cooled OAM with higher specifications and air-cooled OAM with lower specifications. Compared with PCIE, air-cooled OAM It is a high-grade chip. In order to reduce investment, the general practice of chip manufacturers is to design an AI chip that can meet the application requirements of OAM and PCIE cards at the same time. For sales strategy or other reasons (such as chip yield), chips need to be divided into high and low grades for two scenarios, denoted as NPU_OAM and NPU_PCIE.

For example, as shown in Figure 4, an NPU/GPU chip has 36 built-in AICs, and OAM scenarios (such as OAM) support all of them. Low-specification scenarios (such as PCIE cards) have limited power and heat dissipation, and can only support 25 AICs. NPU_OAM opens all 36 AICs to users, and NPU_PCIE only opens 25 AICs in the yellow part.

Based on the AI chip shown in FIG. 4 , the control modes of the multiple AICs included in it may be as shown in FIG. 1 . When the AI chip is shipped from the factory, an enable switch (Open) is set for each AIC in the AI chip. The AIC can be turned off by configuring Open=0, and the AIC can be turned on by configuring Open=1. In addition, in each AIC The (pass) indicates that the AIC function is intact. For the OAM of the high specification file that needs to use 36 AICs, the Open configuration of all AICs shown in Figure 1 is 1; for the low specification file NPU_PCIE that needs to use 25 AICs, the Open configuration of only a part of the AICs is 1, and the other The Open configuration of AIC is 0. For a terminal device using the AI chip, the terminal device reads the Open configuration (0 or 1) corresponding to each AIC in the AI chip, and controls each AIC to be turned on or off according to the configuration.

In addition, in the configuration mode shown in Figure 1, after the AI chip has been working for a period of time, if the AIC whose Open configuration is 1 is partially damaged, as shown in Figure 2 AIC_01 (fail), the performance of the AIC_01 chip is degraded or unavailable. , the terminal equipment using this AI chip must be disassembled to replace the entire AI chip.

It can be seen from the above configuration methods that the control methods of multiple AICs in the current AI chip include at least the following technical problems:

Question 1. In low-specification AI chips, limiting the number of AI chips used is shielded by software, which is easy to be cracked and affects the sales strategy of different grades;

Question 2. As shown in Figure 2, although there is an AIC with an Open configuration of 0 in the AI chip and it is not damaged, the terminal device is limited to the factory configuration of the Open and cannot be used. As a result, the utilization rate of the AIC of the AI chip in this configuration mode is low, which affects the user experience.

In order to solve the above problems, the embodiments of the present application provide a control device, a control method and a controller for an artificial intelligence AI chip, which are used to realize the flexible control of the AIC in the AI chip and at the same time improve the utilization rate of the AIC in the AI chip, thereby Improve user experience.

Referring to FIG. 5 , a control device for an AI chip provided by an embodiment of the present application includes:

a controller, and an inhibiting circuit connected to the controller;

The controller is used to determine the number of AICs allowed to be opened among the N AICs as the first number, and after generating a control command according to the first number, send the control command to the prohibition circuit; the prohibition circuit interconnected with the controller It is connected to the N AICs in the AI chip, and is used for turning on or off at least one AIC in the N AICs according to the control instruction.

It should be noted that, in this embodiment and subsequent embodiments, the AI chip may include an image processing unit GPU, a neural processing unit NPU, or a tensor processing unit TPU, that is, the AI chip may be applicable to a variety of different application scenarios, such as CPU , NPU, TPU, or other AI application scenarios, which are not specifically limited here.

In this embodiment, in the control device of the AI chip, the controller uses the number of AICs allowed to be opened among the N AICs in the AI chip as the basis for generating the control command, and disables the circuit to perform opening or closing of at least one of the N AICs. an AIC. Compared with the way of controlling the opening or closing of each AIC by configuring the Open of each AIC to 1 or 0, the opening or closing of at least one of the N AICs can be flexibly controlled according to the number of AICs allowed to be opened in the N AICs. On or off. To avoid the situation that when part of the AIC whose Open configuration is 1 is damaged and the chip performance is degraded or unavailable, the entire AI chip must be disassembled and replaced, resulting in a low utilization rate of the AIC in the AI chip. While realizing the flexible control of the AIC in the AI chip , to improve the utilization of AIC in AI chips.

In addition, based on the embodiment shown in FIG. 5 , in addition to the controller and the prohibition circuit, the control device of the AI chip can be further optimized. Referring to FIG. 6 , an embodiment of the present application provides a control device for an AI chip.

In a specific implementation manner, as shown in FIG. 6 , the device further includes a quantity limiter connected to the controller; wherein, the quantity limiter is used to limit the number of AICs allowed to be opened among the N AICs to be the first a quantity; at this time, the controller is specifically configured to determine the first quantity through the quantity limiter.

Specifically, in the AI control device, the number of AICs allowed to be opened among the N AICs can be limited by means of hardware, that is, in the control device of the AI chip, the number of AICs allowed to be opened among the N AICs is also limited. The quantity is the quantity limiter of the first quantity, that is, the controller can specifically determine the first quantity through the quantity limiter. While providing a specific implementation manner for the controller to determine the first quantity, the security of limiting the first quantity can be improved by means of hardware limitation of the quantity controller.

In a specific implementation manner, as shown in FIG. 6 , the apparatus further includes an accumulator connected to the controller; wherein, the accumulator is connected to the N AICs for counting the opened AICs in the N AICs The quantity is the second quantity; at this time, the controller is specifically configured to generate the control instruction according to the first quantity and the second quantity.

Specifically, the control device of the AI chip may further include an accumulator for counting the number of opened AICs among the N AICs as the second number, that is, the controller may obtain the second number in real time through the accumulator, and A control command sent to the inhibiting circuit is generated based on the first number and the second number. That is, the controller combines the number of AICs allowed to be opened and the number of AICs that have been opened in the N AICs to open or close at least one AIC of the N AICs, and further optimize the control of the N AICs during the use of the AI chip. .

In addition, the accumulator is specifically used to connect the non-faulty AICs among the N AICs, and the second number is used to indicate the number of opened AICs in the non-faulty AICs. That is to say, the accumulator can specifically avoid the faulty AICs among the N AICs, that is, the number of opened AICs among the non-faulty AICs among the N AICs is counted as the second number, thereby preventing the controller from issuing an opening command To the faulty AIC, the control of the AI chip is further optimized.

In the following, the number N of AICs in the AI chip is 36 for exemplary description. Please refer to FIG. 7 , which is a schematic diagram of a control apparatus for an AI chip provided in an embodiment of the present application.

In the apparatus shown in FIG. 7, a comparator (ie, a controller) is included, and a quantity limiter, an accumulator and a prohibition circuit interconnected with the comparator are included.

Among them, the AIC controls the switch Open, and an open flag open can be set in each AIC, which is configurable by software, and its value can only be 0 or 1. 0 means close the AIC, and 1 means open. The control process of the device shown in FIG. 7 in executing the AI chip includes the following contents.

The number limiter is used to limit the number of AICs allowed to be opened among the N AICs to the first number (referred to as Open_sum), and send Open_sum to the comparator, that is, the open_sum threshold of the number of AICs, the value is 25, the hardware is hard-coded, and the software only Can read but not write;

The accumulator is used to count the number of AICs that have been opened in the N AICs as the second number (recorded as sum), that is, the accumulator of the number of AICs opened, count the open value, and output the sum;

The controller is used to generate the control instruction (referred to as over) according to the first quantity and the second quantity, that is, the AIC turns on the quantity comparator, when sum>=Open_sum, the output overflow indication over=1, when sum<Open_sum, output overflow indication over=0;

The prohibition circuit is connected to the N AICs in the AI chip, and is used to turn on or off at least one AIC in the N AICs according to the control instruction, that is, the AIC turns on the prohibition circuit. When over is 1, it is prohibited to turn on a new AIC. When over is 0, a new AIC is allowed to be opened;

Among them, through the control device of the AI chip shown in FIG. 7, the sum of the number of open=1 of the AIC in the AI chip can be less than or equal to open_sum, so that the total number of AICs that can be opened is controlled by hardware, and the total number cannot be changed by software—avoid software crack.

A specific implementation of the quantity limiter shown in FIG. 6 by hardware may be implemented by an electronic fuse (efuse). Wherein, the quantity limiter includes at least one electronic fuse efuse, and the quantity limiter is used to limit the number of AICs allowed to be opened among the N AICs to the first quantity through the output level of the at least one efuse.

Specifically, the quantity limiter can specifically limit the first quantity by burning at least one efuse, that is, limiting the number of AICs allowed to be opened among the N AICs to the first quantity by the output level of at least one efuse .

Wherein, when the blown state of the at least one efuse is blown, the output level of the at least one efuse is the first level; and/or, when the blown state of the at least one efuse is not blown, the at least one efuse The output level of is a second level; wherein, the first level is different from the second level. That is, different fusing states of the at least one efuse may correspond to different output levels, so that the quantity limiter can limit the first quantity through different output levels of the at least one efuse.

In the following, when the blown state of at least one efuse is blown, the output level of the at least one efuse is the first level corresponding to the high level, and when the blown state of at least one efuse is not blown, the output level of the at least one efuse is not blown. An example is given for the realization that the second level corresponds to the low level.

As shown in FIG. 8 , a specific implementation manner of the quantity controller in the embodiment of the present application may be implemented by at least one efuse shown in FIG. 7 . In Figure 7, when the efuse is blown, the corresponding output is high level (ie "1"), other efuses are not blown, and the corresponding output is low level (ie "0"). Make the quantity controller output to the controller through the at least one efuse that the number of AICs allowed to be opened among the N AICs is the first number, that is, "011001", and the corresponding total output is 25, that is, it indicates that the number of AICs allowed to be opened among the N AICs is the first number. The number of AICs is 25.

In addition, a schematic diagram of an implementation of the inhibit circuit can be shown in FIG. 9 . In FIG. 9 , the inhibiting circuit includes at least a configuration interface and a plurality of switches.

In the implementation process of the prohibition circuit shown in Figure 9, when over=1, open=0, the switch is turned off, and the configuration interface cannot modify the open value, that is, a new AIC cannot be opened; when over=1, open=1, When the switch is turned on, the configuration interface can modify the open value, that is, the opened AIC can be closed; when over=0, open=0/1, the switch is turned on, and the configuration interface can modify the open value, that is, a new AIC can be opened.

The following will exemplify the sieving process of the AI chip by taking the control device of the AI chip applied to the scenario where the AI chip is an NPU as an example. As shown in Figure 10-1, in the AI control device, AIC_O is the minimum AIC quantity that satisfies the OAM, and AIC_P is the minimum AIC quantity that satisfies the PCIE card. The total number of AICs is recorded as AIC_A, and the relationship among the three is AIC_A>=AIC_O>=AIC_P. For ease of understanding, this paper takes AIC_A=AIC_O=36 and AIC_P=25. For the PCIE card scenario, the normal number of AICs >= AIC_P, that is, there is a surplus of AICs, which is suitable for similar high-end and low-use scenarios.

Through the sieving process in Figure 10-1, when the normal number of AICs corresponding to the NPU chip>=AIC_O, it can be determined that the model of the NPU chip is set to NPU_OAM; when the normal number of AICs corresponding to the NPU chip<AIC_O and the normal number of AICs>= When AIC_P, it can be determined that the model of the NPU chip is set to NPU_PCIE; and when the normal number of AICs corresponding to the NPU chip < AIC_P, it can be determined that the NPU chip is a waste chip, that is, it cannot be used by OAM or PCIE devices.

Exemplarily, after the AI chip is screened, in the process of using the AI chip, the control device of the AI chip shown in any of the foregoing embodiments can be used to control the use of the AI chip. Please refer to FIG. 10-2 , which is a schematic flowchart of a control device using an AI chip to control the AI chip in an embodiment of the present application.

Through the process shown in Figure 10-2, the model of the AI chip is PCIE. At this time, the controller can determine the number of AICs allowed to be opened among the N AICs as the first number, that is, AIC_P; and the controller can also determine the number of AICs among the N AICs. The number of opened AICs is the second number and is recorded as sum(Open), and sum(Open) is accumulated and assigned to open_sum.

When the number of open AICs in the current N AICs is open_sum<AIC_P, it is determined that new AICs can be opened (that is, allowed); when the number of open AICs in the current N AICs is open_sum=AIC_P, it is determined that it is forbidden to open new AICs AIC; when the number of open AICs in the current N AICs is open_sum > AIC_P, it is determined to close the AICs.

The specific implementation scenario can be shown in Figure 11-1. When all AICs are normal, you can choose to open_sum AICs (for example, open AIC_00 to AIC_04, AIC_10 to AIC_14, AIC_20 to AIC_24, AIC_30 to AIC_34, AIC_40 to AIC_44); as shown in Figure 11- 2. When one or more AICs are faulty, close them (for example, set AIC_01 from Open=1 to Open=0), select other normal AICs to open (for example, avoid the faulty AIC_01, and choose to open AIC_05 ).

The control device of the AI chip in the embodiment of the present application has been described above, and the following will be introduced from the perspective of the control method of the AI chip.

Referring to FIG. 12 , a method for controlling an AI chip in an embodiment of the present application includes the following steps.

The method is applied to a controller in a control device of the AI chip, and the control device further includes a prohibiting circuit, wherein the AI chip includes N artificial intelligence core AICs, where N is an integer greater than 1, and the method includes:

S101. Determine that the number of AICs allowed to be opened in the N AICs is a first number;

S102. Generate a control instruction according to the first quantity, where the control instruction is used to instruct to open or close at least one AIC in the N AICs;

S103. Send the control instruction to the prohibition circuit.

Based on the above technical solution, in the control device of the AI chip, the controller uses the number of AICs allowed to be opened among the N AICs in the AI chip as the basis for generating the control command, and sends the control command to the prohibition circuit, so that the prohibition circuit executes Turn on or off at least one AIC of the N AICs. Compared with the way of controlling the opening or closing of each AIC by configuring the Open of each AIC as 1 or 0, it is possible to flexibly control the opening or closing of at least one of the N AICs according to the number of AICs allowed to be opened in the N AICs. On or off. To avoid the situation that when part of the AIC whose Open configuration is 1 is damaged and the chip performance is degraded or unavailable, the entire AI chip must be disassembled and replaced, resulting in a low utilization rate of the AIC in the AI chip. While realizing the flexible control of the AIC in the AI chip , to improve the utilization of AIC in the AI chip, thereby improving the user experience.

In a specific implementation manner, before generating the control instruction in step S101, the method further includes:

determining a first number, where the first number is the number of AICs allowed to be opened in the N AICs;

Generating a control instruction in this step S101 includes:

The control instruction is generated according to the first number.

determining a second number, where the second number is the number of opened AICs in the N AICs;

Generating a control instruction in this step S101 includes:

The control instruction is generated according to the first quantity and the second quantity.

In a specific implementation manner, the second number is used to indicate the number of opened AICs among the non-faulty AICs of the N AICs.

In a specific implementation manner, the N AICs include N image processing units GPU, N neural processing units NPU or N tensor processing units TPU.

The control method of the AI chip implemented by the controller is described above, and the controller 1300 provided by the embodiment of the present application is described below with reference to the accompanying drawings.

Referring to FIG. 13 , an embodiment of the present application provides a controller 1300 of an artificial intelligence AI chip, the controller 1300 is included in a control device of the AI chip, and the control device further includes a prohibition circuit, wherein the AI chip includes N an artificial intelligence core AIC, where N is an integer greater than 1, and the controller includes:

Determining unit 1301, the number of AICs allowed to be opened in the N AICs is the first number;

A generating unit 1302, configured to generate a control instruction according to the first number, the control instruction being used to instruct to open or close at least one AIC in the N AICs;

The sending unit 1303 is configured to send the control instruction to the prohibiting circuit.

In a specific implementation manner, the device further includes a quantity limiter, and the quantity limiter is used to limit the number of AICs allowed to be opened among the N AICs to a first number;

The determining unit 1301 is specifically configured to determine, through the quantity limiter, the number of AICs allowed to be opened among the N AICs as the first number.

In a specific implementation manner, the device further includes an accumulator, and the accumulator is used to count the number of AICs that have been opened in the N AICs as the second number;

The determining unit 1301 is further configured to determine the second quantity through the accumulator;

The generating unit 1302 is specifically configured to generate the control instruction according to the first quantity and the second quantity.

In a specific implementation manner, the AI chip includes an image processing unit GPU, a neural processing unit NPU or a tensor processing unit TPU.

It should be noted that, for the information exchange and execution process among the units of the controller 1300, for details, please refer to the descriptions in the method embodiments shown in the foregoing application, which will not be repeated here.

Embodiments of the present application further provide a computer-readable storage medium that stores one or more computer-executable instructions. When the computer-executable instructions are executed by a processor, the processor executes the above-mentioned control method for an AI chip.

Embodiments of the present application further provide a computer program product that stores one or more computer-executable instructions, and when the computer-executable instructions are executed by the processor, the processor executes the above-mentioned control method for an AI chip.

The present application also provides a chip system, where the chip system includes a processor for supporting the controller to implement the functions involved in the above-mentioned power replacement control method. In a possible design, the chip system may further include a memory for storing necessary program instructions and data. The chip system may be composed of chips, or may include chips and other discrete devices.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above may refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.

The integrated unit, if implemented in the form of a software functional unit and sold or used as an independent product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of software products in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, and the computer software products are stored in a storage medium , including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes .

Claims

A control device for an artificial intelligence AI chip, wherein the AI chip includes N artificial intelligence core AICs, where N is an integer greater than 1, and the device includes:

a controller, and a disabling circuit connected to the controller;

The controller is configured to determine that the number of AICs allowed to be opened among the N AICs is a first number, and after generating a control command according to the first number, send the control command to the prohibition circuit;

The prohibiting circuit is connected to the N AICs, and is used for turning on or off at least one AIC of the N AICs according to the control instruction.
The apparatus of claim 1, wherein the apparatus further comprises a quantity limiter connected to the controller;

The quantity limiter is used to limit the number of AICs allowed to be opened in the N AICs to the first quantity;

The controller is specifically configured to determine the first quantity through the quantity limiter.
The device according to claim 2, wherein the quantity limiter comprises at least one electronic fuse efuse, and the quantity limiter is configured to limit the allowable ones in the N AICs through the output level of the at least one efuse The number of opened AICs is the first number.
The device of claim 3, wherein:

When the blown state of the at least one efuse is blown, the output level of the at least one efuse is the first level; and/or,

When the blown state of the at least one efuse is not blown, the output level of the at least one efuse is a second level; wherein the first level is different from the second level.
The device according to any one of claims 1 to 4, wherein the device further comprises an accumulator connected to the controller;

The accumulator is connected to the N AICs, and is used to count the number of opened AICs in the N AICs as the second number;

The controller is specifically configured to generate the control instruction according to the first quantity and the second quantity.
The apparatus according to claim 5, wherein the accumulator is specifically configured to connect non-faulty AICs in the N AICs, and the second number is used to indicate the opened AICs in the non-faulty AICs quantity.
The apparatus according to any one of claims 1 to 6, wherein the AI chip comprises an image processing unit GPU, a neural processing unit NPU or a tensor processing unit TPU.
A method for controlling an artificial intelligence AI chip, characterized in that the method is applied to a controller in a control device of the AI chip, the device further comprising a prohibition circuit, wherein the AI chip includes N artificial intelligence The core AIC, where N is an integer greater than 1, the method includes:

determining that the number of AICs allowed to be opened in the N AICs is the first number;

generating a control instruction according to the first number, the control instruction being used to instruct to open or close at least one AIC of the N AICs;

The control command is sent to the inhibit circuit.
The method according to claim 8, wherein the device further comprises a quantity limiter, and the quantity limiter is used to limit the number of AICs allowed to be opened in the N AICs to a first quantity;

The determining that the number of AICs allowed to be opened in the N AICs is the first number includes:

The number of AICs allowed to be opened among the N AICs is determined by the number limiter as the first number.
The method according to claim 9, wherein the device further comprises an accumulator, and the accumulator is used to count the number of the AICs that have been opened among the N AICs as the second number; Before the control instruction, the method further includes:

determining the second quantity by the accumulator;

The generating a control instruction according to the first quantity includes:

The control instruction is generated according to the first quantity and the second quantity.
The method according to any one of claims 8 to 10, wherein the second number is used to indicate the number of opened AICs among the non-faulty AICs of the N AICs.
The method according to any one of claims 8 to 11, wherein the AI chip comprises an image processing unit GPU, a neural processing unit NPU or a tensor processing unit TPU.
A controller of an artificial intelligence AI chip, characterized in that the controller is included in a control device of the AI chip, and the control device further includes a prohibition circuit, wherein the AI chip includes N artificial intelligence core AICs , where N is an integer greater than 1, and the controller includes:

a determining unit, where the number of AICs allowed to be opened in the N AICs is the first number;

a generating unit, configured to generate a control instruction according to the first quantity, where the control instruction is used to instruct to open or close at least one AIC in the N AICs;

A sending unit, configured to send the control instruction to the prohibiting circuit.
The controller according to claim 13, wherein the device further comprises a quantity limiter, and the quantity limiter is configured to limit the number of AICs allowed to be opened among the N AICs to a first number;

The determining unit is specifically configured to determine, by the quantity limiter, the number of AICs allowed to be opened among the N AICs as the first number.
The controller according to claim 14, wherein the device further comprises an accumulator, and the accumulator is used to count the number of the opened AICs among the N AICs as the second number;

the determining unit, further configured to determine the second quantity through the accumulator;

The generating unit is specifically configured to generate the control instruction according to the first quantity and the second quantity.
The controller according to any one of claims 13 to 15, wherein the second number is used to indicate the number of opened AICs among the non-faulty AICs of the N AICs.
The controller according to any one of claims 13 to 16, wherein the AI chip comprises an image processing unit GPU, a neural processing unit NPU or a tensor processing unit TPU.
A computer program product comprising instructions, characterized in that, when the computer program product is run on a computer, the computer is caused to perform the method of any one of claims 8 to 12.
A computer-readable storage medium for storing program instructions, characterized in that, when the program instructions are executed on a computer, the computer is made to execute any one of claims 8 to 12. method described in item.