WO2022083638A1

WO2022083638A1 - Chip clock frequency adjustment method and apparatus, chip, and electronic device

Info

Publication number: WO2022083638A1
Application number: PCT/CN2021/124977
Authority: WO
Inventors: 刘广辉
Original assignee: 维沃移动通信有限公司
Priority date: 2020-10-23
Filing date: 2021-10-20
Publication date: 2022-04-28
Also published as: CN112150962B; CN112150962A

Abstract

A chip clock frequency adjustment method and apparatus, a chip, and an electronic device. The chip comprises an RC oscillator. The RC oscillator is used for outputting a clock signal, and comprises an RC frequency selection network consisting of a first resistor and a first capacitor. The method comprises: determining a frequency error of a clock signal output by the RC oscillator (101), the frequency error being the ratio of a clock frequency difference to a target clock frequency; the clock frequency difference being the difference between a first clock frequency of the clock signal output by the RC oscillator, and the target clock frequency; and when the absolute value of the frequency error is greater than a first preset value, adjusting a resistance value of the RC frequency selection network, so that the absolute value of the frequency error is less than or equal to the first preset value (102), the first preset value being greater than 0, and being less than 1.

Description

Chip clock frequency adjustment method, device, chip and electronic equipment

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Chinese Patent Application No. 202011148686.0 filed in China on October 23, 2020, the entire contents of which are incorporated herein by reference.

technical field

The present application relates to the field of communication technologies, and in particular, to a method, device, chip and electronic device for adjusting the clock frequency of a chip.

Background technique

With the popularization of electronic devices, the functions of electronic devices are becoming more and more perfect, but the structures of electronic devices are also becoming more and more complex. In order to facilitate the screen of the electronic device to achieve a full screen, the distance between the driver chip of the electronic device and the antenna reaches the sub-millimeter level. In order to prevent the clock signal of the driver chip from interfering with the antenna, the clock frequency of the clock signal can be avoided from the communication frequency band. The clock signal is generated by an RC oscillator, and the clock frequency of the RC oscillator in the prior art is within or close to the communication frequency band, resulting in low communication quality.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a chip clock frequency adjustment method, device, chip and electronic device, which can solve the problem that the clock frequency of the RC oscillator in the prior art is within or close to the communication frequency band, resulting in low communication quality.

In order to solve the above-mentioned technical problems, the present invention is achieved in this way:

In a first aspect, an embodiment of the present application provides a chip clock frequency adjustment method, which is applied to a chip, where the chip includes an RC oscillator, and the RC oscillator is used to output a clock signal, and the RC oscillator includes a first An RC frequency selection network composed of a resistor and a first capacitor, the method includes:

Determine the frequency error of the clock signal output by the RC oscillator, the frequency error is the ratio of the clock frequency difference to the target clock frequency, and the clock frequency difference is the first clock of the clock signal output by the RC oscillator the difference between the frequency and the target clock frequency;

When the absolute value of the frequency error is greater than the first preset value, adjust the resistance value of the RC frequency selection network so that the absolute value of the frequency error is less than or equal to the first preset value, so The first preset value is greater than 0, and the first preset value is less than 1.

In a second aspect, an embodiment of the present application provides a chip, the chip includes an RC oscillator, the RC oscillator is used to output a clock signal, and the RC oscillator includes an RC composed of a first resistor and a first capacitor frequency selection network, the RC oscillator further includes a resistance value adjustment module connected to the first resistor, the resistance value adjustment module is used to adjust the resistance value of the RC frequency selection network, so that the RC oscillator The absolute value of the frequency error of the output clock signal is less than or equal to the first preset value, the frequency error is the ratio of the clock frequency difference to the target clock frequency, and the clock frequency difference is the clock output by the RC oscillator The difference between the first clock frequency of the signal and the target clock frequency, the first preset value is greater than 0, and the first preset value is less than 1.

In a third aspect, an embodiment of the present application provides a chip clock frequency adjustment device, the chip includes an RC oscillator, the RC oscillator is used to output a clock signal, and the RC oscillator includes a first resistor and a first An RC frequency selection network composed of capacitors, the device includes:

a first determining module, configured to determine the frequency error of the clock signal output by the RC oscillator, where the frequency error is the ratio of the clock frequency difference to the target clock frequency, and the clock frequency difference is the RC oscillator output The difference between the first clock frequency of the clock signal and the target clock frequency;

an adjustment module, configured to adjust the resistance value of the RC frequency selection network when the absolute value of the frequency error is greater than a first preset value, so that the absolute value of the frequency error is less than or equal to the first A preset value, the first preset value is greater than 0, and the first preset value is less than 1.

In a fourth aspect, an embodiment of the present application provides an electronic device, the electronic device includes a processor, a memory, and a program or instruction stored on the memory and executable on the processor, the program or instruction being The processor implements the steps in the chip clock frequency adjustment method according to the first aspect when executed.

In a fifth aspect, an embodiment of the present application provides a readable storage medium, where a program or an instruction is stored on the readable storage medium, and when the program or instruction is executed by a processor, the chip clock frequency according to the first aspect is realized Adjust the steps in the method.

In a sixth aspect, an embodiment of the present application provides a chip, the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is configured to run a program or an instruction to implement the first aspect the method described.

In a seventh aspect, an embodiment of the present application provides a computer program product, the computer program product is stored in a non-volatile storage medium, and the computer program product is executed by at least one processor to implement the first aspect. method described.

In the embodiment of the present application, the frequency error of the clock signal output by the RC oscillator is determined, the frequency error is the ratio of the clock frequency difference to the target clock frequency, and the clock frequency difference is the output of the RC oscillator The difference between the first clock frequency of the clock signal and the target clock frequency; when the absolute value of the frequency error is greater than the first preset value, adjust the resistance value of the RC frequency selection network, so that all The absolute value of the frequency error is less than or equal to the first preset value, the first preset value is greater than 0, and the first preset value is less than 1. In this way, by adjusting the resistance value of the RC frequency selection network, the frequency error of the clock signal output by the RC oscillator can be reduced, so that the clock frequency of the clock signal can be adjusted to avoid the current radio frequency communication frequency band, and the communication quality can be improved.

Description of drawings

1 is a flowchart of a method for adjusting a chip clock frequency provided by an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a chip provided by an embodiment of the present application;

3 is a schematic diagram of a clock pulse count provided by an embodiment of the present application;

4 is a schematic diagram of a clock frequency adjustment provided by an embodiment of the present application;

FIG. 5 is a partial structural schematic diagram of a chip provided by an embodiment of the present application;

6 is one of the schematic structural diagrams of a chip clock frequency adjustment device provided by an embodiment of the present application;

FIG. 7 is the second schematic structural diagram of a chip clock frequency adjustment device provided by an embodiment of the present application;

8 is one of the schematic structural diagrams of an electronic device provided by an embodiment of the present application;

FIG. 9 is a second schematic structural diagram of an electronic device provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work, all belong to the scope of protection of this application.

The terms "first", "second" and the like in the description and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances so that the embodiments of the present application can be practiced in sequences other than those illustrated or described herein, and distinguish between "first", "second", etc. The objects are usually of one type, and the number of objects is not limited. For example, the first object may be one or more than one. In addition, "and/or" in the description and claims indicates at least one of the connected objects, and the character "/" generally indicates that the associated objects are in an "or" relationship.

The following describes the chip clock frequency adjustment method provided by the embodiment of the present application in detail through specific embodiments and application scenarios with reference to the accompanying drawings.

Referring to FIG. 1, FIG. 1 is a flowchart of a chip clock frequency adjustment method provided by an embodiment of the present application. The method is applied to a chip, and the chip includes an RC oscillator, and the RC oscillator is used to output a clock signal, As shown in FIG. 2 , the RC oscillator includes an RC frequency selection network 2 composed of a first resistor 21 and a first capacitor. As shown in FIG. 1 , the RC oscillator includes the following steps:

Step 101: Determine the frequency error of the clock signal output by the RC oscillator, where the frequency error is the ratio of the clock frequency difference to the target clock frequency, and the clock frequency difference is the frequency of the clock signal output by the RC oscillator. The difference between the first clock frequency and the target clock frequency.

The number of the first resistors may be one or more, and the number of the first capacitors may be one or more. As shown in FIG. 2 , the number of the first resistors may be three, and the number of the first capacitors may be three. The RC oscillator may include an amplifier, the RC frequency selection network 2 may be connected to the amplifier, and the clock signal may be outputted through the amplifier. The first clock frequency may be the clock frequency of the clock signal output by the RC oscillator, that is, the current actual clock frequency. The target clock frequency may be a preset clock frequency, or may be a clock frequency determined based on the current radio frequency communication frequency band.

Step 102, in the case that the absolute value of the frequency error is greater than the first preset value, adjust the resistance value of the RC frequency selection network, so that the absolute value of the frequency error is less than or equal to the first preset value value, the first preset value is greater than 0, and the first preset value is less than 1.

Wherein, the first preset value may be 0.2%, or may be 0.3%, or may be 0.5%, etc., which is not limited in this embodiment. The resistance value of the RC frequency selection network can be adjusted by a resistance value adjustment module, and the resistance value adjustment module can include at least one resistance value reduction unit and at least one resistance value increase unit, and the resistance value reduction unit is used for The resistance value of the RC frequency selection network is reduced, and the resistance value increasing unit is used to increase the resistance value of the RC frequency selection network; each of the resistance value reduction units includes: at least one second resistor connected in parallel with the resistors, and a first switch connected in series with each of the second resistors; each of the resistance increasing units includes: at least one third resistor connected in series with the first resistor, and a second switch in series with each of said third resistors.

In practical applications, taking the chip as a display driver chip as an example, the display driver chip gives priority to logic and timing implementation in chip design, and leaves a large margin in related design, and even considers Electromagnetic Compatibility (Electromagnetic Compatibility, EMC) problems are all system integration problems, and electronic devices need to find solutions at the system side, thus ignoring the principle of least processing cost at the source, resulting in related manufacturers' measures and solutions for chip-level electromagnetic interference (Electromagnetic Interference, EMI). The research investment is very small, and the function and EMI-related performance cannot be balanced, resulting in a large defect in the EMI performance of the display driver chip. Driven by the appearance of the extreme full screen of electronic devices, the distance between the display driver chip and the antenna is already sub-millimeter level, and the direct radiated EMI interference generated by the clock of the display driver chip can be radiated and coupled to the antenna at close range.

Optionally, the determining the frequency error of the clock signal output by the RC oscillator includes:

receive line scan signal;

obtaining the first pulse number of the clock signal output by the RC oscillator between the reception moments of at least two line scan signals;

obtaining a target pulse number based on the target clock frequency;

A frequency error of the clock signal output by the RC oscillator is determined based on the first pulse number and the target pulse number.

Wherein, the target pulse number may be the product of the time difference between the receiving moments of the at least two line scan signals and the target clock frequency, and the frequency error of the clock signal output by the RC oscillator may be: (N0 -N1)/N1*100%, N0 is the first pulse number, N1 is the target pulse number. As shown in FIG. 3 , t1 is the clock period, and t0 is the time period between the reception times of at least two line scan signals, so N1 is: t0/t1. t0 can be provided by the processor, usually more than 0.001% accuracy, the accuracy is high. The first pulse number can be counted by a 16-bit pulse counter. The 16-bit pulse counter can achieve a maximum of 65536 pulse counts. In theory, the maximum frequency error (1-65535/65536) can be achieved, with a judgment accuracy of about 0.0025%.

In the related art, the clock signal output by the RC oscillator has poor clock accuracy, which can only reach about 2% to 5% of the target clock frequency, and will drift with the temperature change, and the jitter will be large, resulting in the spectrum of the interference signal. The bandwidth reaches more than 3MHz. Poor clock accuracy makes it impossible to select a specific frequency so that the associated interference avoids all communication bands. And due to the limitations of the process and platform, the reference clock cannot be directly input from the outside, and the chip cannot add a high-precision clock source. The package and process of the display driver chip do not support high-precision clock source modules, such as the integration of crystals; and the chip cannot support external high-precision clocks as a reference, resulting in poor compatibility.

It should be noted that, when the frequency error is determined, the frequency error as accurate as possible can be obtained through higher clock precision requirements. For example, when the clock accuracy is 0.05%, a relatively accurate frequency error can be obtained. You can round up N1 to an integer to get N2; calculate (1-N2*t1/t0) to get the precision of the clock. For example, if the target clock frequency is 100MHz, the clock period is 10ns, and the condition of more than 2000 pulses is satisfied, the unit time is 20000ns or more than 20us, corresponding to a 60Hz screen, the scanning time of each line is 7us, and the scanning time of 3 lines is taken. is 21us, and the corresponding target pulse number is 2100, which can meet the accuracy requirement of 0.05%.

In this embodiment, the frequency error of the clock can be determined by tracking the number of clock pulses in the unit period of the line scanning signal with high contrast accuracy, so that the frequency error can be determined more accurately, and then the clock frequency can be determined based on the more accurate frequency error. Adjustment.

Optionally, when the absolute value of the frequency error is greater than the first preset value, adjust the resistance value of the RC frequency selection network, so that the absolute value of the frequency error is less than or equal to the first preset value. a preset value, including:

When the absolute value of the frequency error is greater than the first preset value, and the frequency error is greater than 0, increase the resistance value of the RC frequency selection network, so that the absolute value of the frequency error is less than or equal to the first preset value;

When the absolute value of the frequency error is greater than the first preset value, and the frequency error is less than 0, reduce the resistance value of the RC frequency selection network, so that the absolute value of the frequency error is less than or equal to the first preset value.

Wherein, the resistance value of the RC frequency selection network can be increased by all or part of the resistance value increasing units in the at least one resistance value increasing unit, and all or part of the resistance value increasing units in the at least one resistance value decreasing unit can be used. The partial resistance value reducing unit reduces the resistance value of the RC frequency selection network.

In this embodiment, the frequency error of the clock frequency is reduced by increasing or decreasing the resistance value of the RC frequency selection network, so that the clock frequency can be adjusted accurately so that the clock frequency avoids the radio frequency communication frequency band, and the EMI performance of the display driver chip is improved. , thereby improving the network adaptability experience.

Optionally, before determining the frequency error of the clock signal output by the RC oscillator, the method further includes:

Obtain the current radio frequency communication frequency band;

If the first clock frequency is within the current radio frequency communication frequency band, the target clock frequency is determined based on the current radio frequency communication frequency band, wherein the target clock frequency is outside the current radio frequency communication frequency band.

Among them, a frequency setting look-up table may be preset, and the frequency setting look-up table may store the radio frequency communication frequency band and the corresponding clock frequency, that is, the target clock frequency. The radio frequency communication frequency band does not include the target clock frequency, so that the target clock frequency can be Avoid RF communication bands. The target clock frequency may be the clock frequency corresponding to the current radio frequency communication frequency band in the frequency setting look-up table. As shown in FIG. 4 , the current radio frequency communication frequency band may be between FL and FH, and the first clock frequency in the current radio frequency communication frequency band may be frequency hopped to a target clock frequency outside the current radio frequency communication frequency band.

In practical applications, the clock accuracy and frequency error of the display driver chip can be detected synchronously when switching the radio frequency communication frequency band and channel to confirm whether the clock-related interference avoids the radio frequency communication frequency band. If the current clock frequency cannot avoid the current radio frequency communication frequency band, the clock frequency can be adjusted to the target clock frequency in the preset frequency setting look-up table. By adjusting the current clock frequency so that the current clock frequency is as close to the target clock frequency as possible, based on improving the clock accuracy and reducing the frequency error, a small range of frequency hopping can be performed without affecting the function, avoiding the current RF communication frequency band, which can solve the problem of display driver. EMI interference problems caused by the clock module of the chip.

In this embodiment, the target clock frequency is determined based on the current radio frequency communication frequency band, and the clock frequency can be dynamically and intelligently adjusted and compensated with the change of the radio frequency communication frequency band, so that the interference frequency of the clock module can avoid the radio frequency communication frequency band , so as to solve the EMI interference problem caused by the clock module.

Referring to FIG. 2, FIG. 2 is a schematic structural diagram of a chip provided by an embodiment of the present application, the chip includes an RC oscillator, the RC oscillator is used to output a clock signal, and the RC oscillator includes a first resistor 21 The RC frequency selection network 2 formed with the first capacitor, as shown in FIG. 5 , the RC oscillator further includes a resistance adjustment module 22 connected with the first resistor 21 , and the resistance adjustment module 22 is used for adjusting The resistance value of the RC frequency selection network 2, so that the absolute value of the frequency error of the clock signal output by the RC oscillator is less than or equal to the first preset value, and the frequency error is the difference between the clock frequency and the target clock frequency. The ratio of the clock frequency difference is the difference between the first clock frequency of the clock signal output by the RC oscillator and the target clock frequency, the first preset value is greater than 0, and the first preset value is greater than 0. Set the value to less than 1.

Among them, the clock frequency of the RC oscillator is inversely proportional to the resistance value of the RC frequency selection network 2, for example, f=1/(2πRC), f is the clock frequency, R is the resistance value of the RC frequency selection network 2, and C is the RC Capacitance value of frequency selection network 2.

Adjusting the resistance value of the RC frequency selection network 2 through the resistance value adjustment module 22 can improve the clock accuracy and reduce the frequency error, thereby reducing the difficulty of chip integration development; and can reduce the cost and reliability without sacrificing reliability. Under the circumstance, the EMI performance of the chip is improved, thereby improving the network adaptability experience; and it can shorten the product development verification cycle.

In the embodiment of the present application, by adjusting the resistance value of the RC frequency selection network 2 by the resistance value adjustment module 22, the frequency error of the clock signal output by the RC oscillator can be reduced, so that the clock frequency of the clock signal can be adjusted to avoid the current The radio frequency communication frequency band can improve the communication quality.

Optionally, the resistance adjustment module 22 includes at least one resistance reducing unit and at least one resistance increasing unit, and the resistance reducing unit is used to reduce the resistance value of the RC frequency selection network 2, The resistance value increasing unit is used to increase the resistance value of the RC frequency selection network 2;

Each of the resistance reducing units includes: at least one second resistor connected in parallel with the first resistor 21, and a first switch connected in series with each of the second resistors;

Each of the resistance increasing units includes: at least one third resistor connected in series with the first resistor 21 , and a second switch connected in series with each of the third resistors.

The resistance value of the second resistor is greater than the resistance value of the first resistor 21 , and the resistance value of the third resistor is smaller than the resistance value of the first resistor 21 . For example, the resistance value of the second resistor is 100 times the resistance value of the first resistor 21 , and the resistance value of the third resistor is 1% of the resistance value of the first resistor 21 . The resistance values of the RC frequency selection network 2 reduced by a plurality of resistance value reducing units may be different, and the resistance values of the RC frequency selection network 2 increased by a plurality of resistance value increasing units may be different, so that the step-by-step process can be realized. The frequency error is adjusted progressively.

The increased circuit area of the resistance adjustment module 22 accounts for a very small amount of the entire chip area, and the cost of the chip is related to the area. Therefore, this embodiment can improve the EMI performance of the clock of the chip at a small cost and cost, and at the same time, due to the improvement of the clock accuracy , thereby improving the reliability of chip-related functions.

In this embodiment, by connecting a plurality of resistors with different resistance values in parallel or in series on the first resistor 21 of the RC frequency selection network 2, a larger resistor in parallel or a smaller resistor in series can change the clock frequency in a small range, so that the clock frequency can be changed in a small range through all The at least one resistance reducing unit and the at least one resistance increasing unit adjust the frequency error stepwise.

Optionally, the at least one resistance reduction unit includes a first resistance reduction unit 221 and a second resistance reduction unit 222, and the first resistance reduction unit 221 is used to reduce the RC selection. The resistance value of the frequency selection network 2 is set to make the resistance value of the RC frequency selection network 2 smaller than the second preset value, and the second resistance reduction unit 222 is used to reduce the resistance value of the RC frequency selection network 2 , so that the resistance value of the RC frequency selection network 2 is smaller than the third preset value, and the second preset value is greater than the third preset value;

The at least one resistance increasing unit includes a first resistance increasing unit 225 and a second resistance increasing unit 226, and the first resistance increasing unit 225 is used to increase the resistance of the RC frequency selection network 2. resistance value, so that the resistance value of the RC frequency selection network 2 is greater than the fourth preset value, and the second resistance value increasing unit 226 is used to increase the resistance value of the RC frequency selection network 2, so that all The resistance value of the RC frequency selection network 2 is greater than the fifth preset value, and the fourth preset value is smaller than the fifth preset value.

The first resistance reducing unit 221 and the second resistance reducing unit 222 reduce the resistance of the RC frequency selection network 2, thereby increasing the clock frequency, and the first resistance reducing unit 221 corresponds to The increase value of the clock frequency of , is smaller than the increase value of the clock frequency corresponding to the second resistance value reducing unit 222 . The first resistance value increasing unit 225 and the second resistance value increasing unit 226 increase the resistance value of the RC frequency selection network 2, so that the clock frequency can be reduced. The first resistance value increasing unit 225 corresponds to the clock frequency The reduction value is smaller than the reduction value of the clock frequency corresponding to the second resistance value increasing unit 226 .

As an embodiment, the at least one resistance reducing unit includes a first resistance reducing unit 221 , a second resistance reducing unit 222 , a third resistance reducing unit 223 and a fourth resistance reducing unit 224. The first resistance reducing unit 221 can increase the clock frequency to change the absolute value of the frequency error by 0.1%; the second resistance reducing unit 222 can increase the clock frequency to change the absolute value of the frequency error by 0.5%; The resistance reducing unit 223 can increase the clock frequency to change the absolute value of the frequency error by 0.2%, and the fourth resistance reducing unit 224 can increase the clock frequency to change the absolute value of the frequency error by 1%. The at least one resistance increasing unit includes a first resistance increasing unit 225, a second resistance increasing unit 226, a third resistance increasing unit 227, and a fourth resistance increasing unit 228. The first resistance increasing unit 228. The increasing unit 225 can reduce the clock frequency to change the absolute value of the frequency error by 0.1%, the second resistance increasing unit 226 can reduce the clock frequency to change the absolute value of the frequency error by 0.5%, and the third resistance increasing unit 227 The clock frequency can be reduced to change the absolute value of the frequency error by 0.2%, and the fourth resistance increasing unit 228 can reduce the clock frequency to change the absolute value of the frequency error by 1%. The resistance adjustment module 22 may further include a third switch 229, which may be connected in series with the first resistance 21, and the third switch 229 may be disconnected when the resistance value of the RC frequency selection network 2 needs to be increased. ; When the resistance value of the RC frequency selection network 2 does not need to be increased, the third switch 229 can be closed.

In practical applications, it can be judged whether the absolute value of the frequency error is less than 0.2%. If the absolute value of the frequency error is judged to be less than 0.2%, the clock frequency can not be adjusted; if the absolute value of the frequency error is judged to be greater than 0.5%, and the frequency error is less than 0, the frequency error can be adjusted by controlling the second resistance reducing unit 222 and the first switch in the fourth resistance reducing unit 224; if it is judged that the absolute value of the frequency error is greater than or equal to 0.2% and less than or is equal to 0.5%, and the frequency error is less than 0, the frequency error can be adjusted by controlling the first switch in the first resistance reducing unit 221 and the third resistance reducing unit 223; if it is judged that the absolute value of the frequency error is greater than 0.5%, and the frequency error is greater than 0, the frequency error can be adjusted by controlling the second resistance increasing unit 226 and the second switch in the fourth resistance increasing unit 228; is equal to 0.2% and less than or equal to 0.5%, and the frequency error is less than 0, the frequency error can be adjusted by controlling the second switches in the first resistance increasing unit 225 and the third resistance increasing unit 227 .

By adjusting the resistance value of the RC frequency selection network 2 by the resistance value adjustment module 22, the frequency error can be adjusted within a preset range within ms, so that even if a certain noise bandwidth is considered, the requirements of the radio frequency communication frequency band for interference and noise avoidance can be met. .

In this embodiment, through the first resistance reducing unit 221 and the second resistance reducing unit 222, when the current clock frequency is lower than the target clock frequency, the clock frequency can be gradually increased, so that the current clock frequency is close to the target clock frequency, thereby gradually reducing the frequency error; through the first resistance increasing unit 225 and the second resistance increasing unit 226, when the current clock frequency is greater than the target clock frequency, the clock frequency can be gradually reduced, so that the current clock frequency The frequency is close to the target clock frequency, thereby gradually reducing the frequency error.

The chip clock frequency adjustment method in the embodiment of FIG. 1 can be applied to the chips in the above-mentioned embodiments, and the same beneficial effects can be achieved.

It should be noted that, for the chip clock frequency adjustment method provided by the embodiments of the present application, the execution body may be a chip clock frequency adjustment apparatus, or a control module in the chip clock frequency adjustment apparatus for executing the loading chip clock frequency adjustment method. In the embodiment of the present application, the method for adjusting the clock frequency of a loaded chip by an apparatus for adjusting the clock frequency of a chip is used as an example to describe the apparatus for adjusting the clock frequency of a chip provided by the embodiment of the present application.

Referring to FIG. 6, FIG. 6 is a schematic structural diagram of a chip clock frequency adjustment device provided by an embodiment of the present application, the chip includes an RC oscillator, the RC oscillator is used to output a clock signal, and the RC oscillator includes a The RC frequency selection network formed by the first resistor and the first capacitor, as shown in FIG. 6 , the device 300 includes:

The first determination module 301 is used to determine the frequency error of the clock signal output by the RC oscillator, the frequency error is the ratio of the clock frequency difference to the target clock frequency, and the clock frequency difference is the RC oscillator the difference between the first clock frequency of the output clock signal and the target clock frequency;

An adjustment module 302, configured to adjust the resistance value of the RC frequency selection network when the absolute value of the frequency error is greater than a first preset value, so that the absolute value of the frequency error is less than or equal to the first A preset value, the first preset value is greater than 0, and the first preset value is less than 1.

Optionally, the first determining module 301 is specifically configured to:

receive line scan signal;

Obtain the first pulse number of the clock signal output by the RC oscillator between the reception moments of at least two line scan signals;

obtaining a target pulse number based on the target clock frequency;

Optionally, the adjustment module 302 is specifically used for:

Optionally, as shown in FIG. 7 , the apparatus 300 further includes:

an acquisition module 303, configured to acquire the current radio frequency communication frequency band;

The second determining module 304 is configured to determine the target clock frequency based on the current radio frequency communication frequency band if the first clock frequency is within the current radio frequency communication frequency band, wherein the target clock frequency is within the current radio frequency communication frequency band outside the radio frequency communication band.

The device for adjusting the clock frequency of a chip in this embodiment of the present application may be a device, or may be a component, an integrated circuit, or a chip in a terminal. The apparatus may be a mobile electronic device or a non-mobile electronic device. Exemplarily, the mobile electronic device may be a mobile phone, a tablet computer, a notebook computer, a palmtop computer, an in-vehicle electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (personal digital assistant). assistant, PDA), etc., non-mobile electronic devices can be servers, network attached storage (Network Attached Storage, NAS), personal computer (personal computer, PC), television (television, TV), teller machine or self-service machine, etc., this application Examples are not specifically limited.

The device for adjusting the clock frequency of the chip in the embodiment of the present application may be a device having an operating system. The operating system may be an Android (Android) operating system, an ios operating system, or other possible operating systems, which are not specifically limited in the embodiments of the present application.

The chip clock frequency adjustment device provided by the embodiment of the present application can implement each process implemented by the method embodiment in FIG. 1 , and to avoid repetition, details are not described here.

Optionally, as shown in FIG. 8 , an embodiment of the present application further provides an electronic device 400, including a processor 401, a memory 402, a program or instruction stored in the memory 402 and executable on the processor 401, When the program or instruction is executed by the processor 401, each process of the above-mentioned embodiments of the chip clock frequency adjustment method can be realized, and the same technical effect can be achieved. To avoid repetition, details are not described here.

It should be noted that the electronic devices in the embodiments of the present application include the aforementioned mobile electronic devices and non-mobile electronic devices.

FIG. 9 is a schematic diagram of a hardware structure of an electronic device implementing an embodiment of the present application.

The electronic device 500 includes but is not limited to: a radio frequency unit 501, a network module 502, an audio output unit 503, an input unit 504, a sensor 505, a display unit 506, a user input unit 507, an interface unit 508, a memory 509, and a processor 510, etc. part.

Those skilled in the art can understand that the electronic device 500 may also include a power supply (such as a battery) for supplying power to various components, and the power supply may be logically connected to the processor 510 through a power management system, so as to manage charging, discharging, and power management through the power management system. consumption management and other functions. The structure of the electronic device shown in FIG. 9 does not constitute a limitation to the electronic device. The electronic device may include more or less components than the one shown, or combine some components, or arrange different components, which will not be repeated here. .

Wherein, the electronic device includes a chip, the chip includes an RC oscillator, the RC oscillator is used to output a clock signal, the RC oscillator includes an RC frequency selection network composed of a first resistor and a first capacitor, and the processing The device 510 is configured to: determine the frequency error of the clock signal output by the RC oscillator, where the frequency error is the ratio of the clock frequency difference to the target clock frequency, and the clock frequency difference is the clock output by the RC oscillator the difference between the first clock frequency of the signal and the target clock frequency;

Optionally, the processor 510 is further configured to:

receive line scan signal;

obtaining a target pulse number based on the target clock frequency;

Optionally, the processor 510 is further configured to:

Obtain the current radio frequency communication frequency band;

It should be understood that, in this embodiment of the present application, the input unit 504 may include a graphics processor (Graphics Processing Unit, GPU) 5041 and a microphone 5042. Such as camera) to obtain still pictures or video image data for processing. The display unit 506 may include a display panel 5061, which may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit 507 includes a touch panel 5071 and other input devices 5072 . The touch panel 5071 is also called a touch screen. The touch panel 5071 may include two parts, a touch detection device and a touch controller. Other input devices 5072 may include, but are not limited to, physical keyboards, function keys (such as volume control keys, switch keys, etc.), trackballs, mice, and joysticks, which are not described herein again. Memory 509 may be used to store software programs as well as various data, including but not limited to application programs and operating systems. The processor 510 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface, and application programs, and the like, and the modem processor mainly processes wireless communication. It can be understood that, the above-mentioned modulation and demodulation processor may not be integrated into the processor 510.

Embodiments of the present application further provide a readable storage medium, where a program or an instruction is stored on the readable storage medium, and when the program or instruction is executed by a processor, each process of the above-mentioned embodiments of the chip clock frequency adjustment method is implemented, and can To achieve the same technical effect, in order to avoid repetition, details are not repeated here.

Wherein, the processor is the processor in the electronic device described in the foregoing embodiments. The readable storage medium includes a computer-readable storage medium, such as a computer read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and the like.

An embodiment of the present application further provides a chip, where the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is used for running a program or an instruction to implement the above method for adjusting the clock frequency of the chip In order to avoid repetition, the details are not repeated here.

It should be understood that the chip mentioned in the embodiments of the present application may also be referred to as a system-on-chip, a system-on-chip, a system-on-a-chip, or a system-on-a-chip, or the like.

It should be noted that, herein, the terms "comprising", "comprising" or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements, It also includes other elements not expressly listed or inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element. In addition, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in the reverse order depending on the functions involved. To perform functions, for example, the described methods may be performed in an order different from that described, and various steps may also be added, omitted, or combined. Additionally, features described with reference to some examples may be combined in other examples.

From the description of the above embodiments, those skilled in the art can clearly understand that the method of the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is better implementation. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product in essence or in a part that contributes to the prior art, and the computer software product is stored in a storage medium (such as ROM/RAM, magnetic disk, CD), including several instructions to make a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) execute the methods described in the various embodiments of this application.

The embodiments of the present application have been described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific embodiments, which are merely illustrative rather than restrictive. Under the inspiration of this application, without departing from the scope of protection of the purpose of this application and the claims, many forms can be made, which all fall within the protection of this application.

Claims

A chip clock frequency adjustment method is applied to a chip, the chip includes an RC oscillator, the RC oscillator is used for outputting a clock signal, and the RC oscillator includes an RC frequency selection composed of a first resistor and a first capacitor network, the method includes:

Determine the frequency error of the clock signal output by the RC oscillator, the frequency error is the ratio of the clock frequency difference to the target clock frequency, and the clock frequency difference is the first clock of the clock signal output by the RC oscillator the difference between the frequency and the target clock frequency;

When the absolute value of the frequency error is greater than the first preset value, adjust the resistance value of the RC frequency selection network so that the absolute value of the frequency error is less than or equal to the first preset value, so The first preset value is greater than 0, and the first preset value is less than 1.
The method according to claim 1, wherein the determining the frequency error of the clock signal output by the RC oscillator comprises:

receive line scan signal;

obtaining the first pulse number of the clock signal output by the RC oscillator between the reception moments of at least two line scan signals;

obtaining a target pulse number based on the target clock frequency;

A frequency error of the clock signal output by the RC oscillator is determined based on the first pulse number and the target pulse number.
The method according to claim 1, wherein when the absolute value of the frequency error is greater than a first preset value, adjusting the resistance value of the RC frequency selection network, so that the absolute value of the frequency error is The value is less than or equal to the first preset value, including:

When the absolute value of the frequency error is greater than the first preset value, and the frequency error is greater than 0, increase the resistance value of the RC frequency selection network, so that the absolute value of the frequency error is less than or equal to the first preset value;

When the absolute value of the frequency error is greater than the first preset value, and the frequency error is less than 0, reduce the resistance value of the RC frequency selection network, so that the absolute value of the frequency error is less than or equal to the first preset value.
The method of claim 1, wherein before said determining the frequency error of the clock signal output by the RC oscillator, the method further comprises:

Obtain the current radio frequency communication frequency band;

If the first clock frequency is within the current radio frequency communication frequency band, the target clock frequency is determined based on the current radio frequency communication frequency band, wherein the target clock frequency is outside the current radio frequency communication frequency band.
A chip, the chip includes an RC oscillator, the RC oscillator is used for outputting a clock signal, the RC oscillator includes an RC frequency selection network composed of a first resistor and a first capacitor, and the RC oscillator also Including a resistance adjustment module connected to the first resistor, the resistance adjustment module is used to adjust the resistance value of the RC frequency selection network, so that the absolute value of the frequency error of the clock signal output by the RC oscillator is less than or equal to the first preset value, the frequency error is the ratio of the clock frequency difference to the target clock frequency, and the clock frequency difference is the first clock frequency of the clock signal output by the RC oscillator and the target The difference between clock frequencies, the first preset value is greater than 0, and the first preset value is less than 1.
The chip according to claim 5, wherein the resistance adjusting module comprises at least one resistance reducing unit and at least one resistance increasing unit, and the resistance reducing unit is used for reducing the RC frequency selection The resistance value of the network, the resistance value increasing unit is used to increase the resistance value of the RC frequency selection network;

Each of the resistance reducing units includes: at least one second resistor connected in parallel with the first resistor, and a first switch connected in series with each of the second resistors;

Each of the resistance increasing units includes: at least one third resistor connected in series with the first resistor, and a second switch connected in series with each of the third resistors.
The chip according to claim 6, wherein the at least one resistance reducing unit comprises a first resistance reducing unit and a second resistance reducing unit, the first resistance reducing unit is used for reducing The resistance value of the RC frequency selection network, so that the resistance value of the RC frequency selection network is smaller than the second preset value, and the second resistance value reduction unit is used to reduce the resistance value of the RC frequency selection network. , so that the resistance value of the RC frequency selection network is smaller than the third preset value, and the second preset value is greater than the third preset value;

The at least one resistance increase unit includes a first resistance increase unit and a second resistance increase unit, the first resistance increase unit is used to increase the resistance value of the RC frequency selection network, so as to Make the resistance value of the RC frequency selection network greater than the fourth preset value, and the second resistance value increasing unit is used to increase the resistance value of the RC frequency selection network, so that the resistance of the RC frequency selection network The value is greater than the fifth preset value, and the fourth preset value is smaller than the fifth preset value.
A chip clock frequency adjustment device, the chip includes an RC oscillator, the RC oscillator is used for outputting a clock signal, the RC oscillator includes an RC frequency selection network composed of a first resistor and a first capacitor, the The device includes:

a first determining module, configured to determine the frequency error of the clock signal output by the RC oscillator, where the frequency error is the ratio of the clock frequency difference to the target clock frequency, and the clock frequency difference is the RC oscillator output The difference between the first clock frequency of the clock signal and the target clock frequency;

an adjustment module, configured to adjust the resistance value of the RC frequency selection network when the absolute value of the frequency error is greater than a first preset value, so that the absolute value of the frequency error is less than or equal to the first A preset value, the first preset value is greater than 0, and the first preset value is less than 1.
The apparatus according to claim 8, wherein the first determining module is specifically configured to:

receive line scan signal;

obtaining the first pulse number of the clock signal output by the RC oscillator between the reception moments of at least two line scan signals;

obtaining a target pulse number based on the target clock frequency;

A frequency error of the clock signal output by the RC oscillator is determined based on the first pulse number and the target pulse number.
The device according to claim 8, wherein the adjustment module is specifically used for:

When the absolute value of the frequency error is greater than the first preset value, and the frequency error is greater than 0, increase the resistance value of the RC frequency selection network, so that the absolute value of the frequency error is less than or equal to the first preset value;

When the absolute value of the frequency error is greater than the first preset value, and the frequency error is less than 0, reduce the resistance value of the RC frequency selection network, so that the absolute value of the frequency error is less than or equal to the first preset value.
The apparatus of claim 8, wherein the apparatus further comprises:

The acquisition module is used to acquire the current radio frequency communication frequency band;

a second determining module, configured to determine the target clock frequency based on the current radio frequency communication frequency band if the first clock frequency is in the current radio frequency communication frequency band, wherein the target clock frequency is in the current radio frequency out of the communication band.
An electronic device, comprising a processor, a memory, and a program or instruction stored on the memory and executable on the processor, wherein the program or instruction is executed by the processor to achieve as claimed in claim 1 Steps of the chip clock frequency adjustment method described in any one of -4.
A readable storage medium on which a program or an instruction is stored, wherein the program or instruction is executed by a processor to implement the chip clock frequency adjustment method according to any one of claims 1-4 A step of.
A chip, comprising a processor and a communication interface, wherein the communication interface is coupled with the processor, and the processor is used to run a program or an instruction to implement the chip clock according to any one of claims 1-4 The steps of the frequency adjustment method.
A computer program product, wherein the computer program product is stored in a non-volatile storage medium, the computer program product being executed by at least one processor to implement the method of any one of claims 1-4 The steps of the chip clock frequency adjustment method.