WO2022078375A1 - 一种芯片系统、处理虚拟中断的方法及相应装置 - Google Patents

一种芯片系统、处理虚拟中断的方法及相应装置 Download PDF

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WO2022078375A1
WO2022078375A1 PCT/CN2021/123497 CN2021123497W WO2022078375A1 WO 2022078375 A1 WO2022078375 A1 WO 2022078375A1 CN 2021123497 W CN2021123497 W CN 2021123497W WO 2022078375 A1 WO2022078375 A1 WO 2022078375A1
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virtual
interrupt
processor
physical processor
identifier
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PCT/CN2021/123497
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English (en)
French (fr)
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赵思齐
蒋毅飞
邓凯
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华为技术有限公司
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Priority to JP2023522963A priority Critical patent/JP2023545818A/ja
Priority to KR1020237015942A priority patent/KR20230084300A/ko
Priority to EP21879418.8A priority patent/EP4220394A4/en
Publication of WO2022078375A1 publication Critical patent/WO2022078375A1/zh
Priority to US18/300,515 priority patent/US20230259380A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45545—Guest-host, i.e. hypervisor is an application program itself, e.g. VirtualBox
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G06F2009/4557—Distribution of virtual machine instances; Migration and load balancing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G06F2009/45575—Starting, stopping, suspending or resuming virtual machine instances
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G06F2009/45579—I/O management, e.g. providing access to device drivers or storage
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G06F2009/45583—Memory management, e.g. access or allocation

Definitions

  • the present application relates to the field of virtualization technologies, and in particular, to a chip system, a method for processing virtual interrupts, and a corresponding device.
  • Virtual interrupt is a necessary part of virtualization technology.
  • a virtual machine runs in a computer device.
  • Hardware devices such as disks and input/output (I/O) devices in the computer device are Notifications from the virtual machine, as well as various synchronization and coordination tasks within the virtual machine rely on virtual interrupts.
  • a virtual interrupt is an event, which can come from various sources, and the processing process for the event will be different for different sources, but such events from each source will be notified in the form of an interrupt received when the virtual machine is running to the virtual machine.
  • the host needs to use its own various mechanisms to complete the work of sending the virtual interrupt from the source to the destination virtual machine.
  • the control flow of the processor needs to be switched from the executing virtual machine to the host, or from the user mode of the host to the kernel mode of the host, resulting in a large switching overhead.
  • Embodiments of the present application provide a chip system, a method for processing virtual interrupts, and a corresponding device, which are used to reduce the switching from a virtual machine to a host machine, or from a user state of a host machine to a kernel state of the host machine due to virtual interrupts. overhead.
  • the embodiments of the present application also provide corresponding computer devices, computer storage media, computer program products, and the like.
  • a first aspect of the present application provides a chip system, including: a source physical processor, a control device, an intermediate device, a sending device, and a target physical processor, where the source physical processor is used to run a host machine or a virtual machine, and the control device includes a register, and the register It is used to receive information for triggering virtual interrupts, and the information used to trigger virtual interrupts can come from a host machine or a virtual machine; the control device is used to: send the information used to trigger virtual interrupts in the registers to the intermediate device; the intermediate device Used for: triggering the virtual interrupt according to the information for triggering the virtual interrupt, and sending the virtual interrupt to the sending device; the sending device is used for: receiving the virtual interrupt from the intermediate device, and sending the virtual interrupt to the target physical processor.
  • the chip system may be a system on chip (system on chip, SOC), and the source physical processor and the target physical processor may each be a processing unit (processing unit), such as a physical core.
  • processing unit processing unit
  • the control device, the intermediate device and the sending device can all be implemented by hardware circuits or by software.
  • the source physical processor and the target physical processor can be physical cores in a multi-core processor.
  • the multi-core processor includes multiple physical cores.
  • the physical core is the core integrated in the processor.
  • the physical core is a processing unit, such as dual-core processing.
  • a processor can be understood as a processor with two physical cores. Control means and transmission means may be deployed in the multi-core processor, coupled to the source physical processor and the target physical processor.
  • the intermediary device may be deployed in the multi-core processor or on peripheral devices/peripheral components coupled to the multi-core processor.
  • a system on a chip may include a multi-core processor and peripheral devices/peripheral components coupled to the multi-core processor. Any physical processor in the chip system can be used as both a source physical processor and a target physical processor.
  • a virtual interrupt refers to a hardware device in a computer device, a host machine, a clock of the virtual machine or a virtual processor (virtual processor) of the virtual machine, etc. sent to a virtual machine (virtual machine, VM)
  • the hardware device that generates the virtual interrupt may be a disk, a network card, a sound card, a mouse, a hard disk, etc. in the computer device.
  • a physical interrupt refers to an interrupt sent by a hardware device to a physical processor. Physical interrupts are handled by the host, while virtual interrupts are handled by the virtual machine.
  • a specific implementation manner of the virtual processor mentioned in the various embodiments of this application may be a virtual central processing unit (virtual central processing unit, vCPU).
  • vCPU virtual central processing unit
  • the "vCPU” mentioned later can also be replaced by “virtual processor” to understand.
  • virtual interrupts may include virtual local interrupts, virtual software interrupts, virtual device interrupts, and direct peripheral interrupts.
  • the virtual local interrupt refers to an interrupt issued by a virtual local device simulated by the virtual machine or an interrupt issued by a local device of a vCPU of the virtual machine, such as a clock interrupt issued by a timer of a vCPU of the virtual machine.
  • a virtual software interrupt is triggered by software, usually refers to an interrupt sent by one vCPU of a virtual machine to another vCPU of the virtual machine.
  • a virtual machine can have multiple vCPUs, and these vCPUs can run on different physical processors at a time.
  • a virtual device interrupt refers to an interrupt triggered by a host computer emulating a hardware device, such as an interrupt generated by the host computer emulating a virtual machine disk controller or emulating other hardware devices.
  • the control device may include at least one register, wherein each register may be configured to receive one type of information for triggering a virtual interrupt.
  • each register may be configured to receive one type of information for triggering a virtual interrupt.
  • three registers are included, one register is used to receive information for triggering virtual local interrupts, one register is used to receive information used to trigger virtual software interrupts, and one register is used to receive information used to trigger virtual device interrupts.
  • only one register may be configured for the virtual interrupt, the information for triggering each type of virtual interrupt is different, and the type of the virtual interrupt can be identified by the information received by the register.
  • the sending device may be that each physical processor has one sending device, or multiple physical processors may share one sending device.
  • a register dedicated to processing virtual interrupts is set in the control device, so that the host or virtual machine in user mode or kernel mode can directly write information for triggering virtual interrupts into
  • the control device can send the information for triggering the virtual interrupt to the intermediate device, the virtual interrupt is triggered by the intermediate device, and the intermediate device sends the virtual interrupt to the sending device, and the sending device sends the virtual interrupt to the Target physical processor.
  • the host machine or the virtual machine can directly access the register, and write the information used to trigger the virtual interrupt into the register, so as to send the virtual interrupt out; therefore, compared with the prior art, the solution provided by the present application
  • the source physical processor does not need to perform the switch from the virtual machine to the host, nor does the source physical processor need to perform the switch from the user mode of the host to the kernel mode of the host, thereby reducing the switching overhead generated by processing virtual interrupts.
  • the performance of the chip system is improved.
  • the virtual interrupt is a virtual local interrupt
  • the target physical processor and the source physical processor are the same physical processor
  • the register is used for: receiving the data written by the virtual machine for triggering the virtual local interrupt information
  • the sending device is used for: sending the virtual partial interrupt to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.
  • the target physical processor and the source physical processor are the same physical processor.
  • the intermediary device may be a timer, and the virtual local interrupt may be a clock interrupt.
  • a physical processor can only run one vCPU of one virtual machine at a time, and the operation of sending the virtual local interrupt to the virtual machine can be completed by sending the virtual local interrupt to the vCPU. It can be known from this possible implementation that the process of processing the virtual local interrupt does not require the source physical processor to perform switching from the virtual machine to the host, thereby reducing the switching overhead generated by processing the virtual local interrupt and improving the performance of the chip system.
  • the virtual interrupt is a virtual software interrupt
  • the information used to trigger the virtual interrupt includes the identifier of the second vCPU written into the register by the first vCPU of the virtual machine, and the second vCPU is running on The vCPU of the virtual machine on the target physical processor
  • the control device is used to: read the identifier of the second vCPU from the register, and obtain the identifier of the virtual machine; and, send the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device
  • the intermediate device is used for: according to the identification of the virtual machine and the identification of the second vCPU, from the first corresponding relationship, determine the target physical processor corresponding to the identification of the virtual machine and the identification of the second vCPU; wherein, the first corresponding relationship uses recording the correspondence between the target physical processor, the second vCPU running on the target processor and the virtual machine; sending the virtual software interrupt to the sending device corresponding to the target physical processor; the sending
  • the virtual software interrupt is an interrupt sent by the first vCPU of the virtual machine to the second vCPU of the virtual machine. Therefore, when the first vCPU of the virtual machine wants to trigger the virtual software interrupt, the identifier of the second vCPU needs to be written into the register.
  • a virtual machine can have multiple vCPUs, and vCPUs belonging to the same virtual machine can be run on a physical processor in a time-division multiplexing manner. After processor 1 finishes running the vCPU1, it can run the vCPU2 of the virtual machine 1 again. Multiple vCPUs belonging to the same virtual machine can also run on different physical processors, and can run on different physical processors at a time.
  • Run different vCPUs for example: run vCPU1 of virtual machine 1 on physical processor 1, and run vCPU2 of virtual machine 1 on physical processor 2.
  • the first vCPU runs on the source physical processor
  • the second vCPU runs on the target physical processor.
  • the control device may acquire the identity of the virtual machine from a register dedicated to storing the identity of the virtual machine running on the source physical processor. Because each virtual machine may have multiple vCPUs, and the identifiers of the vCPUs of different virtual machines may be the same, the control apparatus needs to send the identifier of the virtual machine and the identifier of the second vCPU to the intermediate apparatus.
  • the above-mentioned first correspondence can be stored on the intermediate device, and the first correspondence can be located in the in-position vCPU identification group, and each physical processor, each physical processor in the chip system is recorded in the in-position vCPU identification group.
  • the present application can target physical processors by searching for the in-position vCPU identification group. It can be known from this possible implementation that the process of processing the virtual software interrupt does not require the source physical processor to perform switching from the virtual machine to the host, thereby reducing the switching overhead caused by processing the virtual software interrupt and improving the performance of the chip system.
  • the virtual interrupt is a virtual device interrupt
  • the information used to trigger the virtual interrupt includes a target interrupt number written into the register by the host and an identifier of the virtual machine
  • the target interrupt number is a host simulation
  • the identifier of the interrupt triggered by the hardware device the control device is used to: read the target interrupt number and the identifier of the virtual machine from the register, and send the identifier of the virtual machine and the target interrupt number to the intermediate device; the intermediate device is used for: according to the virtual machine
  • the identifier of the machine and the target interrupt number look for the identifier of the first vCPU of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number in the second correspondence, and the second correspondence is used to record the virtual machine, the target interrupt number and the first vCPU.
  • a correspondence between the vCPUs according to the identification of the virtual machine and the identification of the first vCPU, determine the target physical processor corresponding to the identification of the virtual machine and the identification of the first vCPU from the third correspondence; wherein, the third corresponding The relationship is used to record the corresponding relationship between the target physical processor, the first vCPU running on the target processor, and the virtual machine; send the virtual device interrupt to the sending device corresponding to the target physical processor; the sending device is used to: send the virtual device The device interrupt is sent to the first vCPU running on the target physical processor.
  • the virtual device interrupt is an interrupt triggered by the simulated hardware device of the host in the user mode.
  • the interrupt number of each type of hardware device is different. If the host computer simulates a disk, the target interrupt number is the interrupt number of the disk. Because there can be multiple virtual machines managed by the host, the host needs to write the identifier of the virtual machine and the target interrupt number into the register.
  • the second correspondence may be located in the interrupt affinity table.
  • the interrupt affinity table can be configured by the virtual machine, so there is one interrupt affinity table for each virtual machine.
  • the interrupt affinity table of the virtual machine can be found according to the identifier of the virtual machine, and then the corresponding vCPU is determined from the interrupt affinity table of the virtual machine according to the target interrupt number, and the target interrupt number is 10. If in the interrupt affinity table, the interrupt number 10 corresponds to vCPU ID1, it can be determined that the vCPU ID corresponding to the target interrupt number is 1. After the routing device determines that the vCPU ID is 1, it can find the physical processor corresponding to the vCPU ID1 according to the in-position vCPU identification group. The meaning of the in-position vCPU identification group can be understood by referring to the description of the aforementioned virtual software interrupt.
  • the third correspondence It can also be understood with reference to the foregoing first correspondence. It can be seen from this possible implementation that the process of processing the virtual device interrupt does not require the source physical processor to perform switching from the user mode of the host to the kernel mode of the host, thereby reducing the switching overhead generated by processing the virtual device interrupt and improving the performance of the virtual device. the performance of the system-on-chip.
  • the intermediate device includes an address register, and the address register is used to store the address of the second correspondence in the memory and the identifier of the virtual machine; the intermediate device is further configured to: according to the identifier of the virtual machine The address register is found, and the second correspondence is obtained from the memory according to the address in the address register.
  • the above-mentioned interrupt affinity table may be stored in an intermediate device or in a memory, and the intermediate device may provide an address register for each physical processor, and the address register may be a base
  • the address register, the base address register can store the address of the interrupt affinity table in the memory and the identifier of the virtual machine. This avoids taking up too much storage space for the intermediate device.
  • the sending device is configured to: write the virtual interrupt into a to-be-processed register of the target physical processor, and the to-be-processed register is used to receive a command of the process executed by the target physical processor.
  • the to-be-processed register is used to receive a command to be executed by the target physical processor next, and the virtual interrupt is written into the to-be-processed register, then the target physical processor will execute the next command.
  • This virtual interrupt can interrupt the currently executing process, thereby shielding the action of switching to the host in the existing solution. Reduces the switching overhead of the target physical processor from the virtual machine to the host.
  • a second aspect of the present application provides a chip system
  • the chip system includes a source physical processor, a control device, an intermediate device, a sending device, and a target physical processor, where the source physical processor is used to run a host machine or a virtual machine; the chip system further Including the hardware device that the virtual machine communicates directly with the virtual machine; the intermediate device is used to: receive the pass-through peripheral interrupt triggered by the hardware device; according to the physical interrupt number of the pass-through peripheral interrupt, find the corresponding virtual machine ID and ID from the virtual interrupt table.
  • Virtual interrupt number the virtual interrupt table records the correspondence between the physical interrupt number and the virtual machine identifier and the virtual interrupt number; the corresponding interrupt affinity table is determined according to the virtual machine identifier, and the virtual machine is determined from the interrupt affinity table.
  • the identifier of the target virtual processor vCPU corresponding to the virtual interrupt number, and the corresponding relationship between the virtual interrupt number and the virtual processor is recorded in the interrupt affinity table; According to the identifier of the target vCPU, determine the target vCPU from the in-position vCPU identifier group The identifier of the corresponding target physical processor; the pass-through peripheral interrupt is sent to the sending device corresponding to the target physical processor. The sending means sends the pass-through peripheral interrupt to the virtual machine running on the target physical processor.
  • the pass-through peripheral device interrupt refers to an interrupt that is triggered by an external device passed through to the virtual machine, for example, an interrupt generated by a graphics card passed through to the virtual machine.
  • the virtual interrupt table, the interrupt affinity table and the in-position vCPU identification group will be used in turn.
  • the interrupt affinity table and the in-position vCPU identification group can refer to the possible The description in the implementation mode is understood, and the virtual interrupt table is introduced below.
  • the virtual interrupt table maintains the corresponding relationship between the physical interrupt number and the ID of the virtual machine and the virtual interrupt number. Entering a physical interrupt number can output the ID of the virtual machine and the virtual interrupt number.
  • the intermediate device receives the physical interrupt number sent by the pass-through peripheral, and searches the virtual interrupt table for the identifier and virtual interrupt number of the corresponding virtual machine through the physical interrupt number, for example: input a physical interrupt Number 100, the ID 1 of the virtual machine and the virtual interrupt number 10 can be output. Then, according to the ID 1 of the virtual machine and the virtual interrupt number 10, the interrupt affinity table is searched, and the corresponding vCPU ID is found, for example, the vCPU ID is found to be 1.
  • the intermediate device can send the pass-through peripheral interrupt to the corresponding sending device of the physical processor 1, by The sending device sends the pass-through peripheral interrupt to the vCPU corresponding to the vCPU ID1.
  • the sending process can be completed by searching three corresponding relationships, which improves the flexibility of the cut-through peripheral interrupt processing.
  • a third aspect of the present application provides a control device.
  • the control device is applied to a chip system.
  • the chip system further includes a source physical processor, an intermediate device, and a sending device.
  • the source physical processor is used to run a host machine or a virtual machine, and the control device includes a register. ;
  • the register is used to receive the information used to trigger the virtual interrupt, and the information used to trigger the virtual interrupt comes from the host or the virtual machine;
  • the control device is used to: read the information used to trigger the virtual interrupt from the register, and use it for The information for triggering the virtual interrupt is sent to the intermediate device, and the information for triggering the virtual interrupt is used to make the intermediate device trigger the virtual interrupt, and the virtual interrupt is sent by the sending device to the target physical processor.
  • the virtual interrupt is a virtual local interrupt
  • the target physical processor and the source physical processor are the same physical processor
  • the register is used to receive the data written by the virtual machine for triggering the virtual local interrupt
  • the control device is used to: send the information used to trigger the virtual partial interrupt to the intermediate device, and the information used to trigger the virtual partial interrupt is used to make the intermediate device trigger the virtual partial interrupt, and the virtual partial interrupt is sent by the sending device to the virtual machine
  • the first virtual processor vCPU of the first vCPU runs on the source physical processor.
  • the virtual interrupt is a virtual software interrupt
  • the information used to trigger the virtual interrupt includes the identifier of the second vCPU written into the register by the first VCPU of the virtual machine, and the second vCPU is running on The vCPU of the virtual machine on the target physical processor;
  • the control device is used to: read the identifier of the second vCPU from the register, and obtain the identifier of the virtual machine; and, send the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device , the identifier of the virtual machine and the identifier of the second vCPU are used by the intermediary device to determine the target physical processor and trigger a virtual software interrupt, and the virtual software interrupt is sent by the sending device to the second vCPU of the target physical processor.
  • the virtual interrupt is a virtual device interrupt
  • the information used to trigger the virtual interrupt includes a target interrupt number written into the register by the host and an identifier of the virtual machine, and the target interrupt number is a host simulation
  • the identifier of the interrupt triggered by the hardware device; the control device is used to: read the target interrupt number and the identifier of the virtual machine from the register, and send the identifier of the virtual machine and the target interrupt number to the intermediate device, the identifier of the virtual machine and the target interrupt
  • the number is used by the intermediate device to determine the target physical processor and trigger the virtual device interrupt, and the virtual device interrupt is sent by the sending device to the first vCPU of the virtual machine of the target physical processor.
  • a fourth aspect of the present application provides an intermediate device.
  • the intermediate device is applied to a chip system.
  • the chip system further includes a source physical processor, a control device, a sending device, and a target physical processor.
  • the source physical processor is used to run a host machine or a virtual machine.
  • the control device includes a register; the register is used to receive the information used to trigger the virtual interrupt, and the information used to trigger the virtual interrupt comes from the host machine or the virtual machine; the intermediate device is used to: receive the information used to trigger the virtual interrupt from the control device , triggering the virtual interrupt according to the information for triggering the virtual interrupt, and sending the virtual interrupt to the sending device, and the virtual interrupt is sent by the sending device to the target physical processor.
  • the virtual interrupt is a virtual local interrupt
  • the target physical processor and the source physical processor are the same physical processor
  • the register is used to receive the virtual local interrupt written by the virtual machine for triggering the virtual local interrupt
  • the intermediate device is used for: triggering the virtual local interrupt according to the information used to trigger the virtual local interrupt, and sending the virtual local interrupt to the sending device, and the virtual local interrupt is sent by the sending device to the first virtual processor vCPU of the virtual machine , the first vCPU runs on the source physical processor.
  • the virtual interrupt is a virtual software interrupt
  • the information used to trigger the virtual interrupt includes the identifier of the second vCPU written into the register by the first vCPU of the virtual machine, and the second vCPU is running on The vCPU of the virtual machine on the target physical processor
  • the intermediate device is used for: receiving the identifier of the virtual machine and the identifier of the second vCPU from the control device; according to the identifier of the virtual machine and the identifier of the second vCPU, from the first correspondence Determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU; wherein the first correspondence is used to record the correspondence between the target physical processor, the second vCPU running on the target processor, and the virtual machine triggering a virtual software interrupt; sending the virtual software interrupt to a sending device corresponding to the target physical processor, and the virtual software interrupt is sent by the sending device to the second vCPU of the target physical processor.
  • the virtual interrupt is a virtual device interrupt
  • the information used to trigger the virtual interrupt includes a target interrupt number written into the register by the host and an identifier of the virtual machine
  • the target interrupt number is a host simulation
  • the identifier of the interrupt triggered when the hardware device is used; the intermediate device is used to: receive the identifier of the virtual machine and the target interrupt number from the control device; Identifies the identifier of the first vCPU of the virtual machine corresponding to the target interrupt number, and the second correspondence is used to record the correspondence between the virtual machine, the target interrupt number and the first vCPU; according to the identifier of the virtual machine and the identifier of the first vCPU , determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the first vCPU from the third correspondence; wherein, the third correspondence is used to record the target physical processor, the first vCPU running on the target processor, and Correspondence between virtual machines; triggering a virtual
  • the intermediate device includes an address register, and the address register is used to store the address of the second correspondence in the memory and the identifier of the virtual machine; the intermediate device is further configured to: according to the identifier of the virtual machine The address register is found, and the second correspondence is obtained from the memory according to the address in the address register.
  • a fifth aspect of the present application provides a sending device.
  • the sending device is applied to a chip system.
  • the chip system further includes a source physical processor, an intermediate device, and a target physical processor control device.
  • the source physical processor is used to run a host machine or a virtual machine.
  • the control device includes a register; the register is used to receive the information used to trigger the virtual interrupt, and the information used to trigger the virtual interrupt comes from the host machine or the virtual machine; the sending device is used to: receive the virtual interrupt from the intermediate device, and send the virtual interrupt to the virtual interrupt.
  • the interrupt is sent to the target physical processor.
  • the virtual interrupt is a virtual local interrupt
  • the target physical processor and the source physical processor are the same physical processor
  • the sending device is configured to: receive the virtual local interrupt from the intermediate device, and The virtual local interrupt is sent to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.
  • the virtual interrupt is a virtual software interrupt
  • the information used to trigger the virtual interrupt includes the identifier of the second vCPU written into the register by the first vCPU of the virtual machine, and the second vCPU is running on The vCPU of the virtual machine on the target physical processor;
  • the sending device is used for: receiving the virtual software interrupt from the intermediate device, and sending the virtual software interrupt to the second vCPU running on the target physical processor.
  • the virtual interrupt is a virtual device interrupt
  • the information used to trigger the virtual interrupt includes a target interrupt number written into a register by the host and an identifier of the virtual machine, and the target interrupt number is a host simulation
  • the identifier of the interrupt triggered by the hardware device; the sending device is used for: receiving the virtual device interrupt from the intermediate device, and sending the virtual device interrupt to the first vCPU running on the target physical processor.
  • the sending device is configured to: write the virtual interrupt into a pending register of the target physical processor, and the pending register is used to receive a command of the process executed by the target physical processor.
  • a sixth aspect of the present application provides a method for processing virtual interrupts.
  • the method is applied to a control device in a chip system.
  • the chip system further includes a source physical processor, an intermediate device, a sending device, and a target physical processor.
  • the source physical processor uses For running a host machine or a virtual machine, the control device includes a register; the register is used for receiving information for triggering a virtual interrupt, and the information for triggering a virtual interrupt comes from the host machine or the virtual machine, and the method includes: reading from the register The information used to trigger the virtual interrupt; the information used to trigger the virtual interrupt is sent to the intermediate device, the information used to trigger the virtual interrupt is used by the intermediate device to trigger the virtual interrupt, and the virtual interrupt is sent by the sending device to the target physical processor.
  • the virtual interrupt is a virtual local interrupt
  • the target physical processor and the source physical processor are the same physical processor
  • the register is used to receive the data written by the virtual machine and used to trigger the virtual local interrupt
  • the information used to trigger the virtual local interrupt is used to make the intermediate device trigger the virtual local interrupt
  • the virtual local interrupt is sent by the sending device to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.
  • the virtual interrupt is a virtual software interrupt
  • the information used to trigger the virtual interrupt includes the identifier of the second vCPU written into the register by the first VCPU of the virtual machine, and the second vCPU is running on the vCPU of the virtual machine on the target physical processor; the method further includes: acquiring the identifier of the virtual machine; sending the identifier of the virtual machine to the intermediate device, and the identifier of the virtual machine and the identifier of the second vCPU are used by the intermediate device to determine the target physical processing and triggers a virtual software interrupt, and the virtual software interrupt is sent by the sending device to the second vCPU of the target physical processor.
  • the virtual interrupt is a virtual device interrupt
  • the information used to trigger the virtual interrupt includes a target interrupt number written into the register by the host and an identifier of the virtual machine, and the target interrupt number is a host simulation
  • the identifier of the interrupt triggered by the hardware device; the identifier of the virtual machine and the target interrupt number are used by the intermediate device to determine the target physical processor and trigger the virtual device interrupt, and the virtual device interrupt is sent by the sending device to the first vCPU of the target physical processor.
  • a seventh aspect of the present application provides a method for processing virtual interrupts.
  • the method is applied to an intermediate device in a chip system.
  • the chip system further includes a source physical processor, a control device, a sending device, and a target physical processor.
  • the source physical processor is used for Running the host or virtual machine
  • the control device includes a register; the register is used to receive information for triggering a virtual interrupt, the information for triggering a virtual interrupt comes from the host or the virtual machine
  • the method includes: receiving the information from the control device. information for triggering the virtual interrupt; triggering the virtual interrupt according to the information for triggering the virtual interrupt; sending the virtual interrupt to the sending device, and the virtual interrupt is sent by the sending device to the target physical processor.
  • the virtual interrupt is a virtual local interrupt
  • the target physical processor and the source physical processor are the same physical processor
  • the register is used to receive the virtual local interrupt written by the virtual machine for triggering the virtual local interrupt
  • the information used to trigger the virtual local interrupt is used to trigger the virtual local interrupt
  • the virtual local interrupt is sent by the sending device to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.
  • the virtual interrupt is a virtual software interrupt
  • the information used to trigger the virtual interrupt includes the identifier of the second vCPU written into the register by the first vCPU of the virtual machine, and the second vCPU is running on The vCPU of the virtual machine on the target physical processor; the above steps: triggering the virtual interrupt according to the information for triggering the virtual interrupt, including: according to the identifier of the virtual machine and the identifier of the second vCPU, determining from the first correspondence relationship with the virtual machine The target physical processor corresponding to the identifier of the second vCPU and the identifier of the second vCPU; wherein, the first correspondence is used to record the correspondence between the target physical processor, the second vCPU running on the target processor and the virtual machine; trigger the virtual software interrupt, the virtual software interrupt is sent by the sending means to the second vCPU of the target physical processor.
  • the virtual interrupt is a virtual device interrupt
  • the information used to trigger the virtual interrupt includes a target interrupt number written into the register by the host and an identifier of the virtual machine, and the target interrupt number is a host simulation
  • the identifier of the interrupt triggered when the hardware device the above steps: triggering the virtual interrupt according to the information for triggering the virtual interrupt, including: according to the identifier of the virtual machine and the target interrupt number, searching for the identifier and the virtual machine in the second corresponding relationship.
  • the identifier of the first vCPU of the virtual machine corresponding to the target interrupt number, and the second correspondence is used to record the corresponding relationship between the virtual machine, the target interrupt number and the first vCPU; according to the identifier of the virtual machine and the identifier of the first vCPU, from
  • the target physical processor corresponding to the identifier of the virtual machine and the identifier of the first vCPU is determined; wherein, the third correspondence is used to record the target physical processor, the first vCPU running on the target processor, and the virtual machine
  • the corresponding relationship between the virtual device interrupts is triggered, and the virtual device interrupts are sent by the sending device to the first vCPU of the target physical processor.
  • the method further includes: finding an address register according to an identifier of the virtual machine, obtaining a second correspondence from a memory according to an address in the address register, and the address register is used to store the second correspondence The address of the correspondence in memory and the identifier of the virtual machine.
  • An eighth aspect of the present application provides a method for processing virtual interrupts.
  • the method is applied to a sending device in a chip system.
  • the chip system further includes a source physical processor, an intermediate device, a control device, and a target physical processor.
  • the source physical processor is used for Running a host machine or a virtual machine
  • the control device includes a register; the register is used for receiving information for triggering a virtual interrupt, the information for triggering a virtual interrupt comes from the host machine or the virtual machine, and the method includes: receiving from the intermediate device. Virtual interrupt; sends a virtual interrupt to the target physical processor.
  • the virtual interrupt is a virtual local interrupt
  • the target physical processor and the source physical processor are the same physical processor; the above steps: sending the virtual interrupt to the target physical processor, including: The virtual local interrupt is sent to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.
  • the virtual interrupt is a virtual software interrupt
  • the information used to trigger the virtual interrupt includes the identifier of the second vCPU written into the register by the first vCPU of the virtual machine, and the second vCPU is running on The vCPU of the virtual machine on the target physical processor; the above steps: sending the virtual interrupt to the target physical processor includes: sending the virtual software interrupt to the second vCPU running on the target physical processor.
  • the virtual interrupt is a virtual device interrupt
  • the information used to trigger the virtual interrupt includes a target interrupt number written into a register by the host and an identifier of the virtual machine, and the target interrupt number is a host simulation
  • the identifier of the interrupt triggered by the hardware device; the above steps: sending the virtual interrupt to the target physical processor includes: sending the virtual device interrupt to the first vCPU running on the target physical processor.
  • the method further includes: writing the virtual interrupt into a to-be-processed register of the target physical processor, where the to-be-processed register is used to receive a command of the process executed by the target physical processor.
  • a ninth aspect of the present application provides a control device, the control device is applied in a chip system, the chip system further includes a source physical processor, an intermediate device, a sending device and a target physical processor, and the source physical processor is used to run a host or A virtual machine, the control device includes a register; the register is used to receive information for triggering a virtual interrupt, and the information for triggering a virtual interrupt comes from a host machine or a virtual machine, and the control device includes: a reading unit for reading from the register.
  • the sending unit is used to send the information used to trigger the virtual interrupt to the intermediate device, the information used to trigger the virtual interrupt is used by the intermediate device to trigger the virtual interrupt, and the virtual interrupt is sent by the sending device to the intermediate device.
  • Target physical processor
  • the virtual interrupt is a virtual local interrupt
  • the target physical processor and the source physical processor are the same physical processor
  • the register is used to receive the virtual local interrupt written by the virtual machine for triggering the virtual local interrupt
  • the information used to trigger the virtual local interrupt is used to make the intermediate device trigger the virtual local interrupt
  • the virtual local interrupt is sent by the sending device to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.
  • the virtual interrupt is a virtual software interrupt
  • the information used to trigger the virtual interrupt includes an identifier of the second vCPU written into the register by the first VCPU of the virtual machine, and the second vCPU is running on the vCPU of the virtual machine on the target physical processor
  • the control device further includes a processing unit, the processing unit is used to obtain the identifier of the virtual machine
  • the sending unit is used to send the identifier of the virtual machine to the intermediate device, the identifier of the virtual machine and the identifier of the second vCPU are used by the intermediary device to determine the target physical processor and trigger a virtual software interrupt
  • the virtual software interrupt is sent by the sending device to the second vCPU of the target physical processor.
  • the virtual interrupt is a virtual device interrupt
  • the information used to trigger the virtual interrupt includes a target interrupt number written into the register by the host and an identifier of the virtual machine, and the target interrupt number is a host simulation
  • the identifier of the interrupt triggered by the hardware device; the identifier of the virtual machine and the target interrupt number are used by the intermediate device to determine the target physical processor and trigger the virtual device interrupt, and the virtual device interrupt is sent by the sending device to the first vCPU of the target physical processor.
  • a tenth aspect of the present application provides an intermediate device.
  • the intermediate device is applied to a chip system, and the chip system further includes a source physical processor, a control device, a sending device, and a target physical processor.
  • the source physical processor is used to run a host or A virtual machine
  • the control device includes a register; the register is used to receive information for triggering a virtual interrupt, the information for triggering a virtual interrupt comes from a host machine or a virtual machine
  • the intermediate device includes: a receiving unit for receiving information from the control device The information used to trigger the virtual interrupt; the processing unit is used to trigger the virtual interrupt according to the information used to trigger the virtual interrupt; the sending unit is used to send the virtual interrupt to the sending device, and the virtual interrupt is sent by the sending device to the target physical processor .
  • the virtual interrupt is a virtual local interrupt
  • the target physical processor and the source physical processor are the same physical processor
  • the register is used to receive the data written by the virtual machine and used to trigger the virtual local interrupt
  • the information used to trigger the virtual local interrupt is used to trigger the virtual local interrupt
  • the virtual local interrupt is sent by the sending device to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.
  • the virtual interrupt is a virtual software interrupt
  • the information used for triggering the virtual interrupt includes an identifier of a second vCPU written into a register by the first vCPU of the virtual machine, and the second vCPU is running on The vCPU of the virtual machine on the target physical processor;
  • the processing unit is used to determine, according to the identifier of the virtual machine and the identifier of the second vCPU, the target physical device corresponding to the identifier of the virtual machine and the identifier of the second vCPU from the first correspondence processor; wherein, the first correspondence is used to record the correspondence between the target physical processor, the second vCPU running on the target processor, and the virtual machine; triggering a virtual software interrupt, the virtual software interrupt is sent by the sending device to the target physical processor The processor's second vCPU.
  • the virtual interrupt is a virtual device interrupt
  • the information used to trigger the virtual interrupt includes a target interrupt number written into the register by the host machine and an identifier of the virtual machine, and the target interrupt number is the host machine simulation
  • the identifier of the interrupt triggered during the hardware device; the processing unit is used to search the first vCPU of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number in the second correspondence according to the identifier of the virtual machine and the target interrupt number.
  • the second correspondence is used to record the correspondence between the virtual machine, the target interrupt number and the first vCPU; according to the identification of the virtual machine and the identification of the first vCPU, determine the identification and The target physical processor corresponding to the identifier of the first vCPU; wherein, the third corresponding relationship is used to record the corresponding relationship between the target physical processor, the first vCPU running on the target processor, and the virtual machine;
  • the device interrupt is sent by the sending means to the first vCPU of the target physical processor.
  • the processing unit is further configured to find the address register according to the identifier of the virtual machine, obtain the second correspondence from the memory according to the address in the address register, and the address register is used for storing The second corresponding relationship is the address in the memory and the identifier of the virtual machine.
  • An eleventh aspect of the present application provides a sending device.
  • the sending device is applied to a chip system.
  • the chip system further includes a source physical processor, an intermediate device, a control device, and a target physical processor.
  • the source physical processor is used to run a host machine. or virtual machine
  • the control device includes a register; the register is used to receive information used to trigger a virtual interrupt, the information used to trigger a virtual interrupt comes from the host machine or the virtual machine
  • the sending device includes: a receiving unit for receiving information from an intermediate The virtual interrupt of the device; the sending unit is used to send the virtual interrupt to the target physical processor.
  • the virtual interrupt is a virtual local interrupt
  • the target physical processor and the source physical processor are the same physical processor
  • the sending unit is configured to send the virtual local interrupt to the virtual machine's
  • the first virtual processor vCPU runs on the source physical processor.
  • the virtual interrupt is a virtual software interrupt
  • the information used to trigger the virtual interrupt includes the identifier of the second vCPU written into the register by the first vCPU of the virtual machine, and the second vCPU is running the vCPU of the virtual machine on the target physical processor; the sending unit is configured to send the virtual software interrupt to the second vCPU running on the target physical processor.
  • the virtual interrupt is a virtual device interrupt
  • the information used to trigger the virtual interrupt includes a target interrupt number written into the register by the host and an identifier of the virtual machine, and the target interrupt number is the host machine
  • the identifier of the interrupt triggered when the hardware device is simulated; the sending unit is configured to send the virtual device interrupt to the first vCPU running on the target physical processor.
  • the sending unit is configured to write the virtual interrupt into a to-be-processed register of the target physical processor, and the to-be-processed register is used to receive a command of the process executed by the target physical processor.
  • a twelfth aspect of the present application provides a computer-readable storage medium storing one or more computer-executable instructions.
  • the processor executes any one of the above-mentioned sixth aspect or the sixth aspect. method of implementation.
  • a thirteenth aspect of the present application provides a computer-readable storage medium storing one or more computer-executable instructions.
  • the processor executes any one of the above seventh aspect or the seventh aspect. method of implementation.
  • a fourteenth aspect of the present application provides a computer-readable storage medium that stores one or more computer-executable instructions.
  • the processor executes the eighth aspect or any of the eighth aspects. method of implementation.
  • a fifteenth aspect of the present application provides a computer program product that stores one or more computer-executable instructions.
  • the processor executes any possible implementation of the sixth aspect or the sixth aspect. way method.
  • a sixteenth aspect of the present application provides a computer program product that stores one or more computer-executable instructions.
  • the processor executes any possible implementation of the seventh aspect or the seventh aspect. way method.
  • a seventeenth aspect of the present application provides a computer program product that stores one or more computer-executable instructions.
  • the processor executes the eighth aspect or any of the possible implementations of the eighth aspect. way method.
  • An eighteenth aspect of the present application provides a computer device, where the computer device includes the chip system described in the first aspect or any possible implementation manner of the first aspect.
  • a nineteenth aspect of the present application provides a chip system, where the chip system includes a source physical processor, a control device and a sending device, and a target physical processor.
  • the control device is the aforementioned third aspect, the ninth aspect, any possible implementation manner of the third aspect or any possible implementation manner of the ninth aspect
  • the sending device is any of the aforementioned fifth aspect, the eleventh aspect, and the eleventh aspect.
  • the chip system may further include the intermediate device described in any possible implementation manner of the foregoing fourth aspect, tenth aspect, or tenth aspect, or any possible implementation manner of the fourth aspect.
  • the chip system provided in the nineteenth aspect is a processor, the source physical processor and the target physical processor are physical cores in the processor, and the control device is located in the processor and is connected to the source physical processor.
  • the physical core may include both a control device and a transmission device.
  • a register dedicated to processing virtual interrupts is set in the control device.
  • the host machine or virtual machine in the user state can directly write the information used to trigger the virtual interrupt into the register, and control the
  • the device can send the information for triggering the virtual interrupt to the intermediate device, the virtual interrupt is triggered by the intermediate device, and the intermediate device sends the virtual interrupt to the sending device, and the sending device sends the virtual interrupt to the target physical processor.
  • the host machine or the virtual machine can directly access the register, and write the information used to trigger the virtual interrupt into the register, so as to send the virtual interrupt out; therefore, compared with the prior art, the solution provided by the present application
  • the source physical processor does not need to perform switching from the virtual machine to the host, or perform switching from the user mode of the host to the kernel mode of the host, thereby reducing the switching overhead generated by processing virtual interrupts and improving the performance of the chip system .
  • FIG. 1 is a schematic structural diagram of a computer device provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a type of virtual interrupt provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a chip system provided by an embodiment of the present application.
  • FIG. 4 is another schematic structural diagram of a chip system provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a virtual clock interruption provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of an example of an in-position virtual processor identification group provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of an example of a virtual software interrupt provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a routing device provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of an example of a cut-through peripheral interrupt provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a chip system in a RISC-V microarchitecture provided by an embodiment of the present application
  • FIG. 11 is a schematic diagram of a process of processing clock interrupts in the RISC-V microarchitecture provided by an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a process for processing virtual software interrupts in the RISC-V microarchitecture provided by an embodiment of the present application
  • FIG. 13 is a schematic diagram of a process for processing virtual device interrupts in the RISC-V microarchitecture provided by an embodiment of the present application
  • FIG. 14 is a schematic diagram of another process for processing virtual device interrupts in the RISC-V microarchitecture provided by an embodiment of the present application.
  • FIG. 15 is a schematic diagram of a process of processing a pass-through peripheral interrupt in the RISC-V micro-architecture provided by an embodiment of the present application;
  • FIG. 16 is a schematic diagram of an embodiment of a method for processing a virtual interrupt provided by an embodiment of the present application.
  • FIG. 17 is a schematic diagram of an embodiment of a control device provided by an embodiment of the present application.
  • FIG. 18 is a schematic diagram of an embodiment of an intermediate device provided by an embodiment of the present application.
  • FIG. 19 is a schematic diagram of an embodiment of a sending apparatus provided by an embodiment of the present application.
  • FIG. 20 is another schematic structural diagram of a computer device provided by an embodiment of the present application.
  • Embodiments of the present application provide a chip system, a method for processing virtual interrupts, and a corresponding device, which are used to reduce the switching from a virtual machine to a host machine, or from a user state of a host machine to a kernel state of the host machine due to virtual interrupts. overhead.
  • the embodiments of the present application also provide corresponding computer devices, computer storage media, computer program products, and the like. Each of them will be described in detail below.
  • Virtualization is to virtualize hardware resources (such as processors, storage space in memory, and network resources) in the hardware layer of a computer device and share them for use by multiple virtual computers.
  • a virtual computer is a general term for a running environment virtualized by software in all types of virtualization devices, and the concept includes virtual machines or containers.
  • the computer device 100 includes a hardware layer 112 , a host layer 109 and a virtualization layer, and the virtualization layer includes virtual machines 101 and 102 .
  • the number of virtual machines may be more or less, and only two are taken as an example here.
  • Hardware layer 112 includes processor system 114 , memory 113 , communication interface 115 and interrupt controller 116 .
  • a virtual machine is simulated on a computer device through virtualization software.
  • a guest operating system (guest OS) (105 and 106 in Fig. 1) can be installed on the virtual machine (101 and 102 in Fig. 1), and one or more applications (103 in Fig. 1) run on the guest operating system. and 104).
  • Virtual machines can also access network resources. For applications running in a virtual machine, it is like working on a real computer.
  • Virtual processor (107 and 108 in Figure 1): Under the virtualization technology, it represents a processing unit provided to a virtual computer in a shared or sharded manner, such as a virtual central processing unit (vCPU).
  • a virtual computer can be served by one or more virtual processors. When there are multiple virtual processors, usually one virtual processor is the master virtual processor, and the others are slave virtual processors. Other virtual hardware resources such as virtual memory included in the virtual machine are not shown in FIG. 1 .
  • the virtual processor is virtualized by virtualization software, and its operation is actually realized by the processor or physical core of the host machine reading and running the software program. For example, a physical core reads the software program and assists in the hardware of the physical core.
  • the software program is run in a specific mode of virtualization (eg x86's non-Root mode) to implement a virtual processor.
  • Multiple virtual processors of a virtual machine can be located on different physical cores.
  • the vCPU mentioned in the various embodiments of this application is an optional specific implementation manner of the virtual processor.
  • the "vCPU" mentioned in the various embodiments may be understood as being replaced by a "virtual processor”.
  • Virtual processor trap (trap in) and virtual processor trap (trap out) The virtualization system includes two modes: host mode and guest mode.
  • the host mode can also be referred to as the privilege level of the host, such as the user mode of the host or the kernel mode of the host, and the guest mode can also be referred to as the privilege level of the VM, such as the user mode of the VM or the kernel mode of the VM.
  • trapping virtual
  • the process of trapping can also be understood as the switching of the physical processor from the running host to the running virtual machine; when the physical processor leaves the guest mode, it is called trapping (virtual).
  • the process of trapping can also be understood as the physical processor switching from running the virtual machine to running the host. After the trap, the physical processor will temporarily not execute the code of the virtual processor, so it can be understood that the virtual processor is not running at this time.
  • running a virtual machine on a physical processor it will run one virtual processor of the virtual machine.
  • a virtual machine can have multiple virtual processors.
  • a physical processor only runs one virtual processor of the virtual machine at a time. Multiple virtual processors of the same virtual machine can run on the physical processor in a time-division multiplexing manner. For example, run vCPU1 of virtual machine 1 on physical processor 1 first, and physical processor 1 ends the vCPU1. After running, you can run the vCPU2 of the virtual machine 1 again.
  • the host layer 109 is used as a management layer to complete the management and allocation of hardware resources, and to provide various virtual hardware resources for virtual machines, such as virtual processors (107, 108), virtual memory, virtual disks, virtual network cards, etc., It can also implement scheduling and isolation of virtual machines.
  • the host layer 109 may include a host operating system 111 and a virtual monitoring device, such as a virtual machine monitor 110 (virtual machine monitor, VMM).
  • the virtual monitor 110 may be deployed within the host operating system 111 , or may be deployed outside the host operating system 111 .
  • the virtual monitoring device may also be referred to as a hypervisor or other types of virtual monitoring devices.
  • the host layer 109 may also be referred to as a virtualization platform, and sometimes the host layer may also be simply referred to as a host.
  • the privilege level of the host includes user mode and kernel mode.
  • Hardware layer 112 The hardware platform on which the virtualization environment runs.
  • the hardware layer may include a variety of hardware.
  • the hardware layer may include a processor system 114 and a memory 113, and may also include a communication interface 115, such as a network interface card (NIC); and may also include interrupt control 116, input/output (I/O) devices, and the like.
  • the processor system 114 may include one or more processors, such as processor 1 and processor 2 as listed in FIG. 1 .
  • Each processor may include multiple physical cores, and the processor may further include multiple registers, such as general-purpose registers, floating-point registers, and the like.
  • the processor system 114 may include multiple processors, such as processor 1 and processor 2 in FIG. 1 . Both the processor 1 and the processor 2 in FIG. 1 are physical processors, such as a source physical processor and a target physical processor. Each physical processor can be understood as a physical core.
  • the processor system 114 may be embodied as a multi-core processor, and the multi-core processor includes a source physical processor and a target physical processor.
  • a virtual processor and a physical core can be in a bound relationship, that is, a virtual processor is fixed to run on a certain physical core and cannot be scheduled to run on other physical cores, then the virtual processor is a bound core; a virtual processor If it can be scheduled to run on different physical cores as required, the virtual processor is a non-core bound.
  • the interrupt controller 116 is set between the hardware that triggers the interrupt request and the processor, and is mainly used to collect the interrupt request generated by each hardware and send it to the processor according to a certain priority or other rules.
  • Interrupts can include virtual interrupts and physical interrupts.
  • Virtual interrupts refer to hardware devices in computer equipment, the host, the clock of the virtual machine, or the virtual central processing unit (vCPU) of the virtual machine.
  • virtual machine, VM) interrupt the hardware device that generates the virtual interrupt may be a disk, a network card, a sound card, a mouse, a hard disk, etc. in the computer device.
  • a physical interrupt refers to an interrupt notified to a physical processor by a hardware device. Physical interrupts are handled by the host, while virtual interrupts are handled by the virtual machine.
  • ISR interrupt service routine
  • An interrupt service routine also known as an interrupt handler, is a program used to process interrupt requests.
  • the processor receives an interrupt request, it temporarily stops the execution of the current program and executes the interrupt service program corresponding to the interrupt request.
  • the storage space (address space) provided by the memory 113 is divided for use by the virtual machine and the host machine.
  • the host physical address (HPA) refers to the physical address space that the local host (host) can use;
  • the host virtual address (HVA) is the virtual address that the local host (host) can use. space.
  • the guest physical address (GPA) is the physical address space usable by the guest operating system of the virtual machine;
  • the guest virtual address (GVA) is the virtual address space usable by the guest operating system of the virtual machine.
  • the computer device 100 may be a physical device, such as a server or a terminal device.
  • the end device may be a handheld device with wireless connectivity, or other processing device connected to a wireless modem.
  • it can be a mobile phone, a personal computer (PC), a tablet computer, a personal digital assistant (PDA), a mobile Internet device (MID), a wearable device and an e-book reader (e -book reader), etc.; it can also be a portable, pocket-sized, hand-held, computer built-in or vehicle-mounted mobile device.
  • the virtual machine or the host machine in the above-mentioned computer device 100 may send the information for triggering the virtual interrupt, and then the corresponding process of processing the virtual interrupt is completed by the chip system provided in the embodiment of the present application.
  • the chip system provided by the embodiment of the present application may include the interrupt controller and the processor system in the foregoing FIG. 1 , or may include the interrupt controller or the processor system in the foregoing FIG. 1 .
  • the virtual interrupt may include a virtual local interrupt (virtual local interrupt), a virtual software interrupt (virtual software interrupt), and a virtual device interrupt (virtual device interrupt) and direct peripheral interrupt.
  • the virtual local interrupt refers to an interrupt simulated by a virtual machine, such as an interrupt issued by a virtual local device such as a virtual timer and a virtual mouse, or an interrupt issued by a local device of a vCPU of the virtual machine, such as the timing of a vCPU of the virtual machine.
  • the interrupt issued by the timer is also called the clock interrupt.
  • the clock interrupt refers to the interrupt issued by the timer when the time point configured by the virtual machine is reached by the timer.
  • the virtual software interrupt is triggered by software, usually refers to the interrupt sent by one vCPU of the virtual machine to another vCPU of the virtual machine, such as the interrupt sent by the first vCPU belonging to the same virtual machine to the second vCPU in Figure 2,
  • a virtual machine can have multiple vCPUs, and these vCPUs can run on different physical processors at a time to perform different tasks of the virtual machine. When the tasks executed by different vCPUs have dependencies or need to be scheduled, they will be A virtual software interrupt has occurred.
  • a virtual device interrupt refers to an interrupt triggered by a host computer emulating a hardware device, such as an interrupt generated by the host computer emulating a virtual machine disk controller or emulating other hardware devices.
  • Pass-through peripheral interrupts refer to interrupts that are triggered by external devices that are passed through to the virtual machine, for example, the interrupts generated by the graphics card passed through to the virtual machine.
  • an embodiment of the present application provides a chip system, in the process of processing virtual interrupts, it is not necessary to switch the physical processor running the virtual machine from the virtual machine to the host machine, or from the user mode of the host machine to the host machine.
  • the kernel mode can save switching overhead.
  • the chip system includes: a source physical processor, a control device, an intermediate device, a sending device, and a target physical processor.
  • the source physical processor is used to run a host machine or a virtual machine
  • the control device includes Register, the register is used to receive the information for triggering the virtual interrupt, the information for triggering the virtual interrupt can come from the host machine or the virtual machine;
  • the control device is used for: sending the information in the register for triggering the virtual interrupt to the middle device;
  • the intermediate device is used for: triggering the virtual interrupt according to the information for triggering the virtual interrupt, and sending the virtual interrupt to the sending device;
  • the sending device is used for: receiving the virtual interrupt from the intermediate device, and sending the virtual interrupt to the target physical device processor.
  • the chip system can be applied to the computer device shown in FIG. 1 above, and the chip system can be the interrupt controller or the processor system in the above-mentioned FIG. 1 .
  • the chip system provided in the embodiments of the present application may be a system on chip (SOC), and the source physical processor and the target physical processor may be respectively a processing unit.
  • the source physical processor or the target physical processor may be The physical core is located in the same processor; the source physical processor and the target physical processor can also be different processors located in the same chip system.
  • the control device, the intermediate device and the sending device can all be implemented by hardware circuits. Realized.
  • the control device and the sending device can be deployed in the multi-core processor, coupled with the source physical processor and the target physical processor.
  • the intermediate device can be deployed in the multi-core processor, or can be deployed in the multi-core processor coupled with the multi-core processor.
  • a system-on-chip may include a multi-core processor and peripheral devices/peripheral components coupled with the multi-core processor. Any physical processor in the system-on-chip can be used as either a source physical processor or a target physical processor device.
  • the source physical processor and the target physical processor are used in this application. It should be noted that the source physical processor and the target physical processor may be two physical cores in a multi-core processor, or may be located in different processors. of two physical cores. In an implementation manner, the source physical processor and the target physical processor may be the same physical entity. For example, in the scenario of a virtual partial interrupt, the source physical processor and the target physical processor may be the same physical processor.
  • the control device may include at least one register, wherein each register may be configured to receive one type of information for triggering a virtual interrupt.
  • each register may be configured to receive one type of information for triggering a virtual interrupt.
  • three registers are included, one register is used to receive information for triggering virtual local interrupts, one register is used to receive information used to trigger virtual software interrupts, and one register is used to receive information used to trigger virtual device interrupts.
  • only one register may be configured for the virtual interrupt, the information for triggering each type of virtual interrupt is different, and the type of the virtual interrupt can be identified by the information received by the register.
  • the sending device may be that each physical processor has one sending device, or multiple physical processors may share one sending device.
  • a register dedicated to processing virtual interrupts is set in the control device.
  • the host machine or virtual machine in the user state can directly write the information used to trigger the virtual interrupt into the register, and control the
  • the device can send the information for triggering the virtual interrupt to the intermediate device, the virtual interrupt is triggered by the intermediate device, and the intermediate device sends the virtual interrupt to the sending device, and the sending device sends the virtual interrupt to the target physical processor,
  • the source physical processor does not need to perform switching from the virtual machine to the host, or perform switching from the user mode of the host to the kernel mode of the host, thereby reducing the switching overhead generated by processing virtual interrupts and improving the performance of the chip system .
  • the intermediate device can be a virtual local interrupt generating device or a routing device. If the virtual interrupt is a virtual local interrupt, the intermediate device can be called a local interrupt generating device (such as a timer). If the virtual interrupt is a virtual local interrupt If it is a virtual software interrupt or a virtual device interrupt, the intermediate device may be called a routing device.
  • register 1 is used for receiving information for triggering virtual device interrupt
  • register 2 is used for receiving information for triggering virtual software interrupt
  • register 3 is used for receiving information for triggering virtual local interrupt.
  • the source physical processor is used to run the host or virtual machine, and both the host and the virtual machine can have permission level 1 and permission level 2, wherein permission level 1 can be user mode, permission level 2 Can be in kernel state.
  • permission level 1 can be user mode
  • permission level 2 Can be in kernel state.
  • the states corresponding to the first permission level and the second permission level may be different, which are not limited in this embodiment of the present application.
  • FIG. 4 of the present application four types of virtual interrupts are marked with four different lines.
  • the line marked with number 1 represents the process of processing virtual local interrupts
  • the line marked with number 2 represents the process of processing virtual software.
  • the interrupt process, the line marked with number 3 represents the process of processing virtual device interrupts, and the line marked with number 4 represents the process of processing the interrupt of the pass-through peripheral.
  • the involved register is register 3, and the intermediate device may be called a local interrupt generating device. Since the virtual local interrupt is an in-core interrupt, the target physical processor and the source physical processor are the same physical processor, and the transmitting device corresponds to the source physical processor.
  • the register is used to: receive the information written by the virtual machine for triggering the virtual local interrupt.
  • the local interrupt generating device is used for generating a virtual local interrupt according to the information for triggering the virtual local interrupt.
  • the sending device is used for: sending the virtual partial interrupt to the first virtual processor vCPU of the virtual machine, where the first vCPU runs on the source physical processor.
  • one physical processor can only run one vCPU of one virtual machine at a time, and sending the virtual local interrupt to the vCPU can complete the sending of the virtual local interrupt to the virtual machine operation.
  • the above-mentioned local interrupt generating device in FIG. 4 may be a timer, and the virtual local interrupt may be a clock interrupt. In the case of clock interruption, the implementation of this process can be understood by referring to FIG. 5 .
  • the virtual machine writes the interruption time into the control device (this process can be understood by referring to the third register in Figure 4), the control device will write the interruption time into the timer, and the timer will follow After starting, the timer sends a clock interrupt after the preset time expires. After receiving the clock interrupt, the sending device determines that the first vCPU of the virtual machine is running, and sends the clock interrupt to the first vCPU.
  • the process of processing the virtual local interrupt does not require the source physical processor to perform switching from the virtual machine to the host machine, thereby reducing the switching overhead generated by processing the virtual local interrupt and improving the chip system. performance.
  • the virtual software is interrupted.
  • the involved register is register 2, and the intermediate device may be called a routing device.
  • the source physical processor runs the first vCPU of the virtual machine
  • the target physical processor runs the second vCPU of the virtual machine.
  • the register is used to: receive the identifier of the second vCPU written by the first vCPU.
  • the control device is used for: reading the identifier of the second vCPU from the register, and acquiring the identifier of the virtual machine; and sending the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device.
  • the intermediate device is used to: determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from the first correspondence according to the identifier of the virtual machine and the identifier of the second vCPU; wherein the first correspondence is used for The correspondence between the target physical processor, the second vCPU running on the target processor, and the virtual machine is recorded; the virtual software interrupt is sent to the sending device corresponding to the target physical processor.
  • the sending means is used for: sending the virtual software interrupt to the second vCPU running on the target physical processor.
  • the control apparatus may acquire the identifier of the virtual machine from a register specially used for storing the identifier of the virtual machine running on the source physical processor. Because each virtual machine may have multiple vCPUs, and the identifiers of the vCPUs of different virtual machines may be the same, the control apparatus needs to send the identifier of the virtual machine and the identifier of the second vCPU to the intermediate apparatus.
  • the above-mentioned first correspondence can be stored on the intermediate device, and the first correspondence can be located in the in-position vCPU identification group, and each physical processor, each physical processor in the chip system is recorded in the in-position vCPU identification group.
  • the present application can target physical processors by searching for the in-position vCPU identification group.
  • the process of processing the virtual software interrupt does not require the source physical processor to perform switching from the virtual machine to the host, thereby reducing the switching overhead generated by processing the virtual software interrupt and improving the performance of the chip system.
  • the above-mentioned in-position vCPU identification group can be understood by referring to FIG. 6 .
  • the meaning represented in Figure 6 is: vCPU1 of VM1 runs on physical processor 1, vCPU2 of VM1 runs on physical processor 2, vCPU1 of VM2 runs on physical processor 3, and vCPU1 of VM2 runs on physical processor 4.
  • vCPU2. If the identification of VM1 and the identification of vCPU2 are received by the routing device from the control device, it can be determined that vCPU2 is running on physical processor 2 according to the in-position vCPU identification group shown in FIG. 6, and the virtual software can be interrupted to send To the sending device corresponding to the physical processor 2 , the sending device corresponding to the physical processor 2 sends the virtual software interrupt to the vCPU 2 running on the physical processor 2 .
  • the routing device can send the virtual software interrupt to the sending device of the source physical processor, and the sending device of the source physical processor The device sends the virtual software interrupt to the host, and after the second vCPU goes online, the host sends the virtual software interrupt to the second vCPU.
  • the in-position vCPU identification group in the above-mentioned routing device of the in-position vCPU identification group may be the source physical Managed by the host on the processor.
  • the process of processing virtual software interruption in the embodiment of the present application can be understood by referring to FIG. 7 .
  • the virtual machine runs on the source physical processor, and the first vCPU of the virtual machine runs on the source physical processor.
  • the second vCPU runs on another physical processor. If the first vCPU wants to send a virtual software interrupt to the second vCPU, the first vCPU of the virtual machine writes the identifier of the second vCPU to the register 2 of the control device.
  • the control device finds the identifier of the virtual machine, and then sends the identifier of the virtual machine and the identifier of the second vCPU to the routing device.
  • the routing device searches, for example, the in-position vCPU identification group shown in FIG.
  • the routing device sends the virtual software interrupt to the sending device corresponding to the target physical processor, and the sending device corresponding to the target physical processor sends the virtual software interrupt to the second vCPU, that is, to the virtual software interrupt running on the target physical processor virtual machine.
  • the processing process of the virtual software interrupt provided by the embodiment of the present application does not require the source physical processor to perform switching from the virtual machine to the host machine, thereby reducing the processing of virtual software interrupts.
  • the resulting switching overhead improves the performance of the chip system.
  • the virtual device is interrupted.
  • the involved register is register 1
  • the intermediate device is the routing device.
  • the host runs on the source physical processor, and the host is in user mode.
  • the register is used to: receive the target interrupt number written by the host and the identifier of the virtual machine, and the target interrupt number is the identifier of the interrupt triggered when the host simulates the hardware device.
  • the control device is used for: reading the target interrupt number and the identifier of the virtual machine from the register, and sending the identifier of the virtual machine and the target interrupt number to the intermediate device.
  • the intermediate device is used to: according to the identifier of the virtual machine and the target interrupt number, find the identifier of the first vCPU of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number in the second correspondence, and the second correspondence is used to record the virtual machine.
  • the sending means is used for: sending the virtual device interrupt to the first vCPU running on the target physical processor.
  • the virtual device interrupt is an interrupt triggered by the simulated hardware device of the host in the user mode.
  • the interrupt number of each type of hardware device is different.
  • the target interrupt number is the interrupt number of the disk. Because there can be multiple virtual machines managed by the host, the host needs to write the identifier of the virtual machine and the target interrupt number into the register.
  • the second correspondence may be located in the interrupt affinity table.
  • the interrupt affinity table can be configured by the virtual machine, so there is one interrupt affinity table for each virtual machine.
  • the interrupt affinity table of the virtual machine can be found according to the identifier of the virtual machine, and then the corresponding vCPU is determined from the interrupt affinity table of the virtual machine according to the target interrupt number, and the target interrupt number is 10. If in the interrupt affinity table, the interrupt number 10 corresponds to vCPU ID1, it can be determined that the vCPU ID corresponding to the target interrupt number is 1. After the routing device determines that the vCPU ID is 1, it can find the physical processor corresponding to the vCPU ID1 according to the in-position vCPU identification group. The meaning of the in-position vCPU identification group can be understood by referring to the description of the aforementioned virtual software interrupt. The third correspondence It can also be understood with reference to the foregoing first correspondence.
  • Table 1 is just an example, and is not limited to the ones listed in Table 1 in fact, and there may also be corresponding forms of other expressions, and there may be more in number.
  • An additional column may also be added to the table 1, and the additional column is used to store the identifier of the virtual machine in FIG. 4 .
  • the interrupt affinity table can be stored in the routing device or in the memory.
  • the routing device can provide each physical processor with an address register, and the address register can be a base address register.
  • the memory address of the interrupt affinity table and the identifier of the virtual machine may be stored.
  • the base address register 1 on the routing device corresponds to the physical processor 1
  • the base address register 2 corresponds to the physical processor 2
  • the base address register 3 corresponds to the physical processor 3
  • the base address register 4 corresponds to the physical processor device 4 corresponds.
  • the address in each base address register points to an interrupt affinity table, such as: base address register 1 points to interrupt affinity table 1, base address register 2 points to interrupt affinity table 2, and base address register 3 points to interrupt affinity table Affinity table 3, base address register 4 points to interrupt affinity table 4.
  • the addresses in the base address registers corresponding to the two physical processors may be the same, and the pointed interrupt affinity table may be the same table.
  • the virtual machine writes the target interrupt number into the register 1, and the control device reads the currently running virtual machine from the register specially used for storing the virtual machine running on the source physical processor Then, the control device sends the target interrupt number and the identifier of the virtual machine to the routing device.
  • the routing device determines the corresponding interrupt affinity table according to the identifier of the virtual machine, and then uses the target interrupt number to find the identifier of the corresponding vCPU from the interrupt affinity table. If the target interrupt number is 10, the corresponding vCPU can be determined.
  • the ID of the vCPU is 1.
  • the routing device After the routing device determines that the identifier of the vCPU is 1, it can find that the processor corresponding to the vCPU 1 is the physical processor 1 according to the in-position vCPU identifier group shown in FIG. 6 .
  • the routing device may send the virtual device interrupt to the sending device corresponding to the physical processor 1, and the sending device sends the virtual device interrupt to the first vCPU corresponding to the vCPU1.
  • the routing device can send the virtual software interrupt to the sending device of the source physical processor, and the sending device of the source physical processor The device sends the virtual software interrupt to the host, and after the first vCPU goes online, the host sends the virtual software interrupt to the first vCPU.
  • the processing process of the virtual device interrupt provided by the embodiment of the present application does not require the source physical processor to execute the process from the user state of the host machine to the kernel state of the host machine. Switching, thereby reducing the switching overhead generated by processing the virtual device interrupt, and improving the performance of the chip system.
  • the pass-through peripheral interrupt is an interrupt triggered by a hardware device that is directly connected to the virtual machine, such as a graphics card that is connected to the virtual machine.
  • the intermediate device can be called a routing device.
  • This type of interrupt handling process can be completed, which includes:
  • the intermediate device is used to: receive the pass-through peripheral interrupt triggered by the hardware device; according to the physical interrupt number of the pass-through peripheral interrupt, look up the corresponding virtual machine identifier and virtual interrupt number from the virtual interrupt table, and the physical interrupt is recorded in the virtual interrupt table.
  • the corresponding relationship between the ID of the virtual machine and the virtual interrupt number; the corresponding interrupt affinity table is determined according to the ID of the virtual machine, and the target virtual processor corresponding to the ID of the virtual machine and the virtual interrupt number is determined from the interrupt affinity table.
  • the corresponding relationship between the virtual interrupt number and the virtual processor is recorded in the interrupt affinity table; according to the identification of the target vCPU, the target physical processor corresponding to the identification of the target vCPU is determined from the in-position vCPU identification group; It is assumed that the interrupt is sent to the sending device corresponding to the target physical processor.
  • the sending device is used for: sending the pass-through peripheral interrupt to the virtual machine running on the target physical processor.
  • the virtual interrupt table, the interrupt affinity table, and the in-position vCPU identification group are sequentially used, and the interrupt affinity table and the in-position vCPU identification group may refer to the previous description.
  • the following describes the virtual interrupt table.
  • the virtual interrupt table maintains the corresponding relationship between the physical interrupt number and the ID of the virtual machine and the virtual interrupt number. Entering a physical interrupt number can output the ID of the virtual machine and the virtual interrupt number.
  • the virtual interrupt table can be understood by referring to Table 2.
  • inputting a physical interrupt number 100 can output the ID 1 of the virtual machine and the virtual interrupt number 10.
  • the virtual interrupt table in this application can be stored in the routing device or in the memory, and the location of the virtual interrupt table in the memory is indicated by another register similar to the base address register.
  • the routing device receives the physical interrupt number sent by the pass-through peripheral, and searches the virtual interrupt table for the identifier and virtual interrupt number of the corresponding virtual machine through the physical interrupt number, For example, inputting a physical interrupt number 100 can output the ID 1 of the virtual machine and the virtual interrupt number 10. Then, look up the interrupt affinity table of Table 1 according to the identifier 1 of the virtual machine and the virtual interrupt number 10, and find the identifier of the corresponding vCPU. For example, the identifier of the vCPU is found to be 1. Further, according to the vCPU1, the corresponding physical processor is searched from the in-position vCPU identification group shown in FIG. 6, for example, if the physical processor 1 is found, the routing device can send the pass-through peripheral interrupt to the corresponding physical processor 1. A sending device, and the sending device sends the pass-through peripheral interrupt to the first vCPU corresponding to the vCPU1.
  • the routing device can send the virtual software interrupt to the sending device of the source physical processor, and the sending device of the source physical processor The device sends the virtual software interrupt to the host, and after the first vCPU goes online, the host sends the virtual software interrupt to the first vCPU.
  • the sending device sends them to the corresponding target physical processor.
  • the above several types of virtual interrupts are written into the pending register, the pending register is used to receive the command to be executed by the target physical processor next, and the virtual interrupt is written into the pending register, then the The target physical processor will then execute the virtual interrupt, so that the currently executing process can be interrupted. If the target vCPU is executing, interrupt the target vCPU and send the interrupt to the target vCPU. If the host is executing, interrupt the host and send the interrupt directly to the running host.
  • the host After the corresponding target vCPU goes online, the host will pass the interrupt to the target vCPU.
  • the target vCPU can be the one described above.
  • FIG. 10 is a schematic structural diagram of the chip system on RISC-V .
  • the system-on-a-chip includes control and transmission means and interrupt routers for interacting with the physical processor.
  • the interrupt router includes the routing device described in the above embodiments.
  • RISC-V-CPU represents the central processing unit in the RISC-V architecture
  • HU-mode represents the user mode of the host
  • HS-mode represents the sink
  • VU-mode represents the user mode of the virtual machine
  • VS-mode represents the kernel mode of the virtual machine.
  • the supervisor generates the information of the inter-processor interrupt logic (supervisor generate inter-processor interrupt, sgenipi) for triggering the virtual software interrupt, and the supervisor time compare logic (stimecmp) is used to trigger the register of the information of the virtual local interrupt.
  • stimecmp supervisor time compare logic
  • the information used to trigger the virtual software interrupt can be sent to the virtual supervisor of the control device through sgenipi to generate an inter-processor interrupt (virtual supervisor generate inter-processor).
  • interrupt, vsgenipi) register, the vsgenipi register is the register described in the foregoing embodiment for receiving information for triggering a virtual software interrupt, such as register 2 .
  • the information for triggering the virtual local interrupt can be sent to the virtual supervisor time compare (virtual supervisor time compare, vstimecmp) register of the control device through stimecmp, and the vstimecmp register is described in the above-mentioned embodiment for receiving the virtual supervisor for triggering the virtual interrupt.
  • Registers for local interrupt information such as: register 3.
  • the user-generate virtual supervisor external interrupt (user generate virtual supervisor external interrupt, ugenvsei) register is a register for receiving information for triggering a virtual device interrupt, such as register 1 described in the above embodiment.
  • the virtual device simulation logic of the host user mode can directly send the information used to trigger the virtual device interrupt to the ugenvsei register.
  • the interrupt router implementation includes registers of virtual heart shared interrupt mapping (vhsimap), a set of registers of virtual interrupt affinity table (virtual table base, vtblbase) (1-n), and a set of interrupt control interface mapping (interface). mapping, ifmap) registers.
  • the vhsimap(1-n) register is used to point to the virtual interrupt table stored in memory.
  • Each vtblbase register in a set of vtblbase(1-n) registers corresponds to a physical processor in the RISC-V system, and is used to point to the virtual interrupt affinity defined by the virtual machine to which the vCPU running on the physical processor belongs surface.
  • the virtual machine uses stimecmp to write the interrupt time into the vstimecmp register, and the control device writes the time when the next virtual clock interrupt is triggered into the clock device dedicated to the virtual machine.
  • the clock device dedicated to the virtual machine triggers the virtual clock interrupt.
  • the virtual clock interrupt is sent to the sending device.
  • one vCPU of the virtual machine (which may be referred to as the source vCPU in this scenario) runs on CPU1, which may be the source physical processor in the foregoing embodiment, and the source vCPU of the virtual machine uses the identifier of the target vCPU Write sgenipi, and write the identifier of the target vCPU into the vsgenipi register in the control device through the sgenipi, the control device obtains the identifier of the virtual machine, and combines the identifier of the virtual machine and the identifier of the target vCPU (vhartid: RISC-V represents vCPU ID) to the interrupt router, the interrupt router searches ifmapx, and the serial number x of the ifmapx register containing the VMID and vhartid is the ID of the corresponding physical processor (mhartid: the ID of the physical processor in RISC-V).
  • the identification of the physical processor is CPU2 in FIG. 12
  • the CPU2 can also be understood by referring to the target physical processor in the foregoing embodiment.
  • the host in user mode writes the ID of the virtual machine and the virtual interrupt number to ugenvsei.
  • the control device sends the identification of the virtual machine and the virtual interrupt number to the interrupt router.
  • the interrupt router looks up the vtblbasex registers and finds one of the vtblbasex registers with the identity of the virtual machine. Look up the interrupt affinity table held in the memory pointed to by this register. Obtain the vhartid of the vCPU defined by the virtual machine that handles the interrupt from the interrupt affinity table.
  • the interrupt router searches ifmapx and finds the serial number x of the physical processor corresponding to the register with the VMID and vhartid, where x is the mhartid of the target physical processor.
  • the host computer writes the ID of the virtual machine and the virtual interrupt number to ugenvsei.
  • the control device sends the identification of the virtual machine and the virtual interrupt number to the interrupt router.
  • Interrupt routers do not implement vtblbasex and by default send virtual interrupts to any vCPU with that virtual machine.
  • the interrupt router searches ifmapx, and finds the serial number x of the physical processor corresponding to the register with the identifier of the virtual machine, where x is the mhartid of the target physical processor.
  • the host performs processing on its behalf, that is, after the virtual machine goes online, the host sends the virtual device interrupt to the virtual machine.
  • the hardware device that communicates directly with the virtual machine triggers the pass-through peripheral interrupt
  • the interrupt router searches the virtual interrupt table pointed to by vhlimap, finds out the ID of the virtual machine to which the interrupt is passed through, and the virtual machine after the pass-through. This virtual interrupt number is considered within.
  • the interrupt router looks up the vtblbasex registers, finds one of the vtblbasex registers with that VM ID, and looks up the virtual interrupt affinity table held by the memory pointed to by that register. Obtain the vhartid of the vCPU defined by the virtual machine that handles the interrupt from the interrupt affinity table.
  • the interrupt router searches ifmapx and finds the serial number x of the physical processor corresponding to the register with the VMID and vhartid, where x is the mhartid of the target physical processor.
  • the interrupt router sends a pass-through peripheral interrupt to the sending device of the physical processor of mhartid.
  • the host performs processing on its behalf, that is, after the virtual machine goes online, the host sends the pass-through peripheral interrupt to the virtual machine.
  • the virtual local interrupt is realized from the local interrupt device to the vCPU and the whole process is not trapped to the host machine.
  • the virtual software interrupt is realized through the control device, the routing device and the sending device without software cooperation between the virtual machine and the host machine, and the whole process from the sending end vCPU to the receiving end vCPU does not fall out to the host machine.
  • the control device, the routing device, and the sending device realize that the virtual device interrupts from the host simulation logic to the receiving end host vCPU without switching context/trapping to the host. Therefore, the solution provided by the embodiment of the present application can accelerate the performance of virtual machine I/O, clock, scheduling, etc.
  • the simulation data shows that the Redis is improved by 80% when the virtual local interrupt is processed by this solution. 6% improvement in handling virtual software interrupts.
  • the process of processing virtual interrupts implemented by means of hardware circuits has been described above.
  • the process of processing virtual interrupts provided by the embodiments of the present application may also be implemented by means of software, and the process implemented by software may also be combined in the above-mentioned system of chips , the chip system includes a source physical processor, a control device, an intermediate device and a transmission device, and the control device includes a register; the register is used to receive information for triggering a virtual interrupt, and the functions of the control device, the intermediate device and the transmission device can be passed through It is implemented in the form of software codes, which will be introduced below in conjunction with the accompanying drawings.
  • an embodiment of the method for processing a virtual interrupt provided by an embodiment of the present application includes:
  • the control device reads the information for triggering the virtual interrupt from the register.
  • the information for triggering the virtual interrupt comes from the host or virtual machine running in the source physical processor.
  • the control device sends the information for triggering the virtual interrupt to the intermediate device, and correspondingly, the intermediate device receives the information for triggering the virtual interrupt.
  • the intermediate device triggers the virtual interrupt according to the information for triggering the virtual interrupt.
  • the intermediate device sends the virtual interrupt to the sending device, and correspondingly, the sending device receives the virtual interrupt.
  • the sending device sends the virtual interrupt to the target physical processor.
  • a register dedicated to processing virtual interrupts is set in the control device, so that the host machine or virtual machine in the user state can directly write the information for triggering the virtual interrupt into the register, and the control device.
  • the information for triggering the virtual interrupt can be sent to the intermediate device, the virtual interrupt is triggered by the intermediate device, and the intermediate device sends the virtual interrupt to the sending device, and the sending device sends the virtual interrupt to the target physical processor.
  • the host machine or the virtual machine can directly access the register, and write the information used to trigger the virtual interrupt into the register, so as to send the virtual interrupt out; therefore, compared with the prior art, the solution provided by the present application
  • the source physical processor does not need to perform the switch from the virtual machine to the host, or the source physical processor performs the switch from the user mode of the host to the kernel mode of the host, thereby reducing the switching overhead generated by processing virtual interrupts and improving the performance. system-on-chip performance.
  • the target physical processor and the source physical processor are the same physical processor; the register receives the information written by the virtual machine for triggering the virtual local interrupt.
  • the intermediate device generates a virtual local interrupt according to the information for triggering the virtual local interrupt.
  • the sending device sends the virtual local interrupt to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.
  • the information for triggering the virtual interrupt read from the register in the above step 101 includes the identifier of the second vCPU written into the register by the first vCPU of the virtual machine, and the second vCPU is running on the target physical device.
  • the vCPU of the virtual machine on the processor.
  • step 102 the control device obtains the identifier of the virtual machine; then step 103 specifically includes sending the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device.
  • Step 103 specifically includes the intermediate device determining the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from the first correspondence according to the identifier of the virtual machine and the identifier of the second vCPU; wherein, the first correspondence uses The corresponding relationship between the target physical processor, the second vCPU running on the target processor and the virtual machine is recorded; the virtual software interrupt is triggered.
  • Step 104 includes: the intermediary device sends the virtual software interrupt to the sending device corresponding to the target physical processor.
  • Step 105 includes: the sending means sends the virtual software interrupt to the second vCPU running on the target physical processor.
  • the information for triggering the virtual interrupt read from the register in the above step 101 includes the target interrupt number written into the register by the host machine and the identifier of the virtual machine, and the target interrupt number is the simulated hardware device of the host machine. The ID of the interrupt that was triggered.
  • Step 102 includes: the control device sends the identifier of the virtual machine and the target interrupt number to the intermediate device.
  • Step 103 includes: according to the identifier of the virtual machine and the target interrupt number, the intermediate device searches for the identifier of the first vCPU of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number in the second correspondence, and the second correspondence is used for recording.
  • the processor wherein the third correspondence is used to record the correspondence between the target physical processor, the first vCPU running on the target processor, and the virtual machine; and generate a virtual device interrupt.
  • Step 104 includes: the intermediary device sends the virtual device interrupt to the sending device corresponding to the target physical processor.
  • Step 105 includes: the sending means sends the virtual device interrupt to the first vCPU running on the target physical processor.
  • control device the intermediate device and the sending device implemented by software can be understood by referring to the corresponding contents in the embodiments corresponding to FIG. 2 to FIG. 15 , which will not be repeated here.
  • an embodiment of the control device 20 provided by the embodiment of the present application includes: the control device 20 is applied to a chip system, and the chip system further includes a source physical processor, an intermediate device, a sending device, and a target physical processor
  • the source physical processor is used to run the host machine or the virtual machine
  • the control device includes a register; the register is used to receive information for triggering a virtual interrupt, and the information for triggering a virtual interrupt comes from the host machine or the virtual machine, and the control device 20 includes:
  • the reading unit 201 is configured to read the information for triggering the virtual interrupt from the register.
  • the sending unit 202 is configured to send the information for triggering the virtual interrupt read by the reading unit 201 to the intermediate device, and the information used for triggering the virtual interrupt is used for the intermediate device to trigger the virtual interrupt, and the virtual interrupt is sent by the sending device to the target physical device. processor.
  • the virtual interrupt is a virtual local interrupt
  • the target physical processor and the source physical processor are the same physical processor
  • the register is used to receive information written by the virtual machine for triggering the virtual local interrupt; for triggering the virtual local interrupt
  • the information is used to make the intermediate device trigger a virtual local interrupt, and the virtual local interrupt is sent by the sending device to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.
  • the virtual interrupt is a virtual software interrupt
  • the information for triggering the virtual interrupt includes the identifier of the second vCPU written into the register by the first VCPU of the virtual machine, and the second vCPU is the ID of the virtual machine running on the target physical processor.
  • the control device 20 further includes a processing unit 203 .
  • the processing unit 203 is configured to acquire the identifier of the virtual machine.
  • the sending unit 202 is used for sending the identifier of the virtual machine to the intermediate device, and the identifier of the virtual machine and the identifier of the second vCPU are used by the intermediate device to determine the target physical processor and trigger a virtual software interrupt, and the virtual software interrupt is sent to the target by the sending device The second vCPU of the physical processor.
  • the virtual interrupt is a virtual device interrupt
  • the information for triggering the virtual interrupt includes the target interrupt number that the host machine writes into the register and the identity of the virtual machine, and the target interrupt number is the identity of the interrupt triggered when the host machine simulates a hardware device.
  • the identifier of the virtual machine and the target interrupt number are used by the intermediate device to determine the target physical processor and trigger the virtual device interrupt, and the virtual device interrupt is sent by the sending device to the first vCPU of the target physical processor.
  • an embodiment of the intermediate device 30 provided by the embodiment of the present application includes: the intermediate device 30 is applied in a chip system, and the chip system further includes a source physical processor, a control device, a sending device, and a target physical processing device
  • the source physical processor is used to run the host machine or the virtual machine
  • the control device includes a register; the register is used to receive information for triggering a virtual interrupt, and the information for triggering a virtual interrupt comes from the host machine or the virtual machine
  • the intermediate device 30 includes:
  • the receiving unit 301 is configured to receive the information for triggering the virtual interrupt from the control device.
  • the processing unit 302 is configured to trigger the virtual interrupt according to the information for triggering the virtual interrupt.
  • the sending unit 303 is configured to send the virtual interrupt to the sending device, and the virtual interrupt is sent by the sending device to the target physical processor.
  • the virtual interrupt is a virtual local interrupt
  • the target physical processor and the source physical processor are the same physical processor
  • the register is used to receive information written by the virtual machine for triggering the virtual local interrupt; for triggering the virtual local interrupt
  • the information is used to trigger a virtual local interrupt
  • the virtual local interrupt is sent by the sending device to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.
  • the virtual interrupt is a virtual software interrupt
  • the information for triggering the virtual interrupt includes the identifier of the second vCPU written into the register by the first vCPU of the virtual machine, and the second vCPU is the ID of the virtual machine running on the target physical processor. vCPUs.
  • the processing unit 302 is configured to determine, according to the identifier of the virtual machine and the identifier of the second vCPU, the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from the first correspondence; The corresponding relationship between the target physical processor, the second vCPU running on the target processor and the virtual machine is recorded; a virtual software interrupt is triggered, and the virtual software interrupt is sent by the sending device to the second vCPU of the target physical processor.
  • the virtual interrupt is a virtual device interrupt
  • the information for triggering the virtual interrupt includes the target interrupt number that the host machine writes into the register and the identity of the virtual machine, and the target interrupt number is the identity of the interrupt triggered when the host machine simulates a hardware device.
  • the processing unit 302 is used to find, according to the identifier of the virtual machine and the target interrupt number, the identifier of the first vCPU of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number in the second correspondence, and the second correspondence is used to record The correspondence between the virtual machine, the target interrupt number and the first vCPU; according to the identifier of the virtual machine and the identifier of the first vCPU, determine the target physical object corresponding to the identifier of the virtual machine and the identifier of the first vCPU from the third correspondence processor; wherein, the third correspondence is used to record the correspondence between the target physical processor, the first vCPU running on the target processor, and the virtual machine; triggering a virtual device interrupt, the virtual device interrupt is sent by the sending device to the target physical processor The processor's first vCPU.
  • the processing unit 302 is further configured to find the address register according to the identifier of the virtual machine, obtain the second correspondence from the memory according to the address in the address register, and the address register is used to store the second correspondence in the memory. address and the identity of the virtual machine.
  • an embodiment of the sending device 40 provided by the embodiment of the present application includes: the sending device 40 is applied in a chip system, and the chip system further includes a source physical processor, an intermediate device, a control device, and a target physical processor
  • the source physical processor is used to run the host machine or the virtual machine
  • the control device includes a register; the register is used to receive the information used to trigger the virtual interrupt, and the information used to trigger the virtual interrupt comes from the host machine or the virtual machine
  • the sending device 40 include:
  • the receiving unit 401 is configured to receive a virtual interrupt from an intermediate device.
  • the sending unit 402 is configured to send the virtual interrupt to the target physical processor.
  • the virtual interrupt is a virtual local interrupt
  • the target physical processor and the source physical processor are the same physical processor
  • the sending unit 402 is configured to send the virtual local interrupt to the first virtual processor vCPU of the virtual machine, the first virtual processor vCPU.
  • vCPUs run on the source physical processors.
  • the virtual interrupt is a virtual software interrupt
  • the information for triggering the virtual interrupt includes the identifier of the second vCPU written into the register by the first vCPU of the virtual machine, and the second vCPU is the ID of the virtual machine running on the target physical processor. vCPUs.
  • the sending unit 402 is configured to send the virtual software interrupt to the second vCPU running on the target physical processor.
  • the virtual interrupt is a virtual device interrupt
  • the information for triggering the virtual interrupt includes the target interrupt number that the host machine writes into the register and the identity of the virtual machine, and the target interrupt number is the identity of the interrupt triggered when the host machine simulates a hardware device.
  • the sending unit 402 is configured to send the virtual device interrupt to the first vCPU running on the target physical processor.
  • the sending unit 402 is configured to write the virtual interrupt into a to-be-processed register of the target physical processor, and the to-be-processed register is used to receive a command of the process executed by the target physical processor.
  • the computer device 50 may include the control device, the intermediate device or the sending device described in FIG. 17 to FIG. 19 .
  • the computer device 50 includes a processor 501 , a communication interface 502 , a memory 503 and a bus 504 .
  • the processor 501 , the communication interface 502 and the memory 503 are connected to each other through a bus 504 .
  • the processor 501 is configured to control and manage the actions of the computer device 50, for example, the processor 501 is configured to execute step 101 or 103 in the method embodiment of FIG. 16 .
  • the memory 503 is used for storing program codes and data of the computer device 50 .
  • the communication interface 502 may be used to perform steps 102, 104 or 105 in the method embodiment of FIG. 16 .
  • the processor 501 may be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array, or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It may implement or execute the various exemplary logical blocks, modules and circuits described in connection with this disclosure.
  • the processor 501 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, and the like.
  • the bus 504 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (Extended Industry Standard Architecture, EISA) bus or the like.
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture
  • a computer-readable storage medium is also provided, where computer-executable instructions are stored in the computer-readable storage medium.
  • the processor of the device executes the computer-executable instructions
  • the device executes the above-mentioned FIG. 16 .
  • a computer program product includes computer-executable instructions, and the computer-executable instructions are stored in a computer-readable storage medium; when a processor of a device executes the computer-executable instructions , the device executes the method for processing virtual interrupts executed by the control device, the intermediate device, or the sending device in FIG. 16 .
  • Another embodiment of the present application further provides a chip system, where the chip system includes a source physical processor, a control device, a sending device, and a target physical processor.
  • the control device is the control device described in the foregoing embodiments of FIG. 2 to FIG. 15
  • the transmission device is the transmission device described in the foregoing embodiments of FIG. 2 to FIG. 15 .
  • system-on-a-chip may further include an intermediate device as described in the foregoing embodiments of FIG. 2 to FIG. 15 .
  • the chip system is a processor
  • the source physical processor and the target physical processor are physical cores in the processor
  • the control device is located in the processor and is coupled to the source physical processor.
  • the sending device is a component located in the processor and coupled to the target physical processor.
  • the physical core may include both a control device and a transmission device.
  • Units described as separate components may or may not be physically separated, and components shown as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the embodiments of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the functions, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer-readable storage medium.
  • the technical solutions of the embodiments of the present application can be embodied in the form of software products in essence, or the parts that make contributions to the prior art or the parts of the technical solutions, and the computer software products are stored in a storage medium , including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in the embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program codes .

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Abstract

一种芯片系统，应用于虚拟化技术领域。该芯片系统包括源物理处理器、控制装置、中间装置、发送装置以及目标物理处理器，源物理处理器上运行有宿主机或虚拟机，控制装置中的寄存器接收宿主机或虚拟机写入的用于触发虚拟中断的信息，控制装置将寄存器中的用于触发虚拟中断的信息发送给中间装置；中间装置根据用于触发虚拟中断的信息触发虚拟中断，并将虚拟中断发送给发送装置；发送装置将虚拟中断发送给目标物理处理器。该方案用于减少因虚拟中断产生的从虚拟机到宿主机，或者从宿主机的用户态切换到宿主机的内核态的切换开销。

Description

一种芯片系统、处理虚拟中断的方法及相应装置
本申请要求于2020年10月15日提交中国专利局、申请号为202011108332.3、发明名称为“一种芯片系统、处理虚拟中断的方法及相应装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及虚拟化技术领域，具体涉及一种芯片系统、处理虚拟中断的方法及相应装置。
背景技术
虚拟中断是虚拟化技术的必要组成部分，虚拟机(virtual machine，VM)运行于计算机设备中，该计算机设备中的磁盘、输入/输出(input/output，I/O)设备等硬件设备对虚拟机的通知，以及虚拟机内部的各种同步以及协调工作都依赖于虚拟中断。虚拟中断是一种事件，这类事件可以有各种来源，来源不同，针对该事件的处理过程也会有不同，但每种来源的这类事件都会以虚拟机运行时收到中断的形式通知到虚拟机。
无论是哪种来源的虚拟中断，在虚拟中断最终到达虚拟机之前，宿主机需要利用自身的各种机制完成将虚拟中断从源头发送到目的虚拟机的工作。在发送该虚拟中断过程中，需要处理器的控制流从正在执行的虚拟机切换到宿主机，或者从宿主机的用户态切换到宿主机的内核态，产生了较大的切换开销。
发明内容
本申请实施例提供一种芯片系统、处理虚拟中断的方法及相应装置，用于减少因虚拟中断产生的从虚拟机到宿主机，或者从宿主机的用户态切换到宿主机的内核态的切换开销。本申请实施例还提供了相应的计算机设备、计算机存储介质以及计算机程序产品等。
本申请第一方面提供一种芯片系统，包括：源物理处理器、控制装置、中间装置、发送装置以及目标物理处理器，源物理处理器用于运行宿主机或虚拟机，控制装置包括寄存器，寄存器用于接收用于触发虚拟中断的信息，用于触发虚拟中断的信息可以来自于宿主机或虚拟机；控制装置用于：将寄存器中的用于触发虚拟中断的信息发送给中间装置；中间装置用于：根据用于触发虚拟中断的信息触发虚拟中断，并将虚拟中断发送给发送装置；发送装置用于：接收来自于中间装置的虚拟中断，并将虚拟中断发送给目标物理处理器。
本申请中，该芯片系统可以是片上系统(system on chip，SOC)，源物理处理器和目标物理处理器可以分别是一个处理单元(processing unit)，例如一个物理核。控制装置、中间装置和发送装置都可以是通过硬件电路来实现的，也可以是通过软件实现的。源物理处理器和目标物理处理器可以为多核处理器中的物理核，多核处理器包括多个物理核，物理核为集成在处理器中的内核，物理核是一种处理单元，比如双核处理器可以理解为具有两个物理核的处理器。控制装置和发送装置可以部署在该多核处理器中，与源物理处理器和目标物理处理器耦合。中间装置可以部署在该多核处理器中，也可以部署在与多核处理器耦合的外围设备/外围组件上。片上系统可以包括多核处理器和与多核处理器耦合的外围设备/外围组件。芯片系统中的任一个物理处理器既可以作为源物理处理器，也可以作为目标物理处理器。
本申请中，虚拟中断(virtual interrupt)指的是计算机设备中的硬件设备、宿主机、该虚拟机的时钟或虚拟机的虚拟处理器(virtual processer)等发送给虚拟机(virtual machine，VM)的中断，产生该虚拟中断的硬件设备可以是计算机设备中的磁盘、网卡、声卡、鼠标、硬盘等。物理中断指的是硬件设备发送给物理处理器的中断。物理中断是由宿主机处理，而虚拟中断是由虚拟机处理。
需要注意的是，本申请各个实施例提到的虚拟处理器的一种具体实现方式可以为虚拟中央处理器(virtual central processing unit，vCPU)。后续提到的“vCPU”也可以替换为“虚拟处理器”来理解。
本申请中，虚拟中断可以包括虚拟局部中断(virtual local interrupt)，虚拟软件中断(virtual software interrupt)，虚拟设备中断(virtual device interrupt)和直通外设中断(direct peripheral interrupt)。其中，虚拟局部中断指由虚拟机模拟的虚拟局部设备发出的中断或虚拟机的某个vCPU的局部设备发出的中断，例如：虚拟机的某个vCPU的计时器发出的时钟中断。虚拟软件中断指由软件触发的，通常指虚拟机的一个vCPU发给该虚拟机的另一个vCPU的中断，一个虚拟机可以有多个vCPU，这些vCPU在一个时刻可以运行在不同的物理处理器上来执行虚拟机的不同任务，当不同的vCPU之间所执行的任务有依赖关系或需要调度时，就会发生虚拟软件中断。虚拟设备中断指由宿主机模拟硬件设备触发的中断，例如宿主机模拟虚拟机磁盘控制器或模拟其他硬件设备产生的中断。
本申请中，控制装置中可以包括至少一个寄存器，其中，可以是每个寄存器用于接收一种类型的用于触发虚拟中断的信息。如：包括三个寄存器，一个寄存器用于接收用于触发虚拟局部中断的信息，一个寄存器用于接收用于触发虚拟软件中断的信息，一个寄存器用于接收用于触发虚拟设备中断的信息。当然，该控制装置中，针对虚拟中断也可以只配置一个寄存器，用于触发每种类型的虚拟中断的信息不同，可以通过寄存器接收的信息来识别虚拟中断的类型。
中间装置可以有一个，也可以有多个。发送装置可以是每个物理处理器有一个发送装置，也可以是多个物理处理器共用一个发送装置。
由上述第一方面可知，该第一方面在控制装置中设置专用于处理虚拟中断的寄存器，这样，处于用户态或内核态的宿主机或虚拟机可以直接将用于触发虚拟中断的信息写入该寄存器中，控制装置可以将该用于触发虚拟中断的信息发送给中间装置，由中间装置触发虚拟中断，并且，中间装置将该虚拟中断发送给发送装置，由发送装置将该虚拟中断发送给目标物理处理器。本申请提供的方案中，宿主机或虚拟机均可以直接访问寄存器，将用于触发虚拟中断的信息写入寄存器，从而将虚拟中断发送出去；因此相比于现有技术，本申请提供的方案不需要源物理处理器执行从虚拟机到宿主机的切换，也不需要源物理处理器执行从宿主机的用户态到宿主机的内核态的切换，从而减少了处理虚拟中断产生的切换开销，提高了芯片系统的性能。
在第一方面的一种可能的实现方式中，虚拟中断为虚拟局部中断，目标物理处理器和源物理处理器为同一物理处理器；寄存器用于：接收虚拟机写入的用于触发虚拟局部中断的信息；发送装置用于：将虚拟局部中断发送给虚拟机的第一虚拟处理器vCPU，第一vCPU 运行在源物理处理器上。
该种可能的实现方式中，因为虚拟局部中断是核内中断，所以，目标物理处理器和源物理处理器为同一物理处理器。中间装置可以为计时器，该虚拟局部中断可以为时钟中断。一个物理处理器一个时刻只会运行一个虚拟机的一个vCPU，将虚拟局部中断发送给该vCPU，即可完成将该虚拟局部中断发送给虚拟机的操作。由该可能的实现方式可知，处理该虚拟局部中断的过程不需要源物理处理器执行从虚拟机到宿主机的切换，从而减少了处理虚拟局部中断产生的切换开销，提高了芯片系统的性能。
在第一方面的一种可能的实现方式中，虚拟中断为虚拟软件中断，用于触发虚拟中断的信息包括虚拟机的第一vCPU写入寄存器的第二vCPU的标识，第二vCPU为运行于目标物理处理器上的虚拟机的vCPU；控制装置用于：从寄存器读取第二vCPU的标识，并获取虚拟机的标识；以及，将虚拟机的标识和第二vCPU的标识发送给中间装置；中间装置用于：根据虚拟机的标识和第二vCPU的标识，从第一对应关系中确定与虚拟机的标识和第二vCPU的标识对应的目标物理处理器；其中，第一对应关系用于记录目标物理处理器、目标处理器上运行的第二vCPU以及虚拟机之间的对应关系；将虚拟软件中断发送给与目标物理处理器对应的发送装置；发送装置用于：将虚拟软件中断发送给运行于目标物理处理器的第二vCPU。
该种可能的实现方式中，虚拟软件中断是虚拟机的第一vCPU发给该虚拟机的第二vCPU的中断。因此，虚拟机的第一vCPU要触发该虚拟软件中断时，需要向寄存器中写入第二vCPU的标识。一个虚拟机可以有多个vCPU，归属于同一个虚拟机的vCPU可以采用分时复用的方式在一个物理处理器上运行，如：在物理处理器1上先运行虚拟机1的vCPU1，物理处理器1结束该vCPU1的运行后，可以再运行该虚拟机1的vCPU2，同属于一个虚拟机的多个vCPU也可以运行在不同的物理处理器上，一个时刻可以在不同的物理处理器上运行不同的vCPU，如：在物理处理器1上运行虚拟机1的vCPU1，在物理处理器2上运行虚拟机1的vCPU2。该虚拟软件中断的场景中，第一vCPU运行于源物理处理器上，第二vCPU运行于目标物理处理器上。控制装置可以从专门用于存储源物理处理器上所运行的虚拟机的标识的寄存器中获取该虚拟机的标识。因为，每个虚拟机都可以有多个vCPU，不同虚拟机的vCPU的标识可能是相同的，所以，控制装置需要向中间装置发送该虚拟机的标识和第二vCPU的标识。中间装置上可以存储上述第一对应关系，该第一对应关系可以位于在位vCPU标识组中，该在位vCPU标识组中记录有该芯片系统中的每个物理处理器、每个物理处理器运行的vCPU，以及在运行的vCPU所属的虚拟机之间的对应关系，本申请可以通过查找在位vCPU标识组的方式来目标物理处理器。由该可能的实现方式可知，处理该虚拟软件中断的过程不需要源物理处理器执行从虚拟机到宿主机的切换，从而减少了处理虚拟软件中断产生的切换开销，提高了芯片系统的性能。
在第一方面的一种可能的实现方式中，虚拟中断为虚拟设备中断，用于触发虚拟中断的信息包括宿主机写入寄存器的目标中断号和虚拟机的标识，目标中断号为宿主机模拟硬件设备时所触发的中断的标识；控制装置用于：从寄存器读取目标中断号和虚拟机的标识，并将虚拟机的标识和目标中断号发送给中间装置；中间装置用于：根据虚拟机的标识和目标中断号，在第二对应关系中查找与虚拟机的标识和目标中断号对应的虚拟机的第一vCPU 的标识，第二对应关系用于记录虚拟机、目标中断号和第一vCPU之间的对应关系；根据虚拟机的标识和第一vCPU的标识，从第三对应关系中确定与虚拟机的标识和第一vCPU的标识对应的目标物理处理器；其中，第三对应关系用于记录目标物理处理器、目标处理器上运行的第一vCPU以及虚拟机之间的对应关系；将虚拟设备中断发送给与目标物理处理器对应的发送装置；发送装置用于：将虚拟设备中断发送给运行于目标物理处理器的第一vCPU。
该种可能的实现方式中，虚拟设备中断是处于用户态的宿主机模拟硬件设备触发的中断。硬件设备的类型可以有多种，每种类型的硬件设备的中断号不相同，若宿主机模拟的是磁盘，则该目标中断号为磁盘的中断号。因为宿主机所管理的虚拟机可以有多个，所以，宿主机需要向寄存器中写入该虚拟机的标识和目标中断号。第二对应关系可以位于中断亲和性表中。该中断亲和性表可以是虚拟机配置的，所以，针对每个虚拟机都有一个中断亲和性表。这样，就可以根据该虚拟机的标识找到该虚拟机的中断亲和性表，然后，在根据该目标中断号从该虚拟机的中断亲和性表中确定出对应的vCPU，目标中断号是10，若中断亲和性表中，中断号10与vCPU ID1对应，则可以确定目标中断号对应的vCPU ID为1。路由装置确定vCPU ID为1后，可以根据在位vCPU标识组查找到该vCPU ID1对应的物理处理器，在位vCPU标识组的含义可以参阅前述虚拟软件中断部分的描述进行理解，第三对应关系也可以参考前述第一对应关系进行理解。由该可能的实现方式可知，处理该虚拟设备中断的过程不需要源物理处理器执行从宿主机的用户态到宿主机的内核态的切换，从而减少了处理虚拟设备中断产生的切换开销，提高了芯片系统的性能。
在第一方面的一种可能的实现方式中，中间装置包括地址寄存器，地址寄存器用于存储第二对应关系在内存中的地址以及虚拟机的标识；中间装置还用于：根据虚拟机的标识查找到地址寄存器，根据地址寄存器中的地址从内存中获取第二对应关系。
该种可能的实现方式中，上述中断亲和性表可以存储在中间装置中，也可以存储在内存中，该中间装置中可以为每个物理处理器提供一个地址寄存器，该地址寄存器可以是基地址寄存器，该基地址寄存器中可以存储该中断亲和性表在内存的地址以及虚拟机的标识。这样可以避免占用太多中间装置的存储空间。
在第一方面的一种可能的实现方式中，发送装置用于：将虚拟中断写入目标物理处理器的待处理寄存器中，待处理寄存器用于接收目标物理处理器所执行流程的命令。
该种可能的实现方式中，该待处理寄存器用于接收目标物理处理器接下来所要执行的命令，将该虚拟中断写入到该待处理寄存器中，那么该目标物理处理器接下来就会执行该虚拟中断，这样就可以打断当前在执行的流程，从而屏蔽现有方案中切换到宿主机的动作。减少了目标物理处理器从虚拟机到宿主机的切换开销。
本申请第二方面提供一种芯片系统，该芯片系统包括源物理处理器、控制装置、中间装置、发送装置以及目标物理处理器，源物理处理器用于运行宿主机或虚拟机；该芯片系统还包括虚拟机与虚拟机直接通信的硬件设备；中间装置用于：接收硬件设备触发的直通外设中断；根据直通外设中断的物理中断号，从虚拟中断表中查找对应的虚拟机的标识和虚拟中断号，虚拟中断表中记录有物理中断号与虚拟机的标识和虚拟中断号的对应关系；根据虚拟机的标识确定对应的中断亲和性表，从中断亲和性表中确定虚拟机的标识和虚拟 中断号对应的目标虚拟处理器vCPU的标识，中断亲和性表中记录虚拟中断号与虚拟处理器的对应关系；根据目标vCPU的标识，从在位vCPU标识组中确定目标vCPU的标识对应的目标物理处理器；将直通外设中断发送给目标物理处理器对应的发送装置。发送装置将直通外设中断发送给目标物理处理器上运行的虚拟机。
该第二方面中，直通外设中断指由直通给虚拟机的外部设备触发的，例如直通给虚拟机的显卡产生的中断。在处理直通外设中断的过程中，会依次使用到虚拟中断表、中断亲和性表和在位vCPU标识组，中断亲和性表和在位vCPU标识组可以参阅前面第一方面的可能的实现方式中的描述进行理解，下面介绍虚拟中断表。虚拟中断表维护物理中断号与虚拟机的标识和虚拟中断号的对应关系，输入一个物理中断号，可以输出虚拟机的标识和虚拟中断号。该处理直通外设中断的过程中，中间装置接收直通外设发送的物理中断号，通过该物理中断号在虚拟中断表中查找对应的虚拟机的标识和虚拟中断号，例如：输入一个物理中断号100，可以输出虚拟机的标识1和虚拟中断号10。然后，根据虚拟机的标识1和虚拟中断号10查找中断亲和性表，查找到对应的vCPU ID，如：查找到vCPU ID为1。再进一步根据该vCPU ID从在位vCPU标识组中查找对应的物理处理器，如：查找到物理处理器1，则中间装置可以将直通外设中断发送给物理处理器1对应的发送装置，由该发送装置将该直通外设中断发送给vCPU ID1对应的vCPU。
该第二方面提供的直通外设中断的处理过程，通过三个对应关系的查找就可以完成发送过程，提高了直通外设中断处理的灵活性。
本申请第三方面提供一种控制装置，该控制装置应用于芯片系统，芯片系统还包括源物理处理器、中间装置和发送装置，源物理处理器用于运行宿主机或虚拟机，控制装置包括寄存器；寄存器用于接收用于触发虚拟中断的信息，用于触发虚拟中断的信息来自于宿主机或虚拟机；控制装置用于：从寄存器中读取用于触发虚拟中断的信息，并将用于触发虚拟中断的信息发送给中间装置，用于触发虚拟中断的信息用于使得中间装置触发虚拟中断，虚拟中断由发送装置发送给目标物理处理器。
在第三方面的一种可能的实现方式中，虚拟中断为虚拟局部中断，目标物理处理器和源物理处理器为同一物理处理器，寄存器用于接收虚拟机写入的用于触发虚拟局部中断的信息；控制装置用于：将用于触发虚拟局部中断的信息发送给中间装置，用于触发虚拟局部中断的信息用于使得中间装置触发虚拟局部中断，虚拟局部中断由发送装置发送给虚拟机的第一虚拟处理器vCPU，第一vCPU运行在源物理处理器上。
在第三方面的一种可能的实现方式中，虚拟中断为虚拟软件中断，用于触发虚拟中断的信息包括虚拟机的第一VCPU写入寄存器的第二vCPU的标识，第二vCPU为运行于目标物理处理器上的虚拟机的vCPU；控制装置用于：从寄存器读取第二vCPU的标识，并获取虚拟机的标识；以及，将虚拟机的标识和第二vCPU的标识发送给中间装置，虚拟机的标识和第二vCPU的标识用于中间装置确定目标物理处理器并触发虚拟软件中断，虚拟软件中断由发送装置发送给目标物理处理器的第二vCPU。
在第三方面的一种可能的实现方式中，虚拟中断为虚拟设备中断，用于触发虚拟中断的信息包括宿主机写入寄存器的目标中断号和虚拟机的标识，目标中断号为宿主机模拟硬 件设备时所触发的中断的标识；控制装置用于：从寄存器读取目标中断号和虚拟机的标识，并将虚拟机的标识和目标中断号发送给中间装置，虚拟机的标识和目标中断号用于中间装置确定目标物理处理器并触发虚拟设备中断，虚拟设备中断由发送装置发送给目标物理处理器的虚拟机的第一vCPU。
本申请第四方面提供一种中间装置，该中间装置应用于芯片系统，芯片系统还包括源物理处理器、控制装置、发送装置以及目标物理处理器，源物理处理器用于运行宿主机或虚拟机，控制装置包括寄存器；寄存器用于接收用于触发虚拟中断的信息，用于触发虚拟中断的信息来自于宿主机或虚拟机；中间装置用于：接收来自控制装置的用于触发虚拟中断的信息，根据用于触发虚拟中断的信息触发虚拟中断，并将虚拟中断发送给发送装置，虚拟中断由发送装置发送给目标物理处理器。
在第四方面的一种可能的实现方式中，虚拟中断为虚拟局部中断，目标物理处理器和源物理处理器为同一物理处理器，寄存器用于接收虚拟机写入的用于触发虚拟局部中断的信息；中间装置用于：根据用于触发虚拟局部中断的信息，触发虚拟局部中断，并将虚拟局部中断发送给发送装置，虚拟局部中断由发送装置发送给虚拟机的第一虚拟处理器vCPU，第一vCPU运行在源物理处理器上。
在第四方面的一种可能的实现方式中，虚拟中断为虚拟软件中断，用于触发虚拟中断的信息包括虚拟机的第一vCPU写入寄存器的第二vCPU的标识，第二vCPU为运行于目标物理处理器上的虚拟机的vCPU；中间装置用于：接收来自控制装置的虚拟机的标识和第二vCPU的标识；根据虚拟机的标识和第二vCPU的标识，从第一对应关系中确定与虚拟机的标识和第二vCPU的标识对应的目标物理处理器；其中，第一对应关系用于记录目标物理处理器、目标处理器上运行的第二vCPU以及虚拟机之间的对应关系；触发虚拟软件中断；将虚拟软件中断发送给与目标物理处理器对应的发送装置，虚拟软件中断由发送装置发送给目标物理处理器的第二vCPU。
在第四方面的一种可能的实现方式中，虚拟中断为虚拟设备中断，用于触发虚拟中断的信息包括宿主机写入寄存器的目标中断号和虚拟机的标识，目标中断号为宿主机模拟硬件设备时所触发的中断的标识；中间装置用于：接收来自控制设备的虚拟机的标识和目标中断号；根据虚拟机的标识和目标中断号，在第二对应关系中查找与虚拟机的标识和目标中断号对应的虚拟机的第一vCPU的标识，第二对应关系用于记录虚拟机、目标中断号和第一vCPU之间的对应关系；根据虚拟机的标识和第一vCPU的标识，从第三对应关系中确定与虚拟机的标识和第一vCPU的标识对应的目标物理处理器；其中，第三对应关系用于记录目标物理处理器、目标处理器上运行的第一vCPU以及虚拟机之间的对应关系；触发虚拟设备中断；将虚拟设备中断发送给与目标物理处理器对应的发送装置，虚拟设备中断由发送装置发送给目标物理处理器的第一vCPU。
在第四方面的一种可能的实现方式中，中间装置包括地址寄存器，地址寄存器用于存储第二对应关系在内存中的地址以及虚拟机的标识；中间装置还用于：根据虚拟机的标识查找到地址寄存器，根据地址寄存器中的地址从内存中获取第二对应关系。
本申请第五方面提供一种发送装置，该发送装置应用于芯片系统，芯片系统还包括源 物理处理器、中间装置、以及目标物理处理器控制装置，源物理处理器用于运行宿主机或虚拟机，控制装置包括寄存器；寄存器用于接收用于触发虚拟中断的信息，用于触发虚拟中断的信息来自于宿主机或虚拟机；发送装置用于：接收来自于中间装置的虚拟中断，并将虚拟中断发送给目标物理处理器。
在第五方面的一种可能的实现方式中，虚拟中断为虚拟局部中断，目标物理处理器和源物理处理器为同一物理处理器；发送装置用于：接收来自中间装置的虚拟局部中断，并将虚拟局部中断发送给虚拟机的第一虚拟处理器vCPU，第一vCPU运行在源物理处理器上。
在第五方面的一种可能的实现方式中，虚拟中断为虚拟软件中断，用于触发虚拟中断的信息包括虚拟机的第一vCPU写入寄存器的第二vCPU的标识，第二vCPU为运行于目标物理处理器上的虚拟机的vCPU；发送装置用于：接收来自中间装置的虚拟软件中断，并将虚拟软件中断发送给运行于目标物理处理器的第二vCPU。
在第五方面的一种可能的实现方式中，虚拟中断为虚拟设备中断，用于触发虚拟中断的信息包括宿主机写入寄存器的目标中断号和虚拟机的标识，目标中断号为宿主机模拟硬件设备时所触发的中断的标识；发送装置用于：接收来自中间装置的虚拟设备中断，并将虚拟设备中断发送给运行于目标物理处理器的第一vCPU。
在第五方面的一种可能的实现方式中，发送装置用于：将虚拟中断写入目标物理处理器的待处理寄存器中，待处理寄存器用于接收目标物理处理器所执行流程的命令。
以上第三方面至第五方面，以及其中任一种可能的实现方式中所描述的特征，以及相应的有意效果，都可以参阅第一方面，以及第一方面的任一可能的实现方式中的描述进行理解，此处不再重复赘述。
本申请第六方面提供一种处理虚拟中断的方法，该方法应用于芯片系统中的控制装置，该芯片系统还包括源物理处理器、中间装置、发送装置以及目标物理处理器，源物理处理器用于运行宿主机或虚拟机，控制装置包括寄存器；寄存器用于接收用于触发虚拟中断的信息，该用于触发虚拟中断的信息来自于宿主机或虚拟机，该方法包括：从寄存器中读取用于触发虚拟中断的信息；将用于触发虚拟中断的信息发送给中间装置，用于触发虚拟中断的信息用于中间装置触发虚拟中断，虚拟中断由发送装置发送给目标物理处理器。
在第六方面的一种可能的实现方式中，虚拟中断为虚拟局部中断，目标物理处理器和源物理处理器为同一物理处理器，寄存器用于接收虚拟机写入的用于触发虚拟局部中断的信息；用于触发虚拟局部中断的信息用于使得中间装置触发虚拟局部中断，虚拟局部中断由发送装置发送给虚拟机的第一虚拟处理器vCPU，第一vCPU运行在源物理处理器上。
在第六方面的一种可能的实现方式中，虚拟中断为虚拟软件中断，用于触发虚拟中断的信息包括虚拟机的第一VCPU写入寄存器的第二vCPU的标识，第二vCPU为运行于目标物理处理器上的虚拟机的vCPU；该方法还包括：获取虚拟机的标识；将虚拟机的标识发送给中间装置，虚拟机的标识和第二vCPU的标识用于中间装置确定目标物理处理器并触发虚拟软件中断，虚拟软件中断由发送装置发送给目标物理处理器的第二vCPU。
在第六方面的一种可能的实现方式中，虚拟中断为虚拟设备中断，用于触发虚拟中断的信息包括宿主机写入寄存器的目标中断号和虚拟机的标识，目标中断号为宿主机模拟硬 件设备时所触发的中断的标识；虚拟机的标识和目标中断号用于中间装置确定目标物理处理器并触发虚拟设备中断，虚拟设备中断由发送装置发送给目标物理处理器的第一vCPU。
本申请第七方面提供一种处理虚拟中断的方法，该方法应用于芯片系统中的中间装置，芯片系统还包括源物理处理器、控制装置、发送装置以及目标物理处理器，源物理处理器用于运行宿主机或虚拟机，控制装置包括寄存器；寄存器用于接收用于触发虚拟中断的信息，该用于触发虚拟中断的信息来自于宿主机或虚拟机，该方法包括：接收来自控制装置的用于触发虚拟中断的信息；根据用于触发虚拟中断的信息触发虚拟中断；将虚拟中断发送给发送装置，虚拟中断由发送装置发送给目标物理处理器。
在第七方面的一种可能的实现方式中，虚拟中断为虚拟局部中断，目标物理处理器和源物理处理器为同一物理处理器，寄存器用于接收虚拟机写入的用于触发虚拟局部中断的信息；用于触发虚拟局部中断的信息用于触发虚拟局部中断，虚拟局部中断由发送装置发送给虚拟机的第一虚拟处理器vCPU，第一vCPU运行在源物理处理器上。
在第七方面的一种可能的实现方式中，虚拟中断为虚拟软件中断，用于触发虚拟中断的信息包括虚拟机的第一vCPU写入寄存器的第二vCPU的标识，第二vCPU为运行于目标物理处理器上的虚拟机的vCPU；上述步骤：根据用于触发虚拟中断的信息触发虚拟中断，包括：根据虚拟机的标识和第二vCPU的标识，从第一对应关系中确定与虚拟机的标识和第二vCPU的标识对应的目标物理处理器；其中，第一对应关系用于记录目标物理处理器、目标处理器上运行的第二vCPU以及虚拟机之间的对应关系；触发虚拟软件中断，虚拟软件中断由发送装置发送给目标物理处理器的第二vCPU。
在第七方面的一种可能的实现方式中，虚拟中断为虚拟设备中断，用于触发虚拟中断的信息包括宿主机写入寄存器的目标中断号和虚拟机的标识，目标中断号为宿主机模拟硬件设备时所触发的中断的标识；上述步骤：根据用于触发虚拟中断的信息触发虚拟中断，包括：根据虚拟机的标识和目标中断号，在第二对应关系中查找与虚拟机的标识和目标中断号对应的虚拟机的第一vCPU的标识，第二对应关系用于记录虚拟机、目标中断号和第一vCPU之间的对应关系；根据虚拟机的标识和第一vCPU的标识，从第三对应关系中确定与虚拟机的标识和第一vCPU的标识对应的目标物理处理器；其中，第三对应关系用于记录目标物理处理器、目标处理器上运行的第一vCPU以及虚拟机之间的对应关系；触发虚拟设备中断，虚拟设备中断由发送装置发送给目标物理处理器的第一vCPU。
在第七方面的一种可能的实现方式中，该方法还包括：根据虚拟机的标识查找到地址寄存器，根据地址寄存器中的地址从内存中获取第二对应关系，地址寄存器用于存储第二对应关系在内存中的地址以及虚拟机的标识。
本申请第八方面提供一种处理虚拟中断的方法，该方法应用于芯片系统中的发送装置，芯片系统还包括源物理处理器、中间装置、控制装置以及目标物理处理器，源物理处理器用于运行宿主机或虚拟机，控制装置包括寄存器；寄存器用于接收用于触发虚拟中断的信息，该用于触发虚拟中断的信息来自于宿主机或虚拟机，该方法包括：接收来自于中间装置的虚拟中断；将虚拟中断发送给目标物理处理器。
在第八方面的一种可能的实现方式中，虚拟中断为虚拟局部中断，目标物理处理器和 源物理处理器为同一物理处理器；上述步骤：将虚拟中断发送给目标物理处理器，包括：将虚拟局部中断发送给虚拟机的第一虚拟处理器vCPU，第一vCPU运行在源物理处理器上。
在第八方面的一种可能的实现方式中，虚拟中断为虚拟软件中断，用于触发虚拟中断的信息包括虚拟机的第一vCPU写入寄存器的第二vCPU的标识，第二vCPU为运行于目标物理处理器上的虚拟机的vCPU；上述步骤：将虚拟中断发送给目标物理处理器，包括：将虚拟软件中断发送给运行于目标物理处理器的第二vCPU。
在第八方面的一种可能的实现方式中，虚拟中断为虚拟设备中断，用于触发虚拟中断的信息包括宿主机写入寄存器的目标中断号和虚拟机的标识，目标中断号为宿主机模拟硬件设备时所触发的中断的标识；上述步骤：将虚拟中断发送给目标物理处理器，包括：将虚拟设备中断发送给运行于目标物理处理器的第一vCPU。
在第八方面的一种可能的实现方式中，该方法还包括：将虚拟中断写入目标物理处理器的待处理寄存器中，待处理寄存器用于接收目标物理处理器所执行流程的命令。
以上第六方面至第八方面，以及其中任一种可能的实现方式中所描述的特征，以及相应的有意效果，都可以参阅第一方面，以及第一方面的任一可能的实现方式中的描述进行理解，此处不再重复赘述。
本申请第九方面提供一种控制装置，该控制装置应用于芯片系统中，该芯片系统还包括源物理处理器、中间装置、发送装置以及目标物理处理器，源物理处理器用于运行宿主机或虚拟机，控制装置包括寄存器；寄存器用于接收用于触发虚拟中断的信息，该用于触发虚拟中断的信息来自于宿主机或虚拟机，该控制装置包括：读取单元，用于从寄存器中读取用于触发虚拟中断的信息；发送单元，用于将用于触发虚拟中断的信息发送给中间装置，用于触发虚拟中断的信息用于中间装置触发虚拟中断，虚拟中断由发送装置发送给目标物理处理器。
在第九方面的一种可能的实现方式中，虚拟中断为虚拟局部中断，目标物理处理器和源物理处理器为同一物理处理器，寄存器用于接收虚拟机写入的用于触发虚拟局部中断的信息；用于触发虚拟局部中断的信息用于使得中间装置触发虚拟局部中断，虚拟局部中断由发送装置发送给虚拟机的第一虚拟处理器vCPU，第一vCPU运行在源物理处理器上。
在第九方面的一种可能的实现方式中，虚拟中断为虚拟软件中断，用于触发虚拟中断的信息包括虚拟机的第一VCPU写入寄存器的第二vCPU的标识，第二vCPU为运行于目标物理处理器上的虚拟机的vCPU；该控制装置还包括处理单元，该处理单元，用于获取虚拟机的标识；发送单元，用于将虚拟机的标识发送给中间装置，虚拟机的标识和第二vCPU的标识用于中间装置确定目标物理处理器并触发虚拟软件中断，虚拟软件中断由发送装置发送给目标物理处理器的第二vCPU。
在第九方面的一种可能的实现方式中，虚拟中断为虚拟设备中断，用于触发虚拟中断的信息包括宿主机写入寄存器的目标中断号和虚拟机的标识，目标中断号为宿主机模拟硬件设备时所触发的中断的标识；虚拟机的标识和目标中断号用于中间装置确定目标物理处理器并触发虚拟设备中断，虚拟设备中断由发送装置发送给目标物理处理器的第一vCPU。
本申请第十方面提供一种中间装置，该中间装置应用于芯片系统中，该芯片系统还包 括源物理处理器、控制装置、发送装置以及目标物理处理器，源物理处理器用于运行宿主机或虚拟机，控制装置包括寄存器；寄存器用于接收用于触发虚拟中断的信息，该用于触发虚拟中断的信息来自于宿主机或虚拟机，该中间装置包括：接收单元，用于接收来自控制装置的用于触发虚拟中断的信息；处理单元，用于根据用于触发虚拟中断的信息触发虚拟中断；发送单元，用于将虚拟中断发送给发送装置，虚拟中断由发送装置发送给目标物理处理器。
在第十方面的一种可能的实现方式中，虚拟中断为虚拟局部中断，目标物理处理器和源物理处理器为同一物理处理器，寄存器用于接收虚拟机写入的用于触发虚拟局部中断的信息；用于触发虚拟局部中断的信息用于触发虚拟局部中断，虚拟局部中断由发送装置发送给虚拟机的第一虚拟处理器vCPU，第一vCPU运行在源物理处理器上。
在第十方面的一种可能的实现方式中，虚拟中断为虚拟软件中断，用于触发虚拟中断的信息包括虚拟机的第一vCPU写入寄存器的第二vCPU的标识，第二vCPU为运行于目标物理处理器上的虚拟机的vCPU；处理单元，用于根据虚拟机的标识和第二vCPU的标识，从第一对应关系中确定与虚拟机的标识和第二vCPU的标识对应的目标物理处理器；其中，第一对应关系用于记录目标物理处理器、目标处理器上运行的第二vCPU以及虚拟机之间的对应关系；触发虚拟软件中断，虚拟软件中断由发送装置发送给目标物理处理器的第二vCPU。
在第十方面的一种可能的实现方式中，虚拟中断为虚拟设备中断，用于触发虚拟中断的信息包括宿主机写入寄存器的目标中断号和虚拟机的标识，目标中断号为宿主机模拟硬件设备时所触发的中断的标识；处理单元，用于根据虚拟机的标识和目标中断号，在第二对应关系中查找与虚拟机的标识和目标中断号对应的虚拟机的第一vCPU的标识，第二对应关系用于记录虚拟机、目标中断号和第一vCPU之间的对应关系；根据虚拟机的标识和第一vCPU的标识，从第三对应关系中确定与虚拟机的标识和第一vCPU的标识对应的目标物理处理器；其中，第三对应关系用于记录目标物理处理器、目标处理器上运行的第一vCPU以及虚拟机之间的对应关系；触发虚拟设备中断，虚拟设备中断由发送装置发送给目标物理处理器的第一vCPU。
在第十方面的一种可能的实现方式中，该处理单元，还用于根据虚拟机的标识查找到地址寄存器，根据地址寄存器中的地址从内存中获取第二对应关系，地址寄存器用于存储第二对应关系在内存中的地址以及虚拟机的标识。
本申请第十一方面提供一种发送装置，该发送装置应用于芯片系统中，该芯片系统还包括源物理处理器、中间装置、控制装置以及目标物理处理器，源物理处理器用于运行宿主机或虚拟机，控制装置包括寄存器；寄存器用于接收用于触发虚拟中断的信息，该用于触发虚拟中断的信息来自于宿主机或虚拟机，发送装置包括：接收单元，用于接收来自于中间装置的虚拟中断；发送单元，用于将虚拟中断发送给目标物理处理器。
在第十一方面的一种可能的实现方式中，虚拟中断为虚拟局部中断，目标物理处理器和源物理处理器为同一物理处理器；发送单元，用于将虚拟局部中断发送给虚拟机的第一虚拟处理器vCPU，第一vCPU运行在源物理处理器上。
在第十一方面的一种可能的实现方式中，虚拟中断为虚拟软件中断，用于触发虚拟中 断的信息包括虚拟机的第一vCPU写入寄存器的第二vCPU的标识，第二vCPU为运行于目标物理处理器上的虚拟机的vCPU；发送单元，用于将虚拟软件中断发送给运行于目标物理处理器的第二vCPU。
在第十一方面的一种可能的实现方式中，虚拟中断为虚拟设备中断，用于触发虚拟中断的信息包括宿主机写入寄存器的目标中断号和虚拟机的标识，目标中断号为宿主机模拟硬件设备时所触发的中断的标识；发送单元，用于将虚拟设备中断发送给运行于目标物理处理器的第一vCPU。
在第十一方面的一种可能的实现方式中，发送单元，用于将虚拟中断写入目标物理处理器的待处理寄存器中，待处理寄存器用于接收目标物理处理器所执行流程的命令。
以上第九方面至第十一方面，以及其中任一种可能的实现方式中所描述的特征，以及相应的有意效果，都可以参阅第一方面，以及第一方面的任一可能的实现方式中的描述进行理解，此处不再重复赘述。
本申请第十二方面提供一种存储一个或多个计算机执行指令的计算机可读存储介质，当计算机执行指令被处理器执行时，处理器执行如上述第六方面或第六方面任意一种可能的实现方式的方法。
本申请第十三方面提供一种存储一个或多个计算机执行指令的计算机可读存储介质，当计算机执行指令被处理器执行时，处理器执行如上述第七方面或第七方面任意一种可能的实现方式的方法。
本申请第十四方面提供一种存储一个或多个计算机执行指令的计算机可读存储介质，当计算机执行指令被处理器执行时，处理器执行如上述第八方面或第八方面任意一种可能的实现方式的方法。
本申请第十五方面提供一种存储一个或多个计算机执行指令的计算机程序产品，当计算机执行指令被处理器执行时，处理器执行如上述第六方面或第六方面任意一种可能的实现方式的方法。
本申请第十六方面提供一种存储一个或多个计算机执行指令的计算机程序产品，当计算机执行指令被处理器执行时，处理器执行如上述第七方面或第七方面任意一种可能的实现方式的方法。
本申请第十七方面提供一种存储一个或多个计算机执行指令的计算机程序产品，当计算机执行指令被处理器执行时，处理器执行如上述第八方面或第八方面任意一种可能的实现方式的方法。
本申请第十八方面提供一种计算机设备，该计算机设备包括上述第一方面或第一方面任一可能的实现方式所述的芯片系统。
本申请第十九方面提供一种芯片系统，该芯片系统包括源物理处理器、控制装置和发送装置以及目标物理处理器。控制装置如前述第三方面、第九方面、第三方面任一可能的实现方式或第九方面任一可能的实现方式，发送装置如前述第五方面、第十一方面、第十一方面任一可能的实现方式或第五方面任一可能的实现方式。
在一种实现方式中，该芯片系统还可以包括如前述第四方面、第十方面、第十方面任 一可能的实现方式或第四方面任一可能的实现方式所述的中间装置。
在一种实现方式中，第十九方面提供的芯片系统为一个处理器，源物理处理器和目标物理处理器是该处理器中的物理核，而控制装置位于该处理器中、与源物理处理器耦合的组件，发送装置是位于该处理器中、与目标物理处理器耦合的组件。可以理解的是，由于处理器中任一个物理核都可能作为虚拟中断的接收方，因此一个物理核可以即作为源物理处理器的角色，又承担目标物理处理器的角色。对应的，与该物理核耦合的可以既包括控制装置也包括发送装置。
本申请实施例提供的芯片系统，在控制装置中设置专用于处理虚拟中断的寄存器，这样，处于用户态的宿主机或虚拟机可以直接将用于触发虚拟中断的信息写入该寄存器中，控制装置可以将该用于触发虚拟中断的信息发送给中间装置，由中间装置触发虚拟中断，并且，中间装置将该虚拟中断发送给发送装置，由发送装置将该虚拟中断发送给目标物理处理器。本申请提供的方案中，宿主机或虚拟机均可以直接访问寄存器，将用于触发虚拟中断的信息写入寄存器，从而将虚拟中断发送出去；因此相比于现有技术，本申请提供的方案不需要源物理处理器执行从虚拟机到宿主机的切换，或者执行从宿主机的用户态到宿主机的内核态的切换，从而减少了处理虚拟中断产生的切换开销，提高了芯片系统的性能。
附图说明
图1是本申请实施例提供的计算机设备的一结构示意图；
图2是本申请实施例提供的虚拟中断的类型示意图；
图3是本申请实施例提供的芯片系统的一结构示意图；
图4是本申请实施例提供的芯片系统的另一结构示意图；
图5是本申请实施例提供的虚拟时钟中断的一示意图；
图6是本申请实施例提供的在位虚拟处理器标识组的一示例示意图；
图7是本申请实施例提供的虚拟软件中断的一示例示意图；
图8是本申请实施例提供的路由装置的一结构示意图；
图9是本申请实施例提供的直通外设中断的一示例示意图；
图10是本申请实施例提供的RISC-V微架构中的芯片系统的一结构示意图；
图11是本申请实施例提供的RISC-V微架构中处理时钟中断的一过程示意图；
图12是本申请实施例提供的RISC-V微架构中处理虚拟软件中断的一过程示意图；
图13是本申请实施例提供的RISC-V微架构中处理虚拟设备中断的一过程示意图；
图14是本申请实施例提供的RISC-V微架构中处理虚拟设备中断的另一过程示意图；
图15是本申请实施例提供的RISC-V微架构中处理直通外设中断的一过程示意图；
图16是本申请实施例提供的处理虚拟中断的方法的一实施例示意图；
图17是本申请实施例提供的控制装置的一实施例示意图；
图18是本申请实施例提供的中间装置的一实施例示意图；
图19是本申请实施例提供的发送装置的一实施例示意图；
图20是本申请实施例提供的计算机设备的另一结构示意图。
具体实施方式
下面结合附图，对本申请的实施例进行描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。本领域普通技术人员可知，随着技术发展和新场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
本申请实施例提供一种芯片系统、处理虚拟中断的方法及相应装置，用于减少因虚拟中断产生的从虚拟机到宿主机，或者从宿主机的用户态切换到宿主机的内核态的切换开销。本申请实施例还提供了相应的计算机设备、计算机存储介质以及计算机程序产品等。以下分别进行详细说明。
虚拟化是将计算机设备的硬件层中的硬件资源(例如处理器、存储器中的存储空间以及网络资源)虚拟化后共享给多个虚拟计算机使用。虚拟计算机为所有类型的虚拟化设备中通过软件虚拟出来的运行环境的统称，该概念包括虚拟机或容器。
如图1所示，计算机设备100包括硬件层112、宿主机层109和虚拟化层，虚拟化层包含虚拟机101和102。虚拟机的个数还可以更多或更少，在此只以两个为例。硬件层112包括处理器系统114、存储器113、通信接口115和中断控制器116。
虚拟机(virtual machine,VM)是通过虚拟化软件在计算机设备上模拟出的。虚拟机(图1中101和102)上可以安装客户操作系统(guest operating system,guest OS)(图1中105和106)，客户操作系统上运行有一个或多个应用程序(图1中103和104)。虚拟机还可访问网络资源。对于在虚拟机中运行的应用程序而言，就像是在真正的计算机中工作。
虚拟处理器(如图1中107和108)：在虚拟化技术下，代表以共享或者分片方式提供给虚拟计算机使用的处理单元，例如虚拟CPU(virtual central processing unit,vCPU)。一台虚拟计算机可以有一个或多个虚拟处理器为其服务，当存在多个虚拟处理器时，通常有一个虚拟处理器为主虚拟处理器,其他为从虚拟处理器。虚拟机包含的虚拟存储器等其他虚拟硬件资源在图1中未示出。虚拟处理器是通过虚拟化软件虚拟出的，它的运行实际是宿主机的处理器或物理核读取并运行软件程序实现的，例如一个物理核读取软件程序并在该物理核的硬件辅助虚拟化的特定模式(例如x86的non-Root模式)下运行该软件程序以实现一个虚拟处理器。一台虚拟机的多个虚拟处理器可以位于不同的物理核上。需要注意的是，本申请各个实施例提到的vCPU是虚拟处理器的一种可选的具体实现方式。各个实施例中提到的“vCPU”可以替换为“虚拟处理器”来理解。
虚拟处理器陷入(trap in)和虚拟处理器陷出(trap out)：虚拟化系统包括两种模式：宿主模式(host mode)与客户模式(guest mode)。宿主模式也可以称为是host的特权级，如：host的用户态或host的内核态，客户模式也可以称为是VM的特权级，如：VM的 用户态或VM的内核态。当一个物理处理器进入客户模式，叫做陷入(虚拟)，陷入的过程也可以理解为是物理处理器从运行宿主机切换到运行虚拟机；当该物理处理器离开客户模式，叫陷出(虚拟)，陷出的过程也可以理解为是物理处理器从运行虚拟机切换到运行宿主机。陷出后物理处理器将暂时不执行该虚拟处理器的代码，所以此时可以理解为虚拟处理器没有运行。物理处理器上运行虚拟机时，会运行该虚拟机的一个虚拟处理器，一个虚拟机可以有多个虚拟处理器，一个物理处理器在一个时刻只运行该虚拟机的一个虚拟处理器，属于同一个虚拟机的多个虚拟处理器可以采用分时复用的方式在该物理处理器上运行，如：在物理处理器1上先运行虚拟机1的vCPU1，物理处理器1结束该vCPU1的运行后，可以再运行该虚拟机1的vCPU2。同属于一个虚拟机的多个vCPU也可以运行在不同的物理处理器上，一个时刻可以在不同的物理处理器上运行不同的vCPU，如：在物理处理器1上运行虚拟机1的vCPU1，在物理处理器2上运行虚拟机1的vCPU2。宿主机(host)层109作为管理层，用以完成硬件资源的管理、分配，为虚拟机提供各种虚拟的硬件资源，如虚拟处理器(107,108)、虚拟内存、虚拟磁盘、虚拟网卡等，还可以实现虚拟机的调度和隔离等。在一些实现方式下，宿主机层109可以包括宿主机操作系统111和虚拟监控装置，例如虚拟机监视器110(virtual machine monitor,VMM)。其中虚拟监控器110可部署在宿主机操作系统111之内，也可以部署在宿主机操作系统111之外。在其他虚拟化架构中虚拟监控装置还可以称为hypervisor或其他类型的虚拟监控装置。宿主机层109还可以称为虚拟化平台，有时宿主机层还可以简称为宿主机。宿主机的特权级包括用户态和内核态。
硬件层112：虚拟化环境运行的硬件平台。其中，硬件层可包括多种硬件，如图1所示，硬件层可包括处理器系统114和存储器113，还可以包括通信接口115，例如网卡(network interface card，NIC)；还可以包括中断控制器116、输入/输出(input/output,I/O)设备等。其中处理器系统114可以包括一个或多个处理器，如图1中列举的处理器1和处理器2。每个处理器中可包括多个物理核，处理器中还可以包括多个寄存器，如：通用寄存器、浮点寄存器等。
处理器系统114，可包括多个处理器，如图1中的处理器1和处理器2。该图1中的处理器1和处理器2都为物理处理器，例如源物理处理器和目标物理处理器。每个物理处理器可以理解为一个物理核。处理器系统114可以具体为一个多核处理器，该多核处理器包括源物理处理器和目标物理处理器。虚拟处理器和物理核可以是绑定的关系，即一个虚拟处理器固定在某个物理核上运行，不能被调度到其他物理核上运行，则该虚拟处理器为绑核；一个虚拟处理器可以根据需要被调度到不同的物理核上运行，则该虚拟处理器为非绑核。
中断控制器116：设置在触发中断请求的硬件和处理器之间，主要用于收集各个硬件产生的中断请求，并按照一定的优先级或其他规则发送给处理器。例如高级可编程中断控制器(advanced programmable interrupt controller,APIC)。
中断(interruption)是指暂停当前程序的指令转而执行中断服务程序。中断可以包括虚拟中断和物理中断，虚拟中断指的是计算机设备中的硬件设备、宿主机、该虚拟机的时钟或虚拟机的虚拟处理器(virtual central processing unit,vCPU)等通知给虚拟机(virtual machine，VM)的中断，产生该虚拟中断的硬件设备可以是计算机设备中的磁盘、 网卡、声卡、鼠标、硬盘等。物理中断指的是硬件设备通知给物理处理器的中断。物理中断是由宿主机处理，而虚拟中断是由虚拟机处理。
中断服务程序(interrupt service routine,ISR)，还可称为中断处理函数，是用于处理中断请求的程序。当处理器接收到中断请求时，暂时停止当前程序的执行转而执行该中断请求对应的中断服务程序。
存储器113提供的存储空间(地址空间)被划分给虚拟机和宿主机使用。宿主机物理地址(host physical address，HPA)指的是本地主机(宿主机)可以使用的物理地址空间；宿主机虚拟地址(host virtual address，HVA)是本地主机(宿主机)可使用的虚拟地址空间。客户机物理地址(guest physical address，GPA)是虚拟机的客户操作系统可使用的物理地址空间；客户机虚拟地址(guest virtual address，GVA)是虚拟机的客户操作系统可使用的虚拟地址空间。
计算机设备100可以为物理设备，例如服务器或终端设备。终端设备可以是具有无线连接功能的手持式设备、或连接到无线调制解调器的其他处理设备。例如，可以为移动电话、计算机(personal computer，PC)、平板电脑、个人数码助理(personal digital assistant，PDA)、移动互联网设备(mobile Internet device，MID)、可穿戴设备和电子书阅读器(e-book reader)等；也可以是便携式、袖珍式、手持式、计算机内置的或者车载的移动设备。
上述计算机设备100中的虚拟机或宿主机可以发送用于触发虚拟中断的信息，进而由本申请实施例提供的芯片系统来完成相应的处理虚拟中断的过程。本申请实施例提供的芯片系统可以包括上述图1中的中断控制器和处理器系统，也可以包括上述图1中的中断控制器或处理器系统。
目标物理处理器目标物理处理器本申请实施例中，如图2所示，虚拟中断可以包括虚拟局部中断(virtual local interrupt)，虚拟软件中断(virtual software interrupt)，虚拟设备中断(virtual device interrupt)和直通外设中断(direct peripheral interrupt)。其中，虚拟局部中断指由虚拟机模拟的例如：虚拟计时器、虚拟鼠标等虚拟局部设备发出的中断或虚拟机的某个vCPU的局部设备发出的中断，例如：虚拟机的某个vCPU的计时器发出的中断，计时器发出的中断也称时钟中断，时钟中断指的是计时器通过计时的方式，在达到虚拟机配置的时间点时计时器所发出的中断。虚拟软件中断指由软件触发的，通常指虚拟机的一个vCPU发给该虚拟机的另一个vCPU的中断，如图2中的同属于一个虚拟机的第一vCPU向第二vCPU发出的中断，一个虚拟机可以有多个vCPU，这些vCPU在一个时刻可以运行在不同的物理处理器上来执行虚拟机的不同任务，当不同的vCPU之间所执行的任务有依赖关系或需要调度时，就会发生虚拟软件中断。虚拟设备中断指由宿主机模拟硬件设备触发的中断，例如宿主机模拟虚拟机磁盘控制器或模拟其他硬件设备产生的中断。直通外设中断指由直通给虚拟机的外部设备触发的，例如直通给虚拟机的显卡产生的中断。
上述四种虚拟中断中，对虚拟局部中断，虚拟软件中断和虚拟设备中断的处理过程需要运行虚拟机的物理处理器由虚拟机切换到宿主机，或者由宿主机的用户态切换到宿主机的内核态，带来了较大的切换开销。为此，本申请实施例提供一种芯片系统，在对处理虚拟中断的过程中，不需要运行虚拟机的物理处理器从虚拟机切换到宿主机，或者由宿主机 的用户态切换到宿主机的内核态，可以节省切换开销。下面结合附图介绍本申请实施例提供的芯片系统。
如图3所示，本申请实施例提供的芯片系统包括：源物理处理器、控制装置、中间装置和发送装置以及目标物理处理器，源物理处理器用于运行宿主机或虚拟机，控制装置包括寄存器，寄存器用于接收用于触发虚拟中断的信息，该用于触发虚拟中断的信息可以来自于宿主机或虚拟机；控制装置用于：将寄存器中的用于触发虚拟中断的信息发送给中间装置；中间装置用于：根据用于触发虚拟中断的信息触发虚拟中断，并将虚拟中断发送给发送装置；发送装置用于：接收来自于中间装置的虚拟中断，并将虚拟中断发送给目标物理处理器。
该芯片系统可以应用于上述图1所示的计算机设备中，该芯片系统可以是上述图1中的中断控制器或处理器系统。
本申请实施例提供的芯片系统可以是片上系统(system on chip，SOC)，源物理处理器和目标物理处理器可以分别是一个处理单元(processing unit。源物理处理器或目标物理处理器可以为物理核，并位于同一个处理器中；源物理处理器和目标物理处理器也可以是位于同一个芯片系统中的不同的处理器。控制装置、中间装置和发送装置都可以是通过硬件电路来实现的。控制装置和发送装置可以部署在该多核处理器中，与源物理处理器和目标物理处理器耦合。中间装置可以部署在该多核处理器中，也可以部署在与多核处理器耦合的外围设备/外围组件上。片上系统可以包括多核处理器和与多核处理器耦合的外围设备/外围组件。芯片系统中的任一个物理处理器既可以作为源物理处理器，也可以作为目标物理处理器。
本申请中使用了源物理处理器和目标物理处理器，需要说明的是，源物理处理器和目标物理处理器可以是一个多核处理器中的两个物理核，也可以是位于不同处理器中的两个物理核。在一种实现方式中，源物理处理器和目标物理处理器可以是同一个物理实体，例如：虚拟局部中断的场景中，源物理处理器和目标物理处理器可以是同一物理处理器。
本申请中，控制装置中可以包括至少一个寄存器，其中，可以是每个寄存器用于接收一种类型的用于触发虚拟中断的信息。如：包括三个寄存器，一个寄存器用于接收用于触发虚拟局部中断的信息，一个寄存器用于接收用于触发虚拟软件中断的信息，一个寄存器用于接收用于触发虚拟设备中断的信息。当然，该控制装置中，针对虚拟中断也可以只配置一个寄存器，用于触发每种类型的虚拟中断的信息不同，可以通过寄存器接收的信息来识别虚拟中断的类型。
中间装置可以有一个，也可以有多个。发送装置可以是每个物理处理器有一个发送装置，也可以是多个物理处理器共用一个发送装置。
本申请实施例提供的芯片系统，在控制装置中设置专用于处理虚拟中断的寄存器，这样，处于用户态的宿主机或虚拟机可以直接将用于触发虚拟中断的信息写入该寄存器中，控制装置可以将该用于触发虚拟中断的信息发送给中间装置，由中间装置触发虚拟中断，并且，中间装置将该虚拟中断发送给发送装置，由发送装置将该虚拟中断发送给目标物理处理器，不需要源物理处理器执行从虚拟机到宿主机的切换，或者执行从宿主机的用户态 到宿主机的内核态的切换，从而减少了处理虚拟中断产生的切换开销，提高了芯片系统的性能。
上述图3中，中间装置可以是虚拟局部中断产生器件，也可以是路由装置，若虚拟中断是虚拟局部中断，则该中间装置可以称为局部中断产生器件(如：计时器)，若虚拟中断是虚拟软件中断或虚拟设备中断，则该中间装置可以称为路由装置。
发送装置前述图2中介绍了虚拟中断的四种类型，下面结合图4，以控制装置中包括寄存器1、寄存器2和寄存器3为例，介绍处理这四种类型的虚拟中断的过程，其中，寄存器1用于接收用于触发虚拟设备中断的信息，寄存器2用于接收用于触发虚拟软件中断的信息，寄存器3用于接收用于触发虚拟局部中断的信息。
图4所示的芯片系统中，源物理处理器用于运行宿主机或虚拟机，宿主机或虚拟机都可以有权限级一和权限级二，其中，权限级一可以是用户态，权限级二可以是内核态。在不同的虚拟化架构中，权限级一和权限级二所对应的状态可能会有不同，对此，本申请实施例中不作限定。
本申请图4中用四种不同的线条标示了四种类型的虚拟中断，其中，用数字1标记的线条表示的是处理虚拟局部中断的过程，用数字2标记的线条表示的是处理虚拟软件中断的过程，用数字3标记的线条表示的是处理虚拟设备中断的过程，用数字4标记的线条表示的是处理直通外设中断的过程。
1、虚拟局部中断。
如图4所示，在处理虚拟局部中断过程中，涉及到的寄存器为寄存器3，中间装置可以称为局部中断产生器件。因为虚拟局部中断是核内中断，所以，目标物理处理器和源物理处理器为同一物理处理器，发送装置与源物理处理器对应。
寄存器用于：接收虚拟机写入的用于触发虚拟局部中断的信息。
局部中断产生器件用于：根据该用于触发虚拟局部中断的信息产生虚拟局部中断。
发送装置用于：将虚拟局部中断发送给虚拟机的第一虚拟处理器vCPU，第一vCPU运行在源物理处理器上。
本申请实施例提供的处理虚拟局部中断的过程，一个物理处理器一个时刻只会运行一个虚拟机的一个vCPU，将虚拟局部中断发送给该vCPU，即可完成将该虚拟局部中断发送给虚拟机的操作。上述图4中的局部中断产生器件可以为计时器，该虚拟局部中断可以为时钟中断。在时钟中断的场景，该过程的实现可以参阅图5进行理解。如图5所示，虚拟机会将中断时间写入控制装置中，(该过程可以参阅图4中的第三寄存器进行理解)，控制装置会将该中断时间写入计时器中，计时器随之启动，预设时间达到后计时器就发出时钟中断，发送装置接收到该时钟中断后，判断虚拟机的第一vCPU在运行，则将该时钟中断发送给第一vCPU。
由上述图4和图5的过程可知，处理该虚拟局部中断的过程不需要源物理处理器执行从虚拟机到宿主机的切换，从而减少了处理虚拟局部中断产生的切换开销，提高了芯片系统的性能。
2、虚拟软件中断。
如图4所示，在处理虚拟软件中断过程中，涉及到的寄存器为寄存器2，中间装置可以称为路由装置。源物理处理器上运行虚拟机的第一vCPU，目标物理处理器上运行虚拟机的第二vCPU。
寄存器用于：接收第一vCPU写入的第二vCPU的标识。
控制装置用于：从寄存器读取第二vCPU的标识，并获取虚拟机的标识；以及，将虚拟机的标识和第二vCPU的标识发送给中间装置。
中间装置用于：根据虚拟机的标识和第二vCPU的标识，从第一对应关系中确定与虚拟机的标识和第二vCPU的标识对应的目标物理处理器；其中，第一对应关系用于记录目标物理处理器、目标处理器上运行的第二vCPU以及虚拟机之间的对应关系；将虚拟软件中断发送给与目标物理处理器对应的发送装置。
发送装置用于：将虚拟软件中断发送给运行于目标物理处理器的第二vCPU。
本申请实施例处理虚拟软件中断的过程中，控制装置可以从专门用于存储源物理处理器上所运行的虚拟机的标识的寄存器中获取该虚拟机的标识。因为，每个虚拟机都可以有多个vCPU，不同虚拟机的vCPU的标识可能是相同的，所以，控制装置需要向中间装置发送该虚拟机的标识和第二vCPU的标识。中间装置上可以存储上述第一对应关系，该第一对应关系可以位于在位vCPU标识组中，该在位vCPU标识组中记录有该芯片系统中的每个物理处理器、每个物理处理器运行的vCPU，以及在运行的vCPU所属的虚拟机之间的对应关系，本申请可以通过查找在位vCPU标识组的方式来目标物理处理器。由上述描述可知，处理该虚拟软件中断的过程不需要源物理处理器执行从虚拟机到宿主机的切换，从而减少了处理虚拟软件中断产生的切换开销，提高了芯片系统的性能。
上述在位vCPU标识组可以参阅图6进行理解。图6所表示的含义为：物理处理器1上运行着VM1的vCPU1，物理处理器2上运行着VM1的vCPU2，物理处理器3上运行着VM2的vCPU1，物理处理器4上运行着VM2的vCPU2。若路由装置从控制装置接收到的是VM1的标识和vCPU2的标识，则可以根据图6所示的在位vCPU标识组可以确定vCPU2在物理处理器2上运行，即可将该虚拟软件中断发送给该物理处理器2对应的发送装置，由物理处理器2对应的发送装置将该虚拟软件中断发送给运行在物理处理器2上的vCPU2。
若经过上述在位vCPU标识组没有查找到第二vCPU，则表示第二vCPU目前没有运行，则路由装置可以将该虚拟软件中断发送给源物理处理器的发送装置，由源物理处理器的发送装置将该虚拟软件中断发送给宿主机，待第二vCPU上线运行后，由宿主机将该虚拟软件中断发送给该第二vCPU。
因为，物理处理器在不同的时间可能运行不同的vCPU，所以，在位vCPU标识组中的对应关系是变化的，该在位vCPU标识组上述路由装置中的在位vCPU标识组可以是源物理处理器上的宿主机来管理的。
本申请实施例处理虚拟软件中断的过程可以参阅图7进行理解。源物理处理器上运行虚拟机，虚拟机的第一vCPU在源物理处理器上运行。第二vCPU运行于另一物理处理器上，第一vCPU要向第二vCPU发送虚拟软件中断，则虚拟机的第一vCPU向控制装置的寄存器2写入第二vCPU的标识。控制装置查找到虚拟机的标识，然后将该虚拟机的标识和第二vCPU的标识 发送给路由装置。路由装置根据虚拟机的标识和第二vCPU的标识查找例如图6中所示的在位vCPU标识组，确定出虚拟机的标识和第二vCPU的标识所对应的物理处理器为目标物理处理器，则路由装置将虚拟软件中断发送给目标物理处理器对应的发送装置，由目标物理处理器对应的发送装置将该虚拟软件中断发送给第二vCPU，也就是发送给在目标物理处理器上运行的虚拟机。
由上述图4、图6和图7的过程可知，本申请实施例提供的虚拟软件中断的处理过程，不需要源物理处理器执行从虚拟机到宿主机的切换，从而减少了处理虚拟软件中断产生的切换开销，提高了芯片系统的性能。
3、虚拟设备中断。
如图4所示，在处理虚拟设备中断过程中，涉及的寄存器为寄存器1，中间装置为路由装置。源物理处理器上运行宿主机，且该宿主机处于用户态。
寄存器用于：接收宿主机写入的目标中断号和虚拟机的标识，目标中断号为宿主机模拟硬件设备时所触发的中断的标识。
控制装置用于：从寄存器读取目标中断号和虚拟机的标识，并将虚拟机的标识和目标中断号发送给中间装置。
中间装置用于：根据虚拟机的标识和目标中断号，在第二对应关系中查找与虚拟机的标识和目标中断号对应的虚拟机的第一vCPU的标识，第二对应关系用于记录虚拟机、目标中断号和第一vCPU之间的对应关系；根据虚拟机的标识和第一vCPU的标识，从第三对应关系中确定与虚拟机的标识和第一vCPU的标识对应的目标物理处理器；其中，第三对应关系用于记录目标物理处理器、目标处理器上运行的第一vCPU以及虚拟机之间的对应关系；将虚拟设备中断发送给与目标物理处理器对应的发送装置。
发送装置用于：将虚拟设备中断发送给运行于目标物理处理器的第一vCPU。
本申请实施例中，虚拟设备中断是处于用户态的宿主机模拟硬件设备触发的中断。硬件设备的类型可以有多种，每种类型的硬件设备的中断号不相同，若宿主机模拟的是磁盘，则该目标中断号为磁盘的中断号。因为宿主机所管理的虚拟机可以有多个，所以，宿主机需要向寄存器中写入该虚拟机的标识和目标中断号。第二对应关系可以位于中断亲和性表中。该中断亲和性表可以是虚拟机配置的，所以，针对每个虚拟机都有一个中断亲和性表。这样，就可以根据该虚拟机的标识找到该虚拟机的中断亲和性表，然后，在根据该目标中断号从该虚拟机的中断亲和性表中确定出对应的vCPU，目标中断号是10，若中断亲和性表中，中断号10与vCPU ID1对应，则可以确定目标中断号对应的vCPU ID为1。路由装置确定vCPU ID为1后，可以根据在位vCPU标识组查找到该vCPU ID1对应的物理处理器，在位vCPU标识组的含义可以参阅前述虚拟软件中断部分的描述进行理解，第三对应关系也可以参考前述第一对应关系进行理解。
下面参阅表1理解虚拟机的中断亲和性表。
表1：图4中的虚拟机的中断亲和性表
中断号 vCPU ID
10 1
20 2
30 3
40 4
上述表1只是举例，实际上不限于表1中列举的几种，还可以有其他表现形式的对应，数量上也可以有更多。该表1中也可以再加入一列，再增加的一列中用于存储图4中虚拟机的标识。
该中断亲和性表可以存储在路由装置中，也可以存储在内存中，该路由装置中可以为每个物理处理器提供一个地址寄存器，该地址寄存器可以是基地址寄存器，该基地址寄存器中可以存储该中断亲和性表在内存的地址以及虚拟机的标识。如图8所示，路由装置上的基地址寄存器1与物理处理器1对应，基地址寄存器2与物理处理器2对应，基地址寄存器3与物理处理器3对应，基地址寄存器4与物理处理器4对应。每个基地址寄存器中的地址指向一个中断亲和性表，如：基地址寄存器1指向中断亲和性表1，基地址寄存器2指向中断亲和性表2，基地址寄存器3指向中断亲和性表3，基地址寄存器4指向中断亲和性表4。若两个物理处理器上运行的是同一个虚拟机，那么两个物理处理器对应的基地址寄存器中的地址可以是相同的，所指向的中断亲和性表可以是同一张表。
这样，在处理虚拟设备中断的过程中，虚拟机向寄存器1中写入目标中断号，控制装置从专门用于存储源物理处理器上运行的虚拟机的寄存器中读取当前在运行的虚拟机的标识，然后，控制装置将该目标中断号和虚拟机的标识发送给路由装置。路由装置根据该虚拟机的标识确定对应的中断亲和性表，再使用目标中断号从该中断亲和性表中查找到对应的vCPU的标识，若目标中断号是10，则可以确定对应的vCPU的标识为1。路由装置确定vCPU的标识为1后，可以根据图6所示的在位vCPU标识组查找到该vCPU 1对应的处理器为物理处理器1。路由装置可以将虚拟设备中断发送给物理处理器1对应的发送装置，由该发送装置将该虚拟设备中断发送给vCPU1对应的第一vCPU。
若经过上述在位vCPU标识组没有查找到第一vCPU，则表示第一vCPU目前没有运行，则路由装置可以将该虚拟软件中断发送给源物理处理器的发送装置，由源物理处理器的发送装置将该虚拟软件中断发送给宿主机，待第一vCPU上线运行后，由宿主机将该虚拟软件中断发送给该第一vCPU。
由上述图4、表1、图8和图6的过程可知，本申请实施例提供的虚拟设备中断的处理过程，不需要源物理处理器执行从宿主机的用户态到宿主机的内核态的切换，从而减少了处理虚拟设备中断产生的切换开销，提高了芯片系统的性能。
4、直通外设中断。
如图4所示，直通外设中断是由与虚拟机直通的硬件设备触发的中断，如与虚拟机直通的显卡，中间装置可以称为路由装置，该直通外设中断通过路由装置和发送装置即可完成该类型的中断处理过程，该过程包括：
中间装置用于：接收硬件设备触发的直通外设中断；根据直通外设中断的物理中断号，从虚拟中断表中查找对应的虚拟机的标识和虚拟中断号，虚拟中断表中记录有物理中断号与虚拟机的标识和虚拟中断号的对应关系；根据虚拟机的标识确定对应的中断亲和性表，从中断亲和性表中确定虚拟机的标识和虚拟中断号对应的目标虚拟处理器vCPU的标识，中断亲和性表中记录虚拟中断号与虚拟处理器的对应关系；根据目标vCPU的标识，从在位vCPU标识组中确定目标vCPU的标识对应的目标物理处理器；将直通外设中断发送给目标物理处理器对应的发送装置。
发送装置用于：将直通外设中断发送给目标物理处理器上运行的虚拟机。
本申请实施例在处理直通外设中断的过程中，会依次使用到虚拟中断表、中断亲和性表和在位vCPU标识组，中断亲和性表和在位vCPU标识组可以参阅前面的描述进行理解，下面介绍虚拟中断表。
虚拟中断表维护物理中断号与虚拟机的标识和虚拟中断号的对应关系，输入一个物理中断号，可以输出虚拟机的标识和虚拟中断号。该虚拟中断表可以参阅表2进行理解。
表2：虚拟中断表
物理中断号 虚拟机的标识 虚拟中断号
100 1 10
200 2 20
300 3 30
400 4 40
如表1所示，输入一个物理中断号100，可以输出虚拟机的标识1和虚拟中断号10。本申请中的虚拟中断表可以存储在路由装置中，也可以存储在内存中，通过类似于基地址寄存器的另一寄存器来指示该虚拟中断表在内存中的位置。
该处理直通外设中断的过程中，如图9所示，路由装置接收直通外设发送的物理中断号，通过该物理中断号在虚拟中断表中查找对应的虚拟机的标识和虚拟中断号，例如：输入一个物理中断号100，可以输出虚拟机的标识1和虚拟中断号10。然后，根据虚拟机的标识1和虚拟中断号10查找表1的中断亲和性表，查找到对应的vCPU的标识，如：查找到vCPU的标识为1。再进一步根据该vCPU1从图6所示的在位vCPU标识组中查找对应的物理处理器，如：查找到物理处理器1，则路由装置可以将直通外设中断发送给物理处理器1对应的发送装置，由该发送装置将该直通外设中断发送给vCPU1对应的第一vCPU。
若经过上述在位vCPU标识组没有查找到第一vCPU，则表示第一vCPU目前没有运行，则路由装置可以将该虚拟软件中断发送给源物理处理器的发送装置，由源物理处理器的发送装置将该虚拟软件中断发送给宿主机，待第一vCPU上线运行后，由宿主机将该虚拟软件中断发送给该第一vCPU。
由上述图4、表2、表1、图6和图9的过程可知，本申请实施例提供的直通外设中断的处理过程，通过三个对应关系的查找就可以完成发送过程，提高了直通外设中断处理的灵活性。
处理上述四种类型的虚拟中断的过程中，发送装置在接收来自中间装置的上述四种类 型的虚拟中断的任意一种后，都进行发送给对应的目标物理处理器，该发送过程可以是将上述几种类型的虚拟中断写入待处理(pending)寄存器中，该待处理寄存器用于接收目标物理处理器接下来所要执行的命令，将该虚拟中断写入到该待处理寄存器中，那么该目标物理处理器接下来就会执行该虚拟中断，这样就可以打断当前在执行的流程，若目标vCPU正在执行，打断目标vCPU，将该中断发送给目标vCPU。若宿主机正在执行，打断宿主机，将该中断直接发送给正在运行的宿主机，待相应的目标vCPU上线后，再由宿主机将该中断传递给目标vCPU，目标vCPU可以是前述描述的第一vCPU或第二vCPU，这样，本申请实施例提供的方案就可以屏蔽现有方案中切换到宿主机的动作，减少了目标物理处理器从虚拟机到宿主机的切换开销。
本申请实施例提供的芯片系统可以应用于RISC-V微架构上，其中，RISC为精简指令集计算(reduced instruction set computing)，如图10所示为芯片系统在RISC-V上的一结构示意图。
如图10所示，芯片系统包括用于与物理处理器交互的控制装置和发送装置和中断路由器。中断路由器包括上述实施例所描述的路由装置。
图10中，RISC-V-CPU表示RISC-V架构中的中央处理器单元，V＝0表示宿主机，V＝1表示虚拟机，HU-mode表示宿主机的用户模式，HS-mode表示宿主机的内核模式，VU-mode表示虚拟机的用户模式，VS-mode表示虚拟机的内核模式。监管器生成处理器间中断逻辑(supervisor generate inter-processor interrupt，sgenipi)用于触发虚拟软件中断的信息，监管器时间比较逻辑(supervisor time compare，stimecmp)用于触发虚拟局部中断的信息的寄存器。在V＝1时，也就是RISC-V-CPU上运行虚拟机时，可以通过sgenipi发送用于触发虚拟软件中断的信息到控制装置的虚拟监管器生成处理器间中断(virtual supervisor generate inter-processor interrupt，vsgenipi)寄存器中，该vsgenipi寄存器为上述实施例中所描述的用于接收用于触发虚拟软件中断的信息的寄存器，如：寄存器2。可以通过stimecmp发送用于触发虚拟局部中断的信息到控制装置的虚拟监管器时间比较(virtual supervisor time compare，vstimecmp)寄存器中，该vstimecmp寄存器为上述实施例中所描述的用于接收用于触发虚拟局部中断的信息的寄存器，如：寄存器3。用户态生成虚拟监管器外部中断(user generate virtual supervisor external interrupt，ugenvsei)寄存器是用于接收用于触发虚拟设备中断的信息的寄存器，如上述实施例中所描述的寄存器1。宿主机用户态的虚拟设备模拟逻辑可以直接发送用于触发虚拟设备中断的信息给ugenvsei寄存器。
中断路由器实现包括虚拟中断表(virtual hart shared interrupt mapping，vhsimap)的寄存器，一组虚拟中断亲和性表(virtual table base，vtblbase)(1-n)的寄存器和一组中断控制界面映射(interface mapping，ifmap)寄存器。其中，vhsimap(1-n)寄存器用于指向内存中存储的虚拟中断表。一组vtblbase(1-n)寄存器中的每个vtblbase寄存器对应RISC-V系统内的一个物理处理器，用于指向该物理处理器上正在运行的vCPU所属的虚拟机定义的虚拟中断亲和性表。提供一组ifmap(1-n)寄存器，每个对应系统内的一个物理处理器，用于记录该物理处理器上正在运行的vCPU的vCPU的标识和所属的虚拟机 的标识。
在上述图10所示的RISC-V架构中，处理虚拟时钟中断的过程可以参阅图11进行理解。
如图11所示，虚拟机利用stimecmp向vstimecmp寄存器写入中断时间，控制装置将下次虚拟时钟中断触发的时间写入虚拟机专用的时钟设备。中断时间到达，该虚拟机专用的时钟设备触发虚拟时钟中断。该虚拟时钟中断发送给发送装置。
发送装置根据当前CPU的虚拟化状态V判断，若V＝1，直接给VS-mode的虚拟机发送局部中断，若V＝0，发送给HS-mode的宿主机，由宿主机代为处理，即在虚拟机上线后，宿主机再将该虚拟时钟中断传递给虚拟机。
在上述图10所示的RISC-V架构中，处理虚拟软件中断的过程可以参阅图12进行理解。
如图12所示，虚拟机的一个vCPU(该场景中可以称为源vCPU)运行在CPU1上，该CPU1可以为前述实施例中的源物理处理器，虚拟机的源vCPU将目标vCPU的标识写入sgenipi，通过该sgenipi将目标vCPU的标识写入控制装置中的vsgenipi寄存器，控制装置获取到虚拟机的标识，并将虚拟机的标识和目标vCPU的标识(vhartid：RISC-V中表示vCPU的标识)发送给中断路由器，中断路由器查找ifmapx，包含该VMID和vhartid的ifmapx寄存器的序号x即为对应的物理处理器的标识(mhartid：RISC-V中表示物理处理器的标识)。该场景中，该物理处理器的标识为图12中的CPU2，该CPU2也可以参阅前述实施例中的目标物理处理器进行理解。中断路由器向上述mhartid的物理处理器的发送装置发送虚拟软件中断，该发送装置判断当前物理处理器的虚拟化状态，若V＝1，发送装置直接给虚拟机发送该虚拟软件中断，若V＝0，发送装置将该虚拟软件中断发送给宿主机代为处理，即在虚拟机上线后，宿主机再将该虚拟软件中断发送给虚拟机。
在上述图10所示的RISC-V架构中，处理虚拟设备中断的过程可以参阅图13进行理解。
如图13所示，处于用户态的宿主机向ugenvsei写入虚拟机的标识和虚拟中断号。控制装置将虚拟机的标识和虚拟中断号发送给中断路由器。中断路由器查找vtblbasex寄存器，找到具有该虚拟机的标识的vtblbasex寄存器中的一个。查找该寄存器指向的内存所保存的中断亲和性表。从中断亲和性表中获得由虚拟机定义的处理该中断的vCPU的vhartid。中断路由器查找ifmapx，找到具有该VMID和vhartid的寄存器对应的物理处理器的序号x，该x为目标物理处理器的mhartid。中断路由器向上述mhartid的物理处理器的发送装置发送虚拟设备中断，发送装置判断当前CPU的虚拟化状态，若V＝1，直接给虚拟机发送设备中断，若V＝0，发送给宿主机代为处理，即在虚拟机上线后，宿主机再将该虚拟设备中断发送给虚拟机。
在上述图10所示的RISC-V架构中，处理虚拟设备中断的另一过程可以参阅图14进行理解。
如图14所示，宿主机向ugenvsei写入虚拟机的标识和虚拟中断号。控制装置将虚拟机的标识和虚拟中断号发送给中断路由器。中断路由器没有实现vtblbasex，默认将虚拟中断发送给具有该虚拟机的任意的vCPU。然后，中断路由器查找ifmapx，找到具有该虚拟机的标识的寄存器对应的物理处理器的序号x，该x为目标物理处理器的mhartid。中断路由器向上述mhartid的物理处理器的发送装置发送虚拟设备中断，发送装置判断当前物理处理器的 虚拟化状态，若V＝1，直接给虚拟机发送虚拟设备中断，若V＝0，发送给宿主机代为处理，即在虚拟机上线后，宿主机再将该虚拟设备中断发送给虚拟机。
在上述图10所示的RISC-V架构中，处理直通外设中断的过程可以参阅图15进行理解。
如图15所示，与虚拟机直接通信的硬件设备触发直通外设中断，中断路由器查找vhlimap指向的虚拟中断表，找出该中断直通给的虚拟机的虚拟机的标识，以及直通后虚拟机内认为的该虚拟中断号。中断路由器查找vtblbasex寄存器，找到具有该VM ID的vtblbasex寄存器中的一个，查找该寄存器指向的内存所保存的虚拟中断亲和性表。从中断亲和性表中获得由虚拟机定义的处理该中断的vCPU的vhartid。中断路由器查找ifmapx，找到具有该VMID和vhartid的寄存器对应的物理处理器的序号x，该x为目标物理处理器的mhartid。中断路由器向上述mhartid的物理处理器的发送装置发送直通外设中断，发送装置判断当前CPU的虚拟化状态，若V＝1，直接给虚拟机发送直通外设中断，若V＝0，发送给宿主机代为处理，即在虚拟机上线后，宿主机再将该直通外设中断发送给虚拟机。
本申请实施例提供的上述方案，通过控制装置，中间装置、发送装置实现虚拟局部中断从局部中断设备到vCPU全程不陷出到宿主机。通过控制装置，路由装置，发送装置实现虚拟软件中断无需虚拟机和宿主机之间的软件配合，从发送端vCPU到接收端vCPU全程不陷出到宿主机。通过控制装置，路由装置，发送装置实现虚拟设备中断从宿主机模拟逻辑到接收端宿主vCPU全程不切换上下文/陷出到宿主机。因此，本申请实施例提供的方案可以加速虚拟机I/O，时钟，调度等方面的性能，仿真数据表明采用本方案处理虚拟局部中断，Redis有80％提升。处理虚拟软件中断有6％提升。
以上描述了通过硬件电路的方式实现的处理虚拟中断的过程，本申请实施例提供的处理虚拟中断的过程还可以通过软件的方式来实现，该软件实现的过程也可以结合在上述的芯片系统中，该芯片系统包括源物理处理器、控制装置、中间装置和发送装置，控制装置包括寄存器；该寄存器用于接收用于触发虚拟中断的信息，关于控制装置、中间装置和发送装置的功能可以通过软件代码的形式来实现，下面结合附图进行介绍。
如图16所示，本申请实施例提供的处理虚拟中断的方法的一实施例包括：
101、控制装置从寄存器中读取用于触发虚拟中断的信息。
该用于触发虚拟中断的信息来源于运行于源物理处理器中的宿主机或虚拟机。
102、控制装置将用于触发虚拟中断的信息发送给中间装置，对应地，中间装置接收该用于触发虚拟中断的信息。
103、中间装置根据用于触发虚拟中断的信息触发虚拟中断。
104、中间装置将虚拟中断发送给发送装置，对应地，发送装置接收虚拟中断。
105、发送装置将虚拟中断发送给目标物理处理器。本申请实施例提供的方案，在控制装置中设置专用于处理虚拟中断的寄存器，这样，处于用户态的宿主机或虚拟机可以直接将用于触发虚拟中断的信息写入该寄存器中，控制装置可以将该用于触发虚拟中断的信息发送给中间装置，由中间装置触发虚拟中断，并且，中间装置将该虚拟中断发送给发送装置，由发送装置将该虚拟中断发送给目标物理处理器。本申请提供的方案中，宿主机或虚拟机均可以直接访问寄存器，将用于触发虚拟中断的信息写入寄存器，从而将虚拟中断发 送出去；因此相比于现有技术，本申请提供的方案不需要源物理处理器执行从虚拟机到宿主机的切换，或者源物理处理器执行从宿主机的用户态到宿主机的内核态的切换，从而减少了处理虚拟中断产生的切换开销，提高了芯片系统的性能。
该虚拟中断为虚拟局部中断时，目标物理处理器和源物理处理器为同一物理处理器；寄存器接收虚拟机写入的用于触发虚拟局部中断的信息。
中间装置根据该用于触发虚拟局部中断的信息产生虚拟局部中断。
发送装置将将虚拟局部中断发送给虚拟机的第一虚拟处理器vCPU，第一vCPU运行在源物理处理器上。
该虚拟中断为虚拟软件中断时，上述步骤101从寄存器中读取的用于触发虚拟中断的信息包括虚拟机的第一vCPU写入寄存器的第二vCPU的标识，第二vCPU为运行于目标物理处理器上的虚拟机的vCPU。
步骤102之前，控制装置获取虚拟机的标识；则步骤103具体包括将虚拟机的标识和第二vCPU的标识发送给中间装置。
步骤103具体包括中间装置根据虚拟机的标识和第二vCPU的标识，从第一对应关系中确定与虚拟机的标识和第二vCPU的标识对应的目标物理处理器；其中，第一对应关系用于记录目标物理处理器、目标处理器上运行的第二vCPU以及虚拟机之间的对应关系；触发虚拟软件中断。
步骤104包括：中间装置将虚拟软件中断发送给与目标物理处理器对应的发送装置。
步骤105包括：发送装置将虚拟软件中断发送给运行于目标物理处理器的第二vCPU。
该虚拟中断为虚拟设备中断时，上述步骤101从寄存器中读取的用于触发虚拟中断的信息包括宿主机写入寄存器的目标中断号和虚拟机的标识，目标中断号为宿主机模拟硬件设备时所触发的中断的标识。
步骤102包括：控制装置将虚拟机的标识和目标中断号发送给中间装置。
步骤103包括：中间装置根据虚拟机的标识和目标中断号，在第二对应关系中查找与虚拟机的标识和目标中断号对应的虚拟机的第一vCPU的标识，第二对应关系用于记录虚拟机、目标中断号和第一vCPU之间的对应关系；根据虚拟机的标识和第一vCPU的标识，从第三对应关系中确定与虚拟机的标识和第一vCPU的标识对应的目标物理处理器；其中，第三对应关系用于记录目标物理处理器、目标处理器上运行的第一vCPU以及虚拟机之间的对应关系；生成虚拟设备中断。
步骤104包括：中间装置将虚拟设备中断发送给与目标物理处理器对应的发送装置。
步骤105包括：发送装置将虚拟设备中断发送给运行于目标物理处理器的第一vCPU。
以上，通过软件的方式来实现的控制装置、中间装置以及发送装置的功能，可以参阅上述图2至图15所对应的实施例中的相应内容进行理解，此处不作重复赘述。
以上介绍了通过软件实现的处理虚拟中断的方法，下面结合附图介绍实现上述处理虚拟中断的方法的装置。
如图17所示，本申请实施例提供的控制装置20的一实施例包括：该控制装置20应用于芯片系统中，该芯片系统还包括源物理处理器、中间装置、发送装置以及目标物理处理器， 源物理处理器用于运行宿主机或虚拟机，控制装置包括寄存器；寄存器用于接收用于触发虚拟中断的信息，该用于触发虚拟中断的信息来自于宿主机或虚拟机，该控制装置20包括：
读取单元201，用于从寄存器中读取用于触发虚拟中断的信息。
发送单元202，用于将读取单元201读取的用于触发虚拟中断的信息发送给中间装置，用于触发虚拟中断的信息用于中间装置触发虚拟中断，虚拟中断由发送装置发送给目标物理处理器。
可选地，虚拟中断为虚拟局部中断，目标物理处理器和源物理处理器为同一物理处理器，寄存器用于接收虚拟机写入的用于触发虚拟局部中断的信息；用于触发虚拟局部中断的信息用于使得中间装置触发虚拟局部中断，虚拟局部中断由发送装置发送给虚拟机的第一虚拟处理器vCPU，第一vCPU运行在源物理处理器上。
可选地，虚拟中断为虚拟软件中断，用于触发虚拟中断的信息包括虚拟机的第一VCPU写入寄存器的第二vCPU的标识，第二vCPU为运行于目标物理处理器上的虚拟机的vCPU；该控制装置20还包括处理单元203。
处理单元203，用于获取虚拟机的标识。
发送单元202，用于将虚拟机的标识发送给中间装置，虚拟机的标识和第二vCPU的标识用于中间装置确定目标物理处理器并触发虚拟软件中断，虚拟软件中断由发送装置发送给目标物理处理器的第二vCPU。
可选地，虚拟中断为虚拟设备中断，用于触发虚拟中断的信息包括宿主机写入寄存器的目标中断号和虚拟机的标识，目标中断号为宿主机模拟硬件设备时所触发的中断的标识；虚拟机的标识和目标中断号用于中间装置确定目标物理处理器并触发虚拟设备中断，虚拟设备中断由发送装置发送给目标物理处理器的第一vCPU。
如图18所示，本申请实施例提供的中间装置30的一实施例包括：该中间装置30应用于芯片系统中，该芯片系统还包括源物理处理器、控制装置、发送装置以及目标物理处理器，源物理处理器用于运行宿主机或虚拟机，控制装置包括寄存器；寄存器用于接收用于触发虚拟中断的信息，该用于触发虚拟中断的信息来自于宿主机或虚拟机，该中间装置30包括：
接收单元301，用于接收来自控制装置的用于触发虚拟中断的信息。
处理单元302，用于根据用于触发虚拟中断的信息触发虚拟中断。
发送单元303，用于将虚拟中断发送给发送装置，虚拟中断由发送装置发送给目标物理处理器。
可选地，虚拟中断为虚拟局部中断，目标物理处理器和源物理处理器为同一物理处理器，寄存器用于接收虚拟机写入的用于触发虚拟局部中断的信息；用于触发虚拟局部中断的信息用于触发虚拟局部中断，虚拟局部中断由发送装置发送给虚拟机的第一虚拟处理器vCPU，第一vCPU运行在源物理处理器上。
可选地，虚拟中断为虚拟软件中断，用于触发虚拟中断的信息包括虚拟机的第一vCPU写入寄存器的第二vCPU的标识，第二vCPU为运行于目标物理处理器上的虚拟机的vCPU。
处理单元302，用于根据虚拟机的标识和第二vCPU的标识，从第一对应关系中确定与虚拟机的标识和第二vCPU的标识对应的目标物理处理器；其中，第一对应关系用于记录目标 物理处理器、目标处理器上运行的第二vCPU以及虚拟机之间的对应关系；触发虚拟软件中断，虚拟软件中断由发送装置发送给目标物理处理器的第二vCPU。
可选地，虚拟中断为虚拟设备中断，用于触发虚拟中断的信息包括宿主机写入寄存器的目标中断号和虚拟机的标识，目标中断号为宿主机模拟硬件设备时所触发的中断的标识。
处理单元302，用于根据虚拟机的标识和目标中断号，在第二对应关系中查找与虚拟机的标识和目标中断号对应的虚拟机的第一vCPU的标识，第二对应关系用于记录虚拟机、目标中断号和第一vCPU之间的对应关系；根据虚拟机的标识和第一vCPU的标识，从第三对应关系中确定与虚拟机的标识和第一vCPU的标识对应的目标物理处理器；其中，第三对应关系用于记录目标物理处理器、目标处理器上运行的第一vCPU以及虚拟机之间的对应关系；触发虚拟设备中断，虚拟设备中断由发送装置发送给目标物理处理器的第一vCPU。
可选地，该处理单元302，还用于根据虚拟机的标识查找到地址寄存器，根据地址寄存器中的地址从内存中获取第二对应关系，地址寄存器用于存储第二对应关系在内存中的地址以及虚拟机的标识。
如图19所示，本申请实施例提供的发送装置40的一实施例包括：该发送装置40应用于芯片系统中，该芯片系统还包括源物理处理器、中间装置、控制装置以及目标物理处理器，源物理处理器用于运行宿主机或虚拟机，控制装置包括寄存器；寄存器用于接收用于触发虚拟中断的信息，该用于触发虚拟中断的信息来自于宿主机或虚拟机，发送装置40包括：
接收单元401，用于接收来自于中间装置的虚拟中断。
发送单元402，用于将虚拟中断发送给目标物理处理器。
可选地，虚拟中断为虚拟局部中断，目标物理处理器和源物理处理器为同一物理处理器；发送单元402，用于将虚拟局部中断发送给虚拟机的第一虚拟处理器vCPU，第一vCPU运行在源物理处理器上。
可选地，虚拟中断为虚拟软件中断，用于触发虚拟中断的信息包括虚拟机的第一vCPU写入寄存器的第二vCPU的标识，第二vCPU为运行于目标物理处理器上的虚拟机的vCPU。
发送单元402，用于将虚拟软件中断发送给运行于目标物理处理器的第二vCPU。
可选地，虚拟中断为虚拟设备中断，用于触发虚拟中断的信息包括宿主机写入寄存器的目标中断号和虚拟机的标识，目标中断号为宿主机模拟硬件设备时所触发的中断的标识。
发送单元402，用于将虚拟设备中断发送给运行于目标物理处理器的第一vCPU。
可选地，发送单元402，用于将虚拟中断写入目标物理处理器的待处理寄存器中，待处理寄存器用于接收目标物理处理器所执行流程的命令。
以上图17至图19所描述的方案，可以参阅上述图2至图15所对应的实施例中的相应内容进行理解，此处不作重复赘述。
图20所示，为本申请的实施例提供的计算机设备50的一种可能的逻辑结构示意图。该计算机设备50可以包括上述图17至图19所介绍的控制装置、中间装置或发送装置，该计算机设备50包括：处理器501、通信接口502、存储器503以及总线504。处理器501、通信接口502以及存储器503通过总线504相互连接。在本申请的实施例中，处理器501用于对计算机设备50的动作进行控制管理，例如，处理器501用于执行图16的方法实施例中的步骤101或 103。存储器503，用于存储计算机设备50的程序代码和数据。通信接口502可以用于执行图16的方法实施例中的步骤102、104或105。
其中，处理器501可以是中央处理器单元，通用处理器，数字信号处理器，专用集成电路，现场可编程门阵列或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。其可以实现或执行结合本申请公开内容所描述的各种示例性的逻辑方框，模块和电路。处理器501也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，数字信号处理器和微处理器的组合等等。总线504可以是外设部件互连标准(Peripheral Component Interconnect，PCI)总线或扩展工业标准结构(Extended Industry Standard Architecture，EISA)总线等。总线可以分为地址总线、数据总线、控制总线等。为便于表示，图20中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
在本申请的另一实施例中，还提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机执行指令，当设备的处理器执行该计算机执行指令时，设备执行上述图16中的控制装置、中间装置或发送装置所执行的处理虚拟中断的方法。
在本申请的另一实施例中，还提供一种计算机程序产品，该计算机程序产品包括计算机执行指令，该计算机执行指令存储在计算机可读存储介质中；当设备的处理器执行该计算机执行指令时，设备执行上述图16中的控制装置、中间装置或发送装置所执行的处理虚拟中断的方法。
本申请另一实施例中还提供一种芯片系统，该芯片系统包括源物理处理器、控制装置和发送装置以及目标物理处理器。控制装置如前述图2至图15的实施例所描述的控制装置，发送装置如前述图2至图15的实施例所描述的发送装置。
在一可能实施例中，该芯片系统还可以包括如前述图2至图15的实施例所描述的中间装置。
在一可能实施例中，该芯片系统为一个处理器，源物理处理器和目标物理处理器是该处理器中的物理核，而控制装置位于该处理器中、与源物理处理器耦合的组件，发送装置是位于该处理器中、与目标物理处理器耦合的组件。可以理解的是，由于处理器中任一个物理核都可能作为虚拟中断的接收方，因此一个物理核可以即作为源物理处理器的角色，又承担目标物理处理器的角色。对应的，与该物理核耦合的可以既包括控制装置也包括发送装置。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请实施例的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请实施例所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，单元 的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请实施例各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请实施例各个实施例方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上，仅为本申请实施例的具体实施方式，但本申请实施例的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请实施例揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请实施例的保护范围之内。因此，本申请实施例的保护范围应以权利要求的保护范围为准。

Claims (37)

  1. 一种芯片系统，其特征在于，包括：源物理处理器、控制装置、中间装置、发送装置以及目标物理处理器，所述源物理处理器用于运行宿主机或虚拟机，所述控制装置包括寄存器，所述寄存器用于接收用于触发虚拟中断的信息，所述用于触发虚拟中断的信息来自于所述宿主机或所述虚拟机；
    所述控制装置用于：将所述寄存器中的所述用于触发虚拟中断的信息发送给中间装置；
    所述中间装置用于：根据所述用于触发虚拟中断的信息触发所述虚拟中断，并将所述虚拟中断发送给所述发送装置；
    所述发送装置用于：接收来自于所述中间装置的所述虚拟中断，并将所述虚拟中断发送给所述目标物理处理器。
  2. 根据权利要求1所述的芯片系统，其特征在于，所述虚拟中断为虚拟局部中断，所述目标物理处理器和所述源物理处理器为同一物理处理器；
    所述寄存器用于：接收所述虚拟机写入的用于触发所述虚拟局部中断的信息；
    所述发送装置用于：将所述虚拟局部中断发送给所述虚拟机的第一虚拟处理器，所述第一虚拟处理器运行在所述源物理处理器上。
  3. 根据权利要求1所述的芯片系统，其特征在于，所述虚拟中断为虚拟软件中断，所述用于触发虚拟中断的信息包括所述虚拟机的第一虚拟处理器写入所述寄存器的第二虚拟处理器的标识，所述第二虚拟处理器为运行于所述目标物理处理器上的所述虚拟机的虚拟处理器；
    所述控制装置用于：从所述寄存器读取所述第二虚拟处理器的标识，并获取所述虚拟机的标识；以及，将所述虚拟机的标识和所述第二虚拟处理器的标识发送给所述中间装置；
    所述中间装置用于：
    根据所述虚拟机的标识和所述第二虚拟处理器的标识，从第一对应关系中确定与所述虚拟机的标识和所述第二虚拟处理器的标识对应的所述目标物理处理器；其中，所述第一对应关系用于记录所述目标物理处理器、所述目标处理器上运行的第二虚拟处理器以及所述虚拟机之间的对应关系；
    将所述虚拟软件中断发送给与所述目标物理处理器对应的所述发送装置；
    所述发送装置用于：将所述虚拟软件中断发送给运行于所述目标物理处理器的所述第二虚拟处理器。
  4. 根据权利要求1所述的芯片系统，其特征在于，所述虚拟中断为虚拟设备中断，所述用于触发虚拟中断的信息包括所述宿主机写入所述寄存器的目标中断号和所述虚拟机的标识，所述目标中断号为所述宿主机模拟硬件设备时所触发的中断的标识；
    所述控制装置用于：从所述寄存器读取所述目标中断号和所述虚拟机的标识，并将所述虚拟机的标识和所述目标中断号发送给所述中间装置；
    所述中间装置用于：
    根据所述虚拟机的标识和所述目标中断号，在第二对应关系中查找与所述虚拟机的标识和所述目标中断号对应的所述虚拟机的第一虚拟处理器的标识，所述第二对应关系用于 记录所述虚拟机、所述目标中断号和所述第一虚拟处理器之间的对应关系；
    根据所述虚拟机的标识和所述第一虚拟处理器的标识，从第三对应关系中确定与所述虚拟机的标识和所述第一虚拟处理器的标识对应的所述目标物理处理器；其中，所述第三对应关系用于记录所述目标物理处理器、所述目标处理器上运行的所述第一虚拟处理器以及所述虚拟机之间的对应关系；
    将所述虚拟设备中断发送给与所述目标物理处理器对应的所述发送装置；
    所述发送装置用于：将所述虚拟设备中断发送给运行于所述目标物理处理器的所述第一虚拟处理器。
  5. 根据权利要求4所述的芯片系统，其特征在于，所述中间装置包括地址寄存器，所述地址寄存器用于存储所述第二对应关系在内存中的地址以及所述虚拟机的标识；
    所述中间装置还用于：根据所述虚拟机的标识查找到所述地址寄存器，根据所述地址寄存器中的地址从所述内存中获取所述第二对应关系。
  6. 一种控制装置，其特征在于，所述控制装置应用于芯片系统，所述芯片系统还包括源物理处理器、中间装置、发送装置以及目标物理处理器，所述源物理处理器用于运行宿主机或虚拟机，所述控制装置包括寄存器；所述寄存器用于接收用于触发虚拟中断的信息，所述用于触发虚拟中断的信息来自于所述宿主机或所述虚拟机；
    所述控制装置用于：从所述寄存器中读取所述用于触发虚拟中断的信息，并将所述用于触发虚拟中断的信息发送给所述中间装置，所述用于触发虚拟中断的信息用于使得所述中间装置触发所述虚拟中断，所述虚拟中断由所述发送装置发送给所述目标物理处理器。
  7. 根据权利要求6所述的控制装置，其特征在于，所述虚拟中断为虚拟局部中断，所述目标物理处理器和所述源物理处理器为同一物理处理器，所述寄存器用于接收所述虚拟机写入的用于触发所述虚拟局部中断的信息；
    所述控制装置用于：将所述用于触发所述虚拟局部中断的信息发送给所述中间装置，所述用于触发所述虚拟局部中断的信息用于使得所述中间装置触发所述虚拟局部中断，所述虚拟局部中断由所述发送装置发送给所述虚拟机的第一虚拟处理器，所述第一虚拟处理器运行在所述源物理处理器上。
  8. 根据权利要求6所述的控制装置，其特征在于，所述虚拟中断为虚拟软件中断，所述用于触发虚拟中断的信息包括所述虚拟机的第一虚拟处理器写入所述寄存器的第二虚拟处理器的标识，所述第二虚拟处理器为运行于所述目标物理处理器上的所述虚拟机的虚拟处理器；
    所述控制装置用于：从所述寄存器读取所述第二虚拟处理器的标识，并获取所述虚拟机的标识；以及，将所述虚拟机的标识和所述第二虚拟处理器的标识发送给所述中间装置，所述虚拟机的标识和所述第二虚拟处理器的标识用于所述中间装置确定目标物理处理器并触发所述虚拟软件中断，所述虚拟软件中断由所述发送装置发送给所述目标物理处理器的所述第二虚拟处理器。
  9. 根据权利要求6所述的控制装置，其特征在于，所述虚拟中断为虚拟设备中断，所述用于触发虚拟中断的信息包括所述宿主机写入所述寄存器的目标中断号和所述虚拟机的标 识，所述目标中断号为所述宿主机模拟硬件设备时所触发的中断的标识；
    所述控制装置用于：从所述寄存器读取所述目标中断号和所述虚拟机的标识，并将所述虚拟机的标识和所述目标中断号发送给所述中间装置，所述虚拟机的标识和所述目标中断号用于所述中间装置确定目标物理处理器并触发所述虚拟设备中断，所述虚拟设备中断由所述发送装置发送给所述目标物理处理器的所述虚拟机的第一虚拟处理器。
  10. 一种中间装置，其特征在于，所述中间装置应用于芯片系统，所述芯片系统还包括源物理处理器、控制装置、发送装置以及目标物理处理器，所述源物理处理器用于运行宿主机或虚拟机，所述控制装置包括寄存器；所述寄存器用于接收用于触发虚拟中断的信息，所述用于触发虚拟中断的信息来自于所述宿主机或所述虚拟机；
    所述中间装置用于：接收来自所述控制装置的所述用于触发虚拟中断的信息，根据所述用于触发虚拟中断的信息触发所述虚拟中断，并将所述虚拟中断发送给所述发送装置，所述虚拟中断由所述发送装置发送给所述目标物理处理器。
  11. 根据权利要求10所述的中间装置，其特征在于，所述虚拟中断为虚拟局部中断，所述目标物理处理器和所述源物理处理器为同一物理处理器，所述寄存器用于接收所述虚拟机写入的用于触发所述虚拟局部中断的信息；
    所述中间装置用于：根据所述用于触发所述虚拟局部中断的信息，触发所述虚拟局部中断，并将所述虚拟局部中断发送给所述发送装置，所述虚拟局部中断由所述发送装置发送给所述虚拟机的第一虚拟处理器，所述第一虚拟处理器运行在所述源物理处理器上。
  12. 根据权利要求10所述的中间装置，其特征在于，所述虚拟中断为虚拟软件中断，所述用于触发虚拟中断的信息包括所述虚拟机的第一虚拟处理器写入所述寄存器的第二虚拟处理器的标识，所述第二虚拟处理器为运行于所述目标物理处理器上的所述虚拟机的虚拟处理器；
    所述中间装置用于：
    接收来自所述控制装置的所述虚拟机的标识和所述第二虚拟处理器的标识；
    根据所述虚拟机的标识和所述第二虚拟处理器的标识，从第一对应关系中确定与所述虚拟机的标识和所述第二虚拟处理器的标识对应的所述目标物理处理器；其中，所述第一对应关系用于记录所述目标物理处理器、所述目标处理器上运行的第二虚拟处理器以及所述虚拟机之间的对应关系；
    触发所述虚拟软件中断；
    将所述虚拟软件中断发送给与所述目标物理处理器对应的所述发送装置，所述虚拟软件中断由所述发送装置发送给所述目标物理处理器的所述第二虚拟处理器。
  13. 根据权利要求10所述的中间装置，其特征在于，所述虚拟中断为虚拟设备中断，所述用于触发虚拟中断的信息包括所述宿主机写入所述寄存器的目标中断号和所述虚拟机的标识，所述目标中断号为所述宿主机模拟硬件设备时所触发的中断的标识；
    所述中间装置用于：
    接收来自所述控制设备的虚拟机的标识和所述目标中断号；
    根据所述虚拟机的标识和所述目标中断号，在第二对应关系中查找与所述虚拟机的标 识和所述目标中断号对应的所述虚拟机的第一虚拟处理器的标识，所述第二对应关系用于记录所述虚拟机、所述目标中断号和所述第一虚拟处理器之间的对应关系；
    根据所述虚拟机的标识和所述第一虚拟处理器的标识，从第三对应关系中确定与所述虚拟机的标识和所述第一虚拟处理器的标识对应的所述目标物理处理器；其中，所述第三对应关系用于记录所述目标物理处理器、所述目标处理器上运行的所述第一虚拟处理器以及所述虚拟机之间的对应关系；
    触发所述虚拟设备中断；
    将所述虚拟设备中断发送给与所述目标物理处理器对应的所述发送装置，所述虚拟设备中断由所述发送装置发送给所述目标物理处理器的所述第一虚拟处理器。
  14. 根据权利要求13所述的中间装置，其特征在于，所述中间装置包括地址寄存器，所述地址寄存器用于存储所述第二对应关系在内存中的地址以及所述虚拟机的标识；
    所述中间装置还用于：根据所述虚拟机的标识查找到所述地址寄存器，根据所述地址寄存器中的地址从所述内存中获取所述第二对应关系。
  15. 一种发送装置，其特征在于，所述发送装置应用于芯片系统，所述芯片系统还包括源物理处理器、中间装置、控制装置以及目标物理处理器，所述源物理处理器用于运行宿主机或虚拟机，所述控制装置包括寄存器；所述寄存器用于接收用于触发虚拟中断的信息，所述用于触发虚拟中断的信息来自于所述宿主机或所述虚拟机；
    所述发送装置用于：接收来自于所述中间装置的所述虚拟中断，并将所述虚拟中断发送给所述目标物理处理器。
  16. 根据权利要求15所述的发送装置，其特征在于，所述虚拟中断为虚拟局部中断，所述目标物理处理器和所述源物理处理器为同一物理处理器；
    所述发送装置用于：接收来自所述中间装置的所述虚拟局部中断，并将所述虚拟局部中断发送给所述虚拟机的第一虚拟处理器，所述第一虚拟处理器运行在所述源物理处理器上。
  17. 根据权利要求15所述的发送装置，其特征在于，所述虚拟中断为虚拟软件中断，所述用于触发虚拟中断的信息包括所述虚拟机的第一虚拟处理器写入所述寄存器的第二虚拟处理器的标识，所述第二虚拟处理器为运行于所述目标物理处理器上的所述虚拟机的虚拟处理器；
    所述发送装置用于：接收来自所述中间装置的所述虚拟软件中断，并将所述虚拟软件中断发送给运行于所述目标物理处理器的所述第二虚拟处理器。
  18. 根据权利要求15所述的发送装置，其特征在于，所述虚拟中断为虚拟设备中断，所述用于触发虚拟中断的信息包括所述宿主机写入所述寄存器的目标中断号和所述虚拟机的标识，所述目标中断号为所述宿主机模拟硬件设备时所触发的中断的标识；
    所述发送装置用于：接收来自所述中间装置的所述虚拟设备中断，并将所述虚拟设备中断发送给运行于所述目标物理处理器的第一虚拟处理器。
  19. 根据权利要求15-18任一项所述的发送装置，其特征在于，
    所述发送装置用于：将所述虚拟中断写入所述目标物理处理器的待处理寄存器中，所 述待处理寄存器用于接收所述目标物理处理器所执行流程的命令。
  20. 一种处理虚拟中断的方法，其特征在于，所述方法应用于芯片系统中的控制装置，所述芯片系统还包括源物理处理器、中间装置、发送装置以及目标物理处理器，所述源物理处理器用于运行宿主机或虚拟机，所述控制装置包括寄存器；所述寄存器用于接收用于触发虚拟中断的信息，所述用于触发虚拟中断的信息来自于所述宿主机或所述虚拟机，所述方法包括：
    从所述寄存器中读取所述用于触发虚拟中断的信息；
    将所述用于触发虚拟中断的信息发送给所述中间装置，所述用于触发虚拟中断的信息用于使得所述中间装置触发所述虚拟中断，所述虚拟中断由所述发送装置发送给所述目标物理处理器。
  21. 根据权利要求20所述的方法，其特征在于，所述虚拟中断为虚拟局部中断，所述目标物理处理器和所述源物理处理器为同一物理处理器，所述寄存器用于接收所述虚拟机写入的用于触发所述虚拟局部中断的信息；
    所述用于触发所述虚拟局部中断的信息用于所述中间装置触发所述虚拟局部中断，所述虚拟局部中断由所述发送装置发送给所述虚拟机的第一虚拟处理器，所述第一虚拟处理器运行在所述源物理处理器上。
  22. 根据权利要求20所述的方法，其特征在于，所述虚拟中断为虚拟软件中断，所述用于触发虚拟中断的信息包括所述虚拟机的第一虚拟处理器写入所述寄存器的第二虚拟处理器的标识，所述第二虚拟处理器为运行于所述目标物理处理器上的所述虚拟机的虚拟处理器；所述方法还包括：
    获取所述虚拟机的标识；
    将所述虚拟机的标识发送给所述中间装置，所述虚拟机的标识和所述第二虚拟处理器的标识用于所述中间装置确定目标物理处理器并触发所述虚拟软件中断，所述虚拟软件中断由所述发送装置发送给所述目标物理处理器的所述第二虚拟处理器。
  23. 根据权利要求20所述的方法，其特征在于，所述虚拟中断为虚拟设备中断，所述用于触发虚拟中断的信息包括所述宿主机写入所述寄存器的目标中断号和所述虚拟机的标识，所述目标中断号为所述宿主机模拟硬件设备时所触发的中断的标识；所述虚拟机的标识和所述目标中断号用于所述中间装置确定目标物理处理器并触发所述虚拟设备中断，所述虚拟设备中断由所述发送装置发送给所述目标物理处理器的所述第一虚拟处理器。
  24. 一种处理虚拟中断的方法，其特征在于，所述方法应用于芯片系统中的中间装置，所述芯片系统还包括源物理处理器、控制装置、发送装置以及目标物理处理器，所述源物理处理器用于运行宿主机或虚拟机，所述控制装置包括寄存器；所述寄存器用于接收用于触发虚拟中断的信息，所述用于触发虚拟中断的信息来自于所述宿主机或所述虚拟机，所述方法包括：
    接收来自所述控制装置的所述用于触发虚拟中断的信息；
    根据所述用于触发虚拟中断的信息触发所述虚拟中断；
    将所述虚拟中断发送给所述发送装置，所述虚拟中断由所述发送装置发送给所述目标 物理处理器。
  25. 根据权利要求24所述的方法，其特征在于，所述虚拟中断为虚拟局部中断，所述目标物理处理器和所述源物理处理器为同一物理处理器，所述寄存器用于接收所述虚拟机写入的用于触发所述虚拟局部中断的信息；
    所述用于触发所述虚拟局部中断的信息用于触发所述虚拟局部中断，所述虚拟局部中断由所述发送装置发送给所述虚拟机的第一虚拟处理器，所述第一虚拟处理器运行在所述源物理处理器上。
  26. 根据权利要求24所述的方法，其特征在于，所述虚拟中断为虚拟软件中断，所述用于触发虚拟中断的信息包括所述虚拟机的第一虚拟处理器写入所述寄存器的第二虚拟处理器的标识，所述第二虚拟处理器为运行于所述目标物理处理器上的所述虚拟机的虚拟处理器；
    所述根据所述用于触发虚拟中断的信息触发所述虚拟中断，包括：
    根据所述虚拟机的标识和所述第二虚拟处理器的标识，从第一对应关系中确定与所述虚拟机的标识和所述第二虚拟处理器的标识对应的所述目标物理处理器；其中，所述第一对应关系用于记录所述目标物理处理器、所述目标处理器上运行的第二虚拟处理器以及所述虚拟机之间的对应关系；
    触发所述虚拟软件中断，所述虚拟软件中断由所述发送装置发送给所述目标物理处理器的所述第二虚拟处理器。
  27. 根据权利要求24所述的方法，其特征在于，所述虚拟中断为虚拟设备中断，所述用于触发虚拟中断的信息包括所述宿主机写入所述寄存器的目标中断号和所述虚拟机的标识，所述目标中断号为所述宿主机模拟硬件设备时所触发的中断的标识；
    所述根据所述用于触发虚拟中断的信息触发所述虚拟中断，包括：
    根据所述虚拟机的标识和所述目标中断号，在第二对应关系中查找与所述虚拟机的标识和所述目标中断号对应的所述虚拟机的第一虚拟处理器的标识，所述第二对应关系用于记录所述虚拟机、所述目标中断号和所述第一虚拟处理器之间的对应关系；
    根据所述虚拟机的标识和所述第一虚拟处理器的标识，从第三对应关系中确定与所述虚拟机的标识和所述第一虚拟处理器的标识对应的所述目标物理处理器；其中，所述第三对应关系用于记录所述目标物理处理器、所述目标处理器上运行的所述第一虚拟处理器以及所述虚拟机之间的对应关系；
    触发所述虚拟设备中断，所述虚拟设备中断由所述发送装置发送给所述目标物理处理器的所述第一虚拟处理器。
  28. 根据权利要求27所述的方法，其特征在于，所述方法还包括：
    根据所述虚拟机的标识查找到地址寄存器，根据所述地址寄存器中的地址从所述内存中获取所述第二对应关系，所述地址寄存器用于存储所述第二对应关系在内存中的地址以及所述虚拟机的标识。
  29. 一种处理虚拟中断的方法，其特征在于，所述方法应用于芯片系统中的发送装置，所述芯片系统还包括源物理处理器、中间装置、控制装置以及目标物理处理器，所述源物 理处理器用于运行宿主机或虚拟机，所述控制装置包括寄存器；所述寄存器用于接收用于触发虚拟中断的信息，所述用于触发虚拟中断的信息来自于所述宿主机或所述虚拟机，所述方法包括：
    接收来自于所述中间装置的所述虚拟中断；
    将所述虚拟中断发送给所述目标物理处理器。
  30. 根据权利要求29所述的方法，其特征在于，所述虚拟中断为虚拟局部中断，所述目标物理处理器和所述源物理处理器为同一物理处理器；
    所述将所述虚拟中断发送给目标物理处理器，包括：
    将所述虚拟局部中断发送给所述虚拟机的第一虚拟处理器，所述第一虚拟处理器运行在所述源物理处理器上。
  31. 根据权利要求29所述的方法，其特征在于，所述虚拟中断为虚拟软件中断，所述用于触发虚拟中断的信息包括所述虚拟机的第一虚拟处理器写入所述寄存器的第二虚拟处理器的标识，所述第二虚拟处理器为运行于所述目标物理处理器上的所述虚拟机的虚拟处理器；
    所述将所述虚拟中断发送给目标物理处理器，包括：
    将所述虚拟软件中断发送给运行于所述目标物理处理器的所述第二虚拟处理器。
  32. 根据权利要求29所述的方法，其特征在于，所述虚拟中断为虚拟设备中断，所述用于触发虚拟中断的信息包括所述宿主机写入所述寄存器的目标中断号和所述虚拟机的标识，所述目标中断号为所述宿主机模拟硬件设备时所触发的中断的标识；
    所述将所述虚拟中断发送给目标物理处理器，包括：
    将所述虚拟设备中断发送给运行于所述目标物理处理器的第一虚拟处理器。
  33. 根据权利要求29-32任一项所述的方法，其特征在于，所述方法还包括：
    将所述虚拟中断写入所述目标物理处理器的待处理寄存器中，所述待处理寄存器用于接收所述目标物理处理器所执行流程的命令。
  34. 一种芯片系统，其特征在于，包括源物理处理器、控制装置和发送装置以及目标物理处理器，所述控制装置为上述权利要求6-9任一项所述的控制装置，所述发送装置为上述权利要求15-19任一项所述的发送装置。
  35. 根据权利要求34所述的芯片系统，其特征在于，所述芯片系统还包括中间装置，所述中间装置为上述权利要求10-14任一项所述的中间装置。
  36. 一种计算机可读存储介质，其上存储有计算机程序，其特征在于，所述计算机程序被处理器执行时实现如权利要求20-23任一项所述的方法，或者，执行时实现如权利要求24-28任一项所述的方法，或者，执行时实现如权利要求29-33任一项所述的方法。
  37. 一种计算机设备，其特征在于，所述计算机设备包括上述权利要求1-5任一项所述的芯片系统，或者包括上述权利要求34或35所述的芯片系统。
PCT/CN2021/123497 2020-10-15 2021-10-13 一种芯片系统、处理虚拟中断的方法及相应装置 WO2022078375A1 (zh)

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