WO2022078120A1

WO2022078120A1 - Insulated gate bipolar transistor and formation method therefor

Info

Publication number: WO2022078120A1
Application number: PCT/CN2021/117225
Authority: WO
Inventors: 王珏; 陈政; 戴银; 徐杨; 徐承福
Original assignee: 绍兴中芯集成电路制造股份有限公司
Priority date: 2020-10-12
Filing date: 2021-09-08
Publication date: 2022-04-21
Also published as: CN111933703A; CN111933703B

Abstract

Provided is an insulated gate bipolar transistor and a formation method therefor. In the formation method, a hydrogen doped region is formed after forming a collector region of a first doping type and a buffer region of a second doping type, and thereby the hydrogen doped region being affected by a processing technique of another doping region can be prevented, improvement of control precision of a preparation technique of the hydrogen doping region is facilitated, and it is easier to form a plurality of hydrogen doped sub-regions having sequentially reduced ion concentration peaks along a direction away from a substrate surface. At this point, on the basis of the formed buffer region and the hydrogen doped region having a precisely controllable concentration distribution, a transistor device at turn-off can be made to achieve a highly efficient electric field stop, and performance of the transistor device is improved.

Description

Insulated gate bipolar transistor and method of forming the same

technical field

The present invention relates to the field of semiconductor technology, in particular to an insulated gate bipolar transistor and a method for forming the same.

Background technique

Insulated Gate Bipolar Transistor (IGBT, Insulated Gate Bipolar Transistor), which combines the gate voltage control characteristics of MOSFET and the low on-resistance characteristics of bipolar transistors, which improves the mutual restraint between the device's withstand voltage and on-resistance , has the advantages of high voltage, high current, high frequency, high power integration density, large input impedance, small on-resistance, and low switching loss. It has been widely used in many fields such as inverter home appliances, industrial control, electric and hybrid vehicles, new energy, and smart grids.

Generally speaking, with the increase of the substrate thickness (ie, the thickness of the drift region) of the insulated gate bipolar transistor, the turn-off voltage of the device tends to be larger and the turn-off time is longer. To this end, a field-stop IGBT device is proposed. The field-stop IGBT device is used to block the electric field by arranging an N-type buffer between the collector region and the drift region, so that the same blocking voltage can be achieved. The thickness of the lower compression drift region, which in turn can reduce the forward voltage drop and turn-off time. However, the performance of the current field-stop IGBT devices is still not stable enough, and further optimization is urgently needed.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a method for forming an insulated gate bipolar transistor, so as to solve the difficulty in preparing a hydrogen doped region with stable distribution by the existing forming method, which is beneficial to improve the performance stability of the formed transistor device.

To this end, the present invention provides a method for forming an insulated gate bipolar transistor, comprising:

A substrate is provided, the substrate has opposing first and second surfaces, and a gate conductive layer, a body region of a first doping type, and a second surface are formed in a portion of the substrate corresponding to the first surface Two doping types of emitter regions;

An ion implantation process and an annealing process are performed on the second surface of the substrate to form a buffer region of the second doping type and a collector region of the first doping type, the collector region extending from the second surface of the substrate. Two surfaces extend inwardly into the substrate, the buffer zone is located on the side of the collector region proximate the body region; and,

An ion implantation process and a thermal annealing process are performed on the second surface of the substrate to form a hydrogen-doped region, the hydrogen-doped region is located on a side of the buffer zone close to the body region, wherein the hydrogen-doped region The impurity region includes a plurality of hydrogen-doped subregions that are sequentially arranged in a direction away from the buffer zone, and ion concentration peaks of the plurality of hydrogen-doped subregions are sequentially decreased in a direction away from the buffer zone.

Optionally, the method for forming the buffer zone includes: sequentially performing at least two ion implantation steps, and performing an annealing process, to form at least two layers of buffer subregions, the at least two layers of buffer subregions being farther away from the collector region. The directions are arranged in sequence; and, the method for forming the hydrogen-doped region includes: performing multiple ion implantation steps in sequence to form the multi-layer hydrogen-doped subregion, and the multi-layer hydrogen-doped subregion is farther away from the buffer. The directions of the zones are arranged in order.

Optionally, the number of hydrogen-doped sub-regions in the hydrogen-doped region is greater than the number of buffer sub-regions in the buffer zone.

Optionally, in the at least two ion implantation steps of forming the buffer zone, as the ion implantation energy increases, the ion implantation dose decreases sequentially, so as to make the ion concentration peak of the formed at least two buffer zones. It decreases sequentially in the direction away from the collector region.

Optionally, in the multi-channel ion implantation step of forming the hydrogen doped region, as the ion implantation energy increases, the ion implantation dose is sequentially decreased, so that the ions of the formed multilayer hydrogen doped region are reduced. The concentration peaks decrease successively in the direction away from the buffer zone.

Optionally, the buffer zone includes two layers of buffer zones, the peak ion concentrations of the buffer zones in the two layers are both between 1E16 atoms/cm ³ and 1E17 atoms/cm ³ , and the widths of the buffer zones in the two layers are both 1E16 atoms/cm 3 and 1E17 atoms/cm 3 0.4μm～0.7μm.

Optionally, the hydrogen-doped region includes four hydrogen-doped subregions, wherein the peak ion concentrations of the two hydrogen-doped subregions closest to the buffer zone are both between 1E12 atoms/cm ³ to 1E14 atoms/cm ³ , and the ion concentration peaks of the two hydrogen-doped partitions farthest from the buffer zone are all between 1E12 atoms/cm ³ and 1E13 atoms/cm ³ , and the widths of the four hydrogen-doped partitions are all 6 μm to 8 μm .

Optionally, the doping ions in the buffer zone include phosphorus, and a laser annealing process is used in the annealing process for forming the buffer zone, and the annealing temperature is set to be greater than or equal to 600°C.

Optionally, in the thermal annealing process for forming the hydrogen doped region, the annealing temperature is 350°C to 450°C.

The present invention also provides an insulated gate bipolar transistor, comprising:

a substrate having opposing first and second surfaces, and having a gate conductive layer, a body region of a first doping type, and a second formed in a portion of the substrate corresponding to the first surface Doping type of emitter region;

a collector region of the first doping type extending inwardly into the substrate from the second surface of the substrate;

A buffer area of a second doping type is formed on the side of the collector region adjacent to the body region, and,

A hydrogen-doped region is formed on a side of the buffer zone close to the body region, and the hydrogen-doped region includes a plurality of hydrogen-doped subregions arranged in sequence in a direction away from the buffer zone, the multiple The ion concentration peaks of each of the hydrogen-doped subregions decrease sequentially in the direction away from the buffer zone.

Optionally, the thickness of the hydrogen doped region is greater than the thickness of the buffer zone.

Optionally, the buffer zone includes at least two buffer zones arranged in sequence away from the collector region, and the number of hydrogen-doped zones in the hydrogen-doped zone is greater than the number of buffer zones in the buffer zone .

Optionally, in the buffer zone, the ion concentration peaks of the at least two buffer zones in a direction away from the collector zone decrease sequentially.

Optionally, the hydrogen-doped subregion with the largest ion concentration peak in the hydrogen-doped region is adjacent to the buffer subregion with the smallest ion concentration peak in the buffer zone, and the hydrogen-doped subregion with the largest ion concentration peak is The peak ion concentration is still smaller than the peak ion concentration of the buffer partition with the smallest peak ion concentration.

In the method for forming an insulated gate bipolar transistor provided by the present invention, the hydrogen doped region is prepared after the buffer zone of the second doping type is formed, so that the formed hydrogen doped region can be prevented from being buffered The influence of the preparation process of the area. It can be seen that, compared with first preparing the hydrogen-doped region and then forming the buffer zone, the method provided by the present invention effectively avoids that the hydrogen in the hydrogen-doped region is recombined during the annealing process of the buffer zone, resulting in the ion concentration of the hydrogen-doped region. Problems where the distribution is unstable and cannot be precisely controlled. That is, according to the method provided by the present invention, it is possible to effectively control the concentration distribution of each hydrogen-doped sub-area in the hydrogen-doped region, and further, a plurality of hydrogen-doped regions with the peak ion concentration decreasing in turn in the direction away from the buffer zone can be prepared. The stray partition is beneficial to improve the performance of the device. For example, the voltage change (dV/dt) between the collector and the emitter when the device is turned off can be more gentle.

Description of drawings

1 is a schematic flowchart of a method for forming an insulated gate bipolar transistor according to an embodiment of the present invention;

2 to 12 are schematic structural diagrams of an insulated gate bipolar transistor in an embodiment of the present invention during its fabrication;

FIG. 13 is a concentration profile of a part of the doped region of the insulated gate bipolar transistor according to an embodiment of the present invention.

Among them, the reference numerals are as follows:

100N-substrate;

200a-gate trench;

210-gate dielectric layer;

220-gate conductive layer;

300P-body area;

400N-emitter region;

500-insulation layer;

600a-contact hole;

610P-heavy doped region;

620 - Contact electrode;

621 - metal diffusion barrier;

622 - metal layer;

630 - electrode lead layer;

700N-buffer;

710N - the first buffer partition;

720N - the second buffer partition;

800P-collector area;

810-ohm electrode;

900H-Hydrogen doped region;

910H-the first hydrogen-doped partition;

920H-second hydrogen doping partition;

930H-the third hydrogen doped partition;

940H-the fourth hydrogen-doped partition;

A1 - the first surface;

A2 - Second surface.

Detailed ways

The core idea of the present invention is to provide a method for forming an insulated gate bipolar transistor, which is beneficial to improve the preparation precision of the buffer layer in the device.

Referring specifically to FIG. 1 , the method for forming the insulated gate bipolar transistor may include:

Step S100, a substrate is provided, the substrate has a first surface and a second surface opposite to each other, and a gate conductive layer, a body of a first doping type are formed in a portion of the substrate corresponding to the first surface region and an emitter region of the second doping type;

Step S200, performing an ion implantation process and an annealing process on the second surface of the substrate to form a buffer region of the second doping type and a collector region of the first doping type;

Step S300, performing an ion implantation process on the second surface of the substrate to form a hydrogen-doped hydrogen-doped region, where the hydrogen-doped region is located on a side of the buffer zone close to the body region, wherein the The hydrogen-doped region includes a plurality of hydrogen-doped subregions that are sequentially arranged in a direction away from the buffer zone, and ion concentration peaks of the plurality of hydrogen-doped subregions are sequentially decreased in a direction away from the buffer zone.

That is, in the formation method provided by the present invention, after forming the buffer region of the second doping type and the collector region of the first doping type, an ion implantation process is performed to form a hydrogen doped region having a plurality of hydrogen doping subregions Miscellaneous area. At this time, the formation of the hydrogen doped region can be prevented from being affected by the preparation process of the buffer region and the collector region, and the hydrogen ions implanted in the hydrogen doped region can be prevented from being recombined at high temperature, so as to ensure the safety of the hydrogen doped region. The stability of the ion concentration distribution is beneficial to the formation of a plurality of hydrogen doping partitions with a gradient in the peak value of the ion concentration.

The insulated gate bipolar transistor and its formation method proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

In step S100 , referring specifically to FIGS. 2 to 12 , a substrate 100N is provided, the substrate 100N has a first surface A1 and a second surface A2 opposite to each other, and the substrate 100N corresponds to the first surface A gate conductive layer 220 , a body region 300P of a first doping type and an emitter region 400N of a second doping type are formed in the portion of .

The substrate 100N is, for example, a substrate 100N of the second doping type, and a part of the substrate 100N may constitute the drift region of the second doping type of the insulated gate bipolar transistor. In this embodiment, the second doping type is N-type, that is, the substrate 100N is an N-type substrate and is used to form an N-type drift region.

And, the preparation steps of the gate conductive layer 220 , the body region 300P and the emitter region 400N can be adjusted according to actual conditions. For example, the gate conductive layer 220 may be preferentially formed in the substrate 100N, and then the body region 300P and the emitter region 400N may be sequentially prepared; or, the body region 300P may be preferentially formed and then prepared The gate conductive layer 220 and the emitter region 400N, etc. In this embodiment, the gate conductive layer 220 is preferentially formed as an example for explanation.

Continuing to refer to FIG. 3 , the gate conductive layer 220 is formed in the gate trench 200a in the substrate 100N. Specifically, by etching the first surface A1 of the substrate 100N, a gate trench 200a extending inward from the first surface A1 of the substrate 100N is formed, wherein the gate trench The trench depth of 200a is, for example, 1 μm˜6 μm, and the sidewalls of the gate trenches 200a may be slightly inclined inclined sidewalls, and the inclined sidewalls of the gate trenches 200a have an acute angle with respect to the horizontal direction. α is, for example, 85° to 90°.

Further, before forming the gate conductive layer 220 in the gate trench 200a, the method further includes: forming a gate dielectric layer 210 on the bottom wall and sidewall of the gate trench 200a. The gate dielectric layer 210 can cover the entire trench sidewall of the gate trench 200a, so that the top of the gate dielectric layer 210 is not lower than the top of the gate trench 200a.

After the gate dielectric layer 210 is formed, the gate conductive layer 220 is filled in the gate trench 200a. Specifically, the method for forming the gate conductive layer 220 includes: filling the gate conductive material layer in the gate trench 200a, and etching back the gate conductive material layer, so that the top surface is lower than the lining material layer. The gate conductive layer 220 on the first surface of the bottom 100N. Wherein, the height difference between the top surface of the gate conductive layer 220 and the first surface A1 of the substrate is, for example, less than or equal to 1 μm.

In this embodiment, the gate dielectric layer 210 covers the entire trench sidewall of the gate trench. Therefore, when an etch-back process is performed to reduce the top surface of the gate conductive layer 220, the Under the protection of the gate dielectric layer 210 , damage to the sidewall of the trench higher than the gate conductive layer 220 is avoided.

In addition, one or more gate conductive layers 220 may be formed on the substrate 100N. In this embodiment, at least two gate conductive layers 220 are formed on the substrate 100N to form at least two transistor cells.

Continuing to refer to FIG. 4 and FIG. 5 , an ion implantation process and an annealing process are performed on the first surface A1 of the substrate 100N to sequentially form the body region 300P of the first doping type and the emitter of the second doping type District 400N. In this embodiment, the body region 300P is a P-type doped region, and the emitter region 400N is an N-type doped region.

4 , the method for forming the body region 300P includes: performing an ion implantation process and an annealing process to form a body region 300P extending into the substrate, and the bottom boundary of the body region 300P is extended to be lower than The depth position of the top of the gate conductive layer 220 is such that the body region 300P at least partially overlaps the gate conductive layer 220 in a lateral space. In this embodiment, the annealing temperature of the annealing process for forming the body region 300P is, for example, 1000° C.˜1200° C., and the extension depth of the body region 300P in the substrate 100N is, for example, 2 μm˜4 μm, which ensures that the body The region 300P can laterally overlap with the gate conductive layer 220 .

Next, as shown in FIG. 5 , the emitter region 400N can also be formed by an ion implantation process and an annealing process, so that the emitter region 400N extends inward from the first surface A1 of the substrate to the body region 300P . The bottom boundary of the emitter region 400N also extends to a depth lower than the top of the gate conductive layer 220 , and the bottom boundary of the emitter region 400N is also higher than the bottom boundary of the body region 300P , so as to utilize the portion of the body region 300P below the emitter region 400N to form a conductive channel region. In this embodiment, the extension depth of the emitter region 400N in the substrate 100N is, for example, 0.2 μm˜1 μm.

Further, after forming the emitter region 400N, the method further includes: forming a contact electrode on the first surface A1 of the substrate 100N for electrically extracting the emitter region 400N and the body region 300P.

Referring specifically to FIGS. 6 to 8 , the method for forming the contact electrode 620 may include the following steps.

The first step, specifically referring to FIG. 6 , forms an insulating layer 500 on the first surface of the substrate 100N, and the insulating layer 500 also fills the space above the gate conductive layer 220 in the gate trench, The gate conductive layer 220 and the emitter region 400N are covered by the insulating layer 500 .

The second step, specifically referring to FIG. 7 , is to etch the insulating layer 500 to the substrate above the emitter region 400N to sequentially expose the emitter region 400N and the body region 300P, and form contacts hole 600a. The contact hole 600 a is used to accommodate the contact electrode 620 .

In this embodiment, the insulating layer 500 and the substrate 100N are sequentially etched, so that the contact hole 600a penetrates through the emitter region 400N and extends into the body region 300P. A contact electrode formed in the contact hole 600a electrically connects the emitter region 400N and the body region 300P

In a further solution, as shown in FIG. 7 , before filling the contact electrode 620 into the contact hole 600a, the method further includes: implanting dopant ions of the first doping type through the contact hole 600a to A heavily doped region 610P is formed at the bottom of the contact hole 600a. In this embodiment, the heavily doped region 610P is a P-type doped region, and the doping concentration of the heavily doped region 610P is higher than that of the body region 300P.

It should be noted that, in the case where the heavily doped region 610P is not provided, the voltage between the collector region and the emitter region will rise instantaneously during the turn-off process of the device, which may easily lead to - The parasitic NPN transistor formed by the body region and the drift region is turned on, resulting in a hold-up effect, which will lead to device failure. To this end, in this embodiment, the heavily doped region 610P is provided at the bottom of the contact hole 600a (after the contact electrode is subsequently formed, the heavily doped region 610P is provided at the bottom of the contact electrode), thereby The parasitic NPN transistors described above can be shorted to improve the hold-up effect of the device. In addition, by arranging the heavily doped region 610P, the contact resistance between the contact electrode and the body region 300P can also be effectively reduced.

In the third step, as shown in FIG. 8 , a contact electrode 620 is formed in the contact hole 600a.

The method for forming the contact electrode 620 includes: forming a metal diffusion barrier layer 621 on the bottom wall and sidewall of the contact hole 600a, and filling the contact hole 600a with a metal layer 622 to form the contact electrode 620. Specifically, a planarization process may be used to make the top surface of the contact electrode 620 flush with the top surface of the insulating layer 500 .

In this embodiment, the metal diffusion barrier layer 621 is surrounded on the periphery of the metal layer 622 to prevent the metal in the metal layer 622 from diffusing into the substrate 100N, thereby improving the leakage current phenomenon of the device. The material of the metal diffusion barrier layer 621 includes, for example, at least one of titanium (Ti) and titanium nitride (TiN), and the thickness of the metal diffusion barrier layer 621 is, for example, 500A˜2000A. And, the material of the metal layer 622 includes, for example, tungsten.

In an optional solution, specifically referring to FIG. 9 , after forming the contact electrodes 620 , the method further includes: forming an electrode lead layer 630 to electrically connect the contact electrodes 620 . Specifically, the electrode lead layer 630 covers the insulating layer 500 and the contact electrode 620 . The material of the electrode lead layer 630 includes, for example, aluminum, copper, aluminum-silicon alloy, or aluminum-silicon-copper alloy.

As described above, at least two gate conductive layers 220 are formed in the substrate 100N of this embodiment, and the body region 300P and the emitter region are correspondingly formed on the sides of each gate conductive layer 220 400N. At this time, at least two contact electrodes 620 are formed correspondingly to connect the corresponding body regions 300P and the emitter regions 400N in a one-to-one correspondence, and the at least two contact electrodes 620 can be electrically connected to the electrode lead layer. 630.

In step S200, referring specifically to FIG. 10, an ion implantation process and an annealing process are performed on the second surface A2 of the substrate 100N to form a buffer zone 700N of the second doping type and a set of the first doping type Electrode area 800P. In this embodiment, the buffer region 700N is an N-type doped region, and the collector region 800P is a P-type doped region.

The buffer area 700N is located on the side of the collector area 800P close to the body area 300P, and the buffer area 700N includes at least two buffer areas arranged in sequence away from the collector area 800P (this In an embodiment, a first buffer partition 710N and a second buffer partition 720N are included.

In a specific solution, before the ion implantation process is performed on the second surface A2 of the substrate 100N, the method further includes: thinning the substrate 100N from the second surface of the substrate 100N, so that the thinned The thickness of the substrate 100N satisfies predetermined requirements.

It should be recognized that the formation method provided in this embodiment is conducive to further reducing the thickness of the drift region of the device, so when the substrate 100N is thinned, the substrate 100N can be correspondingly reduced to a thinner thickness , in order to improve the emission efficiency of the device. For example, the thickness of the thinned substrate 100N is 40 μm˜150 μm.

And, after the substrate 100N is thinned, an ion implantation process can be performed on the thinned substrate 100N to form the buffer region 700N and the collector region 800P. In an optional solution, the buffer region 700N can be formed by the ion implantation process first, and then the collector region 800P can be formed by performing the ion implantation process again; And the ion implantation process is performed again to form the buffer zone 700N.

Specifically, as shown in FIG. 10 and FIG. 12 , when preparing the buffer zone 700N, at least two ion implantation steps and an annealing process can be performed in sequence to form at least two layers of the second dopant in the substrate 100N. Miscellaneous buffer partitions (in this embodiment, including: a first buffer partition 710N and a second buffer partition 720N), and at least two layers of buffer partitions are sequentially arranged along the thickness direction of the substrate 100N, and the buffer partitions The ion concentration peaks of the at least two-layer buffer partitions in 700N successively decrease in the direction away from the second surface A2 of the substrate. That is, in this embodiment, the peak value of the ion concentration of the first buffer zone 710N is lower than the peak value of the ion concentration of the second buffer zone 720N.

The ion implantation energy of the ion implantation step can be adjusted to further adjust the depth position of each buffer subregion implanted into the substrate 100N, and the ion implantation dose of the ion implantation step can be adjusted to further adjust the formed buffer subregions. ion concentration. Based on this, in this embodiment, in the at least two ion implantation steps performed when the buffer zone 700N is formed, that is, as the ion implantation energy increases, the ion implantation dose decreases sequentially, so that the formed at least two ion implantation steps are The ion concentration peaks in the buffer zone decreased sequentially.

In this embodiment, two buffer partitions are formed by sequentially performing two ion implantation steps as an example for explanation.

First, a first ion implantation step is performed to form a first buffer region 710N in a deeper position of the substrate 100N. Wherein, the ion implantation energy of the first ion implantation step is, for example, 1Me˜2Me, and the deepest boundary of the first buffer subregion 710N can reach a depth position of 1.6 μm˜1.9 μm from the second surface of the substrate , and the width dimension of the first buffer subregion 710N along the thickness direction of the substrate is, for example, 0.4 μm˜0.7 μm. Further, the ion concentration distribution of the first buffer subregion 710N presents a Gaussian distribution, and the ion concentration peak value of the first buffer subregion 710 is, for example, 1E16 atoms/cm ³ to 1E17 atoms/cm ³ .

Next, a second ion implantation step is performed to form a second buffer region 720N in a shallower position of the substrate 100N. Wherein, the ion implantation energy of the second ion implantation step is lower than the ion implantation energy of the first ion implantation step. In this embodiment, the ion implantation energy of the second ion implantation step is, for example, 200kev˜700kev, and the distance from the deepest boundary of the formed second buffer region 720N to the second surface of the substrate is 0.3 μm ~1.0 μm, and the width dimension of the second buffer region 720N may be the same as or approximately the same as the width dimension of the first buffer region 710N. Similarly, the ion concentration distribution in the second buffer zone 720 also presents a Gaussian distribution. Specifically, the ion concentration peak value of the second buffer zone 720 is, for example, between 1E16 atoms/cm ³ to 1E17 atoms/cm ³ . within the range.

It should be noted that, in this embodiment, although the ion concentration peaks of the first buffer subregion 710N and the second buffer subregion 720N are both within the same numerical range, the ion implantation doses of the two can still be adjusted within the same numerical range, so that the peak value of the ion concentration of the first buffer zone 710N is lower than the peak value of the ion concentration of the second buffer zone 720N.

In a specific embodiment, the first ion implantation step and the second ion implantation step are, for example, phosphorus ion implantation, arsenic ion implantation or antimony ion implantation, so as to form the N-type first buffer region 710N and the second ion implantation. Two buffer partitions 720N. And, when the first ion implantation step and the second ion implantation step are performed, the ion implantation may be performed at a slightly inclined angle with respect to the second surface A2 of the substrate 100N, for example, the ion implantation may be performed at an inclined angle. Ion implantation is performed on the second surface of the substrate 100N in the direction of 0°˜7°.

Further, after performing the above-mentioned at least two ion implantation steps, an annealing process is performed to activate the implanted ions in each buffer region in the buffer region 700N. Wherein, for the activation of N-type ions (for example, activation of phosphorus ions), a laser annealing process is usually used, and a higher annealing temperature is required, for example, the annealing temperature of the annealing process can be greater than or equal to 600°C.

Continuing to refer to FIG. 10 , after or before the formation of the buffer zone 700N, an ion implantation process and an annealing process are also used to form a collector region 800P of a first doping type, the collector region 800P extending from the substrate 100N The second surface A2 of A2 extends inward to the buffer area 700N so that the buffer area 700N and the collector region 800P abut. Specifically, the thickness of the collector region 800P is, for example, less than or equal to 0.5 μm, that is, the depth of the inward extension of the collector region 800P from the second surface A2 of the substrate 100N is less than or equal to 0.5 μm.

In this embodiment, the ion implantation process for forming the collector region 800P is specifically: an ion implantation process of boron ions to form the P-type collector region 800P. And, the ion doping concentration of the collector region 800P may be 1E16 atoms/cm ³ to 1E18 atoms/cm ³ .

In step S300 , referring specifically to FIG. 11 , an ion implantation process and an annealing process are performed on the second surface of the substrate 100N to form a hydrogen-doped region 900H, and the hydrogen-doped region 900H is located in the buffer zone 700N is close to one side of the body region 300P.

It should be noted that, in this embodiment, the hydrogen-doped region 900H is formed after the buffer region 700N and the collector region 800P are formed. In this way, the annealing process during the preparation of the buffer region 700N and the collector region 800P can effectively avoid the influence on the hydrogen doped region 900H. In particular, when the dopant ions in the buffer zone 700N include phosphorus ions, a higher annealing temperature is usually required to activate the phosphorus ions, and the annealing temperature for activating the phosphorus ions is, for example, higher than 600°C. The environment is particularly prone to cause hydrogen ions in the substrate to be recombined. In this embodiment, by adjusting the preparation steps of the hydrogen doped region 900H to be after the preparation steps of the buffer zone 700N, the hydrogen in the hydrogen doped region 900H is prevented from being recombined at high temperature, which would cause the hydrogen doped region 900H to be recombined. The ion doping concentration cannot be precisely controlled.

In particular, when the prepared hydrogen-doped region 900H includes a plurality of hydrogen-doped sub-regions (in this embodiment, including: the first hydrogen-doped sub-region 910H, the second hydrogen-doped sub-region 910H, the second The hydrogen-doped subregions 920H, the third hydrogen-doped subregions 930H, and the fourth hydrogen-doped subregions 940H), and the ion concentration peaks of the plurality of hydrogen-doped subregions gradually decrease in the direction away from the buffer zone. At this time, if the substrate formed with a plurality of hydrogen-doped partitions is placed under high temperature conditions, the hydrogen-doped partitions closer to the surface of the substrate are more affected by the temperature, which is likely to cause The concentration of the hydrogen doped partition is lower. In other words, when the substrate formed with a plurality of hydrogen-doped subregions is placed under a high temperature condition to complete the high-temperature annealing process, it will be disadvantageous to form a plurality of hydrogen-doped subregions whose concentration peaks decrease sequentially from the substrate surface inward.

However, in this embodiment, the hydrogen doped region 900H is formed after the collector region electricity 800P and the buffer region 700N are prepared, so the hydrogen doped region 900H will not be affected by the collector region electricity 800P and the buffer region 700N. The hydrogen concentration is unstable due to the preparation process of the buffer zone 700N, so that the hydrogen concentration in the formed hydrogen-doped region 900H can be controlled more precisely, so that it is easier to prepare the ion concentration peaks that decrease sequentially from the substrate surface inward. of multiple hydrogen-doped partitions.

In this embodiment, the hydrogen-doped region 900H includes a fourth hydrogen-doped subregion 940H, a third hydrogen-doped subregion 930H, a second hydrogen-doped subregion 920H and The first hydrogen doped partition 910H. And, the ion concentration distributions of the fourth hydrogen-doped subregion 940H, the third hydrogen-doped subregion 930H, the second hydrogen-doped subregion 920H, and the first hydrogen-doped subregion 910H are all Gaussian distributions, and the fourth hydrogen-doped subregion 910H has a Gaussian distribution. The ion concentration peaks of the doping subregion 940H, the third hydrogen doping subregion 930H, the second hydrogen doping subregion 920H and the first hydrogen doping subregion 910H decrease sequentially. That is, the fourth hydrogen-doped subregion 940H is closest to the second surface A2 of the substrate 100N and has the largest ion concentration peak, and the first hydrogen-doped subregion 910H is farthest from the substrate 100N The second surface, A2, has the smallest peak ion concentration.

Continuing to refer to FIG. 11 , the width of the hydrogen-doped region 900H is larger than the width of the buffer zone 700N, so that the hydrogen-doped region 900H can be used to greatly weaken the electric field, so as to realize the electric field cut-off to a greater extent, and can even be based on The hydrogen-doped region 900H directly realizes the electric field cut-off, so that the electric field strength reaching the buffer zone 700N is greatly reduced, and the voltage withstand performance of the device is effectively guaranteed.

In this embodiment, the hydrogen-doped region 900H includes multiple layers of hydrogen-doped subregions, and the buffer region 700N includes at least two layers of buffer subregions, and the hydrogen-doped subregions in the hydrogen-doped region 900H can be The number is greater than the number of buffer partitions in the buffer 700N. In this way, on the one hand, the width of the formed hydrogen doped region 900H is guaranteed to be greater than that of the buffer zone 700N;

Further, the multi-layer hydrogen-doped subregions in the hydrogen-doped region 900H may be formed separately by multiple ion implantation steps. 11 and FIG. 13 , first, a first ion implantation step is performed to form a first hydrogen-doped subregion 910H; then, a second ion implantation step is performed to form a second hydrogen-doped subregion 920H; Next, a third ion implantation step is performed to form a third hydrogen-doped subregion 930H; then, a fourth ion implantation step is performed to form a fourth hydrogen-doped subregion 940H. And, after performing the multi-pass ion implantation steps as described above, an annealing process is performed. Wherein, for the hydrogen-doped region 900H, a thermal annealing process can be used, and the annealing temperature is, for example, 350°C to 450°C.

In a specific embodiment, the process parameters of the four ion implantation steps for forming the hydrogen-doped region 900H and the ion distribution of the formed four-layer hydrogen-doped partition can be referred to, for example, as shown in Table 1.

Table 1

As shown in Table 1, in a specific example, the implant doses of the four hydrogen-doped subregions have overlapping value ranges, however, it should be recognized that the values shown above may still be within the range of the values shown above during the actual ion implantation. The implantation dose of each hydrogen-doped subregion is adjusted within the range, so that the ion concentration peaks of a plurality of hydrogen-doped subregions from deep to shallow increase step by step. In this way, the electric field can be gradually weakened by using a plurality of hydrogen-doped subregions with gradually increasing ion concentrations.

In addition, in this embodiment, the hydrogen-doped subregion (ie, the fourth hydrogen-doped subregion 940H) with the largest ion concentration peak in the hydrogen doping region 900H is adjacent to the buffer with the smallest ion concentration peak in the buffer region 700N partition (ie, the first buffer partition 710N), and the ion concentration peak of the hydrogen-doped partition with the largest ion concentration peak (ie, the fourth hydrogen-doped partition 940H) is still smaller than the buffer with the smallest ion concentration peak The peak ion concentration of the partition (ie, the first buffer partition 710N).

That is, in this embodiment, the ion concentration of the multi-layer doped region formed by the hydrogen doped region 900H and the buffer region 700N is generally increased from deep to shallow, so that the electric field can be weakened step by step. At the same time, the ion concentration of the doped region closest to the collector region 800P is the highest, which ensures that the electric field can be completely cut off in the doped region before the collector region 800P, and is beneficial to improve the leakage phenomenon of the device.

In a further solution, referring specifically to FIG. 12 , after forming the hydrogen-doped region 900H, it further includes: forming an ohmic electrode 810 on the second surface A2 of the substrate 100N, the ohmic electrode 810 and the The collector region 800P contacts.

Specifically, the method for forming the ohmic electrode 810 includes, for example: first, depositing a metal layer on the second surface of the substrate 100N, where the material of the metal layer includes, for example, at least one of aluminum, titanium, nickel and gold Next, an alloying process is performed, so that the metal in the metal layer and the silicon in the substrate 100N realize metal-silicon alloying on the contact surface of the two, so as to reduce the ohmic electrode 810 and the silicon in the substrate 100N. Contact resistance between collector regions 800P.

Based on the above-described formation method, the structure of the formed insulated gate bipolar transistor will be described below. 12 and 13, the insulated gate bipolar transistor includes:

a second conductivity type substrate 100N, the substrate 100N having opposing first and second surfaces;

The gate conductive layer 220 is formed in the substrate 100N;

The body region 300P of the first doping type extends inward from the first surface of the substrate 100N into the substrate 100N, so that the body region 300P at least partially overlaps the gate conductive layer 220 laterally ;

The emitter region 400N of the second doping type extends inward from the first surface of the substrate 100N into the body region 300P, and the bottom boundary of the emitter region 400N is between the gate conductive layer between the top boundary of 220 and the bottom boundary of the body region 300P;

The collector region 800P of the first doping type extends inward from the second surface of the substrate 100N into the substrate 100N;

A buffer zone 700N of the second doping type is formed on the side of the collector region 800P close to the body region 300P, and,

The hydrogen-doped region 900H is formed on the side of the buffer zone 700N close to the body region 300P, and the hydrogen-doped region 900H includes a plurality of hydrogen-doped subregions arranged in sequence away from the buffer zone , the ion concentration peaks of the plurality of hydrogen-doped subregions decrease sequentially in the direction away from the buffer zone. That is, the hydrogen-doped sub-region closest to the second surface of the substrate 100N among the plurality of hydrogen-doped sub-regions has the highest ion concentration peak.

It should be noted that when the substrate structure is heat treated (for example, annealing process), the temperature of the substrate surface is generally the highest, that is, the temperature inside the substrate is usually lower than the temperature of the substrate surface. At this time, if a hydrogen doped region has been formed in the substrate, it is easy to cause the part of the hydrogen doped region closest to the substrate surface to be more susceptible to high temperature recombination, thereby making the hydrogen doped region closest to the substrate surface. Some have lower ion concentrations.

However, different from the traditional process, in this embodiment, the preparation step of the hydrogen-doped region is creatively adjusted to be after the preparation step of the buffer zone, so as to avoid the adverse effect of the preparation process of the buffer zone on the hydrogen-doped region, and improve the efficiency of the buffer zone. The control accuracy of the ion concentration distribution in the formed hydrogen doped region can further prepare a plurality of hydrogen doped subregions with the peak hydrogen ion concentration decreasing in turn in the direction away from the buffer zone, and improve the stability of the prepared device.

Although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or modified into equivalents of equivalent changes Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solutions of the present invention still fall within the protection scope of the technical solutions of the present invention.

It should also be understood that unless otherwise specified or indicated, the terms "first", "second", "third" and other descriptions in the specification are only used to distinguish various components, elements, steps, etc. in the specification, rather than It is used to represent the logical relationship or sequence relationship among various components, elements, steps, etc.

Also, it should be appreciated that the terminology described herein is used to describe particular embodiments only, and not to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a" and "an" include plural references unless the context clearly dictates otherwise. For example, reference to "a step" or "a means" means a reference to one or more steps or means, and may include sub-steps as well as sub-means. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly dictates otherwise. Furthermore, implementation of methods and/or apparatuses in embodiments of the present invention may include performing selected tasks manually, automatically, or a combination.

Claims

A method for forming an insulated gate bipolar transistor, comprising:

A substrate is provided, the substrate has opposing first and second surfaces, and a gate conductive layer, a body region of a first doping type are formed in a portion of the substrate corresponding to the first surface and an emitter region of the second doping type;

An ion implantation process and an annealing process are performed on the second surface of the substrate to form a buffer region of the second doping type and a collector region of the first doping type, the collector region extending from all of the substrate. the second surface extends inwardly into the substrate, the buffer zone is located on a side of the collector region proximate the body region; and,

An ion implantation process and a thermal annealing process are performed on the second surface of the substrate to form a hydrogen-doped region, the hydrogen-doped region is located on a side of the buffer zone close to the body region, wherein the hydrogen-doped region The impurity region includes a plurality of hydrogen-doped subregions that are sequentially arranged in a direction away from the buffer zone, and ion concentration peaks of the plurality of hydrogen-doped subregions are sequentially decreased in a direction away from the buffer zone.
The method for forming an insulated gate bipolar transistor according to claim 1, wherein the method for forming the buffer area comprises: sequentially performing at least two ion implantation steps and performing an annealing process to form at least two buffer layers partitions, the at least two buffer partitions are sequentially arranged in a direction away from the collector region;

And, the method for forming the hydrogen-doped region includes: sequentially performing multiple ion implantation steps to form the multi-layer hydrogen-doped sub-regions, and the multi-layer hydrogen-doped sub-regions are sequentially arranged in a direction away from the buffer zone cloth.
3. The method for forming an insulated gate bipolar transistor according to claim 2, wherein the number of hydrogen-doped subregions in the hydrogen-doped region is greater than the number of buffer subregions in the buffer region.
The method for forming an insulated gate bipolar transistor according to claim 2, wherein in the at least two ion implantation steps of forming the buffer zone, with the increase of ion implantation energy, the ion implantation dose is sequentially decrease, so that the peak values of ion concentrations of the formed at least two-layer buffer regions are successively decreased in the direction away from the collector region.
The method for forming an insulated gate bipolar transistor according to claim 2, wherein in the multi-channel ion implantation step of forming the hydrogen doped region, as the ion implantation energy increases, the ion implantation dose decreasing in sequence, so that the peak value of the ion concentration of the formed multilayer hydrogen-doped subregion decreases in sequence in the direction away from the buffer zone.
The method for forming an insulated gate bipolar transistor according to claim 2, wherein the buffer zone comprises two layers of buffer zones, and the peak ion concentrations of the two layers of the buffer zones are both between 1E16 atoms/cm 3 to 1E17 atoms /cm 3 , and the widths of the buffer partitions of the two layers are both 0.4 μm to 0.7 μm.
The method for forming an insulated gate bipolar transistor according to claim 6, wherein the hydrogen-doped region comprises four hydrogen-doped subregions, wherein two hydrogen-doped subregions closest to the buffer zone are The ion concentration peaks are all between 1E12atoms/cm 3 to 1E14 atoms/cm 3 , and the ion concentration peaks of the two hydrogen-doped partitions farthest from the buffer zone are all between 1E12 atoms/cm 3 to 1E13 atoms/cm 3 , and the widths of the four hydrogen-doped partitions are all 6 μm˜8 μm.
The method for forming an insulated gate bipolar transistor according to claim 1, wherein the doping ions in the buffer zone comprise phosphorus, and a laser annealing process is used in the annealing process for forming the buffer zone, and Make the annealing temperature equal to or higher than 600°C.
The method for forming an insulated gate bipolar transistor according to claim 1, wherein in the thermal annealing process for forming the hydrogen doped region, the annealing temperature is 350°C˜450°C.
An insulated gate bipolar transistor, comprising:

a substrate having opposing first and second surfaces, and a gate conductive layer, a body region of a first doping type, and a portion of the substrate corresponding to the first surface are formed an emitter region of the second doping type;

a collector region of a first doping type extending inwardly into the substrate from the second surface of the substrate;

A buffer area of a second doping type is formed on the side of the collector region adjacent to the body region, and,

A hydrogen-doped region is formed on a side of the buffer zone close to the body region, and the hydrogen-doped region includes a plurality of hydrogen-doped subregions arranged in sequence in a direction away from the buffer zone, the multiple The ion concentration peaks of each of the hydrogen-doped subregions decrease sequentially in the direction away from the buffer zone.
The insulated gate bipolar transistor of claim 10, wherein the thickness of the hydrogen-doped region is greater than the thickness of the buffer region.
11. The insulated gate bipolar transistor of claim 10, wherein the buffer area comprises at least two buffer areas arranged in sequence away from the collector area, and the hydrogen doped area in the hydrogen doped area The number of miscellaneous partitions is greater than the number of buffer partitions in the buffer.
13. The insulated gate bipolar transistor of claim 12, wherein, in the buffer region, the ion concentration peaks of the at least two buffer regions in a direction away from the collector region decrease sequentially.
14. The insulated gate bipolar transistor of claim 13, wherein the buffer zone comprises two layers of buffer zones, and the peak ion concentrations of the two layers of the buffer zones are both between 1E16 atoms/cm 3 to 1E17 atoms/cm 3 between, and the widths of the buffer partitions of the two layers are both 0.4 μm˜0.7 μm.
15. The insulated gate bipolar transistor of claim 14, wherein the hydrogen-doped region comprises four hydrogen-doped subregions, wherein two hydrogen-doped subregions closest to the buffer zone have peak ion concentrations Both are between 1E12atoms/cm 3 to 1E14 atoms/cm 3 , and the peak ion concentrations of the two hydrogen-doped partitions farthest from the buffer zone are both between 1E12 atoms/cm 3 to 1E13 atoms/cm 3 , and all The widths of the four hydrogen-doped partitions are all 6 μm˜8 μm.
13. The insulated gate bipolar transistor of claim 12, wherein the hydrogen-doped subregion with the largest ion concentration peak in the hydrogen-doped region is adjacent to the buffer subregion with the smallest ion concentration peak in the buffer region, And the ion concentration peak value of the hydrogen-doped subregion with the largest ion concentration peak value is still smaller than the ion concentration peak value of the buffer subregion with the smallest ion concentration peak value.