WO2022078029A1 - 存储器测试方法、装置、设备及存储介质 - Google Patents

存储器测试方法、装置、设备及存储介质 Download PDF

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Publication number
WO2022078029A1
WO2022078029A1 PCT/CN2021/110795 CN2021110795W WO2022078029A1 WO 2022078029 A1 WO2022078029 A1 WO 2022078029A1 CN 2021110795 W CN2021110795 W CN 2021110795W WO 2022078029 A1 WO2022078029 A1 WO 2022078029A1
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memory
tested
processing unit
central processing
graphics processor
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PCT/CN2021/110795
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English (en)
French (fr)
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许小峰
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长鑫存储技术有限公司
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Priority to US17/594,536 priority Critical patent/US11860748B2/en
Publication of WO2022078029A1 publication Critical patent/WO2022078029A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested

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  • the present disclosure is based on the Chinese patent application with the application number 202011110688.0, the application date is October 16, 2020, and the application name is "memory testing method, device, equipment and storage medium", and claims the priority of the Chinese patent application, the The entire contents of the Chinese patent application are hereby incorporated by reference into the present disclosure.
  • the present disclosure relates to, but is not limited to, a memory testing method, apparatus, device, and storage medium.
  • Dynamic random access memory (Dynamic Random Access Memory, DRAM)) is an internal memory that directly exchanges data with the central processing unit (Central Processing Unit, CPU), it can be read and written at any time, such as low-power double data rate synchronous dynamic random access memory Access memory (Low Power Double Data Rate SDRAM, LPDDR) is often used in the system-on-a-chip (SoC) in some handheld devices such as mobile phones and tablet computers, so the system-level memory of LPDDR and other memories is Stress testing is very important.
  • DRAM Dynamic Random Access Memory
  • SoC system-on-a-chip
  • the present disclosure provides a memory test, an apparatus, a device and a readable storage medium to improve the load degree of a memory stress test.
  • a memory testing method comprising: acquiring a central processing unit accessible space of a memory to be tested; acquiring a graphics processor accessible space of the memory to be tested; driving the central processing unit based on The central processing unit can access the space to run a test program, so as to access the memory to be tested through the memory bus to be tested; wherein, when the central processing unit runs the test program, the graphics processor is controlled based on the graphics processor The accessible space accesses the memory to be tested through the memory to be tested bus.
  • a memory testing system comprising a central processing unit and a graphics processing unit, wherein: the central processing unit is configured to run a test program based on an allocated central processing unit accessible capacity to access a test program to be tested memory; wherein, when the central processing unit runs the test program, it controls the graphics processor to access the memory to be tested based on the allocated accessible capacity of the graphics processor; the graphics processor is configured to process the memory based on the graphics processor The memory to be tested can be accessed by a processor accessible capacity.
  • a memory testing device comprising: a test preparation module configured to acquire a central processing unit accessible space of a memory to be tested; acquire a graphics processor accessible space of the memory to be tested; test an operation module configured to drive the central processing unit to run a test program based on the accessible space of the central processing unit, so as to access the memory to be tested through the memory bus to be tested; wherein, when the central processing unit runs the test program
  • the graphics processor is controlled to access the memory under test through the memory under test bus based on the accessible space of the graphics processor.
  • an apparatus comprising: a memory, a processor, and executable instructions stored in the memory and executable in the processor, the processor executing the executable instructions When implementing the memory test method as described above.
  • a computer-readable storage medium on which computer-executable instructions are stored, and when the executable instructions are executed by a processor, implement the above-mentioned memory testing method.
  • FIG. 1 shows a schematic diagram of a system structure in an embodiment of the present disclosure.
  • FIG. 2 shows a flowchart of a memory testing method in an embodiment of the present disclosure.
  • FIG. 3 shows a flowchart of another memory testing method in an embodiment of the present disclosure.
  • FIG. 4 shows a flow chart of a memory test according to FIGS. 1 to 3 .
  • Fig. 5 shows an architecture diagram of a memory testing implementation platform according to an exemplary embodiment.
  • FIG. 6 is a block diagram of a memory testing apparatus according to an exemplary embodiment.
  • FIG. 7 shows a schematic structural diagram of an electronic device in an embodiment of the present disclosure.
  • the test of LPDDR in the system segment can be divided into three levels, for example, the first level is, for example, the memory build-in self test (Mbist) module included in the memory controller on the SoC. Mbist can Doing some state-level tests on memory is that the DRAM test is solidified by the SoC itself, and the configurability is relatively poor.
  • the second level is, for example, the Universal Boot loader (Uboot) level.
  • the test software at this level has better scalability and can test all the memory array space, but such tests generally require SoC
  • the original factory support and the development degree of the SoC manufacturer, and because it runs on the SoC, its processing speed is limited by the size of the SoC's Static Random-Access Memory (SRAM).
  • SRAM Static Random-Access Memory
  • the third level is, for example, the test of the base class of Android (Android)/Linux system.
  • the test at this level is closer to the user's applicable method.
  • the scalability and diversity of the test software are very good, but it cannot cover the entire memory. space, because the Android/Linux system itself needs to occupy a large part of the memory space.
  • the present disclosure provides a memory testing method, by driving a central processing unit to run a test program based on the accessible space of the central processing unit, so as to access the to-be-tested memory through a memory bus to be tested, and the central processing unit controls a graphics processor when running the test program Based on the accessible space of the graphics processor, the memory to be tested is accessed through the memory bus to be tested, so that a stress test with a high access load on the memory can be implemented, and the effect of the memory test can be enhanced.
  • FIG. 1 illustrates an exemplary system architecture 10 to which the memory testing method or memory testing apparatus of the present disclosure may be applied.
  • the system architecture 10 may include a central processing unit (CPU) 102 and a graphics processing unit (GPU) 104 , and may also include a memory bus 106 and a memory controller 108 .
  • CPU central processing unit
  • GPU graphics processing unit
  • the various parts of the system architecture 10 are described below.
  • the central processing unit 102 may be configured to run the test program based on the allocated central processing unit accessible capacity to access the memory to be tested, wherein the central processing unit controls the graphics processor 104 based on the allocated graphics when the central processing unit runs the test program.
  • the processor-accessible capacity accesses the memory to be tested.
  • the method of testing memory (such as memory) through CPU is to directly access the memory for testing, and the entire test program can be directly run on the CPU.
  • the CPU can operate the GPU through the general interface of Open Graphics Library (OpenGL) or open programming language (Open Computing Language, OpenCL).
  • OpenGL Open Graphics Library
  • OpenCL Open Computing Language
  • the item of CPU test can be divided into three aspects, the first aspect is for example the test on the array (array) aspect, the second aspect is for example the test on IO, and the third aspect is for example the status Switch test.
  • the test of the array is mainly aimed at whether there are some hardware errors (hard fail) in the array, such as detecting whether a byte jump (bit flip) occurs, etc.
  • the IO test can be divided into two types, for example, the first one is the stress test of the command mode (Command line), such as detecting whether the input and output address jumps occur, etc.; the second one is the data bus mode (DQ bus line) stress test, such as detecting whether the transmission data jumps and so on.
  • the DQ bus line test is the main stress test item.
  • the state switching test can be divided into two kinds of test items, the first one is a switch waiting (suspend) test, for example, and the second one is a restart (reboot) test.
  • the graphics processor 104 may be configured to access the memory to be tested based on the accessible capacity of the graphics processor.
  • the GPU memory test method is an indirect test method.
  • the GPU itself will not directly run the test code.
  • the test code is run on the CPU. Through the operation of the CPU, the GPU will perform image processing instructions, and the GPU will access the memory. do the relevant operations.
  • the memory bus 106 the central processing unit 102 accesses the low-power internal memory through the memory bus 106 to be tested via the memory controller; the graphics processor 104 accesses the low-power internal memory via the memory bus 106 to be tested via the memory controller memory.
  • the GPU or the CPU accesses the memory alone, there is a problem of bus allocation, that is, a part is reserved for the other party and the memory bus 106 cannot be fully occupied.
  • the combined testing method of GPU and CPU can maximize the stress on memory testing.
  • the memory controller 108 can be a memory controller, which is set to exchange data between the CPU and/or GPU and the memory to be tested, and can obtain the maximum memory of the memory it controls through it. capacity, memory type and speed, data width, etc.
  • a general-purpose memory controller can be used for DDR memories of different generations and models. For example, when the memory to be tested is a low-power internal memory (LPDDR), an enhanced general-purpose DDR memory controller can be used.
  • LPDDR low-power internal memory
  • FIG. 2 is a flowchart of a memory testing method according to an exemplary embodiment. The method shown in FIG. 2 can be applied to the system 10 described above, for example.
  • the method 20 provided by this embodiment of the present disclosure may include the following steps.
  • Memory may include internal memory, which may include registers, cache memory, and main memory (commonly referred to as memory), and external memory, which may include hard disks, floppy disks, optical disks, and the like.
  • the internal memory has a small capacity and high speed, and is usually set to temporarily store the currently executing data and programs; the external memory has a large capacity and a slow speed, and is usually set to store data and programs for a long time or permanently.
  • the test methods in this disclosure can be used for various memories and are not limited here.
  • step S204 the accessible space of the graphics processor of the memory to be tested is acquired.
  • memory information such as passable addresses, data volume, speed, etc.
  • memory is allocated to the CPU and GPU respectively, and set the The CPU and GPU have access to obtain the capacity and address of the memory to be tested.
  • the accessible capacity of the CPU can be obtained according to the capacity of the memory to be tested
  • the accessible capacity of the GPU can be obtained according to the capacity of the memory to be tested, and corresponding memory addresses can be allocated respectively.
  • step S206 the central processing unit is driven to run the test program based on the accessible space of the central processing unit to access the memory to be tested through the memory bus to be tested, wherein the central processing unit controls the graphics processor when running the test program
  • the memory under test is accessed through the memory bus under test based on the accessible space of the graphics processor.
  • the address access mode of the CPU can be converted into the block address access mode mapped by the DMA (Direct Memory Access) of the GPU through the conversion interface, so as to realize the conversion of the test logic.
  • DMA Direct Memory Access
  • the central processing unit controls the graphics processor to access the memory to be tested in a predetermined access manner according to the test program based on an open programming language.
  • the CPU can control the GPU based on OpenCL to access the memory to be tested in a predetermined access manner according to the test program.
  • OpenCL is a working standard for writing programs on a heterogeneous parallel computing platform, which can map heterogeneous computing to computing devices such as CPU, GPU, FPGA (Field Programmable Gate Array, Field Programmable Gate Array).
  • OpenCL provides an abstract model of the underlying hardware structure, which can provide a common development application program interface. General-purpose computing programs that can be written through OpenCL to run on GPUs without mapping their algorithms to APIs for 3D graphics such as OpenGL or DirectX.
  • the central processing unit can access the memory to be tested in a predetermined access manner according to the test program through the open graphics program interface CPU or through the OpenGL interface.
  • OpenGL is a graphics application programming interface, including a software library that can access graphics hardware devices such as GPUs. It can implement the OpenGL interface entirely in software on a variety of different graphics hardware systems. Hardware developers of GPUs need to provide implementations that meet the OpenGL specification, often referred to as "drivers", set up to translate API commands defined by OpenGL into GPU instructions.
  • the bus of the memory to be tested can be fully occupied as much as possible, so that the stress test with a high access load on the memory can be implemented, and the memory can be enhanced. test effect.
  • FIG. 3 is a flowchart illustrating another memory testing method according to an exemplary embodiment. The method shown in FIG. 3 can be applied, for example, to the system 10 described above.
  • the method 30 provided by this embodiment of the present disclosure may include the following steps.
  • step S302 the accessible space of the central processing unit of the memory to be tested is obtained.
  • step S304 the accessible space of the graphics processor of the memory to be tested is acquired.
  • steps S302 and S304 reference may be made to steps S202 and S204, which will not be repeated here.
  • step S306 the central processing unit is driven to run the test program based on the accessible space of the central processing unit, so as to access the memory to be tested through the memory bus to be tested, wherein the central processing unit controls the graphics processor when running the test program Based on the accessible space of the graphics processor, the memory to be tested is accessed through the memory bus to be tested, and the central processing unit and the graphics processor serially access the memory to be tested through the memory bus to be tested.
  • the memory bus to be tested may be, for example, an advanced extensible interface protocol bus including a predetermined transmission channel, and the central processing unit and the graphics processor serially access the memory to be tested through the predetermined transmission channel according to the test program.
  • the Advanced eXtensible Interface (AXI) bus includes 5 independent transmission channels, namely, a read address channel, a read data channel, a write address channel, a write data channel, and a write reply channel.
  • the CPU and GPU access memory such as LPDDR through the AXI bus, the access is performed in a serial manner, that is, the transmission is performed sequentially on a transmission channel according to the timing sequence.
  • the memory chip performs firmware configuration, a part may be reserved for the CPU and GPU, that is, if the memory is accessed through the CPU or the GPU for testing, the remaining part of the bus will not be occupied.
  • the AXI bus clock can be occupied by the CPU and GPU by simultaneously sending and writing to their respective memory spaces to access the memory at the same time, so as to maximize the IO test of the memory.
  • the bus of the memory to be tested is occupied as much as possible, thereby maximizing the memory stress testing and enhancing the effect of the memory testing.
  • FIG. 4 is a flow chart of a memory test according to FIGS. 1 to 3 .
  • S402 After the process starts (S402), first obtain the relevant information of the memory (S404), then allocate memory space for the CPU according to the memory information (S406), and allocate memory space for the GPU (S408); after the memory allocation is completed , trigger the joint test of the CPU and GPU (S410), and then check the test result (S412).
  • the test result indicates that after the test is completed, the next memory test is performed (S414), and the process returns to step S402.
  • Fig. 5 is an architecture diagram of a memory testing implementation platform according to an exemplary embodiment.
  • the Android application Application, APP
  • the overall implementation is divided into three parts, the first part is the main control application 502 of the Android application layer, this part is the general control place of the whole test.
  • the second part is to realize the conversion of the test program of the GPU.
  • the GPU test conversion 508 converts the test mode of the CPU into the operation flow of the GPU using the OpenCL interface 510 .
  • the third part is the CPU test engine 506 running the test program of the CPU itself.
  • the program 502 controls the second part and the third part to perform related operations through the relevant application program interface.
  • the native layer may also include a configuration file 504, a recording engine 512, etc. Due to the need for debugging and retention of test results, the test needs to save the test log (log), and the log can be retained in the /data file of Android through the log engine 512.
  • the implementation in Figure 5 requires the root user (root) authority of Android to be implemented, and the developer mode is turned on.
  • Linux low-level driver (kernel mode drive) 514 of the layer is used to complete the memory test.
  • FIG. 6 is a block diagram of a memory testing apparatus according to an exemplary embodiment.
  • the apparatus shown in FIG. 6 can be applied, for example, to the system 10 described above.
  • the apparatus 60 may include a test preparation module 602 and a test running module 604 .
  • the test preparation module 602 may be configured to obtain the accessible space of the central processing unit of the memory to be tested; and obtain the accessible space of the graphics processor of the memory to be tested.
  • the test running module 604 can be configured to drive the central processing unit to run the test program based on the accessible space of the central processing unit, so as to access the memory to be tested through the memory bus to be tested, wherein the central processing unit controls the graphics when running the test program
  • the processor accesses the memory under test through the memory bus under test based on the accessible space of the graphics processor.
  • test running module 604 can also be configured to drive the central processing unit and the graphics processor to access the memory to be tested through the memory bus to be tested in series.
  • the memory bus under test is an Advanced Extensible Interface Protocol bus including predetermined transmission channels.
  • test running module 604 may also be configured to drive the central processing unit and the graphics processing unit to serially access the memory to be tested through a predetermined transmission channel according to the test program.
  • the test running module 604 can also be configured to drive the central processing unit to control the graphics processor based on an open programming language to access the memory to be tested in a predetermined access manner according to the test program.
  • test running module 604 can also be configured for the central processing unit to control the graphics processor to access the memory to be tested in a predetermined access manner according to the test program through an open graphic program interface.
  • the memory to be tested is, for example, a low-power internal memory.
  • the test running module 604 can also be configured to drive the central processing unit to access the low-power internal memory via the memory controller through the memory bus to be tested; when the central processing unit runs the test program, it controls the graphics processor to pass the memory bus to be tested. Access low-power internal memory via the memory controller.
  • FIG. 7 shows a schematic structural diagram of an electronic device in an embodiment of the present disclosure.
  • the device shown in FIG. 7 is only an example of a computer system, which should not impose any limitations on the functions and scope of use of the embodiments of the present disclosure.
  • the apparatus 700 includes a central processing unit (CPU) 701 that can operate according to a program stored in a read only memory (ROM) 702 or a program loaded from a storage section 708 into a random access memory (RAM) 703 Various suitable actions and processes are performed, eg, a test program may be executed to test the connected LPDDR.
  • a graphics processing unit (GPU) 712 may also be included, and the CPU 701 may control the GPU to test the connected memory.
  • various programs and data necessary for the operation of the device 700 are also stored.
  • the CPU 701, the ROM 702, and the RAM 703 are connected to each other through a bus 704.
  • An input/output (I/O) interface 705 is also connected to bus 704 .
  • CPU 701, ROM 702, RAM 703, I/O 705, GPU 712, etc. can be integrated on the Soc as required.
  • an input section 706 including a keyboard, a mouse, etc.
  • an output section 707 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.
  • a storage section 708 of a hard disk, etc. and a communication section 709 including a network interface card such as a LAN card, a modem, and the like.
  • the communication section 709 performs communication processing via a network such as the Internet.
  • a drive 710 is also connected to the I/O interface 705 as needed.
  • a removable medium 711 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is mounted on the drive 710 as needed so that a computer program read therefrom is installed into the storage section 708 as needed.
  • embodiments of the present disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code arranged to perform the method illustrated in the flowchart.
  • the computer program may be downloaded and installed from the network via the communication portion 709 and/or installed from the removable medium 711 .
  • the central processing unit (CPU) 701 the above-described functions defined in the system of the present disclosure are executed.
  • the computer-readable medium shown in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium, or any combination of the above two.
  • the computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or a combination of any of the above. More specific examples of computer readable storage media may include, but are not limited to, electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read only memory (ROM), erasable Programmable read only memory (EPROM or flash memory), fiber optics, portable compact disk read only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
  • a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.
  • a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code therein. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing.
  • a computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can transmit, propagate or transport a program arranged for use by or in connection with the instruction execution system, apparatus or device .
  • Program code embodied on a computer readable medium may be transmitted using any suitable medium including, but not limited to, wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
  • each block in the flowchart or block diagrams may represent a module, segment, or portion of code that contains one or more logical functions arranged to implement the specified functions executable instructions.
  • the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.
  • the modules involved in the embodiments of the present disclosure may be implemented in software or hardware.
  • the described modules can also be provided in the processor, for example, it can be described as: a processor includes a test preparation module and a test running module. Wherein, the names of these modules do not constitute a limitation of the module itself under certain circumstances, for example, the test preparation module can also be described as "a module that obtains memory allocation parameters from the connected terminal".
  • the present disclosure also provides a computer-readable medium.
  • the computer-readable medium may be included in the device described in the above-mentioned embodiments, or it may exist alone without being assembled into the device.
  • the above-mentioned computer-readable medium carries one or more programs, and when the above-mentioned one or more programs are executed by a device, the device includes: acquiring the accessible space of the central processing unit of the memory to be tested; acquiring the graphics of the memory to be tested The accessible space of the processor; driving the central processing unit to run the test program based on the accessible space of the central processing unit, so as to access the memory to be tested through the memory bus to be tested, wherein, when the central processing unit runs the test program, the central processing unit controls the graphics processor based on the availability of the graphics processor.
  • the access space accesses the memory to be tested through the memory bus to be tested.
  • the present disclosure discloses a memory testing method, apparatus, device, and storage medium.
  • the method implements a stress test with a high access load on the memory, and enhances the effect of the memory test.

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Abstract

本公开公布一种存储器测试方法、装置、设备及存储介质。该方法包括：获取待测试存储器的中央处理器可访问空间；获取待测试存储器的图形处理器可访问空间；驱动中央处理器基于中央处理器可访问空间运行测试程序，以通过待测试存储器总线访问待测试存储器，中央处理器运行测试程序时控制图形处理器基于图形处理器可访问空间通过待测试存储器总线访问待测试存储器。

Description

存储器测试方法、装置、设备及存储介质
本公开基于申请号为202011110688.0，申请日为2020年10月16日，申请名称为“存储器测试方法、装置、设备及存储介质”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种存储器测试方法、装置、设备及存储介质。
背景技术
随着半导体工艺尺寸不断缩小，集成电流设计的规模越来越大，高度复杂的集成电路产品正面临着高可靠性、高质量等日益严峻的挑战。动态随机存取存储器(Dynamic Random Access Memory，DRAM))是与中央处理器(Central Processing Unit，CPU)直接交换数据的内部存储器，它可以随时读写，例如低功耗双倍数据速率同步动态随机存取存储器(Low Power Double Data Rate SDRAM，LPDDR)常常用于手机、平板电脑等一些手持的设备中的片上系统(System-on-a-chip，SoC)，所以对LPDDR等存储器的系统级的压力测试就显得十分重要。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种存储器测试、装置、设备及可读存储介质，以提高存储器压力测试的负载度。
根据本公开的第一方面，提供一种存储器测试方法，包括：获取待测试存储器的中央处理器可访问空间；获取所述待测试存储器的图形处理器可访问空间；驱动所述中央处理器基于所述中央处理器可访问空间运行测试程序，以通过待测试存储器总线访问所述待测试存储器；其中，所述中央处理器运 行所述测试程序时控制所述图形处理器基于所述图形处理器可访问空间通过所述待测试存储器总线访问所述待测试存储器。
根据本公开的第二方面，提供一种存储器测试系统，包括中央处理器和图形处理器，其中：所述中央处理器，设置为基于分配的中央处理器可访问容量运行测试程序以访问待测试存储器；其中，所述中央处理器运行所述测试程序时控制所述图形处理器基于分配的图形处理器可访问容量访问所述待测试存储器；所述图形处理器，设置为基于所述图形处理器可访问容量访问所述待测试存储器。
根据本公开的第三方面，提供一种存储器测试装置，包括：测试准备模块，设置为获取待测试存储器的中央处理器可访问空间；获取所述待测试存储器的图形处理器可访问空间；测试运行模块，设置为驱动所述中央处理器基于所述中央处理器可访问空间运行测试程序，以通过待测试存储器总线访问所述待测试存储器；其中，所述中央处理器运行所述测试程序时控制所述图形处理器基于所述图形处理器可访问空间通过所述待测试存储器总线访问所述待测试存储器。
根据本公开的第四方面，提供一种设备，包括：存储器、处理器及存储在所述存储器中并可在所述处理器中运行的可执行指令，所述处理器执行所述可执行指令时实现如上述存储器测试方法。
根据本公开的第五方面，提供一种计算机可读存储介质，其上存储有计算机可执行指令，所述可执行指令被处理器执行时实现如上述存储器测试方法。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性的，并不能限制本公开。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提 下，可以根据这些附图获得其他的附图。
图1示出本公开实施例中一种系统结构的示意图。
图2示出本公开实施例中一种存储器测试方法的流程图。
图3示出本公开实施例中另一种存储器测试方法的流程图。
图4根据图1至图3示出的一种存储器测试流程图。
图5根据一示例性实施例示出的一种存储器测试实现平台架构图。
图6是根据一示例性实施例示出的一种存储器测试装置的框图。
图7示出本公开实施例中一种电子设备的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在系统段对LPDDR的测试可例如分成三个层面，第一个层面例如是在SoC上的内存控制器中包括的内存内建自我测试(Memory build-in self test，Mbist)的模块，Mbist能够对内存做一些状态级测试，是对DRAM的测试是SoC本身固化的，可配置性比较差。第二个层面例如是通用操作系统装载器(Universal Boot loader，Uboot)层面，在这个层面的测试软件的可扩展性较好，可以测试的全部的存储器阵列空间，但是这样的测试一般需要SoC的原厂支持以及SoC厂商的开发度，而且由于运行在SoC上，其处理速度受限于SoC的静态随机存取存储器(Static Random-Access Memory，SRAM)的大小。第三个层面例如是在Android(安卓)/Linux系统基类(base)的测试，这个层面的测试更接近用户的适用方式，测试软件的可扩展性和多样性非常好，但无法覆盖整个内存空间，因为Android/Linux系统本身就需要占用一大部分的内存空间。
相关Android/Linux base的压力测试可以有两种，一种例如是在Android本地(native)层做测试，另一种例如是采用如3Dmark的图像软件做测试。 这两种软件测试方法都存在一定的缺陷，native层的测试的输入输出(IO)访问无法做到满载，而3Dmark软件本身是用来对图形处理器(Graphics Processing Unit，GPU)做测试的，而不是设置为对内存进行测试，因此无法实现相关的存储器测试算法，并且内存IO访问同样无法做到满载。
本公开提供了一种存储器测试方法，通过驱动中央处理器基于中央处理器可访问空间运行测试程序，以通过待测试存储器总线访问所述待测试存储器，中央处理器运行测试程序时控制图形处理器基于图形处理器可访问空间通过该待测试存储器总线访问待测试存储器，从而可实现对存储器进行访问负载度较高的压力测试，增强存储器测试的效果。
图1示出了可以应用本公开的存储器测试方法或存储器测试装置的示例性系统架构10。
如图1所示，系统架构10可以包括中央处理器(CPU)102和图形处理器(GPU)104，还可包括存储器总线106和存储器控制器108。下面对系统架构10的各个部分进行说明。
如图1所示，中央处理器102，可设置为基于分配的中央处理器可访问容量运行测试程序以访问待测试存储器，其中，中央处理器运行测试程序时控制图形处理器104基于分配的图形处理器可访问容量访问待测试存储器。通过CPU进行存储器(如内存)测试方法是采用直接访问存储器的方式进行的测试，整个测试程序可直接运行在CPU上。CPU可通过开放式图形程序(Open Graphics Library，OpenGL)或开放式编程语言(Open Computing Language，OpenCL)的通用接口去操作GPU，CPU运行的测试代码使用这种通用接口去控制GPU访问内存，将CPU的内存测试模式(pattern)转化成为GPU的图像处理逻辑，使GPU的测试pattern和CPU保持一致。
在一些实施例中，例如，CPU测试的项目可分成三个方面，第一个方面例如是阵列(array)方面的测试，第二个方面例如是IO上的测试，第三个方面例如是状态切换的测试。阵列的测试主要是针对array是否存在一些硬件错误(hard fail)，例如检测是否发生字节跳变(bit flip)等。IO方面的测试可例如分为两种，第一种例如是命令模式(Command line)的压力测试，例如检测是否发生输入输出地址跳变等；第二种例如是数据总线模式(DQ bus line)的压力测试，例如检测是否发生发送数据跳变等等。DQ bus line的测试 是主要的压力测试的项目。状态切换测试可分为两种测试项目，第一种例如是切换等待(suspend)测试，第二种例如是重新启动(reboot)测试。
如图1所示，图形处理器104，可设置为基于图形处理器可访问容量访问待测试存储器。GPU内存测试方式是一种间接的测试方式，GPU本身不会去直接运行测试的代码，测试代码是运行在CPU上的，通过CPU的运行给GPU做图像处理的指令，GPU就会去访问内存去做相关的操作。
如图1所示，存储器总线106，中央处理器102通过待测试存储器总线106经由内存控制器访问低功耗内部存储器；图形处理器104通过待测试存储器总线106经由内存控制器访问低功耗内部存储器。无论是GPU还是CPU单独去访问内存，都存在总线分配的问题，即会为对方预留一部分，无法把存储器总线106占满。GPU和CPU联合测试方式可使对内存测试的压力达到最大值。
如图1所示，存储器控制器108，存储器控制器108例如可为内存控制器，设置为CPU和/或GPU与待测试内存之间的数据交换，可通过其获取其控制的内存的最大内存容量、内存类型和速度、数据宽度等。对不同代、型号的DDR内存可采用通用的内存控制器，例如，待测试存储器为低功耗内部存储器(LPDDR)时，可采用增强型通用DDR内存控制器。
图2是根据一示例性实施例示出的一种存储器测试方法的流程图。如图2所示的方法例如可以应用于上述系统10。
如图2所示，本公开实施例提供的方法20可以包括以下步骤。
如图2所示，在步骤S202中，获取待测试存储器的中央处理器可访问空间。存储器可包括内部存储器和外部存储器，内部存储器可包括寄存器、高速缓冲存储器和主存储器(通常称其为内存)，外部存储器可包括硬盘、软盘、光盘等等。内部存储器的容量小、速度快，通常设置为暂时存放当前正在执行的数据和程序；外部存储器的容量大、速度慢，通常设置为长期或永久存放数据和程序。本公开中的测试方法可用于各种存储器，在此不作限制。
如图2所示，在步骤S204中，获取待测试存储器的图形处理器可访问空间。
在一些实施例中，例如，当待测试存储器为内存时，在运行测试程序前，可获取内存信息，如可通过的地址、数据量、速率等等，分别为CPU和GPU 分配内存，分别设置CPU和GPU可访问获取待测试存储器的容量和地址。可根据待测试存储器的容量获得CPU可访问容量，根据待测试存储器的容量获得GPU可访问容量，并可分别分配了对应的内存的地址。
如图2所示，在步骤S206中，驱动中央处理器基于中央处理器可访问空间运行测试程序，以通过待测试存储器总线访问待测试存储器，其中，中央处理器运行测试程序时控制图形处理器基于图形处理器可访问空间通过待测试存储器总线访问待测试存储器。可通过转换接口将CPU的地址访问方式转换为GPU的DMA(Direct Memory Access，直接内存访问)映射的大块地址访问方式，以实现测试逻辑的转换。
在一些实施例中，例如，中央处理器基于开放式编程语言控制图形处理器根据测试程序以预定访问方式访问待测试存储器。CPU可基于OpenCL控制GPU根据测试程序以预定访问方式访问待测试存储器。OpenCL是一个异构并行计算平台编写程序的工作标准，可将异构计算映射到CPU、GPU、FPGA(Field Programmable Gate Array，现场可编程门阵列)等计算设备。OpenCL提供了底层硬件结构的抽象模型，可提供一个通用的开发应用程序接口。可通过OpenCL编写在GPU上运行的通用计算程序，而无需将其算法映射到OpenGL或DirectX等3D图形的应用程序接口上。
在另一些实施例中，例如，中央处理器可通过开放式图形程序接口CPU或者可通过OpenGL接口控制GPU根据测试程序以预定访问方式访问待测试存储器。OpenGL是一种图形应用程序编程接口，包括可以对图像硬件设备如GPU等进行访问的软件库，可以在多种不同的图形硬件系统上，完全通过软件的方式实现OpenGL的接口。GPU的硬件开发商需要提供满足OpenGL规范的实现，这些实现通常被称为“驱动”，设置为将OpenGL定义的应用程序接口命令翻译为GPU指令。
根据本公开实施例提供的方法，通过使用CPU和GPU同时访问内存进行压力测试的方式，尽可能充分占用待测试存储器的总线，从而可实现对存储器进行访问负载度较高的压力测试，增强存储器测试的效果。
图3是根据一示例性实施例示出的另一种存储器测试方法的流程图。如图3所示的方法例如可以应用于上述系统10。
如图3所示，本公开实施例提供的方法30可以包括以下步骤。
如图3所示，在步骤S302中，获取待测试存储器的中央处理器可访问空间。
如图3所示，在步骤S304中，获取待测试存储器的图形处理器可访问空间。
步骤S302和S304的一些具体实施方式可参照步骤S202和S204，此处不再赘述。
如图3所示，在步骤S306中，驱动中央处理器基于中央处理器可访问空间运行测试程序，以通过待测试存储器总线访问待测试存储器，其中，中央处理器运行测试程序时控制图形处理器基于图形处理器可访问空间通过待测试存储器总线访问待测试存储器，中央处理器与图形处理器串行通过待测试存储器总线访问待测试存储器。待测试存储器总线例如可为包括预定传输通道的高级可扩展接口协议总线，中央处理器与图形处理器根据测试程序串行通过预定传输通道访问待测试存储器。
在一些实施例中，例如，高级可扩展接口协议(Advanced eXtensible Interface，AXI)总线包括5个独立的传输通道，即读地址通道、读数据通道、写地址通道、写数据通道和写回复通道。CPU、GPU通过AXI总线访问如LPDDR等内存时，通过串行的方式进行访问，即在一个传输通道上的按照时序依次进行传输。在内存芯片进行固件配置时，可能会为CPU、GPU各自预留一部分，即如果通过CPU或GPU分别访问内存进行测试，会剩余一部分总线未被占用。通过CPU、GPU同时给各自的内存空间发读写以同时访问内存的方式，可将AXI总线时钟占满，以使对内存的IO测试最大化。
根据本公开实施例提供的方法，通过使用CPU和GPU同时访问内存进行压力测试的方式，将待测试存储器的总线尽可能占满，从而可实现对存储器压力测试最大化，增强存储器测试的效果。
图4是根据图1至图3示出的一种存储器测试流程图。如图4所示，流程开始后(S402)，首先获取存储器的相关信息(S404)，然后根据存储器信息为CPU分配内存空间(S406)，并为GPU分配内存空间(S408)；内存分配完成后，触发CPU和GPU的联合测试(S410)，然后检查测试结果(S412)，测试结果表示测试完成后，进行下一个存储器的测试(S414)，返回S402步骤。
图5是根据一示例性实施例示出的一种存储器测试实现平台架构图。如图5所示，以Android base为例，可使用Android应用程序(Application,APP)去调用本地(native)层的驱动的方式去实现内存测试。整体实现分成了三个部分，第一个部分是Android的应用层的主控应用程序502，这个部分是整个测试的总控的地方。第二部分是实现GPU的测试程序的转换，GPU测试转换508将CPU的测试模式使用OpenCL接口510转化成GPU的操作流程。第三部分是CPU测试引擎506运行CPU本身的测试程序，由于第二部分和第三部分都在Android的native层，这两部分都需要外部接口给到第一部分的主控去调用，主控应用程序502通过相关的应用程序接口去控制第二部分和第三部分去做相关的操作。native层还可包括配置文件504、记录引擎512等，由于调试和测试结果保留需要，测试需要保存测试的记录(log)，可通过记录引擎512将log保留在Android的/data文件中。
图5中的实现需要有Android的根用户(root)权限才可以实现，并打开开发者模式。
如图5所示，以Linux base为例，可以直接使用Linux APP去访问虚拟地址空间，采用内核层的Linux页面映射516的页面锁(page lock)的方式去测试，也可以使用APP去调用内核层的Linux底层驱动(kernel mode drive)514去完成对内存的测试。
图6是根据一示例性实施例示出的一种存储器测试装置的框图。如图6所示的装置例如可以应用于中上述系统10。
如图6所示，本公开实施例提供的装置60可以包括测试准备模块602和测试运行模块604。
如图6所示，测试准备模块602可设置为获取待测试存储器的中央处理器可访问空间；获取待测试存储器的图形处理器可访问空间。
如图6所示，测试运行模块604可设置为驱动中央处理器基于中央处理器可访问空间运行测试程序，以通过待测试存储器总线访问待测试存储器，其中，中央处理器运行测试程序时控制图形处理器基于图形处理器可访问空间通过待测试存储器总线访问待测试存储器。
如图6所示，测试运行模块604还可设置为驱动中央处理器与图形处理器串行通过待测试存储器总线访问待测试存储器。待测试存储器总线为包括 预定传输通道的高级可扩展接口协议总线。
如图6所示，测试运行模块604还可设置为驱动中央处理器与图形处理器根据测试程序串行通过预定传输通道访问待测试存储器。
如图6所示，测试运行模块604还可设置为驱动中央处理器基于开放式编程语言控制图形处理器根据测试程序以预定访问方式访问待测试存储器。
如图6所示，测试运行模块604还可设置为中央处理器通过开放式图形程序接口控制图形处理器根据测试程序以预定访问方式访问待测试存储器。
待测试存储器例如为低功耗内部存储器。
如图6所示，测试运行模块604还可设置为驱动中央处理器通过待测试存储器总线经由内存控制器访问低功耗内部存储器；中央处理器运行测试程序时控制图形处理器通过待测试存储器总线经由内存控制器访问低功耗内部存储器。
本公开实施例提供的装置中的各个模块的具体实现可以参照上述方法中的内容，此处不再赘述。
图7示出本公开实施例中一种电子设备的结构示意图。其中，图7示出的设备仅以计算机系统为示例，不应对本公开实施例的功能和使用范围带来任何限制。
如图7所示，设备700包括中央处理器(CPU)701，其可以根据存储在只读存储器(ROM)702中的程序或者从存储部分708加载到随机访问存储器(RAM)703中的程序而执行各种适当的动作和处理，例如可执行测试程序以对连接的LPDDR进行测试。还可包括图形处理器(GPU)712，CPU 701可控制GPU对所连接的存储器进行测试。在RAM 703中，还存储有设备700操作所需的各种程序和数据。CPU 701、ROM 702以及RAM 703通过总线704彼此相连。输入/输出(I/O)接口705也连接至总线704。CPU 701、ROM 702、RAM 703、I/O 705和GPU 712等可根据需要集成在Soc上。
如图7所示，以下部件连接至I/O接口705：包括键盘、鼠标等的输入部分706；包括诸如阴极射线管(CRT)、液晶显示器(LCD)等以及扬声器等的输出部分707；包括硬盘等的存储部分708；以及包括诸如LAN卡、调制解调器等的网络接口卡的通信部分709。通信部分709经由诸如因特网的网络执行通信处理。驱动器710也根据需要连接至I/O接口705。可拆卸介质 711，诸如磁盘、光盘、磁光盘、半导体存储器等等，根据需要安装在驱动器710上，以便于从其上读出的计算机程序根据需要被安装入存储部分708。
如图7所示，根据本公开的实施例，上文参考流程图描述的过程可以被实现为计算机软件程序。例如，本公开的实施例包括一种计算机程序产品，其包括承载在计算机可读介质上的计算机程序，该计算机程序包含设置为执行流程图所示的方法的程序代码。在这样的实施例中，该计算机程序可以通过通信部分709从网络上被下载和安装，和/或从可拆卸介质711被安装。在该计算机程序被中央处理器(CPU)701执行时，执行本公开的系统中限定的上述功能。
其中，本公开所示的计算机可读介质可以是计算机可读信号介质或者计算机可读存储介质或者是上述两者的任意组合。计算机可读存储介质例如可以是——但不限于——电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。计算机可读存储介质的更具体的例子可以包括但不限于：具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、随机访问存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑磁盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。在本公开中，计算机可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。而在本公开中，计算机可读的信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了计算机可读的程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。计算机可读的信号介质还可以是计算机可读存储介质以外的任何计算机可读介质，该计算机可读介质可以发送、传播或者传输设置为由指令执行系统、装置或者器件使用或者与其结合使用的程序。计算机可读介质上包含的程序代码可以用任何适当的介质传输，包括但不限于：无线、电线、光缆、RF等等，或者上述的任意合适的组合。
附图中的流程图和框图，图示了按照本公开各种实施例的系统、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段、或代码的一部分，上述模块、 程序段、或代码的一部分包含一个或多个设置为实现规定的逻辑功能的可执行指令。也应当注意，在有些作为替换的实现中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个接连地表示的方框实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。也要注意的是，框图或流程图中的每个方框、以及框图或流程图中的方框的组合，可以用执行规定的功能或操作的专用的基于硬件的系统来实现，或者可以用专用硬件与计算机指令的组合来实现。
描述于本公开实施例中所涉及到的模块可以通过软件的方式实现，也可以通过硬件的方式来实现。所描述的模块也可以设置在处理器中，例如，可以描述为：一种处理器包括测试准备模块和测试运行模块。其中，这些模块的名称在某种情况下并不构成对该模块本身的限定，例如，测试准备模块还可以被描述为“向所连接的终端获取存储器分配参数的模块”。
作为另一方面，本公开还提供了一种计算机可读介质，该计算机可读介质可以是上述实施例中描述的设备中所包含的；也可以是单独存在，而未装配入该设备中。上述计算机可读介质承载有一个或者多个程序，当上述一个或者多个程序被一个该设备执行时，使得该设备包括：获取待测试存储器的中央处理器可访问空间；获取待测试存储器的图形处理器可访问空间；驱动中央处理器基于中央处理器可访问空间运行测试程序，以通过待测试存储器总线访问待测试存储器，其中，中央处理器运行测试程序时控制图形处理器基于图形处理器可访问空间通过待测试存储器总线访问待测试存储器。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化 描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开公布一种存储器测试方法、装置、设备及存储介质。该方法实现了对存储器进行访问负载度较高的压力测试，增强存储器测试的效果。

Claims (10)

  1. 一种存储器测试方法，包括：
    获取待测试存储器的中央处理器可访问空间；
    获取所述待测试存储器的图形处理器可访问空间；
    驱动所述中央处理器基于所述中央处理器可访问空间运行测试程序，以通过待测试存储器总线访问所述待测试存储器；
    其中，所述中央处理器运行所述测试程序时控制所述图形处理器基于所述图形处理器可访问空间通过所述待测试存储器总线访问所述待测试存储器。
  2. 根据权利要求1所述的方法，其中，所述中央处理器运行所述测试程序时控制所述图形处理器基于所述图形处理器可访问空间通过所述待测试存储器总线访问所述待测试存储器包括：
    所述中央处理器与所述图形处理器串行通过所述待测试存储器总线访问所述待测试存储器。
  3. 根据权利要求2所述的方法，其中，所述待测试存储器总线为包括预定传输通道的高级可扩展接口协议总线；
    所述中央处理器与所述图形处理器串行通过所述待测试存储器总线访问所述待测试存储器包括：
    所述中央处理器与所述图形处理器根据所述测试程序串行通过所述预定传输通道访问所述待测试存储器。
  4. 根据权利要求1所述的方法，其中，所述中央处理器运行所述测试程序时控制所述图形处理器基于所述图形处理器可访问空间通过所述待测试存储器总线访问所述待测试存储器包括：
    所述中央处理器基于开放式编程语言控制所述图形处理器根据所述测试程序以预定访问方式访问所述待测试存储器。
  5. 根据权利要求1所述的方法，其中，所述中央处理器运行所述测试程序时控制所述图形处理器基于所述图形处理器可访问空间通过所述待测试存储器总线访问所述待测试存储器包括：
    所述中央处理器通过开放式图形程序接口控制所述图形处理器根据所述 测试程序以预定访问方式访问所述待测试存储器。
  6. 根据权利要求1至5中任意一项所述的方法，其中，所述待测试存储器包括低功耗内部存储器；
    所述通过待测试存储器总线访问所述待测试存储器包括：
    所述中央处理器通过所述待测试存储器总线经由内存控制器访问所述低功耗内部存储器；
    所述中央处理器运行所述测试程序时控制所述图形处理器基于所述图形处理器可访问空间通过所述待测试存储器总线访问所述待测试存储器包括：
    所述图形处理器通过所述待测试存储器总线经由所述内存控制器访问所述低功耗内部存储器。
  7. 一种存储器测试系统，包括中央处理器和图形处理器，其中：
    所述中央处理器，设置为基于分配的中央处理器可访问容量运行测试程序以访问待测试存储器；其中，所述中央处理器运行所述测试程序时控制所述图形处理器基于分配的图形处理器可访问容量访问所述待测试存储器；
    所述图形处理器，设置为基于所述图形处理器可访问容量访问所述待测试存储器。
  8. 一种存储器测试装置，包括：
    测试准备模块，设置为获取待测试存储器的中央处理器可访问空间；获取所述待测试存储器的图形处理器可访问空间；
    测试运行模块，设置为驱动所述中央处理器基于所述中央处理器可访问空间运行测试程序，以通过待测试存储器总线访问所述待测试存储器；
    其中，所述中央处理器运行所述测试程序时控制所述图形处理器基于所述图形处理器可访问空间通过所述待测试存储器总线访问所述待测试存储器。
  9. 一种设备，包括：存储器、处理器及存储在所述存储器中并可在所述处理器中运行的可执行指令，所述处理器执行所述可执行指令时实现如权利要求1-6任一项所述的方法。
  10. 一种计算机可读存储介质，其上存储有计算机可执行指令，所述可执行指令被处理器执行时实现如权利要求1-6任一项所述的方法。
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