WO2022068618A1 - 一种带精度的量子除法运算方法及装置 - Google Patents

一种带精度的量子除法运算方法及装置 Download PDF

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WO2022068618A1
WO2022068618A1 PCT/CN2021/119125 CN2021119125W WO2022068618A1 WO 2022068618 A1 WO2022068618 A1 WO 2022068618A1 CN 2021119125 W CN2021119125 W CN 2021119125W WO 2022068618 A1 WO2022068618 A1 WO 2022068618A1
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quantum state
quantum
target
bit
module
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PCT/CN2021/119125
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English (en)
French (fr)
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李叶
窦猛汉
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合肥本源量子计算科技有限责任公司
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Priority claimed from CN202011058756.3A external-priority patent/CN112162723B/zh
Priority claimed from CN202011058718.8A external-priority patent/CN112114776B/zh
Priority claimed from CN202011059513.1A external-priority patent/CN112162724B/zh
Priority claimed from CN202011064018.XA external-priority patent/CN112162725B/zh
Priority claimed from CN202011058770.3A external-priority patent/CN112214200B/zh
Application filed by 合肥本源量子计算科技有限责任公司 filed Critical 合肥本源量子计算科技有限责任公司
Priority to EP21874279.9A priority Critical patent/EP4224308A1/en
Priority to US18/029,558 priority patent/US12086569B2/en
Publication of WO2022068618A1 publication Critical patent/WO2022068618A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/535—Dividing only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/4824—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices using signed-digit representation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/20—Models of quantum computing, e.g. quantum circuits or universal quantum computers

Definitions

  • the invention belongs to the field of quantum computing, in particular to a quantum division operation method and device with precision.
  • Quantum computers take advantage of the superposition of quantum, and theoretically have the ability to accelerate exponentially in certain situations. For example, it takes hundreds of years to crack an RSA key on a classical computer, but only a few hours to execute a quantum algorithm on a quantum computer.
  • the current quantum computer is limited by the limited number of controllable bits caused by the development of quantum chip hardware, so the computing power is limited, and quantum algorithms cannot be generally run. Running quantum algorithms universally often requires the use of quantum computing simulation methods.
  • the purpose of the present invention is to provide a quantum division operation method and device with precision, so as to solve the deficiencies in the prior art, which can fill the blank of the relevant technology and be used for realizing basic arithmetic operation in quantum circuits.
  • An embodiment of the present invention provides a quantum division operation method with precision.
  • the method includes: acquiring dividend data and divisor data to be calculated, converting the dividend data into a first target quantum state, and converting the dividend data into a first target quantum state. Converting into a second target quantum state; wherein, the target quantum state includes: a symbol bit sub-quantum state representing the data symbol and a numerical bit sub-quantum state representing the data value; for the first target quantum state and the second The target quantum state, iteratively executes the quantum state evolution corresponding to the subtraction operation, and counts the execution times of the subtraction operation until the dividend data is reduced to a negative number, and the finally obtained counting result is used as the dividend data and all
  • the integer bits of the quotient of the division of the divisor data are output; wherein, the minuend of the subtraction operation performed each time is the subtraction result of the subtraction operation performed last time, and the subtrahend is the divisor data; the current first target quantum state and For the current second target quantum state,
  • the quantum state evolution corresponding to the subtraction operation is iteratively performed for the first target quantum state and the second target quantum state, and the number of times of execution of the subtraction operation is counted until the dividend is calculated.
  • Subtracting the data to a negative number includes: performing the quantum state evolution corresponding to the subtraction operation on the current first target quantum state and the second target quantum state, so as to obtain the first target quantum state including the result of the subtraction operation; Set the third target quantum state of the auxiliary bit and the fourth target quantum state of the current second preset auxiliary bit, and perform the quantum state evolution corresponding to the subtraction operation to add 1 to the value contained in the current third target quantum state;
  • the initial value contained in the third target quantum state and the value contained in the fourth target quantum state are both -1; measure the sign bit sub quantum state of the first target quantum state that currently contains the subtraction result, and judge that the current contains the subtraction result Whether the value of the sign bit of the first target quantum state of For the current second target quantum state, the steps of quantum state evolution corresponding
  • the outputting the finally obtained counting result as the integer bits of the quotient of dividing the dividend data and the divisor data includes: outputting the finally obtained third target quantum state, wherein the The third target quantum state contains an integer-bit binary value whose value is the quotient of the division of the dividend data by the divisor data.
  • the quantum state evolution corresponding to the decimal place operation of the quotient including: converting the sign bit of the current second target quantum state into a quantum state. Negate, perform the quantum state evolution corresponding to the subtraction operation on the second target quantum state after the current first target quantum state and the sign bit are inverted, so as to evolve the current first target quantum state to include the dividend data and the The quantum state of the binary value of the remainder of the division of the divisor data; shift the quantum states of the current first target quantum state to the left by one bit, invert the sign bit quantum state of the current second target quantum state, and shift the quantum state of the current second target quantum state to the left by one
  • the first target quantum state after the bit and the second target quantum state after the inversion iteratively execute the quantum state evolution corresponding to the subtraction operation, and count the execution times of the subtraction operation until the left shift is performed by one bit
  • the first target quantum state is reduced to a negative number, a fraction
  • the method further includes: acquiring a preset sign bit qubit, and for the qubit corresponding to the sign bit sub-quantum state of the first target quantum state and the sign bit sub-quantum state corresponding to the second target quantum state.
  • the qubit, the first preset auxiliary bit and the preset sign bit qubit perform a preset quantum logic gate operation to finally obtain the symbol value represented by the symbol bit sub-quantum state in the third target quantum state.
  • performing the evolution of the quantum state corresponding to the subtraction operation includes: for the two quantum states to be operated, respectively, as the subtracted quantum state containing the subtracted data and the subtracted quantum state containing the subtracted data, and obtaining.
  • the quantum state of the third preset auxiliary bit according to the quantum state of the sign bit in the subtracted quantum state and the quantum state of the third preset auxiliary bit, control the subtracted quantum state to perform a complement operation
  • the corresponding quantum state evolves to obtain a first complement quantum state; wherein, the first complement quantum state is a quantum state containing the complement of the minuend data; the sign bit in the subtraction quantum state is The quantum state performs the quantum state evolution of the sign bit negation response, and controls the current subtraction quantum state to perform the quantum state corresponding to the complement operation according to the negated sign bit quantum state and the quantum state of the third preset auxiliary bit.
  • the second complement quantum state is a quantum state containing the complement of the subtrahend data
  • the first complement quantum state and the second complement quantum state are code quantum state, and perform the quantum state evolution corresponding to the addition operation, so as to evolve the first complement quantum state into a fifth target including the sum of the complement of the minuend data and the complement of the subtrahend data Quantum state; according to the symbol bit sub quantum state in the fifth target quantum state and the quantum state of the third preset auxiliary bit, control the fifth target quantum state to perform the quantum state evolution corresponding to the complement operation, and obtain
  • the evolved sixth target quantum state is output as the result of the subtraction operation between the subtrahend data and the subtrahend data; wherein, the sixth target quantum state is the complement of the sum of the complements of the Quantum state; according to the sign bit quantum state in the current decrement quantum state and the quantum state of the current third preset auxiliary bit, control the current decrement quantum state to perform the quantum state evolution corresponding to the
  • the evolution includes: performing a CNOT gate operation on the first sign bit qubit corresponding to the sign bit quantum state in the subtracted quantum state and the third preset auxiliary bit, wherein the first sign bit qubit is a control bit, the third preset auxiliary bit is a controlled bit; according to the quantum state of the third preset auxiliary bit after performing the CNOT gate operation, it is controlled whether the current subtracted quantum state performs a complement operation corresponding to the quantum state evolution of ; if so, invert the non-sign bit quantum state of the current minuduced quantum state, and compare the inverted quantum state with the quantum state of the fourth preset auxiliary bit
  • Quantum state controlling the quantum state evolution corresponding to the current subtraction quantum state to perform the complement operation, including: performing the X gate operation on the second sign bit qubit corresponding to the sign bit sub-quantum state in the subtraction quantum state, to obtain The inverted sign bit sub-quantum state; the CNOT gate operation is performed on the current second sign bit qubit and the third preset auxiliary bit, wherein the second sign bit qubit is a control bit, and the third preset auxiliary bit The bit is a controlled bit; according to the current quantum state of the third preset auxiliary bit after performing the CNOT gate operation, control whether the current subtraction quantum state performs the quantum state evolution corresponding to the complement operation; The non-sign bit quantum state of the state is inverted, and the inverted quantum state and the quantum state
  • Complement quantum state otherwise, take the current subtraction quantum state as the second complement quantum state; perform the CNOT gate operation on the current second sign bit qubit and the third preset auxiliary bit to convert the third preset auxiliary bit The current quantum state is restored; wherein, the second sign bit qubit is a control bit, and the third preset auxiliary bit is a controlled bit.
  • performing the evolution of the quantum state corresponding to the addition operation includes: determining the pre-cascading module MAJ module to be cascaded and the to-be-cascaded module according to the number of qubits corresponding to the two quantum states to be calculated.
  • the number of target modules of the UMA module of the rear cascading module wherein the number of modules of the MAJ module is the same as the number of modules of the UMA module; according to the addition instruction, the MAJ module and the UMA module of the target module number are Concatenation is performed to generate a target quantum circuit corresponding to the adder; each sub-quantum state of the two quantum states to be calculated is added through the target quantum circuit to generate and output the result of the target quantum state.
  • the MAJ module is a MAJ quantum circuit
  • the UMA module is a UMA quantum circuit
  • both the MAJ quantum circuit and the UMA quantum circuit include two CNOT quantum logic gates and one TOFFOLI quantum logic gate
  • the steps further include: acquiring the two CNOT quantum logic gates and a TOFFOLI quantum logic
  • the operation qubits corresponding to the gates, the control relationship between the operation qubits, and the timing relationship between the two CNOT quantum logic gates and one TOFFOLI quantum logic gate; according to the operation qubits, the control relationship and the Timing relationship, the two CNOT quantum logic gates and one TOFFOLI quantum logic gate are constructed to generate the MAJ quantum circuit or the UMA quantum circuit, as the corresponding MAJ module or UMA module.
  • the MAJ module and the UMA module both include three input items and three output items, and the MAJ module and the UMA module of the target module number are cascaded according to the addition instruction to generate all of the target modules.
  • the step of the target quantum circuit corresponding to the adder specifically includes: according to the addition instruction, using the three output items of a MAJ cascade module as the three input items of a corresponding UMA cascade module, so as to combine the MAJ cascade module with the three input items of the UMA cascade module.
  • Corresponding UMA cascade modules are cascaded to generate a target quantum circuit corresponding to the adder, wherein the MAJ cascade module is determined by the cascade between MAJ modules of the target module number, and the UMA cascade The modules are determined by the cascade connection between the UMA modules of the target module number.
  • the three input items of the MAJ module include a carry input item and two sub-quantum state input items to be calculated
  • the three output items of the MAJ module include a carry output item and two intermediate result output items.
  • the three input items of the UMA module include a carry output item and two intermediate result output items corresponding to the MAJ module
  • the three output items of the UMA module include a result carry output item, an accumulation sum output item and a waiting
  • the addition instruction use the three output items of a MAJ cascade module as the three input items of a corresponding UMA cascade module, so as to connect the MAJ cascade module with the corresponding UMA level
  • the modules are cascaded, and the step of generating the target quantum circuit corresponding to the adder specifically includes: according to the addition instruction, the carry output item output by the previous MAJ module and the input items of the two sub-quantum states to be calculated are used as the next input items.
  • the device includes: a conversion module for acquiring dividend data and divisor data to be calculated, and converting the dividend data into a first target quantum state, converting the divisor data into a second target quantum state; wherein, the target quantum state includes: a symbol bit sub-quantum state representing the data symbol and a numerical bit sub-quantum state representing the data value; the first quantum state evolution module , used to iteratively execute the quantum state evolution corresponding to the subtraction operation for the first target quantum state and the second target quantum state, and count the number of times the subtraction operation is performed until the dividend data is reduced to Negative number, the count result finally obtained is output as the integer bit of the quotient of the division of the dividend data and the divisor data; wherein, the minuend that performs the subtraction operation each time is the subtraction result of the last time the subtraction operation is performed, The subtrahend is the data of the divisor; the second quantum state evolution module is used to iteratively execute the quantum
  • the present invention also provides an electronic device comprising a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to perform the above-mentioned steps and methods.
  • the present invention also provides a storage medium in which a computer program is stored, wherein the computer program is configured to execute the above-mentioned steps and methods when running.
  • the quantum division operation method with precision provided by the present invention obtains the dividend data and the divisor data to be calculated, converts the dividend data into a first target quantum state, and converts the divisor data into a second target quantum state.
  • the quantum state evolution corresponding to the subtraction operation is iteratively performed, and the number of times of the subtraction operation is counted until the dividend data is reduced to a negative number, and the final count result obtained, Output the integer bits as the quotient of the division of the dividend data and the divisor data.
  • the quantum state on the qubit is output with precision, so as to realize basic arithmetic operations that can be used in quantum circuits, filling the gap of related technologies.
  • FIG. 1 is a block diagram of a hardware structure of a computer terminal of a quantum addition/quantum subtraction/quantum multiplication/quantum division/quantum division with precision computing method provided by an embodiment of the present invention
  • FIG. 2 is a schematic flowchart of a quantum addition operation method provided by an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of an adder provided by the present invention.
  • Fig. 5 is the MAJ module schematic diagram provided by the present invention.
  • FIG. 6 is a schematic diagram of the MAJ module quantum circuit combination process provided by the present invention.
  • FIG. 7 is a schematic diagram of a UMA module provided by the present invention.
  • Fig. 9 is the quantum circuit schematic diagram of seeking complement operation provided by the present invention.
  • FIG. 10 is a schematic diagram of the first half quantum circuit corresponding to the subtractor provided by the present invention.
  • FIG. 11 is a schematic diagram of the second half quantum circuit corresponding to the subtractor provided by the present invention.
  • FIG. 12 is a schematic diagram of a quantum circuit corresponding to a subtractor provided by the present invention.
  • FIG. 13 is a schematic structural diagram of a quantum addition device according to an embodiment of the present invention.
  • Figure 15 is a schematic diagram of a quantum circuit for finding complement provided by the present invention.
  • FIG. 16 is a schematic diagram of a quantum circuit for seeking complement code before the addition operation provided by the present invention.
  • Fig. 17 is a schematic diagram of a quantum circuit for obtaining complement code after addition operation provided by the present invention.
  • 19 is a schematic diagram of an adder provided by an embodiment of the present invention.
  • 20 is a schematic diagram of an adder quantum circuit provided by an embodiment of the present invention.
  • FIG. 21 is a schematic diagram of a MAJ module provided by an embodiment of the present invention.
  • FIG. 22 is a schematic diagram of a MAJ module quantum circuit combination process provided by an embodiment of the present invention.
  • FIG. 23 is a schematic diagram of a UMA module provided by an embodiment of the present invention.
  • FIG. 24 is a schematic diagram of a UMA module quantum circuit combination process provided by an embodiment of the present invention.
  • FIG. 25 is a schematic structural diagram of a quantum subtraction apparatus according to an embodiment of the present invention.
  • 26 is a schematic flowchart of a quantum multiplication method according to an embodiment of the present invention.
  • FIG. 27 is a schematic diagram of a storage sign bit operation result provided by an embodiment of the present invention.
  • 29 is a schematic diagram of an adder quantum circuit provided by an embodiment of the present invention.
  • FIG. 30 is a schematic diagram of a MAJ module provided by an embodiment of the present invention.
  • FIG. 31 is a schematic diagram of a MAJ module quantum circuit combination process provided by an embodiment of the present invention.
  • FIG. 34 is a schematic structural diagram of a quantum multiplication device according to an embodiment of the present invention.
  • 35 is a schematic flowchart of a quantum division operation method provided by an embodiment of the present invention.
  • 36 is a schematic diagram of a quantum circuit of a quantum division operation method provided by an embodiment of the present invention.
  • FIG. 37 is a schematic diagram of a quantum circuit of a quantum division operation method provided by another embodiment of the present invention.
  • FIG. 38 is a schematic diagram of a quantum circuit of a complement operation provided by an embodiment of the present invention.
  • 39 is a schematic diagram of the first half of the quantum circuit corresponding to the subtractor provided by an embodiment of the present invention.
  • FIG. 40 is a schematic diagram of the second half of the quantum circuit corresponding to the subtractor provided by an embodiment of the present invention.
  • 41 is a schematic diagram of a quantum circuit corresponding to a subtractor provided by an embodiment of the present invention.
  • 43 is a schematic diagram of an adder quantum circuit provided by an embodiment of the present invention.
  • FIG. 45 is a schematic diagram of a MAJ module quantum circuit combination process provided by an embodiment of the present invention.
  • FIG. 47 is a schematic diagram of a UMA module quantum circuit combination process provided by an embodiment of the present invention.
  • FIG. 48 is a schematic structural diagram of a quantum division operation device provided by an embodiment of the present invention.
  • 49 is a schematic flowchart of a quantum division operation method with precision provided by an embodiment of the present invention.
  • 50 is a schematic diagram of a quantum circuit of a quantum division operation method with precision provided by an embodiment of the present invention.
  • 51 is a schematic diagram of a quantum circuit of a quantum division operation method with precision provided by another embodiment of the present invention.
  • Figure 52 is a schematic diagram of a quantum circuit for a complement operation provided by an embodiment of the present invention.
  • 53 is a schematic diagram of the first half of the quantum circuit corresponding to the subtractor provided by an embodiment of the present invention.
  • 55 is a schematic diagram of a quantum circuit corresponding to a subtractor provided by an embodiment of the present invention.
  • 57 is a schematic diagram of an adder quantum circuit provided by an embodiment of the present invention.
  • 58 is a schematic diagram of a MAJ module provided by an embodiment of the present invention.
  • FIG. 59 is a schematic diagram of a MAJ module quantum circuit combination process provided by an embodiment of the present invention.
  • 60 is a schematic diagram of a UMA module provided by an embodiment of the present invention.
  • FIG. 61 is a schematic diagram of a UMA module quantum circuit combination process provided by an embodiment of the present invention.
  • FIG. 62 is a schematic structural diagram of a quantum division operation device with precision provided by an embodiment of the present invention.
  • Embodiments of the present invention provide a method and device for quantum addition/quantum subtraction/quantum multiplication/quantum division/quantum division with precision, which are used to implement basic arithmetic operations of qubits in quantum circuits.
  • the method can be applied For electronic equipment, such as mobile terminals, such as mobile phones and tablet computers; such as computer terminals, such as ordinary computers, quantum computers, etc.
  • FIG. 1 is a hardware structural block diagram of a computer terminal of a quantum addition/quantum subtraction/quantum multiplication/quantum division/quantum division with precision operation method according to an embodiment of the present application.
  • the computer terminal may include one or more (only one is shown in FIG. 1 ) processor 102 (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data, optionally, the above-mentioned computer terminal may further include a transmission device 106 and an input/output device 108 for communication functions.
  • FIG. 1 is only a schematic diagram, which does not limit the structure of the above-mentioned computer terminal.
  • the computer terminal may also include more or fewer components than shown in FIG. 1 , or have a different configuration than that shown in FIG. 1 .
  • the memory 104 can be used to store software programs and modules of application software, such as program instructions/modules corresponding to the quantum computing simulation method in the embodiments of the present application. A functional application and data processing are implemented, namely, the above-mentioned method is implemented.
  • Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, memory 104 may further include memory located remotely from processor 102, which may be connected to a computer terminal through a network. Examples of such networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
  • Transmission means 106 are used to receive or transmit data via a network.
  • the specific example of the above-mentioned network may include a wireless network provided by the communication provider of the computer terminal.
  • the transmission device 106 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet.
  • the transmission device 106 may be a radio frequency (Radio Frequency, RF) module, which is used for wirelessly communicating with the Internet.
  • RF Radio Frequency
  • a real quantum computer is a hybrid structure, which consists of two parts: one part is a classical computer, which is responsible for performing classical calculations and control; the other part is a quantum device, which is responsible for running quantum programs to realize quantum computing.
  • a quantum program is a sequence of instructions written in a quantum language such as Qrunes that can run on a quantum computer, which supports the operation of quantum logic gates, and finally realizes quantum computing.
  • a quantum program is a series of instruction sequences that operate quantum logic gates in a certain sequence.
  • Quantum computing simulation is the process of realizing the simulation operation of quantum programs corresponding to specific problems by means of a virtual architecture (ie, quantum virtual machine) built with the resources of ordinary computers. Often, it is necessary to construct a quantum program corresponding to a particular problem.
  • Quantum programs referred to in the embodiments of the present invention are programs written in classical languages to characterize qubits and their evolution, wherein qubits, quantum logic gates, etc. related to quantum computing are represented by corresponding classical codes.
  • quantum circuits also known as quantum logic circuits
  • quantum logic circuits are the most commonly used general-purpose quantum computing models, representing circuits that operate on qubits under abstract concepts, including qubits, circuits (timelines) , and various quantum logic gates, the results are often read out through quantum measurement operations.
  • the wires can be regarded as connected by time, that is, the state of qubits evolves naturally with time.
  • the instruction of the Hamiltonian operator which is operated until it encounters a logic gate.
  • a quantum program as a whole corresponds to a total quantum circuit
  • the quantum program in the present invention refers to the total quantum circuit, wherein the total number of qubits in the total quantum circuit is the same as the total number of qubits in the quantum program.
  • a quantum program can be composed of quantum circuits, measurement operations for qubits in the quantum circuits, registers to save the measurement results, and control flow nodes (jump instructions).
  • a quantum circuit can contain dozens, hundreds or even thousands of them. Tens of thousands of quantum logic gate operations.
  • the execution process of a quantum program is the process of executing all quantum logic gates in a certain sequence. It should be noted that timing is the time sequence in which a single quantum logic gate is executed.
  • Quantum logic gates are the basis of quantum circuits. Quantum logic gates include single-bit quantum logic gates, such as Hadamard gates (H gates), Pauli-X gates, Pauli-Y gates, Pauli-Z gate, RX gate, RY gate, RZ gate; multi-bit quantum logic gate, such as CNOT gate, CR gate, iSWAP gate, Toffoli gate. Quantum logic gates are generally represented by a unitary matrix, and a unitary matrix is not only a matrix form, but also an operation and transformation.
  • quantum logic gates that can realize some classical operations such as four operations, for example: addition, subtraction, multiplication, and division operations. It is urgent to construct quantum circuits to realize the functional operation of any four operations, thereby promoting the development of quantum computing. development, as well as the expansion and landing of quantum applications.
  • Embodiment 1 of the present invention provides a quantum addition operation method, as shown in FIG. 2 , the method includes:
  • Any classical logic circuit can also be represented by quantum circuits.
  • quantum circuits There is a one-to-one correspondence between classical circuits and quantum circuits.
  • the input and output of a quantum logic gate/quantum circuit are both qubits, and the number of qubits in the input and output is equal.
  • Quantum circuits allow quantum states to be input in superposition, and output states can be superimposed and output in the same way.
  • Reversible computing is the basis of quantum computing, that is, any reversible circuit has an inverse circuit, that is, taking each original output as an input can just be mapped to the original input.
  • a reversible circuit means that for each output, there is exactly one input corresponding to it, and the mapping is a one-to-one mapping.
  • the NOT gate is a typical reversible logic gate, and its inverse circuit is itself.
  • Typical irreversible logic gates are AND gates and OR gates. For example, when the input of the AND gate is 0, 0; 0, 1; 1, 0, it outputs 0, which means that there is no unique mapping from output to input.
  • Reversible computation means that the information is not lost during the computation, and the original state can be restored after inverse transformation. Irreversible computation means that information is lost. For example, from the output of an AND gate, the state of the input cannot be inferred. For reversible computation, it can be deduced. Any reversible logic gate that executes continuously, together is a reversible operation. All quantum logic gates are reversible logic gates, so quantum circuits are reversible circuits. But quantum measurements are not reversible computations.
  • an addition instruction input by the user is received, and two target data to be operated corresponding to the addition instruction are obtained, and the two target data to be operated are converted into corresponding two target quantum states.
  • the decimal data to be operated can be converted into binary quantum state representation by using the existing amplitude encoding method.
  • the first addition data is 7, the signed binary represents 0111, the highest bit is 0 for positive numbers and 1 for negative numbers; the second addition data is 4, and the signed binary represents 011.
  • the target quantum state is an eigenstate corresponding to two target qubits, and the number of all eigenstate representations corresponding to the qubits is 2 to the power of the number of qubits.
  • a group of qubits is q 0 , q 1 , q 2 , representing the 0th, 1st, and 2nd qubits, and the order from high to low is q 2 q 1 q 0 , then the group of qubits
  • 111> the superposition state between the 8 eigenstates.
  • the number of qubits in this group can be set according to actual operation needs.
  • the first qubit in the line is the first preset auxiliary bit, which is initially in the
  • the a and b in the line are the quantum states corresponding to the data to be added, each corresponding to a group of qubits.
  • c represents the final carry item, corresponding to the preset carry auxiliary bit, and s is the output bit that does not contain carry.
  • the number of qubits corresponding to a and b is required to be the same, and the number of qubits of s and a and b are the same.
  • a [i] and b[i] are the i-th bits of the quantum state corresponding to the two addends, respectively, and c [i] is the previous-level carry.
  • S1202 according to the number of bits of each qubit in the target quantum state, determine the number of target modules of the pre-cascading module MAJ module to be cascaded and the post-cascade module UMA module to be cascaded, wherein the MAJ module
  • the number of modules of the module is the same as the number of modules of the UMA module
  • s a+b.
  • the first qubit that is, c 0 in the cascaded circuit above
  • Both a and b are numbers bound by a group of qubits. Generally, the number of bits of a and b is required to be the same.
  • s is the output bit without carry, and has the same number of bits as b.
  • c is the final carry term.
  • a MAJ module includes three input quantum states and three corresponding output quantum states, wherein the first quantum bit is the first preset auxiliary bit, corresponding to c 0 in the quantum circuit.
  • the first MAJ module includes three input quantum states and three corresponding output quantum states, wherein the three input quantum states are c 0 , a 0 , and b 0 respectively, and a 0 is the first quantum state to be operated. 0-bit quantum state, b 0 is the 0th-bit quantum state of the second quantum state to be operated, c 0 is the quantum state of the third preset auxiliary bit, and the initial value is 0, that is, no carry.
  • the three output quantum states are c 1 , c 1 is the carry after the addition of a 0 and b 0.
  • the three input quantum states of the next MAJ module are c 1 , a 1 , and b 1 , and the three output quantum states are respectively c 2 , and so on to the last MAJ module.
  • the first UMA module includes three input quantum states and three corresponding output quantum states, wherein the three output quantum states of the MAJ module are the three input quantum states of the corresponding UMA module, and the three output quantum states are respectively c 0 , s 0 , a 0 , s 0 is the result of the addition of a 0 and b 0 without carry. Similarly, s 1 is the result of the addition of a 1 and b 1 without carry, and so on, c 4 is the final carry item, corresponding to the preset carry auxiliary bit. It should be noted that, in practical applications, without the requirement of calculating the final carry, the quantum circuit corresponding to c 4 may not be set.
  • the number of modules of the MAJ module and the number of UMA modules can be determined according to the number of sub-quantum states contained in any quantum state to be calculated.
  • One sub-quantum state corresponds to one qubit
  • the number of modules of the MAJ module is and the same number of UMA modules. Shown in the figure is only an example, encoding a and b each requires 4 qubits, and the number of MAJ modules and UMA modules are both 4.
  • the MAJ module and the UMA module constitute the front and rear cascade units of the adder.
  • the MAJ module can be used to extract the carry term of any step and pass it to the next level to calculate the final carry term.
  • the UMA module extracts the information of c and transmits it to the upper-level UMA, also calculates the s (result item) of each level, and restores the information of a.
  • At least one MAJ module is cascaded to form a MAJ cascade module
  • at least one UMA module is cascaded to form a UMA cascade module.
  • Both the MAJ cascade module and the UMA cascade module include three input items and three output items ,
  • the step of cascading the MAJ module and the UMA module of the target module number according to the addition instruction to generate the target quantum circuit corresponding to the adder specifically includes:
  • three output items of a MAJ cascading module are used as three input items of a corresponding UMA cascading module, so that the MAJ cascading module and the corresponding UMA cascading module are cascaded to generate The target quantum circuit corresponding to the adder.
  • the three output bits of the MAJ module are used as the three input bits of the UMA module, so that the same number of MAJ modules and UMA modules are Concatenation is performed to generate the target quantum circuit corresponding to the adder.
  • the MAJ module is a MAJ quantum circuit
  • the UMA module is a UMA quantum circuit
  • both the MAJ quantum circuit and the UMA quantum circuit include two CNOT quantum logic gates and one TOFFOLI quantum logic gate
  • the control relationship and the timing relationship, the two CNOT quantum logic gates and one TOFFOLI quantum logic gate are constructed to generate the MAJ quantum circuit or the UMA quantum circuit, as the corresponding MAJ module or UMA module.
  • the MAJ module and the UMA module constitute the front and rear cascade units of the adder.
  • the MAJ module is used to extract the carry term after each level of addition operation and pass it to the next level, so as to calculate the final carry term.
  • the hollow circles in the circuit diagram represent NOT operations, and the solid circles represent control bits.
  • the UMA module is used to extract the value of the carry item c, and pass the value of the carry item c to the upper-level UMA module, calculate the sum s (result item) of each stage, and restore the value of a.
  • the MAJ module can be composed of three logic gates, namely two CNOT gates and one Toffoli gate.
  • the function of the CNOT gate (the first and second logic gates from left to right in Figure 6) is: add the control bit to the target bit to form a modulo 2 addition, which is an exclusive OR operation, and obtain (a +c)%2, so the order can be swapped.
  • Example 1 a i is 1, b i is 1, and c i is 1.
  • the MAJ module starts to add a i to ci , the value on ci becomes 0, then adds a i to bi , the value on bi also becomes 0, and finally adds bi and ci to On a i , the value of a i becomes 1, that is, the carry of c i+1 is 1.
  • Example 2 a i is 0, b i is 1, and c i is 1.
  • the MAJ module starts to add a i to c i , the value of c i becomes 1, then adds a i to b i , the value of b i also becomes 1, and finally adds b i and c i to On a i , the value of a i becomes 1, that is, the carry of c i+1 is 1.
  • the UMA module is used for the latter stage of the cascaded adder.
  • the implementation of the UMA module is similar to the MAJ module.
  • the Toffoli gate is used first (the first from left to right in Figure 8).
  • logic gates restore c i+1 to a i , and then use a i to restore (a+c)% 2 with the CNOT gate (the second logic gate from left to right in Figure 8 ), restore is c i , and finally, use c i to make a CNOT gate for (a+b)%2 (the third logic gate from left to right in FIG. 8 ) to obtain the final result s i of the current bit.
  • Example 1 (a i + ci )% 2 is 0, (a i +b i )% 2 is 0, and c i+1 is 1.
  • Example 2 (a i + ci )% 2 is 1, (a i +b i )% 2 is 1, and c i+1 is 1.
  • the last CNOT gate from top to bottom that is, the CNOT gate between the MAJ module and the UMA module of the entire adder, is used to save the result of c i+1 .
  • the three input items of the MAJ cascading module include a carry input item and two sub-quantum state input items to be calculated
  • the three output items of the MAJ cascading module include a carry output item and two intermediate Result output items
  • the three input items of the UMA cascading module include one carry output item and two intermediate result output items corresponding to the MAJ cascading module
  • the three output items of the UMA cascading module include a result carry output term, the accumulated sum output term, and an input term of the sub-quantum state to be calculated
  • the step of generating the target quantum circuit corresponding to the adder specifically includes:
  • the carry output item output by the previous MAJ module and the two sub-quantum state input items to be calculated are used as the three input items of the next MAJ module, so that the MAJ module of the target number of modules Perform cascading to generate the MAJ cascading module;
  • a CNOT quantum logic gate is added between the last MAJ cascade module and the corresponding first UMA cascade module in the initial quantum circuit, wherein the qubit corresponding to the carry output item of the MAJ cascade module is used as the control bit, using the preset carry auxiliary bit as the controlled bit to generate the target quantum circuit of the adder.
  • the CNOT gate and the carry auxiliary bit may not be set if the carry item is not required.
  • each sub-quantum state of the two target quantum states such as
  • the adder that is, the target quantum circuit
  • the quantum division operation method provided by the present invention is used to realize the basic arithmetic operation operation in the quantum circuit, obtain the dividend data and divisor data to be operated, and convert the dividend data into the first target quantum state, and the The divisor data is converted into the second target quantum state; for the first target quantum state and the second target quantum state, the quantum state evolution corresponding to the subtraction operation is iteratively performed, and the number of times the subtraction operation is performed is counted until Subtract the dividend data to a negative number; convert the finally obtained counting result as the quotient of dividing the dividend data and the divisor data into decimal representation and output, so as to realize basic arithmetic operations that can be used in quantum circuits operation, filling the gaps in related technologies.
  • Another embodiment of the present invention provides a detailed description of a specific implementation of a method for performing a subtraction operation.
  • the symbol bit sub-quantum state in the state and the quantum state of the second preset auxiliary bit control the quantum state evolution corresponding to the complement operation of the subtracted quantum state, and obtain the first complement quantum state;
  • the first's complement quantum state is a quantum state comprising the complement of the subtrahend data;
  • the two quantum states to be calculated have the following groups: the first target quantum state and the second target quantum state; the third target quantum state and the fourth target quantum state; the first target quantum state and the sign bit
  • the second target quantum state after inversion can be called the minuend quantum state
  • the data contained in the subtraction is called the minuend
  • the latter can be called the minuend quantum state
  • the data contained is the subtrahend.
  • the subtractor it is mainly used to realize the function of the subtractor.
  • the biggest difference between the subtractor and the following adder is that a negative number will be generated. Therefore, a binary processing method is used to add a sign bit to both the subtrahend and the minuend. , to indicate the positive or negative value of the value, and use two's complement for the operation.
  • the complement of positive numbers remains unchanged, and 1 is added after inversion of negative numbers except for the sign bit.
  • the sign bit is used to control whether to perform the complement operation
  • the X gate is used for inversion, and the addition of 1 can be realized by the adder. After the operation is completed in the case of complement, the target value is obtained by performing a complement operation on the result.
  • the minuend data and the subtrahend data to be calculated are acquired, and the minuend data and the subtrahend data are converted into a first target quantum state and a second target quantum state, respectively.
  • the target quantum state includes: a symbol bit sub-quantum state representing the data symbol and a numerical bit sub-quantum state representing the data value.
  • the quantum state evolution corresponding to the complement operation of the subtracted quantum state is controlled, and the subtracted quantum state can be processed
  • the first sign bit qubit and the second preset auxiliary bit corresponding to the sign bit sub-quantum state in the CNOT gate operation are performed, wherein the first sign bit qubit is the control bit, and the second preset auxiliary bit is the controlled bit; and , the CNOT gate can be replaced by other equivalent existing quantum logic gates or quantum logic gate combinations, which is also reasonable and feasible;
  • the quantum state of the second preset auxiliary bit after performing the CNOT gate operation may be
  • the CNOT gate operation is performed on the current first sign bit qubit and the second preset auxiliary bit to restore the quantum state of the current second preset auxiliary bit; wherein, the first sign bit qubit is a control bit, so The second preset auxiliary bits are controlled bits.
  • the subtracted quantum state is assumed to be
  • 0011> is the sub-quantum state of the highest bit, that is, the
  • the set quantum bit q1 is initially
  • the quantum state evolution corresponding to the complement operation is not performed on the subtracted quantum state.
  • the minuend is a positive number, there is no need for complement in the subtraction operation, or in other words, its complement is itself, and
  • the CNOT gate can be executed again on the current g.sign and q1.
  • the quantum state of the g.sign bit is
  • 0> of the controlled bit q1 remains unchanged to restore q1 is in the
  • q 1 is the second preset auxiliary bit, which is used to control whether to perform the complement operation
  • the first target quantum state is g
  • g.sign is the sign bit in the first target quantum state Quantum state
  • the remaining g is the numerical sub-quantum state representing the data value
  • j is the second preset auxiliary bit, that is, the auxiliary bit that is set to a value of 1
  • p is the auxiliary bit used by the adder (the following first preset auxiliary bits).
  • the quantum circuit shown in Figure 9 realizes the quantum circuit that performs the operation of calculating the complement of g.
  • the CNOT gate operation is performed on g.sign and q 1 , so that q 1 temporarily represents g.sign, and q 1 is used to control whether to perform the search.
  • Complement code after obtaining the complement code, restore q 1 .
  • the quantum state evolution corresponding to the complement operation is performed by controlling the subtracted quantum state, and the first complement quantum state is obtained.
  • the second preset auxiliary bit q 1 is used to control whether to perform the complementing operation. If g is negative, the complement operation of the negative number is performed. The complement of a negative number is the bitwise inversion except for the sign bit and then adding 1. If the bitwise inversion operation except for the sign bit is implemented with logic gates, it is only necessary to make X gates for all the numerical bits. 1 needs to be added. Therefore, by adding j and g, the value of j is set to 1, and p is the auxiliary bit of the adder. After adding g and j after the inversion of the value bits, what is stored on g is After taking the complemented value, restore q 1 for the next use.
  • the quantum state evolves the quantum state corresponding to the complement operation to obtain a second complement quantum state; wherein, the second complement quantum state is a quantum state comprising the complement of the subtrahend data;
  • the X gate operation can be performed on the second sign bit qubit corresponding to the sign bit quantum state in the subtraction quantum state to obtain the inverted sign bit quantum state; wherein, the X gate can use other equivalent quantum states. It is also reasonable and feasible to replace some quantum logic gates or combinations of quantum logic gates;
  • the CNOT gate operation is performed on the current second sign bit qubit and the second preset auxiliary bit to restore the current quantum state of the second preset auxiliary bit; wherein, the second sign bit qubit is a control bit, so The second preset auxiliary bits are controlled bits.
  • the decrement quantum state is assumed to be
  • 0100> is the sub-quantum state of the highest bit, that is, the
  • the X gate can be performed on h.sign, the corresponding sign bit quantum state
  • the quantum state of q1 after the CNOT gate operation is performed is
  • An implementation of the quantum state evolution corresponding to performing the complement operation is as follows:
  • 1100> can be negated by executing the X gate; in order to keep the dimensions consistent, the second preset auxiliary bits are preset 4-bit qubits m3, m2, m1, m0, The quantum state
  • the CNOT gate can be executed again on the current h.sign and q1.
  • the quantum state of the h.sign bit is
  • 1> of the controlled bit q1 is reversed as
  • Figure 10 is a schematic diagram of the quantum circuit of the quantum state evolution corresponding to performing the complement operation on g and h.
  • the second target quantum state h performs the quantum state evolution corresponding to the complement operation. , to get the second's complement quantum state.
  • the sixth target quantum state is output as the result of the subtraction operation of the minuend data and the subtrahend data; wherein, the sixth target quantum state is a quantum state that includes the complement of the sum of the complements;
  • 0> of the second preset auxiliary bit The quantum state corresponding to the code operation evolves, and the sixth target quantum state after evolution
  • the evolution of the quantum state corresponding to the complement operation can be the same as the above. After the evolution, the quantum state of the second preset auxiliary bit is still restored to
  • the current subtraction quantum state is controlled to perform the quantum state evolution corresponding to the complement operation, and the quantum state evolution corresponding to the complement operation is performed on the current subtraction quantum state.
  • the sign bit quantum state performs the quantum state evolution of the sign bit negation response to restore the current decremented quantum state.
  • the current subtraction quantum state is the second's complement quantum state
  • the current quantum state of the second preset auxiliary bit is
  • the quantum state evolution corresponding to the complement operation is further performed on the third target quantum state of the sum of the complement of the minuend data and the complement of the subtrahend data.
  • the purpose of making an X gate on j [ 0] is to set the value of j[0] to 1, which is convenient for the +1 operation in the complement.
  • the reason for doing the X gate operation on the sign bit of h is to convert gh to g+(-h).
  • Another embodiment of the present invention provides a quantum addition operation device, as shown in FIG. 13 , the device includes:
  • the operation data acquisition module 11301 is used to acquire the addition instruction and the two target data to be calculated, and convert the two target data into two target quantum states;
  • the cascade module determination module 11302 is used to determine the target module number of the front cascade module MAJ module to be cascaded and the post cascade module UMA module to be cascaded according to the number of bits of each qubit in the target quantum state. number, wherein, the number of modules of the MAJ module is the same as the number of modules of the UMA module;
  • the quantum circuit generation module 11303 is used for cascading the MAJ module and the UMA module of the target module number according to the addition instruction to generate the target quantum circuit corresponding to the adder;
  • the target quantum operation module 11304 is configured to perform an addition operation on each qubit of the two target quantum states through the target quantum circuit, and generate and output the result of the target quantum state.
  • the MAJ module is a MAJ quantum circuit
  • the UMA module is a UMA quantum circuit.
  • Both the MAJ quantum circuit and the UMA quantum circuit include two CNOT quantum logic gates and one TOFFOLI quantum logic gate. Also includes Cascade Module Preset Modules:
  • the control relationship and the timing relationship, the two CNOT quantum logic gates and one TOFFOLI quantum logic gate are constructed to generate the MAJ quantum circuit or the UMA quantum circuit, as the corresponding MAJ module or UMA module.
  • At least one MAJ module is cascaded to form a MAJ cascade module
  • at least one UMA module is cascaded to form a UMA cascade module
  • both the MAJ cascade module and the UMA cascade module include three input items and three outputs.
  • the quantum circuit generation module is also used for:
  • the step of cascading the MAJ module and the UMA module of the target module number according to the addition instruction to generate the target quantum circuit corresponding to the adder specifically includes:
  • three output items of a MAJ cascading module are used as three input items of a corresponding UMA cascading module, so that the MAJ cascading module and the corresponding UMA cascading module are cascaded to generate The target quantum circuit corresponding to the adder.
  • the three input items of the MAJ cascading module include a carry input item and two sub-quantum state input items to be calculated
  • the three output items of the MAJ cascading module include a carry output item and two intermediate Result output items
  • the three input items of the UMA cascading module include one carry output item and two intermediate result output items corresponding to the MAJ cascading module
  • the three output items of the UMA cascading module include a result carry output term, accumulation and output term, and an input term of a sub-quantum state to be calculated
  • the quantum circuit generation module is also used for:
  • the carry output item output by the previous MAJ module and the two sub-quantum state input items to be calculated are used as the three input items of the next MAJ module, so that the MAJ module of the target number of modules Perform cascading to generate the MAJ cascading module;
  • a CNOT quantum logic gate is added between the last MAJ cascade module and the corresponding first UMA cascade module in the initial quantum circuit, wherein the qubit corresponding to the carry output item of the MAJ cascade module is used as the control bit, using the preset carry auxiliary bit as the controlled bit to generate the target quantum circuit of the adder.
  • the device comprises:
  • an operation data acquisition module configured to acquire the minuend data and the subtrahend data to be calculated, convert the subtrahend data into a first target quantum state, and convert the subtrahend data into a second target quantum state;
  • the target quantum state includes: a symbol bit sub-quantum state representing the data symbol and a numerical bit sub-quantum state representing the data value;
  • the first quantum state evolution module is used to obtain the quantum state of the second preset auxiliary bit, and control the quantum state of the symbol bit sub quantum state in the first target quantum state and the quantum state of the second preset auxiliary bit.
  • the first target quantum state performs the quantum state evolution corresponding to the complement operation to obtain a first complement quantum state; wherein, the first complement quantum state is a quantum state that includes the complement of the subtrahend data;
  • the second quantum state evolution module is configured to perform the quantum state evolution of the sign bit inversion reaction for the symbol bit sub-quantum state in the second target quantum state, and according to the inverted symbol bit sub-quantum state and the second predetermined quantum state evolution Set the quantum state of the auxiliary bit, control the current second target quantum state to perform the quantum state evolution corresponding to the complement operation, and obtain the second complement quantum state; wherein, the second complement quantum state contains the subtrahend data 's complement quantum state;
  • the third quantum state evolution module is configured to perform quantum state evolution corresponding to the addition operation on the first complement quantum state and the second complement quantum state, so as to evolve the first complement quantum state into a quantum state including the third target quantum state of the sum of the complement of the minuend data and the complement of the subtrahend data;
  • the target quantum operation module is used to control the third target quantum state to perform the quantum corresponding to the complement operation according to the symbol bit sub-quantum state in the third target quantum state and the quantum state of the second preset auxiliary bit. state evolution, obtain the fourth target quantum state after evolution, and output as the result of the subtraction operation of the minuend data and the subtrahend data; wherein, the fourth target quantum state is the sum containing the complement of the code 's complement quantum state.
  • the device further comprises:
  • the restoration module is used to control the current second target quantum state to perform the quantum state evolution corresponding to the complement operation according to the symbol bit sub quantum state in the current second target quantum state and the quantum state of the current second preset auxiliary bit, and perform the corresponding quantum state evolution on the current second target quantum state.
  • the sign bit sub quantum state in the current second target quantum state performs quantum state evolution of the sign bit negation response, so as to restore the current second target quantum state.
  • the first quantum state evolution module is specifically used for:
  • the second preset auxiliary bits are controlled bits
  • the CNOT gate operation is performed on the current first sign bit qubit and the second preset auxiliary bit to restore the quantum state of the current second preset auxiliary bit; wherein, the first sign bit qubit is a control bit, so The second preset auxiliary bits are controlled bits.
  • a quantum addition operation method characterized in that the method comprises: acquiring an addition instruction and two target data to be calculated, and converting the two target data into two target quantum states; according to the target quantum states
  • the number of bits of each qubit in the qubit determines the number of target modules of the MAJ module to be cascaded and the rear cascade module UMA module to be cascaded, wherein the number of modules of the MAJ module is the same as that of the MAJ module.
  • the number of modules of the UMA module is the same; according to the addition instruction, the MAJ module and the UMA module of the target number of modules are cascaded to generate the target quantum circuit corresponding to the adder; Each qubit of each target quantum state is added to generate and output the result of the target quantum state.
  • the steps of the quantum circuit specifically include: according to the addition instruction, using three output items of a MAJ cascade module as three input items of a corresponding UMA cascade module, so as to connect the MAJ cascade module with the corresponding UMA level
  • the connecting modules are cascaded to generate the target quantum circuit corresponding to the adder.
  • the quantum addition operation method according to any one of C11-C13, wherein the three input items of the MAJ cascade module include a carry input item and two sub-quantum state input items to be calculated, so
  • the three output items of the MAJ cascading module include a carry-out item and two intermediate result output items
  • the three input items of the UMA cascading module include a carry-out item and two intermediate results corresponding to the MAJ cascading module
  • Output items the three output items of the UMA cascading module include a result carry output item, an accumulation sum output item, and an input item of a sub-quantum state to be calculated, and according to the addition instruction, the output of a MAJ cascading module is
  • the three output items are used as three input items of a corresponding UMA cascading module, so as to cascade the MAJ cascading module and the corresponding UMA cascading module, and the step of generating the target quantum circuit corresponding to the adder specifically includes: : According
  • the quantum addition operation method further comprises: acquiring the subtrahend data and the subtrahend data to be calculated, and subtracting the subtrahend data Convert the digital data into a first target quantum state, and convert the subtraction data into a second target quantum state; wherein, the target quantum state includes: a symbol bit quantum state representing the data symbol and a numerical bit representing the data value Quantum state; obtain the quantum state of the second preset auxiliary bit, and control the execution of the first target quantum state according to the symbol bit quantum state in the first target quantum state and the quantum state of the second preset auxiliary bit
  • the quantum state evolution corresponding to the complement operation is obtained, and the first complement quantum state is obtained; wherein, the first complement quantum state is a quantum state containing the complement of the minuend data; the second target quantum state is The symbol bit sub-quantum state in the state performs the corresponding quantum state evolution, and controls the current second target quantum state to perform the complement operation corresponding to the inverted
  • the quantum state evolution of obtains a second complement quantum state; wherein, the second complement quantum state is a quantum state containing the complement of the subtrahend data; for the first complement quantum state and the first complement quantum state Two's complement quantum state, performing a quantum addition operation to evolve the first complement quantum state into a third target quantum state comprising the sum of the complement of the minuend data and the complement of the subtrahend data ; According to the quantum state of the symbol bit sub-quantum in the third target quantum state and the quantum state of the second preset auxiliary bit, control the third target quantum state to perform the quantum state evolution corresponding to the complement operation, and obtain the evolution after the
  • the fourth target quantum state of is output as the result of the subtraction operation of the subtrahend data and the subtrahend data; wherein, the fourth target quantum state is a quantum state that includes the complement of the sum of the complements .
  • the quantum addition operation method according to any one of C11-C15, wherein the control of the third target quantum state to perform the quantum state evolution corresponding to the complement operation, obtains the fourth target after evolution After the quantum state step, the step further includes: controlling the current second target quantum state to perform the quantum state corresponding to the complement operation according to the symbol bit sub quantum state in the current second target quantum state and the current quantum state of the first preset auxiliary bit evolution, and perform the quantum state evolution of the sign bit anti-correspondence on the sign bit sub-quantum state in the current second target quantum state, so as to restore the current second target quantum state.
  • the step of controlling the evolution of the quantum state corresponding to the complement operation of the first target quantum state specifically includes: the first sign bit qubit corresponding to the sign bit sub-quantum state in the first target quantum state and the first sign bit qubit and the second
  • the CNOT gate operation is performed with two preset auxiliary bits, wherein the first sign bit qubit is a control bit, and the second preset auxiliary bit is a controlled bit; according to the second preset after the CNOT gate operation is performed
  • the quantum state of the auxiliary bit controls whether the current first target quantum state performs the quantum state evolution corresponding to the complement calculation;
  • a quantum addition operation device characterized in that the device comprises: an operation data acquisition module for acquiring an addition instruction and two target data to be calculated, and converting the two target data into two target quantum states
  • the cascade module determination module is used to determine the target module number of the front cascade module MAJ module to be cascaded and the rear cascade module UMA module to be cascaded according to the number of digits of each quantum bit in the target quantum state
  • the number of modules of the MAJ module is the same as the number of modules of the UMA module
  • the quantum circuit generation module is used to generate the MAJ module and the UMA module of the target module number according to the addition instruction.
  • the target quantum operation module is used to perform an addition operation on each qubit of the two target quantum states through the target quantum circuit, and generate and output the result of the target quantum state .
  • An electronic device comprising a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute any one of C11-C17. method.
  • a storage medium wherein a computer program is stored in the storage medium, wherein the computer program is configured to execute the method described in any one of C11-C17 when running.
  • Yet another embodiment of the present invention provides an electronic device comprising a memory and a processor, the memory having a computer program stored therein, the processor being configured to run the computer program to perform the method steps as described above.
  • Yet another embodiment of the present invention provides a storage medium, in which a computer program is stored, the computer program being configured to execute the above method steps when executed.
  • the quantum addition operation method provided by the present invention converts the two target data into two target quantum states by acquiring the addition instruction and the two target data to be calculated;
  • the number of bits of each qubit of the The number of modules of the modules is the same; according to the addition instruction, the MAJ module and the UMA module of the target number of modules are cascaded to generate the target quantum circuit corresponding to the adder;
  • Each qubit of the target quantum state performs addition operation to generate and output the result of the target quantum state.
  • Embodiment 1 of the present invention provides a quantum subtraction method, as shown in FIG. 14 , the method includes:
  • S2201 obtain the minuend data and the subtrahend data to be calculated, convert the minuend data into a first target quantum state, and convert the subtrahend data into a second target quantum state; wherein, the target quantum state Including: a symbol bit sub-quantum state representing the data symbol and a numerical bit sub-quantum state representing the data value;
  • the existing amplitude encoding method can be used to convert the decimal data to be operated into a binary quantum state representation.
  • the minuend data is 7, the signed binary represents 0111, the highest bit is 0 for positive numbers, and 1 for negative numbers; the subtrahend data is 4, and the signed binary represents 011.
  • At least 4-bit quantum bits a.sign, a2, a1, a0 are obtained, 7 is encoded into the first target quantum state
  • 0111>
  • 1> are called sub-quantum states of
  • the subtractor it is mainly used to realize the function of the subtractor.
  • the biggest difference between the subtractor and the following adder is that a negative number will be generated. Therefore, a binary processing method is used to add a sign bit to both the subtrahend and the minuend. , to indicate the positive or negative value of the value, and use two's complement for the operation.
  • the complement of positive numbers remains unchanged, and 1 is added after inversion of negative numbers except for the sign bit.
  • the sign bit is used to control whether to perform the complement operation.
  • the X gate can be used to invert, and the addition of 1 can be realized by the adder. After the operation is completed in the case of complement, the target value is obtained by performing a complement operation on the result.
  • the minuend data and the subtrahend data to be calculated are acquired, and the minuend data and the subtrahend data are converted into a first target quantum state and a second target quantum state, respectively.
  • the target quantum state includes: a symbol bit sub-quantum state representing the data symbol and a numerical bit sub-quantum state representing the data value.
  • S2202 Acquire a quantum state of a first preset auxiliary bit, and control the first target quantum state to perform a calculation according to the symbol bit sub-quantum state in the first target quantum state and the quantum state of the first preset auxiliary bit
  • the quantum state corresponding to the complement operation is evolved to obtain a first complement quantum state; wherein, the first complement quantum state is a quantum state comprising the complement of the minuend data;
  • the first target quantum state can be The first sign bit qubit and the first preset auxiliary bit corresponding to the sign bit sub-quantum state in the CNOT gate operation are performed, wherein the first sign bit qubit is the control bit, and the first preset auxiliary bit is the controlled bit; and , the CNOT gate can be replaced by other equivalent existing quantum logic gates or quantum logic gate combinations, which is also reasonable and feasible;
  • the quantum state evolves, and the evolved first complement quantum state is obtained, otherwise, the first target quantum state is used as the first complement quantum state; wherein, the quantum state of the first preset auxiliary bit after the CNOT gate operation is performed When it can be
  • the CNOT gate operation is performed on the current first sign bit qubit and the first preset auxiliary bit to restore the quantum state of the current first preset auxiliary bit; wherein, the first sign bit qubit is a control bit, so The first preset auxiliary bits are controlled bits.
  • the first target quantum state is assumed to be
  • 0011> is the highest-order sub-quantum state, that is, the
  • the set quantum bit q1 is initially
  • the quantum state evolution corresponding to the complement operation is not performed on the first target quantum state.
  • the minuend is a positive number, there is no need for complement in the subtraction operation, or in other words, its complement is itself, and
  • the CNOT gate can be executed again for the current a.sign and q1.
  • the quantum state of the a.sign bit is
  • 0> of the controlled bit q1 remains unchanged to restore q1 is in the state of
  • q 1 is the first preset auxiliary bit, which is used to control whether to perform the complement operation
  • the first target quantum state is a
  • a.sign is the sign bit in the first target quantum state Quantum state
  • the remaining a is the numerical bit quantum state representing the data value
  • j is the second preset auxiliary bit
  • the initial state is the 0 state
  • t is the addition
  • the auxiliary bit (the third preset auxiliary bit described below) used by the controller, the initial state is 0 state.
  • the quantum circuit shown in Figure 15 realizes the quantum circuit that performs the operation of the complement of a.
  • a CNOT gate operation is performed on a.sign and q 1 , so that q 1 temporarily represents a.sign, and q 1 is used to control whether to perform the search.
  • Complement code after obtaining the complement code, restore q 1 .
  • the first target quantum state is controlled to perform the quantum state evolution corresponding to the complement operation, and the first complement quantum state is obtained.
  • the first preset auxiliary bit q 1 is used to control whether to perform the complementing operation. If a is a negative number, the complement operation of the negative number is performed. The complement of a negative number is the bitwise inversion except for the sign bit and then adding 1. If the bitwise inversion operation except for the sign bit is implemented with logic gates, it is only necessary to make X gates for all the numerical bits. 1 needs to be added. Therefore, by adding j and a, the current value of j is set to 1, and t is the auxiliary bit of the adder. It is to take the value after the complement, and then restore q 1 for the next use.
  • the X gate operation can be performed on the second sign bit qubit corresponding to the sign bit sub quantum state in the second target quantum state to obtain the inverted sign bit sub quantum state; wherein, the X gate can use an equivalent other It is also reasonable and feasible to replace the existing quantum logic gate or quantum logic gate combination;
  • the CNOT gate operation is performed on the current second sign bit qubit and the first preset auxiliary bit to restore the current quantum state of the first preset auxiliary bit; wherein, the second sign bit qubit is a control bit, so The first preset auxiliary bits are controlled bits.
  • the second target quantum state is assumed to be
  • 0100> is the sub-quantum state of the highest bit, that is, the
  • the X gate can be performed on b.sign, the corresponding sign bit quantum state
  • the quantum state of q1 after the CNOT gate operation is performed is
  • An implementation of the quantum state evolution corresponding to performing the complement operation is as follows:
  • 1100> can be negated by executing the X gate; in order to keep the dimensions consistent, the second preset auxiliary bit j is the preset 4-bit qubit j [3] , j [ 2] , j [1] , j [0] , the quantum state
  • the CNOT gate can be executed again on the current b.sign and q1.
  • the quantum state of the b.sign bit is
  • 1> of the controlled bit q1 is reversed as
  • Figure 16 is a schematic diagram of the quantum circuit of the quantum state evolution corresponding to performing the complement operation on a and b. Referring to the above-mentioned similar method, the second target quantum state b performs the quantum state evolution corresponding to the complement operation. , to get the second's complement quantum state.
  • the complement code is obtained, a and b are added, and after the addition, the previous operation is restored, and what is stored in a is the desired value.
  • the first complement quantum state and the second complement quantum state are substituted into the quantum circuit of the adder, and the quantum state evolution corresponding to the addition operation is performed, thereby, the first complement quantum state is evolved to include all A third target quantum state of the sum of the complement of the minuend data and the complement of the subtrahend data.
  • the fourth target quantum state is output as the result of the subtraction operation of the subtrahend data and the subtrahend data; wherein, the fourth target quantum state is a quantum that includes the complement of the complement of the sum of the complements. state.
  • 1111> is controlled to perform complementation
  • the evolution of the quantum state corresponding to the complement operation can be the same as the above. After the evolution, the quantum state of the first preset auxiliary bit is still restored to
  • the symbol position in the current second target quantum state can also be obtained.
  • the quantum state and the quantum state of the current first preset auxiliary bit control the current second target quantum state to perform the quantum state evolution corresponding to the complement operation, and perform the sign bit fetch on the sign bit sub-quantum state in the current second target quantum state.
  • the evolution of the corresponding quantum state is performed to restore the current second target quantum state.
  • the current second target quantum state is the second's complement quantum state
  • the current quantum state of the first preset auxiliary bit is
  • the quantum state evolution corresponding to the complement operation is further performed on the third target quantum state of the sum of the complement of the minuend data and the complement of the subtrahend data.
  • Figure 17 after both a and b are complemented, add the complements of a and b. After the addition result is obtained on a, perform a complement operation on a again.
  • the quantum state evolution corresponding to the execution of the addition operation may include:
  • S2301 according to the number of qubit bits corresponding to the two quantum states to be operated, determine the number of target modules of the pre-cascading module MAJ module to be cascaded and the post-cascade module UMA module to be cascaded, wherein all The number of modules of the MAJ module is the same as the number of modules of the UMA module;
  • the two quantum states to be operated can be: the first complement quantum state and the second complement quantum state; the negated first target quantum state and the quantum state of the second preset auxiliary bit
  • the first qubit in the circuit is the third preset auxiliary bit, which is initially in the
  • c represents the final carry item, corresponding to the preset carry auxiliary bit, and s is the output bit that does not contain carry.
  • the number of qubits corresponding to e and f is required to be the same, and the number of s, e and f is the same.
  • e [i] and f [i] are respectively the i-th bit of the quantum state corresponding to the two addends, and c [i] is the upper-order carry bit.
  • the first quantum bit is the third preset auxiliary bit, which corresponds to c 0 in the quantum circuit.
  • the first MAJ module includes three input quantum states and three corresponding output quantum states, wherein the three input quantum states are c 0 , e 0 , and f 0 respectively, and e 0 is the first quantum state to be operated. 0-bit quantum state, f 0 is the 0th-bit quantum state of the second quantum state to be operated, c 0 is the quantum state of the third preset auxiliary bit, and the initial value is 0, that is, no carry.
  • the three output quantum states are c 1 , c 1 is the carry after the addition of e 0 and f 0.
  • the three input quantum states of the next MAJ module are c 1 , e 1 , and f 1 , and the three output quantum states are respectively c 2 , and so on to the last MAJ module.
  • the first UMA module includes three input quantum states and three corresponding output quantum states, wherein the three output quantum states of the MAJ module are the three input quantum states of the corresponding UMA module, and the three output quantum states are respectively c 0 , s 0 , e 0 , s 0 is the result of the addition of e 0 and f 0 without carry. Similarly, s1 is the result of the addition of e 1 and f 1 without carry, and so on, c4 is the final carry term. It should be noted that, in practical applications, without the requirement of calculating the final carry, the quantum circuit corresponding to c4 may not be set.
  • the number of modules of the MAJ module and the number of UMA modules can be determined according to the number of sub-quantum states contained in any quantum state to be calculated.
  • One sub-quantum state corresponds to one qubit
  • the number of modules of the MAJ module is and the same number of UMA modules.
  • 4-bit qubits are required to encode e and f each, and the number of MAJ modules and UMA modules are both 4.
  • the MAJ module and the UMA module constitute the front and rear cascade units of the adder.
  • the MAJ module can be used to extract the carry term of any step and pass it to the next level to calculate the final carry term.
  • the UMA module extracts the information of c and transmits it to the upper-level UMA, and also calculates the s (result item) of each level, and restores the information of e.
  • the MAJ module and the UMA module both include three input items and three output items.
  • the three output items of a MAJ cascade module can be used as the three inputs of a corresponding UMA cascade module. Item, to cascade the MAJ cascading module and the corresponding UMA cascading module to generate the target quantum circuit corresponding to the adder, wherein the MAJ cascading module is composed of the MAJ modules of the number of the target modules.
  • the UMA cascading module is determined by cascading between UMA modules of the target number of modules.
  • the three input items of the MAJ module include a carry input item and two sub-quantum state input items to be calculated
  • the three output items of the MAJ module include a carry output item and two intermediate result output items
  • the three input items of the UMA module include a carry output item and two intermediate result output items corresponding to the MAJ module
  • the three output items of the UMA module include a result carry output item, an accumulation sum output item, and a to-be-calculated item.
  • the carry output item output by the previous MAJ module and the two input items of the sub-quantum state to be calculated can be used as the three input items of the next MAJ module, so that the MAJ of the target module number modules are cascaded;
  • a CNOT quantum logic gate is added between the last MAJ module and the corresponding first UMA module in the initial quantum circuit, wherein the qubit corresponding to the carry output item of the MAJ module is used as the control bit, and the preset carry
  • the auxiliary bits act as controlled bits to generate the target quantum circuit of the adder.
  • the CNOT gate and the carry auxiliary bit may not be set.
  • the three output bits of the MAJ module are used as the three input bits of the UMA module, so that the same number of MAJ modules and UMA modules are Concatenation is performed to generate the target quantum circuit corresponding to the adder.
  • the hollow circle and the solid circle connected in the circuit diagram represent the CNOT gate operation
  • the hollow circle corresponding to the qubit is the control bit
  • the solid circle corresponding to the controlled bit is the CNOT gate operation
  • the MAJ module is a MAJ quantum circuit
  • the UMA module is a UMA quantum circuit.
  • Both the MAJ quantum circuit and the UMA quantum circuit include two CNOT quantum logic gates and one TOFFOLI quantum logic gate.
  • the instruction, before the step of cascading the MAJ modules and the UMA modules of the number of the target modules to generate the target quantum circuit corresponding to the adder also includes: obtaining the two CNOT quantum logic gates and a TOFFOLI quantum logic
  • the operation qubits corresponding to the gates, the control relationship between the operation qubits, and the timing relationship between the two CNOT quantum logic gates and one TOFFOLI quantum logic gate; according to the operation qubits, the control relationship and the Timing relationship, the two CNOT quantum logic gates and one TOFFOLI quantum logic gate are constructed to generate the MAJ quantum circuit or the UMA quantum circuit, as the corresponding MAJ module or UMA module.
  • the MAJ module and the UMA module constitute the front and rear cascade units of the adder.
  • the MAJ module is used to extract the carry term after each level of addition operation and pass it to the next level, thereby calculating the final carry term.
  • the MAJ module can be mainly composed of three logic gates, namely two CNOT gates and one Toffoli gate.
  • the function of the CNOT gate (the first and second logic gates from left to right in Figure 22) is to add the control bit to the target bit to form a modulo 2 addition, which is an exclusive OR operation, and obtain (e i +c i )%2, (e i +f i )%2, the order of the two CNOT gates can be swapped.
  • Example 1 e i is 1, f i is 1, and c i is 1.
  • the MAJ module starts to add ei to ci , the value on ci becomes 0, then adds ei to fi , the value on fi also becomes 0, and finally adds fi and ci to On e i , the value of e i becomes 1, that is, the carry of c i+1 is 1.
  • Example 2 e i is 0, f i is 1, and c i is 1.
  • the MAJ module starts to add ei to ci , the value on ci becomes 1, then adds ei to fi , the value on fi also becomes 1, and finally adds fi and ci to On e i , the value of e i becomes 1, that is, the carry of c i+1 is 1.
  • the UMA module is used for the latter stage of the cascaded adder.
  • the implementation of the UMA module is similar to the MAJ module.
  • the Toffoli gate is used first (the first from left to right in Figure 24).
  • Example 1 ( ei + c i ) % 2 is 0, ( ei +fi )% 2 is 0, and c i +1 is 1.
  • Example 2 ( ei + c i ) % 2 is 1, ( ei +fi )% 2 is 1, and c i +1 is 1.
  • the adder that is, the target quantum circuit
  • the corresponding binary representation of the target quantum state calculation result including the carry term and the result term obtained by the direct addition of each sub-quantum state. Then directly output the target quantum state result
  • the subtrahend data is converted into a first target quantum state, and the subtrahend data is converted into a second target quantum state;
  • the first target quantum state is controlled to perform the quantum state evolution corresponding to the complement operation, Obtain the first's complement quantum state; control the current second target quantum state to perform the quantum state evolution corresponding to the complement operation to obtain the second's complement quantum state; compare the first's complement quantum state and the second's complement quantum state Quantum state, perform the evolution of the quantum state corresponding to the addition operation, and obtain the third target quantum state; control the third target quantum state to perform the quantum state evolution corresponding to the complement operation, and obtain the evolved fourth target quantum state, thereby realizing It can be used for subtraction operations in quantum circuits, filling the gaps in related technologies.
  • another embodiment of the present invention provides a quantum subtraction operation device, and the quantum subtraction operation device includes:
  • Operation data acquisition module 21301 used to acquire the minuend data and the subtrahend data to be calculated, convert the subtrahend data into a first target quantum state, and convert the subtrahend data into a second target quantum state ; wherein, the target quantum state includes: a symbol bit sub-quantum state representing the data symbol and a numerical bit sub-quantum state representing the data value;
  • the first quantum state evolution module 21302 is used to obtain the quantum state of the first preset auxiliary bit, and control the quantum state according to the symbol bit quantum state in the first target quantum state and the quantum state of the first preset auxiliary bit.
  • the first target quantum state performs the quantum state evolution corresponding to the complement operation to obtain a first complement quantum state; wherein, the first complement quantum state is a quantum state that includes the complement of the subtrahend data;
  • the second quantum state evolution module 21303 is configured to perform the quantum state evolution of the sign bit inversion reaction for the sign bit sub-quantum state in the second target quantum state, and according to the inverted sign bit sub-quantum state and the first quantum state evolution Presetting the quantum state of the auxiliary bit, controlling the current second target quantum state to perform the quantum state evolution corresponding to the complement calculation operation, and obtaining the second complement quantum state; wherein, the second complement quantum state includes the subtrahend The quantum state of the complement of the data;
  • the third quantum state evolution module 21304 is configured to perform quantum state evolution corresponding to the addition operation on the first complement quantum state and the second complement quantum state, so as to evolve the first complement quantum state into a third target quantum state comprising the sum of the complement of the minuend data and the complement of the subtrahend data;
  • the target quantum operation module 21305 is configured to control the third target quantum state to perform a complement operation corresponding to the symbol bit sub-quantum state in the third target quantum state and the quantum state of the first preset auxiliary bit.
  • the quantum state evolves, and the fourth target quantum state after evolution is obtained, which is output as the result of the subtraction operation of the subtrahend data and the subtrahend data; wherein, the fourth target quantum state is the one containing the complement of the code. and the quantum state of the complement of .
  • the device further includes:
  • the restoration module is used to control the current second target quantum state to perform the quantum state evolution corresponding to the complement operation according to the symbol bit sub quantum state in the current second target quantum state and the quantum state of the current first preset auxiliary bit, and perform the corresponding quantum state evolution on the current second target quantum state.
  • the sign bit sub quantum state in the current second target quantum state performs quantum state evolution of the sign bit negation response, so as to restore the current second target quantum state.
  • the first quantum state evolution module is specifically used for:
  • the CNOT gate operation is performed on the current first sign bit qubit and the first preset auxiliary bit to restore the quantum state of the current first preset auxiliary bit; wherein, the first sign bit qubit is a control bit, so The first preset auxiliary bits are controlled bits.
  • the second quantum state evolution module is specifically used for:
  • the second sign bit qubit corresponding to the sign bit sub-quantum state in the second target quantum state performs the X gate operation to obtain the inverted sign bit sub-quantum state
  • the CNOT gate operation is performed on the current second sign bit qubit and the first preset auxiliary bit to restore the current quantum state of the first preset auxiliary bit; wherein, the second sign bit qubit is a control bit, so The first preset auxiliary bits are controlled bits.
  • the third quantum state evolution module includes:
  • the determining unit is used to determine the number of target modules of the pre-cascade module MAJ module to be cascaded and the post-cascade module UMA module to be cascaded according to the number of qubit bits corresponding to the two quantum states to be operated, Wherein, the number of modules of the MAJ module is the same as the number of modules of the UMA module;
  • the cascade unit is used for cascading the MAJ module and the UMA module of the target module number according to the addition instruction to generate the target quantum circuit corresponding to the adder;
  • the operation unit is configured to perform an addition operation on each sub-quantum state of the two quantum states to be operated through the target quantum circuit to generate and output the result of the target quantum state.
  • the MAJ module is a MAJ quantum circuit
  • the UMA module is a UMA quantum circuit
  • both the MAJ quantum circuit and the UMA quantum circuit include two CNOT quantum logic gates and one TOFFOLI quantum logic gate
  • the third quantum state evolution module further includes:
  • the obtaining unit is used to obtain the operation qubits corresponding to the two CNOT quantum logic gates and one TOFFOLI quantum logic gate, the control relationship between the operation qubits, and the difference between the two CNOT quantum logic gates and one TOFFOLI quantum logic gate. temporal relationship between;
  • the MAJ module and the UMA module all include three input items and three output items;
  • the cascade unit includes:
  • the cascade subunit is used to use the three output items of a MAJ cascade module as three input items of a corresponding UMA cascade module according to the addition instruction, so as to connect the MAJ cascade module with the corresponding UMA cascade module Perform cascading to generate a target quantum circuit corresponding to the adder, wherein the MAJ cascade module is determined by the cascade between MAJ modules of the target module number, and the UMA cascade module is determined by the target module. The number of cascaded UMA modules is determined.
  • the three input items of the MAJ module include a carry input item and two sub-quantum state input items to be calculated
  • the three output items of the MAJ module include a carry output item and two intermediate result output items
  • the three input items of the UMA module include a carry output item of the corresponding MAJ module and two intermediate result output items
  • the three output items of the UMA module include a result carry output item, Accumulation and output items and a sub-quantum state input item to be calculated
  • the cascaded sub-units are specifically used for:
  • the carry output item output by the previous MAJ module and the two sub-quantum state input items to be calculated are used as the three input items of the next MAJ module, so that the MAJ modules of the target number of modules are graded. link;
  • a CNOT quantum logic gate is added between the last MAJ module and the corresponding first UMA module in the initial quantum circuit, wherein the qubit corresponding to the carry output item of the MAJ module is used as the control bit, and the preset carry
  • the auxiliary bits act as controlled bits to generate the target quantum circuit of the adder.
  • the subtrahend data is converted into a first target quantum state, and the subtrahend data is converted into a second target quantum state;
  • the first target quantum state is controlled to perform the quantum state evolution corresponding to the complement operation, Obtain the first's complement quantum state; control the current second target quantum state to perform the quantum state evolution corresponding to the complement operation to obtain the second's complement quantum state; compare the first's complement quantum state and the second's complement quantum state Quantum state, perform the evolution of the quantum state corresponding to the addition operation, and obtain the third target quantum state; control the third target quantum state to perform the quantum state evolution corresponding to the complement operation, and obtain the evolved fourth target quantum state, thereby realizing It can be used for subtraction operations in quantum circuits, filling the gaps in related technologies.
  • Yet another embodiment of the present invention provides an electronic device comprising a memory and a processor, the memory having a computer program stored therein, the processor being configured to run the computer program to perform a method as described below:
  • S1 obtain the minuend data and the subtrahend data to be calculated, convert the subtrahend data into a first target quantum state, and convert the subtrahend data into a second target quantum state; wherein, the target quantum state Including: a symbol bit sub-quantum state representing the data symbol and a numerical bit sub-quantum state representing the data value;
  • S2 Acquire the quantum state of the first preset auxiliary bit, and control the first target quantum state to perform the calculation according to the quantum state of the symbol bit in the first target quantum state and the quantum state of the first preset auxiliary bit.
  • the quantum state corresponding to the complement operation is evolved to obtain a first complement quantum state; wherein, the first complement quantum state is a quantum state comprising the complement of the minuend data;
  • the target quantum state performs the quantum state evolution corresponding to the complement operation to obtain a second complement quantum state; wherein, the second complement quantum state is a quantum state comprising the complement of the subtraction data;
  • the fourth target quantum state is output as the result of the subtraction operation of the subtrahend data and the subtrahend data; wherein, the fourth target quantum state is a quantum that includes the complement of the complement of the sum of the complements. state.
  • Yet another embodiment of the present invention provides a storage medium, where a computer program is stored in the storage medium, wherein the computer program is configured to execute the following method when running:
  • S1 obtain the minuend data and the subtrahend data to be calculated, convert the subtrahend data into a first target quantum state, and convert the subtrahend data into a second target quantum state; wherein, the target quantum state Including: a symbol bit sub-quantum state representing the data symbol and a numerical bit sub-quantum state representing the data value;
  • S2 Acquire the quantum state of the first preset auxiliary bit, and control the first target quantum state to perform the calculation according to the quantum state of the symbol bit in the first target quantum state and the quantum state of the first preset auxiliary bit.
  • the quantum state corresponding to the complement operation is evolved to obtain a first complement quantum state; wherein, the first complement quantum state is a quantum state comprising the complement of the minuend data;
  • the target quantum state performs the quantum state evolution corresponding to the complement operation to obtain a second complement quantum state; wherein, the second complement quantum state is a quantum state comprising the complement of the subtraction data;
  • the fourth target quantum state is output as the result of the subtraction operation of the subtrahend data and the subtrahend data; wherein, the fourth target quantum state is a quantum that includes the complement of the complement of the sum of the complements. state.
  • a quantum subtraction operation method characterized in that the method comprises: acquiring the minuend data and the subtrahend data to be calculated, converting the minuend data into a first target quantum state, and converting the subtrahend data into a first target quantum state.
  • the target quantum state includes: a symbol bit sub-quantum state representing the data symbol and a numerical bit sub-quantum state representing the data value; obtaining the quantum state of the first preset auxiliary bit , according to the symbol bit sub-quantum state in the first target quantum state and the quantum state of the first preset auxiliary bit, control the first target quantum state to perform the quantum state evolution corresponding to the complement operation, and obtain the first Complement quantum state;
  • the first complement quantum state is a quantum state containing the complement of the minuend data;
  • the symbol bit sub quantum state in the second target quantum state is executed corresponding quantum state evolution , and control the current second target quantum state to perform the quantum state evolution corresponding to the complement operation according to the inverted quantum state of the sign bit and the quantum state of the first preset auxiliary bit to obtain the second complement quantum state;
  • the second's complement quantum state is a quantum state containing the complement of the subtraction data; for the first's complement quantum state and the second
  • the method according to C21 characterized in that, after the step of controlling the third target quantum state to perform the quantum state evolution corresponding to the complement operation, and obtaining the evolved fourth target quantum state, it also includes: According to the symbol bit sub quantum state in the current second target quantum state and the quantum state of the current first preset auxiliary bit, the current second target quantum state is controlled to perform the quantum state evolution corresponding to the complement operation, and the quantum state evolution corresponding to the current second target quantum state is controlled.
  • the sign bit sub-quantum state in the state performs the quantum state evolution of the sign bit inversion response, so as to restore the current second target quantum state.
  • the step of performing the quantum state evolution corresponding to the complement operation on the quantum state specifically includes: performing CNOT on the first sign bit qubit and the first preset auxiliary bit corresponding to the sign bit sub-quantum state in the first target quantum state gate operation, wherein the first sign bit qubit is a control bit, and the first preset auxiliary bit is a controlled bit; according to the quantum state of the first preset auxiliary bit after performing the CNOT gate operation, control Whether the current first target quantum state performs the quantum state evolution corresponding to the complement operation; if so, invert the non-signed bit quantum state of the current first target quantum state, and compare the inverted first target quantum state with the first target quantum state.
  • 1> state of the two preset auxiliary bits perform the quantum state evolution corresponding to the addition operation, and obtain the evolved first's complement quantum state, otherwise, the first target quantum state is used as the first's complement quantum state ; Perform the CNOT gate operation on the current first sign bit qubit and the first preset auxiliary bit to restore the quantum state of the current first preset auxiliary bit; wherein, the first sign bit qubit is a control bit,
  • the first preset auxiliary bits are controlled bits.
  • the step of controlling the second target quantum state to perform the quantum state evolution corresponding to the complement operation specifically includes: in the second target quantum state Perform the X gate operation on the second sign bit qubit corresponding to the sign bit sub-quantum state of , to obtain the inverted sign bit sub-quantum state; perform the CNOT gate operation on the current second sign bit qubit and the first preset auxiliary bit, where , the second sign bit qubit is a control bit, and the first preset auxiliary bit is a controlled bit; according to the current quantum state of the first preset auxiliary bit after performing the CNOT gate operation, control the current second target quantum Whether the state performs the quantum state evolution corresponding to the complement operation; if so, invert the non-sign bit sub-quantum state of the current second target quantum state, and compare the inverted second target quantum state
  • the evolution of the quantum state corresponding to the execution of the addition operation comprises: according to the number of bits of the qubit bits corresponding to the two quantum states to be operated, determining The number of target modules of the front cascading module MAJ module to be cascaded and the rear cascading module UMA module to be cascaded, wherein the number of modules of the MAJ module is the same as the number of modules of the UMA module; according to the addition instruction, the MAJ module and the UMA module of the target module number are cascaded to generate the target quantum circuit corresponding to the adder; each sub-quantum state of the two quantum states to be calculated is performed through the target quantum circuit.
  • the addition operation generates the target quantum state result and outputs it.
  • the MAJ modules and UMA modules of the number of modules are cascaded, and the step of generating the target quantum circuit corresponding to the adder specifically includes: according to the addition instruction, using three output items of a MAJ cascade module as a corresponding UMA cascade module three input items, to cascade the MAJ cascade module and the corresponding UMA cascade module to generate the target quantum circuit corresponding to the adder, wherein the MAJ cascade module is composed of the target module
  • the number of MAJ modules is cascaded and determined, and the UMA cascade module is determined by cascaded between the UMA modules of the target module number.
  • C28 The method according to any one of C21-C27, wherein the three input items of the MAJ module include a carry input item and two sub-quantum state input items to be calculated, and the three input items of the MAJ module
  • the output items include one carry output item and two intermediate result output items
  • the three input items of the UMA module include one carry output item and two intermediate result output items corresponding to the MAJ module
  • the three output items of the UMA module The item includes a result carry output item, an accumulation sum output item, and a sub-quantum state input item to be calculated.
  • the three output items of a MAJ cascade module are used as a corresponding UMA cascade module.
  • the step of generating the target quantum circuit corresponding to the adder specifically includes: according to the addition instruction, the carry output item output by the previous MAJ module And the two sub-quantum state input items to be calculated are used as three input items of the next MAJ module, to cascade the MAJ modules of the target module number; two intermediate result output items of a MAJ module are used as One corresponding to the two input items of the UMA module, obtain the previous UMA module of the corresponding UMA module, and use the result of the previous UMA module to carry the output item as an input item of the corresponding UMA module, so that the The MAJ module of the target module number and the UAM module of the target module number are cascaded to generate the initial quantum circuit; wherein, the carry output item of the last MAJ module is used as an input item of the corresponding first UMA module ; Add a CNOT quantum logic gate between the last MAJ module and the corresponding first
  • a quantum subtraction operation device characterized in that the device comprises: an operation data acquisition module, configured to acquire the minuend data and the subtrahend data to be calculated, and convert the minuend data into a first a target quantum state, converting the subtraction data into a second target quantum state; wherein, the target quantum state includes: a symbol bit sub-quantum state representing the data symbol and a numerical bit sub-quantum state representing the data value; the first quantum state
  • the state evolution module is used to obtain the quantum state of the first preset auxiliary bit, and control the first target according to the symbol bit sub-quantum state in the first target quantum state and the quantum state of the first preset auxiliary bit
  • the quantum state performs the quantum state evolution corresponding to the complement operation to obtain a first complement quantum state; wherein, the first complement quantum state is a quantum state containing the complement of the minuend data; the second quantum state
  • the evolution module is used to perform corresponding quantum state evolution on the symbol bit sub quantum state in the second target quantum state, and control the quantum state according
  • the current second target quantum state performs the quantum state evolution corresponding to the complement operation to obtain a second complement quantum state; wherein, the second complement quantum state is a quantum state containing the complement of the subtraction data;
  • the third The three-quantum state evolution module is configured to perform quantum state evolution corresponding to the addition operation on the first complement quantum state and the second complement quantum state, so as to evolve the first complement quantum state into a quantum state including all the third target quantum state of the sum of the complement of the subtrahend data and the complement of the subtrahend data;
  • the target quantum operation module is used for according to the symbol bit sub-quantum state in the third target quantum state and the The quantum state of the first preset auxiliary bit controls the third target quantum state to perform the quantum state evolution corresponding to the complement operation, and obtains the evolved fourth target quantum state, which is used as the subtrahend data and the subtraction data.
  • the subtraction operation result of the digital data is output; wherein, the fourth target quantum state is a quantum state including the complement of the sum of the complements
  • An electronic device comprising a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute any one of C21-C27. method.
  • a storage medium characterized in that a computer program is stored in the storage medium, wherein the computer program is configured to execute the method described in any one of C21-C27 when running.
  • the quantum subtraction operation method provided by the present invention includes converting the subtrahend data into a first target quantum state, and converting the subtrahend data into a second target quantum state;
  • the first target quantum state performs the quantum state evolution corresponding to the complement operation to obtain the first complement quantum state; controls the current second target quantum state to perform the quantum state evolution corresponding to the complement operation to obtain the second complement quantum state ;
  • For the first complement quantum state and the second complement quantum state perform the quantum state evolution corresponding to the addition operation to obtain the third target quantum state; Control the third target quantum state to execute the complement operation corresponding to The quantum state evolution of the quantum state is obtained, and the fourth target quantum state after evolution is obtained, so as to realize the subtraction operation that can be used in quantum circuits, and fill the gap of related technologies.
  • Embodiments of the present invention provide a quantum multiplication method for implementing basic arithmetic operations, which can be multiplication operations.
  • Figure 26 provides a schematic flowchart of a quantum multiplication method, including:
  • S3201 Acquire the multiplicand data and multiplier data to be calculated, convert the multiplicand data into a first target quantum state, and convert the multiplier data into a second target quantum state; wherein the target quantum state The quantum state stores the binary value of the data, and the number of qubits corresponding to the first target quantum state is at least twice the number of qubits corresponding to the second target quantum state.
  • the multiplicand data to be operated refers to the number to be multiplied in the multiplication operation, also called the factor, which is generally placed in front of the formula;
  • the multiplier data refers to the number multiplied by other numbers in the multiplication operation, also called the factor, Usually placed after the formula.
  • the quantum state space represented by a qubit bit refers to the quantum state information represented by all the eigenstates corresponding to the qubit bit, and the number of all eigenstates is the number power of 2 qubit bits.
  • Quantum state refers to the state of qubits, and its eigenstates are represented by binary in quantum algorithms (or quantum programs). For example, a group of qubits are q0, q1, q2, which represent the 0th, 1st, and 2nd qubits, and the order from high to low is q2q1q0, and the quantum states of this group of qubits are 23 eigenstates
  • the 8 eigenstates (determined states) refer to:
  • a quantum state is a superposition state composed of various eigenstates. When the probability amplitude of other states is 0, it is in one of the certain eigenstates.
  • the quantum state may be
  • the useful information is the information of the two lowest bits, so the quantum state corresponding to the data value to be calculated can also be abbreviated as
  • 2>
  • the data of the multiplicand to be calculated is 7 and the data of the multiplier is 5, then the data of the multiplicand is converted into the first target quantum state as
  • a group of qubits has 3 or more; converting the multiplier data into the second target quantum state is
  • S3202 For each bit of the binary value stored in the second target quantum state, control the third target quantum state of the first preset auxiliary bit and the stored binary value to shift the left-shifted third bit according to the binary value of the current bit. a target quantum state, perform the evolution of the quantum state corresponding to the addition operation, and obtain a third target quantum state that stores the result of the addition operation after evolution, wherein the initial state of the third target quantum state is
  • the first target quantum state performing the quantum state evolution corresponding to the addition operation, includes the following steps:
  • S32021 Obtain a first preset auxiliary bit with the same number of qubits corresponding to the first target quantum state, and initialize the third target quantum state of the first preset auxiliary bit to a
  • the first preset auxiliary bit can be used to store the result of the multiplication operation between the multiplicand data and the multiplier data, the initialized third target quantum state is the
  • a group of qubit bits for storing the first target quantum state is 6 qubits, and the first target quantum state is
  • the number of qubits corresponding to one target quantum state is the same, which is 6 qubits, and the third target quantum state after initialization is
  • S32022 From the first bit in the binary values stored in the second target quantum state, determine the binary value of the current bit.
  • the first bit in the binary value stored in the second target quantum state is the lower bit of the second target quantum state, and whether the current binary value is 1 is determined in sequence from the lower bit.
  • the second target quantum state is
  • the order from high to low is 101
  • the first bit is the binary value 1
  • the first bit is the binary value.
  • Two bits are binary value 0, and the third bit is binary value 1.
  • the initial first target quantum state is
  • the second target quantum state is
  • the third target quantum state is
  • the binary value of the current bit of the second target quantum state is judged in turn. , if it is 1, perform the quantum state evolution corresponding to the addition operation between the current third target quantum state of the first preset auxiliary bit and the current first target quantum state, that is, the current first target quantum state
  • S32024 Using a quantum logic gate, exchange each sub-quantum state included in the first target quantum state, so as to shift the binary value stored in the first target quantum state by one bit to the left.
  • the initial first target quantum state is
  • quantum logic gates are used to exchange sub-quantum states included in the first target quantum state
  • 000111> is shifted left by one bit and converted into a quantum state
  • a SWAP gate is first inserted between the third and fourth qubits from low bits to high bits, that is, the first target quantum state
  • the quantum logic gate SWAP gate is used to realize the left shift of the quantum state above, but in the actual implementation process, it is not limited to one quantum logic gate, and can also use a variety of single quantum logic gates or double quantum logic gates.
  • the combination of logic gates is used to realize the left-shift operation of the quantum state. Therefore, any combination of quantum logic gates that can realize the above-mentioned transformation operations such as the left-shift of the quantum state should be included in the protection scope of this application, and no specific details are given here. limited.
  • S32025 Add one to the number of digits of the current bit, and return to executing the step of judging the binary value of the current bit until the last digit in the binary value stored in the second target quantum state is judged.
  • the number of bits of the current bit is increased by one, that is, the number of bits of the binary value stored in the second target quantum state is increased by one, the first bit is changed to the second bit, and the step of judging the binary value of the current bit is returned to execution , that is, returning to step S2022 to step S2024 until the judgment of the last bit in the binary value stored in the second target quantum state is completed.
  • the second target quantum state is
  • 001110> since the binary value of the current bit of the second target quantum state is 0, the third target quantum state
  • step S2025 the second target quantum state
  • step S2024 the current first target quantum state
  • One bit is transformed into a quantum state
  • 011100> obtains the third target quantum state which stores the result of the post addition operation after evolution.
  • the multiplicand data is the first target quantum state
  • the multiplier data is the second target quantum state
  • 100011> can be converted into a decimal number 35 to represent and output the result, or the binary operation result can be directly output.
  • the method further includes: using a quantum logic gate to restore the current first target quantum state.
  • the quantum logic gate SWAP gate can be used to restore the current first target quantum state to the initial state, so as to facilitate the use and operation of subsequent quantum circuits.
  • a first sub-quantum state in which the sign bit of the multiplicand data is stored and a second sub-quantum state in which the sign bit of the multiplier data is stored are acquired.
  • the sign of the multiplicand data and the multiplier data when the sign of the multiplicand data and the multiplier data is the same, the result after the multiplication operation is positive; the sign of the multiplicand data and the multiplier data are different, and the result after the multiplication operation are all negative numbers; wherein, the sign of the multiplicand data and the multiplier data needs to be represented by the first sub-quantum state, the second sub-quantum state and their corresponding qubit bits that store the sign bit.
  • the initial state of the third sub-quantum state of the sign bit of the multiplication result to be stored is evolved into the third sub-quantum state that stores the sign bit of the multiplication result The final state of the quantum state.
  • FIG. 27 a schematic diagram of saving the result of the sign bit operation of the present embodiment, wherein the values (multiplicand and multiplier) of the two quantum registers a and b are multiplied, and the calculation result is stored in the register.
  • a.sign is the sign bit of a, represented by the first sub quantum state
  • b.sign is the sign bit of b, represented by the second sub quantum state
  • d.sign is the sign bit of the calculation result d, represented by the third sub quantum state state representation
  • the initial value of d.sign is the initial state of the third sub-quantum state, which can be set to
  • the CNOT gate is performed on the first sign bit qubit corresponding to the first sub-quantum state and the second sign bit qubit corresponding to the second sub-quantum state; wherein, the first sign bit qubit is used as the control bit of the CNOT gate (black dots in the figure, the same below), the qubit of the second sign bit is used as the controlled bit of the CNOT gate (the "+" sign in the circle in the figure, the same below); multiply the current second sign bit qubit and the to-be-stored qubit
  • the third sign bit qubit corresponding to the third sub-quantum state of the sign bit of the operation result executes the CNOT gate, so as to evolve the initial state of the third sub-quantum state of the sign bit of the multiplication operation result to be stored into the multiplication operation result stored
  • the final state of the third sub-quantum state of the sign bit of state perform the CNOT gate on the current first sign bit qubit and the current second sign bit qubit to restore the current second sub quantum state; wherein, the first sign
  • the positive and negative of the multiplicand data and the multiplier data share the following four situations: that is, the multiplicand data and the multiplier data are both positive numbers, both negative numbers, and one positive number and one negative number.
  • the positive and negative conditions of the multiplicand data and the multiplier data can be expressed by quantum states as follows: when the first sub-quantum state is preset to the
  • the initial state of the third sub-quantum state of the sign bit of the multiplication result to be stored is evolved into
  • the initial state of the third sub-quantum state where the sign bit of the multiplication result is to be stored is evolved into the symbol storing the multiplication result
  • the final state of the third sub-quantum state of the bit is
  • FIG. 27 is only a schematic diagram of the present embodiment using the CNOT gate to store the result of the sign bit operation.
  • other quantum logic gates can also be used to store the sign bit operation result. There is no specific limitation here.
  • any classical logic circuit can also be represented by a quantum circuit.
  • the input and output of a quantum logic gate/quantum circuit are both quantum states, and the number of qubits in the input and output is equal.
  • Quantum circuits allow quantum states to be input in superposition, and output states can be superimposed and output in the same way.
  • Reversible computing is the basis of quantum computing, that is, any reversible quantum circuit has an inverse circuit, that is, taking each original output as an input can just be mapped to the original input.
  • a reversible circuit means that for every output, there is exactly one input corresponding to it, and the mapping is one-to-one.
  • the quantum state evolution corresponding to the addition operation can be performed by the adder, which can include:
  • the number of qubit bits corresponding to the two quantum states to be operated determine the number of target modules of the pre-cascade module MAJ module to be cascaded and the post-cascade module UMA module to be cascaded, wherein the MAJ module
  • the number of modules of the module is the same as the number of modules of the UMA module.
  • the first qubit in the circuit is the second preset auxiliary bit, which is initially in the state of
  • e and f are the quantum states corresponding to the data to be added, each corresponding to a group of qubits.
  • c represents the final carry item, corresponding to the preset carry auxiliary bit, and s is the output bit that does not contain carry.
  • the number of qubits corresponding to e and f is required to be the same, and the number of s, e and f is the same.
  • e [i] and f [i] are respectively the i-th bit of the quantum state corresponding to the two addends, and c [i] is previous level carry.
  • the first quantum bit is the second preset auxiliary bit, which corresponds to c 0 in the quantum circuit.
  • the first MAJ module includes three input quantum states and three corresponding output quantum states, wherein the three input quantum states are c 0 , e 0 , and f 0 respectively, and e 0 is the first quantum state to be operated. 0-bit quantum state, f 0 is the 0th-bit quantum state of the second quantum state to be operated, c 0 is the quantum state of the second preset auxiliary bit, and the initial value is 0, that is, no carry.
  • the three output quantum states are c 1 , c 1 is the carry after the addition of e 0 and f 0.
  • the three input quantum states of the next MAJ module are c 1 , e 1 , and f 1 , and the three output quantum states are respectively c 2 , and so on to the last MAJ module.
  • the first UMA module includes three input quantum states and three corresponding output quantum states, wherein the three output quantum states of the MAJ module are the three input quantum states of the corresponding UMA module, and the three output quantum states are respectively c 0 , s 0 , e 0 , s 0 is the result of the addition of e 0 and f 0 without carry. Similarly, s1 is the result of the addition of e 1 and f 1 without carry, and so on, c4 is the final carry term. It should be noted that, in practical applications, without the requirement of calculating the final carry, the quantum circuit corresponding to c4 may not be set.
  • the number of modules of the MAJ module and the number of UMA modules can be determined according to the number of sub-quantum states contained in any quantum state to be calculated.
  • One sub-quantum state corresponds to one qubit
  • the number of modules of the MAJ module is and the same number of UMA modules. Shown in the figure is only an example, encoding e and f each requires 4 qubits, and the number of MAJ modules and UMA modules are both 4.
  • the MAJ module and the UMA module constitute the front and rear cascade units of the adder.
  • the MAJ module can be used to extract the carry term of any step and pass it to the next level to calculate the final carry term.
  • the UMA module extracts the information of c and transmits it to the upper-level UMA, and also calculates the s (result item) of each level, and restores the information of e.
  • the MAJ modules and the UMA modules of the target modules are cascaded to generate the target quantum circuit corresponding to the adder.
  • the MAJ module and the UMA module both include three input items and three output items.
  • the three output items of a MAJ cascade module can be used as the three inputs of a corresponding UMA cascade module. Item, to cascade the MAJ cascading module and the corresponding UMA cascading module to generate the target quantum circuit corresponding to the adder, wherein the MAJ cascading module is composed of the MAJ modules of the number of the target modules.
  • the UMA cascading module is determined by cascading between UMA modules of the target number of modules.
  • the three input items of the MAJ module include a carry input item and two sub-quantum state input items to be calculated
  • the three output items of the MAJ module include a carry output item and two intermediate result output items
  • the three input items of the UMA module include a carry output item and two intermediate result output items corresponding to the MAJ module
  • the three output items of the UMA module include a result carry output item, an accumulation sum output item, and a to-be-calculated item.
  • the carry output item output by the previous MAJ module and the two input items of the sub-quantum state to be calculated can be used as the three input items of the next MAJ module, so that the MAJ of the target module number modules are cascaded;
  • a CNOT quantum logic gate is added between the last MAJ module and the corresponding first UMA module in the initial quantum circuit, wherein the qubit corresponding to the carry output item of the MAJ module is used as the control bit, and the preset carry
  • the auxiliary bits act as controlled bits to generate the target quantum circuit of the adder.
  • the CNOT gate and the carry auxiliary bit may not be set.
  • the three output bits of the MAJ module are used as the three input bits of the UMA module, so that the same number of MAJ modules and UMA modules are used. Concatenation is performed to generate the target quantum circuit corresponding to the adder.
  • the hollow circle and the solid circle connected in the circuit diagram represent the CNOT gate operation
  • the hollow circle corresponding to the qubit is the control bit
  • the solid circle corresponding to the controlled bit is the hollow circle corresponding to the controlled bit.
  • the MAJ module is a MAJ quantum circuit
  • the UMA module is a UMA quantum circuit.
  • Both the MAJ quantum circuit and the UMA quantum circuit include two CNOT quantum logic gates and one TOFFOLI quantum logic gate.
  • the instruction, before the step of cascading the MAJ modules and the UMA modules of the number of the target modules to generate the target quantum circuit corresponding to the adder also includes: obtaining the two CNOT quantum logic gates and a TOFFOLI quantum logic
  • the operation qubits corresponding to the gates, the control relationship between the operation qubits, and the timing relationship between the two CNOT quantum logic gates and one TOFFOLI quantum logic gate; according to the operation qubits, the control relationship and the Timing relationship, the two CNOT quantum logic gates and one TOFFOLI quantum logic gate are constructed to generate the MAJ quantum circuit or the UMA quantum circuit, as the corresponding MAJ module or UMA module.
  • FIG. 30 is a schematic diagram of a MAJ module provided by an embodiment of the present invention.
  • the MAJ module is used to extract the carry term after each level of addition operation and pass it to the next level, so as to calculate the final carry term.
  • 31 is a schematic diagram of the quantum circuit combination process of the MAJ module provided by the embodiment of the present invention, wherein the MAJ module may be mainly composed of three logic gates, namely two CNOT gates and one Toffoli gate.
  • the function of the CNOT gate (the first and second logic gates from left to right in Figure 31) is to add the control bit to the target bit to form a modulo 2 addition, which is an exclusive OR operation, and obtain (e i +c i )%2, (e i +f i )%2, the order of the two CNOT gates can be swapped.
  • the front-stage cascade unit of the quantum adder is constituted by two CNOT gates and one TOFFOLI gate.
  • Example 1 e i is 1, f i is 1, and c i is 1.
  • the MAJ module starts to add ei to ci , the value on ci becomes 0, then adds ei to fi , the value on fi also becomes 0, and finally adds fi and ci to On e i , the value of e i becomes 1, that is, the carry of c i+1 is 1.
  • Example 2 e i is 0, f i is 1, and c i is 1.
  • the MAJ module starts to add ei to ci , the value on ci becomes 1, then adds ei to fi , the value on fi also becomes 1, and finally adds fi and ci to On e i , the value of e i becomes 1, that is, the carry of c i+1 is 1.
  • Figure 32 shows a schematic diagram of a UMA module provided by an embodiment of the present invention.
  • the UMA module is used for the subsequent stage of the cascaded adder.
  • the implementation of the UMA module is similar to the MAJ module.
  • Figure 33 shows the UMA module provided by the embodiment of the present invention A schematic diagram of the quantum circuit combination process of the UMA module.
  • Example 1 ( ei + c i ) % 2 is 0, ( ei +fi )% 2 is 0, and c i +1 is 1.
  • Example 2 ( ei + c i ) % 2 is 1, ( ei +fi )% 2 is 1, and c i +1 is 1.
  • Each sub-quantum state of the two quantum states to be calculated is added through the target quantum circuit to generate and output the result of the target quantum state.
  • each sub-quantum state of the two target quantum states such as
  • the adder that is, the target quantum circuit
  • the corresponding binary representation of the target quantum state is obtained.
  • the result including the carry term and the result term obtained by the direct addition of the sub-quantum states).
  • 1110> expressed in binary, or further convert it into a decimal result for output to complete the addition operation of the two target data.
  • a quantum multiplication operation method is used to realize the basic multiplication operation in a quantum circuit, including acquiring the multiplicand data to be operated and the multiplier data, and converting the multiplicand data. Convert to the first target quantum state, convert the multiplier data to the second target quantum state, and control the first preset auxiliary bit for each bit in the binary value stored in the second target quantum state according to the binary value of the current bit.
  • the third target quantum state and the first target quantum state after the stored binary value is shifted to the left, perform the quantum state evolution corresponding to the addition operation, and obtain the third target quantum state that stores the result of the addition operation after evolution.
  • the three target quantum states are output as the multiplication result of the multiplicand data and the multiplier data.
  • the present invention fills the blank of related technologies through a technology capable of realizing basic arithmetic operations in quantum circuits.
  • FIG. 34 is a schematic structural diagram of a quantum multiplication device provided by an embodiment of the present invention.
  • the device may include:
  • the acquisition module 31001 is used to acquire the multiplicand data and multiplier data to be calculated, convert the multiplicand data into a first target quantum state, and convert the multiplier data into a second target quantum state; wherein , the target quantum state stores the binary value of the data, and the number of qubits corresponding to the first target quantum state is at least twice the number of qubits corresponding to the second target quantum state;
  • the control module 31002 is used to control the third target quantum state of the first preset auxiliary bit and the stored binary value according to the binary value of the current bit for each bit of the binary value stored in the second target quantum state.
  • the shifted first target quantum state perform the quantum state evolution corresponding to the addition operation, and obtain the evolved third target quantum state storing the addition operation result, wherein the initial state of the third target quantum state is the
  • the output module 31003 is configured to output the finally obtained third target quantum state as the multiplication result of the multiplicand data and the multiplier data.
  • the device further includes:
  • a storage module configured to obtain a first sub-quantum state storing the sign bit of the multiplicand data and a second sub-quantum state storing the sign bit of the multiplier data;
  • the evolution module is used for, according to the first sub-quantum state and the second sub-quantum state, to evolve the initial state of the third sub-quantum state of the sign bit of the multiplication result to be stored into a symbol that stores the multiplication result The final state of the third sub-quantum state of the bit.
  • the evolution module includes:
  • a first execution unit configured to execute a CNOT gate on a first sign bit qubit corresponding to the first sub-quantum state and a second sign bit qubit corresponding to the second sub-quantum state; wherein, the first sign bit qubit The bit qubit is used as the control bit of the CNOT gate, and the second sign bit qubit is used as the controlled bit of the CNOT gate;
  • the second execution unit is configured to execute the CNOT gate on the current second sign bit qubit and the third sign bit qubit corresponding to the third sub-quantum state of the sign bit of the multiplication result to be stored, so as to store the multiplication result
  • the initial state of the third sub-quantum state of the sign bit evolves into the final state of the third sub-quantum state of the sign bit that stores the multiplication result; wherein, the second sign bit qubit is used as the control bit of the CNOT gate , the third sign bit qubit is used as the controlled bit of the CNOT gate, and the initial state is
  • the third execution unit is configured to execute the CNOT gate on the current first sign bit qubit and the current second sign bit qubit to restore the current second sub-quantum state; wherein the first sign bit qubit is used as the The control bit of the CNOT gate, and the second sign bit qubit is used as the controlled bit of the CNOT gate.
  • the device further includes: a restoring module for restoring the current first target quantum state by using a quantum logic gate.
  • control module includes:
  • an obtaining unit configured to obtain a first preset auxiliary bit with the same number of qubits as the first target quantum state, and initialize the third target quantum state of the first preset auxiliary bit to be
  • a judging unit for judging the binary value of the current bit from the first bit in the binary value stored in the second target quantum state
  • the fourth execution unit is configured to perform the quantum state evolution corresponding to the addition operation on the current third target quantum state of the first preset auxiliary bit and the current first target quantum state under the condition that the binary value of the current bit is judged to be 1 ; otherwise, do nothing;
  • an exchange unit configured to use a quantum logic gate to exchange each sub-quantum state included in the first target quantum state, so that the binary value stored in the first target quantum state is shifted left by one bit;
  • the adding unit is configured to add one to the number of digits of the current bit, and return to executing the step of judging the binary value of the current bit until the last digit in the binary value stored in the second target quantum state is judged.
  • control module includes:
  • the determining unit is used to determine the number of target modules of the pre-cascade module MAJ module to be cascaded and the post-cascade module UMA module to be cascaded according to the number of qubit bits corresponding to the two quantum states to be operated, Wherein, the number of modules of the MAJ module is the same as the number of modules of the UMA module;
  • the first cascading unit is used for cascading the MAJ modules and the UMA modules of the target module number according to the addition instruction to generate the target quantum circuit corresponding to the adder;
  • the first generating unit is configured to perform an addition operation on each sub-quantum state of the two target quantum states through the target quantum circuit, and generate and output the result of the target quantum state and output.
  • the device before the first cascading unit, the device further includes:
  • the obtaining unit is used to obtain the operation qubits corresponding to the two CNOT quantum logic gates and one TOFFOLI quantum logic gate, the control relationship between the operation qubits, and the difference between the two CNOT quantum logic gates and one TOFFOLI quantum logic gate. temporal relationship between;
  • the first cascading unit specifically includes:
  • the second generating unit is configured to use the three output items of a MAJ cascading module as three input items of a corresponding UMA cascading module according to the addition instruction, so as to combine the MAJ cascading module with the corresponding UMA cascading module Perform cascading to generate a target quantum circuit corresponding to the adder, wherein the MAJ cascade module is determined by the cascade between MAJ modules of the target module number, and the UMA cascade module is determined by the target module. The number of cascaded UMA modules is determined.
  • the second generating unit specifically includes:
  • the second cascading unit is configured to use the carry output item output by the previous MAJ module and the two input items of the sub-quantum state to be calculated as the three input items of the next MAJ module, so that the target The MAJ modules of the number of modules are cascaded;
  • the third cascading unit is configured to use two intermediate result output items of a MAJ module as two input items of a corresponding UMA module, obtain the previous UMA module of the corresponding UMA module, and use the previous UMA module
  • the result carry output item is used as an input item of the corresponding UMA module, to cascade the MAJ module of the target module number and the UAM module of the target module number to generate the initial quantum circuit; wherein, The carry output item of the last MAJ module is used as an input item of the corresponding first UMA module;
  • the third generation unit is configured to add a CNOT quantum logic gate between the last MAJ module and the corresponding first UMA module in the initial quantum circuit, wherein the qubit corresponding to the carry output item of the MAJ module is used as Control bits, using preset carry auxiliary bits as controlled bits to generate the target quantum circuit of the adder.
  • a quantum multiplication operation method is used to realize the basic multiplication operation in a quantum circuit, including acquiring the multiplicand data to be operated and the multiplier data, and converting the multiplicand data. Convert to the first target quantum state, convert the multiplier data to the second target quantum state, and control the first preset auxiliary bit for each bit in the binary value stored in the second target quantum state according to the binary value of the current bit.
  • the third target quantum state and the first target quantum state after the stored binary value is shifted to the left, perform the quantum state evolution corresponding to the addition operation, and obtain the third target quantum state that stores the result of the addition operation after evolution.
  • the three target quantum states are output as the multiplication result of the multiplicand data and the multiplier data.
  • the present invention fills the blank of related technologies through a technology capable of realizing basic arithmetic operations in quantum circuits.
  • An embodiment of the present invention further provides a storage medium, where a computer program is stored in the storage medium, wherein the computer program is configured to execute the steps in any one of the above method embodiments when running.
  • the above-mentioned storage medium may be configured to store a computer program for executing the following steps:
  • S3201 Acquire the multiplicand data and multiplier data to be calculated, convert the multiplicand data into a first target quantum state, and convert the multiplier data into a second target quantum state; wherein the target quantum state The quantum state stores the binary value of the data, and the number of qubits corresponding to the first target quantum state is at least twice the number of qubits corresponding to the second target quantum state;
  • S3202 For each bit of the binary value stored in the second target quantum state, control the third target quantum state of the first preset auxiliary bit and the stored binary value to shift the left-shifted third bit according to the binary value of the current bit. a target quantum state, perform the evolution of the quantum state corresponding to the addition operation, and obtain a third target quantum state that stores the result of the addition operation after evolution, wherein the initial state of the third target quantum state is
  • the above-mentioned storage medium may include, but is not limited to: a USB flash drive, a read-only memory (Read-Only Memory, referred to as ROM), a random access memory (Random Access Memory, referred to as RAM), mobile Various media that can store computer programs, such as hard disks, magnetic disks, or optical disks.
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute any one of the above method embodiments. A step of.
  • the above-mentioned electronic device may further include a transmission device and an input-output device, wherein the transmission device is connected to the above-mentioned processor, and the input-output device is connected to the above-mentioned processor.
  • the above-mentioned processor may be configured to execute the following steps through a computer program:
  • S3201 Acquire the multiplicand data and multiplier data to be calculated, convert the multiplicand data into a first target quantum state, and convert the multiplier data into a second target quantum state; wherein the target quantum state The quantum state stores the binary value of the data, and the number of qubits corresponding to the first target quantum state is at least twice the number of qubits corresponding to the second target quantum state;
  • S3202 For each bit of the binary value stored in the second target quantum state, control the third target quantum state of the first preset auxiliary bit and the stored binary value to shift the left-shifted third bit according to the binary value of the current bit. a target quantum state, perform the evolution of the quantum state corresponding to the addition operation, and obtain a third target quantum state that stores the result of the addition operation after evolution, wherein the initial state of the third target quantum state is
  • a quantum multiplication operation method characterized in that the method comprises: acquiring multiplicand data and multiplier data to be operated on, converting the multiplicand data into a first target quantum state, and converting the multiplicand data into a first target quantum state.
  • the multiplier data is converted into a second target quantum state; wherein, the target quantum state stores the binary value of the data, and the number of qubits corresponding to the first target quantum state is at least the number corresponding to the second target quantum state twice the number of qubits; for each bit of the binary value stored in the second target quantum state, control the third target quantum state of the first preset auxiliary bit and the stored binary value according to the binary value of the current bit.
  • the first target quantum state after the value is shifted to the left, perform the quantum state evolution corresponding to the addition operation, and obtain the evolved third target quantum state storing the result of the addition operation, wherein the initial state of the third target quantum state is
  • the method according to C31 characterized in that the method further comprises: acquiring the first sub-quantum state storing the sign bit of the multiplicand data and the first sub-quantum state storing the sign bit of the multiplicand data Two sub-quantum states; according to the first sub-quantum state and the second sub-quantum state, evolve the initial state of the third sub-quantum state of the sign bit of the multiplication result to be stored into the symbol storing the multiplication result The final state of the third sub-quantum state of the bit.
  • C33 The method according to C31 or C32, wherein, according to the first sub-quantum state and the second sub-quantum state, the third sub-quantum state of the sign bit of the multiplication result is to be stored.
  • the initial state evolves into the final state of the third sub-quantum state that stores the sign bit of the multiplication result, including: the first sign bit qubit corresponding to the first sub-quantum state and the second sub-quantum state corresponding to the second sub-quantum state
  • the qubit of the second sign bit performs the CNOT gate; wherein, the qubit of the first sign bit is used as the control bit of the CNOT gate, and the qubit of the second sign bit is used as the controlled bit of the CNOT gate;
  • the second sign bit qubit and the third sign bit qubit corresponding to the third sub-quantum state of the sign bit of the multiplication result to be stored perform a CNOT gate, so as to convert the third sub-quantum state of the sign bit of the multiplication result to be stored.
  • the initial state evolves into the final state of the third sub-quantum state storing the sign bit of the multiplication result; wherein, the second sign bit qubit is used as the control bit of the CNOT gate, and the third sign bit qubit is used as the control bit of the CNOT gate.
  • the controlled bit of the CNOT gate the initial state is
  • C34 The method according to any one of C31-C33, characterized in that, after the finally obtained operation result stored in the third target quantum state, the method further comprises: utilizing a quantum logic gate , restore the current first target quantum state.
  • C35 The method according to any one of C31-C34, characterized in that, for each bit in the binary value stored for the second target quantum state, control the first preset value according to the binary value of the current bit.
  • the evolution of the quantum state corresponding to the execution of the addition operation comprises: according to the number of bits of the qubit bits corresponding to the two quantum states to be operated, determining The number of target modules of the front cascading module MAJ module to be cascaded and the rear cascading module UMA module to be cascaded, wherein the number of modules of the MAJ module is the same as the number of modules of the UMA module; according to the addition instruction, the MAJ module and the UMA module of the target module number are cascaded to generate the target quantum circuit corresponding to the adder; each sub-quantum state of the two quantum states to be calculated is performed through the target quantum circuit.
  • the addition operation generates the target quantum state result and outputs it.
  • the MAJ modules and UMA modules of the number of modules are cascaded, and the step of generating the target quantum circuit corresponding to the adder specifically includes: according to the addition instruction, using three output items of a MAJ cascade module as a corresponding UMA cascade module three input items, to cascade the MAJ cascade module and the corresponding UMA cascade module to generate the target quantum circuit corresponding to the adder, wherein the MAJ cascade module is composed of the target module
  • the number of MAJ modules is cascaded and determined, and the UMA cascade module is determined by cascaded between the UMA modules of the target module number.
  • C39 The method according to any one of C31-C38, wherein the three input items of the MAJ module include a carry input item and two sub-quantum state input items to be calculated, and the three input items of the MAJ module
  • the output items include one carry output item and two intermediate result output items
  • the three input items of the UMA module include one carry output item and two intermediate result output items corresponding to the MAJ module
  • the three output items of the UMA module The item includes a result carry output item, an accumulation sum output item, and a sub-quantum state input item to be calculated.
  • the three output items of a MAJ cascade module are used as a corresponding UMA cascade module.
  • the step of generating the target quantum circuit corresponding to the adder specifically includes: according to the addition instruction, the carry output item output by the previous MAJ module And the two sub-quantum state input items to be calculated are used as three input items of the next MAJ module, to cascade the MAJ modules of the target module number; two intermediate result output items of a MAJ module are used as One corresponding to the two input items of the UMA module, obtain the previous UMA module of the corresponding UMA module, and use the result of the previous UMA module to carry the output item as an input item of the corresponding UMA module, so that the The MAJ module of the target module number and the UAM module of the target module number are cascaded to generate the initial quantum circuit; wherein, the carry output item of the last MAJ module is used as an input item of the corresponding first UMA module
  • the CNOT quantum logic gate is added between the last MAJ module and the corresponding first UMA
  • a quantum multiplication operation device characterized in that the device comprises: an acquisition module for acquiring multiplicand data and multiplier data to be calculated, and converting the multiplicand data into a first target quantum state, and convert the multiplier data into a second target quantum state; wherein, the target quantum state stores the binary value of the data, and the number of qubits corresponding to the first target quantum state is at least the second target quantum state twice the number of qubits corresponding to the target quantum state; the control module is configured to control the first preset auxiliary bit according to the binary value of the current bit for each bit of the binary value stored in the second target quantum state The third target quantum state and the first target quantum state after the stored binary value is shifted to the left, perform the quantum state evolution corresponding to the addition operation, and obtain the evolved third target quantum state that stores the result of the addition operation, wherein the third target quantum state is The initial state of the three target quantum states is
  • An electronic device comprising a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute any one of C31-C39. method.
  • a storage medium characterized in that a computer program is stored in the storage medium, wherein the computer program is configured to execute the method described in any one of C31-C39 when running.
  • a quantum multiplication operation method is used to realize the basic multiplication operation in a quantum circuit, including acquiring the multiplicand data to be operated and the multiplier data, and converting the multiplicand data. Convert to the first target quantum state, convert the multiplier data to the second target quantum state, and control the first preset auxiliary bit for each bit in the binary value stored in the second target quantum state according to the binary value of the current bit.
  • the third target quantum state and the first target quantum state after the stored binary value is shifted to the left, perform the quantum state evolution corresponding to the addition operation, and obtain the third target quantum state that stores the result of the addition operation after evolution.
  • the three target quantum states are output as the multiplication result of the multiplicand data and the multiplier data.
  • the present invention fills the blank of related technologies through a technology capable of realizing basic arithmetic operations in quantum circuits.
  • FIG. 35 is a schematic flowchart of a quantum division operation method provided by an embodiment of the present invention, which may include the following steps:
  • S4201 Acquire the dividend data and the divisor data to be calculated, convert the dividend data into a first target quantum state, and convert the divisor data into a second target quantum state; wherein, the target quantum state includes: a symbol bit sub-quantum state of the data symbol and a numerical bit sub-quantum state representing the data value;
  • the existing amplitude encoding method can be used to convert the decimal data to be operated into a binary quantum state representation. For example, if the dividend data is 7, the signed binary represents 0111, the highest bit is 0 for positive numbers and 1 for negative numbers; the divisor data is 4, and the signed binary represents 011. It should be noted that, in this embodiment, the highest bits of the first target quantum state and the second target quantum state are both 0, that is, both the dividend and the divisor participating in the operation are positive numbers.
  • At least 4-bit quantum bits a.sign, a2, a1, a0 are obtained, 7 is encoded into the first target quantum state
  • 0111>
  • 1> are called sub-quantum states of
  • the number of execution times of the subtraction operation refers to the number of quantum state evolution times corresponding to the subtraction operation performed on the first target quantum state and the second target quantum state, that is, the number of iterations.
  • the quantum state evolution corresponding to the subtraction operation may be performed on the current first target quantum state and the second target quantum state, so as to obtain the first target quantum state including the subtraction operation result;
  • the quantum state evolution corresponding to the subtraction operation For the third target quantum state of the current first preset auxiliary bit and the fourth target quantum state of the current second preset auxiliary bit, perform the quantum state evolution corresponding to the subtraction operation to add the value contained in the current third target quantum state. 1; wherein, the initial value contained in the third target quantum state and the value contained in the fourth target quantum state are both -1;
  • the current first target quantum state and the second target quantum state are
  • the current third target quantum state of r.sign, r2, r1, r0 is the initial state, which can be set to
  • the quantum state of the qubit is usually initialized as
  • 0011> that currently contains the result of the subtraction operation is measured as
  • the current first target quantum state is
  • the current second target quantum state is
  • the quantum state evolution corresponding to the subtraction operation is continued to obtain: the first target quantum state
  • 1001> continue to perform the quantum state evolution corresponding to the subtraction operation, and obtain: the third target quantum state
  • 0000> continues to be added by 1;
  • 1001> is measured to be
  • the finally obtained third target quantum state may be output, wherein the value contained in the third target quantum state is the quotient of the division of the dividend data and the divisor data.
  • the third target quantum state finally obtained after the iteration is
  • 0001> can be directly output, or The value contained in the third target quantum state may be further converted into a decimal value of 1 and output.
  • the remainder of the division operation can also be calculated according to user requirements. Specifically, the sign bit sub-quantum state of the second target quantum state can be inverted, and the quantum state evolution corresponding to the subtraction operation is performed on the current first target quantum state and the second target quantum state after the sign bit is inverted, so as to obtain the dividend The remainder of dividing the data by the divisor data.
  • the final obtained first target quantum state is
  • the second target quantum state is
  • the third target quantum state is
  • the fourth target quantum state is
  • 0> of the second target quantum state is inverted
  • the inverted second target quantum state is
  • the evolved first target quantum state is
  • the second target quantum state contains the binary value 0011 (decimal value 3) as the remainder of the division of the dividend 7 and the divisor 4.
  • FIG. 36 is a schematic diagram of a quantum circuit for performing quantum division operations.
  • t is the classical bit that stores the measurement result
  • a.sign a are the qubit bits of the sign and numerical value of the encoded dividend data
  • b.sign, b are the qubit bits of the sign and value of the encoded divisor data
  • r.sign, r, r[0] form the first preset auxiliary bit
  • r.sign is the qubit of the sign of the coding quotient
  • r, r[0] is the qubit of the numerical value of the coding quotient
  • r[0 ] is the lowest bit
  • d.sign, d, d[0] form the second preset auxiliary bit
  • d.sign is the qubit of the sign of the coding quotient
  • d, d[0] is the qubit of the numerical value of the coding quotient
  • d[0 ] is the lowest bit
  • the subtractor module is a functional module that performs the quantum state evolution corresponding to the subtraction operation, Measure is the measurement operation, and Qwhile represents the quantum iteration operation in the second layer. That is, when the classical bit t ⁇ 1 of the stored measurement result, execute the aforementioned iterative operation until t reaches 1 and end the iteration; X represents the quantum logic gate X gate, and the execution sequence of the quantum circuit is from the first layer to the fifth layer. .
  • a preset sign bit qubit can also be obtained, and the qubit corresponding to the sign bit sub-quantum state of the first target quantum state and the sign bit sub-quantum state of the second target quantum state can also be obtained.
  • the corresponding qubit, the first preset auxiliary bit and the preset sign bit qubit perform a preset quantum logic gate operation to finally obtain the symbol value represented by the sign bit sub-quantum state in the third target quantum state.
  • FIG. 37 is a schematic diagram of a quantum circuit of a quantum division operation that supports sign bit operations.
  • sign bit qubits k[0] and k[1] are added.
  • the circle icon connected with vertical lines represents the quantum logic gate CNOT gate, the qubit corresponding to the timeline where the big circle is located is the controlled bit, and the qubit corresponding to the timeline where the solid dot is located is the control bit.
  • the quantum state evolution corresponding to the subtraction operation can be performed by the subtractor, which can include:
  • the quantum state of the third preset auxiliary bit as the subtracted quantum state containing the subtracted data and the subtracted quantum state containing the subtracted data, respectively, and obtain the quantum state of the third preset auxiliary bit according to the subtracted quantum state
  • the symbol bit sub-quantum state in the quantum state and the quantum state of the third preset auxiliary bit are controlled to perform the quantum state evolution corresponding to the complement operation of the subtracted quantum state, and the first complement quantum state is obtained; wherein , the first complement quantum state is a quantum state comprising the complement of the minuend data;
  • the two quantum states to be calculated have the following groups: the first target quantum state and the second target quantum state; the third target quantum state and the fourth target quantum state; the first target quantum state and the sign bit
  • the second target quantum state after inversion can be called the minuend quantum state
  • the data contained in the subtraction is called the minuend
  • the latter can be called the minuend quantum state
  • the data contained is the subtrahend.
  • the subtractor it is mainly used to realize the function of the subtractor.
  • the biggest difference between the subtractor and the following adder is that a negative number will be generated. Therefore, a binary processing method is used to add a sign bit to both the subtrahend and the minuend. , to indicate the positive or negative value of the value, and use two's complement for the operation.
  • the complement of positive numbers remains unchanged, and 1 is added after inversion of negative numbers except for the sign bit.
  • the sign bit is used to control whether to perform the complement operation
  • the X gate is used for inversion, and the addition of 1 can be realized by the adder. After the operation is completed in the case of complement, the target value is obtained by performing a complement operation on the result.
  • the minuend data and the subtrahend data to be calculated are acquired, and the minuend data and the subtrahend data are converted into a first target quantum state and a second target quantum state, respectively.
  • the target quantum state includes: a symbol bit sub-quantum state representing the data symbol and a numerical bit sub-quantum state representing the data value.
  • the quantum state evolution corresponding to the complement operation of the subtracted quantum state is controlled, and the subtracted quantum state can be processed for the quantum state.
  • the first sign bit qubit and the third preset auxiliary bit corresponding to the sign bit sub quantum state in the CNOT gate operation are performed, wherein the first sign bit qubit is the control bit, and the third preset auxiliary bit is the controlled bit; and , the CNOT gate can be replaced by other equivalent existing quantum logic gates or quantum logic gate combinations, which is also reasonable and feasible;
  • the quantum state evolves to obtain the evolved first's complement quantum state, otherwise, the subtracted quantum state is used as the first's complement quantum state; wherein, the quantum state of the third preset auxiliary bit after the CNOT gate operation is performed When it can be
  • the CNOT gate operation is performed on the current first sign bit qubit and the third preset auxiliary bit to restore the quantum state of the current third preset auxiliary bit; wherein, the first sign bit qubit is a control bit, so The third preset auxiliary bits are controlled bits.
  • the subtracted quantum state is assumed to be
  • 0011> is the sub-quantum state of the highest bit, that is, the
  • the set quantum bit q1 is initially
  • the quantum state evolution corresponding to the complement operation is not performed on the subtracted quantum state.
  • the minuend is a positive number, there is no need for complement in the subtraction operation, or in other words, its complement is itself, and
  • the CNOT gate can be executed again on the current g.sign and q1.
  • the quantum state of the g.sign bit is
  • 0> of the controlled bit q1 remains unchanged to restore q1 is in the
  • q 1 is the third preset auxiliary bit, which is used to control whether to perform the complement operation
  • the first target quantum state is g
  • g.sign is the sign bit in the first target quantum state Quantum state
  • the remaining g is the numerical sub-quantum state representing the data value
  • j is the fourth preset auxiliary bit, that is, the auxiliary bit that is set to a value of 1
  • p is the auxiliary bit used by the adder (the following the fifth preset auxiliary bit).
  • the above k is n+2 bits, that is, it includes: n bits j, 1 bit p, and 1 bit q1.
  • the quantum circuit shown in Figure 38 realizes the quantum circuit that performs the operation of calculating the complement of g.
  • the CNOT gate operation is performed on g.sign and q 1 , so that q 1 temporarily represents g.sign, and q 1 is used to control whether the search is performed or not.
  • Complement code after obtaining the complement code, restore q 1 .
  • the quantum state evolution corresponding to the complement operation is performed by controlling the subtracted quantum state, and the first complement quantum state is obtained.
  • the first preset auxiliary bit q 1 is used to control whether to perform the complementing operation. If g is negative, the complement operation of the negative number is performed. The complement of a negative number is the bitwise inversion except for the sign bit and then adding 1. If the bitwise inversion operation except for the sign bit is implemented with logic gates, it is only necessary to make X gates for all the numerical bits. 1 needs to be added. Therefore, by adding j and g, the value of j is set to 1, and p is the auxiliary bit of the adder. After adding g and j after the inversion of the value bits, what is stored on g is After taking the complemented value, restore q 1 for the next use.
  • the current subtraction quantum state performs the quantum state evolution corresponding to the complement operation to obtain a second complement quantum state; wherein, the second complement quantum state is a quantum state comprising the complement of the subtraction data;
  • the X gate operation can be performed on the second sign bit qubit corresponding to the sign bit quantum state in the subtraction quantum state to obtain the inverted sign bit quantum state; wherein, the X gate can use other equivalent quantum states. It is also reasonable and feasible to replace some quantum logic gates or combinations of quantum logic gates;
  • the CNOT gate operation is performed on the current second sign bit qubit and the third preset auxiliary bit to restore the current quantum state of the third preset auxiliary bit; wherein, the second sign bit qubit is a control bit, so The third preset auxiliary bits are controlled bits.
  • the decrement quantum state is assumed to be
  • 0100> is the sub-quantum state of the highest bit, that is, the
  • the X gate can be performed on h.sign, the corresponding sign bit quantum state
  • the quantum state of q1 after the CNOT gate operation is performed is
  • An implementation of the quantum state evolution corresponding to performing the complement operation is as follows:
  • 1100> can be negated by executing the X gate; in order to keep the dimensions consistent, the fourth preset auxiliary bits are preset 4-bit qubits j3, j2, j1, j0, The quantum state
  • the CNOT gate can be executed again on the current h.sign and q1.
  • the quantum state of the h.sign bit is
  • 1> of the controlled bit q1 is reversed as
  • Figure 39 is a schematic diagram of the quantum circuit of the quantum state evolution corresponding to performing the complement operation on g and h, referring to the above-mentioned similar method, the second target quantum state h performs the quantum state evolution corresponding to the complement operation , to get the second's complement quantum state.
  • S4303 Perform quantum state evolution corresponding to the addition operation on the first's complement quantum state and the second's complement quantum state, so as to evolve the first's complement quantum state into a quantum state including the subtrahend data a fifth target quantum state of the complement of the complement and the complement of the subtrahend data;
  • the first complement quantum state and the second complement quantum state are substituted into the quantum circuit of the adder, and the quantum state evolution corresponding to the addition operation is performed, thereby, the first complement quantum state is evolved to include all A third target quantum state of the sum of the complement of the minuend data and the complement of the subtrahend data.
  • the sixth target quantum state is output as the result of the subtraction operation between the subtrahend data and the subtrahend data; wherein, the sixth target quantum state is a quantum that includes the complement of the complement of the sum of the complements. state;
  • 0> of the third preset auxiliary bit control the fifth target quantum state
  • the quantum state corresponding to the code operation evolves, and the sixth target quantum state after evolution
  • the evolution of the quantum state corresponding to the complement operation can be the same as that described above. After the evolution, the quantum state of the third preset auxiliary bit is still restored to
  • the current subtraction quantum state is the second's complement quantum state
  • the current quantum state of the third preset auxiliary bit is
  • the quantum state evolution corresponding to the complement operation is further performed on the third target quantum state of the sum of the complement of the minuend data and the complement of the subtrahend data.
  • the purpose of making an X gate on j [ 0] is to set the value of j[0] to 1, which is convenient for the +1 operation in the complement.
  • the reason for doing the X gate operation on the sign bit of h is to convert gh to g+(-h). Then, we do the complement processing of both g and h. After the processing is completed, add the complements of g and h.
  • the quantum state evolution corresponding to the addition operation can be performed by the adder, which can include:
  • S4401 according to the number of qubit bits corresponding to the two quantum states to be operated, determine the number of target modules of the pre-cascading module MAJ module to be cascaded and the post-cascade module UMA module to be cascaded, wherein all The number of modules of the MAJ module is the same as the number of modules of the UMA module;
  • the two quantum states to be operated can be: the first's complement quantum state and the second's complement quantum state; the inversely subtracted quantum state and the quantum state of the fourth preset auxiliary bit
  • the first qubit in the circuit is the fifth preset auxiliary bit, which is initially in the
  • c represents the final carry item, corresponding to the preset carry auxiliary bit, and s is the output bit that does not contain carry.
  • the number of qubits corresponding to e and f is required to be the same, and the number of s, e and f is the same.
  • e [i] and f [i] are respectively the i-th bit of the quantum state corresponding to the two addends, and c [i] is the upper-order carry bit.
  • the first quantum bit is the fifth preset auxiliary bit, which corresponds to c 0 in the quantum circuit.
  • the first MAJ module includes three input quantum states and three corresponding output quantum states, wherein the three input quantum states are c 0 , e 0 , and f 0 respectively, and e 0 is the first quantum state to be operated. 0-bit quantum state, f 0 is the 0th-bit quantum state of the second quantum state to be operated, c 0 is the quantum state of the fifth preset auxiliary bit, and the initial value is 0, that is, no carry.
  • the three output quantum states are c 1 , c 1 is the carry after the addition of e 0 and f 0.
  • the three input quantum states of the next MAJ module are c 1 , e 1 , and f 1 , and the three output quantum states are respectively c 2 , and so on to the last MAJ module.
  • the first UMA module includes three input quantum states and three corresponding output quantum states, wherein the three output quantum states of the MAJ module are the three input quantum states of the corresponding UMA module, and the three output quantum states are respectively c 0 , s 0 , e 0 , s 0 is the result of the addition of e 0 and f 0 without carry. Similarly, s1 is the result of the addition of e 1 and f 1 without carry, and so on, c4 is the final carry term. It should be noted that, in practical applications, without the requirement of calculating the final carry, the quantum circuit corresponding to c4 may not be set.
  • the number of modules of the MAJ module and the number of UMA modules can be determined according to the number of sub-quantum states contained in any quantum state to be calculated.
  • One sub-quantum state corresponds to one qubit
  • the number of modules of the MAJ module is and the same number of UMA modules. Shown in the figure is only an example, encoding e and f each requires 4 qubits, and the number of MAJ modules and UMA modules are both 4.
  • the MAJ module and the UMA module constitute the front and rear cascade units of the adder.
  • the MAJ module can be used to extract the carry term of any step and pass it to the next level to calculate the final carry term.
  • the UMA module extracts the information of c and transmits it to the upper-level UMA, and also calculates the s (result item) of each level, and restores the information of e.
  • the MAJ module and the UMA module both include three input items and three output items.
  • the three output items of a MAJ cascade module can be used as the three inputs of a corresponding UMA cascade module. Item, to cascade the MAJ cascading module and the corresponding UMA cascading module to generate the target quantum circuit corresponding to the adder, wherein the MAJ cascading module is composed of the MAJ modules of the number of the target modules.
  • the UMA cascading module is determined by cascading between UMA modules of the target number of modules.
  • the three input items of the MAJ module include a carry input item and two sub-quantum state input items to be calculated
  • the three output items of the MAJ module include a carry output item and two intermediate result output items
  • the three input items of the UMA module include a carry output item and two intermediate result output items corresponding to the MAJ module
  • the three output items of the UMA module include a result carry output item, an accumulation sum output item, and a to-be-calculated item.
  • the carry output item output by the previous MAJ module and the two input items of the sub-quantum state to be calculated can be used as the three input items of the next MAJ module, so that the MAJ of the target module number modules are cascaded;
  • a CNOT quantum logic gate is added between the last MAJ module and the corresponding first UMA module in the initial quantum circuit, wherein the qubit corresponding to the carry output item of the MAJ module is used as the control bit, and the preset carry
  • the auxiliary bits act as controlled bits to generate the target quantum circuit of the adder.
  • the CNOT gate and the carry auxiliary bit may not be set.
  • the three output bits of the MAJ module are used as the three input bits of the UMA module, so that the same number of MAJ modules and UMA modules are Concatenation is performed to generate the target quantum circuit corresponding to the adder.
  • the hollow circle and the solid circle connected in the circuit diagram represent the CNOT gate operation
  • the hollow circle corresponding to the qubit is the control bit
  • the solid circle corresponding to the controlled bit is the hollow circle corresponding to the controlled bit.
  • the MAJ module is a MAJ quantum circuit
  • the UMA module is a UMA quantum circuit.
  • Both the MAJ quantum circuit and the UMA quantum circuit include two CNOT quantum logic gates and one TOFFOLI quantum logic gate.
  • the instruction, before the step of cascading the MAJ modules and the UMA modules of the number of the target modules to generate the target quantum circuit corresponding to the adder also includes: obtaining the two CNOT quantum logic gates and a TOFFOLI quantum logic
  • the operation qubits corresponding to the gates, the control relationship between the operation qubits, and the timing relationship between the two CNOT quantum logic gates and one TOFFOLI quantum logic gate; according to the operation qubits, the control relationship and the Timing relationship, the two CNOT quantum logic gates and one TOFFOLI quantum logic gate are constructed to generate the MAJ quantum circuit or the UMA quantum circuit, as the corresponding MAJ module or UMA module.
  • the MAJ module and the UMA module constitute the front and rear cascade units of the adder.
  • the MAJ module is used to extract the carry term after the addition operation of each stage and pass it to the next stage, thereby calculating the final carry term.
  • the MAJ module can be mainly composed of three logic gates, namely two CNOT gates and one Toffoli gate.
  • the function of the CNOT gate (the first and second logic gates from left to right in Figure 45) is to add the control bit to the target bit to form a modulo 2 addition, which is an exclusive OR operation, and obtain (e i +c i )%2, (e i +f i )%2, the order of the two CNOT gates can be swapped.
  • the front-stage cascade unit of the quantum adder is constituted by two CNOT gates and one TOFFOLI gate.
  • Example 1 e i is 1, f i is 1, and c i is 1.
  • the MAJ module starts to add ei to ci , the value on ci becomes 0, then adds ei to fi , the value on fi also becomes 0, and finally adds fi and ci to On e i , the value of e i becomes 1, that is, the carry of c i+1 is 1.
  • Example 2 e i is 0, f i is 1, and c i is 1.
  • the MAJ module starts to add ei to ci , the value on ci becomes 1, then adds ei to fi , the value on fi also becomes 1, and finally adds fi and ci to On e i , the value of e i becomes 1, that is, the carry of c i+1 is 1.
  • the UMA module is used for the latter stage of the cascaded adder.
  • the implementation of the UMA module is similar to the MAJ module.
  • the Toffoli gate is used first (the first from left to right in Figure 47).
  • Example 1 ( ei + c i ) % 2 is 0, ( ei +fi )% 2 is 0, and c i +1 is 1.
  • Example 2 ( ei + c i ) % 2 is 1, ( ei +fi )% 2 is 1, and c i +1 is 1.
  • the adder that is, the target quantum circuit
  • the corresponding binary representation of the target quantum state calculation result including the carry term and the result term obtained by the direct addition of each sub-quantum state. Then directly output the target quantum state result
  • the quantum division operation method provided by the present invention is used to realize the basic arithmetic operation operation in the quantum circuit, obtain the dividend data and the divisor data to be operated, and convert the dividend data into the first target quantum state, and the The divisor data is converted into the second target quantum state; for the first target quantum state and the second target quantum state, the quantum state evolution corresponding to the subtraction operation is iteratively performed, and the number of times the subtraction operation is performed is counted until Subtract the dividend data to a negative number; convert the finally obtained counting result as the quotient of dividing the dividend data and the divisor data into decimal representation and output, so as to realize basic arithmetic operations that can be used in quantum circuits operation, filling the gaps in related technologies.
  • FIG. 48 is a schematic structural diagram of a quantum division operation device provided by an embodiment of the present invention, which may include:
  • the conversion module 41501 is used to obtain the dividend data and the divisor data to be calculated, convert the dividend data into a first target quantum state, and convert the divisor data into a second target quantum state; wherein, the target quantum state Including: a symbol bit sub-quantum state representing the data symbol and a numerical bit sub-quantum state representing the data value;
  • the operation module 41502 is used to iteratively execute the quantum state evolution corresponding to the subtraction operation on the first target quantum state and the second target quantum state, and count the execution times of the subtraction operation until the dividend is The data is reduced to a negative number; wherein, the minuend of each execution of the subtraction operation is the subtraction result of the last execution of the subtraction operation, and the subtrahend is the data of the divisor;
  • the output module 41503 is configured to output the finally obtained counting result as the quotient of dividing the dividend data by the divisor data.
  • the operation module is specifically used for:
  • the quantum state evolution corresponding to the subtraction operation For the third target quantum state of the current first preset auxiliary bit and the fourth target quantum state of the current second preset auxiliary bit, perform the quantum state evolution corresponding to the subtraction operation to add the value contained in the current third target quantum state. 1; wherein, the initial value included in the third target quantum state and the value included in the fourth target quantum state are both -1;
  • the output module is specifically used for:
  • the finally obtained third target quantum state is output, wherein the value contained in the third target quantum state is the quotient of dividing the dividend data by the divisor data.
  • the device further includes:
  • the first execution module is used to invert the sign bit sub-quantum state of the second target quantum state, and perform the quantum state corresponding to the subtraction operation on the second target quantum state after the current first target quantum state and the sign bit are inverted Evolving to obtain the remainder of dividing the dividend data by the divisor data.
  • the device further includes:
  • the second execution module is configured to obtain a preset sign bit qubit, for the qubit corresponding to the sign bit sub-quantum state of the first target quantum state, the qubit corresponding to the sign bit sub-quantum state of the second target quantum state,
  • the first preset auxiliary bit and the preset sign bit qubit perform a preset quantum logic gate operation to finally obtain the sign value represented by the sign bit sub-quantum state in the third target quantum state.
  • the computing module includes:
  • the first's complement arithmetic unit is used to obtain the quantum state of the third preset auxiliary bit as the subtrahened quantum state containing the subtracted data and the subtracted quantum state containing the subtracted data for the two quantum states to be calculated. state, according to the quantum state of the sign bit in the subtracted quantum state and the quantum state of the third preset auxiliary bit, control the quantum state evolution corresponding to the complement operation of the subtracted quantum state to obtain the first One's complement quantum state; wherein, the first complement quantum state is a quantum state comprising the complement of the minuend data;
  • the second’s complement arithmetic unit is configured to perform the quantum state evolution of the sign bit inversion response for the sign bit sub-quantum state in the subtraction quantum state, and according to the inverted sign bit sub-quantum state and the third preset
  • the quantum state of the auxiliary bit controls the current subtraction quantum state to perform the quantum state evolution corresponding to the complement operation, and obtains the second complement quantum state; wherein, the second complement quantum state is the complement of the subtraction data including the subtraction data. the quantum state of the code;
  • the addition operation unit is used to perform the quantum state evolution corresponding to the addition operation on the first complement quantum state and the second complement quantum state, so as to evolve the first complement quantum state to include the a fifth target quantum state of the sum of the complement of the subtrahend data and the complement of the subtrahend data;
  • a third complement operation unit configured to control the fifth target quantum state to perform a complement operation corresponding to the symbol bit sub-quantum state in the fifth target quantum state and the quantum state of the third preset auxiliary bit
  • the quantum state evolution of obtains the sixth target quantum state after evolution, which is output as the result of the subtraction operation of the subtrahend data and the subtrahend data; wherein, the sixth target quantum state contains the complement code the quantum state of the complement of the sum;
  • the fourth complement operation unit is configured to control the current subtraction quantum state to perform the quantum state evolution corresponding to the complement operation according to the sign bit quantum state in the current subtraction quantum state and the current quantum state of the third preset auxiliary bit, And perform the quantum state evolution of the sign bit inversion response to the sign bit quantum state in the current decrement quantum state, so as to restore the current decrement quantum state.
  • the first complement arithmetic unit is specifically used for:
  • the third preset auxiliary bit is a controlled bit
  • the CNOT gate operation is performed on the current first sign bit qubit and the third preset auxiliary bit to restore the quantum state of the current third preset auxiliary bit; wherein, the first sign bit qubit is a control bit, so The third preset auxiliary bits are controlled bits.
  • the second complement arithmetic unit is specifically used for:
  • the CNOT gate operation is performed on the current second sign bit qubit and the third preset auxiliary bit to restore the current quantum state of the third preset auxiliary bit; wherein, the second sign bit qubit is a control bit, so The third preset auxiliary bits are controlled bits.
  • the addition unit includes:
  • the determining subunit is used to determine the number of target modules of the pre-cascade module MAJ module to be cascaded and the post-cascade module UMA module to be cascaded according to the number of qubit bits corresponding to the two quantum states to be operated , wherein the number of modules of the MAJ module is the same as the number of modules of the UMA module;
  • the cascade subunit is used to cascade the MAJ module and the UMA module of the target module number according to the addition instruction to generate the target quantum circuit corresponding to the adder;
  • the operation subunit is configured to perform an addition operation on each sub-quantum state of the two quantum states to be operated through the target quantum circuit to generate and output the result of the target quantum state.
  • the MAJ module is a MAJ quantum circuit
  • the UMA module is a UMA quantum circuit
  • both the MAJ quantum circuit and the UMA quantum circuit include two CNOT quantum logic gates and one TOFFOLI quantum logic gate; the addition
  • the arithmetic unit also includes:
  • the obtaining subunit is used to obtain the operation qubits corresponding to the two CNOT quantum logic gates and one TOFFOLI quantum logic gate, the control relationship between the operation qubits, and the two CNOT quantum logic gates and one TOFFOLI quantum logic gate temporal relationship between;
  • the MAJ module and the UMA module include three input items and three output items; the cascaded subunits are specifically used for:
  • three output items of a MAJ cascade module are used as three input items of a corresponding UMA cascade module, so as to cascade the MAJ cascade module and the corresponding UMA cascade module to generate the The target quantum circuit corresponding to the adder, wherein the MAJ cascade module is determined by the cascade between MAJ modules of the target module number, and the UMA cascade module is determined by the target module number between the UMA modules Cascade OK.
  • the three input items of the MAJ module include a carry input item and two sub-quantum state input items to be calculated
  • the three output items of the MAJ module include a carry output item and two intermediate result output items
  • the three input items of the UMA module include a carry output item and two intermediate result output items corresponding to the MAJ module
  • the three output items of the UMA module include a result carry output item, an accumulation sum output item, and a to-be-calculated item.
  • Sub-quantum state input; the cascaded sub-unit is specifically used for:
  • the carry output item output by the previous MAJ module and the two sub-quantum state input items to be calculated are used as the three input items of the next MAJ module, so that the MAJ modules of the target number of modules are graded. link;
  • a CNOT quantum logic gate is added between the last MAJ module and the corresponding first UMA module in the initial quantum circuit, wherein the qubit corresponding to the carry output item of the MAJ module is used as the control bit, and the preset carry
  • the auxiliary bits act as controlled bits to generate the target quantum circuit of the adder.
  • Yet another embodiment of the present invention provides an electronic device comprising a memory and a processor, the memory having a computer program stored therein, the processor being configured to run the computer program to perform a method as described below:
  • the target quantum state includes: a symbol bit sub-quantum state of the data symbol and a numerical bit sub-quantum state representing the data value;
  • Yet another embodiment of the present invention provides a storage medium, where a computer program is stored in the storage medium, wherein the computer program is configured to execute the following method when running:
  • the target quantum state includes: a symbol bit sub-quantum state of the data symbol and a numerical bit sub-quantum state representing the data value;
  • a quantum division operation method characterized in that the method comprises: acquiring dividend data and divisor data to be calculated, converting the dividend data into a first target quantum state, and converting the divisor data into a first target quantum state.
  • Two target quantum states wherein, the target quantum state includes: a symbol bit sub-quantum state representing the data symbol and a numerical bit sub-quantum state representing the data value;
  • the quantum state evolution corresponding to the subtraction operation For the first target quantum state and the second target quantum state, iteratively execute the quantum state evolution corresponding to the subtraction operation, and count the execution times of the subtraction operation until the dividend data is reduced to a negative number; wherein , the minuend of each execution of the subtraction operation is the subtraction result of the last execution of the subtraction operation, and the subtrahend is the divisor data; the count result obtained at last is used as the quotient of dividing the dividend data and the divisor data. output.
  • C42 The method according to C41, characterized in that, for the first target quantum state and the second target quantum state, the quantum state evolution corresponding to the subtraction operation is iteratively performed, and the execution of the subtraction operation is performed. Counting the number of times until the dividend data is reduced to a negative number, including: performing the quantum state evolution corresponding to the subtraction operation on the current first target quantum state and the second target quantum state, so as to obtain the first target quantum state including the subtraction operation result.
  • the target quantum state for the third target quantum state of the current first preset auxiliary bit and the fourth target quantum state of the current second preset auxiliary bit, perform the quantum state evolution corresponding to the subtraction operation, so as to transform the current third target quantum state Add 1 to the included value; wherein, the initial value included in the third target quantum state and the value included in the fourth target quantum state are both -1; measure the sign bit of the first target quantum state that currently includes the result of the subtraction operation Quantum state, determine whether the value of the sign bit of the first target quantum state that currently contains the subtraction result is 0; if the value of the sign bit of the first target quantum state that currently contains the subtraction result is 0, return to execute the For the current first target quantum state and the current second target quantum state, perform the steps of quantum state evolution corresponding to the subtraction operation, until it is determined that the value of the sign bit of the first target quantum state that currently contains the subtraction operation result is 1.
  • outputting the finally obtained counting result as the quotient of dividing the dividend data by the divisor data includes: converting the finally obtained third target The quantum state is output, wherein the value contained in the third target quantum state is the quotient of dividing the dividend data by the divisor data.
  • C45 The method according to any one of C41-C44, characterized in that the method further comprises: acquiring a preset sign bit qubit, for the qubit corresponding to the sign bit sub-quantum state of the first target quantum state , the qubit corresponding to the sign bit sub-quantum state of the second target quantum state, the first preset auxiliary bit and the preset sign bit qubit, perform a preset quantum logic gate operation to finally obtain the first The sign value represented by the sign bit sub quantum state in the three target quantum states.
  • the first complement quantum state is the complement code containing the minuend data
  • the quantum state of the sign bit quantum state in the subtraction quantum state is performed by the quantum state evolution of the sign bit negation reaction, and the quantum state of the symbol bit quantum state after the negation and the quantum state of the third preset auxiliary bit are performed.
  • the second complement quantum state is a quantum state that includes the complement of the subtraction data;
  • For the first's complement quantum state and the second's complement quantum state perform the quantum state evolution corresponding to the addition operation to evolve the first's complement quantum state into the complement code including the minuend data and the fifth target quantum state of the complement of the subtrahend data; control the fifth target quantum state according to the sign bit sub quantum state in the fifth target quantum state and the quantum state of the third preset auxiliary bit
  • the target quantum state performs the quantum state evolution corresponding to the complement operation, and obtains the sixth target quantum state after evolution, which is output as the result of the subtraction operation between the minuend data and the subtrahend data; wherein, the sixth target quantum state is output.
  • the target quantum state is a quantum state containing the complement of the complement of the complement; according to the sign bit quantum state in the current subtraction quantum state and the current quantum state of the third preset auxiliary bit, the current subtraction quantum state is controlled to execute the calculation.
  • the quantum state evolution corresponding to the complement operation is performed, and the quantum state evolution corresponding to the sign bit negation is performed on the sign bit quantum state in the current subtraction quantum state, so as to restore the current subtraction quantum state.
  • C48 The method according to any one of C41-C47, wherein the sign bit sub-quantum state in the subtraction quantum state performs the quantum state evolution of the sign bit negation reaction, and according to the inverted quantum state The quantum state of the sign bit and the quantum state of the third preset auxiliary bit, and controlling the quantum state evolution corresponding to the current subtraction quantum state to perform the complement operation, including: performing the quantum state evolution of the sign bit in the subtraction quantum state For the corresponding second sign bit qubit, perform the X gate operation to obtain the inverted sign bit sub-quantum state; perform the CNOT gate operation on the current second sign bit qubit and the third preset auxiliary bit, wherein the second The sign bit qubit is a control bit, and the third preset auxiliary bit is a controlled bit; according to the current quantum state of the third preset auxiliary bit after performing the CNOT gate operation, it is controlled whether to perform a complement code for the current subtraction quantum state Calculate the corresponding quantum state evolution; if so, invert the non-sign bit quantum
  • the quantum state evolution corresponding to the execution of the addition operation comprises: according to the number of bits of the qubit bits corresponding to the two quantum states to be operated, determining The number of target modules of the front cascading module MAJ module to be cascaded and the rear cascading module UMA module to be cascaded, wherein the number of modules of the MAJ module is the same as the number of modules of the UMA module; according to the addition instruction, the MAJ module and the UMA module of the target module number are cascaded to generate the target quantum circuit corresponding to the adder; each sub-quantum state of the two quantum states to be calculated is performed through the target quantum circuit.
  • the addition operation generates the target quantum state result and outputs it.
  • C410 The method according to any one of C41-C49, wherein the MAJ module is a MAJ quantum circuit, the UMA module is a UMA quantum circuit, and both the MAJ quantum circuit and the UMA quantum circuit include Two CNOT quantum logic gates and one TOFFOLI quantum logic gate, before the step of cascading the MAJ modules and UMA modules of the target module number according to the addition instruction to generate the target quantum circuit corresponding to the adder, further comprising: : Obtain the operation qubits corresponding to the two CNOT quantum logic gates and one TOFFOLI quantum logic gate, the control relationship between the operation qubits, and the timing relationship between the two CNOT quantum logic gates and one TOFFOLI quantum logic gate ; According to the operation qubit, the control relationship and the timing relationship, the two CNOT quantum logic gates and one TOFFOLI quantum logic gate are constructed to generate the MAJ quantum circuit or the UMA quantum circuit, as the corresponding MAJ module or UMA module.
  • the MAJ modules and UMA modules of the number of modules are cascaded, and the step of generating the target quantum circuit corresponding to the adder specifically includes: according to the addition instruction, using three output items of a MAJ cascade module as a corresponding UMA cascade module three input items, to cascade the MAJ cascade module and the corresponding UMA cascade module to generate the target quantum circuit corresponding to the adder, wherein the MAJ cascade module is composed of the target module
  • the number of MAJ modules is cascaded and determined, and the UMA cascade module is determined by cascaded between the UMA modules of the target module number.
  • C412 The method according to any one of C41-C411, wherein the three input items of the MAJ module include a carry input item and two sub-quantum state input items to be calculated, and the three input items of the MAJ module
  • the output items include one carry output item and two intermediate result output items
  • the three input items of the UMA module include one carry output item and two intermediate result output items corresponding to the MAJ module
  • the three output items of the UMA module The item includes a result carry output item, an accumulation sum output item, and a sub-quantum state input item to be calculated.
  • the three output items of a MAJ cascade module are used as a corresponding UMA cascade module.
  • the step of generating the target quantum circuit corresponding to the adder specifically includes: according to the addition instruction, the carry output item output by the previous MAJ module And the two sub-quantum state input items to be calculated are used as three input items of the next MAJ module, to cascade the MAJ modules of the target module number; two intermediate result output items of a MAJ module are used as One corresponding to the two input items of the UMA module, obtain the previous UMA module of the corresponding UMA module, and use the result of the previous UMA module to carry the output item as an input item of the corresponding UMA module, so that the The MAJ module of the target module number and the UAM module of the target module number are cascaded to generate the initial quantum circuit; wherein, the carry output item of the last MAJ module is used as an input item of the corresponding first UMA module ; Add a CNOT quantum logic gate between the last MAJ module and the corresponding first
  • a quantum division operation device characterized in that the device comprises: a conversion module for acquiring dividend data and divisor data to be calculated, converting the dividend data into a first target quantum state, and converting the dividend data into a first target quantum state.
  • the divisor data is converted into a second target quantum state; wherein, the target quantum state includes: a symbol bit sub-quantum state representing the data symbol and a numerical bit sub-quantum state representing the data value; an operation module, used for the For a target quantum state and the second target quantum state, iteratively execute the quantum state evolution corresponding to the subtraction operation, and count the execution times of the subtraction operation until the dividend data is reduced to a negative number; wherein, each execution The minuend of the subtraction operation is the subtraction result of the last subtraction operation, and the subtrahend is the divisor data; the output module is used for taking the finally obtained counting result as the quotient of dividing the dividend data and the divisor data to output.
  • An electronic device comprising a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute any one of C41-C412. method.
  • a storage medium wherein a computer program is stored in the storage medium, wherein the computer program is configured to execute the method described in any one of C41-C412 when running.
  • the quantum division operation method obtains the dividend data and divisor data to be calculated, converts the dividend data into a first target quantum state, and converts the divisor data into a second quantum state. target quantum state; for the first target quantum state and the second target quantum state, iteratively execute the quantum state evolution corresponding to the subtraction operation, and count the execution times of the subtraction operation until the dividend data is decremented. is a negative number; the finally obtained counting result is output as the quotient of the division of the dividend data and the divisor data, so as to realize basic arithmetic operations that can be used in quantum circuits, filling the gap in the related art.
  • FIG. 49 is a schematic flowchart of a quantum division operation method with precision provided by an embodiment of the present invention, which may include the following steps:
  • S5201 Acquire the dividend data and the divisor data to be calculated, convert the dividend data into a first target quantum state, and convert the divisor data into a second target quantum state; wherein, the target quantum state includes: a symbol bit sub-quantum state of the data symbol and a numerical bit sub-quantum state representing the data value;
  • the existing amplitude encoding method can be used to convert the decimal data to be operated into a binary quantum state representation. For example, if the dividend data is 7, the signed binary represents 0111, the highest bit is 0 for positive numbers and 1 for negative numbers; the divisor data is 4, and the signed binary represents 011. It should be noted that, in this embodiment, the highest bits of the first target quantum state and the second target quantum state are both 0, that is, both the dividend and the divisor participating in the operation are positive numbers.
  • 5-bit qubits a.sign, a3, a2, a1, a0 can be obtained, and 7 is encoded into the first target quantum state of a.sign, a3, a2, a1, a0
  • 00111>
  • 1> are called sub quantum states of
  • the number of executions of the subtraction operation here refers to the number of quantum state evolution times corresponding to the subtraction operation performed on the first target quantum state and the second target quantum state, that is, the number of iterations.
  • the quantum state evolution corresponding to the subtraction operation may be performed on the current first target quantum state and the second target quantum state, so as to obtain the first target quantum state including the subtraction operation result;
  • the quantum state evolution corresponding to the subtraction operation For the third target quantum state of the current first preset auxiliary bit and the fourth target quantum state of the current second preset auxiliary bit, perform the quantum state evolution corresponding to the subtraction operation to add the value contained in the current third target quantum state. 1; wherein, the initial value contained in the third target quantum state and the value contained in the fourth target quantum state are both -1;
  • the current first target quantum state and the second target quantum state are
  • 00100> to subtract the value 00111 contained in
  • the current third target quantum state of r.sign, r2, r1, r0 is the initial state, which can be set to
  • the quantum state of the qubit is usually initialized as
  • 00011> that currently contains the result of the subtraction operation is measured as
  • the current first target quantum state is
  • the current second target quantum state is
  • the quantum state evolution corresponding to the subtraction operation is continued to obtain: the first target quantum state
  • 1001> continue to perform the quantum state evolution corresponding to the subtraction operation, and obtain: the third target quantum state
  • 0000> continues to be added by 1;
  • 10001> is measured to be
  • the finally obtained third target quantum state may be output, wherein the value contained in the third target quantum state is the quotient of the division of the dividend data and the divisor data.
  • the third target quantum state finally obtained after the iteration is
  • 0001 can be directly output >, the value contained in the third target quantum state can be further converted into a decimal value of 1 and output.
  • iteratively performing the quantum state evolution corresponding to the decimal place operation of the quotient may include:
  • S52031 Invert the sign bit sub quantum state of the current second target quantum state, and perform the quantum state evolution corresponding to the subtraction operation on the current first target quantum state and the second target quantum state after the inversion of the sign bit, so as to transform the current first target quantum state and the second target quantum state after the sign bit is inverted.
  • a target quantum state evolves into a quantum state comprising the remainder binary value of dividing the dividend data by the divisor data;
  • S52032 Shift each sub-quantum state of the current first target quantum state by one bit to the left, invert the sign bit quantum state of the current second target quantum state, and perform a left-shifted first target quantum state and a second sub-quantum state. Inverting the second target quantum state, iteratively executes the quantum state evolution corresponding to the subtraction operation, and counts the execution times of the subtraction operation until the first target quantum state shifted to the left by one bit is reduced to a negative number , obtain a fractional quantum state containing the binary value of the counting result on the preset intermediate bit qubit;
  • S52033 Swap the last bit quantum state of the fractional quantum state with the initial quantum state
  • the decimal place of the quotient retains 3-digit precision.
  • Step 1 Negate the sign bit quantum state
  • the evolved first target quantum state becomes
  • Step 2 Shift the whole first target quantum state
  • Step 3 Swap the last bit quantum state
  • the quantum state is output to f2, the second iteration is output to f1, and the third iteration is output to f0.
  • FIG. 50 is a schematic diagram of a quantum circuit for performing quantum division operation with precision.
  • t is the classical bit that stores the measurement result
  • a.sign a are the qubit bits of the sign and value of the encoded dividend data, corresponding to the first target quantum state;
  • b.sign, b are the qubit bits of the sign and value of the encoded divisor data, corresponding to the second target quantum state;
  • r.sign, r, r[0] form the first preset auxiliary bit
  • r.sign is the qubit of the sign of the coding quotient
  • r, r[0] is the qubit of the numerical value of the coding quotient
  • r[0 ] is the lowest bit
  • d.sign, d, and d[0] form the second preset auxiliary bit
  • d.sign encodes the sign bit
  • d encodes the value bit
  • the corresponding initial state of the second preset auxiliary bit is For the fourth target quantum state of the 0 state, the symbol bit quantum state corresponding to d.sign and the numerical bit quantum state corresponding to d[0] are inverted through the X gate to obtain the fourth target quantum state with a value of -1, using For the addition of 1 in the subtractor, it plays the role of counting;
  • kk is the auxiliary qubit required by the subtractor module in the upper half of the line, a total of n+3 bits, k is the auxiliary qubit required by the subtractor module in the lower half of the line, a total of n+2 bits, the n+2 Bits share the first (n+2) auxiliary qubits in kk.
  • the difference in the figure shows that kk actually contains k; f[cnt-1], f[i], f[0] represent preset precision bit qubits bit;
  • the subtractor module is a functional module that performs the quantum state evolution corresponding to the subtraction operation, X represents the quantum logic gate X gate, Qwhile represents the quantum iterative operation, and the execution sequence of the quantum circuit is from the first layer to the fifth layer:
  • the measurement operation in Qwhile is used to measure the value of a.sign and store it in the classical bit t.
  • t ⁇ 1 execute the iterative operation in Qwhile, and execute sum++ to store the sum value in the corresponding classical bit.
  • the iteration ends when t reaches 1;
  • Second layer The number of iterations of the second layer is cnt times, and cnt is the decimal precision of the required quotient. In each iteration of the second layer, the Qwhile layer of the second layer also needs to perform corresponding iterations.
  • the third layer the number of iterations of the third layer is cnt times, when s[cnt-i-1]>0, execute the subtractor iteration operation in this layer Qwhile, and execute s[cnt-i-1]-- , until s[cnt-i-1] is less than or equal to 0, the iteration in Qwhile ends;
  • the inverse left shift operation is the inverse operation of left shift by one;
  • Fourth layer when sum>0, execute the subtractor iteration operation in Qwhile of this layer, and execute sum--, until sum is less than or equal to 0, end the iteration in Qwhile; the two X gates at the bottom left of the fourth layer are used Inverting the quantum state of d.sign and d[0] again, the realization is restored to the initial state.
  • s[i] sum can be restored to the initial value 0, and a.sign, a, b.sign, b, d.sign, d[0] can be restored to In the initial state, the integer bits of the quotient are obtained on r, and the preset precision decimal places of the quotient are obtained on f, and the quantum state of the auxiliary qubit will be restored, so that it can be reused.
  • the quantum states of the qubits f2, f1 and f0 of the 3-bit preset precision bits are finally obtained as
  • 0>
  • the value is 110 (0.75 decimal).
  • the integer bit binary value of the quotient obtained by the foregoing calculation is 0001 (decimal 1), and the final quotient of the dividend 7 and the divisor 4 can be obtained as 1.75.
  • a preset sign bit qubit can also be obtained, the qubit corresponding to the sign bit quantum state of the first target quantum state, and the sign bit quantum state of the second target quantum state.
  • the qubit corresponding to the quantum state, the first preset auxiliary bit and the preset sign bit qubit perform a preset quantum logic gate operation to finally obtain the symbol value represented by the sign bit sub-quantum state in the third target quantum state.
  • FIG. 51 is a schematic diagram of a quantum circuit for a quantum division operation with precision that supports sign bit operations.
  • the positive divider with precision is the quantum circuit shown in Figure 50, and the sign bit qubits u[0] and u[1] are added; the circle icon connected with a vertical line represents the quantum logic gate CNOT gate, and the big circle is the quantum logic gate CNOT gate.
  • the qubit corresponding to the timeline at is the controlled bit, and the qubit corresponding to the timeline where the solid point is located is the control bit;
  • the classical bits have a total of cnt+2 bits, including in Figure 50: 1 bit sum, cnt bit s[i ], 1 bit t;
  • v is a total of 3n+3 bits of auxiliary quantum bits, including in Figure 50: n+3 bits kk, n bits d.sign and d, and n bits cc.sign and cc.
  • the quantum state evolution corresponding to the subtraction operation can be performed by the subtractor, which can include:
  • the quantum state of the third preset auxiliary bit as the subtracted quantum state containing the subtracted data and the subtracted quantum state containing the subtracted data, respectively, and obtain the quantum state of the third preset auxiliary bit according to the subtracted quantum state.
  • the symbol bit sub-quantum state in the quantum state and the quantum state of the third preset auxiliary bit are controlled to perform the quantum state evolution corresponding to the complement operation of the subtracted quantum state, and the first complement quantum state is obtained; wherein , the first complement quantum state is a quantum state comprising the complement of the minuend data;
  • the two quantum states to be calculated have the following groups: the first target quantum state and the second target quantum state; the third target quantum state and the fourth target quantum state; the first target quantum state and the sign bit
  • the second target quantum state after inversion can be called the minuend quantum state
  • the data contained in the subtraction is called the minuend
  • the latter can be called the minuend quantum state
  • the data contained is the subtrahend.
  • the subtractor it is mainly used to realize the function of the subtractor.
  • the biggest difference between the subtractor and the following adder is that a negative number will be generated. Therefore, a binary processing method is used to add a sign bit to both the subtrahend and the minuend. , to indicate the positive or negative value of the value, and use two's complement for the operation.
  • the complement of positive numbers remains unchanged, and 1 is added after inversion of negative numbers except for the sign bit.
  • the sign bit is used to control whether to perform the complement operation
  • the X gate is used for inversion, and the addition of 1 can be realized by the adder. After the operation is completed in the case of complement, the target value is obtained by performing a complement operation on the result.
  • the minuend data and the subtrahend data to be calculated are acquired, and the minuend data and the subtrahend data are converted into a first target quantum state and a second target quantum state, respectively.
  • the target quantum state includes: a symbol bit sub-quantum state representing the data symbol and a numerical bit sub-quantum state representing the data value.
  • the quantum state evolution corresponding to the complement operation of the subtracted quantum state is controlled, and the subtracted quantum state can be processed for the quantum state.
  • the first sign bit qubit and the third preset auxiliary bit corresponding to the sign bit sub quantum state in the CNOT gate operation are performed, wherein the first sign bit qubit is the control bit, and the third preset auxiliary bit is the controlled bit; and , the CNOT gate can be replaced by other equivalent existing quantum logic gates or quantum logic gate combinations, which is also reasonable and feasible;
  • the quantum state evolves to obtain the evolved first's complement quantum state, otherwise, the subtracted quantum state is used as the first's complement quantum state; wherein, the quantum state of the third preset auxiliary bit after the CNOT gate operation is performed When it can be
  • the CNOT gate operation is performed on the current first sign bit qubit and the third preset auxiliary bit to restore the quantum state of the current third preset auxiliary bit; wherein, the first sign bit qubit is a control bit, so The third preset auxiliary bits are controlled bits.
  • the subtracted quantum state is assumed to be
  • 0011> is the highest-order sub-quantum state, namely
  • the set quantum bit q1 is initially
  • the quantum state evolution corresponding to the complement operation is not performed on the subtracted quantum state.
  • the minuend is a positive number, there is no need for complement in the subtraction operation, or in other words, its complement is itself, and
  • the CNOT gate can be executed again on the current g.sign and q1.
  • the quantum state of the g.sign bit is
  • 0> of the controlled bit q1 remains unchanged to restore q1 is in the
  • q 1 is the third preset auxiliary bit, which is used to control whether to perform complement operation
  • the first target quantum state is g
  • g.sign is the sign bit in the first target quantum state Quantum state
  • the remaining g is the numerical sub-quantum state representing the data value
  • j is the fourth preset auxiliary bit, that is, the auxiliary bit that is set to a value of 1
  • p is the auxiliary bit used by the adder (the following the fifth preset auxiliary bit).
  • the above k is n+2 bits, that is, it includes: n bits j, 1 bit p, and 1 bit q1.
  • the quantum circuit shown in Figure 52 realizes the quantum circuit that performs the operation of calculating the complement of g.
  • the CNOT gate operation is performed on g.sign and q 1 , so that q 1 temporarily represents g.sign, and q 1 is used to control whether to perform the search.
  • Complement code after obtaining the complement code, restore q 1 .
  • the quantum state evolution corresponding to the complement operation is performed by controlling the subtracted quantum state, and the first complement quantum state is obtained.
  • the first preset auxiliary bit q 1 is used to control whether to perform the complementing operation. If g is negative, the complement operation of the negative number is performed. The complement of a negative number is the bitwise inversion except for the sign bit and then adding 1. If the bitwise inversion operation except for the sign bit is implemented with logic gates, it is only necessary to make X gates for all the numerical bits. 1 needs to be added. Therefore, by adding j and g, the value of j is set to 1, and p is the auxiliary bit of the adder. After adding g and j after the inversion of the value bits, what is stored on g is After taking the complemented value, restore q 1 for the next use.
  • the current subtraction quantum state performs the quantum state evolution corresponding to the complement operation to obtain a second complement quantum state; wherein, the second complement quantum state is a quantum state comprising the complement of the subtraction data;
  • the X gate operation can be performed on the second sign bit qubit corresponding to the sign bit quantum state in the subtraction quantum state to obtain the inverted sign bit quantum state; wherein, the X gate can use other equivalent quantum states. It is also reasonable and feasible to replace some quantum logic gates or combinations of quantum logic gates;
  • the CNOT gate operation is performed on the current second sign bit qubit and the third preset auxiliary bit to restore the current quantum state of the third preset auxiliary bit; wherein, the second sign bit qubit is a control bit, so The third preset auxiliary bits are controlled bits.
  • the decrement quantum state is assumed to be
  • 0100> is the sub-quantum state of the highest bit, that is, the
  • the X gate can be performed on h.sign, the corresponding sign bit quantum state
  • the quantum state of q1 after the CNOT gate operation is performed is
  • An implementation of the quantum state evolution corresponding to performing the complement operation is as follows:
  • 1100> can be negated by executing the X gate; in order to keep the dimensions consistent, the fourth preset auxiliary bits are preset 4-bit qubits j3, j2, j1, j0, The quantum state
  • the CNOT gate can be executed again on the current h.sign and q1.
  • the quantum state of the h.sign bit is
  • 1> of the controlled bit q1 is reversed as
  • Figure 53 is a schematic diagram of the quantum circuit of the quantum state evolution corresponding to performing the complement operation on g and h, referring to the above-mentioned similar method, the second target quantum state h performs the quantum state evolution corresponding to the complement operation , to get the second's complement quantum state.
  • S5303 perform quantum state evolution corresponding to the addition operation on the first's complement quantum state and the second's complement quantum state, so as to evolve the first's complement quantum state into a quantum state including the subtrahend data a fifth target quantum state of the complement of the complement and the complement of the subtrahend data;
  • the first complement quantum state and the second complement quantum state are substituted into the quantum circuit of the adder, and the quantum state evolution corresponding to the addition operation is performed, thereby, the first complement quantum state is evolved to include all A third target quantum state of the sum of the complement of the minuend data and the complement of the subtrahend data.
  • the sixth target quantum state is output as the result of the subtraction operation between the subtrahend data and the subtrahend data; wherein, the sixth target quantum state is a quantum that includes the complement of the complement of the sum of the complements. state;
  • 0> of the third preset auxiliary bit control the fifth target quantum state
  • the quantum state corresponding to the code operation evolves, and the sixth target quantum state after evolution
  • the evolution of the quantum state corresponding to the complement operation can be the same as that described above. After the evolution, the quantum state of the third preset auxiliary bit is still restored to
  • S5305 according to the sign bit quantum state in the current subtraction quantum state and the current quantum state of the third preset auxiliary bit, control the current subtraction quantum state to perform the quantum state evolution corresponding to the complement operation, and perform the quantum state evolution corresponding to the current subtraction quantum state
  • the sign bit sub quantum state in performs the quantum state evolution of the sign bit inversion response to restore the current decrement quantum state.
  • the current subtraction quantum state is the second's complement quantum state
  • the current quantum state of the third preset auxiliary bit is
  • the quantum state evolution corresponding to the complement operation is further performed on the third target quantum state of the sum of the complement of the minuend data and the complement of the subtrahend data.
  • the purpose of making an X gate on j [ 0] is to set the value of j[0] to 1, which is convenient for the +1 operation in the complement.
  • the reason for doing the X gate operation on the sign bit of h is to convert gh to g+(-h). Then, we do the complement processing of both g and h. After the processing is completed, add the complements of g and h.
  • the quantum state evolution corresponding to the addition operation can be performed by the adder, which can include:
  • S5401 according to the number of qubit bits corresponding to the two quantum states to be operated, determine the number of target modules of the pre-cascading module MAJ module to be cascaded and the post-cascade module UMA module to be cascaded, wherein all The number of modules of the MAJ module is the same as the number of modules of the UMA module;
  • the two quantum states to be operated can be: the first's complement quantum state and the second's complement quantum state; the inversely subtracted quantum state and the quantum state of the fourth preset auxiliary bit
  • the first qubit in the circuit is the fifth preset auxiliary bit, which is initially in the
  • c represents the final carry item, corresponding to the preset carry auxiliary bit, and s is the output bit that does not contain carry.
  • the number of qubits corresponding to e and f is required to be the same, and the number of s, e and f is the same.
  • e [i] and f [i] are respectively the i-th bit of the quantum state corresponding to the two addends, and c [i] is the upper-order carry bit.
  • the first quantum bit is the fifth preset auxiliary bit, which corresponds to c 0 in the quantum circuit.
  • the first MAJ module includes three input quantum states and three corresponding output quantum states, wherein the three input quantum states are c 0 , e 0 , and f 0 respectively, and e 0 is the first quantum state to be operated. 0-bit quantum state, f 0 is the 0th-bit quantum state of the second quantum state to be operated, c 0 is the quantum state of the fifth preset auxiliary bit, and the initial value is 0, that is, no carry.
  • the three output quantum states are c 1 , c 1 is the carry after the addition of e 0 and f 0.
  • the three input quantum states of the next MAJ module are c 1 , e 1 , and f 1 , and the three output quantum states are respectively c 2 , and so on to the last MAJ module.
  • the first UMA module includes three input quantum states and three corresponding output quantum states, wherein the three output quantum states of the MAJ module are the three input quantum states of the corresponding UMA module, and the three output quantum states are respectively c 0 , s 0 , e 0 , s 0 is the result of the addition of e 0 and f 0 without carry. Similarly, s1 is the result of the addition of e 1 and f 1 without carry, and so on, c4 is the final carry term. It should be noted that, in practical applications, without the requirement of calculating the final carry, the quantum circuit corresponding to c4 may not be set.
  • the number of modules of the MAJ module and the number of UMA modules can be determined according to the number of sub-quantum states contained in any quantum state to be calculated.
  • One sub-quantum state corresponds to one qubit
  • the number of modules of the MAJ module is and the same number of UMA modules. Shown in the figure is only an example, encoding e and f each requires 4 qubits, and the number of MAJ modules and UMA modules are both 4.
  • the MAJ module and the UMA module constitute the front and rear cascade units of the adder.
  • the MAJ module can be used to extract the carry term of any step and pass it to the next level to calculate the final carry term.
  • the UMA module extracts the information of c and transmits it to the upper-level UMA, and also calculates the s (result item) of each level, and restores the information of e.
  • the MAJ module and the UMA module both include three input items and three output items.
  • the three output items of a MAJ cascade module can be used as the three inputs of a corresponding UMA cascade module. Item, to cascade the MAJ cascading module and the corresponding UMA cascading module to generate the target quantum circuit corresponding to the adder, wherein the MAJ cascading module is composed of the MAJ modules of the number of the target modules.
  • the UMA cascading module is determined by cascading between UMA modules of the target number of modules.
  • the three input items of the MAJ module include a carry input item and two sub-quantum state input items to be calculated
  • the three output items of the MAJ module include a carry output item and two intermediate result output items
  • the three input items of the UMA module include a carry output item and two intermediate result output items corresponding to the MAJ module
  • the three output items of the UMA module include a result carry output item, an accumulation sum output item, and a to-be-calculated item.
  • the carry output item output by the previous MAJ module and the two input items of the sub-quantum state to be calculated can be used as the three input items of the next MAJ module, so that the MAJ of the target module number modules are cascaded;
  • a CNOT quantum logic gate is added between the last MAJ module and the corresponding first UMA module in the initial quantum circuit, wherein the qubit corresponding to the carry output item of the MAJ module is used as the control bit, and the preset carry
  • the auxiliary bits act as controlled bits to generate the target quantum circuit of the adder.
  • the CNOT gate and the carry auxiliary bit may not be set.
  • the three output bits of the MAJ module are used as the three input bits of the UMA module, so that the same number of MAJ modules and UMA modules are Concatenation is performed to generate the target quantum circuit corresponding to the adder.
  • the hollow circle and the solid circle connected in the circuit diagram represent the CNOT gate operation
  • the hollow circle corresponding to the qubit is the control bit
  • the solid circle corresponding to the controlled bit is the CNOT gate operation
  • the MAJ module is a MAJ quantum circuit
  • the UMA module is a UMA quantum circuit.
  • Both the MAJ quantum circuit and the UMA quantum circuit include two CNOT quantum logic gates and one TOFFOLI quantum logic gate.
  • the instruction, before the step of cascading the MAJ modules and the UMA modules of the number of the target modules to generate the target quantum circuit corresponding to the adder also includes: obtaining the two CNOT quantum logic gates and a TOFFOLI quantum logic
  • the operation qubits corresponding to the gates, the control relationship between the operation qubits, and the timing relationship between the two CNOT quantum logic gates and one TOFFOLI quantum logic gate; according to the operation qubits, the control relationship and the Timing relationship, the two CNOT quantum logic gates and one TOFFOLI quantum logic gate are constructed to generate the MAJ quantum circuit or the UMA quantum circuit, as the corresponding MAJ module or UMA module.
  • the MAJ module and the UMA module constitute the front and rear cascade units of the adder.
  • the MAJ module is used to extract the carry term after the addition operation of each stage and pass it to the next stage, thereby calculating the final carry term.
  • the MAJ module can be mainly composed of three logic gates, namely two CNOT gates and one Toffoli gate.
  • the function of the CNOT gate (the first and second logic gates from left to right in Figure 59) is to add the control bit to the target bit to form a modulo 2 addition, which is an exclusive OR operation, and obtain (e i +c i )%2, (e i +f i )%2, the order of the two CNOT gates can be swapped.
  • the front-stage cascade unit of the quantum adder is constituted by two CNOT gates and one TOFFOLI gate.
  • Example 1 e i is 1, f i is 1, and c i is 1.
  • the MAJ module starts to add ei to ci , the value on ci becomes 0, then adds ei to fi , the value on fi also becomes 0, and finally adds fi and ci to On e i , the value of e i becomes 1, that is, the carry of c i+1 is 1.
  • Example 2 e i is 0, f i is 1, and c i is 1.
  • the MAJ module starts to add ei to ci , the value on ci becomes 1, then adds ei to fi , the value on fi also becomes 1, and finally adds fi and ci to On e i , the value of e i becomes 1, that is, the carry of c i+1 is 1.
  • the UMA module is used for the latter stage of the cascaded adder.
  • the implementation of the UMA module is similar to the MAJ module.
  • the Toffoli gate is used first (the first from left to right in Figure 61).
  • Example 1 ( ei + c i ) % 2 is 0, ( ei +fi )% 2 is 0, and c i +1 is 1.
  • Example 2 ( ei + c i ) % 2 is 1, ( ei +fi )% 2 is 1, and c i +1 is 1.
  • the adder that is, the target quantum circuit
  • the corresponding binary representation of the target quantum state calculation result including the carry term and the result term obtained by the direct addition of each sub-quantum state. Then directly output the target quantum state result
  • FIG. 62 is a schematic structural diagram of a quantum division operation device with precision provided by an embodiment of the present invention, which may include:
  • the conversion module 51501 is used to obtain the dividend data and the divisor data to be calculated, convert the dividend data into a first target quantum state, and convert the divisor data into a second target quantum state; wherein, the target quantum state includes: a symbol bit sub-quantum state representing the data symbol and a numerical bit sub-quantum state representing the data value;
  • the first quantum state evolution module 51502 is used to iteratively execute the quantum state evolution corresponding to the subtraction operation on the first target quantum state and the second target quantum state, and count the execution times of the subtraction operation until Subtract the dividend data to a negative number, and output the finally obtained counting result as the integer bits of the quotient of dividing the dividend data and the divisor data; wherein, the minuend of the subtraction operation performed each time is the last time The subtraction result and the subtrahend of performing the subtraction operation are the divisor data;
  • the second quantum state evolution module 51503 is configured to iteratively execute the quantum state evolution corresponding to the decimal place operation of the quotient for the current first target quantum state and the current second target quantum state; wherein, the preset number of iterations of the iteration is the same as The number of decimal places to be calculated is the same, and after each iteration, a quantum state containing the value of the corresponding precision bit is obtained on the corresponding preset precision bit qubit;
  • the output module 51504 is configured to output the finally obtained quantum state on the qubit with preset precision, wherein the quantum state includes the binary value of the decimal place of the quotient.
  • the first quantum state evolution module is specifically used for:
  • the quantum state evolution corresponding to the subtraction operation For the third target quantum state of the current first preset auxiliary bit and the fourth target quantum state of the current second preset auxiliary bit, perform the quantum state evolution corresponding to the subtraction operation to add the value contained in the current third target quantum state. 1; wherein, the initial value included in the third target quantum state and the value included in the fourth target quantum state are both -1;
  • the output module is specifically used for:
  • the finally obtained third target quantum state is output, wherein the value contained in the third target quantum state is an integer-bit binary value of the quotient of the division of the dividend data and the divisor data.
  • the second quantum state evolution module is specifically used for:
  • the quantum state evolves into a quantum state containing the remainder binary value of dividing the dividend data by the divisor data;
  • the device further includes:
  • the execution module is used to obtain a preset sign bit qubit, the qubit corresponding to the sign bit sub-quantum state of the first target quantum state, the qubit corresponding to the sign bit sub-quantum state of the second target quantum state, the The first preset auxiliary bit and the preset sign bit qubit perform a preset quantum logic gate operation to finally obtain the sign value represented by the sign bit sub-quantum state in the third target quantum state.
  • the computing module includes:
  • the first's complement arithmetic unit is used to obtain the quantum state of the third preset auxiliary bit as the subtrahened quantum state containing the subtracted data and the subtracted quantum state containing the subtracted data for the two quantum states to be calculated. state, according to the quantum state of the sign bit in the subtracted quantum state and the quantum state of the third preset auxiliary bit, control the quantum state evolution corresponding to the complement operation of the subtracted quantum state to obtain the first One's complement quantum state; wherein, the first complement quantum state is a quantum state comprising the complement of the minuend data;
  • the second’s complement arithmetic unit is configured to perform the quantum state evolution of the sign bit inversion response for the sign bit sub-quantum state in the subtraction quantum state, and according to the inverted sign bit sub-quantum state and the third preset
  • the quantum state of the auxiliary bit controls the current subtraction quantum state to perform the quantum state evolution corresponding to the complement operation, and obtains the second complement quantum state; wherein, the second complement quantum state is the complement of the subtraction data including the subtraction data. the quantum state of the code;
  • the addition operation unit is used to perform the quantum state evolution corresponding to the addition operation on the first complement quantum state and the second complement quantum state, so as to evolve the first complement quantum state to include the a fifth target quantum state of the sum of the complement of the subtrahend data and the complement of the subtrahend data;
  • a third complement operation unit configured to control the fifth target quantum state to perform a complement operation corresponding to the symbol bit sub-quantum state in the fifth target quantum state and the quantum state of the third preset auxiliary bit
  • the quantum state evolution of obtains the sixth target quantum state after evolution, which is output as the result of the subtraction operation of the subtrahend data and the subtrahend data; wherein, the sixth target quantum state contains the complement code the quantum state of the complement of the sum;
  • the fourth complement operation unit is configured to control the current subtraction quantum state to perform the quantum state evolution corresponding to the complement operation according to the sign bit quantum state in the current subtraction quantum state and the current quantum state of the third preset auxiliary bit, And perform the quantum state evolution of the sign bit inversion response to the sign bit quantum state in the current decrement quantum state, so as to restore the current decrement quantum state.
  • the first complement arithmetic unit is specifically used for:
  • the third preset auxiliary bit is a controlled bit
  • the CNOT gate operation is performed on the current first sign bit qubit and the third preset auxiliary bit to restore the quantum state of the current third preset auxiliary bit; wherein, the first sign bit qubit is a control bit, so The third preset auxiliary bits are controlled bits.
  • the second complement arithmetic unit is specifically used for:
  • the CNOT gate operation is performed on the current second sign bit qubit and the third preset auxiliary bit to restore the current quantum state of the third preset auxiliary bit; wherein, the second sign bit qubit is a control bit, so The third preset auxiliary bits are controlled bits.
  • the addition unit includes:
  • the determining subunit is used to determine the number of target modules of the pre-cascade module MAJ module to be cascaded and the post-cascade module UMA module to be cascaded according to the number of qubit bits corresponding to the two quantum states to be operated , wherein the number of modules of the MAJ module is the same as the number of modules of the UMA module;
  • the cascade subunit is used to cascade the MAJ module and the UMA module of the target module number according to the addition instruction to generate the target quantum circuit corresponding to the adder;
  • the operation subunit is configured to perform an addition operation on each sub-quantum state of the two quantum states to be operated through the target quantum circuit to generate and output the result of the target quantum state.
  • the MAJ module is a MAJ quantum circuit
  • the UMA module is a UMA quantum circuit
  • both the MAJ quantum circuit and the UMA quantum circuit include two CNOT quantum logic gates and one TOFFOLI quantum logic gate
  • the addition operation unit also includes:
  • the obtaining subunit is used to obtain the operation qubits corresponding to the two CNOT quantum logic gates and one TOFFOLI quantum logic gate, the control relationship between the operation qubits, and the two CNOT quantum logic gates and one TOFFOLI quantum logic gate temporal relationship between;
  • the MAJ module and the UMA module each include three input items and three output items, and the cascaded subunits are specifically used for:
  • three output items of a MAJ cascade module are used as three input items of a corresponding UMA cascade module, so as to cascade the MAJ cascade module and the corresponding UMA cascade module to generate the The target quantum circuit corresponding to the adder, wherein the MAJ cascade module is determined by the cascade between MAJ modules of the target module number, and the UMA cascade module is determined by the target module number between the UMA modules Cascade OK.
  • the three input items of the MAJ module include a carry input item and two sub-quantum state input items to be calculated
  • the three output items of the MAJ module include a carry output item and two intermediate result output items
  • the three input items of the UMA module include a carry output item and two intermediate result output items corresponding to the MAJ module
  • the three output items of the UMA module include a result carry output item, an accumulation sum output item, and a to-be-calculated item.
  • Sub-quantum state input; the cascaded sub-unit is specifically used for:
  • the carry output item output by the previous MAJ module and the two sub-quantum state input items to be calculated are used as the three input items of the next MAJ module, so that the MAJ modules of the target number of modules are graded. link;
  • a CNOT quantum logic gate is added between the last MAJ module and the corresponding first UMA module in the initial quantum circuit, wherein the qubit corresponding to the carry output item of the MAJ module is used as the control bit, and the preset carry
  • the auxiliary bits act as controlled bits to generate the target quantum circuit of the adder.
  • the present invention obtains the dividend data to be calculated and the divisor data, converts the dividend data into the first target quantum state, and converts the divisor data into the second target quantum state. , iteratively execute the quantum state evolution corresponding to the subtraction operation, and count the execution times of the subtraction operation until the dividend data is reduced to a negative number. Output, for the current first target quantum state and the current second target quantum state, iteratively execute the quantum state evolution corresponding to the decimal place operation of the quotient, and output the quantum state on the qubit of the preset precision bit obtained finally, so as to realize the It is used for basic arithmetic operations in quantum circuits, filling the gaps in related technologies.
  • Yet another embodiment of the present invention provides an electronic device comprising a memory and a processor, the memory having a computer program stored therein, the processor being configured to run the computer program to perform a method as described below:
  • the target quantum state includes: a symbol bit sub-quantum state of the data symbol and a numerical bit sub-quantum state representing the data value;
  • Yet another embodiment of the present invention provides a storage medium, where a computer program is stored in the storage medium, wherein the computer program is configured to execute the following method when running:
  • the target quantum state includes: a symbol bit sub-quantum state of the data symbol and a numerical bit sub-quantum state representing the data value;

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Abstract

一种带精度的量子除法运算方法及装置，属于量子计算领域，该方法包括：获取待运算的被除数数据和除数数据，并将被除数数据转换为第一目标量子态，将除数数据转换为第二目标量子态（S5201）；对第一目标量子态和第二目标量子态，迭代执行减法运算对应的量子态演化，并对减法运算的执行次数进行计数，直至将被除数数据减为负数，将最终获得的计数结果，作为被除数数据与除数数据相除的商的整数位进行输出（S5202）；对当前第一目标量子态和当前第二目标量子态，迭代执行商的小数位运算对应的量子态演化（S5203）；将最终获得的预设精度位量子比特上的量子态进行输出（S5204）；该方法实现了可以用于量子线路中的基本算术运算操作。

Description

一种带精度的量子除法运算方法及装置
本公开要求于2020年09月30日提交中国专利局、申请号为202011058756.3、申请名称为“一种量子加法运算方法、装置、电子装置及存储介质”的中国专利申请；2020年09月30日提交中国专利局、申请号为202011058770.3、申请名称为“一种量子减法运算方法、装置、电子装置及存储介质”的中国专利申请；2020年09月30日提交中国专利局、申请号为202011058718.8、申请名称为“一种量子乘法运算方法、装置、电子装置及存储介质”的中国专利申请；2020年09月30日提交中国专利局、申请号为202011064018.X、申请名称为“一种量子除法运算方法、装置、电子装置及存储介质”的中国专利申请；和2020年09月30日提交中国专利局、申请号为202011059513.1、申请名称为“一种带精度的量子除法运算方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本发明属于量子计算领域，特别是一种带精度的量子除法运算方法及装置。
背景技术
量子计算机利用量子的叠加性，理论上在某些情形下有指数级加速的能力。譬如破解RSA密钥在经典计算机上需要数百年，而在量子计算机上执行量子算法只需数小时。但是目前量子计算机的受限于量子芯片硬件的发展导致的可操控的比特数有限，因此计算能力有限，并不能普遍地去运行量子算法。普遍地运行量子算法通常需要借助量子计算模拟方法。
在量子算法的模拟实现过程中，通常需要借助各种量子逻辑门构建量子算法，但是，仅依靠各种量子逻辑门构建量子算法时，并没有对应经典运算例如加、减、乘、除的基本算术运算操作的量子逻辑门。因此，急需提供一种能够实现量子线路中的基本算术运算操作的技术，以填补相关技术空白。
发明内容
本发明的目的是提供一种带精度的量子除法运算方法及装置，以解决现有技术中的不足，它能够填补相关技术空白，用于量子线路中实现基本算术运算操作。
本发明采用的技术方案如下：
本发明实施例提供了一种带精度的量子除法运算方法，所述方法包括：获取待运算的被除数数据和除数数据，并将所述被除数数据转换为第一目标量子态，将所述除数数据转换为第二目标量子态；其中，目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态；对所述第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为负数，将最终获得的计数结果，作为所述被除数数据与所述除数数据相除的商的整数位进行输出；其中，每次执行减法运算的被减数为上次执行减法运算的减法结果、减数为所述除数数据；对当前第一目标量子态和当前第二目标量子态，迭代执行所述商的小数位运算对应的量子态演化；其中，该迭代的预设迭代次数与待计算的小数位精度的位数一致，每次迭代后在对应的预设精度位量子比特上得到包含对应精度位的值的量子态；将最终获得的预设精度位量子比特上的量子态进行输出，其中，该量子态包含所述商的小数位的二进制值。
可选的，所述对所述第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子 态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为负数，包括：对当前第一目标量子态和所述第二目标量子态，执行减法运算对应的量子态演化，以获得包含减法运算结果的第一目标量子态；对当前第一预设辅助比特的第三目标量子态和当前第二预设辅助比特的第四目标量子态，执行减法运算对应的量子态演化，以将当前第三目标量子态包含的值加1；其中，所述第三目标量子态包含的初值、所述第四目标量子态包含的值均为-1；测量当前包含减法运算结果的第一目标量子态的符号位子量子态，判断当前包含减法运算结果的第一目标量子态的符号位的值是否为0；在当前包含减法运算结果的第一目标量子态的符号位的值为0的情况下，返回执行所述对当前第一目标量子态和当前第二目标量子态，执行减法运算对应的量子态演化的步骤，直至判断出当前包含减法运算结果的第一目标量子态的符号位的值为1。
可选的，所述将最终获得的计数结果，作为所述被除数数据与所述除数数据相除的商的整数位进行输出，包括：将最终获得的第三目标量子态进行输出，其中，所述第三目标量子态包含的值为所述被除数数据与所述除数数据相除的商的整数位二进制值。
可选的，所述对当前第一目标量子态和当前第二目标量子态，迭代执行所述商的小数位运算对应的量子态演化，包括：将当前第二目标量子态的符号位子量子态取反，对当前第一目标量子态和符号位取反后的第二目标量子态，执行减法运算对应的量子态演化，以将当前第一目标量子态演化为包含所述被除数数据与所述除数数据相除的余数二进制值的量子态；将当前第一目标量子态的各位子量子态均左移一位，将当前第二目标量子态的符号位子量子态再取反，对左移一位后的第一目标量子态和再取反后的第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述左移一位后的第一目标量子态减为负数，在预设中间位量子比特上得到包含计数结果的二进制值的小数位量子态；将所述小数位量子态的最后一位子量子态与对应的预设精度位量子比特的初始量子态|0>态进行交换，并输出交换后的预设精度位量子比特上的量子态；返回执行所述将当前第二目标量子态的符号位子量子态取反，对当前第一目标量子态和符号位取反后的第二目标量子态，执行减法运算对应的量子态演化的步骤，直至达到所述迭代执行所述商的小数位运算对应的量子态演化所需的预设迭代次数，其中，所述预设迭代次数与待计算的小数位精度的位数一致。
可选的，所述方法还包括：获取预设符号位量子比特，对所述第一目标量子态的符号位子量子态对应的量子比特、所述第二目标量子态的符号位子量子态对应的量子比特、所述第一预设辅助比特和所述预设符号位量子比特，执行预设量子逻辑门操作，以最终获得所述第三目标量子态中符号位子量子态表示的符号值。
可选的，所述执行减法运算对应的量子态演化，包括：对于待运算的两个量子态，分别作为包含被减数据的被减数量子态和包含减数数据的减数量子态，获取第三预设辅助比特的量子态，根据所述被减数量子态中的符号位子量子态和所述第三预设辅助比特的量子态，控制所述被减数量子态执行求补码运算对应的量子态演化，得到第一补码量子态；其中，所述第一补码量子态为包含所述被减数数据的补码的量子态；将所述减数量子态中的符号位子量子态执行符号位取反对应的量子态演化，并根据取反后的符号位子量子态和所述第三预设辅助比特的量子态，控制当前减数量子态执行求补码运算对应的量子态演化，得到第二补码量子态；其中，所述第二补码量子态为包含所述减数数据的补码的量子态；对所述第一补码量子态和所述第二补码量子态，执行加法运算对应的量子态演化，以将所述第一补码量子态演化为包含所述被减数数据的补码与所述减数数据的补码之和的第五目标量子态；根据所述第五目标量子态中的符号位子量子态和所述第三预设辅助比特的量子态，控制所述第五目标量子态执行求补码运算对应的量子态演化，得到演化后的第六目标量子态，作为所述被减数数据和所述减数数据的减法运算结果进行输出；其中，所述第六目标量子态为包含所述补码之和的补码的量子态；根据当前减数量子态中的符号位子量子态和当前第三预设辅助比特的量子态，控制当前减数量子态执行求补码运算对应的量子态演化，并对当前减数量子态中的符号位子量子态执行符号位取反对应的量子态演化，以将当前减数量子态进行还原。
可选的，所述根据所述被减数量子态中的符号位子量子态和所述第三预设辅助比特的量子态，控制所述被减数量子态执行求补码运算对应的量子态演化，包括：对所述被减数量子态中的符号位子量子态对应的第一符号位量子比特和所述第三预设辅助比特执行CNOT门操作，其中，所述第一符号位量子比特为控制比特，所述第三预设辅助比特为受控比特；根据执行CNOT门操作后的所述第三预设辅助比特的量子态，控制当前被减数量子态是否执行求补码运算对应的量子态演化；若是，则对当前被减数量子态的非符号位子量子态取反，并将取反后的被减数量子态与第四预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第一补码量子态，否则，将所述被减数量子态作为第一补码量子态；对当前第一符号位量子比特和第三预设辅助比特执行CNOT门操作，以将当前第三预设辅助比特的量子态进行还原；其中，所述第一符号位量子比特为控制比特，所述第三预设辅助比特为受控比特。
可选的，所述将所述减数量子态中的符号位子量子态执行符号位取反对应的量子态演化，并根据取反后的符号位子量子态和所述第三预设辅助比特的量子态，控制当前减数量子态执行求补码运算对应的量子态演化，包括：对所述减数量子态中的符号位子量子态对应的第二符号位量子比特，执行X门操作，得到取反后的符号位子量子态；对当前第二符号位量子比特和第三预设辅助比特执行CNOT门操作，其中，所述第二符号位量子比特为控制比特，所述第三预设辅助比特为受控比特；根据执行CNOT门操作后的第三预设辅助比特的当前量子态，控制当前减数量子态是否执行求补码运算对应的量子态演化；若是，则对当前减数量子态的非符号位子量子态取反，并将取反后的减数量子态与第四预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第二补码量子态，否则，将当前减数量子态作为第二补码量子态；对当前第二符号位量子比特和第三预设辅助比特执行CNOT门操作，以将第三预设辅助比特的当前量子态进行还原；其中，所述第二符号位量子比特为控制比特，所述第三预设辅助比特为受控比特。
可选的，所述执行加法运算对应的量子态演化，包括：根据待运算的两个量子态对应的量子比特位的位数，确定待级联的前级联模块MAJ模块以及待级联的后级联模块UMA模块的目标模块个数，其中，所述MAJ模块的模块个数与所述UMA模块的模块个数相同；根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成加法器对应的目标量子线路；通过所述目标量子线路对所述待运算的两个量子态的各子量子态进行加法运算，生成目标量子态结果并输出。
可选的，所述MAJ模块为MAJ量子线路，所述UMA模块为UMA量子线路，所述MAJ量子线路和所述UMA量子线路均包括两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门，所述根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成加法器对应的目标量子线路的步骤之前，还包括：获取所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门对应的操作量子比特、操作量子比特之间的控制关系以及所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门之间的时序关系；根据所述操作量子比特、所述控制关系以及所述时序关系，将所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门构建生成所述MAJ量子线路或所述UMA量子线路，作为对应的MAJ模块或UMA模块。
可选的，所述MAJ模块以及所述UMA模块均包括三个输入项以及三个输出项，所述根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成所述加法器对应的目标量子线路的步骤具体包括：根据加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路，其中，所述MAJ级联模块由所述目标模块个数的MAJ模块之间级联确定，所述UMA级联模块由所述目标模块个数的UMA模块之间级联确定。
可选的，所述MAJ模块的三个输入项包括一个进位输入项以及两个待计算子量子态输入项，所述MAJ模块的三个输出项包括一个进位输出项和两个中间结果输出项，所述UMA模块的三个输入项包括对应MAJ模块的一个进位输出项以及两个中间结果输出项，所述UMA模块的三个输 出项包括一个结果进位输出项、累加和输出项和一待计算子量子态输入项，所述根据加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路的步骤具体包括：根据加法指令，将上一MAJ模块输出的进位输出项以及所述两个待计算子量子态输入项作为下一MAJ模块的三个输入项，以将所述目标模块个数的MAJ模块进行级联；将一MAJ模块的两个中间结果输出项作为一对应UMA模块的两个输入项，获取所述对应UMA模块的上一UMA模块，并将所述上一UMA模块的结果进位输出项作为所述对应UMA模块的一个输入项，以将所述目标模块个数的MAJ模块以及所述目标模块个数的UAM模块进行级联，生成所述初始量子线路；其中，最后一个MAJ模块的进位输出项作为对应的第一个UMA模块的一个输入项；将所述初始量子线路中最后一个MAJ模块与对应的第一个UMA模块之间添加CNOT量子逻辑门，其中，将所述MAJ模块的进位输出项对应的量子比特作为控制比特，将预设进位辅助比特位作为受控比特位，以生成所述加法器的目标量子线路。
本发明又一实施例提供了一种带精度的量子除法运算装置，所述装置包括：转换模块，用于获取待运算的被除数数据和除数数据，并将所述被除数数据转换为第一目标量子态，将所述除数数据转换为第二目标量子态；其中，目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态；第一量子态演化模块，用于对所述第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为负数，将最终获得的计数结果，作为所述被除数数据与所述除数数据相除的商的整数位进行输出；其中，每次执行减法运算的被减数为上次执行减法运算的减法结果、减数为所述除数数据；第二量子态演化模块，用于对当前第一目标量子态和当前第二目标量子态，迭代执行所述商的小数位运算对应的量子态演化；其中，该迭代的预设迭代次数与待计算的小数位精度的位数一致，每次迭代后在对应的预设精度位量子比特上得到包含对应精度位的值的量子态；输出模块，用于将最终获得的预设精度位量子比特上的量子态进行输出，其中，该量子态包含所述商的小数位的二进制值。
本发明还提供一种电子装置，包括存储器和处理器，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行上述步骤方法。
本发明还提供一种存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行上述步骤方法。
与现有技术相比，本发明提供的带精度的量子除法运算方法，获取待运算的被除数数据和除数数据，并将被除数数据转换为第一目标量子态，将除数数据转换为第二目标量子态，对第一目标量子态和第二目标量子态，迭代执行减法运算对应的量子态演化，并对减法运算的执行次数进行计数，直至将被除数数据减为负数，将最终获得的计数结果，作为被除数数据与除数数据相除的商的整数位进行输出，对当前第一目标量子态和当前第二目标量子态，迭代执行商的小数位运算对应的量子态演化，将最终获得的预设精度位量子比特上的量子态进行输出，从而实现可以用于量子线路中的基本算术运算操作，填补了相关技术的空白。
附图说明
图1是本发明一实施例提供的量子加法/量子减法/量子乘法/量子除法/带精度的量子除法运算方法的计算机终端硬件结构框图；
图2是本发明一实施例提供的量子加法运算方法的流程示意图；
图3是本发明提供的加法器示意图；
图4是本发明提供的加法器量子线路示意图；
图5是本发明提供的MAJ模块示意图；
图6是本发明提供的MAJ模块量子线路组合过程示意图；
图7是本发明提供的UMA模块示意图；
图8是本发明提供的UMA模块量子线路组合过程示意图；
图9是本发明提供的求补码运算的量子线路示意图；
图10是本发明提供的减法器对应的前半部分量子线路示意图；
图11是本发明提供的减法器对应的后半部分量子线路示意图；
图12是本发明提供的减法器对应的量子线路示意图；
图13是本发明一实施例提供的量子加法运算装置的结构示意图。
图14是本发明一实施例提供的量子减法运算方法的流程示意图；
图15是本发明提供的求补码量子线路示意图；
图16是本发明提供的加法运算前求补码量子线路示意图；
图17是本发明提供的加法运算后求补码量子线路示意图；
图18是本发明提供的减法器的量子线路示意图；
图19是本发明一实施例提供的加法器示意图；
图20是本发明一实施例提供的加法器量子线路示意图；
图21是本发明一实施例提供的MAJ模块示意图；
图22是本发明一实施例提供的MAJ模块量子线路组合过程示意图；
图23是本发明一实施例提供的UMA模块示意图；
图24是本发明一实施例提供的UMA模块量子线路组合过程示意图；
图25是本发明一实施例提供的量子减法运算装置的结构示意图。
图26是本发明一实施例提供的一种量子乘法运算方法的流程示意图；
图27是本发明一实施例提供的一种保存符号位运算结果的示意图；
图28是本发明一实施例提供的加法器示意图；
图29是本发明一实施例提供的加法器量子线路示意图；
图30是本发明一实施例提供的MAJ模块示意图；
图31是本发明一实施例提供的MAJ模块量子线路组合过程示意图；
图32是本发明一实施例提供的UMA模块示意图；
图33是本发明一实施例提供的UMA模块量子线路组合过程示意图；
图34是本发明一实施例提供的一种量子乘法运算装置的结构示意图。
图35是本发明一实施例提供的量子除法运算方法的流程示意图；
图36是本发明一实施例提供的量子除法运算方法的量子线路示意图；
图37是本发明另一实施例提供的量子除法运算方法的量子线路示意图；
图38是本发明一实施例提供的求补码运算的量子线路示意图；
图39是本发明一实施例提供的减法器对应的前半部分量子线路示意图；
图40是本发明一实施例提供的减法器对应的后半部分量子线路示意图；
图41是本发明一实施例提供的减法器对应的量子线路示意图；
图42是本发明一实施例提供的加法器示意图；
图43是本发明一实施例提供的加法器量子线路示意图；
图44是本发明一实施例提供的MAJ模块示意图；
图45是本发明一实施例提供的MAJ模块量子线路组合过程示意图；
图46是本发明一实施例提供的UMA模块示意图；
图47是本发明一实施例提供的UMA模块量子线路组合过程示意图。
图48是本发明一实施例提供的量子除法运算装置的结构示意图。
图49是本发明一实施例提供的带精度的量子除法运算方法的流程示意图；
图50是本发明一实施例提供的带精度的量子除法运算方法的量子线路示意图；
图51是本发明另一实施例提供的带精度的量子除法运算方法的量子线路示意图；
图52是本发明一实施例提供的求补码运算的量子线路示意图；
图53是本发明一实施例提供的减法器对应的前半部分量子线路示意图；
图54是本发明一实施例提供的减法器对应的后半部分量子线路示意图；
图55是本发明一实施例提供的减法器对应的量子线路示意图；
图56是本发明一实施例提供的加法器示意图；
图57是本发明一实施例提供的加法器量子线路示意图；
图58是本发明一实施例提供的MAJ模块示意图；
图59是本发明一实施例提供的MAJ模块量子线路组合过程示意图；
图60是本发明一实施例提供的UMA模块示意图；
图61是本发明一实施例提供的UMA模块量子线路组合过程示意图。
图62是本发明一实施例提供的带精度的量子除法运算装置的结构示意图。
具体实施方式
下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
需要说明的是，本发明的说明书和权利要求书中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
本发明的实施例提供了一种量子加法/量子减法/量子乘法/量子除法/带精度的量子除法运算方法及装置，用于在量子线路中实现量子比特的基本算术运算操作，该方法可以应用于电子设备，如移动终端，具体如手机、平板电脑；如计算机终端，具体如普通电脑、量子计算机等。
下面以运行在计算机终端上为例对其进行详细说明。图1是本申请实施例的一种量子加法/量子减法/量子乘法/量子除法/带精度的量子除法运算方法的计算机终端的硬件结构框图。如图1所示，计算机终端可以包括一个或多个(图1中仅示出一个)处理器102(处理器102可以包括但不限于微处理器MCU或可编程逻辑器件FPGA等的处理装置)和用于存储数据的存储器104，可选地，上述计算机终端还可以包括用于通信功能的传输装置106以及输入输出设备108。本领域普通技术人员可以理解，图1所示的结构仅为示意，其并不对上述计算机终端的结构造成限定。例如，计算机终端还可包括比图1中所示更多或者更少的组件，或者具有与图1所示不同的配置。
存储器104可用于存储应用软件的软件程序以及模块，如本申请实施例中的量子计算模拟方法对应的程序指令/模块，处理器102通过运行存储在存储器104内的软件程序以及模块，从而执行各种功能应用以及数据处理，即实现上述的方法。存储器104可包括高速随机存储器，还可包括非易失性存储器，如一个或者多个磁性存储装置、闪存、或者其他非易失性固态存储器。在一些实例中，存储器104可进一步包括相对于处理器102远程设置的存储器，这些远程存储器可以通过网络连接至计算机终端。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
传输装置106用于经由一个网络接收或者发送数据。上述的网络具体实例可包括计算机终端的通信供应商提供的无线网络。在一个实例中，传输装置106包括一个网络适配器(Network Interface Controller，NIC)，其可通过基站与其他网络设备相连从而可与互联网进行通讯。在一个实例中，传输装置106可以为射频(Radio Frequency，RF)模块，其用于通过无线方式与互联网进行通讯。
需要说明的是，真正的量子计算机是混合结构的，它包含两大部分：一部分是经典计算机，负责执行经典计算与控制；另一部分是量子设备，负责运行量子程序进而实现量子计算。而量子程序是由量子语言如Qrunes语言编写的一串能够在量子计算机上运行的指令序列，实现了对量子逻辑门操作的支持，并最终实现量子计算。具体的说，量子程序就是一系列按照一定时序操作量子逻辑门的指令序列。
在实际应用中，因受限于量子设备硬件的发展，通常需要进行量子计算模拟以验证量子算法、量子应用等等。量子计算模拟即借助通普通计算机的资源搭建的虚拟架构(即量子虚拟机)实现特定问题对应的量子程序的模拟运行的过程。通常，需要构建特定问题对应的量子程序。本发明实施例所指量子程序，即是经典语言编写的表征量子比特及其演化的程序，其中与量子计算相关的量子比特、量子逻辑门等等均有相应的经典代码表示。
量子线路作为量子程序的一种体现方式，也称量子逻辑电路，是最常用的通用量子计算模型，表示在抽象概念下对于量子比特进行操作的线路，其组成包括量子比特、线路(时间线)，以及各种量子逻辑门，最后常需要通过量子测量操作将结果读取出来。
不同于传统电路是用金属线所连接以传递电压信号或电流信号，在量子线路中，线路可看成是由时间所连接，亦即量子比特的状态随着时间自然演化，在这过程中按照哈密顿运算符的指示，一直到遇上逻辑门而被操作。
一个量子程序整体上对应有一条总的量子线路，本发明所述量子程序即指该条总的量子线路，其中，该总的量子线路中的量子比特总数与量子程序的量子比特总数相同。可以理解为：一个量子程序可以由量子线路、针对量子线路中量子比特的测量操作、保存测量结果的寄存器及控制流节点(跳转指令)组成，一条量子线路可以包含几十上百个甚至千上万个量子逻辑门操作。量子程序的执行过程，就是对所有的量子逻辑门按照一定时序执行的过程。需要说明的是，时序即单个量子逻辑门被执行的时间顺序。
需要说明的是，经典计算中，最基本的单元是比特，而最基本的控制模式是逻辑门，可以通过逻辑门的组合来达到控制电路的目的。类似地，处理量子比特的方式就是量子逻辑门。使用量子逻辑门，能够使量子态发生演化，量子逻辑门是构成量子线路的基础，量子逻辑门包括单比特量子逻辑门，如Hadamard门(H门)、Pauli-X门、Pauli-Y门、Pauli-Z门、RX门、RY门、RZ门；多比特量子逻辑门，如CNOT门、CR门、iSWAP门、Toffoli门。量子逻辑门一般使用酉矩阵表示，而酉矩阵不仅是矩阵形式，也是一种操作和变换。
目前，并没有可以实现一些经典运算例如四则运算功能，示例性的：加、减、乘、除运算量子逻辑门，亟待构造量子线路以实现任一四则运算的功能操作，进而推动量子计算的发展，以及量子应用领域的扩展和落地。
本发明的实施例一提供了一种量子加法运算方法，如图2所示，所述方法包括：
S1201，获取加法指令以及待运算的两目标数据，并将所述两目标数据转换为两个目标量子态；
本实施例用于介绍如何在量子计算机中实现加法运算的逻辑电路，并结合预先开发软件QPanda对每个模块进行说明。任何经典逻辑电路，也可以通过量子线路来表示。经典电路和量子线路一一对应，量子逻辑门/量子线路的输入与输出均是量子比特，且输入与输出的量子比特数量相等。量子线路允许量子态以叠加的方式输入，输出的状态即可以相同的方式叠加输出。可逆计算是量子计算的基本，即任何可逆线路存在逆线路，也就是说，将每个原有的输出作为输入，正好可以映射到原来的输入上。可逆线路意味着对于每一种输出，都正好有一种输入与之对应，这种映射是一一映射。例如非门是一个典型的可逆逻辑门，它的逆线路就是它自身。典型的不可逆逻辑门就是与门、或门。例如与门的输入是0,0；0,1；1,0的时候均输出0，这说明不存在从输出到输入的唯一映射。可逆计算意味着信息在计算过程中没有丢失，经过逆变换之后可以恢复原来的状态。不可逆计算意味着信息丢失了。例如从与门的输出，无法推知输入的状态。对于可逆计算来说，是可以推知的。任何连续执行的可逆逻辑门，合起来是一个可逆操作。量子逻辑门全部是可逆逻辑门，所以量子线路是可逆线路。但是量子测量不是可逆计算。
具体地，接收用户输入的加法指令，并获取加法指令对应的待运算的两目标数据，并将待运算的两个目标数据转换为对应的两个目标量子态。可以利用现有的振幅编码方式，将待运算的十进制数据转换为二进制的量子态表示。例如，第一加法数数据为7，带符号的二进制表示0111，最高 位为0表示正数，1表示负数；第二加法数据为4，带符号的二进制表示011。其中，目标量子态为两个目标量子比特对应的本征态，量子比特位对应的所有本征态表征的数量是2的量子比特位的个数次方。例如：例如一组量子比特为q 0、q 1、q 2，表示第0位、第1位、第2位量子比特，从高位到低位排序为q 2q 1q 0，则该组量子比特位对应的本征态(即量子态)总共有8个，分别为：|000>、|001>、|010>、|011>、|100>、|101>、|110>、|111>，该8个本征态之间的叠加态。该组量子比特位的个数可以根据实际运算需要进行设置。
需要说明的是，如图3所示，线路中第一个量子比特位为第一预设辅助比特位，初始为|0>态，最终会恢复为|0>态，线路中的a和b是待相加的数据对应的量子态，各对应一组量子比特位。c表示最终的进位项，对应预设进位辅助比特位，s是不包含进位的输出位。一般要求a和b对应的量子比特位数相同,s和a、b的位数相同。其中，a [i]和 b[i]分别是两个加数对应量子态的第i位，c [i]是上一级进位。
s [i]＝a [i]XOR b [i]XOR c [i]，
c [i+1]＝(a [i]AND b [i])XOR(a [i]AND b [i])XOR(a [i]AND b [i])。
S1202，根据所述目标量子态中的各量子比特的位数，确定待级联的前级联模块MAJ模块以及待级联的后级联模块UMA模块的目标模块个数，其中，所述MAJ模块的模块个数与所述UMA模块的模块个数相同；
本实施例中，如图4所示，s＝a+b。在最终输出的结果中，第一个qubit(也就是上面级联线路中的c 0)，最终会恢复为0态。a和b都是一组qubit绑定成的数，一般要求a和b的位数相同。s是不包含进位的输出位，和b的位数相同。c是最终的进位项。一个MAJ模块包括三个输入量子态以及对应的三个输出量子态，其中，第一个量子比特即为第一预设辅助比特位，对应量子线路中的c 0。第一个MAJ模块包括三个输入量子态以及对应的三个输出量子态，其中，三个输入量子态分别为c 0、a 0、b 0，a 0为第一个待运算量子态的第0位量子态，b 0为第二个待运算量子态的第0位量子态，c 0为第三预设辅助比特的量子态，初始值为0，即无进位。三个输出量子态分别为
Figure PCTCN2021119125-appb-000001
Figure PCTCN2021119125-appb-000002
c 1，c 1为a 0和b 0相加后的进位，同理，下一个MAJ模块的三个输入量子态为c 1、a 1、b 1，三个输出量子态分别为
Figure PCTCN2021119125-appb-000003
c 2，以此类推至最后一个MAJ模块。
对于第一个UMA模块，包括三个输入量子态以及对应的三个输出量子态，其中，MAJ模块的三个输出量子态为对应UMA模块的三个输入量子态，三个输出量子态分别为c 0、s 0、a 0，s 0为a 0和b 0相加的不含进位的结果。同理，s 1为a 1和b 1相加的不含进位的结果，以此类推，c 4是最终的进位项，对应预设进位辅助比特。需要说明的是，在实际应用中，在无计算最终进位的需求下，量子线路中可以不设置c 4对应的量子比特位。
并且，可以根据其中待运算的任一量子态包含的子量子态数量确定MAJ模块的模块个数以及UMA模块的个数，一子量子态对应一位量子比特，其中，MAJ模块的模块个数以及UMA模块的个数相等。图中所示仅仅作为示例，编码a和b各所需4位量子比特，MAJ模块和UMA模块的个数均为4。MAJ模块和UMA模块构成了加法器的前、后级联单元。MAJ模块可以用于提取出任何一步的进位项并且传递到下一级，从而将最终进位项计算出来。UMA模块一方面提取了c的信息会传递到上一级UMA，还计算出每一级的s(结果项)，并且恢复了a的信息。
示例性的：当4(对应编码在3个量子比特的量子态表示为100)+2(对应编码在3个量子比特的量子态表示为010)＝6(对应编码在3个量子比特的量子态表示为110)。此时编码运算结果的量子比特与编码a的量子比特位的个数或用来编码b的量子比特位的个数一致，MAJ模块的模块个数以及UMA模块的个数均为3。
示例性的：当4(对应编码在3个量子比特的量子态表示为100)+7(对应编码在3个量子比特的量子态表示为111)＝11(对应编码在3个量子比特的量子态表示为011)，但是，可以理解的是11对应的二进制数为1011，最左侧的1所在的位为进位项，该进位项可以通过辅助比特位表 示。此时编码运算结果的量子比特与编码a的量子比特位的个数或用来编码b的量子比特位的个数要多，MAJ模块的模块个数以及UMA模块的个数均为3。
示例性的，当2(对应编码在2个量子比特的量子态表示为10)+4(对应编码在3个量子比特的量子态表示为100)＝6(对应编码在3个量子比特的量子态表示为110)。此时，编码“6”数值的数值项“3”与编码b的量子比特位的量子态个数一致，MAJ模块的模块个数以及UMA模块的个数均为3。
S1203，根据所述加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成加法器对应的目标量子线路；
其中，至少一个MAJ模块级联组成MAJ级联模块，至少一个UMA模块级联组成UMA级联模块，所述MAJ级联模块以及所述UMA级联模块均包括三个输入项以及三个输出项，
所述根据所述加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成所述加法器对应的目标量子线路的步骤具体包括：
根据所述加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路。
本实施例中，如图4所示，根据图示方式，将所述MAJ模块的三个输出比特作为所述UMA模块的三个输入比特，由此，将相同个数的MAJ模块以及UMA模块进行级联，生成所述加法器对应的目标量子线路。
其中，所述MAJ模块为MAJ量子线路，所述UMA模块为UMA量子线路，所述MAJ量子线路和所述UMA量子线路均包括两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门，
所述根据所述加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成加法器对应的目标量子线路的步骤之前，还包括：
获取所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门对应的操作量子比特、操作量子比特之间的控制关系以及所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门之间的时序关系；
根据所述操作量子比特、所述控制关系以及所述时序关系，将所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门构建生成所述MAJ量子线路或所述UMA量子线路，作为对应的MAJ模块或UMA模块。
本实施例中，MAJ模块和UMA模块构成了加法器的前、后级联单元。如图5所示，MAJ模块用于提取出每一级加法运算后的进位项并且传递到下一级，从而将最终进位项计算出来。其中，线路图中空心圆表示NOT操作，实心圆表示控制比特。UMA模块一方面用于提取进位项c的值，并将进位项c的值传递到上一级UMA模块，并计算出每一级的和s(结果项)，并且恢复了a的值。其中，如图6所示，MAJ模块可以由三个逻辑门组成，分别是两个CNOT门和一个Toffoli门。CNOT门(图6中的由左向右的第一个、第二个逻辑门)的作用为：将控制位加到目标位上去，形成一个模2加法，即为异或操作，得到(a+c)％2，因此顺序可以交换。Toffoli门(图6中的由左向右的第三个逻辑门)的作用为：将两个控制位都加到目标位上去,得到进位项c i，c [i+1]＝(a [i]AND b [i])XOR(a [i]AND b [i])XOR(a [i]AND b [i])。即通过图6中的由左向右的第一个CNOT门实现，通过图6中的由左向右的第二个CNOT门实现，通过图6中的由左向右的第三个TOFFOLI门实现c i+1，由此通过2个CNOT门和1个TOFFOLI门，构成量子加法器的前级级联单元。
例子1：a i为1，b i为1，c i为1。
MAJ模块开始把a i加到c i上，c i上的值变为0，再把a i加到b i上，b i上的值也变为0，最后用b i和c i加到a i上，a i的值变为1，也就是c i+1的进位为1。
例子2：a i为0，b i为1，c i为1。
MAJ模块开始把a i加到c i上，c i上的值变为1，再把a i加到b i上，b i上的值也变为1，最后 用b i和c i加到a i上，a i的值变为1，也就是c i+1的进位为1。
如图7所示，UMA模块用于级联加法器的后级，UMA模块的实现方式和MAJ模块类似，如图8所示，首先使用Toffoli门(图8中的由左向右的第一个逻辑门)将c i+1还原为a i，再用a i对(a+c)％2用CNOT门(图8中的由左向右的第二个逻辑门)做一次还原，还原为c i，最后，再使用c i对(a+b)％2做一次CNOT门(图8中的由左向右的第三个逻辑门)，得到当前位的最终结果s i。
例子1：(a i+c i)％2为0，(a i+b i)％2为0，c i+1为1。
开始把(a i+c i)％2和(a i+b i)％2加到c i+1上，c i+1的值变为1，表示的意义变为a i，再用a i加到(a i+c i)％2上，(a i+c i)％2的值变为1，表示的意义变为c i,再用c i加到(a i+b i)％2上，(a i+b i)％2的值变为1，表示的意义变为s i。
例子2：(a i+c i)％2为1，(a i+b i)％2为1，c i+1为1。
开始把(a i+c i)％2和(a i+b i)％2加到c i+1上，c i+1的值变为0，表示的意义变为a i，再用a i加到(a i+c i)％2上，(a i+c i)％2的值变为1，表示的意义变为c i,再用c i加到(a i+b i)％2上，(a i+b i)％2的值变为0，表示的意义变为s i。
如图4中由上向下的最后一个CNOT门，即整个加法器MAJ模块和UMA模块中间的CNOT门，用于保存c i+1的结果。
具体地，所述MAJ级联模块的三个输入项包括一个进位输入项以及两个待计算子量子态输入项，所述MAJ级联模块的三个输出项包括一个进位输出项和两个中间结果输出项，所述UMA级联模块的三个输入项包括对应MAJ级联模块的一个进位输出项以及两个中间结果输出项，所述UMA级联模块的三个输出项包括一个结果进位输出项、累加和输出项和一待计算子量子态输入项，
所述根据所述加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路的步骤具体包括：
根据所述加法指令，将上一MAJ模块输出的进位输出项以及所述两个待计算子量子态输入项作为下一MAJ模块的三个输入项，以将所述目标模块个数的MAJ模块进行级联，生成所述MAJ级联模块；
将一MAJ模块的两个中间结果输出项作为一对应UMA模块的两个输入项，获取所述对应UMA模块的上一UMA模块，并将所述上一UMA模块的结果进位输出项作为所述对应UMA模块的一个输入项，以将所述目标模块个数的MAJ模块以及所述目标模块个数的UAM模块进行级联，生成所述UMA级联模块，其中，最后一个MAJ模块的进位输出项作为对应的第一UMA模块的一个输入项；
将所述一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述初始量子线路；
将所述初始量子线路中最后一个MAJ级联模块与对应的第一个UMA级联模块之间添加CNOT量子逻辑门，其中，将所述MAJ级联模块的进位输出项对应的量子比特作为控制比特，将预设进位辅助比特作为受控比特位，以生成所述加法器的目标量子线路。
更多实施例中，在不需要进位项的情况下，可以不设置该CNOT门以及进位辅助比特位。
S1204，通过所述目标量子线路对所述两个目标量子态的各量子比特进行加法运算，生成并输出目标量子态结果。
本实施例中，通过将两个目标量子态的各子量子态，如|111>和|111>、，输入加法器(即所述目标量子线路)中，得到对应的二进制表示目标量子态计算结果(包括进位项以及各子量子态直接相加得到的结果项)。然后将二进制表示的目标量子态结果|1110>直接输出，或进一步转化为十进制结果14并输出，完成两目标数据的加法运算。
可见，本发明提供的量子除法运算方法，用于实现量子线路中的基本算术运算操作，获取待 运算的被除数数据和除数数据，并将所述被除数数据转换为第一目标量子态，将所述除数数据转换为第二目标量子态；对所述第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为负数；将最终获得的计数结果，作为所述被除数数据与所述除数数据相除的商，转换为十进制表示并输出，从而实现可以用于量子线路中的基本算术运算操作，填补了相关技术的空白。
本发明的另一实施例提供了详细说明执行减法运算方法的具体实现方式。
对于待运算的两个量子态，分别作为包含被减数据的被减数量子态和包含减数数据的减数量子态，获取第二预设辅助比特的量子态，根据所述被减数量子态中的符号位子量子态和所述第二预设辅助比特的量子态，控制所述被减数量子态执行求补码运算对应的量子态演化，得到第一补码量子态；其中，所述第一补码量子态为包含所述被减数数据的补码的量子态；
由前述实施例可知，待运算的两个量子态有以下组：第一目标量子态和第二目标量子态；第三目标量子态和第四目标量子态；第一目标量子态和符号位取反后的第二目标量子态。其中，前者可称被减数量子态，包含的数据在减法运算中为被减数，后者可称减数量子态，包含的数据为减数。
本实施例中，主要用于实现减法器功能，减法器和下述加法器最大的区别就是会产生负数的情况，因此，采用二进制的处理方式，对减数和被减数都加一个符号位，来表示数值的正负，并且使用补码来进行运算。正数补码不变，负数除符号位外按位取反后，再加1。对应到量子线路中，即用符号位控制是否做补码操作，取反用X门，加1可通过加法器实现。在补码情况下运算完成后，再将结果做一次补码运算就得到了目标数值。获取待运算的被减数数据和减数数据，并将所述被减数数据以及所述减数数据分别转换为第一目标量子态和第二目标量子态。其中，目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态。
具体的，根据被减数量子态中的符号位子量子态和第二预设辅助比特的量子态，控制被减数量子态执行求补码运算对应的量子态演化，可以对被减数量子态中的符号位子量子态对应的第一符号位量子比特和第二预设辅助比特执行CNOT门操作，其中，第一符号位量子比特为控制比特，第二预设辅助比特为受控比特；并且，CNOT门可以用等效的其他现有的量子逻辑门或量子逻辑门组合进行替代，也是合理可行的；
根据执行CNOT门操作后的第二预设辅助比特的量子态，控制当前被减数量子态是否执行求补码运算对应的量子态演化；
若是，则对当前被减数量子态的非符号位子量子态取反，并将取反后的被减数量子态与第二预设辅助比特的量子态|1>态，执行量子加法运算，得到演化后的第一补码量子态，否则，将所述被减数量子态作为第一补码量子态；其中，执行CNOT门操作后的第二预设辅助比特的量子态可以为|1>态时，才控制执行求补码运算对应的量子态演化，否则不执行；
对当前第一符号位量子比特和第二预设辅助比特执行CNOT门操作，以将当前第二预设辅助比特的量子态进行还原；其中，所述第一符号位量子比特为控制比特，所述第二预设辅助比特为受控比特。
示例性的，被减数量子态假设为|0011>。|0011>的符号位子量子态为最高位的子量子态即|0>态，该位的值为0，对应的第一符号位量子比特设为g.sign，第二预设辅助比特为预设的量子比特q1，初始为|0>态。
对g.sign和q1执行CNOT门操作，g.sign作为控制比特，q1作为受控比特，g.sign位的量子态为|0>态，经过CNOT门操作后，受控比特位q1的量子态|0>不变。
由于执行CNOT门操作后的q1的量子态为|0>态，故不对被减数量子态执行求补码运算对应的量子态演化。原理上在于，被减数为正数时，在减法运算中无需求补码，或者说，其补码即为本身，可直接将|0011>作为第一补码量子态。
最后，可以对当前g.sign和q1再次执行CNOT门，g.sign位的量子态为|0>态，经过CNOT门操作后，受控比特位q1的量子态|0>不变，以还原q1为|0>态，从而释放第三辅助比特存储的信 息。可得，第一补码量子态包含的值0011为被减数0011的补码。
如图9所示，q 1为第二预设辅助比特，用于控制是否做补码操作，所述第一目标量子态为g，g.sign为所述第一目标量子态中的符号位子量子态，剩余的g为表示所述数据数值的数值位子量子态，j为第二预设辅助比特，即被设置成值为1的辅助比特，p为加法器所使用的辅助比特(下述第一预设辅助比特)。
图9所示的量子线路实现了对g做求补码的操作的量子线路，先对g.sign与q 1进行CNOT门操作，使得q 1暂时表示g.sign，并用q 1控制是否进行求补码，求完补码后，再将q 1还原。由此，控制被减数量子态执行求补码运算对应的量子态演化，得到第一补码量子态。
具体地，根据g的符号位子量子态，用第二预设辅助比特q 1来控制是否做取补码的操作。若g为负数，则进行负数的取补码操作。负数的补码为除符号位外按位取反后加1，除符号位外按位取反的操作用逻辑门来实现的话，只需要对数值位全都做X门即可，取反后还需要加1，因此，通过使用j和g相加，j的值被设置为了1，p为加法器的辅助比特，在将数值位取反后的g和j相加后，g上存放的就是取完补码后的数值，再将q 1还原，以便下次使用。
例子：当g为负数时，g.sign为1，因此q 1也为1，就需要做取反等操作，而当g为正数时，g.sign为0，因此q 1也为0，就不需要再求补码了。
将所述减数量子态中的符号位子量子态执行符号位取反对应的量子态演化，并根据取反后的符号位子量子态和所述第二预设辅助比特的量子态，控制当前减数量子态执行求补码运算对应的量子态演化，得到第二补码量子态；其中，所述第二补码量子态为包含所述减数数据的补码的量子态；
具体的，可以对减数量子态中的符号位子量子态对应的第二符号位量子比特，执行X门操作，得到取反后的符号位子量子态；其中，X门可以用等效的其他现有的量子逻辑门或量子逻辑门组合进行替代，也是合理可行的；
同样的，继续对当前第二符号位量子比特和第二预设辅助比特执行CNOT门操作，其中，所述第二符号位量子比特为控制比特，所述第二预设辅助比特为受控比特；
根据执行CNOT门操作后的第二预设辅助比特的当前量子态，控制当前减数量子态是否执行求补码运算对应的量子态演化；
若是，则对当前减数量子态的非符号位子量子态取反，并将取反后的减数量子态与第二预设辅助比特的量子态|1>态，执行量子加法运算，得到演化后的第二补码量子态，否则，将当前减数量子态作为第二补码量子态；
对当前第二符号位量子比特和第二预设辅助比特执行CNOT门操作，以将第二预设辅助比特的当前量子态进行还原；其中，所述第二符号位量子比特为控制比特，所述第二预设辅助比特为受控比特。
示例性的，减数量子态假设为|0100>。|0100>的符号位子量子态为最高位的子量子态即|0>态，该位的值为0，对应的第二符号位量子比特设为b.sign，当前第三辅助比特被还原为|0>态。
首先，可以对h.sign执行X门，将对应的符号位子量子态|0>取反为|1>，减数量子态变为|1100>。
继续对h.sign和q1执行CNOT门操作，h.sign作为控制比特，q1作为受控比特，当前h.sign位的量子态为|1>态，经过CNOT门操作后，受控比特位q1的量子态|0>被取反为|1>态。
执行CNOT门操作后的q1的量子态为|1>态，故对当前减数量子态|1100>执行求补码运算对应的量子态演化。一种执行求补码运算对应的量子态演化的实现如下：
对当前减数量子态|1100>的非符号位子量子态取反，并将取反后的减数量子态|1011>与第二预设辅助比特的量子态|1>态，执行量子加法运算，得到演化后的第二补码量子态为|1100>。
其中，可通过执行X门对|1100>的非符号位子量子态|100>取反；为了保持维度一致，第二预设辅助比特为预设的4位量子比特m3、m2、m1、m0，第二预设辅助比特的量子态|1>实际上写为|0001>，两者是等同的。
最后，可对当前h.sign和q1再次执行CNOT门，h.sign位的量子态为|1>态，经过CNOT门 操作后，受控比特位q1的量子态|1>被取反为|0>，从而再次还原q1为初始|0>态，释放q1的存储空间。可得，第二补码量子态包含的值1100为对h.sign执行X门后的减数1100的补码。
本实施例中，所述第二目标量子态h也是同理，初始对j [0]做X门是为了设置值为1，对第二目标量子态中的符号位子量子态h.sign做X门是为了把减法变成加法。如图10所示，图10为对g、h执行求补码运算对应的量子态演化的量子线路示意图，参考上述同理方法将第二目标量子态h执行求补码运算对应的量子态演化，得到第二补码量子态。
对所述第一补码量子态和所述第二补码量子态，执行量子加法运算，以将所述第一补码量子态演化为包含所述被减数数据的补码与所述减数数据的补码之和的第五目标量子态；
示例性的，对第一补码量子态为|0011>和第二补码量子态为|1100>，执行量子加法运算，将第一补码量子态|0011>演化为第五目标量子态|1111>。
本实施例中，在求完补码后，将g和h进行加法操作，加完后，再将之前的操作进行还原，g内储存的即为所求。将所述第一补码量子态和所述第二补码量子态代入加法器的量子线路，执行量子加法运算，由此，将所述第一补码量子态演化为包含所述被减数数据的补码与所述减数数据的补码之和的第三目标量子态。
根据所述第五目标量子态中的符号位子量子态和所述第二预设辅助比特的量子态，控制所述第五目标量子态执行求补码运算对应的量子态演化，得到演化后的第六目标量子态，作为所述被减数数据和所述减数数据的减法运算结果进行输出；其中，所述第六目标量子态为包含所述补码之和的补码的量子态；
示例性的，根据当前第五目标量子态|1111>中的符号位子量子态|1>和当前第二预设辅助比特的量子态|0>，控制第五目标量子态|1111>执行求补码运算对应的量子态演化，得到演化后的第六目标量子态|1001>，其包含的值为1001(十进制-1)，即为被减数量子态|0011>包含的被减数0011(十进制3)与减数量子态|0100>包含的减数0100(十进制4)的减法结果。
需要说明的是，执行求补码运算对应的量子态演化可与前述同理，演化后，第二预设辅助比特的量子态仍被还原为|0>，以便于后续计算使用。
根据当前减数量子态中的符号位子量子态和当前第二预设辅助比特的量子态，控制当前减数量子态执行求补码运算对应的量子态演化，并对当前减数量子态中的符号位子量子态执行符号位取反对应的量子态演化，以将当前减数量子态进行还原。
示例性的，当前减数量子态为第二补码量子态|1100>，当前第二预设辅助比特的量子态为|0>。继续按前述同理的方式，控制|1100>执行求补码运算对应的量子态演化，得到演化后的|1100>，然后通过X门操作对其符号位子量子态取反，将其还原成初始的减数量子态|0100>。
本实施例中，进行加法运算后，进一步对所述被减数数据的补码与所述减数数据的补码之和的第三目标量子态执行求补码运算对应的量子态演化。如图11所示，首先，对j [0]做一个X门的目的是将j [0]的值设置为1，方便求补码中的+1运算。而对h的符号位做X门的操作的原因，则是为了将g-h转换为g+(-h)。然后，我们将g和h都做好补码的处理，处理完成后，再将g和h的补码进行相加，得到结果后，再将g和h做一次求补码的操作，将其还原为正常的数值，最后再对初始操作进行还原，也就是对辅助比特进行还原，做2个X门即可。由此组成了如图12所示的整个减法器的量子线路图，是一种功能上的简易示例。
本发明的另一实施例提供了一种量子加法运算装置，如图13所示，所述装置包括：
运算数据获取模块11301，用于获取加法指令以及待运算的两目标数据，并将所述两目标数据转换为两个目标量子态；
级联模块确定模块11302，用于根据所述目标量子态中的各量子比特的位数，确定待级联的前级联模块MAJ模块以及待级联的后级联模块UMA模块的目标模块个数，其中，所述MAJ模块的模块个数与所述UMA模块的模块个数相同；
量子线路生成模块11303，用于根据所述加法指令，将所述目标模块个数的MAJ模块以及 UMA模块进行级联，生成所述加法器对应的目标量子线路；
目标量子运算模块11304，用于通过所述目标量子线路对所述两个目标量子态的各量子比特进行加法运算，生成并输出目标量子态结果。
进一步地，所述MAJ模块为MAJ量子线路，所述UMA模块为UMA量子线路，所述MAJ量子线路和所述UMA量子线路均包括两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门，所述装置还包括级联模块预置模块：
获取所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门对应的操作量子比特、操作量子比特之间的控制关系以及所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门之间的时序关系；
根据所述操作量子比特、所述控制关系以及所述时序关系，将所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门构建生成所述MAJ量子线路或所述UMA量子线路，作为对应的MAJ模块或UMA模块。
进一步地，至少一个MAJ模块级联组成MAJ级联模块，至少一个UMA模块级联组成UMA级联模块，所述MAJ级联模块以及所述UMA级联模块均包括三个输入项以及三个输出项，所述量子线路生成模块还用于：
所述根据所述加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成所述加法器对应的目标量子线路的步骤具体包括：
根据所述加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路。
进一步地，所述MAJ级联模块的三个输入项包括一个进位输入项以及两个待计算子量子态输入项，所述MAJ级联模块的三个输出项包括一个进位输出项和两个中间结果输出项，所述UMA级联模块的三个输入项包括对应MAJ级联模块的一个进位输出项以及两个中间结果输出项，所述UMA级联模块的三个输出项包括一个结果进位输出项、累加和输出项和一待计算子量子态输入项，所述量子线路生成模块还用于：
根据所述加法指令，将上一MAJ模块输出的进位输出项以及所述两个待计算子量子态输入项作为下一MAJ模块的三个输入项，以将所述目标模块个数的MAJ模块进行级联，生成所述MAJ级联模块；
将一MAJ模块的两个中间结果输出项作为一对应UMA模块的两个输入项，获取所述对应UMA模块的上一UMA模块，并将所述上一UMA模块的结果进位输出项作为所述对应UMA模块的一个输入项，以将所述目标模块个数的MAJ模块以及所述目标模块个数的UAM模块进行级联，生成所述UMA级联模块，其中，最后一个MAJ模块的进位输出项作为对应的第一UMA模块的一个输入项；
将所述一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述初始量子线路；
将所述初始量子线路中最后一个MAJ级联模块与对应的第一个UMA级联模块之间添加CNOT量子逻辑门，其中，将所述MAJ级联模块的进位输出项对应的量子比特作为控制比特，将预设进位辅助比特作为受控比特位，以生成所述加法器的目标量子线路。
如上所述的，其中，优选的是，所述装置包括：
运算数据获取模块，用于获取待运算的被减数数据和减数数据，并将所述被减数数据转换为第一目标量子态，将所述减数数据转换为第二目标量子态；其中，目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态；
第一量子态演化模块，用于获取第二预设辅助比特的量子态，根据所述第一目标量子态中的符号位子量子态和所述第二预设辅助比特的量子态，控制所述第一目标量子态执行求补码运算对应 的量子态演化，得到第一补码量子态；其中，所述第一补码量子态为包含所述被减数数据的补码的量子态；
第二量子态演化模块，用于将所述第二目标量子态中的符号位子量子态执行符号位取反对应的量子态演化，并根据取反后的符号位子量子态和所述第二预设辅助比特的量子态，控制当前第二目标量子态执行求补码运算对应的量子态演化，得到第二补码量子态；其中，所述第二补码量子态为包含所述减数数据的补码的量子态；
第三量子态演化模块，用于对所述第一补码量子态和所述第二补码量子态，执行加法运算对应的量子态演化，以将所述第一补码量子态演化为包含所述被减数数据的补码与所述减数数据的补码之和的第三目标量子态；
目标量子运算模块，用于根据所述第三目标量子态中的符号位子量子态和所述第二预设辅助比特的量子态，控制所述第三目标量子态执行求补码运算对应的量子态演化，得到演化后的第四目标量子态，作为所述被减数数据和所述减数数据的减法运算结果进行输出；其中，所述第四目标量子态为包含所述补码之和的补码的量子态。
如上所述的，其中，优选的是，在所述目标量子运算模块之后，所述装置还包括：
还原模块，用于根据当前第二目标量子态中的符号位子量子态和当前第二预设辅助比特的量子态，控制当前第二目标量子态执行求补码运算对应的量子态演化，并对当前第二目标量子态中的符号位子量子态执行符号位取反对应的量子态演化，以将当前第二目标量子态进行还原。
如上所述的，其中，优选的是，所述第一量子态演化模块，具体用于：
对所述第一目标量子态中的符号位子量子态对应的第一符号位量子比特和所述第二预设辅助比特执行CNOT门操作，其中，所述第一符号位量子比特为控制比特，所述第二预设辅助比特为受控比特；
根据执行CNOT门操作后的所述第二预设辅助比特的量子态，控制当前第一目标量子态是否执行求补码运算对应的量子态演化；
若是，则对当前第一目标量子态的非符号位子量子态取反，并将取反后的第一目标量子态与第二预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第一补码量子态，否则，将所述第一目标量子态作为第一补码量子态；
对当前第一符号位量子比特和第二预设辅助比特执行CNOT门操作，以将当前第二预设辅助比特的量子态进行还原；其中，所述第一符号位量子比特为控制比特，所述第二预设辅助比特为受控比特。
上述实施例可以总结如下。
C11.一种量子加法运算方法，其特征在于，所述方法包括：获取加法指令以及待运算的两目标数据，并将所述两目标数据转换为两个目标量子态；根据所述目标量子态中的各量子比特的位数，确定待级联的前级联模块MAJ模块以及待级联的后级联模块UMA模块的目标模块个数，其中，所述MAJ模块的模块个数与所述UMA模块的模块个数相同；根据所述加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成加法器对应的目标量子线路；通过所述目标量子线路对所述两个目标量子态的各量子比特进行加法运算，生成并输出目标量子态结果。
C12.根据C11所述的量子加法运算方法，其特征在于，所述MAJ模块为MAJ量子线路，所述UMA模块为UMA量子线路，所述MAJ量子线路和所述UMA量子线路均包括两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门，所述根据所述加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成加法器对应的目标量子线路的步骤之前，还包括：获取所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门对应的操作量子比特、操作量子比特之间的控制关系以及所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门之间的时序关系；根据所述操作量子比特、所述控制关系以及所述时序关系，将所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门构建生成所述MAJ量子线路或所述UMA量子线路，作为对应的MAJ模块或UMA模块。
C13.根据C11或C12所述的量子加法运算方法，其特征在于，至少一个MAJ模块级联组成MAJ级联模块，至少一个UMA模块级联组成UMA级联模块，所述MAJ级联模块以及所述UMA级联模块均包括三个输入项以及三个输出项，所述根据所述加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成所述加法器对应的目标量子线路的步骤具体包括：根据所述加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路。
C14.根据C11-C13中的任何一个所述的量子加法运算方法，其特征在于，所述MAJ级联模块的三个输入项包括一个进位输入项以及两个待计算子量子态输入项，所述MAJ级联模块的三个输出项包括一个进位输出项和两个中间结果输出项，所述UMA级联模块的三个输入项包括对应MAJ级联模块的一个进位输出项以及两个中间结果输出项，所述UMA级联模块的三个输出项包括一个结果进位输出项、累加和输出项和一待计算子量子态输入项，所述根据所述加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路的步骤具体包括：根据所述加法指令，将上一MAJ模块输出的进位输出项以及所述两个待计算子量子态输入项作为下一MAJ模块的三个输入项，以将所述目标模块个数的MAJ模块进行级联，生成所述MAJ级联模块；将一MAJ模块的两个中间结果输出项作为一对应UMA模块的两个输入项，获取所述对应UMA模块的上一UMA模块，并将所述上一UMA模块的结果进位输出项作为所述对应UMA模块的一个输入项，以将所述目标模块个数的MAJ模块以及所述目标模块个数的UAM模块进行级联，生成所述UMA级联模块，其中，最后一个MAJ模块的进位输出项作为对应的第一UMA模块的一个输入项；将所述一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述初始量子线路；将所述初始量子线路中最后一个MAJ级联模块与对应的第一个UMA级联模块之间添加CNOT量子逻辑门，其中，将所述MAJ级联模块的进位输出项对应的量子比特作为控制比特，将预设进位辅助比特作为受控比特位，以生成所述加法器的目标量子线路。
C15.根据C11-C14中的任何一个所述的量子加法运算方法，其特征在于，所述量子加法运算方法还包括：获取待运算的被减数数据和减数数据，并将所述被减数数据转换为第一目标量子态，将所述减数数据转换为第二目标量子态；其中，目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态；获取第二预设辅助比特的量子态，根据所述第一目标量子态中的符号位子量子态和所述第二预设辅助比特的量子态，控制所述第一目标量子态执行求补码运算对应的量子态演化，得到第一补码量子态；其中，所述第一补码量子态为包含所述被减数数据的补码的量子态；将所述第二目标量子态中的符号位子量子态执行对应的量子态演化，并根据取反后的符号位子量子态和所述第二预设辅助比特的量子态，控制当前第二目标量子态执行求补码运算对应的量子态演化，得到第二补码量子态；其中，所述第二补码量子态为包含所述减数数据的补码的量子态；对所述第一补码量子态和所述第二补码量子态，执行量子加法运算，以将所述第一补码量子态演化为包含所述被减数数据的补码与所述减数数据的补码之和的第三目标量子态；根据所述第三目标量子态中的符号位子量子态和所述第二预设辅助比特的量子态，控制所述第三目标量子态执行求补码运算对应的量子态演化，得到演化后的第四目标量子态，作为所述被减数数据和所述减数数据的减法运算结果进行输出；其中，所述第四目标量子态为包含所述补码之和的补码的量子态。
C16.根据C11-C15中的任何一个所述的量子加法运算方法，其特征在于，所述控制所述第三目标量子态执行求补码运算对应的量子态演化，得到演化后的第四目标量子态的步骤之后，还包括：根据当前第二目标量子态中的符号位子量子态和当前第一预设辅助比特的量子态，控制当前第二目标量子态执行求补码运算对应的量子态演化，并对当前第二目标量子态中的符号位子量子态执行符号位取反对应的量子态演化，以将当前第二目标量子态进行还原。
C17.根据C11-C16中的任何一个所述的量子加法运算方法，其特征在于，所述根据所述第一目标量子态中的符号位子量子态和所述第二预设辅助比特的量子态，控制所述第一目标量子态执行求补码运算对应的量子态演化的步骤具体包括：对所述第一目标量子态中的符号位子量子态对应的第一符号位量子比特和所述第二预设辅助比特执行CNOT门操作，其中，所述第一符号位量子比特为控制比特，所述第二预设辅助比特为受控比特；根据执行CNOT门操作后的所述第二预设辅助比特的量子态，控制当前第一目标量子态是否执行求补码运算对应的量子态演化；若是，则对当前第一目标量子态的非符号位子量子态取反，并将取反后的第一目标量子态与第二预设辅助比特的量子态|1>态，执行量子加法运算，得到演化后的第一补码量子态，否则，将所述第一目标量子态作为第一补码量子态；对当前第一符号位量子比特和第二预设辅助比特执行CNOT门操作，以将当前第二预设辅助比特的量子态进行还原；其中，所述第一符号位量子比特为控制比特，所述第二预设辅助比特为受控比特。
C18、一种量子加法运算装置，其特征在于，所述装置包括：运算数据获取模块，用于获取加法指令以及待运算的两目标数据，并将所述两目标数据转换为两个目标量子态；级联模块确定模块，用于根据所述目标量子态中的各量子比特的位数，确定待级联的前级联模块MAJ模块以及待级联的后级联模块UMA模块的目标模块个数，其中，所述MAJ模块的模块个数与所述UMA模块的模块个数相同；量子线路生成模块，用于根据所述加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成所述加法器对应的目标量子线路；目标量子运算模块，用于通过所述目标量子线路对所述两个目标量子态的各量子比特进行加法运算，生成并输出目标量子态结果。
C19、一种电子装置，包括存储器和处理器，其特征在于，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行C11-C17中的任何一个所述的方法。
C110、一种存储介质，其特征在于，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行C11-C17中的任何一个所述的方法。
本发明的再一实施例提供了一种电子装置，包括存储器和处理器，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行如上所述方法步骤。
本发明的再一实施例提供了一种存储介质，所述存储介质中存储有计算机程序，所述计算机程序被设置为运行时执行如上所述方法步骤。
与现有技术相比，本发明提供的量子加法运算方法，通过获取加法指令以及待运算的两目标数据，并将所述两目标数据转换为两个目标量子态；根据所述目标量子态中的各量子比特的位数，确定待级联的前级联模块MAJ模块以及待级联的后级联模块UMA模块的目标模块个数，其中，所述MAJ模块的模块个数与所述UMA模块的模块个数相同；根据所述加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成加法器对应的目标量子线路；通过所述目标量子线路对所述两个目标量子态的各量子比特进行加法运算，生成并输出目标量子态结果。从而实现可以用于量子线路中的基本算术运算操作，填补了相关技术的空白。
本发明的实施例一提供了一种量子减法运算方法，如图14所示，所述方法包括：
S2201，获取待运算的被减数数据和减数数据，并将所述被减数数据转换为第一目标量子态，将所述减数数据转换为第二目标量子态；其中，目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态；
具体的，可以利用现有的振幅编码方式，将待运算的十进制数据转换为二进制的量子态表示。例如，被减数数据为7，带符号的二进制表示0111，最高位为0表示正数，1表示负数；减数数据为4，带符号的二进制表示011。
至少获取4位量子比特a.sign、a2、a1、a0，将7编码到a.sign、a2、a1、a0的第一目标量子态|0111>上，量子态的振幅设为1。其中，|0111>＝|0>|1>|1>|1>，|0>、|1>、|1>、|1>称为|0111>的子量子态，一子量子态对应一量子比特位，且从右至左表示由高位至低位，最高位对应a.sign、第三位对应a2、第二位对应a1、最低位对应a0，最高位的|0>表示符号位子量子态，其余表示数值位 子量子态。为了统一运算维度，另外获取4位量子比特b.sign、b2、b1、b0，将4编码到b.sign、b2、b1、b0的第二目标量子态|0100>，其振幅同为1。
本实施例中，主要用于实现减法器功能，减法器和下述加法器最大的区别就是会产生负数的情况，因此，采用二进制的处理方式，对减数和被减数都加一个符号位，来表示数值的正负，并且使用补码来进行运算。正数补码不变，负数除符号位外按位取反后，再加1。对应到量子线路中，即用符号位控制是否做补码操作，取反可以用X门，加1可通过加法器实现。在补码情况下运算完成后，再将结果做一次补码运算就得到了目标数值。获取待运算的被减数数据和减数数据，并将所述被减数数据以及所述减数数据分别转换为第一目标量子态和第二目标量子态。其中，目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态。
S2202，获取第一预设辅助比特的量子态，根据所述第一目标量子态中的符号位子量子态和所述第一预设辅助比特的量子态，控制所述第一目标量子态执行求补码运算对应的量子态演化，得到第一补码量子态；其中，所述第一补码量子态为包含所述被减数数据的补码的量子态；
具体的，根据第一目标量子态中的符号位子量子态和第一预设辅助比特的量子态，控制第一目标量子态执行求补码运算对应的量子态演化，可以对第一目标量子态中的符号位子量子态对应的第一符号位量子比特和第一预设辅助比特执行CNOT门操作，其中，第一符号位量子比特为控制比特，第一预设辅助比特为受控比特；并且，CNOT门可以用等效的其他现有的量子逻辑门或量子逻辑门组合进行替代，也是合理可行的；
根据执行CNOT门操作后的第一预设辅助比特的量子态，控制当前第一目标量子态是否执行求补码运算对应的量子态演化；
若是，则对当前第一目标量子态的非符号位子量子态取反，并将取反后的第一目标量子态与第二预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第一补码量子态，否则，将所述第一目标量子态作为第一补码量子态；其中，执行CNOT门操作后的第一预设辅助比特的量子态可以为|1>态时，才控制执行求补码运算对应的量子态演化，否则不执行；
对当前第一符号位量子比特和第一预设辅助比特执行CNOT门操作，以将当前第一预设辅助比特的量子态进行还原；其中，所述第一符号位量子比特为控制比特，所述第一预设辅助比特为受控比特。
示例性的，第一目标量子态假设为|0011>。|0011>的符号位子量子态为最高位的子量子态即|0>态，该位的值为0，对应的第一符号位量子比特设为a.sign，第一预设辅助比特为预设的量子比特q1，初始为|0>态。
对a.sign和q1执行CNOT门操作，a.sign作为控制比特，q1作为受控比特，a.sign位的量子态为|0>态，经过CNOT门操作后，受控比特位q1的量子态|0>不变。
由于执行CNOT门操作后的q1的量子态为|0>态，故不对第一目标量子态执行求补码运算对应的量子态演化。原理上在于，被减数为正数时，在减法运算中无需求补码，或者说，其补码即为本身，可直接将|0011>作为第一补码量子态。
最后，可以对当前a.sign和q1再次执行CNOT门，a.sign位的量子态为|0>态，经过CNOT门操作后，受控比特位q1的量子态|0>不变，以还原q1为|0>态，从而释放第一预设辅助比特存储的信息。可得，第一补码量子态包含的值0011为被减数0011的补码。
如图15所示，q 1为第一预设辅助比特，用于控制是否做补码操作，所述第一目标量子态为a，a.sign为所述第一目标量子态中的符号位子量子态，剩余的a为表示所述数据数值的数值位子量子态，j为第二预设辅助比特，初始态为0态，在求补码之前通过X门被设置为1态，t为加法器所使用的辅助比特(下述第三预设辅助比特)，初始态为0态。
图15所示的量子线路实现了对a做求补码的操作的量子线路，先对a.sign与q 1进行CNOT门操作，使得q 1暂时表示a.sign，并用q 1控制是否进行求补码，求完补码后，再将q 1还原。由此，控制第一目标量子态执行求补码运算对应的量子态演化，得到第一补码量子态。
具体地，根据a的符号位子量子态，用第一预设辅助比特q 1来控制是否做取补码的操作。若a为负数，则进行负数的取补码操作。负数的补码为除符号位外按位取反后加1，除符号位外按位取反的操作用逻辑门来实现的话，只需要对数值位全都做X门即可，取反后还需要加1，因此，通过使用j和a相加，j的当前值被设置为了1，t为加法器的辅助比特，在将数值位取反后的a和j相加后，a上存放的就是取完补码后的数值，再将q 1还原，以便下次使用。
例子：当a为负数时，a.sign为1，因此q 1也为1，就需要做取反等操作，而当a为正数时，a.sign为0，因此q 1也为0，就不需要再求补码了。
S2203，将所述第二目标量子态中的符号位子量子态执行符号位取反对应的量子态演化，并根据取反后的符号位子量子态和所述第一预设辅助比特的量子态，控制当前第二目标量子态执行求补码运算对应的量子态演化，得到第二补码量子态；其中，所述第二补码量子态为包含所述减数数据的补码的量子态；
具体的，可以对第二目标量子态中的符号位子量子态对应的第二符号位量子比特，执行X门操作，得到取反后的符号位子量子态；其中，X门可以用等效的其他现有的量子逻辑门或量子逻辑门组合进行替代，也是合理可行的；
同样的，继续对当前第二符号位量子比特和第一预设辅助比特执行CNOT门操作，其中，所述第二符号位量子比特为控制比特，所述第一预设辅助比特为受控比特；
根据执行CNOT门操作后的第一预设辅助比特的当前量子态，控制当前第二目标量子态是否执行求补码运算对应的量子态演化；
若是，则对当前第二目标量子态的非符号位子量子态取反，并将取反后的第二目标量子态与第二预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第二补码量子态，否则，将当前第二目标量子态作为第二补码量子态；
对当前第二符号位量子比特和第一预设辅助比特执行CNOT门操作，以将第一预设辅助比特的当前量子态进行还原；其中，所述第二符号位量子比特为控制比特，所述第一预设辅助比特为受控比特。
示例性的，第二目标量子态假设为|0100>。|0100>的符号位子量子态为最高位的子量子态即|0>态，该位的值为0，对应的第二符号位量子比特设为b.sign，当前第三辅助比特被还原为|0>态。
首先，可以对b.sign执行X门，将对应的符号位子量子态|0>取反为|1>，第二目标量子态变为|1100>。
继续对b.sign和q1执行CNOT门操作，b.sign作为控制比特，q1作为受控比特，当前b.sign位的量子态为|1>态，经过CNOT门操作后，受控比特位q1的量子态|0>被取反为|1>态。
执行CNOT门操作后的q1的量子态为|1>态，故对当前第二目标量子态|1100>执行求补码运算对应的量子态演化。一种执行求补码运算对应的量子态演化的实现如下：
对当前第二目标量子态|1100>的非符号位子量子态取反，并将取反后的第二目标量子态|1011>与第二预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第二补码量子态为|1100>。
其中，可通过执行X门对|1100>的非符号位子量子态|100>取反；为了保持维度一致，第二预设辅助比特j为预设的4位量子比特j [3]、j [2]、j [1]、j [0]，第二预设辅助比特的量子态|1>实际上写为|0001>，两者是等同的。
最后，可对当前b.sign和q1再次执行CNOT门，b.sign位的量子态为|1>态，经过CNOT门操作后，受控比特位q1的量子态|1>被取反为|0>，从而再次还原q1为初始|0>态，释放q1的存储空间。可得，第二补码量子态包含的值1100为对b.sign执行X门后的减数1100的补码。
本实施例中，所述第二目标量子态b也是同理，j的初始态为0态，初始对j [0]做X门是为了设置值为1，对第二目标量子态中的符号位子量子态b.sign做X门是为了把减法变成加法。如图16所示，图16为对a、b执行求补码运算对应的量子态演化的量子线路示意图，参考上述同理方法将 第二目标量子态b执行求补码运算对应的量子态演化，得到第二补码量子态。
S2204，对所述第一补码量子态和所述第二补码量子态，执行加法运算对应的量子态演化，以将所述第一补码量子态演化为包含所述被减数数据的补码与所述减数数据的补码之和的第三目标量子态；
示例性的，对第一补码量子态为|0011>和第二补码量子态为|1100>，执行加法运算对应的量子态演化，将第一补码量子态|0011>演化为第五目标量子态|1111>。
本实施例中，在求完补码后，将a和b进行加法操作，加完后，再将之前的操作进行还原，a内储存的即为所求。将所述第一补码量子态和所述第二补码量子态代入加法器的量子线路，执行加法运算对应的量子态演化，由此，将所述第一补码量子态演化为包含所述被减数数据的补码与所述减数数据的补码之和的第三目标量子态。
S2205，根据所述第三目标量子态中的符号位子量子态和所述第一预设辅助比特的量子态，控制所述第三目标量子态执行求补码运算对应的量子态演化，得到演化后的第四目标量子态，作为所述被减数数据和所述减数数据的减法运算结果进行输出；其中，所述第四目标量子态为包含所述补码之和的补码的量子态。
示例性的，根据当前第五目标量子态|1111>中的符号位子量子态|1>和当前第一预设辅助比特的量子态|0>，控制第五目标量子态|1111>执行求补码运算对应的量子态演化，得到演化后的第六目标量子态|1001>，其包含的值为1001(十进制-1)，即为第一目标量子态|0011>包含的被减数0011(十进制3)与第二目标量子态|0100>包含的减数0100(十进制4)的减法结果。
需要说明的是，执行求补码运算对应的量子态演化可与前述同理，演化后，第一预设辅助比特的量子态仍被还原为|0>，以便于后续计算使用。
进一步地，所述控制所述第三目标量子态执行求补码运算对应的量子态演化，得到演化后的第四目标量子态的步骤之后，还可以根据当前第二目标量子态中的符号位子量子态和当前第一预设辅助比特的量子态，控制当前第二目标量子态执行求补码运算对应的量子态演化，并对当前第二目标量子态中的符号位子量子态执行符号位取反对应的量子态演化，以将当前第二目标量子态进行还原。
示例性的，当前第二目标量子态为第二补码量子态|1100>，当前第一预设辅助比特的量子态为|0>。继续按前述同理的方式，控制|1100>执行求补码运算对应的量子态演化，得到演化后的|1100>，然后通过X门操作对其符号位子量子态取反，将其还原成初始的第二目标量子态|0100>。
本实施例中，进行加法运算后，进一步对所述被减数数据的补码与所述减数数据的补码之和的第三目标量子态执行求补码运算对应的量子态演化。如图17所示，将a和b都做好补码的处理完成后，再将a和b的补码进行相加，在a上得到加法结果后，再对a做一次求补码的操作，将a演化为最终减法结果；通过对b做一次求补码和通过X门对b的符号位再取反，以对b进行还原；并且通过最后一个CNOT门对第一预设辅助比特q1进行还原，通过X门再对j [0]取反还原为初始0态，从而由图16和图17得到如图18所示的整个减法器的简易量子线路图。
进一步地，所述执行加法运算对应的量子态演化，可以包括：
S2301,根据待运算的两个量子态对应的量子比特位的位数，确定待级联的前级联模块MAJ模块以及待级联的后级联模块UMA模块的目标模块个数，其中，所述MAJ模块的模块个数与所述UMA模块的模块个数相同；
由前述可知，待运算的两个量子态，可以是：第一补码量子态和第二补码量子态；取反后的第一目标量子态和第二预设辅助比特的量子态|1>态。
示例性的，如图19所示，线路中第一个量子比特位为第三预设辅助比特位，初始为|0>态，最终会恢复为|0>态，e和f是待相加的数据对应的量子态，各对应一组量子比特位。c表示最终的进位项，对应预设进位辅助比特位，s为是不包含进位的输出位。一般要求e和f对应的量子比特位数相同,s和e、f的位数相同。
示例性的，如图20所示，e [i]和f [i]分别是两个加数对应量子态的第i位，c [i]是上一级进位。
s [i]＝e [i]XOR f [i]XOR c [i]，
c [i+1]＝(e [i]AND f [i])XOR(e [i]AND f [i])XOR(e [i]AND f [i])，
其中，第一个量子比特即为第三预设辅助比特位，对应量子线路中的c 0。第一个MAJ模块包括三个输入量子态以及对应的三个输出量子态，其中，三个输入量子态分别为c 0、e 0、f 0，e 0为第一个待运算量子态的第0位量子态，f 0为第二个待运算量子态的第0位量子态，c 0为第三预设辅助比特的量子态，初始值为0，即无进位。三个输出量子态分别为
Figure PCTCN2021119125-appb-000004
c 1，c 1为e 0和f 0相加后的进位，同理，下一个MAJ模块的三个输入量子态为c 1、e 1、f 1，三个输出量子态分别为
Figure PCTCN2021119125-appb-000005
c 2，以此类推至最后一个MAJ模块。
对于第一个UMA模块，包括三个输入量子态以及对应的三个输出量子态，其中，MAJ模块的三个输出量子态为对应UMA模块的三个输入量子态，三个输出量子态分别为c 0、s 0、e 0，s 0为e 0和f 0相加的不含进位的结果。同理，s1为e 1和f 1相加的不含进位的结果，以此类推，c4是最终的进位项。需要说明的是，在实际应用中，在无计算最终进位的需求下，量子线路中可以不设置c4对应的量子比特位。
并且，可以根据其中待运算的任一量子态包含的子量子态数量确定MAJ模块的模块个数以及UMA模块的个数，一子量子态对应一位量子比特，其中，MAJ模块的模块个数以及UMA模块的个数相等。图20中所示仅仅作为示例，编码e和f各所需4位量子比特，MAJ模块和UMA模块的个数均为4。MAJ模块和UMA模块构成了加法器的前、后级联单元。MAJ模块可以用于提取出任何一步的进位项并且传递到下一级，从而将最终进位项计算出来。UMA模块一方面提取了c的信息会传递到上一级UMA，还计算出每一级的s(结果项)，并且恢复了e的信息。
示例性的：当4(对应编码在3个量子比特的量子态表示为100)+2(对应编码在3个量子比特的量子态表示为010)＝6(对应编码在3个量子比特的量子态表示为110)。此时编码运算结果的量子比特与编码e的量子比特位的个数或用来编码f的量子比特位的个数一致，MAJ模块的模块个数以及UMA模块的个数均为3。
示例性的：当4(对应编码在3个量子比特的量子态表示为100)+7(对应编码在3个量子比特的量子态表示为111)＝11(对应编码在3个量子比特的量子态表示为011)，但是，可以理解的是11对应的二进制数为1011，最左侧的1所在的位为进位项，该进位项可以通过辅助比特位表示。此时编码运算结果的量子比特与编码e的量子比特位的个数或用来编码f的量子比特位的个数要多，MAJ模块的模块个数以及UMA模块的个数均为3。
示例性的，当2(对应编码在2个量子比特的量子态表示为10)+4(对应编码在3个量子比特的量子态表示为100)＝6(对应编码在3个量子比特的量子态表示为110)。此时，编码“6”数值的数值项“3”与编码b的量子比特位的量子态个数一致，MAJ模块的模块个数以及UMA模块的个数均为3。
S2302,根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成所述加法器对应的目标量子线路；
其中，所述MAJ模块以及所述UMA模块均包括三个输入项以及三个输出项，可以根据加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路，其中，所述MAJ级联模块由所述目标模块个数的MAJ模块之间级联确定，所述UMA级联模块由所述目标模块个数的UMA模块之间级联确定。
具体地，所述MAJ模块的三个输入项包括一个进位输入项以及两个待计算子量子态输入项，所述MAJ模块的三个输出项包括一个进位输出项和两个中间结果输出项，所述UMA模块的三个输入项包括对应MAJ模块的一个进位输出项以及两个中间结果输出项，所述UMA模块的三个输出项包括一个结果进位输出项、累加和输出项和一待计算子量子态输入项，
然后，可以根据加法指令，将上一MAJ模块输出的进位输出项以及所述两个待计算子量子态输入项作为下一MAJ模块的三个输入项，以将所述目标模块个数的MAJ模块进行级联；
将一MAJ模块的两个中间结果输出项作为一对应UMA模块的两个输入项，获取所述对应UMA模块的上一UMA模块，并将所述上一UMA模块的结果进位输出项作为所述对应UMA模块的一个输入项，以将所述目标模块个数的MAJ模块以及所述目标模块个数的UAM模块进行级联，生成所述初始量子线路；其中，最后一个MAJ模块的进位输出项作为对应的第一个UMA模块的一个输入项；
将所述初始量子线路中最后一个MAJ模块与对应的第一个UMA模块之间添加CNOT量子逻辑门，其中，将所述MAJ模块的进位输出项对应的量子比特作为控制比特，将预设进位辅助比特位作为受控比特位，以生成所述加法器的目标量子线路。在不需要进位项的情况下，可以不设置该CNOT门以及进位辅助比特位。
本实施例中，如图20所示，根据图示方式，将所述MAJ模块的三个输出比特作为所述UMA模块的三个输入比特，由此，将相同个数的MAJ模块以及UMA模块进行级联，生成所述加法器对应的目标量子线路。其中，线路图中相连的空心圆与实心圆，表示CNOT门操作，空心圆对应量子比特为控制比特位，实心圆对应为受控比特位。
其中，所述MAJ模块为MAJ量子线路，所述UMA模块为UMA量子线路，所述MAJ量子线路和所述UMA量子线路均包括两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门，所述根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成所述加法器对应的目标量子线路的步骤之前，还包括：获取所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门对应的操作量子比特、操作量子比特之间的控制关系以及所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门之间的时序关系；根据所述操作量子比特、所述控制关系以及所述时序关系，将所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门构建生成所述MAJ量子线路或所述UMA量子线路，作为对应的MAJ模块或UMA模块。
本实施例中，MAJ模块和UMA模块构成了加法器的前、后级联单元。如图21所示，MAJ模块用于提取出每一级加法运算后的进位项并且传递到下一级，从而将最终进位项计算出来。其中，如图22所示，MAJ模块主要可以由三个逻辑门组成，分别是两个CNOT门和一个Toffoli门。CNOT门(图22中的由左向右的第一个、第二个逻辑门)的作用为：将控制位加到目标位上去，形成一个模2加法，即为异或操作，得到(e i+c i)％2、(e i+f i)％2，两个CNOT门的顺序可以交换。Toffoli门(图22中的由左向右的第三个逻辑门)的作用为：将两个控制位都加到目标位上去,得到进位项c [i+1]＝(e [i]AND f [i])XOR(e [i]AND f [i])XOR(e [i]AND f [i])。即通过图22中的由左向右的第一个CNOT门实现
Figure PCTCN2021119125-appb-000006
通过图24中的由左向右的第二个CNOT门实现
Figure PCTCN2021119125-appb-000007
通过图22中的由左向右的第三个TOFFOLI门实现c i+1，由此通过2个CNOT门和1个TOFFOLI门，构成量子加法器的前级级联单元。
例子1：e i为1，f i为1，c i为1。
MAJ模块开始把e i加到c i上，c i上的值变为0，再把e i加到f i上，f i上的值也变为0，最后用f i和c i加到e i上，e i的值变为1，也就是c i+1的进位为1。
例子2：e i为0，f i为1，c i为1。
MAJ模块开始把e i加到c i上，c i上的值变为1，再把e i加到f i上，f i上的值也变为1，最后用f i和c i加到e i上，e i的值变为1，也就是c i+1的进位为1。
如图23所示，UMA模块用于级联加法器的后级，UMA模块的实现方式和MAJ模块类似，如图24所示，首先使用Toffoli门(图24中的由左向右的第一个逻辑门)将c i+1还原为e i，再用e i对(e+c)％2用CNOT门(图24中的由左向右的第二个逻辑门)做一次还原，将(e i+c i)％2还原为c i，最后，再使用c i对(e i+f i)％2做一次CNOT门(图24中的由左向右的第三个逻辑门)，得到当前位的最终结果s [i]＝e [i]XOR f [i]XOR c [i]。
例子1：(e i+c i)％2为0，(e i+f i)％2为0，c i+1为1。
开始把(e i+c i)％2和(e i+f i)％2加到c i+1上，c i+1的值变为1，表示的意义变为e i，再用e i加到(e i+c i)％2上，(e i+c i)％2的值变为1，表示的意义变为c i,再用c i加到(e i+f i)％2上，(e i+f i)％2的值变为1，意义变为s i。
例子2：(e i+c i)％2为1，(e i+f i)％2为1，c i+1为1。
开始把(e i+c i)％2和(e i+f i)％2加到c i+1上，c i+1的值变为0，意义变为e i，再用e i加到(e i+c i)％2上，(e i+c i)％2的值变为1，意义变为c i,再用c i加到(e i+f i)％2上，(e i+f i)％2的值变为0，意义变为s i。
如图22中由上向下的最后一个CNOT门，即整个加法器MAJ模块和UMA模块中间的CNOT门，用于保存c i+1的结果。
S2303，通过所述目标量子线路对所述待运算的两个量子态的各子量子态进行加法运算，生成目标量子态结果并输出。
本实施例中，通过将待运算的两个量子态，如|111>和|111>，输入加法器(即所述目标量子线路)中，得到对应的二进制表示目标量子态计算结果(包括进位项以及各子量子态直接相加得到的结果项)。然后将二进制表示的目标量子态结果|1110>直接输出，或进一步转化为十进制结果14并输出，完成两目标数据的加法运算。
可见，将所述被减数数据转换为第一目标量子态，将所述减数数据转换为第二目标量子态；控制所述第一目标量子态执行求补码运算对应的量子态演化，得到第一补码量子态；控制当前第二目标量子态执行求补码运算对应的量子态演化，得到第二补码量子态；对所述第一补码量子态和所述第二补码量子态，执行加法运算对应的量子态演化，得到第三目标量子态；控制所述第三目标量子态执行求补码运算对应的量子态演化，得到演化后的第四目标量子态，从而实现可以用于量子线路中的减法运算操作，填补了相关技术的空白。
参见图25，本发明的另一实施例提供了一种量子减法运算装置，所述量子减法运算装置包括：
运算数据获取模块21301，用于获取待运算的被减数数据和减数数据，并将所述被减数数据转换为第一目标量子态，将所述减数数据转换为第二目标量子态；其中，目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态；
第一量子态演化模块21302，用于获取第一预设辅助比特的量子态，根据所述第一目标量子态中的符号位子量子态和所述第一预设辅助比特的量子态，控制所述第一目标量子态执行求补码运算对应的量子态演化，得到第一补码量子态；其中，所述第一补码量子态为包含所述被减数数据的补码的量子态；
第二量子态演化模块21303，用于将所述第二目标量子态中的符号位子量子态执行符号位取反对应的量子态演化，并根据取反后的符号位子量子态和所述第一预设辅助比特的量子态，控制当前第二目标量子态执行求补码运算对应的量子态演化，得到第二补码量子态；其中，所述第二补码量子态为包含所述减数数据的补码的量子态；
第三量子态演化模块21304，用于对所述第一补码量子态和所述第二补码量子态，执行加法运算对应的量子态演化，以将所述第一补码量子态演化为包含所述被减数数据的补码与所述减数数据的补码之和的第三目标量子态；
目标量子运算模块21305，用于根据所述第三目标量子态中的符号位子量子态和所述第一预设辅助比特的量子态，控制所述第三目标量子态执行求补码运算对应的量子态演化，得到演化后的第四目标量子态，作为所述被减数数据和所述减数数据的减法运算结果进行输出；其中，所述第四目标量子态为包含所述补码之和的补码的量子态。
具体的，在所述目标量子运算模块之后，所述装置还包括：
还原模块，用于根据当前第二目标量子态中的符号位子量子态和当前第一预设辅助比特的量子态，控制当前第二目标量子态执行求补码运算对应的量子态演化，并对当前第二目标量子态中的 符号位子量子态执行符号位取反对应的量子态演化，以将当前第二目标量子态进行还原。
具体的，所述第一量子态演化模块，具体用于：
对所述第一目标量子态中的符号位子量子态对应的第一符号位量子比特和所述第一预设辅助比特执行CNOT门操作，其中，所述第一符号位量子比特为控制比特，所述第一预设辅助比特为受控比特；
根据执行CNOT门操作后的所述第一预设辅助比特的量子态，控制当前第一目标量子态是否执行求补码运算对应的量子态演化；
若是，则对当前第一目标量子态的非符号位子量子态取反，并将取反后的第一目标量子态与第二预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第一补码量子态，否则，将所述第一目标量子态作为第一补码量子态；
对当前第一符号位量子比特和第一预设辅助比特执行CNOT门操作，以将当前第一预设辅助比特的量子态进行还原；其中，所述第一符号位量子比特为控制比特，所述第一预设辅助比特为受控比特。
具体的，所述第二量子态演化模块，具体用于：
所述第二目标量子态中的符号位子量子态对应的第二符号位量子比特，执行X门操作，得到取反后的符号位子量子态；
对当前第二符号位量子比特和第一预设辅助比特执行CNOT门操作，其中，所述第二符号位量子比特为控制比特，所述第一预设辅助比特为受控比特；
根据执行CNOT门操作后的第一预设辅助比特的当前量子态，控制当前第二目标量子态是否执行求补码运算对应的量子态演化；
若是，则对当前第二目标量子态的非符号位子量子态取反，并将取反后的第二目标量子态与第二预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第二补码量子态，否则，将当前第二目标量子态作为第二补码量子态；
对当前第二符号位量子比特和第一预设辅助比特执行CNOT门操作，以将第一预设辅助比特的当前量子态进行还原；其中，所述第二符号位量子比特为控制比特，所述第一预设辅助比特为受控比特。
具体的，所述第三量子态演化模块，包括：
确定单元，用于根据待运算的两个量子态对应的量子比特位的位数，确定待级联的前级联模块MAJ模块以及待级联的后级联模块UMA模块的目标模块个数，其中，所述MAJ模块的模块个数与所述UMA模块的模块个数相同；
级联单元，用于根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成加法器对应的目标量子线路；
运算单元，用于通过所述目标量子线路对所述待运算的两个量子态的各子量子态进行加法运算，生成目标量子态结果并输出。
具体的，所述MAJ模块为MAJ量子线路，所述UMA模块为UMA量子线路，所述MAJ量子线路和所述UMA量子线路均包括两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门，
在所述级联单元之前，所述第三量子态演化模块还包括：
获取单元，用于获取所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门对应的操作量子比特、操作量子比特之间的控制关系以及所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门之间的时序关系；
构建单元，用于根据所述操作量子比特、所述控制关系以及所述时序关系，将所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门构建生成所述MAJ量子线路或所述UMA量子线路，作为对应的MAJ模块或UMA模块。
具体的，所述MAJ模块以及所述UMA模块均包括三个输入项以及三个输出项；所述级联 单元，包括：
级联子单元，用于根据加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路，其中，所述MAJ级联模块由所述目标模块个数的MAJ模块之间级联确定，所述UMA级联模块由所述目标模块个数的UMA模块之间级联确定。
如上所述的，其中，优选的是，所述MAJ模块的三个输入项包括一个进位输入项以及两个待计算子量子态输入项，所述MAJ模块的三个输出项包括一个进位输出项和两个中间结果输出项，所述UMA模块的三个输入项包括对应MAJ模块的一个进位输出项以及两个中间结果输出项，所述UMA模块的三个输出项包括一个结果进位输出项、累加和输出项和一待计算子量子态输入项；所述级联子单元具体用于：
根据加法指令，将上一MAJ模块输出的进位输出项以及所述两个待计算子量子态输入项作为下一MAJ模块的三个输入项，以将所述目标模块个数的MAJ模块进行级联；
将一MAJ模块的两个中间结果输出项作为一对应UMA模块的两个输入项，获取所述对应UMA模块的上一UMA模块，并将所述上一UMA模块的结果进位输出项作为所述对应UMA模块的一个输入项，以将所述目标模块个数的MAJ模块以及所述目标模块个数的UAM模块进行级联，生成所述初始量子线路；其中，最后一个MAJ模块的进位输出项作为对应的第一个UMA模块的一个输入项；
将所述初始量子线路中最后一个MAJ模块与对应的第一个UMA模块之间添加CNOT量子逻辑门，其中，将所述MAJ模块的进位输出项对应的量子比特作为控制比特，将预设进位辅助比特位作为受控比特位，以生成所述加法器的目标量子线路。
可见，将所述被减数数据转换为第一目标量子态，将所述减数数据转换为第二目标量子态；控制所述第一目标量子态执行求补码运算对应的量子态演化，得到第一补码量子态；控制当前第二目标量子态执行求补码运算对应的量子态演化，得到第二补码量子态；对所述第一补码量子态和所述第二补码量子态，执行加法运算对应的量子态演化，得到第三目标量子态；控制所述第三目标量子态执行求补码运算对应的量子态演化，得到演化后的第四目标量子态，从而实现可以用于量子线路中的减法运算操作，填补了相关技术的空白。
本发明的再一实施例提供了一种电子装置，包括存储器和处理器，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行如下所述的方法：
S1，获取待运算的被减数数据和减数数据，并将所述被减数数据转换为第一目标量子态，将所述减数数据转换为第二目标量子态；其中，目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态；
S2，获取第一预设辅助比特的量子态，根据所述第一目标量子态中的符号位子量子态和所述第一预设辅助比特的量子态，控制所述第一目标量子态执行求补码运算对应的量子态演化，得到第一补码量子态；其中，所述第一补码量子态为包含所述被减数数据的补码的量子态；
S3，将所述第二目标量子态中的符号位子量子态执行对应的量子态演化，并根据取反后的符号位子量子态和所述第一预设辅助比特的量子态，控制当前第二目标量子态执行求补码运算对应的量子态演化，得到第二补码量子态；其中，所述第二补码量子态为包含所述减数数据的补码的量子态；
S4，对所述第一补码量子态和所述第二补码量子态，执行加法运算对应的量子态演化，以将所述第一补码量子态演化为包含所述被减数数据的补码与所述减数数据的补码之和的第三目标量子态；
S5，根据所述第三目标量子态中的符号位子量子态和所述第一预设辅助比特的量子态，控制所述第三目标量子态执行求补码运算对应的量子态演化，得到演化后的第四目标量子态，作为所述被减数数据和所述减数数据的减法运算结果进行输出；其中，所述第四目标量子态为包含所述补 码之和的补码的量子态。
本发明的再一实施例提供了一种存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行如下所述的方法：
S1，获取待运算的被减数数据和减数数据，并将所述被减数数据转换为第一目标量子态，将所述减数数据转换为第二目标量子态；其中，目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态；
S2，获取第一预设辅助比特的量子态，根据所述第一目标量子态中的符号位子量子态和所述第一预设辅助比特的量子态，控制所述第一目标量子态执行求补码运算对应的量子态演化，得到第一补码量子态；其中，所述第一补码量子态为包含所述被减数数据的补码的量子态；
S3，将所述第二目标量子态中的符号位子量子态执行对应的量子态演化，并根据取反后的符号位子量子态和所述第一预设辅助比特的量子态，控制当前第二目标量子态执行求补码运算对应的量子态演化，得到第二补码量子态；其中，所述第二补码量子态为包含所述减数数据的补码的量子态；
S4，对所述第一补码量子态和所述第二补码量子态，执行加法运算对应的量子态演化，以将所述第一补码量子态演化为包含所述被减数数据的补码与所述减数数据的补码之和的第三目标量子态；
S5，根据所述第三目标量子态中的符号位子量子态和所述第一预设辅助比特的量子态，控制所述第三目标量子态执行求补码运算对应的量子态演化，得到演化后的第四目标量子态，作为所述被减数数据和所述减数数据的减法运算结果进行输出；其中，所述第四目标量子态为包含所述补码之和的补码的量子态。
上述实施例可以总结如下。
C21.一种量子减法运算方法，其特征在于，所述方法包括：获取待运算的被减数数据和减数数据，并将所述被减数数据转换为第一目标量子态，将所述减数数据转换为第二目标量子态；其中，目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态；获取第一预设辅助比特的量子态，根据所述第一目标量子态中的符号位子量子态和所述第一预设辅助比特的量子态，控制所述第一目标量子态执行求补码运算对应的量子态演化，得到第一补码量子态；其中，所述第一补码量子态为包含所述被减数数据的补码的量子态；将所述第二目标量子态中的符号位子量子态执行对应的量子态演化，并根据取反后的符号位子量子态和所述第一预设辅助比特的量子态，控制当前第二目标量子态执行求补码运算对应的量子态演化，得到第二补码量子态；其中，所述第二补码量子态为包含所述减数数据的补码的量子态；对所述第一补码量子态和所述第二补码量子态，执行加法运算对应的量子态演化，以将所述第一补码量子态演化为包含所述被减数数据的补码与所述减数数据的补码之和的第三目标量子态；根据所述第三目标量子态中的符号位子量子态和所述第一预设辅助比特的量子态，控制所述第三目标量子态执行求补码运算对应的量子态演化，得到演化后的第四目标量子态，作为所述被减数数据和所述减数数据的减法运算结果进行输出；其中，所述第四目标量子态为包含所述补码之和的补码的量子态。
C22.根据C21所述的方法，其特征在于，所述控制所述第三目标量子态执行求补码运算对应的量子态演化，得到演化后的第四目标量子态的步骤之后，还包括：根据当前第二目标量子态中的符号位子量子态和当前第一预设辅助比特的量子态，控制当前第二目标量子态执行求补码运算对应的量子态演化，并对当前第二目标量子态中的符号位子量子态执行符号位取反对应的量子态演化，以将当前第二目标量子态进行还原。
C23.根据C21或C22所述的方法，其特征在于，所述根据所述第一目标量子态中的符号位子量子态和所述第一预设辅助比特的量子态，控制所述第一目标量子态执行求补码运算对应的量子态演化的步骤具体包括：对所述第一目标量子态中的符号位子量子态对应的第一符号位量子比特和所述第一预设辅助比特执行CNOT门操作，其中，所述第一符号位量子比特为控制比特，所述第一 预设辅助比特为受控比特；根据执行CNOT门操作后的所述第一预设辅助比特的量子态，控制当前第一目标量子态是否执行求补码运算对应的量子态演化；若是，则对当前第一目标量子态的非符号位子量子态取反，并将取反后的第一目标量子态与第二预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第一补码量子态，否则，将所述第一目标量子态作为第一补码量子态；对当前第一符号位量子比特和第一预设辅助比特执行CNOT门操作，以将当前第一预设辅助比特的量子态进行还原；其中，所述第一符号位量子比特为控制比特，所述第一预设辅助比特为受控比特。
C24.根据C21-C23中的任何一个所述的方法，其特征在于，所述将所述第二目标量子态中的符号位子量子态执行符号位取反对应的量子态演化，并根据取反后的符号位子量子态和所述第一预设辅助比特的量子态，控制所述第二目标量子态执行求补码运算对应的量子态演化的步骤具体包括：所述第二目标量子态中的符号位子量子态对应的第二符号位量子比特，执行X门操作，得到取反后的符号位子量子态；对当前第二符号位量子比特和第一预设辅助比特执行CNOT门操作，其中，所述第二符号位量子比特为控制比特，所述第一预设辅助比特为受控比特；根据执行CNOT门操作后的第一预设辅助比特的当前量子态，控制当前第二目标量子态是否执行求补码运算对应的量子态演化；若是，则对当前第二目标量子态的非符号位子量子态取反，并将取反后的第二目标量子态与第二预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第二补码量子态，否则，将当前第二目标量子态作为第二补码量子态；对当前第二符号位量子比特和第一预设辅助比特执行CNOT门操作，以将第一预设辅助比特的当前量子态进行还原；其中，所述第二符号位量子比特为控制比特，所述第一预设辅助比特为受控比特。
C25.根据C21-C24中的任何一个所述的方法，其特征在于，所述执行加法运算对应的量子态演化，包括：根据待运算的两个量子态对应的量子比特位的位数，确定待级联的前级联模块MAJ模块以及待级联的后级联模块UMA模块的目标模块个数，其中，所述MAJ模块的模块个数与所述UMA模块的模块个数相同；根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成加法器对应的目标量子线路；通过所述目标量子线路对所述待运算的两个量子态的各子量子态进行加法运算，生成目标量子态结果并输出。
C26.根据C21-C25中的任何一个所述的方法，其特征在于，所述MAJ模块为MAJ量子线路，所述UMA模块为UMA量子线路，所述MAJ量子线路和所述UMA量子线路均包括两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门，所述根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成加法器对应的目标量子线路的步骤之前，还包括：获取所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门对应的操作量子比特、操作量子比特之间的控制关系以及所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门之间的时序关系；根据所述操作量子比特、所述控制关系以及所述时序关系，将所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门构建生成所述MAJ量子线路或所述UMA量子线路，作为对应的MAJ模块或UMA模块。
C27.根据C21-C26中的任何一个所述的方法，其特征在于，所述MAJ模块以及所述UMA模块均包括三个输入项以及三个输出项，所述根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成所述加法器对应的目标量子线路的步骤具体包括：根据加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路，其中，所述MAJ级联模块由所述目标模块个数的MAJ模块之间级联确定，所述UMA级联模块由所述目标模块个数的UMA模块之间级联确定。
C28.根据C21-C27中的任何一个所述的方法，其特征在于，所述MAJ模块的三个输入项包括一个进位输入项以及两个待计算子量子态输入项，所述MAJ模块的三个输出项包括一个进位输出项和两个中间结果输出项，所述UMA模块的三个输入项包括对应MAJ模块的一个进位输出项以及两个中间结果输出项，所述UMA模块的三个输出项包括一个结果进位输出项、累加和输出 项和一待计算子量子态输入项，所述根据加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路的步骤具体包括：根据加法指令，将上一MAJ模块输出的进位输出项以及所述两个待计算子量子态输入项作为下一MAJ模块的三个输入项，以将所述目标模块个数的MAJ模块进行级联；将一MAJ模块的两个中间结果输出项作为一对应UMA模块的两个输入项，获取所述对应UMA模块的上一UMA模块，并将所述上一UMA模块的结果进位输出项作为所述对应UMA模块的一个输入项，以将所述目标模块个数的MAJ模块以及所述目标模块个数的UAM模块进行级联，生成所述初始量子线路；其中，最后一个MAJ模块的进位输出项作为对应的第一个UMA模块的一个输入项；将所述初始量子线路中最后一个MAJ模块与对应的第一个UMA模块之间添加CNOT量子逻辑门，其中，将所述MAJ模块的进位输出项对应的量子比特作为控制比特，将预设进位辅助比特位作为受控比特位，以生成所述加法器的目标量子线路。
C28、一种量子减法运算装置，其特征在于，所述装置包括：运算数据获取模块，用于获取待运算的被减数数据和减数数据，并将所述被减数数据转换为第一目标量子态，将所述减数数据转换为第二目标量子态；其中，目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态；第一量子态演化模块，用于获取第一预设辅助比特的量子态，根据所述第一目标量子态中的符号位子量子态和所述第一预设辅助比特的量子态，控制所述第一目标量子态执行求补码运算对应的量子态演化，得到第一补码量子态；其中，所述第一补码量子态为包含所述被减数数据的补码的量子态；第二量子态演化模块，用于将所述第二目标量子态中的符号位子量子态执行对应的量子态演化，并根据取反后的符号位子量子态和所述第一预设辅助比特的量子态，控制当前第二目标量子态执行求补码运算对应的量子态演化，得到第二补码量子态；其中，所述第二补码量子态为包含所述减数数据的补码的量子态；第三量子态演化模块，用于对所述第一补码量子态和所述第二补码量子态，执行加法运算对应的量子态演化，以将所述第一补码量子态演化为包含所述被减数数据的补码与所述减数数据的补码之和的第三目标量子态；目标量子运算模块，用于根据所述第三目标量子态中的符号位子量子态和所述第一预设辅助比特的量子态，控制所述第三目标量子态执行求补码运算对应的量子态演化，得到演化后的第四目标量子态，作为所述被减数数据和所述减数数据的减法运算结果进行输出；其中，所述第四目标量子态为包含所述补码之和的补码的量子态。
C29、一种电子装置，包括存储器和处理器，其特征在于，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行C21-C27中的任何一个所述的方法。
C210、一种存储介质，其特征在于，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行C21-C27中的任何一个所述的方法。
与现有技术相比，本发明提供的量子减法运算方法，该方法包括将所述被减数数据转换为第一目标量子态，将所述减数数据转换为第二目标量子态；控制所述第一目标量子态执行求补码运算对应的量子态演化，得到第一补码量子态；控制当前第二目标量子态执行求补码运算对应的量子态演化，得到第二补码量子态；对所述第一补码量子态和所述第二补码量子态，执行加法运算对应的量子态演化，得到第三目标量子态；控制所述第三目标量子态执行求补码运算对应的量子态演化，得到演化后的第四目标量子态，从而实现可以用于量子线路中的减法运算操作，填补了相关技术的空白。
本发明的实施例提供了一种量子乘法运算方法，用于实现基本算术运算操作，基本算术运算操作可以为乘法运算，如图26提供的一种量子乘法运算方法的流程示意图，包括：
S3201：获取待运算的被乘数数据和乘数数据，并将所述被乘数数据转换为第一目标量子态，将所述乘数数据转换为第二目标量子态；其中，所述目标量子态存储所述数据的二进制值，所述第一目标量子态对应的量子比特位数至少为所述第二目标量子态对应的量子比特位数的两倍。
具体的，待运算的被乘数数据指乘法运算中被乘的数字，又叫因数，一般来说放在算式的前 面；乘数数据指乘法运算中乘以其他数字的数字，又叫因数，一般来说放在算式的后面。
量子比特位表示的量子态空间，是指量子比特位对应的所有本征态表征的量子态信息，所有本征态的数量为2的量子比特位的个数次方。
量子态，即指量子比特的状态，其本征态在量子算法(或称量子程序)中用二进制表示。例如，一组量子比特为q0、q1、q2，表示第0位、第1位、第2位量子比特，从高位到低位排序为q2q1q0，该组量子比特的量子态为2 3个本征态的叠加态，8个本征态(确定的状态)是指：|000>、|001>、|010>、|011>、|100>、|101>、|110>、|111>，每个本征态与量子比特位对应一致，如|000>态，000从高位到低位对应q2q1q0。简言之，量子态是各本征态组成的叠加态，当其他态的概率幅为0时，即处于其中一个确定的本征态。
例如，待运算数据值为2，用于存储所述待运算数据的一组量子比特位有2位或者更多，例如有5位量子比特，则其量子态可为|00010>,其中，最低位的两位为二进制10，用于表示所述待运算数据的二进制取值。有用信息为最低位的两位信息，故该待运算数据值对应的量子态也可简写为|2>＝|10>。
示例性的，获取待运算的被乘数数据为7，乘数数据为5，则将所述被乘数数据转换为第一目标量子态为|111>，用于存储第一目标量子态的一组量子比特位有3个或者更多；将所述乘数数据转换为第二目标量子态为|101>，由于第一目标量子态对应的量子比特位数至少为第二目标量子态对应的量子比特位数的两倍，因此存储第一目标量子态的量子比特位需要进行量子比特位数的增加，即存储第一目标量子态的一组量子比特位增加到6个量子比特，此时第一目标量子态为|000111>。
S3202：针对所述第二目标量子态存储的二进制值中的每一位，根据当前位的二进制值，控制第一预设辅助比特的第三目标量子态与存储的二进制值左移后的第一目标量子态，执行加法运算对应的量子态演化，获得演化后的存储加法运算结果的第三目标量子态，其中，所述第三目标量子态的初始态为|0>态，所述二进制值左移的左移位数由所述当前位的位数确定。
具体的，针对所述第二目标量子态存储的二进制值中的每一位，根据当前位的二进制值，控制第一预设辅助比特的第三目标量子态与存储的二进制值左移后的第一目标量子态，执行加法运算对应的量子态演化，包括如下步骤：
S32021：获得与所述第一目标量子态对应的量子比特位数相同的第一预设辅助比特，并初始化所述第一预设辅助比特的第三目标量子态为|0>态。
具体的，第一预设辅助比特可用于存储被乘数数据与乘数数据进行乘法运算后的结果，其初始化的第三目标量子态为|0>态，且第一预设辅助比特的位数与存储第一目标量子态对应的量子比特位数相同。
示例性的，接上述示例，存储第一目标量子态的一组量子比特位为6个量子比特，第一目标量子态为|000111>，此时第一预设辅助比特的位数与存储第一目标量子态对应的量子比特位数相同，均为6个量子比特位，且初始化后的第三目标量子态为|000000>态。
S32022：从所述第二目标量子态存储的二进制值中的第一位起，判断当前位的二进制值。
具体的，第二目标量子态存储的二进制值中的第一位即为第二目标量子态的低位，从该低位开始依次判断当前二进制值是否为1。
示例性的，第二目标量子态为|101>，从高位到低位排序为101，预设第二目标量子态存储的二进制值的位置顺序从低位开始，则第一位为二进制值1、第二位为二进制值0、第三位为二进制值1。
S32023：在判断当前位的二进制值为1的情况下，将第一预设辅助比特的当前第三目标量子态与当前第一目标量子态，执行加法运算对应的量子态演化；否则，不做操作。
具体的，接上述示例，初始第一目标量子态为|000111>，第二目标量子态为|101>，第三目标量子态为|000000>，依次判断第二目标量子态当前位的二进制值，若为1，则将第一预设辅助比特的当前第三目标量子态与当前第一目标量子态，执行加法运算对应的量子态演化，即当前第一目 标量子态|000111>与第三目标量子态|000000>执行加法运算对应的量子态演化；若为0，则不进行任何操作。
S32024：利用量子逻辑门，将所述第一目标量子态包含的各子量子态间进行交换，以使所述第一目标量子态存储的二进制值左移一位。
具体的，接上述示例，初始第一目标量子态为|000111>，利用量子逻辑门，将所述第一目标量子态|000111>包含的各子量子态间进行交换，以使所述第一目标量子态存储的二进制值左移一位转换成量子态|001110>。
示例性的，例如利用量子逻辑门SWAP门实现将第一目标量子态|000111>左移一位转换成量子态|001110>。具体的，在存储第一目标量子态的量子线路中，由低位向高位首先在第三个和第四个量子比特位之间插入一个SWAP门，即将第一目标量子态|000111>转换为第一中间量子态|001011>；在第四个和第五个量子比特位之间插入一个SWAP门，即将第一中间量子态|001011>转换为第二中间量子态|001101>；最后在第五个和第六个量子比特位之间插入一个SWAP门，即将二中间量子态|001101>转换为第一目标量子态左移一位后的量子态|001110>。
需要说明的是，上述实现量子态的左移利用了量子逻辑门SWAP门，但在实际实现过程中，并不仅仅局限于一种量子逻辑门，也可以使用多种单量子逻辑门或双量子逻辑门的组合去实现量子态的左移操作，因此凡是能实现上述量子态的左移等转换操作的量子逻辑门的组合，均应包含在本申请的保护范围之内，在此不做具体限定。
S32025：将所述当前位的位数加一，返回执行所述判断当前位的二进制值的步骤，直至所述第二目标量子态存储的二进制值中的最后一位判断完成。
具体的，将所述当前位的位数加一，即将第二目标量子态存储的二进制值的位数加一，由第一位变为第二位，返回执行判断当前位的二进制值的步骤，即返回执行步骤S2022至步骤S2024，直至所述第二目标量子态存储的二进制值中的最后一位判断完成。
示例性的，第二目标量子态为|101>且当前位二进制值1，执行当前第三目标量子态|000000>与第一目标量子态|000111>加法运算对应的量子态演化；执行完成后，第二目标量子态的当前位的位数加一，第二位为二进制值0，返回执行步骤S2022至步骤S2024，其中，第一目标量子态|000111>左移一位转变为量子态|001110>，因第二目标量子态当前位的二进制值为0，不执行第三目标量子态|000000>与第一目标量子态|000111>加法运算对应的量子态演化完成后的量子态与量子态|001110>的加法运算；继续执行步骤S2025，第二目标量子态|101>第三位为二进制值1，返回执行步骤S2022至步骤S2024，其中，当前第一目标量子态|001110>左移一位转变为量子态|011100>，因第二目标量子态当前位的二进制值为1，执行第三目标量子态|000000>与第一目标量子态|000111>加法运算对应的量子态演化完成后的量子态与量子态|011100>的加法运算，获得演化后的存储加法运算结果的第三目标量子态。
S3203：将最终获得的所述第三目标量子态，作为所述被乘数数据和乘数数据的乘法运算结果进行输出。
示例性的，被乘数数据为第一目标量子态|000111>，乘数数据为第二目标量子态|101>，则将最终获得的所述第三目标量子态存储的加法运算结果|100011>，作为所述被乘数数据和乘数数据的乘法运算结果，再将该加法运算结果|100011>可以转换为十进制数35表示并输出结果，也可以直接将二进制运算结果进行输出。
在将最终获得的所述第三目标量子态所存储的运算结果后，还包括：利用量子逻辑门，将当前第一目标量子态还原。
具体的，可以利用量子逻辑门SWAP门将当前第一目标量子态还原为初始状态，方便后续量子线路的使用操作。
由以上介绍可知，在乘法运算操作中，运算的被乘数数据和乘数数据为存储在个数不同的量子比特位，但没有考虑被乘数数据和乘数数据的符号问题(正负值)，因此在进行被乘数数据和乘 数数据的运算中，还需要考虑得到的运算结果的符号，因此需要进行如下步骤，去获取运算结果的正负情况。
获取存储有所述被乘数数据的符号位的第一子量子态和存储有所述乘数数据的符号位的第二子量子态。
具体的，根据周知的乘法规则可知，当被乘数数据和乘数数据符号相同，经过乘法运算后的结果均为正数；被乘数数据和乘数数据符号不同，经过乘法运算后的结果均为负数；其中，被乘数数据和乘数数据的正负号需要用存储符号位的第一子量子态、第二子量子态及其对应的量子比特位来表示。
根据所述第一子量子态和所述第二子量子态，将待存储乘法运算结果的符号位的第三子量子态的初态，演化为存储有乘法运算结果的符号位的第三子量子态的末态。
示例性的，如图27所示的本实施例的一种保存符号位运算结果的示意图，其中a和b两个量子寄存器的值(被乘数和乘数)相乘，计算结果保存到寄存器d中。a.sign为a的符号位，用第一子量子态表示；b.sign为b的符号位，用第二子量子态表示，d.sign为计算结果d的符号位，用第三子量子态表示，并且d.sign初值即第三子量子态的初态，可以设置为|0>。对所述第一子量子态对应的第一符号位量子比特和所述第二子量子态对应的第二符号位量子比特执行CNOT门；其中，第一符号位量子比特作为CNOT门的控制比特(图示黑色圆点，下同)，第二符号位量子比特作为CNOT门的受控比特(图示圈内“+”号，下同)；对当前第二符号位量子比特和待存储乘法运算结果的符号位的第三子量子态对应的第三符号位量子比特执行CNOT门，以将待存储乘法运算结果的符号位的第三子量子态的初态，演化为存储有乘法运算结果的符号位的第三子量子态的末态；其中，第二符号位量子比特作为CNOT门的控制比特，第三符号位量子比特作为CNOT门的受控比特，所述初态为|0>态；对当前第一符号位量子比特和当前第二符号位量子比特执行CNOT门，以将当前第二子量子态进行还原；其中，所述第一符号位量子比特作为所述CNOT门的控制比特，所述第二符号位量子比特作为所述CNOT门的受控比特。
具体的，被乘数数据和乘数数据的正负共有以下情况：即被乘数数据和乘数数据同为正数、同为负数以及一个为正数和一个为负数四种情况。被乘数数据和乘数数据的正负情况用量子态表示可以为：当第一子量子态预设为|0>态，代表被乘数数据为一个正数；第一子量子态预设为|1>态，代表被乘数数据为一个负数；同样的，当第二子量子态预设为|0>态，代表乘数数据为一个正数；第二子量子态预设为|1>态，代表乘数数据为一个负数；因此，经过如图27所示的量子线路后，即经过3个CNOT门操作后的结果如下表所示：
a.sign b.sign d.sign
|0> |0> |0>
|0> |1> |1>
|1> |0> |1>
|1> |1> |0>
从上表可以看出，例如根据第一子量子态|0>和所述第二子量子态|0>，将待存储乘法运算结果的符号位的第三子量子态的初态，演化为存储有乘法运算结果的符号位的第三子量子态的末态，即为|0>态，表示当被乘数数据和乘数数据同为正数时，其运算后的结果也是正数；例如根据第一子量子态|1>和所述第二子量子态|0>，将待存储乘法运算结果的符号位的第三子量子态的初态，演化为存储有乘法运算结果的符号位的第三子量子态的末态，即为|1>态，表示当被乘数数据为负数、乘数数据为正数时，其运算后的结果为负数。
需要说明的是，图27所示仅为本实施例的一种利用CNOT门保存符号位运算结果的示意图，在具体的实现方式中，还可以通过其他量子逻辑门去保存符号位的运算结果，在此不做具体限定。
以下说明执行加法运算对应的量子态演化的具体步骤，用于介绍如何在量子计算机中实现加法运算对应的量子态演化的逻辑电路，并结合预先开发软件QPanda对每个模块进行说明。任何经 典逻辑电路，也可以通过量子线路来表示，经典电路和量子线路一一对应，量子逻辑门/量子线路的输入与输出均是量子态，且输入与输出的量子比特数量相等。量子线路允许量子态以叠加的方式输入，输出的状态即可以相同的方式叠加输出。可逆计算是量子计算的基本，即任何可逆量子线路存在逆线路，也就是说，将每个原有的输出作为输入，正好可以映射到原来的输入上。可逆线路意味着对于每一种输出，都正好有一种输入与之对应，这种映射是一一对应的。
下面详细说明执行加法运算对应的量子态演化的具体实现方式。
具体的，可以通过加法器执行加法运算对应的量子态演化，可以包括：
根据待运算的两个量子态对应的量子比特位的位数，确定待级联的前级联模块MAJ模块以及待级联的后级联模块UMA模块的目标模块个数，其中，所述MAJ模块的模块个数与所述UMA模块的模块个数相同。
示例性的，如图28所示为本发明实施例提供的加法器示意图，线路中第一个量子比特位为第二预设辅助比特位，初始为|0>态，最终会恢复为|0>态，e和f是待相加的数据对应的量子态，各对应一组量子比特位。c表示最终的进位项，对应预设进位辅助比特位，s为是不包含进位的输出位。一般要求e和f对应的量子比特位数相同,s和e、f的位数相同。
示例性的，如图29所示为本发明实施例提供的加法器量子线路示意图，e [i]和f [i]分别是两个加数对应量子态的第i位，c [i]是上一级进位。
s [i]＝e [i]XOR f [i]XOR c [i]，
c [i+1]＝(e [i]AND f [i])XOR(e [i]AND f [i])XOR(e [i]AND f [i])，
其中，第一个量子比特即为第二预设辅助比特位，对应量子线路中的c 0。第一个MAJ模块包括三个输入量子态以及对应的三个输出量子态，其中，三个输入量子态分别为c 0、e 0、f 0，e 0为第一个待运算量子态的第0位量子态，f 0为第二个待运算量子态的第0位量子态，c 0为第二预设辅助比特的量子态，初始值为0，即无进位。三个输出量子态分别为
Figure PCTCN2021119125-appb-000008
c 1，c 1为e 0和f 0相加后的进位，同理，下一个MAJ模块的三个输入量子态为c 1、e 1、f 1，三个输出量子态分别为
Figure PCTCN2021119125-appb-000009
c 2，以此类推至最后一个MAJ模块。
对于第一个UMA模块，包括三个输入量子态以及对应的三个输出量子态，其中，MAJ模块的三个输出量子态为对应UMA模块的三个输入量子态，三个输出量子态分别为c 0、s 0、e 0，s 0为e 0和f 0相加的不含进位的结果。同理，s1为e 1和f 1相加的不含进位的结果，以此类推，c4是最终的进位项。需要说明的是，在实际应用中，在无计算最终进位的需求下，量子线路中可以不设置c4对应的量子比特位。
并且，可以根据其中待运算的任一量子态包含的子量子态数量确定MAJ模块的模块个数以及UMA模块的个数，一子量子态对应一位量子比特，其中，MAJ模块的模块个数以及UMA模块的个数相等。图中所示仅仅作为示例，编码e和f各所需4位量子比特，MAJ模块和UMA模块的个数均为4。MAJ模块和UMA模块构成了加法器的前、后级联单元。MAJ模块可以用于提取出任何一步的进位项并且传递到下一级，从而将最终进位项计算出来。UMA模块一方面提取了c的信息会传递到上一级UMA，还计算出每一级的s(结果项)，并且恢复了e的信息。
示例性的：当4(对应编码在3个量子比特的量子态表示为100)+2(对应编码在3个量子比特的量子态表示为010)＝6(对应编码在3个量子比特的量子态表示为110)。此时编码运算结果的量子比特与编码e的量子比特位的个数或用来编码f的量子比特位的个数一致，MAJ模块的模块个数以及UMA模块的个数均为3。
示例性的：当4(对应编码在3个量子比特的量子态表示为100)+7(对应编码在3个量子比特的量子态表示为111)＝11(对应编码在3个量子比特的量子态表示为011)，但是，可以理解的是11对应的二进制数为1011，最左侧的1所在的位为进位项，该进位项可以通过辅助比特位表示。此时编码运算结果的量子比特与编码e的量子比特位的个数或用来编码f的量子比特位的个数要多，MAJ模块的模块个数以及UMA模块的个数均为3。
示例性的，当2(对应编码在2个量子比特的量子态表示为10)+4(对应编码在3个量子比特的量子态表示为100)＝6(对应编码在3个量子比特的量子态表示为110)。此时，编码“6”数值的数值项“3”与编码b的量子比特位的量子态个数一致，MAJ模块的模块个数以及UMA模块的个数均为3。
根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成加法器对应的目标量子线路。
其中，所述MAJ模块以及所述UMA模块均包括三个输入项以及三个输出项，可以根据加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路，其中，所述MAJ级联模块由所述目标模块个数的MAJ模块之间级联确定，所述UMA级联模块由所述目标模块个数的UMA模块之间级联确定。
具体地，所述MAJ模块的三个输入项包括一个进位输入项以及两个待计算子量子态输入项，所述MAJ模块的三个输出项包括一个进位输出项和两个中间结果输出项，所述UMA模块的三个输入项包括对应MAJ模块的一个进位输出项以及两个中间结果输出项，所述UMA模块的三个输出项包括一个结果进位输出项、累加和输出项和一待计算子量子态输入项，
然后，可以根据加法指令，将上一MAJ模块输出的进位输出项以及所述两个待计算子量子态输入项作为下一MAJ模块的三个输入项，以将所述目标模块个数的MAJ模块进行级联；
将一MAJ模块的两个中间结果输出项作为一对应UMA模块的两个输入项，获取所述对应UMA模块的上一UMA模块，并将所述上一UMA模块的结果进位输出项作为所述对应UMA模块的一个输入项，以将所述目标模块个数的MAJ模块以及所述目标模块个数的UAM模块进行级联，生成所述初始量子线路；其中，最后一个MAJ模块的进位输出项作为对应的第一个UMA模块的一个输入项；
将所述初始量子线路中最后一个MAJ模块与对应的第一个UMA模块之间添加CNOT量子逻辑门，其中，将所述MAJ模块的进位输出项对应的量子比特作为控制比特，将预设进位辅助比特位作为受控比特位，以生成所述加法器的目标量子线路。在不需要进位项的情况下，可以不设置该CNOT门以及进位辅助比特位。
本实施例中，如图29所示，根据图示方式，将所述MAJ模块的三个输出比特作为所述UMA模块的三个输入比特，由此，将相同个数的MAJ模块以及UMA模块进行级联，生成所述加法器对应的目标量子线路。其中，线路图中相连的空心圆与实心圆，表示CNOT门操作，空心圆对应量子比特为控制比特位，实心圆对应为受控比特位。
其中，所述MAJ模块为MAJ量子线路，所述UMA模块为UMA量子线路，所述MAJ量子线路和所述UMA量子线路均包括两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门，所述根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成所述加法器对应的目标量子线路的步骤之前，还包括：获取所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门对应的操作量子比特、操作量子比特之间的控制关系以及所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门之间的时序关系；根据所述操作量子比特、所述控制关系以及所述时序关系，将所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门构建生成所述MAJ量子线路或所述UMA量子线路，作为对应的MAJ模块或UMA模块。
本实施例中，MAJ模块和UMA模块构成了加法器的前、后级联单元。如图30所示为本发明实施例提供的MAJ模块示意图，MAJ模块用于提取出每一级加法运算后的进位项并且传递到下一级，从而将最终进位项计算出来。其中，如图31所示为本发明实施例提供的MAJ模块量子线路组合过程示意图，其中，MAJ模块主要可以由三个逻辑门组成，分别是两个CNOT门和一个Toffoli门。CNOT门(图31中的由左向右的第一个、第二个逻辑门)的作用为：将控制位加到目标位上去，形成一个模2加法，即为异或操作，得到(e i+c i)％2、(e i+f i)％2，两个CNOT门的顺序可以交 换。Toffoli门(图31中的由左向右的第三个逻辑门)的作用为：将两个控制位都加到目标位上去,得到进位项c [i+1]＝(e [i]AND f [i])XOR(e [i]AND f [i])XOR(e [i]AND f [i])。即通过图31中的由左向右的第一个CNOT门实现
Figure PCTCN2021119125-appb-000010
通过图31中的由左向右的第二个CNOT门实现
Figure PCTCN2021119125-appb-000011
通过图31中的由左向右的第三个TOFFOLI门实现c i+1，由此通过2个CNOT门和1个TOFFOLI门，构成量子加法器的前级级联单元。
例子1：e i为1，f i为1，c i为1。
MAJ模块开始把e i加到c i上，c i上的值变为0，再把e i加到f i上，f i上的值也变为0，最后用f i和c i加到e i上，e i的值变为1，也就是c i+1的进位为1。
例子2：e i为0，f i为1，c i为1。
MAJ模块开始把e i加到c i上，c i上的值变为1，再把e i加到f i上，f i上的值也变为1，最后用f i和c i加到e i上，e i的值变为1，也就是c i+1的进位为1。
如图32所示为本发明实施例提供的UMA模块示意图，UMA模块用于级联加法器的后级，UMA模块的实现方式和MAJ模块类似，如图33所示为本发明实施例提供的UMA模块量子线路组合过程示意图，首先使用Toffoli门(图33中的由左向右的第一个逻辑门)将c i+1还原为e i，再用e i对(e+c)％2用CNOT门(图33中的由左向右的第二个逻辑门)做一次还原，将(e i+c i)％2还原为c i，最后，再使用c i对(e i+f i)％2做一次CNOT门(图33中的由左向右的第三个逻辑门)，得到当前位的最终结果s [i]＝e [i]XOR f [i]XOR c [i]。
例子1：(e i+c i)％2为0，(e i+f i)％2为0，c i+1为1。
开始把(e i+c i)％2和(e i+f i)％2加到c i+1上，c i+1的值变为1，表示的意义变为e i，再用e i加到(e i+c i)％2上，(e i+c i)％2的值变为1，表示的意义变为c i,再用c i加到(e i+f i)％2上，(e i+f i)％2的值变为1，意义变为s i。
例子2：(e i+c i)％2为1，(e i+f i)％2为1，c i+1为1。
开始把(e i+c i)％2和(e i+f i)％2加到c i+1上，c i+1的值变为0，意义变为e i，再用e i加到(e i+c i)％2上，(e i+c i)％2的值变为1，意义变为c i,再用c i加到(e i+f i)％2上，(e i+f i)％2的值变为0，意义变为s i。
如图29中由上向下的最后一个CNOT门，即整个加法器MAJ模块和UMA模块中间的CNOT门，用于保存c i+1的结果。
通过所述目标量子线路对所述待运算的两个量子态的各子量子态进行加法运算，生成目标量子态结果并输出。
本实施例中，通过将两个目标量子态的各子量子态，如|111>和|111>、，输入加法器(即所述目标量子线路)中，得到对应的二进制表示目标量子态计算结果(包括进位项以及各子量子态直接相加得到的结果项)。然后将二进制表示的目标量子态结果|1110>直接输出，或进一步转化为十进制结果输出，完成两目标数据的加法运算。
与现有技术相比，本发明提供的一种量子乘法运算方法，用于实现量子线路中的基本乘法运算操作，包括获取待运算的被乘数数据和乘数数据，并将被乘数数据转换为第一目标量子态，将乘数数据转换为第二目标量子态，针对第二目标量子态存储的二进制值中的每一位，根据当前位的二进制值，控制第一预设辅助比特的第三目标量子态与存储的二进制值左移后的第一目标量子态，执行加法运算对应的量子态演化，获得演化后的存储加法运算结果的第三目标量子态，将最终获得的第三目标量子态，作为被乘数数据和乘数数据的乘法运算结果进行输出。本发明通过一种能够实现量子线路中的基本算术运算操作的技术，填补相关技术空白。
参见图34，图34为本发明实施例提供的一种量子乘法运算装置的结构示意图，与图26所示的流程相对应，该装置可以包括：
获取模块31001，用于获取待运算的被乘数数据和乘数数据，并将所述被乘数数据转换为第一目标量子态，将所述乘数数据转换为第二目标量子态；其中，所述目标量子态存储所述数据的二进制值，所述第一目标量子态对应的量子比特位数至少为所述第二目标量子态对应的量子比特位数 的两倍；
控制模块31002，用于针对所述第二目标量子态存储的二进制值中的每一位，根据当前位的二进制值，控制第一预设辅助比特的第三目标量子态与存储的二进制值左移后的第一目标量子态，执行加法运算对应的量子态演化，获得演化后的存储加法运算结果的第三目标量子态，其中，所述第三目标量子态的初始态为|0>态，所述二进制值左移的左移位数由所述当前位的位数确定；
输出模块31003，用于将最终获得的所述第三目标量子态，作为所述被乘数数据和乘数数据的乘法运算结果进行输出。
可选的，所述装置还包括：
存储模块，用于获取存储有所述被乘数数据的符号位的第一子量子态和存储有所述乘数数据的符号位的第二子量子态；
演化模块，用于根据所述第一子量子态和所述第二子量子态，将待存储乘法运算结果的符号位的第三子量子态的初态，演化为存储有乘法运算结果的符号位的第三子量子态的末态。
可选的，所述演化模块，包括：
第一执行单元，用于对所述第一子量子态对应的第一符号位量子比特和所述第二子量子态对应的第二符号位量子比特执行CNOT门；其中，所述第一符号位量子比特作为所述CNOT门的控制比特，所述第二符号位量子比特作为所述CNOT门的受控比特；
第二执行单元，用于对当前第二符号位量子比特和待存储乘法运算结果的符号位的第三子量子态对应的第三符号位量子比特执行CNOT门，以将待存储乘法运算结果的符号位的第三子量子态的初态，演化为存储有乘法运算结果的符号位的第三子量子态的末态；其中，所述第二符号位量子比特作为所述CNOT门的控制比特，所述第三符号位量子比特作为所述CNOT门的受控比特，所述初态为|0>态；
第三执行单元，用于对当前第一符号位量子比特和当前第二符号位量子比特执行CNOT门，以将当前第二子量子态进行还原；其中，所述第一符号位量子比特作为所述CNOT门的控制比特，所述第二符号位量子比特作为所述CNOT门的受控比特。
可选的，所述输出模块之后，所述装置还包括：还原模块，用于利用量子逻辑门，将当前第一目标量子态还原。
可选的，所述控制模块，包括：
获得单元，用于获得与所述第一目标量子态对应的量子比特位数相同的第一预设辅助比特，并初始化所述第一预设辅助比特的第三目标量子态为|0>态；
判断单元，用于从所述第二目标量子态存储的二进制值中的第一位起，判断当前位的二进制值；
第四执行单元，用于在判断当前位的二进制值为1的情况下，将第一预设辅助比特的当前第三目标量子态与当前第一目标量子态，执行加法运算对应的量子态演化；否则，不做操作；
交换单元，用于利用量子逻辑门，将所述第一目标量子态包含的各子量子态间进行交换，以使所述第一目标量子态存储的二进制值左移一位；
添加单元，用于将所述当前位的位数加一，返回执行所述判断当前位的二进制值的步骤，直至所述第二目标量子态存储的二进制值中的最后一位判断完成。
可选的，所述控制模块，包括：
确定单元，用于根据待运算的两个量子态对应的量子比特位的位数，确定待级联的前级联模块MAJ模块以及待级联的后级联模块UMA模块的目标模块个数，其中，所述MAJ模块的模块个数与所述UMA模块的模块个数相同；
第一级联单元，用于根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成加法器对应的目标量子线路；
第一生成单元，用于通过所述目标量子线路对所述两个目标量子态的各子量子态进行加法运 算，生成并输出目标量子态结果并输出。
可选的，在所述第一级联单元之前，所述装置还包括：
获取单元，用于获取所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门对应的操作量子比特、操作量子比特之间的控制关系以及所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门之间的时序关系；
构建单元，用于根据所述操作量子比特、所述控制关系以及所述时序关系，将所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门构建生成所述MAJ量子线路或所述UMA量子线路，作为对应的MAJ模块或UMA模块。
可选的，所述第一级联单元，具体包括：
第二生成单元，用于根据加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路，其中，所述MAJ级联模块由所述目标模块个数的MAJ模块之间级联确定，所述UMA级联模块由所述目标模块个数的UMA模块之间级联确定。
可选的，所述第二生成单元，具体包括：
第二级联单元，用于根据加法指令，将上一MAJ模块输出的进位输出项以及所述两个待计算子量子态输入项作为下一MAJ模块的三个输入项，以将所述目标模块个数的MAJ模块进行级联；
第三级联单元，用于将一MAJ模块的两个中间结果输出项作为一对应UMA模块的两个输入项，获取所述对应UMA模块的上一UMA模块，并将所述上一UMA模块的结果进位输出项作为所述对应UMA模块的一个输入项，以将所述目标模块个数的MAJ模块以及所述目标模块个数的UAM模块进行级联，生成所述初始量子线路；其中，最后一个MAJ模块的进位输出项作为对应的第一个UMA模块的一个输入项；
第三生成单元，用于将所述初始量子线路中最后一个MAJ模块与对应的第一个UMA模块之间添加CNOT量子逻辑门，其中，将所述MAJ模块的进位输出项对应的量子比特作为控制比特，将预设进位辅助比特位作为受控比特位，以生成所述加法器的目标量子线路。
与现有技术相比，本发明提供的一种量子乘法运算方法，用于实现量子线路中的基本乘法运算操作，包括获取待运算的被乘数数据和乘数数据，并将被乘数数据转换为第一目标量子态，将乘数数据转换为第二目标量子态，针对第二目标量子态存储的二进制值中的每一位，根据当前位的二进制值，控制第一预设辅助比特的第三目标量子态与存储的二进制值左移后的第一目标量子态，执行加法运算对应的量子态演化，获得演化后的存储加法运算结果的第三目标量子态，将最终获得的第三目标量子态，作为被乘数数据和乘数数据的乘法运算结果进行输出。本发明通过一种能够实现量子线路中的基本算术运算操作的技术，填补相关技术空白。
本发明实施例还提供了一种存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行上述任一项中方法实施例中的步骤。
具体的，在本实施例中，上述存储介质可以被设置为存储用于执行以下步骤的计算机程序：
S3201：获取待运算的被乘数数据和乘数数据，并将所述被乘数数据转换为第一目标量子态，将所述乘数数据转换为第二目标量子态；其中，所述目标量子态存储所述数据的二进制值，所述第一目标量子态对应的量子比特位数至少为所述第二目标量子态对应的量子比特位数的两倍；
S3202：针对所述第二目标量子态存储的二进制值中的每一位，根据当前位的二进制值，控制第一预设辅助比特的第三目标量子态与存储的二进制值左移后的第一目标量子态，执行加法运算对应的量子态演化，获得演化后的存储加法运算结果的第三目标量子态，其中，所述第三目标量子态的初始态为|0>态，所述二进制值左移的左移位数由所述当前位的位数确定；
S3203：将最终获得的所述第三目标量子态，作为所述被乘数数据和乘数数据的乘法运算结果进行输出。
具体的，在本实施例中，上述存储介质可以包括但不限于：U盘、只读存储器(Read-Only  Memory，简称为ROM)、随机存取存储器(Random Access Memory，简称为RAM)、移动硬盘、磁碟或者光盘等各种可以存储计算机程序的介质。
本发明实施例还提供了一种电子装置，包括存储器和处理器，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行上述任一项中方法实施例中的步骤。
具体的，上述电子装置还可以包括传输设备以及输入输出设备，其中，该传输设备和上述处理器连接，该输入输出设备和上述处理器连接。
具体的，在本实施例中，上述处理器可以被设置为通过计算机程序执行以下步骤：
S3201：获取待运算的被乘数数据和乘数数据，并将所述被乘数数据转换为第一目标量子态，将所述乘数数据转换为第二目标量子态；其中，所述目标量子态存储所述数据的二进制值，所述第一目标量子态对应的量子比特位数至少为所述第二目标量子态对应的量子比特位数的两倍；
S3202：针对所述第二目标量子态存储的二进制值中的每一位，根据当前位的二进制值，控制第一预设辅助比特的第三目标量子态与存储的二进制值左移后的第一目标量子态，执行加法运算对应的量子态演化，获得演化后的存储加法运算结果的第三目标量子态，其中，所述第三目标量子态的初始态为|0>态，所述二进制值左移的左移位数由所述当前位的位数确定；
S3203：将最终获得的所述第三目标量子态，作为所述被乘数数据和乘数数据的乘法运算结果进行输出。
上述实施例可以总结如下。
C31.一种量子乘法运算方法，其特征在于，所述方法包括：获取待运算的被乘数数据和乘数数据，并将所述被乘数数据转换为第一目标量子态，将所述乘数数据转换为第二目标量子态；其中，所述目标量子态存储所述数据的二进制值，所述第一目标量子态对应的量子比特位数至少为所述第二目标量子态对应的量子比特位数的两倍；针对所述第二目标量子态存储的二进制值中的每一位，根据当前位的二进制值，控制第一预设辅助比特的第三目标量子态与存储的二进制值左移后的第一目标量子态，执行加法运算对应的量子态演化，获得演化后的存储加法运算结果的第三目标量子态，其中，所述第三目标量子态的初始态为|0>态，所述二进制值左移的左移位数由所述当前位的位数确定；将最终获得的所述第三目标量子态，作为所述被乘数数据和乘数数据的乘法运算结果进行输出。
C32.根据C31所述的方法，其特征在于，所述方法还包括：获取存储有所述被乘数数据的符号位的第一子量子态和存储有所述乘数数据的符号位的第二子量子态；根据所述第一子量子态和所述第二子量子态，将待存储乘法运算结果的符号位的第三子量子态的初态，演化为存储有乘法运算结果的符号位的第三子量子态的末态。
C33.根据C31或C32所述的方法，其特征在于，所述根据所述第一子量子态和所述第二子量子态，将待存储乘法运算结果的符号位的第三子量子态的初态，演化为存储有乘法运算结果的符号位的第三子量子态的末态，包括：对所述第一子量子态对应的第一符号位量子比特和所述第二子量子态对应的第二符号位量子比特执行CNOT门；其中，所述第一符号位量子比特作为所述CNOT门的控制比特，所述第二符号位量子比特作为所述CNOT门的受控比特；对当前第二符号位量子比特和待存储乘法运算结果的符号位的第三子量子态对应的第三符号位量子比特执行CNOT门，以将待存储乘法运算结果的符号位的第三子量子态的初态，演化为存储有乘法运算结果的符号位的第三子量子态的末态；其中，所述第二符号位量子比特作为所述CNOT门的控制比特，所述第三符号位量子比特作为所述CNOT门的受控比特，所述初态为|0>态；对当前第一符号位量子比特和当前第二符号位量子比特执行CNOT门，以将当前第二子量子态进行还原；其中，所述第一符号位量子比特作为所述CNOT门的控制比特，所述第二符号位量子比特作为所述CNOT门的受控比特。
C34.根据C31-C33中的任何一个所述的方法，其特征在于，所述在将最终获得的所述第三目标量子态所存储的运算结果后，所述方法还包括：利用量子逻辑门，将当前第一目标量子态还原。
C35.根据C31-C34中的任何一个所述的方法，其特征在于，所述针对所述第二目标量子态 存储的二进制值中的每一位，根据当前位的二进制值，控制第一预设辅助比特的第三目标量子态与存储的二进制值左移后的第一目标量子态，执行加法运算对应的量子态演化，包括：获得与所述第一目标量子态对应的量子比特位数相同的第一预设辅助比特，并初始化所述第一预设辅助比特的第三目标量子态为|0>态；从所述第二目标量子态存储的二进制值中的第一位起，判断当前位的二进制值；在判断当前位的二进制值为1的情况下，将第一预设辅助比特的当前第三目标量子态与当前第一目标量子态，执行加法运算对应的量子态演化；否则，不做操作；利用量子逻辑门，将所述第一目标量子态包含的各子量子态间进行交换，以使所述第一目标量子态存储的二进制值左移一位；将所述当前位的位数加一，返回执行所述判断当前位的二进制值的步骤，直至所述第二目标量子态存储的二进制值中的最后一位判断完成。
C36.根据C31-C35中的任何一个所述的方法，其特征在于，所述执行加法运算对应的量子态演化，包括：根据待运算的两个量子态对应的量子比特位的位数，确定待级联的前级联模块MAJ模块以及待级联的后级联模块UMA模块的目标模块个数，其中，所述MAJ模块的模块个数与所述UMA模块的模块个数相同；根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成加法器对应的目标量子线路；通过所述目标量子线路对所述待运算的两个量子态的各子量子态进行加法运算，生成目标量子态结果并输出。
C37.根据C31-C36中的任何一个所述的方法，其特征在于，所述MAJ模块为MAJ量子线路，所述UMA模块为UMA量子线路，所述MAJ量子线路和所述UMA量子线路均包括两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门，所述根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成加法器对应的目标量子线路的步骤之前，还包括：获取所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门对应的操作量子比特、操作量子比特之间的控制关系以及所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门之间的时序关系；根据所述操作量子比特、所述控制关系以及所述时序关系，将所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门构建生成所述MAJ量子线路或所述UMA量子线路，作为对应的MAJ模块或UMA模块。
C38.根据C31-C37中的任何一个所述的方法，其特征在于，所述MAJ模块以及所述UMA模块均包括三个输入项以及三个输出项，所述根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成所述加法器对应的目标量子线路的步骤具体包括：根据加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路，其中，所述MAJ级联模块由所述目标模块个数的MAJ模块之间级联确定，所述UMA级联模块由所述目标模块个数的UMA模块之间级联确定。
C39.根据C31-C38中的任何一个所述的方法，其特征在于，所述MAJ模块的三个输入项包括一个进位输入项以及两个待计算子量子态输入项，所述MAJ模块的三个输出项包括一个进位输出项和两个中间结果输出项，所述UMA模块的三个输入项包括对应MAJ模块的一个进位输出项以及两个中间结果输出项，所述UMA模块的三个输出项包括一个结果进位输出项、累加和输出项和一待计算子量子态输入项，所述根据加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路的步骤具体包括：根据加法指令，将上一MAJ模块输出的进位输出项以及所述两个待计算子量子态输入项作为下一MAJ模块的三个输入项，以将所述目标模块个数的MAJ模块进行级联；将一MAJ模块的两个中间结果输出项作为一对应UMA模块的两个输入项，获取所述对应UMA模块的上一UMA模块，并将所述上一UMA模块的结果进位输出项作为所述对应UMA模块的一个输入项，以将所述目标模块个数的MAJ模块以及所述目标模块个数的UAM模块进行级联，生成所述初始量子线路；其中，最后一个MAJ模块的进位输出项作为对应的第一个UMA模块的一个输入项；将所述初始量子线路中最后一个MAJ模块与对应的第一个UMA模块之间添加CNOT量子逻辑门，其中，将所述MAJ模块的进位输出项对应的量子比特作为控制比特， 将预设进位辅助比特位作为受控比特位，以生成所述加法器的目标量子线路。
C310.一种量子乘法运算装置，其特征在于，所述装置包括：获取模块，用于获取待运算的被乘数数据和乘数数据，并将所述被乘数数据转换为第一目标量子态，将所述乘数数据转换为第二目标量子态；其中，所述目标量子态存储所述数据的二进制值，所述第一目标量子态对应的量子比特位数至少为所述第二目标量子态对应的量子比特位数的两倍；控制模块，用于针对所述第二目标量子态存储的二进制值中的每一位，根据当前位的二进制值，控制第一预设辅助比特的第三目标量子态与存储的二进制值左移后的第一目标量子态，执行加法运算对应的量子态演化，获得演化后的存储加法运算结果的第三目标量子态，其中，所述第三目标量子态的初始态为|0>态，所述二进制值左移的左移位数由所述当前位的位数确定；输出模块，用于将最终获得的所述第三目标量子态，作为所述被乘数数据和乘数数据的乘法运算结果进行输出。
C311.一种电子装置，包括存储器和处理器，其特征在于，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行C31-C39中的任何一个所述的方法。
C312.一种存储介质，其特征在于，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行C31-C39中的任何一个所述的方法。
与现有技术相比，本发明提供的一种量子乘法运算方法，用于实现量子线路中的基本乘法运算操作，包括获取待运算的被乘数数据和乘数数据，并将被乘数数据转换为第一目标量子态，将乘数数据转换为第二目标量子态，针对第二目标量子态存储的二进制值中的每一位，根据当前位的二进制值，控制第一预设辅助比特的第三目标量子态与存储的二进制值左移后的第一目标量子态，执行加法运算对应的量子态演化，获得演化后的存储加法运算结果的第三目标量子态，将最终获得的第三目标量子态，作为被乘数数据和乘数数据的乘法运算结果进行输出。本发明通过一种能够实现量子线路中的基本算术运算操作的技术，填补相关技术空白。
参见图35，图35为本发明实施例提供的一种量子除法运算方法的流程示意图，可以包括如下步骤：
S4201，获取待运算的被除数数据和除数数据，并将所述被除数数据转换为第一目标量子态，将所述除数数据转换为第二目标量子态；其中，所述目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态；
具体的，可以利用现有的振幅编码方式，将待运算的十进制数据转换为二进制的量子态表示。例如，被除数数据为7，带符号的二进制表示0111，最高位为0表示正数，1表示负数；除数数据为4，带符号的二进制表示011。需要说明的是，本实施例中，第一目标量子态和第二目标量子态的最高位均为0，即参与运算的被除数和除数均为正数。
至少获取4位量子比特a.sign、a2、a1、a0，将7编码到a.sign、a2、a1、a0的第一目标量子态|0111>上，量子态的振幅设为1。其中，|0111>＝|0>|1>|1>|1>，|0>、|1>、|1>、|1>称为|0111>的子量子态，一子量子态对应一量子比特位，且从右至左表示由高位至低位，最高位对应a.sign、第三位对应a2、第二位对应a1、最低位对应a0，最高位的|0>表示符号位子量子态，其余表示数值位子量子态。为了统一运算维度，另外获取4位量子比特b.sign、b2、b1、b0，将4编码到b.sign、b2、b1、b0的第二目标量子态|0100>，其振幅同为1。
S4202，对所述第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为负数；其中，每次执行减法运算的被减数为上次执行减法运算的减法结果、减数为所述除数数据；
具体的，减法运算的执行次数是指对第一目标量子态和第二目标量子态执行减法运算对应的量子态演化的次数，也就是迭代次数。
在具体实现中，可以对当前第一目标量子态和第二目标量子态，执行减法运算对应的量子态演化，以获得包含减法运算结果的第一目标量子态；
对当前第一预设辅助比特的第三目标量子态和当前第二预设辅助比特的第四目标量子态，执 行减法运算对应的量子态演化，以将当前第三目标量子态包含的值加1；其中，第三目标量子态包含的初值、第四目标量子态包含的值均为-1；
测量当前包含减法运算结果的第一目标量子态的符号位子量子态，判断当前包含减法运算结果的第一目标量子态的符号位的值是否为0；
在当前包含减法运算结果的第一目标量子态的符号位的值为0的情况下，返回执行对当前第一目标量子态和当前第二目标量子态，执行减法运算对应的量子态演化的步骤，直至判断出当前包含减法运算结果的第一目标量子态的符号位的值为1。
示例性的，当前第一目标量子态和第二目标量子态为|0111>和|0100>。对|0111>和|0100>执行减法运算对应的量子态演化，以将|0111>包含的值0111减去|0100>包含的值0100，得到包含减法运算结果0011的第一目标量子态|0011>，第二目标量子态|0100>不变；
获取4位第一预设辅助比特r.sign、r2、r1、r0，r.sign、r2、r1、r0的当前第三目标量子态为初始态，可设为|1001>，即包含的初值为-1，并获取4为第二预设辅助比特d.sign、d2、d1、d0，d.sign、d2、d1、d0的当前第四目标量子态也为|1001>；
其中，通常初始化量子比特的量子态为|0>，可以通过对相应的量子比特施加量子逻辑门操作比如X门，将|0>态取反，得到|1>态；
然后，对当前第三目标量子态|1001>和当前第四目标量子态|1001>执行减法运算对应的量子态演化，以将|1001>包含的值1001减去|1001>包含的值1001，得到包含减法运算结果0的第三目标量子态|0000>，第四目标量子态|1001>不变，实现将原第三目标量子态|1001>的值-1加1；
通过对第一目标量子态的符号位子量子态对应的量子比特a.sign施加测量操作，测量当前包含减法运算结果的第一目标量子态|0011>的符号位子量子态为|0>，即符号位的值为0，返回执行对当前第一目标量子态和当前第二目标量子态，执行减法运算对应的量子态演化的步骤：
此时，当前第一目标量子态为|0011>，当前第二目标量子态为|0100>，继续执行减法运算对应的量子态演化，得到：第一目标量子态|1001>、第二目标量子态|0100>；
当前第三目标量子态|0000>，当前第四目标量子态|1001>，继续执行减法运算对应的量子态演化，得到：第三目标量子态|0001>、第四目标量子态|1001>，从而将原第三目标量子态|0000>的值0继续加1；
测量出当前第一目标量子态|1001>的符号位子量子态为|1>，即符号位的值为1，表示被除数7经过两次减法被减为负数，则结束迭代。可得，最终的迭代次数为1，第三目标量子态即起到计数的作用。
S4203，将最终获得的计数结果，作为所述被除数数据与所述除数数据相除的商进行输出。
具体的，可以将最终获得的第三目标量子态进行输出，其中，所述第三目标量子态包含的值为所述被除数数据与所述除数数据相除的商。
继续以上述为例，迭代结束后最终获得的第三目标量子态为|0001>，包含的值为0001，作为被除数7与除数4的商，可以直接输出第三目标量子态|0001>，也可以进一步将第三目标量子态包含的值转换成十进制值1并输出。
在实际应用中，还可以根据用户需求，计算除法运算的余数。具体的，可以将第二目标量子态的符号位子量子态取反，对当前第一目标量子态和符号位取反后的第二目标量子态，执行减法运算对应的量子态演化，以获得被除数数据与除数数据相除的余数。
继续以上述为例，最终获得的第一目标量子态为|1001>、第二目标量子态为|0100>、第三目标量子态为|0001>、第四目标量子态为|1001>。此时，对第二目标量子态的符号位子量子态|0>取反，取反后的第二目标量子态为|1100>。对当前第一目标量子态|1001>和取反后的第二目标量子态|1100>，执行减法运算对应的量子态演化，演化后的第一目标量子态为|0011>、第二目标量子态|1100>，即|0011>包含的二进制值0011(十进制值3)，作为被除数7与除数4相除的余数。
示例性的，图36为一种执行量子除法运算的量子线路示意图。如图36所示，t为存储测量 结果的经典比特位，a.sign、a为编码被除数数据的符号、数值的量子比特位；
b.sign、b为编码除数数据的符号、数值的量子比特位；
r.sign、r、r[0]组成第一预设辅助比特，r.sign为编码商的符号的量子比特位，r、r[0]为编码商的数值的量子比特位，r[0]为最低位；
d.sign、d、d[0]组成第二预设辅助比特，d.sign为编码商的符号的量子比特位，d、d[0]为编码商的数值的量子比特位，d[0]为最低位；
k为减法器模块所需的辅助量子比特，共n+2位，减法器模块为执行减法运算对应的量子态演化的功能模块，Measure为测量操作，Qwhile表示第二层内的量子迭代操作，即在存储测量结果的经典比特位t<1时，执行前述迭代操作，直至t到达1时结束迭代；X表示量子逻辑门X门，量子线路的执行时序为从第一层依次到第五层。
在实际应用中，对于被除数或除数存在负数的情况，还可以获取预设符号位量子比特，对第一目标量子态的符号位子量子态对应的量子比特、第二目标量子态的符号位子量子态对应的量子比特、第一预设辅助比特和所述预设符号位量子比特，执行预设量子逻辑门操作，以最终获得第三目标量子态中符号位子量子态表示的符号值。
示例性的，图37为一种支持符号位运算的量子除法运算的量子线路示意图。在图36所示的量子线路基础上，增设符号位量子比特k[0]、k[1]。其中，相连有竖线的圆圈图标表示量子逻辑门CNOT门，大圆所处的时间线对应的量子比特为受控比特，实心点所处的时间线对应的量子比特为控制比特。
通过对k[0]、k[1]、a.sign、b.sign、r.sign施加一系列如图37所示的CNOT门，最终可在r.sign上获得包含商的符号值的符号位子量子态。
下面详细说明执行减法运算对应的量子态演化的具体实现方式。
具体的，可通过减法器执行减法运算对应的量子态演化，可以包括：
S4301，对于待运算的两个量子态，分别作为包含被减数据的被减数量子态和包含减数数据的减数量子态，获取第三预设辅助比特的量子态，根据所述被减数量子态中的符号位子量子态和所述第三预设辅助比特的量子态，控制所述被减数量子态执行求补码运算对应的量子态演化，得到第一补码量子态；其中，所述第一补码量子态为包含所述被减数数据的补码的量子态；
由前述实施例可知，待运算的两个量子态有以下组：第一目标量子态和第二目标量子态；第三目标量子态和第四目标量子态；第一目标量子态和符号位取反后的第二目标量子态。其中，前者可称被减数量子态，包含的数据在减法运算中为被减数，后者可称减数量子态，包含的数据为减数。
本实施例中，主要用于实现减法器功能，减法器和下述加法器最大的区别就是会产生负数的情况，因此，采用二进制的处理方式，对减数和被减数都加一个符号位，来表示数值的正负，并且使用补码来进行运算。正数补码不变，负数除符号位外按位取反后，再加1。对应到量子线路中，即用符号位控制是否做补码操作，取反用X门，加1可通过加法器实现。在补码情况下运算完成后，再将结果做一次补码运算就得到了目标数值。获取待运算的被减数数据和减数数据，并将所述被减数数据以及所述减数数据分别转换为第一目标量子态和第二目标量子态。其中，目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态。
具体的，根据被减数量子态中的符号位子量子态和第三预设辅助比特的量子态，控制被减数量子态执行求补码运算对应的量子态演化，可以对被减数量子态中的符号位子量子态对应的第一符号位量子比特和第三预设辅助比特执行CNOT门操作，其中，第一符号位量子比特为控制比特，第三预设辅助比特为受控比特；并且，CNOT门可以用等效的其他现有的量子逻辑门或量子逻辑门组合进行替代，也是合理可行的；
根据执行CNOT门操作后的第三预设辅助比特的量子态，控制当前被减数量子态是否执行求补码运算对应的量子态演化；
若是，则对当前被减数量子态的非符号位子量子态取反，并将取反后的被减数量子态与第四 预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第一补码量子态，否则，将所述被减数量子态作为第一补码量子态；其中，执行CNOT门操作后的第三预设辅助比特的量子态可以为|1>态时，才控制执行求补码运算对应的量子态演化，否则不执行；
对当前第一符号位量子比特和第三预设辅助比特执行CNOT门操作，以将当前第三预设辅助比特的量子态进行还原；其中，所述第一符号位量子比特为控制比特，所述第三预设辅助比特为受控比特。
示例性的，被减数量子态假设为|0011>。|0011>的符号位子量子态为最高位的子量子态即|0>态，该位的值为0，对应的第一符号位量子比特设为g.sign，第三预设辅助比特为预设的量子比特q1，初始为|0>态。
对g.sign和q1执行CNOT门操作，g.sign作为控制比特，q1作为受控比特，g.sign位的量子态为|0>态，经过CNOT门操作后，受控比特位q1的量子态|0>不变。
由于执行CNOT门操作后的q1的量子态为|0>态，故不对被减数量子态执行求补码运算对应的量子态演化。原理上在于，被减数为正数时，在减法运算中无需求补码，或者说，其补码即为本身，可直接将|0011>作为第一补码量子态。
最后，可以对当前g.sign和q1再次执行CNOT门，g.sign位的量子态为|0>态，经过CNOT门操作后，受控比特位q1的量子态|0>不变，以还原q1为|0>态，从而释放第三辅助比特存储的信息。可得，第一补码量子态包含的值0011为被减数0011的补码。
如图38所示，q 1为第三预设辅助比特，用于控制是否做补码操作，所述第一目标量子态为g，g.sign为所述第一目标量子态中的符号位子量子态，剩余的g为表示所述数据数值的数值位子量子态，j为第四预设辅助比特，即被设置成值为1的辅助比特，p为加法器所使用的辅助比特(下述第五预设辅助比特)。与图36对应的是，上述k为n+2位，即包括：n位j、1位p、1位q1。
图38所示的量子线路实现了对g做求补码的操作的量子线路，先对g.sign与q 1进行CNOT门操作，使得q 1暂时表示g.sign，并用q 1控制是否进行求补码，求完补码后，再将q 1还原。由此，控制被减数量子态执行求补码运算对应的量子态演化，得到第一补码量子态。
具体地，根据g的符号位子量子态，用第一预设辅助比特q 1来控制是否做取补码的操作。若g为负数，则进行负数的取补码操作。负数的补码为除符号位外按位取反后加1，除符号位外按位取反的操作用逻辑门来实现的话，只需要对数值位全都做X门即可，取反后还需要加1，因此，通过使用j和g相加，j的值被设置为了1，p为加法器的辅助比特，在将数值位取反后的g和j相加后，g上存放的就是取完补码后的数值，再将q 1还原，以便下次使用。
例子：当g为负数时，g.sign为1，因此q 1也为1，就需要做取反等操作，而当g为正数时，g.sign为0，因此q 1也为0，就不需要再求补码了。
S4302，将所述减数量子态中的符号位子量子态执行符号位取反对应的量子态演化，并根据取反后的符号位子量子态和所述第三预设辅助比特的量子态，控制当前减数量子态执行求补码运算对应的量子态演化，得到第二补码量子态；其中，所述第二补码量子态为包含所述减数数据的补码的量子态；
具体的，可以对减数量子态中的符号位子量子态对应的第二符号位量子比特，执行X门操作，得到取反后的符号位子量子态；其中，X门可以用等效的其他现有的量子逻辑门或量子逻辑门组合进行替代，也是合理可行的；
同样的，继续对当前第二符号位量子比特和第三预设辅助比特执行CNOT门操作，其中，所述第二符号位量子比特为控制比特，所述第三预设辅助比特为受控比特；
根据执行CNOT门操作后的第三预设辅助比特的当前量子态，控制当前减数量子态是否执行求补码运算对应的量子态演化；
若是，则对当前减数量子态的非符号位子量子态取反，并将取反后的减数量子态与第四预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第二补码量子态，否则， 将当前减数量子态作为第二补码量子态；
对当前第二符号位量子比特和第三预设辅助比特执行CNOT门操作，以将第三预设辅助比特的当前量子态进行还原；其中，所述第二符号位量子比特为控制比特，所述第三预设辅助比特为受控比特。
示例性的，减数量子态假设为|0100>。|0100>的符号位子量子态为最高位的子量子态即|0>态，该位的值为0，对应的第二符号位量子比特设为h.sign，当前第三辅助比特被还原为|0>态。
首先，可以对h.sign执行X门，将对应的符号位子量子态|0>取反为|1>，减数量子态变为|1100>。
继续对h.sign和q1执行CNOT门操作，h.sign作为控制比特，q1作为受控比特，当前h.sign位的量子态为|1>态，经过CNOT门操作后，受控比特位q1的量子态|0>被取反为|1>态。
执行CNOT门操作后的q1的量子态为|1>态，故对当前减数量子态|1100>执行求补码运算对应的量子态演化。一种执行求补码运算对应的量子态演化的实现如下：
对当前减数量子态|1100>的非符号位子量子态取反，并将取反后的减数量子态|1011>与第四预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第二补码量子态为|1100>。
其中，可通过执行X门对|1100>的非符号位子量子态|100>取反；为了保持维度一致，第四预设辅助比特为预设的4位量子比特j3、j2、j1、j0，第四预设辅助比特的量子态|1>实际上写为|0001>，两者是等同的。
最后，可对当前h.sign和q1再次执行CNOT门，h.sign位的量子态为|1>态，经过CNOT门操作后，受控比特位q1的量子态|1>被取反为|0>，从而再次还原q1为初始|0>态，释放q1的存储空间。可得，第二补码量子态包含的值1100为对h.sign执行X门后的减数1100的补码。
本实施例中，所述第二目标量子态h也是同理，初始对j [0]做X门是为了设置值为1，对第二目标量子态中的符号位子量子态h.sign做X门是为了把减法变成加法。如图39所示，图39为对g、h执行求补码运算对应的量子态演化的量子线路示意图，参考上述同理方法将第二目标量子态h执行求补码运算对应的量子态演化，得到第二补码量子态。
S4303，对所述第一补码量子态和所述第二补码量子态，执行加法运算对应的量子态演化，以将所述第一补码量子态演化为包含所述被减数数据的补码与所述减数数据的补码之和的第五目标量子态；
示例性的，对第一补码量子态为|0011>和第二补码量子态为|1100>，执行加法运算对应的量子态演化，将第一补码量子态|0011>演化为第五目标量子态|1111>。
本实施例中，在求完补码后，将g和h进行加法操作，加完后，再将之前的操作进行还原，g内储存的即为所求。将所述第一补码量子态和所述第二补码量子态代入加法器的量子线路，执行加法运算对应的量子态演化，由此，将所述第一补码量子态演化为包含所述被减数数据的补码与所述减数数据的补码之和的第三目标量子态。
S4304，根据所述第五目标量子态中的符号位子量子态和所述第三预设辅助比特的量子态，控制所述第五目标量子态执行求补码运算对应的量子态演化，得到演化后的第六目标量子态，作为所述被减数数据和所述减数数据的减法运算结果进行输出；其中，所述第六目标量子态为包含所述补码之和的补码的量子态；
示例性的，根据当前第五目标量子态|1111>中的符号位子量子态|1>和当前第三预设辅助比特的量子态|0>，控制第五目标量子态|1111>执行求补码运算对应的量子态演化，得到演化后的第六目标量子态|1001>，其包含的值为1001(十进制-1)，即为被减数量子态|0011>包含的被减数0011(十进制3)与减数量子态|0100>包含的减数0100(十进制4)的减法结果。
需要说明的是，执行求补码运算对应的量子态演化可与前述同理，演化后，第三预设辅助比特的量子态仍被还原为|0>，以便于后续计算使用。
S4305，根据当前减数量子态中的符号位子量子态和当前第三预设辅助比特的量子态，控制 当前减数量子态执行求补码运算对应的量子态演化，并对当前减数量子态中的符号位子量子态执行符号位取反对应的量子态演化，以将当前减数量子态进行还原。
示例性的，当前减数量子态为第二补码量子态|1100>，当前第三预设辅助比特的量子态为|0>。继续按前述同理的方式，控制|1100>执行求补码运算对应的量子态演化，得到演化后的|1100>，然后通过X门操作对其符号位子量子态取反，将其还原成初始的减数量子态|0100>。
本实施例中，进行加法运算后，进一步对所述被减数数据的补码与所述减数数据的补码之和的第三目标量子态执行求补码运算对应的量子态演化。如图40所示，首先，对j [0]做一个X门的目的是将j [0]的值设置为1，方便求补码中的+1运算。而对h的符号位做X门的操作的原因，则是为了将g-h转换为g+(-h)。然后，我们将g和h都做好补码的处理，处理完成后，再将g和h的补码进行相加，得到结果后，再将g和h做一次求补码的操作，将其还原为正常的数值，最后再对初始操作进行还原，也就是对辅助比特进行还原，做2个X门即可。由此组成了如图41所示的整个减法器的量子线路图，是一种功能上的简易示例。
下面详细说明执行加法运算对应的量子态演化的具体实现方式。
具体的，可以通过加法器执行加法运算对应的量子态演化，可以包括：
S4401,根据待运算的两个量子态对应的量子比特位的位数，确定待级联的前级联模块MAJ模块以及待级联的后级联模块UMA模块的目标模块个数，其中，所述MAJ模块的模块个数与所述UMA模块的模块个数相同；
由前述可知，待运算的两个量子态，可以是：第一补码量子态和第二补码量子态；取反后的被减数量子态和第四预设辅助比特的量子态|1>态。
示例性的，如图42所示，线路中第一个量子比特位为第五预设辅助比特位，初始为|0>态，最终会恢复为|0>态，e和f是待相加的数据对应的量子态，各对应一组量子比特位。c表示最终的进位项，对应预设进位辅助比特位，s为是不包含进位的输出位。一般要求e和f对应的量子比特位数相同,s和e、f的位数相同。
示例性的，如图43所示，e [i]和f [i]分别是两个加数对应量子态的第i位，c [i]是上一级进位。
s [i]＝e [i]XOR f [i]XOR c [i]，
c [i+1]＝(e [i]AND f [i])XOR(e [i]AND f [i])XOR(e [i]AND f [i])，
其中，第一个量子比特即为第五预设辅助比特位，对应量子线路中的c 0。第一个MAJ模块包括三个输入量子态以及对应的三个输出量子态，其中，三个输入量子态分别为c 0、e 0、f 0，e 0为第一个待运算量子态的第0位量子态，f 0为第二个待运算量子态的第0位量子态，c 0为第五预设辅助比特的量子态，初始值为0，即无进位。三个输出量子态分别为
Figure PCTCN2021119125-appb-000012
c 1，c 1为e 0和f 0相加后的进位，同理，下一个MAJ模块的三个输入量子态为c 1、e 1、f 1，三个输出量子态分别为
Figure PCTCN2021119125-appb-000013
c 2，以此类推至最后一个MAJ模块。
对于第一个UMA模块，包括三个输入量子态以及对应的三个输出量子态，其中，MAJ模块的三个输出量子态为对应UMA模块的三个输入量子态，三个输出量子态分别为c 0、s 0、e 0，s 0为e 0和f 0相加的不含进位的结果。同理，s1为e 1和f 1相加的不含进位的结果，以此类推，c4是最终的进位项。需要说明的是，在实际应用中，在无计算最终进位的需求下，量子线路中可以不设置c4对应的量子比特位。
并且，可以根据其中待运算的任一量子态包含的子量子态数量确定MAJ模块的模块个数以及UMA模块的个数，一子量子态对应一位量子比特，其中，MAJ模块的模块个数以及UMA模块的个数相等。图中所示仅仅作为示例，编码e和f各所需4位量子比特，MAJ模块和UMA模块的个数均为4。MAJ模块和UMA模块构成了加法器的前、后级联单元。MAJ模块可以用于提取出任何一步的进位项并且传递到下一级，从而将最终进位项计算出来。UMA模块一方面提取了c的信息会传递到上一级UMA，还计算出每一级的s(结果项)，并且恢复了e的信息。
示例性的：当4(对应编码在3个量子比特的量子态表示为100)+2(对应编码在3个量子 比特的量子态表示为010)＝6(对应编码在3个量子比特的量子态表示为110)。此时编码运算结果的量子比特与编码e的量子比特位的个数或用来编码f的量子比特位的个数一致，MAJ模块的模块个数以及UMA模块的个数均为3。
示例性的：当4(对应编码在3个量子比特的量子态表示为100)+7(对应编码在3个量子比特的量子态表示为111)＝11(对应编码在3个量子比特的量子态表示为011)，但是，可以理解的是11对应的二进制数为1011，最左侧的1所在的位为进位项，该进位项可以通过辅助比特位表示。此时编码运算结果的量子比特与编码e的量子比特位的个数或用来编码f的量子比特位的个数要多，MAJ模块的模块个数以及UMA模块的个数均为3。
示例性的，当2(对应编码在2个量子比特的量子态表示为10)+4(对应编码在3个量子比特的量子态表示为100)＝6(对应编码在3个量子比特的量子态表示为110)。此时，编码“6”数值的数值项“3”与编码b的量子比特位的量子态个数一致，MAJ模块的模块个数以及UMA模块的个数均为3。
S4402,根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成所述加法器对应的目标量子线路；
其中，所述MAJ模块以及所述UMA模块均包括三个输入项以及三个输出项，可以根据加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路，其中，所述MAJ级联模块由所述目标模块个数的MAJ模块之间级联确定，所述UMA级联模块由所述目标模块个数的UMA模块之间级联确定。
具体地，所述MAJ模块的三个输入项包括一个进位输入项以及两个待计算子量子态输入项，所述MAJ模块的三个输出项包括一个进位输出项和两个中间结果输出项，所述UMA模块的三个输入项包括对应MAJ模块的一个进位输出项以及两个中间结果输出项，所述UMA模块的三个输出项包括一个结果进位输出项、累加和输出项和一待计算子量子态输入项，
然后，可以根据加法指令，将上一MAJ模块输出的进位输出项以及所述两个待计算子量子态输入项作为下一MAJ模块的三个输入项，以将所述目标模块个数的MAJ模块进行级联；
将一MAJ模块的两个中间结果输出项作为一对应UMA模块的两个输入项，获取所述对应UMA模块的上一UMA模块，并将所述上一UMA模块的结果进位输出项作为所述对应UMA模块的一个输入项，以将所述目标模块个数的MAJ模块以及所述目标模块个数的UAM模块进行级联，生成所述初始量子线路；其中，最后一个MAJ模块的进位输出项作为对应的第一个UMA模块的一个输入项；
将所述初始量子线路中最后一个MAJ模块与对应的第一个UMA模块之间添加CNOT量子逻辑门，其中，将所述MAJ模块的进位输出项对应的量子比特作为控制比特，将预设进位辅助比特位作为受控比特位，以生成所述加法器的目标量子线路。在不需要进位项的情况下，可以不设置该CNOT门以及进位辅助比特位。
本实施例中，如图43所示，根据图示方式，将所述MAJ模块的三个输出比特作为所述UMA模块的三个输入比特，由此，将相同个数的MAJ模块以及UMA模块进行级联，生成所述加法器对应的目标量子线路。其中，线路图中相连的空心圆与实心圆，表示CNOT门操作，空心圆对应量子比特为控制比特位，实心圆对应为受控比特位。
其中，所述MAJ模块为MAJ量子线路，所述UMA模块为UMA量子线路，所述MAJ量子线路和所述UMA量子线路均包括两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门，所述根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成所述加法器对应的目标量子线路的步骤之前，还包括：获取所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门对应的操作量子比特、操作量子比特之间的控制关系以及所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门之间的时序关系；根据所述操作量子比特、所述控制关系以及所述时序关系， 将所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门构建生成所述MAJ量子线路或所述UMA量子线路，作为对应的MAJ模块或UMA模块。
本实施例中，MAJ模块和UMA模块构成了加法器的前、后级联单元。如图44所示，MAJ模块用于提取出每一级加法运算后的进位项并且传递到下一级，从而将最终进位项计算出来。其中，如图45所示，MAJ模块主要可以由三个逻辑门组成，分别是两个CNOT门和一个Toffoli门。CNOT门(图45中的由左向右的第一个、第二个逻辑门)的作用为：将控制位加到目标位上去，形成一个模2加法，即为异或操作，得到(e i+c i)％2、(e i+f i)％2，两个CNOT门的顺序可以交换。Toffoli门(图45中的由左向右的第三个逻辑门)的作用为：将两个控制位都加到目标位上去,得到进位项c [i+1]＝(e [i]AND f [i])XOR(e [i]AND f [i])XOR(e [i]AND f [i])。即通过图45中的由左向右的第一个CNOT门实现
Figure PCTCN2021119125-appb-000014
通过图45中的由左向右的第二个CNOT门实现
Figure PCTCN2021119125-appb-000015
通过图45中的由左向右的第三个TOFFOLI门实现c i+1，由此通过2个CNOT门和1个TOFFOLI门，构成量子加法器的前级级联单元。
例子1：e i为1，f i为1，c i为1。
MAJ模块开始把e i加到c i上，c i上的值变为0，再把e i加到f i上，f i上的值也变为0，最后用f i和c i加到e i上，e i的值变为1，也就是c i+1的进位为1。
例子2：e i为0，f i为1，c i为1。
MAJ模块开始把e i加到c i上，c i上的值变为1，再把e i加到f i上，f i上的值也变为1，最后用f i和c i加到e i上，e i的值变为1，也就是c i+1的进位为1。
如图46所示，UMA模块用于级联加法器的后级，UMA模块的实现方式和MAJ模块类似，如图47所示，首先使用Toffoli门(图47中的由左向右的第一个逻辑门)将c i+1还原为e i，再用e i对(e+c)％2用CNOT门(图47中的由左向右的第二个逻辑门)做一次还原，将(e i+c i)％2还原为c i，最后，再使用c i对(e i+f i)％2做一次CNOT门(图47中的由左向右的第三个逻辑门)，得到当前位的最终结果s [i]＝e [i]XOR f [i]XOR c [i]。
例子1：(e i+c i)％2为0，(e i+f i)％2为0，c i+1为1。
开始把(e i+c i)％2和(e i+f i)％2加到c i+1上，c i+1的值变为1，表示的意义变为e i，再用e i加到(e i+c i)％2上，(e i+c i)％2的值变为1，表示的意义变为c i,再用c i加到(e i+f i)％2上，(e i+f i)％2的值变为1，意义变为s i。
例子2：(e i+c i)％2为1，(e i+f i)％2为1，c i+1为1。
开始把(e i+c i)％2和(e i+f i)％2加到c i+1上，c i+1的值变为0，意义变为e i，再用e i加到(e i+c i)％2上，(e i+c i)％2的值变为1，意义变为c i,再用c i加到(e i+f i)％2上，(e i+f i)％2的值变为0，意义变为s i。
如图43中由上向下的最后一个CNOT门，即整个加法器MAJ模块和UMA模块中间的CNOT门，用于保存c i+1的结果。
S4403，通过所述目标量子线路对所述待运算的两个量子态的各子量子态进行加法运算，生成目标量子态结果并输出。
本实施例中，通过将待运算的两个量子态，如|111>和|111>，输入加法器(即所述目标量子线路)中，得到对应的二进制表示目标量子态计算结果(包括进位项以及各子量子态直接相加得到的结果项)。然后将二进制表示的目标量子态结果|1110>直接输出，或进一步转化为十进制结果14并输出，完成两目标数据的加法运算。
可见，本发明提供的量子除法运算方法，用于实现量子线路中的基本算术运算操作，获取待运算的被除数数据和除数数据，并将所述被除数数据转换为第一目标量子态，将所述除数数据转换为第二目标量子态；对所述第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为负数；将最终获得的计数结果，作为所述被除数数据与所述除数数据相除的商，转换为十进制表示并输出，从而实现可以用于量子线路中的基本算术运算操作，填补了相关技术的空白。
参见图48，图48是本发明一实施例提供的量子除法运算装置的结构示意图，可以包括：
转换模块41501，用于获取待运算的被除数数据和除数数据，并将所述被除数数据转换为第一目标量子态，将所述除数数据转换为第二目标量子态；其中，所述目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态；
运算模块41502，用于对所述第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为负数；其中，每次执行减法运算的被减数为上次执行减法运算的减法结果、减数为所述除数数据；
输出模块41503，用于将最终获得的计数结果，作为所述被除数数据与所述除数数据相除的商进行输出。
具体的，所述运算模块，具体用于：
对当前第一目标量子态和所述第二目标量子态，执行减法运算对应的量子态演化，以获得包含减法运算结果的第一目标量子态；
对当前第一预设辅助比特的第三目标量子态和当前第二预设辅助比特的第四目标量子态，执行减法运算对应的量子态演化，以将当前第三目标量子态包含的值加1；其中，所述第三目标量子态包含的初值、所述第四目标量子态包含的值均为-1；
测量当前包含减法运算结果的第一目标量子态的符号位子量子态，判断当前包含减法运算结果的第一目标量子态的符号位的值是否为0；
在当前包含减法运算结果的第一目标量子态的符号位的值为0的情况下，返回执行所述对当前第一目标量子态和当前第二目标量子态，执行减法运算对应的量子态演化的步骤，直至判断出当前包含减法运算结果的第一目标量子态的符号位的值为1。
具体的，所述输出模块，具体用于：
将最终获得的第三目标量子态进行输出，其中，所述第三目标量子态包含的值为所述被除数数据与所述除数数据相除的商。
具体的，所述装置还包括：
第一执行模块，用于将所述第二目标量子态的符号位子量子态取反，对当前第一目标量子态和符号位取反后的第二目标量子态，执行减法运算对应的量子态演化，以获得所述被除数数据与所述除数数据相除的余数。
具体的，所述装置还包括：
第二执行模块，用于获取预设符号位量子比特，对所述第一目标量子态的符号位子量子态对应的量子比特、所述第二目标量子态的符号位子量子态对应的量子比特、所述第一预设辅助比特和所述预设符号位量子比特，执行预设量子逻辑门操作，以最终获得所述第三目标量子态中符号位子量子态表示的符号值。
具体的，所述运算模块，包括：
第一补码运算单元，用于对于待运算的两个量子态，分别作为包含被减数据的被减数量子态和包含减数数据的减数量子态，获取第三预设辅助比特的量子态，根据所述被减数量子态中的符号位子量子态和所述第三预设辅助比特的量子态，控制所述被减数量子态执行求补码运算对应的量子态演化，得到第一补码量子态；其中，所述第一补码量子态为包含所述被减数数据的补码的量子态；
第二补码运算单元，用于将所述减数量子态中的符号位子量子态执行符号位取反对应的量子态演化，并根据取反后的符号位子量子态和所述第三预设辅助比特的量子态，控制当前减数量子态执行求补码运算对应的量子态演化，得到第二补码量子态；其中，所述第二补码量子态为包含所述减数数据的补码的量子态；
加法运算单元，用于对所述第一补码量子态和所述第二补码量子态，执行加法运算对应的量子态演化，以将所述第一补码量子态演化为包含所述被减数数据的补码与所述减数数据的补码之和的第五目标量子态；
第三补码运算单元，用于根据所述第五目标量子态中的符号位子量子态和所述第三预设辅助比特的量子态，控制所述第五目标量子态执行求补码运算对应的量子态演化，得到演化后的第六目标量子态，作为所述被减数数据和所述减数数据的减法运算结果进行输出；其中，所述第六目标量子态为包含所述补码之和的补码的量子态；
第四补码运算单元，用于根据当前减数量子态中的符号位子量子态和当前第三预设辅助比特的量子态，控制当前减数量子态执行求补码运算对应的量子态演化，并对当前减数量子态中的符号位子量子态执行符号位取反对应的量子态演化，以将当前减数量子态进行还原。
具体的，所述第一补码运算单元，具体用于：
对所述被减数量子态中的符号位子量子态对应的第一符号位量子比特和所述第三预设辅助比特执行CNOT门操作，其中，所述第一符号位量子比特为控制比特，所述第三预设辅助比特为受控比特；
根据执行CNOT门操作后的所述第三预设辅助比特的量子态，控制当前被减数量子态是否执行求补码运算对应的量子态演化；
若是，则对当前被减数量子态的非符号位子量子态取反，并将取反后的被减数量子态与第四预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第一补码量子态，否则，将所述被减数量子态作为第一补码量子态；
对当前第一符号位量子比特和第三预设辅助比特执行CNOT门操作，以将当前第三预设辅助比特的量子态进行还原；其中，所述第一符号位量子比特为控制比特，所述第三预设辅助比特为受控比特。
具体的，所述第二补码运算单元，具体用于：
对所述减数量子态中的符号位子量子态对应的第二符号位量子比特，执行X门操作，得到取反后的符号位子量子态；
对当前第二符号位量子比特和第三预设辅助比特执行CNOT门操作，其中，所述第二符号位量子比特为控制比特，所述第三预设辅助比特为受控比特；
根据执行CNOT门操作后的第三预设辅助比特的当前量子态，控制当前减数量子态是否执行求补码运算对应的量子态演化；
若是，则对当前减数量子态的非符号位子量子态取反，并将取反后的减数量子态与第四预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第二补码量子态，否则，将当前减数量子态作为第二补码量子态；
对当前第二符号位量子比特和第三预设辅助比特执行CNOT门操作，以将第三预设辅助比特的当前量子态进行还原；其中，所述第二符号位量子比特为控制比特，所述第三预设辅助比特为受控比特。
具体的，所述加法运算单元，包括：
确定子单元，用于根据待运算的两个量子态对应的量子比特位的位数，确定待级联的前级联模块MAJ模块以及待级联的后级联模块UMA模块的目标模块个数，其中，所述MAJ模块的模块个数与所述UMA模块的模块个数相同；
级联子单元，用于根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成加法器对应的目标量子线路；
运算子单元，用于通过所述目标量子线路对所述待运算的两个量子态的各子量子态进行加法运算，生成目标量子态结果并输出。
具体的，所述MAJ模块为MAJ量子线路，所述UMA模块为UMA量子线路，所述MAJ量子线路和所述UMA量子线路均包括两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门；所述加法运算单元，还包括：
获取子单元，用于获取所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门对应的操作 量子比特、操作量子比特之间的控制关系以及所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门之间的时序关系；
构建子单元，用于根据所述操作量子比特、所述控制关系以及所述时序关系，将所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门构建生成所述MAJ量子线路或所述UMA量子线路，作为对应的MAJ模块或UMA模块。
具体的，所述MAJ模块以及所述UMA模块均包括三个输入项以及三个输出项；所述级联子单元，具体用于：
根据加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路，其中，所述MAJ级联模块由所述目标模块个数的MAJ模块之间级联确定，所述UMA级联模块由所述目标模块个数的UMA模块之间级联确定。
具体的，所述MAJ模块的三个输入项包括一个进位输入项以及两个待计算子量子态输入项，所述MAJ模块的三个输出项包括一个进位输出项和两个中间结果输出项，所述UMA模块的三个输入项包括对应MAJ模块的一个进位输出项以及两个中间结果输出项，所述UMA模块的三个输出项包括一个结果进位输出项、累加和输出项和一待计算子量子态输入项；所述级联子单元，具体用于：
根据加法指令，将上一MAJ模块输出的进位输出项以及所述两个待计算子量子态输入项作为下一MAJ模块的三个输入项，以将所述目标模块个数的MAJ模块进行级联；
将一MAJ模块的两个中间结果输出项作为一对应UMA模块的两个输入项，获取所述对应UMA模块的上一UMA模块，并将所述上一UMA模块的结果进位输出项作为所述对应UMA模块的一个输入项，以将所述目标模块个数的MAJ模块以及所述目标模块个数的UAM模块进行级联，生成所述初始量子线路；其中，最后一个MAJ模块的进位输出项作为对应的第一个UMA模块的一个输入项；
将所述初始量子线路中最后一个MAJ模块与对应的第一个UMA模块之间添加CNOT量子逻辑门，其中，将所述MAJ模块的进位输出项对应的量子比特作为控制比特，将预设进位辅助比特位作为受控比特位，以生成所述加法器的目标量子线路。
可见，通过获取待运算的被除数数据和除数数据，并将所述被除数数据转换为第一目标量子态，将所述除数数据转换为第二目标量子态；对所述第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为负数；将最终获得的计数结果，作为所述被除数数据与所述除数数据相除的商，转换为十进制表示并输出，从而实现可以用于量子线路中的基本算术运算操作，填补了相关技术的空白。
本发明的再一实施例提供了一种电子装置，包括存储器和处理器，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行如下所述的方法：
S1，获取待运算的被除数数据和除数数据，并将所述被除数数据转换为第一目标量子态，将所述除数数据转换为第二目标量子态；其中，所述目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态；
S2，对所述第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为负数；其中，每次执行减法运算的被减数为上次执行减法运算的减法结果、减数为所述除数数据；
S3，将最终获得的计数结果，作为所述被除数数据与所述除数数据相除的商进行输出。
本发明的再一实施例提供了一种存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行如下所述的方法：
S1，获取待运算的被除数数据和除数数据，并将所述被除数数据转换为第一目标量子态，将所述除数数据转换为第二目标量子态；其中，所述目标量子态包括：表示所述数据符号的符号位 子量子态和表示所述数据数值的数值位子量子态；
S2，对所述第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为负数；其中，每次执行减法运算的被减数为上次执行减法运算的减法结果、减数为所述除数数据；
S3，将最终获得的计数结果，作为所述被除数数据与所述除数数据相除的商进行输出。
上述实施例可以总结如下。
C41.一种量子除法运算方法，其特征在于，所述方法包括：获取待运算的被除数数据和除数数据，并将所述被除数数据转换为第一目标量子态，将所述除数数据转换为第二目标量子态；其中，目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态；
对所述第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为负数；其中，每次执行减法运算的被减数为上次执行减法运算的减法结果、减数为所述除数数据；将最终获得的计数结果，作为所述被除数数据与所述除数数据相除的商进行输出。
C42.根据C41所述的方法，其特征在于，所述对所述第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为负数，包括：对当前第一目标量子态和所述第二目标量子态，执行减法运算对应的量子态演化，以获得包含减法运算结果的第一目标量子态；对当前第一预设辅助比特的第三目标量子态和当前第二预设辅助比特的第四目标量子态，执行减法运算对应的量子态演化，以将当前第三目标量子态包含的值加1；其中，所述第三目标量子态包含的初值、所述第四目标量子态包含的值均为-1；测量当前包含减法运算结果的第一目标量子态的符号位子量子态，判断当前包含减法运算结果的第一目标量子态的符号位的值是否为0；在当前包含减法运算结果的第一目标量子态的符号位的值为0的情况下，返回执行所述对当前第一目标量子态和当前第二目标量子态，执行减法运算对应的量子态演化的步骤，直至判断出当前包含减法运算结果的第一目标量子态的符号位的值为1。
C43.根据C41或C42所述的方法，其特征在于，所述将最终获得的计数结果，作为所述被除数数据与所述除数数据相除的商进行输出，包括：将最终获得的第三目标量子态进行输出，其中，所述第三目标量子态包含的值为所述被除数数据与所述除数数据相除的商。
C44.根据C41-C43中的任何一个所述的方法，其特征在于，所述方法还包括：
将所述第二目标量子态的符号位子量子态取反，对当前第一目标量子态和符号位取反后的第二目标量子态，执行减法运算对应的量子态演化，以获得所述被除数数据与所述除数数据相除的余数。
C45.根据C41-C44中的任何一个所述的方法，其特征在于，所述方法还包括：获取预设符号位量子比特，对所述第一目标量子态的符号位子量子态对应的量子比特、所述第二目标量子态的符号位子量子态对应的量子比特、所述第一预设辅助比特和所述预设符号位量子比特，执行预设量子逻辑门操作，以最终获得所述第三目标量子态中符号位子量子态表示的符号值。
C46.根据C41-C45中的任何一个所述的方法，其特征在于，所述执行减法运算对应的量子态演化，包括：对于待运算的两个量子态，分别作为包含被减数据的被减数量子态和包含减数数据的减数量子态，获取第三预设辅助比特的量子态，根据所述被减数量子态中的符号位子量子态和所述第三预设辅助比特的量子态，控制所述被减数量子态执行求补码运算对应的量子态演化，得到第一补码量子态；其中，所述第一补码量子态为包含所述被减数数据的补码的量子态；将所述减数量子态中的符号位子量子态执行符号位取反对应的量子态演化，并根据取反后的符号位子量子态和所述第三预设辅助比特的量子态，控制当前减数量子态执行求补码运算对应的量子态演化，得到第二补码量子态；其中，所述第二补码量子态为包含所述减数数据的补码的量子态；对所述第一补码量子态和所述第二补码量子态，执行加法运算对应的量子态演化，以将所述第一补码量子态演化为包含所述被减数数据的补码与所述减数数据的补码之和的第五目标量子态；根据所述第五目标量子态 中的符号位子量子态和所述第三预设辅助比特的量子态，控制所述第五目标量子态执行求补码运算对应的量子态演化，得到演化后的第六目标量子态，作为所述被减数数据和所述减数数据的减法运算结果进行输出；其中，所述第六目标量子态为包含所述补码之和的补码的量子态；根据当前减数量子态中的符号位子量子态和当前第三预设辅助比特的量子态，控制当前减数量子态执行求补码运算对应的量子态演化，并对当前减数量子态中的符号位子量子态执行符号位取反对应的量子态演化，以将当前减数量子态进行还原。
C47.根据C41-C46中的任何一个所述的方法，其特征在于，所述根据所述被减数量子态中的符号位子量子态和所述第三预设辅助比特的量子态，控制所述被减数量子态执行求补码运算对应的量子态演化，包括：对所述被减数量子态中的符号位子量子态对应的第一符号位量子比特和所述第三预设辅助比特执行CNOT门操作，其中，所述第一符号位量子比特为控制比特，所述第三预设辅助比特为受控比特；根据执行CNOT门操作后的所述第三预设辅助比特的量子态，控制当前被减数量子态是否执行求补码运算对应的量子态演化；若是，则对当前被减数量子态的非符号位子量子态取反，并将取反后的被减数量子态与第四预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第一补码量子态，否则，将所述被减数量子态作为第一补码量子态；对当前第一符号位量子比特和第三预设辅助比特执行CNOT门操作，以将当前第三预设辅助比特的量子态进行还原；其中，所述第一符号位量子比特为控制比特，所述第三预设辅助比特为受控比特。
C48.根据C41-C47中的任何一个所述的方法，其特征在于，所述将所述减数量子态中的符号位子量子态执行符号位取反对应的量子态演化，并根据取反后的符号位子量子态和所述第三预设辅助比特的量子态，控制当前减数量子态执行求补码运算对应的量子态演化，包括：对所述减数量子态中的符号位子量子态对应的第二符号位量子比特，执行X门操作，得到取反后的符号位子量子态；对当前第二符号位量子比特和第三预设辅助比特执行CNOT门操作，其中，所述第二符号位量子比特为控制比特，所述第三预设辅助比特为受控比特；根据执行CNOT门操作后的第三预设辅助比特的当前量子态，控制当前减数量子态是否执行求补码运算对应的量子态演化；若是，则对当前减数量子态的非符号位子量子态取反，并将取反后的减数量子态与第四预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第二补码量子态，否则，将当前减数量子态作为第二补码量子态；对当前第二符号位量子比特和第三预设辅助比特执行CNOT门操作，以将第三预设辅助比特的当前量子态进行还原；其中，所述第二符号位量子比特为控制比特，所述第三预设辅助比特为受控比特。
C49.根据C41-C48中的任何一个所述的方法，其特征在于，所述执行加法运算对应的量子态演化，包括：根据待运算的两个量子态对应的量子比特位的位数，确定待级联的前级联模块MAJ模块以及待级联的后级联模块UMA模块的目标模块个数，其中，所述MAJ模块的模块个数与所述UMA模块的模块个数相同；根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成加法器对应的目标量子线路；通过所述目标量子线路对所述待运算的两个量子态的各子量子态进行加法运算，生成目标量子态结果并输出。
C410.根据C41-C49中的任何一个所述的方法，其特征在于，所述MAJ模块为MAJ量子线路，所述UMA模块为UMA量子线路，所述MAJ量子线路和所述UMA量子线路均包括两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门，所述根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成加法器对应的目标量子线路的步骤之前，还包括：获取所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门对应的操作量子比特、操作量子比特之间的控制关系以及所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门之间的时序关系；根据所述操作量子比特、所述控制关系以及所述时序关系，将所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门构建生成所述MAJ量子线路或所述UMA量子线路，作为对应的MAJ模块或UMA模块。
C411.根据C41-C410中的任何一个所述的方法，其特征在于，所述MAJ模块以及所述UMA模块均包括三个输入项以及三个输出项，所述根据加法指令，将所述目标模块个数的MAJ模块以 及UMA模块进行级联，生成所述加法器对应的目标量子线路的步骤具体包括：根据加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路，其中，所述MAJ级联模块由所述目标模块个数的MAJ模块之间级联确定，所述UMA级联模块由所述目标模块个数的UMA模块之间级联确定。
C412.根据C41-C411中的任何一个所述的方法，其特征在于，所述MAJ模块的三个输入项包括一个进位输入项以及两个待计算子量子态输入项，所述MAJ模块的三个输出项包括一个进位输出项和两个中间结果输出项，所述UMA模块的三个输入项包括对应MAJ模块的一个进位输出项以及两个中间结果输出项，所述UMA模块的三个输出项包括一个结果进位输出项、累加和输出项和一待计算子量子态输入项，所述根据加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路的步骤具体包括：根据加法指令，将上一MAJ模块输出的进位输出项以及所述两个待计算子量子态输入项作为下一MAJ模块的三个输入项，以将所述目标模块个数的MAJ模块进行级联；将一MAJ模块的两个中间结果输出项作为一对应UMA模块的两个输入项，获取所述对应UMA模块的上一UMA模块，并将所述上一UMA模块的结果进位输出项作为所述对应UMA模块的一个输入项，以将所述目标模块个数的MAJ模块以及所述目标模块个数的UAM模块进行级联，生成所述初始量子线路；其中，最后一个MAJ模块的进位输出项作为对应的第一个UMA模块的一个输入项；将所述初始量子线路中最后一个MAJ模块与对应的第一个UMA模块之间添加CNOT量子逻辑门，其中，将所述MAJ模块的进位输出项对应的量子比特作为控制比特，将预设进位辅助比特位作为受控比特位，以生成所述加法器的目标量子线路。
C413.一种量子除法运算装置，其特征在于，所述装置包括：转换模块，用于获取待运算的被除数数据和除数数据，并将所述被除数数据转换为第一目标量子态，将所述除数数据转换为第二目标量子态；其中，所述目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态；运算模块，用于对所述第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为负数；其中，每次执行减法运算的被减数为上次执行减法运算的减法结果、减数为所述除数数据；输出模块，用于将最终获得的计数结果，作为所述被除数数据与所述除数数据相除的商进行输出。
C414.一种电子装置，包括存储器和处理器，其特征在于，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行C41-C412中的任何一个所述的方法。
C415.一种存储介质，其特征在于，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行C41-C412中的任何一个所述的方法。
与现有技术相比，本发明提供的量子除法运算方法，通过获取待运算的被除数数据和除数数据，并将所述被除数数据转换为第一目标量子态，将所述除数数据转换为第二目标量子态；对所述第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为负数；将最终获得的计数结果，作为所述被除数数据与所述除数数据相除的商进行输出，从而实现可以用于量子线路中的基本算术运算操作，填补了相关技术的空白。
参见图49，图49为本发明实施例提供的一种带精度的量子除法运算方法的流程示意图，可以包括如下步骤：
S5201，获取待运算的被除数数据和除数数据，并将所述被除数数据转换为第一目标量子态，将所述除数数据转换为第二目标量子态；其中，所述目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态；
具体的，可以利用现有的振幅编码方式，将待运算的十进制数据转换为二进制的量子态表示。例如，被除数数据为7，带符号的二进制表示0111，最高位为0表示正数，1表示负数；除数数据 为4，带符号的二进制表示011。需要说明的是，本实施例中，第一目标量子态和第二目标量子态的最高位均为0，即参与运算的被除数和除数均为正数。
可以获取5位量子比特a.sign、a3、a2、a1、a0，将7编码到a.sign、a3、a2、a1、a0的第一目标量子态|00111>上，量子态的振幅设为1。其中，|00111>＝|0>|0>|1>|1>|1>，|0>、|0>、|1>、|1>、|1>称为|00111>的子量子态，一子量子态对应一量子比特位，且从右至左表示由高位至低位，最高位对应a.sign、第四位对应a3、第三位对应a2、第二位对应a1、最低位对应a0，最高位的|0>表示符号位子量子态，其余表示数值位子量子态。为了统一运算维度，另外获取5位量子比特b.sign、b3、b2、b1、b0，将4编码到b.sign、b3、b2、b1、b0的第二目标量子态|00100>，其振幅同为1。
S5202，对所述第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为负数，将最终获得的计数结果，作为所述被除数数据与所述除数数据相除的商的整数位进行输出；其中，每次执行减法运算的被减数为上次执行减法运算的减法结果、减数为所述除数数据；
具体的，该处减法运算的执行次数是指对第一目标量子态和第二目标量子态执行减法运算对应的量子态演化的次数，也就是迭代次数。
在具体实现中，可以对当前第一目标量子态和第二目标量子态，执行减法运算对应的量子态演化，以获得包含减法运算结果的第一目标量子态；
对当前第一预设辅助比特的第三目标量子态和当前第二预设辅助比特的第四目标量子态，执行减法运算对应的量子态演化，以将当前第三目标量子态包含的值加1；其中，第三目标量子态包含的初值、第四目标量子态包含的值均为-1；
测量当前包含减法运算结果的第一目标量子态的符号位子量子态，判断当前包含减法运算结果的第一目标量子态的符号位的值是否为0；
在当前包含减法运算结果的第一目标量子态的符号位的值为0的情况下，返回执行对当前第一目标量子态和当前第二目标量子态，执行减法运算对应的量子态演化的步骤，直至判断出当前包含减法运算结果的第一目标量子态的符号位的值为1。
示例性的，当前第一目标量子态和第二目标量子态为|00111>和|00100>。对|00111>和|00100>执行减法运算对应的量子态演化，以将|00111>包含的值00111减去|00100>包含的值00100，得到包含减法运算结果00011的第一目标量子态|00011>，第二目标量子态|00100>不变；
获取4位第一预设辅助比特r.sign、r2、r1、r0，r.sign、r2、r1、r0的当前第三目标量子态为初始态，可设为|1001>，即包含的初值为-1，并获取4为第二预设辅助比特d.sign、d2、d1、d0，d.sign、d2、d1、d0的当前第四目标量子态也为|1001>；
其中，通常初始化量子比特的量子态为|0>，可以通过对相应的量子比特施加量子逻辑门操作比如X门，将|0>态取反，得到|1>态；
然后，对当前第三目标量子态|1001>和当前第四目标量子态|1001>执行减法运算对应的量子态演化，以将|1001>包含的值1001减去|1001>包含的值1001，得到包含减法运算结果0的第三目标量子态|0000>，第四目标量子态|1001>不变，实现将原第三目标量子态|1001>的值-1加1；
通过对第一目标量子态的符号位子量子态对应的量子比特a3施加测量操作，测量当前包含减法运算结果的第一目标量子态|00011>的符号位子量子态为|0>，即符号位的值为0，返回执行对当前第一目标量子态和当前第二目标量子态，执行减法运算对应的量子态演化的步骤：
此时，当前第一目标量子态为|00011>，当前第二目标量子态为|00100>，继续执行减法运算对应的量子态演化，得到：第一目标量子态|10001>、第二目标量子态|00100>；
当前第三目标量子态|0000>，当前第四目标量子态|1001>，继续执行减法运算对应的量子态演化，得到：第三目标量子态|0001>、第四目标量子态|1001>，从而将原第三目标量子态|0000>的值0继续加1；
测量出当前第一目标量子态|10001>的符号位子量子态为|1>，即符号位的值为1，表示被除数7经过两次减法被减为负数，则结束迭代。可得，最终的迭代次数为1，第三目标量子态即起到计数的作用。
具体的，可以将最终获得的第三目标量子态进行输出，其中，所述第三目标量子态包含的值为所述被除数数据与所述除数数据相除的商。
继续以上述为例，迭代结束后最终获得的第三目标量子态为|0001>，包含的值为0001，作为被除数7与除数4的商的整数位，可以直接输出第三目标量子态|0001>，也可以进一步将第三目标量子态包含的值转换成十进制值1并输出。
S5203，对当前第一目标量子态和当前第二目标量子态，迭代执行所述商的小数位运算对应的量子态演化；其中，该迭代的预设迭代次数与待计算的小数位精度的位数一致，每次迭代后在对应的预设精度位量子比特上得到包含对应精度位的值的量子态；
具体的，对当前第一目标量子态和当前第二目标量子态，迭代执行所述商的小数位运算对应的量子态演化，可以包括：
S52031，将当前第二目标量子态的符号位子量子态取反，对当前第一目标量子态和符号位取反后的第二目标量子态，执行减法运算对应的量子态演化，以将当前第一目标量子态演化为包含所述被除数数据与所述除数数据相除的余数二进制值的量子态；
S52032，将当前第一目标量子态的各位子量子态均左移一位，将当前第二目标量子态的符号位子量子态再取反，对左移一位后的第一目标量子态和再取反后的第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述左移一位后的第一目标量子态减为负数，在预设中间位量子比特上得到包含计数结果的二进制值的小数位量子态；
S52033，将所述小数位量子态的最后一位子量子态与对应的预设精度位量子比特的初始量子态|0>态进行交换，并输出交换后的预设精度位量子比特上的量子态；
S52034，返回执行所述将当前第二目标量子态的符号位子量子态取反，对当前第一目标量子态和符号位取反后的第二目标量子态，执行减法运算对应的量子态演化的步骤，直至达到所述迭代执行所述商的小数位运算对应的量子态演化所需的预设迭代次数，其中，所述预设迭代次数与待计算的小数位精度的位数一致。
示例性的，当前第一目标量子态|10001>、第二目标量子态|00100>、第三目标量子态|0001>、第四目标量子态|1001>，商的小数位保留3位精度。
第一次迭代：步骤1：对第二目标量子态的符号位子量子态|0>取反，取反后的第二目标量子态为|10100>，对当前第一目标量子态|10001>和取反后的第二目标量子态|10100>，执行减法运算对应的量子态演化，演化后的第一目标量子态成为|00011>、第二目标量子态为|10100>；实际上，|00011>包含的二进制值00011(十进制值3)，即为被除数7与除数4相除的余数。
步骤2：将第一目标量子态|00011>整体左移一位为|00110>，对第二目标量子态|10100>的符号位再取反以还原为|00100>，然后对|00110>和|00100>迭代执行减法运算对应的量子态演化，并对此处的迭代次数进行计数，直至将|00110>减为负数，将计数结果保存到预设中间位量子比特cc.sign、cc2、cc1、cc0的小数位量子态上，最后得到：第一目标量子态|10010>、第二目标量子态|00100>、小数位量子态|0001>；
需要说明的是，其原理与上述对第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为负数的实现原理相同，实际上即是对|00110>和|00100>做除法运算。
步骤3：将小数位量子态|0001>的最后一位子量子态|1>，与对应的预设精度位量子比特f2的初始量子态|0>，利用SWAP门进行交换，输出交换后的f2的量子态|1>，小数位量子态变为|0000>；其中，预设精度位量子比特可设3位为f2、f1、f0，第一次迭代中，小数位量子态的最后一位子量子态输出到f2上，第二次迭代输出到f1上，第三次迭代输出到f0上。
第二次迭代：当前第一目标量子态|10010>、当前第二目标量子态|00100>、当前小数位量子态|0000>，返回执行步骤1-步骤3，将小数位量子态的最后一位子量子态与f1的初始量子态|0>交换，输出交换后的f1的量子态，最终得到：当前第一目标量子态|10100>、当前第二目标量子态|00100>、f2的量子态|1>、小数位量子态|0000>。
第三次迭代：当前第一目标量子态|10100>、当前第二目标量子态|00100>、当前小数位量子态|0000>，返回执行步骤1-步骤3，将小数位量子态的最后一位子量子态与f0的初始量子态|0>交换，输出交换后的f0的量子态，最终得到：当前第一目标量子态|10100>、当前第二目标量子态|00100>、f0的量子态|0>、小数位量子态|0000>。
示例性的，图50为一种执行带精度的量子除法运算的量子线路示意图。如图50所示，t为存储测量结果的经典比特位，a.sign、a为编码被除数数据的符号、数值的量子比特位，对应第一目标量子态；
b.sign、b为编码除数数据的符号、数值的量子比特位，对应第二目标量子态；
r.sign、r、r[0]组成第一预设辅助比特，r.sign为编码商的符号的量子比特位，r、r[0]为编码商的数值的量子比特位，r[0]为最低位；
d.sign、d、d[0]组成第二预设辅助比特，d.sign编码符号位，d编码数值位，其中，d[0]为最低位；第二预设辅助比特对应初态为0态的第四目标量子态，通过X门将d.sign对应的符号位子量子态和d[0]对应的数值位子量子态取反，以得到包含值为-1的第四目标量子态，用于在减法器中的加1操作，起到计数的作用；
kk为线路上半部分的减法器模块所需的辅助量子比特，共n+3位，k为线路下半部分的减法器模块所需的辅助量子比特，共n+2位，该n+2位共用了kk中的前(n+2)位辅助量子比特，图中区别显示，实际上kk包含k；f[cnt-1]、f[i]、f[0]表示预设精度位量子比特；
减法器模块为执行减法运算对应的量子态演化的功能模块，X表示量子逻辑门X门，Qwhile表示量子迭代操作，量子线路的执行时序为从第一层依次到第五层：
第一层：Qwhile内的测量操作用于测量a.sign的值并存储到经典比特位t上，当t<1时，执行Qwhile内的迭代操作，并执行sum++，将sum值存储到对应经典比特上(sum初值为0)，直至t到达1时结束迭代；
第二层：第二层的迭代次数为cnt次，cnt为所需的商的小数精度位，在第二层每次迭代中，该层Qwhile也要进行相应的迭代，t＝0模块表示将t置为0；cc.sign、cc、cc[0]表示预设中间位量子比特，其中，cc.sign表示符号位；该层Qwhile内的测量操作用于测量a.sign的值并存储到经典比特位t上，当t<1时，执行Qwhile内的迭代操作，并执行s[i]++，将s[i]值存储到对应经典比特上(s[i]初值为0，i＝0,1,2……表示第二层的第i次迭代)，直至t到达1时结束Qwhile内的迭代；第二层右下方一实竖线与两虚竖线图标表示量子逻辑门SWAP门；
第三层：第三层的迭代次数为cnt次，当s[cnt-i-1]>0时，执行该层Qwhile内的减法器迭代操作，并执行s[cnt-i-1]--，直至s[cnt-i-1]小于等于0时结束Qwhile内的迭代；逆左移一位操作为左移一位的逆操作；
第四层：当sum>0时，执行该层Qwhile内的减法器迭代操作，并执行sum--，直至sum小于等于0时结束Qwhile内的迭代；第四层左下方的两个X门用于对d.sign、d[0]的量子态进行再次取反，实现还原为初始态。
进一步的，经过第三层和第四层操作，可以对s[i]、sum还原为初值0，对a.sign、a、b.sign、b、d.sign、d[0]还原为初始态,r上得到商的整数位，f上得到商的预设精度小数位，辅助量子比特的量子态会被还原，从而可被重复利用。
S5204，将最终获得的预设精度位量子比特上的量子态进行输出，其中，该量子态包含所述商的小数位的二进制值。
继续以上述为例，经过三次迭代，最终得到的3位预设精度位量子比特f2、f1、f0的量子态 为|1>|1>|0>＝|110>，即商的小数位二进制值为110(十进制0.75)。前述计算得到商的整数位二进制值为0001(十进制1)，可得最终被除数7与除数4的商为1.75。
在实际应用中，对于被除数和/或除数存在负数的情况，还可以获取预设符号位量子比特，对第一目标量子态的符号位子量子态对应的量子比特、第二目标量子态的符号位子量子态对应的量子比特、第一预设辅助比特和所述预设符号位量子比特，执行预设量子逻辑门操作，以最终获得第三目标量子态中符号位子量子态表示的符号值。
示例性的，图51为一种支持符号位运算的带精度的量子除法运算的量子线路示意图。其中，带精度的正数除法器即为图50所示的量子线路，增设符号位量子比特u[0]、u[1]；相连有竖线的圆圈图标表示量子逻辑门CNOT门，大圆所处的时间线对应的量子比特为受控比特，实心点所处的时间线对应的量子比特为控制比特；经典比特共cnt+2位，包括图50中：1位sum、cnt位s[i]、1位t；v为辅助量子比特共3n+3位，包括图50中：n+3位kk、n位d.sign和d、n位cc.sign和cc。
通过对u[0]、u[1]、a.sign、b.sign、r.sign施加一系列如图51所示的CNOT门，最终可在r.sign上获得包含商的符号值的符号位子量子态。
下面详细说明执行减法运算对应的量子态演化的具体实现方式。
具体的，可通过减法器执行减法运算对应的量子态演化，可以包括：
S5301，对于待运算的两个量子态，分别作为包含被减数据的被减数量子态和包含减数数据的减数量子态，获取第三预设辅助比特的量子态，根据所述被减数量子态中的符号位子量子态和所述第三预设辅助比特的量子态，控制所述被减数量子态执行求补码运算对应的量子态演化，得到第一补码量子态；其中，所述第一补码量子态为包含所述被减数数据的补码的量子态；
由前述实施例可知，待运算的两个量子态有以下组：第一目标量子态和第二目标量子态；第三目标量子态和第四目标量子态；第一目标量子态和符号位取反后的第二目标量子态。其中，前者可称被减数量子态，包含的数据在减法运算中为被减数，后者可称减数量子态，包含的数据为减数。
本实施例中，主要用于实现减法器功能，减法器和下述加法器最大的区别就是会产生负数的情况，因此，采用二进制的处理方式，对减数和被减数都加一个符号位，来表示数值的正负，并且使用补码来进行运算。正数补码不变，负数除符号位外按位取反后，再加1。对应到量子线路中，即用符号位控制是否做补码操作，取反用X门，加1可通过加法器实现。在补码情况下运算完成后，再将结果做一次补码运算就得到了目标数值。获取待运算的被减数数据和减数数据，并将所述被减数数据以及所述减数数据分别转换为第一目标量子态和第二目标量子态。其中，目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态。
具体的，根据被减数量子态中的符号位子量子态和第三预设辅助比特的量子态，控制被减数量子态执行求补码运算对应的量子态演化，可以对被减数量子态中的符号位子量子态对应的第一符号位量子比特和第三预设辅助比特执行CNOT门操作，其中，第一符号位量子比特为控制比特，第三预设辅助比特为受控比特；并且，CNOT门可以用等效的其他现有的量子逻辑门或量子逻辑门组合进行替代，也是合理可行的；
根据执行CNOT门操作后的第三预设辅助比特的量子态，控制当前被减数量子态是否执行求补码运算对应的量子态演化；
若是，则对当前被减数量子态的非符号位子量子态取反，并将取反后的被减数量子态与第四预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第一补码量子态，否则，将所述被减数量子态作为第一补码量子态；其中，执行CNOT门操作后的第三预设辅助比特的量子态可以为|1>态时，才控制执行求补码运算对应的量子态演化，否则不执行；
对当前第一符号位量子比特和第三预设辅助比特执行CNOT门操作，以将当前第三预设辅助比特的量子态进行还原；其中，所述第一符号位量子比特为控制比特，所述第三预设辅助比特为受控比特。
示例性的，被减数量子态假设为|0011>。|0011>的符号位子量子态为最高位的子量子态即|0> 态，该位的值为0，对应的第一符号位量子比特设为g.sign，第三预设辅助比特为预设的量子比特q1，初始为|0>态。
对g.sign和q1执行CNOT门操作，g.sign作为控制比特，q1作为受控比特，g.sign位的量子态为|0>态，经过CNOT门操作后，受控比特位q1的量子态|0>不变。
由于执行CNOT门操作后的q1的量子态为|0>态，故不对被减数量子态执行求补码运算对应的量子态演化。原理上在于，被减数为正数时，在减法运算中无需求补码，或者说，其补码即为本身，可直接将|0011>作为第一补码量子态。
最后，可以对当前g.sign和q1再次执行CNOT门，g.sign位的量子态为|0>态，经过CNOT门操作后，受控比特位q1的量子态|0>不变，以还原q1为|0>态，从而释放第三辅助比特存储的信息。可得，第一补码量子态包含的值0011为被减数0011的补码。
如图52所示，q 1为第三预设辅助比特，用于控制是否做补码操作，所述第一目标量子态为g，g.sign为所述第一目标量子态中的符号位子量子态，剩余的g为表示所述数据数值的数值位子量子态，j为第四预设辅助比特，即被设置成值为1的辅助比特，p为加法器所使用的辅助比特(下述第五预设辅助比特)。与图50对应的是，上述k为n+2位，即包括：n位j、1位p、1位q1。
图52所示的量子线路实现了对g做求补码的操作的量子线路，先对g.sign与q 1进行CNOT门操作，使得q 1暂时表示g.sign，并用q 1控制是否进行求补码，求完补码后，再将q 1还原。由此，控制被减数量子态执行求补码运算对应的量子态演化，得到第一补码量子态。
具体地，根据g的符号位子量子态，用第一预设辅助比特q 1来控制是否做取补码的操作。若g为负数，则进行负数的取补码操作。负数的补码为除符号位外按位取反后加1，除符号位外按位取反的操作用逻辑门来实现的话，只需要对数值位全都做X门即可，取反后还需要加1，因此，通过使用j和g相加，j的值被设置为了1，p为加法器的辅助比特，在将数值位取反后的g和j相加后，g上存放的就是取完补码后的数值，再将q 1还原，以便下次使用。
例子：当g为负数时，g.sign为1，因此q 1也为1，就需要做取反等操作，而当g为正数时，g.sign为0，因此q 1也为0，就不需要再求补码了。
S5302，将所述减数量子态中的符号位子量子态执行符号位取反对应的量子态演化，并根据取反后的符号位子量子态和所述第三预设辅助比特的量子态，控制当前减数量子态执行求补码运算对应的量子态演化，得到第二补码量子态；其中，所述第二补码量子态为包含所述减数数据的补码的量子态；
具体的，可以对减数量子态中的符号位子量子态对应的第二符号位量子比特，执行X门操作，得到取反后的符号位子量子态；其中，X门可以用等效的其他现有的量子逻辑门或量子逻辑门组合进行替代，也是合理可行的；
同样的，继续对当前第二符号位量子比特和第三预设辅助比特执行CNOT门操作，其中，所述第二符号位量子比特为控制比特，所述第三预设辅助比特为受控比特；
根据执行CNOT门操作后的第三预设辅助比特的当前量子态，控制当前减数量子态是否执行求补码运算对应的量子态演化；
若是，则对当前减数量子态的非符号位子量子态取反，并将取反后的减数量子态与第四预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第二补码量子态，否则，将当前减数量子态作为第二补码量子态；
对当前第二符号位量子比特和第三预设辅助比特执行CNOT门操作，以将第三预设辅助比特的当前量子态进行还原；其中，所述第二符号位量子比特为控制比特，所述第三预设辅助比特为受控比特。
示例性的，减数量子态假设为|0100>。|0100>的符号位子量子态为最高位的子量子态即|0>态，该位的值为0，对应的第二符号位量子比特设为h.sign，当前第三辅助比特被还原为|0>态。
首先，可以对h.sign执行X门，将对应的符号位子量子态|0>取反为|1>，减数量子态变为|1100>。
继续对h.sign和q1执行CNOT门操作，h.sign作为控制比特，q1作为受控比特，当前h.sign位的量子态为|1>态，经过CNOT门操作后，受控比特位q1的量子态|0>被取反为|1>态。
执行CNOT门操作后的q1的量子态为|1>态，故对当前减数量子态|1100>执行求补码运算对应的量子态演化。一种执行求补码运算对应的量子态演化的实现如下：
对当前减数量子态|1100>的非符号位子量子态取反，并将取反后的减数量子态|1011>与第四预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第二补码量子态为|1100>。
其中，可通过执行X门对|1100>的非符号位子量子态|100>取反；为了保持维度一致，第四预设辅助比特为预设的4位量子比特j3、j2、j1、j0，第四预设辅助比特的量子态|1>实际上写为|0001>，两者是等同的。
最后，可对当前h.sign和q1再次执行CNOT门，h.sign位的量子态为|1>态，经过CNOT门操作后，受控比特位q1的量子态|1>被取反为|0>，从而再次还原q1为初始|0>态，释放q1的存储空间。可得，第二补码量子态包含的值1100为对h.sign执行X门后的减数1100的补码。
本实施例中，所述第二目标量子态h也是同理，初始对j [0]做X门是为了设置值为1，对第二目标量子态中的符号位子量子态h.sign做X门是为了把减法变成加法。如图53所示，图53为对g、h执行求补码运算对应的量子态演化的量子线路示意图，参考上述同理方法将第二目标量子态h执行求补码运算对应的量子态演化，得到第二补码量子态。
S5303，对所述第一补码量子态和所述第二补码量子态，执行加法运算对应的量子态演化，以将所述第一补码量子态演化为包含所述被减数数据的补码与所述减数数据的补码之和的第五目标量子态；
示例性的，对第一补码量子态为|0011>和第二补码量子态为|1100>，执行加法运算对应的量子态演化，将第一补码量子态|0011>演化为第五目标量子态|1111>。
本实施例中，在求完补码后，将g和h进行加法操作，加完后，再将之前的操作进行还原，g内储存的即为所求。将所述第一补码量子态和所述第二补码量子态代入加法器的量子线路，执行加法运算对应的量子态演化，由此，将所述第一补码量子态演化为包含所述被减数数据的补码与所述减数数据的补码之和的第三目标量子态。
S5304，根据所述第五目标量子态中的符号位子量子态和所述第三预设辅助比特的量子态，控制所述第五目标量子态执行求补码运算对应的量子态演化，得到演化后的第六目标量子态，作为所述被减数数据和所述减数数据的减法运算结果进行输出；其中，所述第六目标量子态为包含所述补码之和的补码的量子态；
示例性的，根据当前第五目标量子态|1111>中的符号位子量子态|1>和当前第三预设辅助比特的量子态|0>，控制第五目标量子态|1111>执行求补码运算对应的量子态演化，得到演化后的第六目标量子态|1001>，其包含的值为1001(十进制-1)，即为被减数量子态|0011>包含的被减数0011(十进制3)与减数量子态|0100>包含的减数0100(十进制4)的减法结果。
需要说明的是，执行求补码运算对应的量子态演化可与前述同理，演化后，第三预设辅助比特的量子态仍被还原为|0>，以便于后续计算使用。
S5305，根据当前减数量子态中的符号位子量子态和当前第三预设辅助比特的量子态，控制当前减数量子态执行求补码运算对应的量子态演化，并对当前减数量子态中的符号位子量子态执行符号位取反对应的量子态演化，以将当前减数量子态进行还原。
示例性的，当前减数量子态为第二补码量子态|1100>，当前第三预设辅助比特的量子态为|0>。继续按前述同理的方式，控制|1100>执行求补码运算对应的量子态演化，得到演化后的|1100>，然后通过X门操作对其符号位子量子态取反，将其还原成初始的减数量子态|0100>。
本实施例中，进行加法运算后，进一步对所述被减数数据的补码与所述减数数据的补码之和的第三目标量子态执行求补码运算对应的量子态演化。如图54所示，首先，对j [0]做一个X门的目 的是将j [0]的值设置为1，方便求补码中的+1运算。而对h的符号位做X门的操作的原因，则是为了将g-h转换为g+(-h)。然后，我们将g和h都做好补码的处理，处理完成后，再将g和h的补码进行相加，得到结果后，再将g和h做一次求补码的操作，将其还原为正常的数值，最后再对初始操作进行还原，也就是对辅助比特进行还原，做2个X门即可。由此组成了如图55所示的整个减法器的量子线路图，是一种功能上的简易示例。
下面详细说明执行加法运算对应的量子态演化的具体实现方式。
具体的，可以通过加法器执行加法运算对应的量子态演化，可以包括：
S5401,根据待运算的两个量子态对应的量子比特位的位数，确定待级联的前级联模块MAJ模块以及待级联的后级联模块UMA模块的目标模块个数，其中，所述MAJ模块的模块个数与所述UMA模块的模块个数相同；
由前述可知，待运算的两个量子态，可以是：第一补码量子态和第二补码量子态；取反后的被减数量子态和第四预设辅助比特的量子态|1>态。
示例性的，如图56所示，线路中第一个量子比特位为第五预设辅助比特位，初始为|0>态，最终会恢复为|0>态，e和f是待相加的数据对应的量子态，各对应一组量子比特位。c表示最终的进位项，对应预设进位辅助比特位，s为是不包含进位的输出位。一般要求e和f对应的量子比特位数相同,s和e、f的位数相同。
示例性的，如图57所示，e [i]和f [i]分别是两个加数对应量子态的第i位，c [i]是上一级进位。
s [i]＝e [i]XOR f [i]XOR c [i]，
c [i+1]＝(e [i]AND f [i])XOR(e [i]AND f [i])XOR(e [i]AND f [i])，
其中，第一个量子比特即为第五预设辅助比特位，对应量子线路中的c 0。第一个MAJ模块包括三个输入量子态以及对应的三个输出量子态，其中，三个输入量子态分别为c 0、e 0、f 0，e 0为第一个待运算量子态的第0位量子态，f 0为第二个待运算量子态的第0位量子态，c 0为第五预设辅助比特的量子态，初始值为0，即无进位。三个输出量子态分别为
Figure PCTCN2021119125-appb-000016
c 1，c 1为e 0和f 0相加后的进位，同理，下一个MAJ模块的三个输入量子态为c 1、e 1、f 1，三个输出量子态分别为
Figure PCTCN2021119125-appb-000017
c 2，以此类推至最后一个MAJ模块。
对于第一个UMA模块，包括三个输入量子态以及对应的三个输出量子态，其中，MAJ模块的三个输出量子态为对应UMA模块的三个输入量子态，三个输出量子态分别为c 0、s 0、e 0，s 0为e 0和f 0相加的不含进位的结果。同理，s1为e 1和f 1相加的不含进位的结果，以此类推，c4是最终的进位项。需要说明的是，在实际应用中，在无计算最终进位的需求下，量子线路中可以不设置c4对应的量子比特位。
并且，可以根据其中待运算的任一量子态包含的子量子态数量确定MAJ模块的模块个数以及UMA模块的个数，一子量子态对应一位量子比特，其中，MAJ模块的模块个数以及UMA模块的个数相等。图中所示仅仅作为示例，编码e和f各所需4位量子比特，MAJ模块和UMA模块的个数均为4。MAJ模块和UMA模块构成了加法器的前、后级联单元。MAJ模块可以用于提取出任何一步的进位项并且传递到下一级，从而将最终进位项计算出来。UMA模块一方面提取了c的信息会传递到上一级UMA，还计算出每一级的s(结果项)，并且恢复了e的信息。
示例性的：当4(对应编码在3个量子比特的量子态表示为100)+2(对应编码在3个量子比特的量子态表示为010)＝6(对应编码在3个量子比特的量子态表示为110)。此时编码运算结果的量子比特与编码e的量子比特位的个数或用来编码f的量子比特位的个数一致，MAJ模块的模块个数以及UMA模块的个数均为3。
示例性的：当4(对应编码在3个量子比特的量子态表示为100)+7(对应编码在3个量子比特的量子态表示为111)＝11(对应编码在3个量子比特的量子态表示为011)，但是，可以理解的是11对应的二进制数为1011，最左侧的1所在的位为进位项，该进位项可以通过辅助比特位表示。此时编码运算结果的量子比特与编码e的量子比特位的个数或用来编码f的量子比特位的个数 要多，MAJ模块的模块个数以及UMA模块的个数均为3。
示例性的，当2(对应编码在2个量子比特的量子态表示为10)+4(对应编码在3个量子比特的量子态表示为100)＝6(对应编码在3个量子比特的量子态表示为110)。此时，编码“6”数值的数值项“3”与编码b的量子比特位的量子态个数一致，MAJ模块的模块个数以及UMA模块的个数均为3。
S5402,根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成所述加法器对应的目标量子线路；
其中，所述MAJ模块以及所述UMA模块均包括三个输入项以及三个输出项，可以根据加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路，其中，所述MAJ级联模块由所述目标模块个数的MAJ模块之间级联确定，所述UMA级联模块由所述目标模块个数的UMA模块之间级联确定。
具体地，所述MAJ模块的三个输入项包括一个进位输入项以及两个待计算子量子态输入项，所述MAJ模块的三个输出项包括一个进位输出项和两个中间结果输出项，所述UMA模块的三个输入项包括对应MAJ模块的一个进位输出项以及两个中间结果输出项，所述UMA模块的三个输出项包括一个结果进位输出项、累加和输出项和一待计算子量子态输入项，
然后，可以根据加法指令，将上一MAJ模块输出的进位输出项以及所述两个待计算子量子态输入项作为下一MAJ模块的三个输入项，以将所述目标模块个数的MAJ模块进行级联；
将一MAJ模块的两个中间结果输出项作为一对应UMA模块的两个输入项，获取所述对应UMA模块的上一UMA模块，并将所述上一UMA模块的结果进位输出项作为所述对应UMA模块的一个输入项，以将所述目标模块个数的MAJ模块以及所述目标模块个数的UAM模块进行级联，生成所述初始量子线路；其中，最后一个MAJ模块的进位输出项作为对应的第一个UMA模块的一个输入项；
将所述初始量子线路中最后一个MAJ模块与对应的第一个UMA模块之间添加CNOT量子逻辑门，其中，将所述MAJ模块的进位输出项对应的量子比特作为控制比特，将预设进位辅助比特位作为受控比特位，以生成所述加法器的目标量子线路。在不需要进位项的情况下，可以不设置该CNOT门以及进位辅助比特位。
本实施例中，如图57所示，根据图示方式，将所述MAJ模块的三个输出比特作为所述UMA模块的三个输入比特，由此，将相同个数的MAJ模块以及UMA模块进行级联，生成所述加法器对应的目标量子线路。其中，线路图中相连的空心圆与实心圆，表示CNOT门操作，空心圆对应量子比特为控制比特位，实心圆对应为受控比特位。
其中，所述MAJ模块为MAJ量子线路，所述UMA模块为UMA量子线路，所述MAJ量子线路和所述UMA量子线路均包括两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门，所述根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成所述加法器对应的目标量子线路的步骤之前，还包括：获取所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门对应的操作量子比特、操作量子比特之间的控制关系以及所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门之间的时序关系；根据所述操作量子比特、所述控制关系以及所述时序关系，将所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门构建生成所述MAJ量子线路或所述UMA量子线路，作为对应的MAJ模块或UMA模块。
本实施例中，MAJ模块和UMA模块构成了加法器的前、后级联单元。如图58所示，MAJ模块用于提取出每一级加法运算后的进位项并且传递到下一级，从而将最终进位项计算出来。其中，如图59所示，MAJ模块主要可以由三个逻辑门组成，分别是两个CNOT门和一个Toffoli门。CNOT门(图59中的由左向右的第一个、第二个逻辑门)的作用为：将控制位加到目标位上去，形成一个模2加法，即为异或操作，得到(e i+c i)％2、(e i+f i)％2，两个CNOT门的顺序可以交换。Toffoli 门(图12中的由左向右的第三个逻辑门)的作用为：将两个控制位都加到目标位上去,得到进位项c [i+1]＝(e [i]AND f [i])XOR(e [i]AND f [i])XOR(e [i]AND f [i])。即通过图59中的由左向右的第一个CNOT门实现
Figure PCTCN2021119125-appb-000018
通过图59中的由左向右的第二个CNOT门实现
Figure PCTCN2021119125-appb-000019
通过图59中的由左向右的第三个TOFFOLI门实现c i+1，由此通过2个CNOT门和1个TOFFOLI门，构成量子加法器的前级级联单元。
例子1：e i为1，f i为1，c i为1。
MAJ模块开始把e i加到c i上，c i上的值变为0，再把e i加到f i上，f i上的值也变为0，最后用f i和c i加到e i上，e i的值变为1，也就是c i+1的进位为1。
例子2：e i为0，f i为1，c i为1。
MAJ模块开始把e i加到c i上，c i上的值变为1，再把e i加到f i上，f i上的值也变为1，最后用f i和c i加到e i上，e i的值变为1，也就是c i+1的进位为1。
如图60所示，UMA模块用于级联加法器的后级，UMA模块的实现方式和MAJ模块类似，如图61所示，首先使用Toffoli门(图61中的由左向右的第一个逻辑门)将c i+1还原为e i，再用e i对(e+c)％2用CNOT门(图61中的由左向右的第二个逻辑门)做一次还原，将(e i+c i)％2还原为c i，最后，再使用c i对(e i+f i)％2做一次CNOT门(图61中的由左向右的第三个逻辑门)，得到当前位的最终结果s [i]＝e [i]XOR f [i]XOR c [i]。
例子1：(e i+c i)％2为0，(e i+f i)％2为0，c i+1为1。
开始把(e i+c i)％2和(e i+f i)％2加到c i+1上，c i+1的值变为1，表示的意义变为e i，再用e i加到(e i+c i)％2上，(e i+c i)％2的值变为1，表示的意义变为c i,再用c i加到(e i+f i)％2上，(e i+f i)％2的值变为1，意义变为s i。
例子2：(e i+c i)％2为1，(e i+f i)％2为1，c i+1为1。
开始把(e i+c i)％2和(e i+f i)％2加到c i+1上，c i+1的值变为0，意义变为e i，再用e i加到(e i+c i)％2上，(e i+c i)％2的值变为1，意义变为c i,再用c i加到(e i+f i)％2上，(e i+f i)％2的值变为0，意义变为s i。
如图57中由上向下的最后一个CNOT门，即整个加法器MAJ模块和UMA模块中间的CNOT门，用于保存c i+1的结果。
S5403，通过所述目标量子线路对所述待运算的两个量子态的各子量子态进行加法运算，生成目标量子态结果并输出。
本实施例中，通过将待运算的两个量子态，如|111>和|111>，输入加法器(即所述目标量子线路)中，得到对应的二进制表示目标量子态计算结果(包括进位项以及各子量子态直接相加得到的结果项)。然后将二进制表示的目标量子态结果|1110>直接输出，或进一步转化为十进制结果14并输出，完成两目标数据的加法运算。
可见，通过获取待运算的被除数数据和除数数据，并将被除数数据转换为第一目标量子态，将除数数据转换为第二目标量子态，对第一目标量子态和第二目标量子态，迭代执行减法运算对应的量子态演化，并对减法运算的执行次数进行计数，直至将被除数数据减为负数，将最终获得的计数结果，作为被除数数据与除数数据相除的商的整数位进行输出，对当前第一目标量子态和当前第二目标量子态，迭代执行商的小数位运算对应的量子态演化，将最终获得的预设精度位量子比特上的量子态进行输出，从而实现可以用于量子线路中的基本算术运算操作，填补了相关技术的空白。
参见图62，图62是本发明一实施例提供的带精度的量子除法运算装置的结构示意图，可以包括：
转换模块51501，用于获取待运算的被除数数据和除数数据，并将所述被除数数据转换为第一目标量子态，将所述除数数据转换为第二目标量子态；其中，目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态；
第一量子态演化模块51502，用于对所述第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为 负数，将最终获得的计数结果，作为所述被除数数据与所述除数数据相除的商的整数位进行输出；其中，每次执行减法运算的被减数为上次执行减法运算的减法结果、减数为所述除数数据；
第二量子态演化模块51503，用于对当前第一目标量子态和当前第二目标量子态，迭代执行所述商的小数位运算对应的量子态演化；其中，该迭代的预设迭代次数与待计算的小数位精度的位数一致，每次迭代后在对应的预设精度位量子比特上得到包含对应精度位的值的量子态；
输出模块51504，用于将最终获得的预设精度位量子比特上的量子态进行输出，其中，该量子态包含所述商的小数位的二进制值。
具体的，所述第一量子态演化模块，具体用于：
对当前第一目标量子态和所述第二目标量子态，执行减法运算对应的量子态演化，以获得包含减法运算结果的第一目标量子态；
对当前第一预设辅助比特的第三目标量子态和当前第二预设辅助比特的第四目标量子态，执行减法运算对应的量子态演化，以将当前第三目标量子态包含的值加1；其中，所述第三目标量子态包含的初值、所述第四目标量子态包含的值均为-1；
测量当前包含减法运算结果的第一目标量子态的符号位子量子态，判断当前包含减法运算结果的第一目标量子态的符号位的值是否为0；
在当前包含减法运算结果的第一目标量子态的符号位的值为0的情况下，返回执行所述对当前第一目标量子态和当前第二目标量子态，执行减法运算对应的量子态演化的步骤，直至判断出当前包含减法运算结果的第一目标量子态的符号位的值为1。
具体的，所述输出模块，具体用于：
将最终获得的第三目标量子态进行输出，其中，所述第三目标量子态包含的值为所述被除数数据与所述除数数据相除的商的整数位二进制值。
具体的，所述第二量子态演化模块，具体用于：
将当前第二目标量子态的符号位子量子态取反，对当前第一目标量子态和符号位取反后的第二目标量子态，执行减法运算对应的量子态演化，以将当前第一目标量子态演化为包含所述被除数数据与所述除数数据相除的余数二进制值的量子态；
将当前第一目标量子态的各位子量子态均左移一位，将当前第二目标量子态的符号位子量子态再取反，对左移一位后的第一目标量子态和再取反后的第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述左移一位后的第一目标量子态减为负数，在预设中间位量子比特上得到包含计数结果的二进制值的小数位量子态；
将所述小数位量子态的最后一位子量子态与对应的预设精度位量子比特的初始量子态|0>态进行交换，并输出交换后的预设精度位量子比特上的量子态；
返回执行所述将当前第二目标量子态的符号位子量子态取反，对当前第一目标量子态和符号位取反后的第二目标量子态，执行减法运算对应的量子态演化的步骤，直至达到所述迭代执行所述商的小数位运算对应的量子态演化所需的预设迭代次数，其中，所述预设迭代次数与待计算的小数位精度的位数一致。
具体的，所述装置还包括：
执行模块，用于获取预设符号位量子比特，对所述第一目标量子态的符号位子量子态对应的量子比特、所述第二目标量子态的符号位子量子态对应的量子比特、所述第一预设辅助比特和所述预设符号位量子比特，执行预设量子逻辑门操作，以最终获得所述第三目标量子态中符号位子量子态表示的符号值。
具体的，所述运算模块，包括：
第一补码运算单元，用于对于待运算的两个量子态，分别作为包含被减数据的被减数量子态和包含减数数据的减数量子态，获取第三预设辅助比特的量子态，根据所述被减数量子态中的符号位子量子态和所述第三预设辅助比特的量子态，控制所述被减数量子态执行求补码运算对应的量子 态演化，得到第一补码量子态；其中，所述第一补码量子态为包含所述被减数数据的补码的量子态；
第二补码运算单元，用于将所述减数量子态中的符号位子量子态执行符号位取反对应的量子态演化，并根据取反后的符号位子量子态和所述第三预设辅助比特的量子态，控制当前减数量子态执行求补码运算对应的量子态演化，得到第二补码量子态；其中，所述第二补码量子态为包含所述减数数据的补码的量子态；
加法运算单元，用于对所述第一补码量子态和所述第二补码量子态，执行加法运算对应的量子态演化，以将所述第一补码量子态演化为包含所述被减数数据的补码与所述减数数据的补码之和的第五目标量子态；
第三补码运算单元，用于根据所述第五目标量子态中的符号位子量子态和所述第三预设辅助比特的量子态，控制所述第五目标量子态执行求补码运算对应的量子态演化，得到演化后的第六目标量子态，作为所述被减数数据和所述减数数据的减法运算结果进行输出；其中，所述第六目标量子态为包含所述补码之和的补码的量子态；
第四补码运算单元，用于根据当前减数量子态中的符号位子量子态和当前第三预设辅助比特的量子态，控制当前减数量子态执行求补码运算对应的量子态演化，并对当前减数量子态中的符号位子量子态执行符号位取反对应的量子态演化，以将当前减数量子态进行还原。
具体的，所述第一补码运算单元，具体用于：
对所述被减数量子态中的符号位子量子态对应的第一符号位量子比特和所述第三预设辅助比特执行CNOT门操作，其中，所述第一符号位量子比特为控制比特，所述第三预设辅助比特为受控比特；
根据执行CNOT门操作后的所述第三预设辅助比特的量子态，控制当前被减数量子态是否执行求补码运算对应的量子态演化；
若是，则对当前被减数量子态的非符号位子量子态取反，并将取反后的被减数量子态与第四预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第一补码量子态，否则，将所述被减数量子态作为第一补码量子态；
对当前第一符号位量子比特和第三预设辅助比特执行CNOT门操作，以将当前第三预设辅助比特的量子态进行还原；其中，所述第一符号位量子比特为控制比特，所述第三预设辅助比特为受控比特。
具体的，所述第二补码运算单元，具体用于：
对所述减数量子态中的符号位子量子态对应的第二符号位量子比特，执行X门操作，得到取反后的符号位子量子态；
对当前第二符号位量子比特和第三预设辅助比特执行CNOT门操作，其中，所述第二符号位量子比特为控制比特，所述第三预设辅助比特为受控比特；
根据执行CNOT门操作后的第三预设辅助比特的当前量子态，控制当前减数量子态是否执行求补码运算对应的量子态演化；
若是，则对当前减数量子态的非符号位子量子态取反，并将取反后的减数量子态与第四预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第二补码量子态，否则，将当前减数量子态作为第二补码量子态；
对当前第二符号位量子比特和第三预设辅助比特执行CNOT门操作，以将第三预设辅助比特的当前量子态进行还原；其中，所述第二符号位量子比特为控制比特，所述第三预设辅助比特为受控比特。
具体的，所述加法运算单元，包括：
确定子单元，用于根据待运算的两个量子态对应的量子比特位的位数，确定待级联的前级联模块MAJ模块以及待级联的后级联模块UMA模块的目标模块个数，其中，所述MAJ模块的模块个数与所述UMA模块的模块个数相同；
级联子单元，用于根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成加法器对应的目标量子线路；
运算子单元，用于通过所述目标量子线路对所述待运算的两个量子态的各子量子态进行加法运算，生成目标量子态结果并输出。
具体的，所述MAJ模块为MAJ量子线路，所述UMA模块为UMA量子线路，所述MAJ量子线路和所述UMA量子线路均包括两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门，
所述加法运算单元，还包括：
获取子单元，用于获取所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门对应的操作量子比特、操作量子比特之间的控制关系以及所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门之间的时序关系；
构建子单元，用于根据所述操作量子比特、所述控制关系以及所述时序关系，将所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门构建生成所述MAJ量子线路或所述UMA量子线路，作为对应的MAJ模块或UMA模块。
具体的，所述MAJ模块以及所述UMA模块均包括三个输入项以及三个输出项，所述级联子单元，具体用于：
根据加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路，其中，所述MAJ级联模块由所述目标模块个数的MAJ模块之间级联确定，所述UMA级联模块由所述目标模块个数的UMA模块之间级联确定。
具体的，所述MAJ模块的三个输入项包括一个进位输入项以及两个待计算子量子态输入项，所述MAJ模块的三个输出项包括一个进位输出项和两个中间结果输出项，所述UMA模块的三个输入项包括对应MAJ模块的一个进位输出项以及两个中间结果输出项，所述UMA模块的三个输出项包括一个结果进位输出项、累加和输出项和一待计算子量子态输入项；所述级联子单元，具体用于：
根据加法指令，将上一MAJ模块输出的进位输出项以及所述两个待计算子量子态输入项作为下一MAJ模块的三个输入项，以将所述目标模块个数的MAJ模块进行级联；
将一MAJ模块的两个中间结果输出项作为一对应UMA模块的两个输入项，获取所述对应UMA模块的上一UMA模块，并将所述上一UMA模块的结果进位输出项作为所述对应UMA模块的一个输入项，以将所述目标模块个数的MAJ模块以及所述目标模块个数的UAM模块进行级联，生成所述初始量子线路；其中，最后一个MAJ模块的进位输出项作为对应的第一个UMA模块的一个输入项；
将所述初始量子线路中最后一个MAJ模块与对应的第一个UMA模块之间添加CNOT量子逻辑门，其中，将所述MAJ模块的进位输出项对应的量子比特作为控制比特，将预设进位辅助比特位作为受控比特位，以生成所述加法器的目标量子线路。
可见，本发明通过获取待运算的被除数数据和除数数据，并将被除数数据转换为第一目标量子态，将除数数据转换为第二目标量子态，对第一目标量子态和第二目标量子态，迭代执行减法运算对应的量子态演化，并对减法运算的执行次数进行计数，直至将被除数数据减为负数，将最终获得的计数结果，作为被除数数据与除数数据相除的商的整数位进行输出，对当前第一目标量子态和当前第二目标量子态，迭代执行商的小数位运算对应的量子态演化，将最终获得的预设精度位量子比特上的量子态进行输出，从而实现可以用于量子线路中的基本算术运算操作，填补了相关技术的空白。
本发明的再一实施例提供了一种电子装置，包括存储器和处理器，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行如下所述的方法：
S1，获取待运算的被除数数据和除数数据，并将所述被除数数据转换为第一目标量子态， 将所述除数数据转换为第二目标量子态；其中，所述目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态；
S2，对所述第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为负数，将最终获得的计数结果，作为所述被除数数据与所述除数数据相除的商的整数位进行输出；其中，每次执行减法运算的被减数为上次执行减法运算的减法结果、减数为所述除数数据；
S3，对当前第一目标量子态和当前第二目标量子态，迭代执行所述商的小数位运算对应的量子态演化；其中，该迭代的预设迭代次数与待计算的小数位精度的位数一致，每次迭代后在对应的预设精度位量子比特上得到包含对应精度位的值的量子态；
S4，将最终获得的预设精度位量子比特上的量子态进行输出，其中，该量子态包含所述商的小数位的二进制值。
本发明的再一实施例提供了一种存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行如下所述的方法：
S1，获取待运算的被除数数据和除数数据，并将所述被除数数据转换为第一目标量子态，将所述除数数据转换为第二目标量子态；其中，所述目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态；
S2，对所述第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为负数，将最终获得的计数结果，作为所述被除数数据与所述除数数据相除的商的整数位进行输出；其中，每次执行减法运算的被减数为上次执行减法运算的减法结果、减数为所述除数数据；
S3，对当前第一目标量子态和当前第二目标量子态，迭代执行所述商的小数位运算对应的量子态演化；其中，该迭代的预设迭代次数与待计算的小数位精度的位数一致，每次迭代后在对应的预设精度位量子比特上得到包含对应精度位的值的量子态；
S4，将最终获得的预设精度位量子比特上的量子态进行输出，其中，该量子态包含所述商的小数位的二进制值。
以上依据图式所示的实施例详细说明了本发明的构造、特征及作用效果，以上所述仅为本发明的较佳实施例，但本发明不以图面所示限定实施范围，凡是依照本发明的构想所作的改变，或修改为等同变化的等效实施例，仍未超出说明书与图示所涵盖的精神时，均应在本发明的保护范围内。。

Claims (15)

  1. 一种带精度的量子除法运算方法，其特征在于，所述方法包括：
    获取待运算的被除数数据和除数数据，并将所述被除数数据转换为第一目标量子态，将所述除数数据转换为第二目标量子态；其中，目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态；
    对所述第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为负数，将最终获得的计数结果，作为所述被除数数据与所述除数数据相除的商的整数位进行输出；其中，每次执行减法运算的被减数为上次执行减法运算的减法结果、减数为所述除数数据；
    对当前第一目标量子态和当前第二目标量子态，迭代执行所述商的小数位运算对应的量子态演化；其中，该迭代的预设迭代次数与待计算的小数位精度的位数一致，每次迭代后在对应的预设精度位量子比特上得到包含对应精度位的值的量子态；
    将最终获得的预设精度位量子比特上的量子态进行输出，其中，该量子态包含所述商的小数位的二进制值。
  2. 根据权利要求1所述的方法，其特征在于，所述对所述第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为负数，包括：
    对当前第一目标量子态和所述第二目标量子态，执行减法运算对应的量子态演化，以获得包含减法运算结果的第一目标量子态；
    对当前第一预设辅助比特的第三目标量子态和当前第二预设辅助比特的第四目标量子态，执行减法运算对应的量子态演化，以将当前第三目标量子态包含的值加1；其中，所述第三目标量子态包含的初值、所述第四目标量子态包含的值均为-1；
    测量当前包含减法运算结果的第一目标量子态的符号位子量子态，判断当前包含减法运算结果的第一目标量子态的符号位的值是否为0；
    在当前包含减法运算结果的第一目标量子态的符号位的值为0的情况下，返回执行所述对当前第一目标量子态和当前第二目标量子态，执行减法运算对应的量子态演化的步骤，直至判断出当前包含减法运算结果的第一目标量子态的符号位的值为1。
  3. 根据权利要求2所述的方法，其特征在于，所述将最终获得的计数结果，作为所述被除数数据与所述除数数据相除的商的整数位进行输出，包括：
    将最终获得的第三目标量子态进行输出，其中，所述第三目标量子态包含的值为所述被除数数据与所述除数数据相除的商的整数位二进制值。
  4. 根据权利要求3所述的方法，其特征在于，所述对当前第一目标量子态和当前第二目标量子态，迭代执行所述商的小数位运算对应的量子态演化，包括：
    将当前第二目标量子态的符号位子量子态取反，对当前第一目标量子态和符号位取反后的第二目标量子态，执行减法运算对应的量子态演化，以将当前第一目标量子态演化为包含所述被除数数据与所述除数数据相除的余数二进制值的量子态；
    将当前第一目标量子态的各位子量子态均左移一位，将当前第二目标量子态的符号位子量子态再取反，对左移一位后的第一目标量子态和再取反后的第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述左移一位后的第一目标量子态减为负数，在预设中间位量子比特上得到包含计数结果的二进制值的小数位量子态；
    将所述小数位量子态的最后一位子量子态与对应的预设精度位量子比特的初始量子态|0>态进行交换，并输出交换后的预设精度位量子比特上的量子态；
    返回执行所述将当前第二目标量子态的符号位子量子态取反，对当前第一目标量子态和符号 位取反后的第二目标量子态，执行减法运算对应的量子态演化的步骤，直至达到所述迭代执行所述商的小数位运算对应的量子态演化所需的预设迭代次数，其中，所述预设迭代次数与待计算的小数位精度的位数一致。
  5. 根据权利要求4所述的方法，其特征在于，所述方法还包括：
    获取预设符号位量子比特，对所述第一目标量子态的符号位子量子态对应的量子比特、所述第二目标量子态的符号位子量子态对应的量子比特、所述第一预设辅助比特和所述预设符号位量子比特，执行预设量子逻辑门操作，以最终获得所述第三目标量子态中符号位子量子态表示的符号值。
  6. 根据权利要求5所述的方法，其特征在于，所述执行减法运算对应的量子态演化，包括：
    对于待运算的两个量子态，分别作为包含被减数据的被减数量子态和包含减数数据的减数量子态，获取第三预设辅助比特的量子态，根据所述被减数量子态中的符号位子量子态和所述第三预设辅助比特的量子态，控制所述被减数量子态执行求补码运算对应的量子态演化，得到第一补码量子态；其中，所述第一补码量子态为包含所述被减数数据的补码的量子态；
    将所述减数量子态中的符号位子量子态执行符号位取反对应的量子态演化，并根据取反后的符号位子量子态和所述第三预设辅助比特的量子态，控制当前减数量子态执行求补码运算对应的量子态演化，得到第二补码量子态；其中，所述第二补码量子态为包含所述减数数据的补码的量子态；
    对所述第一补码量子态和所述第二补码量子态，执行加法运算对应的量子态演化，以将所述第一补码量子态演化为包含所述被减数数据的补码与所述减数数据的补码之和的第五目标量子态；
    根据所述第五目标量子态中的符号位子量子态和所述第三预设辅助比特的量子态，控制所述第五目标量子态执行求补码运算对应的量子态演化，得到演化后的第六目标量子态，作为所述被减数数据和所述减数数据的减法运算结果进行输出；其中，所述第六目标量子态为包含所述补码之和的补码的量子态；
    根据当前减数量子态中的符号位子量子态和当前第三预设辅助比特的量子态，控制当前减数量子态执行求补码运算对应的量子态演化，并对当前减数量子态中的符号位子量子态执行符号位取反对应的量子态演化，以将当前减数量子态进行还原。
  7. 根据权利要求6所述的方法，其特征在于，所述根据所述被减数量子态中的符号位子量子态和所述第三预设辅助比特的量子态，控制所述被减数量子态执行求补码运算对应的量子态演化，包括：
    对所述被减数量子态中的符号位子量子态对应的第一符号位量子比特和所述第三预设辅助比特执行CNOT门操作，其中，所述第一符号位量子比特为控制比特，所述第三预设辅助比特为受控比特；
    根据执行CNOT门操作后的所述第三预设辅助比特的量子态，控制当前被减数量子态是否执行求补码运算对应的量子态演化；
    若是，则对当前被减数量子态的非符号位子量子态取反，并将取反后的被减数量子态与第四预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第一补码量子态，否则，将所述被减数量子态作为第一补码量子态；
    对当前第一符号位量子比特和第三预设辅助比特执行CNOT门操作，以将当前第三预设辅助比特的量子态进行还原；其中，所述第一符号位量子比特为控制比特，所述第三预设辅助比特为受控比特。
  8. 根据权利要求6所述的方法，其特征在于，所述将所述减数量子态中的符号位子量子态执行符号位取反对应的量子态演化，并根据取反后的符号位子量子态和所述第三预设辅助比特的量子态，控制当前减数量子态执行求补码运算对应的量子态演化，包括：
    对所述减数量子态中的符号位子量子态对应的第二符号位量子比特，执行X门操作，得到取反后的符号位子量子态；
    对当前第二符号位量子比特和第三预设辅助比特执行CNOT门操作，其中，所述第二符号 位量子比特为控制比特，所述第三预设辅助比特为受控比特；
    根据执行CNOT门操作后的第三预设辅助比特的当前量子态，控制当前减数量子态是否执行求补码运算对应的量子态演化；
    若是，则对当前减数量子态的非符号位子量子态取反，并将取反后的减数量子态与第四预设辅助比特的量子态|1>态，执行加法运算对应的量子态演化，得到演化后的第二补码量子态，否则，将当前减数量子态作为第二补码量子态；
    对当前第二符号位量子比特和第三预设辅助比特执行CNOT门操作，以将第三预设辅助比特的当前量子态进行还原；其中，所述第二符号位量子比特为控制比特，所述第三预设辅助比特为受控比特。
  9. 根据权利要求6所述的方法，其特征在于，所述执行加法运算对应的量子态演化，包括：
    根据待运算的两个量子态对应的量子比特位的位数，确定待级联的前级联模块MAJ模块以及待级联的后级联模块UMA模块的目标模块个数，其中，所述MAJ模块的模块个数与所述UMA模块的模块个数相同；
    根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成加法器对应的目标量子线路；
    通过所述目标量子线路对所述待运算的两个量子态的各子量子态进行加法运算，生成目标量子态结果并输出。
  10. 根据权利要求9所述的方法，其特征在于，所述MAJ模块为MAJ量子线路，所述UMA模块为UMA量子线路，所述MAJ量子线路和所述UMA量子线路均包括两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门，
    所述根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成加法器对应的目标量子线路的步骤之前，还包括：
    获取所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门对应的操作量子比特、操作量子比特之间的控制关系以及所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门之间的时序关系；
    根据所述操作量子比特、所述控制关系以及所述时序关系，将所述两个CNOT量子逻辑门和一个TOFFOLI量子逻辑门构建生成所述MAJ量子线路或所述UMA量子线路，作为对应的MAJ模块或UMA模块。
  11. 根据权利要求10所述的方法，其特征在于，所述MAJ模块以及所述UMA模块均包括三个输入项以及三个输出项，
    所述根据加法指令，将所述目标模块个数的MAJ模块以及UMA模块进行级联，生成所述加法器对应的目标量子线路的步骤具体包括：
    根据加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路，其中，所述MAJ级联模块由所述目标模块个数的MAJ模块之间级联确定，所述UMA级联模块由所述目标模块个数的UMA模块之间级联确定。
  12. 根据权利要求11所述的方法，其特征在于，所述MAJ模块的三个输入项包括一个进位输入项以及两个待计算子量子态输入项，所述MAJ模块的三个输出项包括一个进位输出项和两个中间结果输出项，所述UMA模块的三个输入项包括对应MAJ模块的一个进位输出项以及两个中间结果输出项，所述UMA模块的三个输出项包括一个结果进位输出项、累加和输出项和一待计算子量子态输入项，
    所述根据加法指令，将一MAJ级联模块的三个输出项作为一对应UMA级联模块的三个输入项，以将所述MAJ级联模块与对应的UMA级联模块进行级联，生成所述加法器对应的目标量子线路的步骤具体包括：
    根据加法指令，将上一MAJ模块输出的进位输出项以及所述两个待计算子量子态输入项作为下一MAJ模块的三个输入项，以将所述目标模块个数的MAJ模块进行级联；
    将一MAJ模块的两个中间结果输出项作为一对应UMA模块的两个输入项，获取所述对应UMA模块的上一UMA模块，并将所述上一UMA模块的结果进位输出项作为所述对应UMA模块的一个输入项，以将所述目标模块个数的MAJ模块以及所述目标模块个数的UAM模块进行级联，生成所述初始量子线路；其中，最后一个MAJ模块的进位输出项作为对应的第一个UMA模块的一个输入项；
    将所述初始量子线路中最后一个MAJ模块与对应的第一个UMA模块之间添加CNOT量子逻辑门，其中，将所述MAJ模块的进位输出项对应的量子比特作为控制比特，将预设进位辅助比特位作为受控比特位，以生成所述加法器的目标量子线路。
  13. 一种带精度的量子除法运算装置，其特征在于，所述装置包括：
    转换模块，用于获取待运算的被除数数据和除数数据，并将所述被除数数据转换为第一目标量子态，将所述除数数据转换为第二目标量子态；其中，目标量子态包括：表示所述数据符号的符号位子量子态和表示所述数据数值的数值位子量子态；
    第一量子态演化模块，用于对所述第一目标量子态和所述第二目标量子态，迭代执行减法运算对应的量子态演化，并对所述减法运算的执行次数进行计数，直至将所述被除数数据减为负数，将最终获得的计数结果，作为所述被除数数据与所述除数数据相除的商的整数位进行输出；其中，每次执行减法运算的被减数为上次执行减法运算的减法结果、减数为所述除数数据；
    第二量子态演化模块，用于对当前第一目标量子态和当前第二目标量子态，迭代执行所述商的小数位运算对应的量子态演化；其中，该迭代的预设迭代次数与待计算的小数位精度的位数一致，每次迭代后在对应的预设精度位量子比特上得到包含对应精度位的值的量子态；
    输出模块，用于将最终获得的预设精度位量子比特上的量子态进行输出，其中，该量子态包含所述商的小数位的二进制值。
  14. 一种电子装置，包括存储器和处理器，其特征在于，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行所述权利要求1至12任一项中所述的方法。
  15. 一种存储介质，其特征在于，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行所述权利要求1至12任一项中所述的方法。
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