WO2022068302A1

WO2022068302A1 - Chip, communication system and communication method

Info

Publication number: WO2022068302A1
Application number: PCT/CN2021/103888
Authority: WO
Inventors: 王柯鉴; 陈永炜; 潘银海; 李永耀; 范茂斌
Original assignee: 华为技术有限公司
Priority date: 2020-09-30
Filing date: 2021-06-30
Publication date: 2022-04-07

Abstract

Provided are a chip, a communication system and a communication method. The communication method comprises the following steps: a chip shaking hands with an opposite chip, so as to establish a transmission link; when a data transmission error is detected, controlling the transmission link to enter a recovery state; in the recovery state, performing data recovery on the transmission link, and correcting matching parameters of ports at two ends of the transmission link when same is in a data transmission state; and after the recovery of the transmission link is completed, controlling the transmission link to enter a low power consumption state. In the solution, by means of setting a recovery state, when data transmission fails, a transmission link is recovered, such that the reliability thereof during data transmission is improved. In addition, during recovery, only matching parameters corresponding to data transmission are recovered, and it is not necessary to re-match basic information of two chips during handshaking, thereby improving the recovery effect.

Description

A chip, communication system and communication method

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of the Chinese patent application filed on September 30, 2020 with the application number 202011066534.6 and the application title is "a chip, communication system and communication method", the entire contents of which are incorporated herein by reference In application; this application claims the priority of the Chinese patent application with the application number 202011196760.6 and the application name "a chip, communication system and communication method" submitted to the Chinese Patent Office on October 31, 2020, the entire contents of which are by reference Incorporated in this application.

technical field

The present application relates to the field of communication technologies, and in particular, to a chip, a communication system and a communication method.

Background technique

In recent years, the progress of industrial technology has led to a substantial increase in the level of port data transmission in the mobile device industry. The mobile device industry has begun to widely use high-speed data serial ports in terminal products. Physical layer ports must face the increasing data transmission rate. higher challenge. Under the condition of high-speed data transmission, the working state of the port needs strict logic support.

At present, the environment in which high-speed data serial ports are used in terminal products can be roughly divided into the following application scenarios: application processor-camera, application processor-display, storage, etc. Therefore, high-speed data serial ports need to support a variety of applications Due to the limitation of application scenarios, with the continuous improvement of data transmission rate, the possibility of various errors in the data transmission link is increasing, which poses a great challenge to the stability of the transmission link. The data transmission in the network can no longer meet the demand.

SUMMARY OF THE INVENTION

The present application provides a chip, a communication system and a communication method, aiming at improving the reliability during communication.

In a first aspect, a communication method is provided, the communication method is applied to the conversion of communication transmission links in a communication system, the communication method includes the following steps: when a data transmission error is detected in a data transmission state, controlling a sending port and receiving All ports enter the repair state, where the data transmission state includes high-speed data transmission state and low-speed data transmission state. In the high-speed data transmission state, the data transmission rate is greater than or equal to 1Gbps, the sending port is located on the main chip side, and the receiving port is located on the side of the main chip. The master chip has the slave chip side of the communication relationship; in the repair state, data repair is performed on the sending port and the receiving port, the parameters of the sending port are repaired to the parameters when the sending port is in the data transmission state, and the parameters of the receiving port are repaired to The parameters when the receiving port is in the data transmission state; after completing the data restoration of the sending port and the receiving port, control the sending port and the receiving port to enter the low power consumption state or enter the high-speed data transmission state again. In the above solution, by setting the repair state, when the data transmission fails, the transmission link is repaired, which improves the reliability of the data transmission. In addition, when repairing, only the matching parameters corresponding to data transmission are repaired, and there is no need to match the basic information of the two chips during handshake, which improves the repairing efficiency.

In a specific implementation, after the data transmission error is detected, and before both the sending port and the receiving port are controlled to enter the repair state, the method further includes: controlling the sending Both the port and the receiving port enter a low power consumption state. The low-power state is used as an intermediate state to facilitate state switching.

In a specific implementation, the controlling both the sending port and the receiving port to enter the repair state specifically refers to: controlling both the sending port and the receiving port to enter the low power consumption state to the repaired state. Repair the ports at both ends of the transmission link.

In a specific implementation, when a data transmission error is detected, both the sending port and the receiving port are controlled to enter a repair state; specifically: when the data transmission error is detected, control the sending The port enters the repair state, and sends a repair control code stream to the slave chip, so that the protocol layer or controller of the slave chip controls the receiving port to enter the repair state according to the repair control code stream . The main chip controls the sending port and the receiving port to enter the repair state.

In a specific implementation, the method further includes: after completing the data restoration and before controlling both the transmitting port and the receiving port to enter the low power consumption state, the method further includes: It is confirmed that the parameters of the sending port after the repair are the parameters when the sending port is in the data transmission state, and the parameters of the receiving port are the parameters when the receiving port is in the data transmission state. After the parameter configuration of the transmission link is changed, a handshake process is added to make a preliminary judgment on the accuracy of the repaired data transmission to improve the robustness of the transmission link.

In a specific implementation, before the high-speed data transmission state in which the data transmission error is detected, both the transmitting port and the receiving port are in the low power consumption state. The low-power state is used as an intermediate state to facilitate state switching.

In a specific implementation, the method further includes: after completing the data transmission, controlling both the sending port and the receiving port to enter the low power consumption state for waiting for a next state trigger condition. The interoperability between the states of the state machine is improved through the low power consumption state, and the configuration process of the transmission link is reasonably arranged, so that the transition between any different states only needs to jump twice at most.

In a specific implementation, the method further includes: triggering the transmission link to enter a low-speed data transmission state through a low-speed data control code stream, and performing low-speed data transmission; after completing the low-speed data transmission, controlling the The transmission link enters the low power consumption state. The interoperability between the states of the state machine is improved through the low power consumption state, and the configuration process of the transmission link is reasonably arranged, so that the transition between any different states only needs to jump twice at most.

In a specific implementation, before both the sending port and the receiving port enter the low power consumption state for the first time, the method further includes: establishing transmission between the master chip and the slave chip link, and perform port information exchange. The port information exchange means that the master chip sends the port information of the sending port to the slave chip, and the slave chip sends the port information of the receiving port to the slave chip. the main chip; after completing the port information exchange, both the sending port and the receiving port enter the low power consumption state for the first time. It is convenient to switch state.

In a second aspect, a communication method is provided, the method comprising: before a sending port and a receiving port enter a data transmission state, detecting the current parameters of the sending port and the current parameters of the receiving port, and judging the sending port Whether the current parameters are consistent with the parameters matched by the sending port when sending data according to the target data transmission rate, and determine whether the current parameters of the receiving port match the parameters when the receiving port receives data according to the target data transmission rate Whether it is consistent, the sending port is located on the master chip side, and the receiving port is located on the slave chip side that has a communication relationship with the master chip; the current parameters of the sending port and the receiving port are the same as their target data When the parameters matched in the transmission rate are inconsistent, control the sending port and the receiving port to enter a rate switching state; in the rate switching state, switch the current parameters of the sending port to the sending port that transmits data according to the target data The parameters matched when sending data at a rate, and the parameters of the receiving port are switched to the parameters matched when the receiving port receives data according to the target data transmission rate; after the switching is completed, the sending port and the receiving port into a low-power state. By matching the transmission link before data transmission, the reliability of data transmission is improved.

In a specific implementation, the method further includes: when the current parameter of the sending port is switched to the parameter matched when the sending port sends data according to the target data transmission rate, and the current parameter of the receiving port is switched After being switched to the parameters that the receiving port matches when receiving data according to the target data transmission rate, receive the data transmission control code stream and control the transmission link to switch from the low power consumption state to the transmission of the target data A rate-matched high-speed data transfer state or a low-speed data transfer state, the high-speed data transfer rate being greater than the low-speed data transfer rate. Enter the data transmission state after matching the parameters.

In a specific implementation, the method further includes: during the data transmission process, when the data transmission rate changes, controlling both the sending port and the receiving port to enter the low power consumption state, and both Enter the rate switching state from the low power consumption state; in the rate switching state, switch the current parameters of the sending port to match when the sending port transmits data according to the changed data transmission rate and, switch the current parameters of the receiving port to the parameters that the receiving port matches when receiving data according to the changed data transmission rate; after switching is completed, control the sending port and the receiving port The ports all enter the low power consumption state.

In a specific implementation, the method further includes: when the current parameter of the sending port is switched to the parameter matched by the sending port when sending data according to the changed data transmission rate, and the receiving When the current parameter of the port is switched to the parameter matched when the receiving port receives data according to the changed data transmission rate, the data transmission control code stream is received and the transmission link is controlled to be switched from the low power consumption state to a high-speed data transfer state or a low-speed data transfer state matching the transfer rate of the target data.

In a specific implementation, the method further includes: when a data transmission error is detected in the data transmission state, controlling both the sending port and the receiving port to enter a repair state; wherein, the data transmission The state includes a high-speed data transmission state and a low-speed data transmission state; in the repair state, data repair is performed on the sending port and the receiving port, and the parameters of the sending port are repaired until the sending port is in the data transmission state. state, and restore the parameters of the receiving port to the parameters when the receiving port is in the data transmission state; after completing the data restoration of the sending port and the receiving port, control the Both the transmitting port and the receiving port enter a low power consumption state or both enter the high-speed data transmission state again. The reliability of the transmission link is improved.

In a specific implementation, after the data transmission error is detected, and before both the sending port and the receiving port are controlled to enter the repair state, the method further includes: controlling the sending Both the port and the receiving port enter a low power consumption state. It is convenient to switch state.

In a third aspect, a chip is provided, the chip includes a first sending port and a first controller; the first controller is configured to control the first sending port to enter when a data transmission error is detected in a data transmission state to the repair state; send a repair control code stream that controls the first receiving port of the opposite end chip to enter the repair state; wherein, the data transmission state includes a high-speed data transmission state and a low-speed data transmission state; the first A controller is further configured to perform data repair on the first sending port in the repair state, and repair the parameters of the first sending port to the parameters when the first sending port is in the data transmission state; The first controller is further configured to control the first sending port to enter a low power consumption state or enter the high-speed data transmission state again after completing the data restoration on the first sending port; wherein, in the In the high-speed data transmission state, the data transmission rate is greater than or equal to 1Gbps. In the above solution, by setting the repair state, when the high-speed data transmission fails, the first sending port is repaired, which improves the reliability of the high-speed data transmission. In addition, during repair, only matching parameters corresponding to high-speed data transmission are repaired, which improves repair efficiency.

In a specific implementation, the first controller is further configured to control the first transmission after detecting the data transmission error and before controlling the first transmission port to enter the repair state The port enters a low power state. It is convenient to switch state.

In a specific implementation, the first controller is further configured to, after completing the data restoration and before controlling the first sending port to enter the low power consumption state, confirm that the A parameter of a sending port is a parameter when the first sending port is in the data transmission state. The reliability of the transmission link is improved.

In a specific implementation, the first controller is further configured to control the first sending port to enter a low power consumption state before the first sending port enters the high-speed data transmission state. It is convenient to switch state.

In a specific implementation, the chip further includes a second receiving port; the second receiving port is configured to receive the port information of the first receiving port sent by the second sending port of the opposite chip; The first controller is further configured to control the first sending port to establish a transmission link with the first receiving port of the opposite chip, and control the first sending port to send the port information of the first sending port to The first receiving port of the peer chip.

In a fourth aspect, a chip is provided, the chip includes a first receiving port and a second controller; the first receiving port is used to receive a repair control code stream sent by a first sending port of a peer chip; the first receiving port The second controller is configured to control the first receiving port to enter a repair state according to the repair control code stream; wherein, the repair control code stream is that the first controller of the opposite end chip detects data in the data transmission state When a transmission error occurs, a repair control code stream is generated for controlling the first receiving port to switch to a repair state; wherein, the data transmission state includes a high-speed data transmission state and a low-speed data transmission state; the second controller also In the repair state, data repair is performed on the first receiving port, and the parameters of the first receiving port are repaired to the parameters when the first receiving port is in the data transmission state; the second receiving port The controller is further configured to control the first receiving port to enter a low power consumption state or enter the high-speed data transmission state again after completing the data restoration of the first receiving port; wherein, in the high-speed data transmission state , the data transfer rate is greater than or equal to 1Gbps. The reliability of the transmission link is improved.

In a specific implementation, the second controller is further configured to control the first receiving port after detecting the data transmission error and before controlling the first receiving port to enter the repair state The port enters a low power state. It is convenient to switch state.

In a specific implementation, the second controller is further configured to, after completing the data restoration and before controlling the first receiving port to enter the low power consumption state, confirm that the A parameter of a receiving port is a parameter when the first receiving port is in the data transmission state. The reliability of the transmission link is improved.

In a specific implementation, the second controller is further configured to control the first receiving port to enter a low power consumption state before the first receiving port enters the high-speed data transmission state. It is convenient to switch state.

In a specific implementation, it further includes a second sending port; the second controller is further configured to control the first receiving port to establish a transmission link with the first sending port of the opposite chip, and control the The second sending port sends the port information of the first receiving port to the second receiving port of the opposite end chip; the first receiving port is also used to receive the data sent by the first sending port of the opposite end chip The port information of the first sending port.

A fifth aspect provides a chip, the chip includes a first sending port and a first controller, the first controller is configured to detect the current state of the first sending port before the first sending port enters a data transmission state parameters and determine whether the current parameters of the first sending port are consistent with the parameters matched by the first sending port when sending data according to the target data transmission rate; the first controller is also used for sending data at the first sending port When the current parameter is inconsistent with the parameter matched by the first sending port at the target data transmission rate, the first sending port is controlled to enter a rate switching state; the first controller is further configured to, in the rate switching state, Switching the current parameters of the first sending port to the parameters matched by the first sending port when sending data according to the target data transmission rate; the first controller is further configured to control the first sending port to send data to the opposite end The first receiving port of the chip sends a control code stream that controls the first receiving port to enter a rate switching state; the first controller is further configured to control the first sending port to enter a low power consumption state after switching is completed state. The reliability of the transmission link is improved.

In a specific implementation, the first controller is further configured to, after the current parameter of the first sending port is switched to the parameter matched by the first sending port when sending data according to the target data transmission rate , receiving a data transmission control code stream and controlling the first sending port to switch from the low power consumption state to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data; the first controller It is also used to control the first sending port to send the control to the first receiving port of the opposite chip to control the first receiving port to switch to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data. A code stream; wherein the high-speed data transmission rate is greater than the low-speed data transmission rate.

In a specific implementation, the first controller is further configured to control the first sending port to enter the low power consumption state when the data transmission rate changes during the data transmission process, and from The low power consumption state enters the rate switching state; the first controller is further configured to, in the rate switching state, control the current parameters of the first sending port to switch to the first sending port in accordance with: The parameter matched when the changed data transmission rate transmits data; the first controller is further configured to control the first sending port to send to the first receiving port of the opposite chip, and control the first receiving port to enter the The control code stream of the low power consumption state and the rate switching state; the first controller is further configured to control the first sending port to enter the low power consumption state after the switching is completed. The reliability of the transmission link is improved.

In a specific implementation, the first controller is further configured to send data according to the changed data transmission rate when the current parameter of the first sending port is switched to the first sending port sending data according to the changed data transmission rate When matching parameters, receive a data transmission control code stream and control the first sending port to switch from the low power consumption state to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data; the The first controller is further configured to control the first sending port to send to the first receiving port of the opposite chip and control the first receiving port to switch to a high-speed data transmission state or low-speed data that matches the transmission rate of the target data The control stream of the transmission state.

In a specific implementation, the first controller is further configured to control the first sending port to enter a repair state when a data transmission error is detected in the data transmission state; and send the control to the opposite end chip to the opposite end chip The repair control code stream in which the first receiving port enters the repair state; wherein, the data transmission state includes a high-speed data transmission state and a low-speed data transmission state; the first controller is further configured to, in the repair state, performing data restoration on the first sending port, and restoring the parameters of the first sending port to the parameters when the first sending port is in the data transmission state; the first controller is further configured to After the data of the first sending port is restored, the first sending port is controlled to enter a low power consumption state or enter the high-speed data transmission state again. The reliability of the transmission link is improved.

In a specific implementation, the first controller is further configured to control the first controller after detecting the data transmission error and before controlling the first sending port to enter the repair state The transmit port enters a low power state. It is convenient to switch state.

In a sixth aspect, a chip is provided, the chip includes a first receiving port and a second controller, and before the first receiving port enters a data transmission state, the first receiving port is used to receive the control station sent by the opposite end chip. The first receiving port enters the rate-switching state of the control code stream; the second controller is configured to control the first receiving port to enter the rate-switching state according to the control code stream; and according to the control code stream to control the The first receiving port enters a rate switching state; the second controller is further configured to switch the current parameters of the first receiving port in the rate switching state to the first receiving port sending according to the target data transmission rate and the second controller is further configured to control the first receiving port to enter a low power consumption state after switching is completed. The reliability of the transmission link is improved.

In a specific implementation, the second controller is further configured to, after the current parameter of the first receiving port is switched to the parameter matched by the first receiving port when sending data according to the target data transmission rate , controlling the first receiving port to receive a control code stream that controls the first receiving port to switch to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data, and controls the control code stream according to the control code stream The first receiving port is switched from the low power consumption state to a high-speed data transmission state or a low-speed data transmission state matching the transmission rate of the target data; wherein the high-speed data transmission rate is greater than the low-speed data transmission rate .

In a specific implementation, in the process of data transmission, when the data transmission rate changes, the first receiving port is configured to receive the data sent by the opposite end chip and control the first receiving port to enter a low power consumption state and a control code stream in a rate switching state; the second controller is configured to control the first receiving port to enter a low power consumption state and a control code stream in a rate switching state according to the control code stream; and control the first receiving port according to the control code stream A receiving port enters a low power consumption state, and enters a rate switching state after entering the low power consumption state; the second controller is further configured to control the current parameter of the first receiving port to switch to the rate switching state in the rate switching state parameters matched by the first receiving port when transmitting data according to the changed data transmission rate; the second controller is further configured to control the first receiving port to enter the low-power mode after switching is completed consumption status.

In a specific implementation, the second controller is further configured to, after the current parameter of the first receiving port is switched to the parameter matched by the first receiving port when sending data according to the target data transmission rate , controlling the first receiving port to receive a control code stream that controls the first receiving port to switch to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data, and controls the control code stream according to the control code stream The first receiving port is switched from the low power consumption state to a high-speed data transmission state or a low-speed data transmission state matching the transmission rate of the target data.

In a specific implementation, the second controller is further configured to control the first receiving port to enter a repair state according to the repair control code stream; wherein the repair control code stream is the opposite end When the first controller of the chip detects a data transmission error in the high-speed data transmission state, it generates a repair control code stream for controlling the first receiving port to switch to the repair state;

The second controller is further configured to perform data repair on the first receiving port in the repair state, and repair the parameters of the first receiving port to the parameters when the first receiving port is in a data transmission state ; Wherein, the data transmission state includes a high-speed data transmission state and a low-speed data transmission state;

The second controller is further configured to control the first receiving port to enter a low power consumption state or enter the high-speed data transmission state again after completing data restoration on the first receiving port.

In a specific implementation, the second controller is further configured to control the first receiving port after detecting the data transmission error and before controlling the first receiving port to enter the repair state The receive port enters a low power state.

In a seventh aspect, a communication system is provided, the communication system includes a first chip and a second chip; wherein the first chip is any one of the chips described in any one of the above; the second chip is a pair of the first chip A terminal chip; a transmission link is established between the first chip and the second chip. In the above solution, by setting the repair state, when the high-speed data transmission fails, the transmission link is repaired, which improves the reliability of the high-speed data transmission. In addition, when repairing, only matching parameters corresponding to high-speed data transmission are repaired, and there is no need to match the basic information of the two chips during handshake, which improves the repairing efficiency.

In an eighth aspect, a mobile terminal is provided, the mobile terminal includes a first chip and a second chip; wherein the first chip is the chip described in any one of the above; the second chip is a pair of the first chip A terminal chip; a transmission link is established between the first chip and the second chip. In the above solution, by setting the repair state, when the high-speed data transmission fails, the transmission link is repaired, which improves the reliability of the high-speed data transmission. In addition, when repairing, only matching parameters corresponding to high-speed data transmission are repaired, and there is no need to match the basic information of the two chips during handshake, which improves the repairing efficiency.

In a ninth aspect, an embodiment of the present application provides a signal processing module, where the signal processing module includes a processor, and is configured to implement the method described in the first aspect or the second aspect. The signal processing module may also include a memory for storing instructions and data. The memory is coupled to the processor, and when the processor executes the program instructions stored in the memory, the method described in the first aspect can be implemented. The signal processing module may also include a communication port, which is used for the apparatus to communicate with other devices. Exemplarily, the communication port may be a transceiver, circuit, bus, module or other type of communication port. It can be a network device or a terminal device, etc.

In a specific implementation solution, the signal processing module includes: a memory for storing program instructions; a processor for invoking the instructions stored in the memory, so that the apparatus executes the first aspect and the first aspect of the present application Any of the possible design methods.

In a tenth aspect, an embodiment of the present application further provides a computer-readable storage medium, including instructions, which, when executed on a computer, enable the computer to execute the first aspect of the present application and any possible design method of the first aspect , or the second aspect and any two possible design methods in the second aspect.

In an eleventh aspect, the embodiments of the present application further provide a computer program product, including instructions, which, when run on a computer, enable the computer to execute the first aspect of the present application and any possible design method in the first aspect , or the second aspect and any two possible design methods in the second aspect.

In addition, for the technical effects brought by any of the possible design methods in the ninth aspect to the eleventh aspect, reference may be made to the effects brought by different design methods in the method section, which will not be repeated here.

Description of drawings

FIG. 1 is a scenario in which the communication method provided by the embodiment of the present application may be applied in a terminal device;

FIG. 2 is a scenario in which the communication method provided by the embodiment of the present application may be applied in a storage device;

FIG. 3 shows a logical schematic diagram of various states of a transmission link provided by an embodiment of the present application;

FIG. 4 shows a working mode management process after the chip is powered on provided by an embodiment of the present application;

FIG. 5 shows a working mode management process under high-speed data transmission provided by an embodiment of the present application;

FIG. 6 shows a working mode management process under low-speed data transmission provided by an embodiment of the present application;

FIG. 7 shows a working mode management process under ultra-low power consumption provided by an embodiment of the present application;

FIG. 8 shows a communication system provided by the present application;

Fig. 9 shows the workflow of the port under the communication system architecture in the LINK-STARTUP state;

Figure 10 shows the workflow of the port in the SPEED-CHANGE state under the communication system architecture;

Figure 11 shows the workflow of the port in the RECOVERY state under the communication system architecture;

Figure 12 shows another communication system provided by the present application;

Figure 13 shows the workflow of the port in the LINK-STARTUP state under the communication system architecture;

Figure 14 shows the workflow of the port in the SPEED-CHANGE state under the communication system architecture;

Figure 15 shows the workflow of the port in the RECOVERY state under the communication system architecture;

FIG. 16 shows a structural block diagram of a signal processing module provided by an embodiment of the present application.

Detailed ways

The embodiments of the present application will be further described below with reference to the accompanying drawings.

First, it is explained that the communication method provided by the embodiment of the present application is a high-speed communication method, which is mainly applied to various transmission links in terminal services that require high-speed communication. Common scenarios include the processor-camera data communication transmission link of terminal products such as mobile phones and tablets, the processor-display data communication transmission link, and the data communication transmission link between storage devices.

Referring to FIG. 1 , FIG. 1 shows a scenario in which the communication method provided by the embodiment of the present application may be applied in a terminal device. The terminal device 200 includes a processor, a camera module, a display module, a radio frequency module, a storage module, and the like, all of which can be regarded as chips.

Transmission links

201, 202, 203, and 204 respectively represent transmission links between the processor and the camera module, the processor and the display module, the processor and the radio frequency module, and the processor and the storage module. The communication methods provided in the embodiments of the present application can be applied to the port working modes on both sides of the data transmission link such as 201 , 202 , 203 , and 204 for low power consumption management, so as to ensure stable and reliable data transmission in high-speed scenarios.

It should be understood that, in the embodiments of the present application, the main chip is also called the local chip, which refers to a chip used for sending data between two chips having a communication relationship. The slave chip is also called the peer chip, which refers to the chip used to receive data between two chips with a communication relationship. Generally speaking, each chip has the function of data sending and sending. When the chip is used to send data, we can call the chip as the main chip or the local chip. Correspondingly, it is located on the opposite end of the chip and used for The chip that receives the data can be called the slave chip or the peer chip. It can be seen from the above description that among the two chips with a communication relationship, one chip is not a fixed master chip, or a fixed slave chip. As for whether a specific chip is a master chip or a slave chip, It depends on whether it is sending data or receiving data. Exemplarily, taking the processor and the camera module as an example, when the processor sends data to the camera module, the processor is the master chip (the local chip), and the camera module is the slave chip (the opposite end chip). When the camera module sends data to the processor, the camera module is the master chip (the local chip), and the processor is the slave chip (the opposite end chip).

Referring to FIG. 2, FIG. 2 shows a scenario in which the communication method provided by the embodiment of the present application may be applied in a storage device. Data exchange is performed between the storage device 1 and the storage device 2 through a physical layer port, and the transmit port and the receive port between the two devices constitute a data transmission link 301 . The communication method provided by the present application ensures stable and reliable data transmission in high-speed scenarios by performing low power consumption management on the port working modes on both sides of the data transmission link such as 301 .

In order to facilitate understanding of several working states of the transmission link involved in the communication method provided by the embodiment of the present application, the scene of the local chip and the opposite chip shown in FIG. 1 is used for description. Wherein, when the local chip and the opposite end chip establish a transmission link, the transmission link is formed by the sending port of the local end chip, the receiving port of the opposite end chip and the link between them. It should be understood that both the local chip and the opposite chip include a protocol layer and a physical layer, wherein the protocol layer is used to send data or control instructions to the physical layer, and the physical layer sends and processes data according to the instructions of the protocol layer. The sending port of the local chip and the receiving port of the opposite chip are both physical layer ports.

The working mode management method for a high-speed data serial port provided by the embodiment of the present application is expressed in the form of a state machine. The state machine is shown in FIG. 3 . Each state in FIG. 3 corresponds to each working mode of the transmission link. The link includes the following working states: DISABLED state, PHY-INIT state, LINK-STARTUP state, LOW-POWER0 state, LOW-POWER1 state, TRANS0 state, TRANS1 state, RECOVERY state, and SPEED-CHANGE state. The functions of the transmission link in each state are defined in detail below. First, refer to Table 1, which shows the Chinese meanings corresponding to the English abbreviations of various states.

Table 1

It should be understood that in the various working modes of the above-mentioned transmission link, the sending port and the receiving port also correspond to the same working mode. The road is in a different working mode. The above working modes are described in detail below:

DISABLED status:

This state represents the state when the chip is powered on and reset. This state can be entered automatically after the chip is initially powered on, or can be entered in any state after being triggered by the trigger condition Trigger0.

During this state, the physical layer port disables transmit and receive operations and does not enter the PHY-INIT state until Trigger0 ends or fails.

PHY-INIT status:

This state represents the state of the port being initialized, which can be entered automatically after the DISABLED state ends, or can be entered after being triggered by the trigger condition Trigger1 in any state.

During this state, all transport link configurations and registers are restored to default values, and after the initialization of the transport link, the physical layer port transmit and receive operations are still disabled, keeping the physical layer in a very low power state, Wait for the trigger condition to enter LINK-STARTUP.

The trigger condition for entering LINK-STARTUP can come from the control of the upper-layer chip or from the control code stream on the transmission link.

LINK-STARTUP status:

This state represents the state of establishing a reliable connection between physical layer ports. In this state, the physical layer port allows transmit and receive operations. The physical layer port in this state needs to determine the state of the transmission link, establish a link with the physical layer port on the other end of the transmission link, and exchange basic information of the physical layer port.

The physical layer port in this state communicates at the lowest rate supported by the chip, and the operation performed at this rate is considered reliable. If the communication fails due to the timeout due to the chip synchronization problem, the connection with the peer chip will be stopped. , notify the upper layer and enter the PHY-INIT state.

After the physical layer port establishes a reliable connection, it is triggered by the upper layer control or the control code stream on the transmission link to enter the LOW-POWER0 state.

LOW-POWER0 state:

This state represents a low power state. The physical layer port in this state needs to save power without affecting the start-up time of data transfer. The physical layer port in this state does not perform parameter configuration, and only immediately enters the next state under the triggering condition of the upper layer control or the control code stream on the transmission link.

LOW-POWER1 state:

This state is an ultra-low power state. During this state, the physical layer port keeps the current configuration and register values of the chip unchanged, and shuts down specific circuit modules. The physical layer port in this state does not perform sending and receiving operations, and the corresponding circuit module is reopened to enter the LOW-POWER0 state under the triggering condition of the upper layer control or the control code stream on the transmission link.

TRANS0 state:

This state is the low-speed data transmission state of the physical layer port. The port in this state performs low-speed (less than 1Gbps) data transmission and can support different low-speed speed gears. The physical layer port in this state will enter the LOW-POWER0 state after the data transfer is completed.

TRANS1 state:

This state is the high-speed data transmission state of the physical layer port. In this state, the physical layer port performs high-speed and large-volume data transmission, and can support different high-speed speed gears. Specifically, the data transmission rate is greater than or equal to 1 Gbps.

The physical layer port in this state will enter the LOW-POWER0 state after the data transmission is completed, and will enter the RECOVERY state only when the upper layer control or the control code stream on the transmission link is triggered.

RECOVERY status:

This state represents the data recovery state of the physical layer port. When an error occurs in the data transmission link of the physical layer port during data transmission, the port should enter the RECOVERY state to repair the corresponding data transmission link.

The physical layer port in this state can take corresponding repair measures according to different transmission error conditions, and only perform data transmission related to the repair, that is, only repair the matching parameters corresponding to the data transmission state, and do not process the establishment of the transmission link handshake. time base configuration. After the configuration is completed, the physical layer port can send some handshake information to confirm that the transmission link is available again, and then enter the next state according to the upper layer control or the control code flow on the transmission link.

SPEED-CHANGE Status:

This state represents the physical layer port data transmission rate switching state. The physical layer port enters the SPEED-CHANGE state according to the instructions of the upper layer to change the rate configuration parameters of the port.

The physical layer port in this state only performs data transmission related to cutting speed. After the configuration is completed, the physical layer port needs to send some handshake information at the new rate to confirm that the transmission link is available again, and then trigger back to the LOW-POWER0 state according to the upper layer control or the control code flow on the transmission link.

Among the above DISABLED status, PHY-INIT status, LINK-STARTUP status, LOW-POWER0 status, LOW-POWER1 status, TRANS0 status, TRANS1 status, RECOVERY status, and SPEED-CHANGE status, the LOW-POWER0 status, TRANS1 status, and RECOVERY status are: The communication method provided by the embodiment of the present application mainly involves several states, and the other states are optional states of the transmission link. In practical application, the above several optional states can be set as required.

In order to facilitate understanding of the methods provided by the embodiments of the present application, the following describes the communication methods provided by the embodiments of the present application with reference to the specific drawings. The communication methods provided by the embodiments of the present application are used to switch several working states of the above-mentioned transmission link. . It should be understood that the working state of the transmission link corresponds to the working state of the sending port of the end chip and the receiving port of the opposite end chip. When the transmission link has the above several working states, the corresponding sending port and the receiving port also have the above several working states.

First, it will be explained that the interfaces in the flowcharts shown in FIG. 4 to FIG. 7 refer to the sending port and/or the receiving port of the end chip and the opposite end chip.

Referring to FIG. 4, a transmission link is established between the first chip and the second chip, and port information exchange is performed. Port information exchange means that the first chip sends the port information of the sending port to the second chip, and the second chip will receive The port information of the port is sent to the first chip; after the port information exchange is completed, both the sending port and the receiving port enter a low power consumption state for the first time.

Exemplarily, FIG. 4 shows the working mode management flow after the chip is powered on. The power-on reset signal of the chip can be regarded as a kind of trigger condition Trigger0. First, the first chip and the second chip shake hands to establish a transmission link; and exchange basic information of ports at both ends of the transmission link. In the embodiments of the present application, the first chip is taken as an end chip, and the second chip is an opposite end chip as an example for description. When the first chip is the end chip and the second chip is the opposite end chip, the first chip has a sending port, and the second chip has a receiving port. When a transmission link is established, the sending port and the receiving port are the two ends of the transmission link. port.

After the first chip is powered on and reset, the sending port of the first chip enters the DISABLED state from any previous state. After the power-on reset signal ends or fails, the transmitting port automatically enters the PHY-INIT state and performs initialization operations. After the initialization operation is completed, the transmit port waits for the trigger condition to enter LINK-STARTUP in a very low power state. The sending port enters the LINK-STARTUP state after receiving the trigger condition, tries to establish a reliable link with the receiving port of the second chip, and the first chip transmits the basic information (such as capability information and version information) of the sending port to the second chip, and The second chip transmits the basic information of the receiving port (such as capability information and version information) to the first chip.

If the link establishment (establishing the transmission link) fails, the sending port returns to the PHY-INIT state and re-initializes. If after the initialization is completed, the sending port and the receiving port also complete the reliable link establishment, then enter the LOW-POWER0 state under the trigger of the upper layer control or the control code stream on the transmission link, and wait for the trigger condition to enter the next state. The above LOW-POWER0 state, as an intermediate state, after the sending port and the receiving port complete any data transmission work, the first chip can control the transmission link to enter the LOW-POWER0 state and wait for the next state trigger condition to reduce energy consumption .

Referring to FIG. 5, FIG. 5 shows a working mode management flow under high-speed data transmission. The transmission link is in a LOW-POWER0 state before high-speed data transmission, that is, before the sending port and the receiving port enter the high-speed data transmission state, they are in a low-power state.

When performing high-speed data transmission, the transmission link can be triggered to enter a high-speed data transmission state through a high-speed data control code stream to perform high-speed data transmission. Specifically, the controller or the protocol layer of the first chip triggers both the sending port and the receiving port to enter the high-speed data transmission state through the high-speed data control code stream.

When a high-speed data transmission error is detected, the transmission link can be controlled to enter a repair state. For example, if an error occurs during data transmission, the upper layer control or the control code stream on the transmission link can trigger the transmission link to exit the TRANS1 state and directly enter the RECOVERY state, and the transmission link is repaired in the RECOVERY state.

In the above process, the protocol layer of the first chip controls both the sending port and the receiving port to enter the repair state; when a high-speed data transmission error is detected, the controller or the protocol layer of the first chip controls the sending port to enter the repair state, and Sending the repair control code stream to the second chip, so that the protocol layer or the controller of the second chip controls the receiving port to enter the repair state according to the repair control code stream, and the protocol layer of the first chip controls the receiving port to enter the repair state. It refers to the above-mentioned control of the second chip through the repair control code flow, so that the receiving port enters the repair state, so that both the sending port and the receiving port enter the repair state.

After the data transmission error is detected, and before both the sending port and the receiving port are controlled to enter the repair state, both the sending port and the receiving port are controlled to enter a low power consumption state. Specifically, it refers to controlling both the sending port and the receiving port to enter the restoration state from the low power consumption state.

In the repair state, the controller or the protocol layer of the first chip performs data repair (reset and repair) on the sending port and the receiving port, and restores the parameters of the sending port to the parameters when the sending port is in a high-speed data transmission state, And, the parameters of the receiving port are repaired to the parameters when the receiving port is in a high-speed data transmission state. In this state, the sending port and the receiving port can take corresponding repair measures according to different transmission error conditions, that is, only repair the corresponding matching parameters in the state of data transmission, and do not involve the basic configuration when the transmission link handshake is established. Taking reset as an example, the controller or the protocol layer of the first chip resets the parameters of the sending port to the parameters matching the high-speed data transmission state. Similarly, the protocol layer or controller of the second chip resets the parameters of the receiving port to the parameters matching the high-speed data transmission state according to the relevant code stream sent by the first chip.

As an optional solution, after the transmission link is repaired, a handshake process is added. Through the handshake process, it is confirmed that the parameters of the repaired sending port are the parameters when the sending port is in a high-speed data transmission state and the parameters of the receiving port are the receiving port. Parameters in the state of high-speed data transmission to ensure the robustness of the transmission link.

If the data transmission is completed, the protocol layer or the controller of the first chip controls the transmission link to exit the TRANS1 state, enter the LOW-POWER0 state, and wait for a trigger condition for entering the next state.

As an optional solution, before entering the TRANS1 state, that is, before the sending port and the receiving port enter the data transmission state, the protocol layer or controller of the first chip detects whether the transmission rate of the transmission link is consistent with the transmission rate of the target data;

Exemplarily, detecting the current parameters of the sending port and the current parameters of the receiving port, and judging whether the current parameters of the sending port are consistent with the parameters matched by the sending port when sending data according to the target data transmission rate, and judging the current parameters of the receiving port Whether it is consistent with the parameters matched by the receiving port when receiving data according to the target data transmission rate, that is, it is judged whether the current parameters of the ports at both ends of the transmission link are consistent with the parameters matched when the ports at both ends of the transmission link send and receive data according to the target data transmission rate. .

When the current parameters of the sending port and the receiving port are inconsistent with their matching parameters at the target data transmission rate, the protocol layer or controller of the first chip controls the sending port and the receiving port to enter a rate switching state. During specific control, the protocol layer or the controller of the first chip controls the sending port to enter the low power consumption state, and after entering the low power consumption state, enters the rate switching state. And in the above-mentioned switching process, the protocol layer or controller of the first chip controls the sending port to send the relevant switching control code stream to the receiving port of the second chip, and the protocol layer or controller of the second chip passes the received relevant control code. The flow control receiving port correspondingly enters the low power consumption state, and enters the rate switching state after entering the low power consumption state.

In the rate switching state, the protocol layer or controller of the first chip switches the current parameters of the sending port to the parameters matched by the sending port when sending data according to the target data transmission rate. At the same time, the protocol layer or controller of the second chip will receive The parameters of the port are switched to the parameters matched by the receiving port when receiving data according to the target data transmission rate; and after the switching is completed, both the transmitting port and the receiving port enter a low power consumption state.

In addition, the current parameters of the first sending port are consistent with the parameters that the first sending port matches when sending data according to the target data transmission rate, and the current parameters of the receiving port are the same as the parameters that the receiving port matches when receiving data according to the target data receiving rate. When they are consistent, the control transmission link is switched from a low power consumption state to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data.

In the above process, the sending port needs to determine whether the data transmission rate supported by the current transmission link configuration is consistent with the transmission rate of the target data. If inconsistent, the sending port needs to enter the SPEED-CHANGE state, and reconfigure the parameters of the transmission link to meet the transmission rate requirements of the target data. If the data transmission rate supported by the current transmission link configuration is consistent with the transmission rate of the target data, the sending port directly enters the TRANS1 state under the trigger of the trigger condition (high-speed data control code stream) to perform high-speed data transmission. Similarly, the receiving port also performs corresponding operations.

In addition, in the process of data transmission, when the data transmission rate changes, after the control transmission link enters the low power consumption state, it switches to the rate switching state; the parameters of the ports at both ends of the transmission link are switched to the two ends of the transmission link. The parameters matched when the port performs data transmission according to the changed data transmission rate; and after the switching is completed, both the sending port and the receiving port enter a low power consumption state.

Specifically, if the required transmission rate of the transmitted data is different from the transmission rate on the current transmission link, the data transmission rate of the transmission link can be changed. For example, the sending port and the receiving port can be triggered to exit the TRANS1 state and enter the LOW-POWER0 state through the upper layer control or the control code stream on the transmission link, and then trigger the sending port and the receiving port to enter the SPEED-CHANGE state; in the SPEED-CHANGE state, to The data parameters of the sending port and the receiving port are configured, that is, the parameters of the ports at both ends of the transmission link are switched to the parameters matching the transmission rate corresponding to the data after the changed rate, so as to adapt to the changed rate requirement. The above-mentioned transmission rate switching during the data transmission process is the same as the transmission rate switching before entering the high-speed data transmission state, and details are not described herein again.

FIG. 6 shows the working mode management flow under low-speed data transmission. The low-speed data control code stream can trigger the transmission link to enter the low-speed data transmission state, and perform low-speed data transmission; after completing the low-speed data transmission, control the transmission link to enter the low-speed data transmission state.

The transmission link is in the LOW-POWER0 state before low-speed data transmission. Before entering the TRANS0 state, the sending port and the receiving port need to determine whether the data transmission rate supported by the current transmission link configuration is consistent with the target data transmission rate. If inconsistent, the transmission link needs to enter the SPEED-CHANGE state, and reconfigure the transmission link parameters to meet the transmission rate requirements of the target data. If the data transmission rate supported by the current transmission link configuration is consistent with the transmission rate of the target data, the sending port and the receiving port directly enter the TRANS0 state under the trigger condition to perform low-speed data transmission. The process is similar to the related description in FIG. 5 above, and will not be repeated here.

In the process of data transmission, if you need to change the current transmission rate, you can change the data transmission rate of the transmission link, and trigger the sending port and the receiving port to exit the TRANS0 state and enter the LOW-POWER0 state through the upper layer control or the control code stream on the transmission link. Then trigger the sending port and the receiving port to enter the SPEED-CHANGE state; in the SPEED-CHANGE state, configure the data parameters of the sending port and the receiving port, that is, switch the parameters of the ports at both ends of the transmission link to match the data corresponding to the changed rate. The parameters of the transmission rate, so as to adapt to the changed rate requirements. The process is similar to the related description in FIG. 5 above, and will not be repeated here.

During data transmission, if a data transmission error occurs, the transmission link can be controlled to enter a repair state. For example, if an error occurs during data transmission, the upper layer control or the control code stream on the transmission link can trigger the transmission link to exit the TRANS0 state and directly enter the RECOVERY state, and the transmission link is repaired in the RECOVERY state. In the specific repair process, Reference may be made to the related description in FIG. 5 , which will not be repeated here.

If the data transmission is completed, the sending port and the receiving port exit the TRANS0 state, enter the LOW-POWER0 state, and wait for the trigger condition to enter the next state.

FIG. 7 shows the working mode management flow under ultra-low power consumption. When data transmission is not performed, the transmission link enters an ultra-low power consumption state from a low power consumption state.

Specifically, the sending port and the receiving port are in the LOW-POWER0 state before entering the LOW-POWER1 state, and the sending port and the receiving port are triggered to exit the LOW-POWER0 state and enter the LOW-POWER1 state through the upper layer control or the control code stream on the transmission link. When the sending port and the receiving port need to exit the LOW-POWER1 state, the sending port is triggered to exit the LOW-POWER1 state and enter the LOW-POWER0 state through the upper layer control or the control code stream on the transmission link.

In order to facilitate the understanding of the above-mentioned communication methods provided by the embodiments of the present application, the above-mentioned several working states are described with reference to the communication system shown in FIG. 8 .

The communication system shown in FIG. 8 includes a first chip 100 and a second chip 200, wherein both the first chip 100 and the second chip 200 are opposite chips of another chip, and the first chip 100 and the second chip 200 have similar composition structure.

Taking the first chip 100 as an example, the first chip 100 includes a protocol layer and a physical layer structure. Among them, the protocol layer is responsible for sending upper-layer data information and control information, receiving data information and control information from other chips of the same level or upper-layer chips, and can control the physical layer. The physical layer of the first chip 100 includes a sending module, a receiving module and a first controller 105 . The sending module is used to send data, the receiving module is used to receive data, and the first controller 105 is used to control the sending module and the receiving module.

The sending module includes a first data processing module 102 and a first sending port 101. The first data processing module 102 performs operations such as encoding, scrambling, and serial processing on the data information and control information from the protocol layer to process the data information into data. packet, and then send the data packet out through the first sending port 101 .

The receiving module includes a second data processing module 104 and a second receiving port 103, the second receiving port 103 receives data packets from the transmission link, and the second data processing module 104 performs decoding, descrambling, and decoding on the data packets. Serial processing and other operations, and then transmit the data information and control information to the protocol layer, or indirectly control the first controller 105 according to the control information.

The first controller 105 is directly controlled by the protocol layer, and can also be indirectly controlled from the receiving module, so as to manage the sending module and the receiving module. The first controller 105 can manage the sending and receiving of data by managing the sending module and the receiving module.

The structure of the second chip 200 is similar to that of the first chip 100 . The second sending port 201 , the third data processing module 202 , the first receiving port 203 , the fourth data processing module 204 and the second The controller 205 may refer to the related description of the same type of structure in the first chip 100 . The second sending port 201 of the second chip 200 is connected with the second receiving port 103 of the first chip 100 to form a transmission link, and the first receiving port 203 of the second chip 200 and the first sending port 101 of the first chip 100 form a transmission link link. When establishing a transmission link, the above two transmission links are established synchronously. And when the first sending port 101 and the first receiving port 203 establish a transmission link, the port information of the first receiving port can be sent to the second receiving port 103 through the second sending port 201, so as to realize the connection between the first receiving port 203 and the second receiving port 103. A port information exchange of the sending port 101. Similarly, when the second sending port 201 establishes a transmission link with the second receiving port 103 , the port information of the second receiving port 103 may be sent to the first receiving port 203 through the first sending port 101 .

The communication system provided by the embodiment of the present application realizes the management of the transmission link of the communication system by managing the port working mode state machine. The transmission link between the first chip 100 and the second chip 200 of the communication system can perform power-on operation, high-speed data transmission operation, low-speed data transmission operation and ultra-low power consumption operation according to the above-described working states.

In the communication system, the flow of the LINK-STARTUP state, the SPEED-CHANGE state and the RECOVERY state of the first chip 100 is as follows:

First of all, it should be noted that the sending port hereinafter refers to the first sending port 101 in the first chip 100 , and the receiving port refers to the first receiving port 203 of the second chip 200 .

FIG. 9 shows the workflow of the port in the LINK-STARTUP state under the communication system architecture. The first chip and the second chip shake hands, establish a transmission link, and exchange basic information of ports at both ends of the transmission link (the first sending port and the first receiving port, and the second sending port and the first receiving port).

Specifically, after the initialization of the first sending port is completed, the protocol layer of the first chip controls the first sending port to enter the LINK-STARTUP state, and the first sending port sends the LINK-STARTUP control code stream on the transmission link to the first receiving port, The LINK-STARTUP control code stream is used as a condition for triggering the first receiving port to enter the LINK-STARTUP. The second controller of the second chip controls the first receiving port to enter the LINK-STARTUP state according to the received LINK-STARTUP control code stream. Similarly, the second sending port of the second chip sends the LINK-STARTUP control code stream to the second receiving port of the first chip, and the first controller of the first chip controls the second receiving port according to the received LINK-STARTUP control code stream. Enter the LINK-STARTUP state.

When the first sending port enters the LINK-STARTUP state, the first sending port attempts to establish a link with the first receiving port and confirms the status of the transmission link by sending a link-building related code stream on the transmission link; Send a link establishment related code stream on the transmission link, try to establish a link with the second receiving port and confirm the status of the transmission link. The link establishment related code stream includes the judgment information for establishing a reliable link of the transmission link and the basic information that the ports need to exchange.

The first controller needs to determine whether a reliable link is established with the opposite port according to the link establishment related code streams sent and received by the first sending port and the second receiving port, and refresh the basic information exchanged in time. If it is judged that the port has not established a reliable link, it will notify the protocol layer that the link building fails and return to the PHY-INIT state; if it is judged that the first sending port and the second receiving port have established a reliable link with the opposite port, it means that the link has been established successfully and LINK-STARTUP The state ends, waiting for the trigger condition to enter the next state. Similarly, the second controller also needs to perform the same operations as the first controller, and details are not repeated here.

After the transmission link is established, the transmission link may enter a low power consumption state through a trigger condition, and wait for the next state trigger condition.

FIG. 10 shows the workflow of the port in the SPEED-CHANGE state under the communication system architecture. The first sending port and the first receiving port are in the LOW-POWER0 state before entering the SPEED-CHANGE state. After the protocol layer of the first chip sends the SPEED-CHANGE request, the first sending port enters the SPEED-CHANGE state and is in the first sending port. The SPEED-CHANGE control code stream is sent on the transmission link with the first receiving port (that is, the control code stream entering the rate switching state is sent to the first receiving port), and the SPEED-CHANGE control code stream is used as the physical The condition for the layer port (the first receiving port) to enter the SPEED-CHANGE state. The second controller controls the first receiving port to enter the SPEED-CHANGE state according to the SPEED-CHANGE control code stream received by the first receiving port.

After entering the SPEED-CHANGE state, the first sending port changes the current configuration parameters to the configuration parameters matching the target rate according to the request of the protocol layer or the transmission rate (target rate) of the target data in the SPEED-CHANGE control code stream. After the configuration of the parameters of the first sending port is completed, the speed-cutting related code stream will be sent to the first receiving port at the target rate to try to communicate at the target rate. The rate-cutting related code stream includes but is not limited to the judgment information of the link rate-cutting success.

After the data transmission rate change is completed and the ports of the transmission link are matched, a code stream is sent to confirm the matching parameters of the transmission link and the target data. Taking the first chip as an example, the first sending port and the second receiving port need to determine whether the port successfully communicates with the first receiving port and the second sending port at the new rate according to the rate-cutting related code streams sent and received. If it is judged that the port fails to communicate, it will notify the protocol layer that the speed cut fails and return to the LOW-POWER0 state; if it is judged that the communication can be performed at the transmission rate of the target data, it means that the speed cut is successful, the SPEED-CHANGE state is over, and it is waiting to enter the next state. Triggering conditions. It can be seen from the above description that a handshake process is added after the parameter configuration of the data transmission link is changed, and a preliminary judgment is made on the accuracy of the data transmission at the cutting speed, so as to improve the robustness of the transmission link.

The above SPEED-CHANGE state is applied in two scenarios. One state is: before data transmission, before entering the low-speed data transmission state or the high-speed data transmission state as shown in FIG. 5 and FIG. 6 , the parameters of the ports at both ends of the transmission link are modified.

Exemplarily, before entering the SPEED-CHANGE state, the protocol layer of the first chip or the first controller detects the current parameters of the first sending port, and determines that the current parameters of the first sending port and the first sending port are in accordance with the target data. Whether the parameters matched when sending data at the transmission rate are consistent. At the same time, the protocol layer of the second chip or the second controller detects the current parameters of the second receiving port, and determines whether the current parameters of the second receiving port are consistent with the parameters matched by the second receiving port when receiving data according to the target data transmission rate, That is, it is judged whether the current parameters of the ports at both ends of the transmission link are consistent with the parameters matched when the ports at both ends of the transmission link send and receive data according to the target data transmission rate.

When the current parameters of the first sending port and the first receiving port are inconsistent with their matching parameters at the target data transmission rate, the protocol layer of the first chip or the first controller controls the first sending port to enter the SPEED-CHANGE state. During specific control, the protocol layer of the first chip or the first controller controls the first sending port to enter the low power consumption state, and after entering the low power consumption state, controls the first sending port to enter the SPEED-CHANGE state. And in the above switching process, the protocol layer or the first controller of the first chip controls the first sending port to send the relevant switching control code stream to the first receiving port of the second chip, and the protocol layer or the second controller of the second chip sends the relevant switching control code stream. The controller controls the first receiving port to correspondingly enter the low power consumption state through the received related control code stream, and enters the SPEED-CHANGE state after entering the low power consumption state. Similarly, the second receiving port of the first chip and the second sending port of the second chip also perform the above operations.

In the SPEED-CHANGE state, in the SPEED-CHANGE state, according to the flow of the example in FIG. 10, the protocol layer of the first chip or the first controller switches the current parameters of the first sending port to the first sending port and transmits data according to the target data The parameter to match when sending data at the rate. At the same time, the protocol layer of the second chip or the second controller switches the parameters of the first receiving port to the parameters matched by the first receiving port when receiving data according to the target data transmission rate; and after the switching is completed, the first sending port and The first receiving ports all enter into a low power consumption state. And after the matching is completed, it enters a low power consumption state, and waits to enter a high-speed data transmission state or a low-speed data transmission state corresponding to the target data transmission. In addition, after the port matching of the transmission link is completed, a code stream is sent to confirm the matching parameters corresponding to the transmission link and the target data, so as to improve the robustness of the transmission link.

In addition, the current parameters of the first sending port are consistent with the parameters that the first sending port matches when sending data according to the target data transmission rate, and the current parameters of the first receiving port and the first receiving port are receiving data according to the target data receiving rate. When the matched parameters are consistent, the first controller or the protocol layer of the first chip controls the first sending port to switch from a low power consumption state to a high-speed data transmission state or a low-speed data transmission state matching the transmission rate of the target data. The second controller or protocol layer of the second chip controls the first receiving port to switch from a low power consumption state to a high-speed data transmission state or a low-speed data transmission state matching the transmission rate of the target data. That is, the control transmission link is switched from a low power consumption state to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data.

The other involves the SPEED-CHANGE state that the transmission link is in data transmission, and when the data transmission rate changes, the transmission rate needs to be switched. For example, in the case of low-speed data transmission or high-speed data transmission, when the data transmission rate is changed, the transmission rate of the transmission link needs to be adjusted to the transmission rate corresponding to the changed rate data. Specifically, the protocol layer of the first chip or the first controller controls the first sending port to enter the SPEED-CHANGE state. During specific control, the protocol layer of the first chip or the first controller controls the first sending port to enter the low power consumption state, and after entering the low power consumption state, controls the first sending port to enter the SPEED-CHANGE state. And in the above switching process, the protocol layer or the first controller of the first chip controls the first sending port to send the relevant switching control code stream to the first receiving port of the second chip, and the protocol layer or the second controller of the second chip sends the relevant switching control code stream. The controller controls the first receiving port to correspondingly enter the low power consumption state through the received related control code stream, and enters the SPEED-CHANGE state after entering the low power consumption state. Similarly, the first receiving port of the first chip and the second sending port of the second chip also perform the above operations.

Switch to SPEED-CHANGE state. In the SPEED-CHANGE state, according to the flow shown in Figure 10 above, the parameters of the ports at both ends of the transmission link are switched to parameters that match the transmission rate of the target data; and after the matching is completed, it enters the low-power state, waiting for the target data to enter. The transmission corresponds to the high-speed data transmission state or the low-speed data transmission state. In addition, after the port matching of the transmission link is completed, a code stream is sent to confirm the matching parameters corresponding to the transmission link and the target data, so as to improve the robustness of the transmission link.

FIG. 11 shows the workflow of the port in the RECOVERY state under the communication system architecture. After both the first sending port and the first receiving port are in a low power consumption state and receive the data transmission control code stream, both the first sending port and the first receiving port enter the data transmission state for data transmission, and the data transmission control code stream is A high-speed data control code stream or a low-speed data control code stream, wherein high speed refers to a data transmission rate of the order of Gbps, and low speed refers to a data transmission rate of Mbps. When the data transmission control code stream is a high-speed data transmission control code stream, both the first sending port and the first receiving port enter a high-speed data transmission state to perform high-speed data transmission. During high-speed data transfer, data transfer errors may occur. When data transmission errors occur, the transmission link needs to be repaired. The specific repair process is as follows:

If an error occurs in the data transmission process, the control stream on the protocol layer of the first chip can trigger the transmission link to exit the TRANS1 state and directly enter the RECOVERY state, and the transmission link is repaired in the RECOVERY state.

In the above process, when a high-speed data transmission error is detected, the first controller or the protocol layer of the first chip controls the first sending port to enter the repair state, and sends the repair control code stream (RECOVER control code stream) to the second chip. ), so that the protocol layer of the second chip or the second controller controls the first receiving port to enter the repair state according to the repair control code flow. In this way, both the first sending port and the first receiving port enter the repair state.

After entering the RECOVERY state, the first receiving port sends a repair related code stream according to the type of error occurred in the data transmission link described in the RECOVERY control code stream. The repair-related code stream may include, but is not limited to, the receiver bit synchronization code stream, the receiver equalization training code stream, and the judging information that the transmission link is repaired successfully.

In the RECOVERY state, the first controller or protocol layer of the first chip performs data recovery (reset and repair) on the first sending port, and the second controller or protocol layer of the second chip performs data recovery on the first receiving port The modification is to restore the parameters of the first receiving port to the parameters when the first receiving port is in a high-speed data transmission state. In this state, the first sending port and the first receiving port can take corresponding repair measures according to different transmission error conditions, that is, only repair the corresponding matching parameters in the state of data transmission, not involving the establishment of the transmission link handshake. Basic configuration. Taking reset as an example, the controller or the protocol layer of the first chip resets the parameters of the sending port to the parameters matching the high-speed data transmission state. Similarly, the protocol layer or controller of the second chip resets the parameters of the receiving port to the parameters matching the high-speed data transmission state according to the relevant code stream sent by the first chip.

After the repair of the transmission link is completed, confirm that the parameters of the ports at both ends of the repaired transmission link are the matching parameters when the high-speed data transmission state is realized. The sending port can judge whether the port is repaired successfully according to the repair-related code streams sent and received. If it is judged that the sending port is not repaired successfully, it will notify the protocol layer that the repair fails and return to the LOW-POWER0 state; if it is judged that the port is repaired successfully, the RECOVERY state ends, waiting for the trigger condition to enter the next state. It can be seen from the above description that a handshake process is added after the parameter configuration of the data transmission link is changed, and a preliminary judgment is made on the accuracy of the repaired data transmission to improve the robustness of the transmission link.

After completing the repair of the transmission link, the transmission link is controlled to enter a low power consumption state to wait for the next trigger condition.

The communication method provided by the embodiment of the present application further includes the TRANS1 state, and for details, reference may be made to the related description in FIG. 5 . After the transmission link completes high-speed data transmission, the transmission link is controlled to enter a low power consumption state and wait for the next state trigger condition.

In addition, for the TRANS1 state, the low-speed data control stream can trigger the transmission link to enter the low-speed data transmission state, and perform low-speed data transmission; after completing the low-speed data transmission, control the transmission link to enter the low-power state.

For the LOW-POWER1 state, when data transmission is not performed, the transmission link enters the ultra-low power consumption state from the low power consumption state.

It can be seen from the above description that no matter what the working state of the transmission link is, after completion, it jumps into the low-power state, and the low-power state improves the interoperability between the states of the state machine and reasonably arranges the transmission link The configuration process makes the transition between any different states only need to jump two times at most.

The communication method in this embodiment of the present application may include only the workflow shown in FIG. 10 , or only the workflow shown in FIG. 11 , or may also include a combination of the workflows shown in FIG. 10 and FIG. 11 . .

The embodiment of the present application further provides a chip, and the chip can be the above-mentioned first chip and second chip. For details, reference may be made to the first chip or the second chip in the communication system shown in FIG. 8 .

When the chip is the first chip 100 and the first chip 100 mainly implements the workflow shown in FIG. 11 , the first chip 100 includes a first sending port 101 and a first controller 105 ; the first controller 105 is used for When a data transmission error is detected in the high-speed data transmission state, the first transmission port 101 is controlled to enter the repair state; Repair the control code stream; the first controller 105 is further configured to perform data repair on the first sending port 101 in the repair state, and repair the parameters of the first sending port 101 to the parameters when the first sending port 101 is in the high-speed data transmission state ; The first controller 105 is further configured to control the first transmission port 101 to enter a low power consumption state or enter a high-speed data transmission state again after completing the data restoration of the first transmission port 101; wherein, in the high-speed data transmission state , the data transfer rate is greater than or equal to 1Gbps. In a specific implementation, the first controller 105 is further configured to control the first sending port 101 to enter a low power consumption state after detecting a data transmission error and before controlling the first sending port 101 to enter the repair state . It is convenient to switch state.

In addition, the first controller 105 is further configured to control the first sending port 101 to enter the low power consumption state before the first sending port 101 enters the high-speed data transmission state. After completing the data restoration and before controlling the first sending port 101 to enter a low power consumption state, confirm that the parameters of the first sending port 101 after restoration are the parameters when the first sending port 101 is in a high-speed data transmission state. The reliability of the transmission link is improved.

When establishing a transmission link, the first chip 100 further includes a second receiving port 103; the second receiving port 103 is used to receive the port information of the first receiving port 203 sent by the second sending port 201 of the opposite chip; the first control The device 105 is further configured to control the first sending port 101 to establish a transmission link with the first receiving port 203 of the opposite chip, and control the first sending port 101 to send the port information of the first sending port 101 to the first receiving port 203 of the opposite chip. Receive port 203.

When the chip is the second chip 200 , the second chip 200 includes a first receiving port 203 and a second controller 205 ; the first receiving port 203 is used to receive the transmission from the first sending port 103 of the opposite chip (the first chip 100 ) The second controller 205 is used to control the first receiving port 203 to enter the repair state according to the repair control code stream; wherein, the repair control code stream is that the first controller 105 of the opposite end chip is in a high-speed data transmission state When a data transmission error is detected, a repair control code stream is generated for controlling the first receiving port 203 to switch to the repair state; the second controller 205 is also used to perform data repair on the first receiving port 203 in the repair state, Restoring the parameters of the first receiving port 203 to the parameters when the first receiving port 203 is in a high-speed data transmission state; the second controller 205 is further configured to control the first receiving port after completing the data restoration of the first receiving port 203 203 Enter into a low power consumption state or enter into a high-speed data transmission state again; wherein, in the high-speed data transmission state, the data transmission rate is greater than or equal to 1 Gbps. For details, please refer to the description in FIG. 11 .

In addition, the second controller 205 is further configured to control the first receiving port 203 to enter a low power consumption state before the first receiving port 203 enters a high-speed data transmission state. In addition, after the data transmission error is detected and before the first receiving port 203 is controlled to enter the repair state, the first receiving port 203 is controlled to enter the low power consumption state. The second controller 205 is further configured to confirm that the parameter of the first receiving port 203 after the repair is that the first receiving port 203 is in a high-speed data transmission state after completing the data repair and before controlling the first receiving port 203 to enter the low power consumption state time parameters. The reliability of the transmission link is improved. For details, please refer to the description in FIG. 11 .

When establishing a transmission link, the second chip 200 further includes a second sending port 201; the second controller 205 is further configured to control the first receiving port 203 to establish a transmission link with the first sending port 103 of the opposite chip, and control the The second sending port 201 sends the port information of the first receiving port 203 to the second receiving port 103 of the opposite chip; the first receiving port 203 is also used to receive the first sending port sent by the first sending port 103 of the opposite chip 103 port information. For details, please refer to the description in FIG. 11 .

When the chip is used to implement the work flow shown in FIG. 10 and FIG. 11 , when the chip is the first chip, the first chip includes a first sending port 101 and a first controller 105 , and the first controller 105 is used for Before the sending port 101 enters the data transmission state, detect the current parameters of the first sending port 101 and determine whether the current parameters of the first sending port 101 are consistent with the parameters matched when the first sending port 101 sends data according to the target data transmission rate; The first controller 105 is further configured to control the first sending port 101 to enter the rate switching state when the current parameters of the first sending port 101 are inconsistent with the parameters matched by the first sending port 101 at the target data transmission rate; the first controller 105 is also used to switch the current parameters of the first sending port 101 to the parameters matched when the first sending port 101 sends data according to the target data transmission rate in the rate switching state; the first controller 105 is also used to control the first sending The port 101 sends a control code stream that controls the first receiving port 203 to enter the rate switching state to the first receiving port 203 of the opposite chip; the first controller 105 is also used to control the first sending port 101 to enter the rate switching state after the switching is completed Low power state. For details, refer to the step flow shown in FIG. 10 .

The first controller 105 is further configured to receive the data transmission control code stream and control the first transmission after the current parameters of the first transmission port 101 are switched to the parameters matched when the first transmission port 101 transmits data according to the target data transmission rate. The port 101 is switched from a low power consumption state to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data; the first controller 105 is further configured to control the first sending port 101 to the first receiving port of the opposite chip 203 sends a control code stream that controls the first receiving port 203 to switch to a high-speed data transmission state or a low-speed data transmission state matching the transmission rate of the target data; wherein the high-speed data transmission rate is greater than the low-speed data transmission rate. In addition, the first controller 105 is further configured to control the first sending port 101 to enter the low power consumption state and enter the rate switching state from the low power consumption state when the data transmission rate changes during the data transmission process; A controller 105 is further configured to control the current parameters of the first sending port 101 to switch to the parameters matched when the first sending port 101 transmits data according to the changed data transmission rate in the rate switching state; the first controller 105 also uses To control the first sending port 101 to send a control code stream for controlling the first receiving port 203 to enter the low power consumption state and the rate switching state to the first receiving port 203 of the opposite chip; the first controller 105 is also used to complete the switching Then, the first sending port 101 is controlled to enter a low power consumption state. And the first controller 105 is further configured to receive the data transmission control code stream and control the data transmission control code stream when the current parameters of the first transmission port 101 are switched to the parameters matched by the first transmission port 101 when transmitting data according to the changed data transmission rate. The first sending port 101 is switched from a low power consumption state to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data; the first controller 105 is also used to control the first sending port 101 to the opposite end chip. A receiving port 203 sends a control code stream that controls the first receiving port 203 to switch to a high-speed data transmission state or a low-speed data transmission state matching the transmission rate of the target data. For details, refer to the workflow shown in FIG. 10 .

The first controller 105 is also used to control the first sending port 101 to enter a high-speed data transmission state to perform high-speed data transmission when the data transmission control code stream is a high-speed data transmission control code stream; When a data transmission error is detected in the transmission state, the first sending port 101 is controlled to enter the repair state; the repair control code stream that controls the first receiving port 203 of the opposite end chip to enter the repair state is sent to the opposite end chip; the first control The controller 105 is further configured to perform data repair on the first sending port 101 in the repair state, and repair the parameters of the first sending port 101 to the parameters when the first sending port 101 is in the high-speed data transmission state; the first controller 105 also uses After the data restoration of the first sending port 101 is completed, the first sending port 101 is controlled to enter a low power consumption state or enter a high-speed data transmission state again. The first controller 105 is further configured to control the first sending port 101 to enter a low power consumption state after detecting a data transmission error and before controlling the first sending port 101 to enter the repair state. For details, refer to the workflow shown in FIG. 11 .

When the chip is the second chip, the second chip includes the first receiving port 203 and the second controller 205. Before the first receiving port 203 enters the data transmission state, the first receiving port 203 is used to receive the control sent by the opposite end chip. The first receiving port 203 enters the control code stream of the rate switching state; the second controller 205 is used to control the first receiving port 203 to enter the rate switching state according to the control code stream; and control the first receiving port 203 according to the control code stream Enter the rate switching state; the second controller 205 is also used to switch the current parameters of the first receiving port 203 to the parameters matched when the first receiving port 203 sends data according to the target data transmission rate in the rate switching state; the second control The controller 205 is further configured to control the first receiving port 203 to enter a low power consumption state after switching is completed. The second controller 205 is further configured to control the first receiving port 203 to receive and control the first receiving port 203 after the current parameters of the first receiving port 203 are switched to the parameters matched by the first receiving port 203 when sending data according to the target data transmission rate The port 203 switches to a control code stream of a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data, and controls the first receiving port 203 to switch from a low-power state to the transmission rate of the target data according to the control code stream A matching high-speed data transfer state or a low-speed data transfer state; wherein the high-speed data transfer rate is greater than the low-speed data transfer rate. For details, refer to the workflow in FIG. 10 .

During the data transmission process, when the data transmission rate changes, the first receiving port 203 is used to receive the control code stream sent by the opposite chip to control the first receiving port 203 to enter the low power consumption state and the rate switching state; The controller 205 is used to control the first receiving port 203 to enter the low power consumption state and the rate switching state according to the control code stream; and control the first receiving port 203 to enter the low power consumption state according to the control code stream, and enter the low power consumption state The second controller 205 is also used to control the current parameters of the first receiving port 203 to switch to the parameters matched when the first receiving port 203 transmits data according to the changed data transmission rate in the rate switching state. ; The second controller 205 is further configured to control the first receiving port 203 to enter a low power consumption state after switching is completed. The second controller 205 is further configured to control the first receiving port 203 to receive and control the first receiving port 203 after the current parameters of the first receiving port 203 are switched to the parameters matched by the first receiving port 203 when sending data according to the target data transmission rate The port 203 switches to a control code stream of a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data, and controls the first receiving port 203 to switch from a low-power state to the transmission rate of the target data according to the control code stream Matching high-speed data transfer state or low-speed data transfer state. For details, refer to the workflow in FIG. 10 .

The second controller 205 is further configured to control the first receiving port 203 to enter the high-speed data transmission state to perform high-speed data transmission when the control code stream is the control code stream that controls the first receiving port 203 to switch to the high-speed data transmission state; the second control The controller 205 is configured to control the first receiving port 203 to enter the repair state according to the repair control code stream; wherein, the repair control code stream is that when the first controller 105 of the opposite chip detects a data transmission error in the high-speed data transmission state, it generates a The repair control code stream used to control the first receiving port 203 to switch to the repairing state; the second controller 205 is also used to perform data repairing on the first receiving port 203 in the repairing state, and repair the parameters of the first receiving port 203 The parameters to when the first receiving port 203 is in a high-speed data transmission state; the second controller 205 is also used to control the first receiving port 203 to enter a low power consumption state after completing the data restoration of the first receiving port 203 Enter the high-speed data transmission state; the second controller 205 is further configured to control the first receiving port 203 to enter a low power consumption state after detecting a data transmission error and before controlling the first receiving port 203 to enter the repairing state. For details, please refer to the workflow in FIG. 11 .

It should be understood that the above-mentioned first chip and second chip provided in the embodiments of the present application may also be applied to the modification of data transmission errors that occur in the state of low-speed data transmission. The first controller and the second controller can perform the same repair process as when a data transmission error occurs in the high-speed data state, which will not be repeated here.

FIG. 12 is another communication system to which the present application may be applied, including a first chip 300, a second chip 400 and an out-of-band control link. The first chip 300 only has the ability to receive data, and the second chip 400 only has the ability to send data. The out-of-band control link is a communication path outside the first chip 300 and the second chip 400 , has a certain bidirectional communication capability, and does not share a physical layer port with the first chip 300 and the second chip 400 . Commonly used out-of-band control links such as I2C, SPI, etc., whose main function is to transmit control information and configuration information from the protocol layer.

The first chip 300 applied in this application includes a protocol layer and a physical layer structure. The protocol layer is responsible for sending or receiving data information, sending and receiving control information of the out-of-band control link, and can control the physical layer according to the control information of the out-of-band control link. The physical layer includes a first controller 303, a sending module or a receiving module. The first controller 303 and the second controller 403 are directly controlled by the protocol layer to manage the sending module or the receiving module corresponding to the first chip 300 and the second chip 400 . The sending module includes a first data processing module 302 and a sending port 301. The first data processing module 302 performs operations such as encoding, scrambling, serial processing, etc. on the data information from the protocol layer to process the data information into data packets, and then send the data information into data packets. Port 301 sends packets out. The receiving module includes a second data processing module 402 and a receiving port 401, the receiving port 401 receives data packets from the transmission link, and the second data processing module 402 performs decoding, descrambling, and deserialization processing on the data packets, etc. operation, and then transmit the data information to the protocol layer.

The present application manages the ports of the communication system through the port working mode state machine, and the ports of the first chip 300 and the second chip 400 of the communication system perform power-on operation, high-speed data transmission operation, and low-speed data transmission according to the port working mode management process operation and ultra-low power operation. Under the communication system, the chip's LINK-STARTUP state, SPEED-CHANGE state and RECOVERY state flow are as follows:

Figure 13 shows the workflow of the port in the LINK-STARTUP state under the communication system architecture. After the port initialization is completed, the protocol layer of the first chip controls the receiving port to enter the LINK-STARTUP state. The protocol layer can exchange basic information with the sending port of the second chip through the out-of-band control link, and negotiate the rate of in-band communication. The physical layer configures port parameters according to the basic information of the two ports and the negotiated in-band communication rate, and communicates over the in-band transmission link at the negotiated rate. If the communication is successful, wait for the condition to enter the next state; if the communication fails, notify the protocol layer and return to the PHY-INIT state.

FIG. 14 shows the workflow of the port in the SPEED-CHANGE state under the communication system architecture. When the protocol layer needs to change the current in-band communication rate, the target communication rate of the in-band transmission link can be negotiated with the opposite port through the out-of-band control link. After that, the protocol layer instructs the physical layer port to end the current state (LOW-POWER0 state or TRANS0 state or TRANS1 state) and enter the SPEED-CHANGE state. The physical layer configures port parameters according to the negotiated transmission rate of the target data of the in-band transmission link, and communicates on the in-band transmission link at the negotiated rate. If the communication is successful, wait for the condition to enter the next state; if the communication fails, notify the protocol layer and return to the LOW-POWER0 state.

Figure 15 shows the workflow of the port in the RECOVERY state under the communication system architecture. When an error occurs in the communication process of the in-band data transmission link, the protocol layer confirms the error type of the in-band transmission link with the peer port through the out-of-band control link. After that, the protocol layer instructs the physical layer port to end the current state (LOW-POWER0 state or TRANS1 state) and enter the RECOVERY state. The physical layer sends or receives the repair-related code stream on the in-band transmission link according to the error type, and performs repair measures on the in-band communication transmission link according to the repair-related code stream. The repair-related code stream may include, but is not limited to, the receiver bit synchronization code stream and the receiver equalization training code stream. If the repair is successful, wait for the condition to enter the next state; if the repair fails, notify the protocol layer and return to the LOW-POWER0 state.

It should be understood that the above-mentioned first chip, second chip, and out-of-band control link provided in the embodiments of the present application can also be applied to the modification of data transmission errors that occur in the state of low-speed data transmission. The first chip, the second chip and the out-of-band control link can perform the same repair process as when a data transmission error occurs in the high-speed data state, which will not be repeated here. For details, please refer to the description of the data repair in FIG. 5 and FIG. 6 . .

It can be seen from the above description that the embodiment of the present application provides a high-speed communication method, which increases the handshake process of the port after reconfiguring the parameters of the transmission link, and judges the accuracy of data transmission of the transmission link; The interoperability between the states of the state machine reduces the number of port jumps between different states.

An embodiment of the present application further provides a mobile terminal, where the mobile terminal includes a chip and an opposite-end chip communicatively connected to the chip; wherein the chip and the opposite-end chip are the chips of any of the above. In the above solution, by setting the repair state, when the high-speed data transmission fails, the transmission link is repaired, which improves the reliability of the high-speed data transmission. In addition, when repairing, only matching parameters corresponding to high-speed data transmission are repaired, and there is no need to match the basic information of the two chips during handshake, which improves the repair effect.

As shown in FIG. 16 , the embodiment of the present application further provides a signal processing module 1000 for implementing the functions of the above method. The signal processing module 1000 may be a communication device, or may be a device in a communication device. The signal processing module 1000 includes at least one processor 1001 for implementing the functions of the apparatus in the above method. For example, the processor 1001 may be configured to control the communication port 1003 (transmitting port) to perform state switching according to the acquired sending and receiving requirements of the first chip. For details, refer to the detailed description in the method, which is not described herein again.

In some embodiments, the signal processing module 1000 may further include at least one memory 1002 for storing program instructions and/or data. Memory 1002 is coupled to processor 1001 . The coupling in the embodiments of the present application is the spaced coupling or communication connection between devices, units or modules, which may be in electrical, mechanical or other forms, and is used for information interaction between the devices, units or modules. As another implementation, the memory 1002 may also be located outside the signal processing module 1000 . The processor 1001 may cooperate with the memory 1002 . Processor 1001 may execute program instructions stored in memory 1002 . At least one of the at least one memory may be included in the processor.

In some embodiments, the signal processing module 1000 includes a communication port 1003 for communicating with other devices through a transmission medium, so that the apparatus used in the signal processing module 1000 can communicate with other devices. Illustratively, the communication port 1003 may be a transceiver, circuit, bus, module or other type of communication port, and the other device may be a network device or other terminal device or the like. The processor 1001 uses the communication port 1003 to send and receive data, and is used to implement the methods in the above embodiments. Illustratively, the communication port 1003 may be used to communicate signals.

The embodiment of the present application does not limit the connection medium between the communication port 1003 , the processor 1001 , and the memory 1002 . For example, in the embodiment of the present application, the memory 1002, the processor 1001, and the communication port 1003 may be connected through a bus in FIG. 16, and the bus may be divided into an address bus, a data bus, and a control bus.

In this embodiment of the present application, the processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, which can implement or The methods, steps and logic block diagrams disclosed in the embodiments of this application are executed. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the methods disclosed in conjunction with the embodiments of the present application may be directly embodied as executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.

In this embodiment of the present application, the memory may be a non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), etc., or may also be a volatile memory (volatile memory), for example Random-access memory (RAM). Memory is, but is not limited to, any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. The memory in this embodiment of the present application may also be a circuit or any other device capable of implementing a storage function, for storing program instructions and/or data.

The methods provided in the embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented in whole or in part in the form of a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the procedures or functions according to the embodiments of the present application are generated in whole or in part. A computer may be a general purpose computer, a special purpose computer, a computer network, network equipment, user equipment, or other programmable apparatus. Computer instructions may be stored on or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server, or data center over a wire (e.g. Coaxial cable, optical fiber, digital subscriber line (DSL) or wireless (such as infrared, wireless, microwave, etc.) means to transmit to another website site, computer, server or data center. A computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, or the like that contains an integration of one or more available media. Useful media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, digital video discs (DVD)), or semiconductor media (eg, SSDs), and the like.

Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

A communication method, comprising the steps of:

When a data transmission error is detected in the data transmission state, both the sending port and the receiving port are controlled to enter a repair state, wherein the data transmission state includes a high-speed data transmission state and a low-speed data transmission state, and the sending port is located on the main chip side, so The receiving port is located on the side of the slave chip that has a communication relationship with the master chip;

In the repair state, data repair is performed on the sending port and the receiving port, the parameters of the sending port are repaired to the parameters when the sending port is in the data transmission state, and the parameters of the receiving port are repaired Repair the parameters when the receiving port is in the data transmission state;

After completing the data restoration on the sending port and the receiving port, both the sending port and the receiving port are controlled to enter a low power consumption state or both enter the high-speed data transmission state again.
The communication method according to claim 1, wherein after detecting the data transmission error and before controlling both the sending port and the receiving port to enter the repair state, the method further comprises: :

Both the transmitting port and the receiving port are controlled to enter a low power consumption state.
The communication method according to claim 1, wherein the controlling both the sending port and the receiving port to enter a repair state specifically refers to:

Both the transmit port and the receive port are controlled to enter the repair state from the low power consumption state.
The communication method according to any one of claims 1 to 3, wherein when a data transmission error is detected, both the sending port and the receiving port are controlled to enter a repair state; specifically:

When the data transmission error is detected, the sending port is controlled to enter the repair state, and a repair control code stream is sent to the slave chip, so that the protocol layer or the controller of the slave chip can perform the repair according to the repair state. The control code flow controls the receiving port to enter the repair state.
The communication method according to any one of claims 1 to 4, further comprising:

After completing the data restoration and before controlling both the sending port and the receiving port to enter the low power consumption state, the method further includes: confirming that the parameter of the sending port after the restoration is the sending port The parameters in the data transmission state and the parameters of the receiving port are the parameters when the receiving port is in the data transmission state.
The communication method of claim 1, wherein before the data transmission state in which the data transmission error is detected, both the sending port and the receiving port are in the low power consumption state.
The communication method according to claim 1, wherein before both the transmitting port and the receiving port enter the low power consumption state for the first time, the method further comprises:

A transmission link is established between the master chip and the slave chip, and port information exchange is performed. The port information exchange means that the master chip sends the port information of the sending port to the slave chip, and The slave chip sends the port information of the receiving port to the master chip;

After the port information exchange is completed, both the sending port and the receiving port enter the low power consumption state for the first time.
The communication method according to any one of claims 1 to 7, further comprising:

After completing the data transmission, both the sending port and the receiving port are controlled to enter the low power consumption state for waiting for the next state trigger condition.
A communication method, characterized in that the method comprises:

Before the sending port and the receiving port enter the data transmission state, the current parameters of the sending port and the current parameters of the receiving port are detected, and it is determined that the current parameters of the sending port and the sending port are sending according to the target data transmission rate Whether the parameters matched at the time of data transmission are consistent, and whether the current parameters of the receiving port are consistent with the parameters matched when the receiving port receives data according to the target data transmission rate, the sending port is located on the main chip side, and the receiving port is located on the main chip side. The port is located on the side of the slave chip that has a communication relationship with the master chip;

When the current parameters of the sending port and the receiving port are inconsistent with their matching parameters at the target data transmission rate, controlling the sending port and the receiving port to enter a rate switching state;

In the rate switching state, the current parameter of the sending port is switched to the parameter matched by the sending port when sending data according to the target data transmission rate, and the parameter of the receiving port is switched to that the receiving port is in Parameters matched when receiving data according to the target data transmission rate;

After the switching is completed, both the transmitting port and the receiving port enter a low power consumption state.
The communication method of claim 9, further comprising:

The current parameter of the sending port is switched to the parameter matched when the sending port sends data according to the target data transmission rate, and the current parameter of the receiving port is switched to the receiving port that receives data according to the target data transmission rate After matching the parameters of the data, the data transmission control code stream is received and the transmission link is controlled to switch from the low power consumption state to the high-speed data transmission state or the low-speed data transmission state matching the transmission rate of the target data. The high-speed data transfer rate is greater than the low-speed data transfer rate.
The communication method according to claim 9 or 10, further comprising:

In the data transmission process, when the data transmission rate changes, both the transmitting port and the receiving port are controlled to enter the low power consumption state, and both enter the rate switching state from the low power consumption state ;

In the rate switching state, the current parameter of the sending port is switched to the parameter matched by the sending port when transmitting data according to the changed data transmission rate, and the current parameter of the receiving port is switched to The parameter matched when the receiving port receives data according to the changed data transmission rate;

After the switching is completed, both the transmitting port and the receiving port are controlled to enter the low power consumption state.
The communication method of claim 11, further comprising:

When the current parameter of the sending port is switched to the parameter that the sending port matches when sending data according to the changed data transmission rate, and the current parameter of the receiving port is switched to When the changed data transmission rate matches the parameters when receiving data, the data transmission control code stream is received and the transmission link is controlled to switch from the low power consumption state to the high-speed data transmission that matches the transmission rate of the target data. status or low-speed data transfer status.
The communication method according to claim 10 or 12, further comprising:

When a data transmission error is detected in the data transmission state, both the sending port and the receiving port are controlled to enter a repair state; wherein the data transmission state includes a high-speed data transmission state and a low-speed data transmission state;

In the repair state, data repair is performed on the sending port and the receiving port, the parameters of the sending port are repaired to the parameters when the sending port is in the data transmission state, and the receiving port is The parameters are repaired to the parameters when the receiving port is in the data transmission state;

After completing the data restoration on the sending port and the receiving port, both the sending port and the receiving port are controlled to enter a low power consumption state or both enter the high-speed data transmission state again.
The communication method according to claim 13, wherein after detecting the data transmission error and before controlling both the sending port and the receiving port to enter the repair state, the method further comprises: :

Both the transmitting port and the receiving port are controlled to enter a low power consumption state.
A chip, characterized in that it includes a first sending port and a first controller; the first controller is configured to control the first sending port to enter a repair state when a data transmission error is detected in a data transmission state; Sending to the opposite end chip a repair control code stream that controls the first receiving port of the opposite end chip to enter a repair state; wherein, the data transmission state includes a high-speed data transmission state and a low-speed data transmission state;

The first controller is further configured to perform data repair on the first sending port in the repair state, and repair the parameters of the first sending port until the first sending port is in the data transmission state parameter;

The first controller is further configured to control the first sending port to enter a low power consumption state or enter the high-speed data transmission state again after completing data restoration on the first sending port.
The chip of claim 15, wherein the first controller is further configured to, after detecting the data transmission error and before controlling the first sending port to enter the repair state, control the The first sending port enters a low power consumption state.
The chip according to claim 15 or 16, wherein the first controller is further configured to, after completing the data restoration and before controlling the first sending port to enter the low power consumption state, It is confirmed that the parameters of the first sending port after repairing are the parameters when the first sending port is in the data transmission state.
The chip according to any one of claims 15 to 17, wherein the first controller is further configured to control the first sending port before the first sending port enters the high-speed data transmission state into a low power state.
The chip according to any one of claims 15 to 18, characterized in that, the chip further comprises a second receiving port; the second receiving port is used to receive the data sent by the second sending port of the opposite chip. Describe the port information of the first receiving port;

The first controller is further configured to control the first sending port to establish a transmission link with the first receiving port of the opposite chip, and control the first sending port to send the port information of the first sending port to The first receiving port of the peer chip.
A chip, characterized in that it includes a first receiving port and a second controller; the first receiving port is used to receive a repair control code stream sent by a first sending port of a peer chip;

The second controller is configured to control the first receiving port to enter a repair state according to the repair control code stream; wherein the repair control code stream is that the first controller of the opposite end chip is in a data transmission state When a data transmission error is detected, a repair control code stream is generated for controlling the first receiving port to switch to a repair state; wherein, the data transmission state includes a high-speed data transmission state and a low-speed data transmission state;

The second controller is further configured to perform data repair on the first receiving port in the repair state, and repair the parameters of the first receiving port until the first receiving port is in the data transmission state parameter;

The second controller is further configured to control the first receiving port to enter a low power consumption state or enter the high-speed data transmission state again after completing data restoration on the first receiving port.
The chip of claim 20, wherein the second controller is further configured to, after detecting the data transmission error and before controlling the first receiving port to enter the repair state, control the The first receiving port enters a low power consumption state.
The chip according to claim 20 or 21, wherein the second controller is further configured to, after completing the data restoration and before controlling the first receiving port to enter the low power consumption state, It is confirmed that the parameters of the first receiving port after repairing are the parameters when the first receiving port is in the data transmission state.
The chip according to any one of claims 20 to 22, wherein the second controller is further configured to control the first receiving port before the first receiving port enters the high-speed data transmission state into a low power state.
The chip according to any one of claims 20 to 23, further comprising a second sending port; the second controller is further configured to control the first receiving port and the first receiving port of the opposite chip The sending port establishes a transmission link, and controls the second sending port to send the port information of the first receiving port to the second receiving port of the opposite chip;

The first receiving port is further configured to receive port information of the first sending port sent by the first sending port of the opposite chip.
A chip, characterized in that it includes a first sending port and a first controller, and the first controller is used to detect the current parameters of the first sending port and determine the current parameters of the first sending port before the first sending port enters a data transmission state. Whether the current parameters of the first sending port are consistent with the parameters matched by the first sending port when sending data according to the target data transmission rate;

The first controller is further configured to control the first sending port to enter a rate switching state when the current parameter of the first sending port is inconsistent with the parameter matching the first sending port at the target data transmission rate;

The first controller is further configured to switch the current parameter of the first sending port to the parameter matched when the first sending port sends data according to the target data transmission rate in the rate switching state;

The first controller is further configured to control the first sending port to send a control code stream for controlling the first receiving port to enter a rate switching state to the first receiving port of the opposite chip;

The first controller is further configured to control the first sending port to enter a low power consumption state after switching is completed.
The chip according to claim 25, wherein the first controller is further configured to switch the current parameter of the first sending port to when the first sending port sends data according to a target data transmission rate After matching the parameters, receiving a data transmission control code stream and controlling the first sending port to switch from the low power consumption state to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data;

The first controller is further configured to control the first sending port to send to the first receiving port of the opposite chip, and control the first receiving port to switch to a high-speed data transmission state matching the transmission rate of the target data or Control stream of low-speed data transmission state;

Wherein, the high-speed data transmission rate is greater than the low-speed data transmission rate.
The chip according to claim 25 or 26, wherein the first controller is further configured to control the first sending port to enter the low a power consumption state, and enter the rate switching state from the low power consumption state;

The first controller is further configured to, in the rate switching state, control the current parameters of the first sending port to switch to parameters matched by the first sending port when transmitting data according to the changed data transmission rate ;

The first controller is further configured to control the first sending port to send a control code stream for controlling the first receiving port to enter a low power consumption state and a rate switching state to the first receiving port of the opposite chip;

The first controller is further configured to control the first sending port to enter the low power consumption state after switching is completed.
The chip according to claim 27, wherein the first controller is further configured to switch the current parameter of the first sending port to the data transmission of the first sending port after the change When the data rate matches the parameters when sending data, receive the data transmission control code stream and control the first sending port to switch from the low power consumption state to the high-speed data transmission state or low-speed data transmission that matches the transmission rate of the target data state;

The first controller is further configured to control the first sending port to send to the first receiving port of the opposite chip, and control the first receiving port to switch to a high-speed data transmission state matching the transmission rate of the target data or Control code flow for low-speed data transmission status.
The chip according to claim 26 or 28, wherein the first controller is further configured to control the first sending port to enter a repair state when a data transmission error is detected in the data transmission state; The chip sends a repair control code stream that controls the first receiving port of the opposite chip to enter a repair state; wherein, the data transmission state includes a high-speed data transmission state and a low-speed data transmission state;

The first controller is further configured to perform data repair on the first sending port in the repair state, and repair the parameters of the first sending port until the first sending port is in the data transmission state parameter;

The first controller is further configured to control the first sending port to enter a low power consumption state or enter the high-speed data transmission state again after completing data restoration on the first sending port.
The chip of claim 29, wherein the first controller is further configured to, after detecting the data transmission error and before controlling the first sending port to enter the repair state, control the The first transmission port enters a low power consumption state.
A chip, characterized in that it includes a first receiving port and a second controller,

Before the first sending port enters the data transmission state, the first receiving port is used to receive the control code stream sent by the opposite end chip to control the first receiving port to enter the rate switching state;

The second controller is configured to control the first receiving port to enter a rate switching state according to a control code stream; and control the first receiving port to enter a rate switching state according to the control code stream;

The second controller is further configured to switch the current parameter of the first receiving port to the parameter matched when the first receiving port sends data according to the target data transmission rate in the rate switching state;

The second controller is further configured to control the first receiving port to enter a low power consumption state after switching is completed.
The chip of claim 31, wherein the second controller is further configured to switch the current parameter of the first receiving port to when the first receiving port sends data according to a target data transmission rate After matching the parameters, control the first receiving port to receive a control code stream that controls the first receiving port to switch to a high-speed data transmission state or a low-speed data transmission state matching the transmission rate of the target data, and according to the The control code flow controls the first receiving port to switch from the low power consumption state to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data;

Wherein, the high-speed data transmission rate is greater than the low-speed data transmission rate.
The chip according to claim 31 or 32, characterized in that, in the process of data transmission, when the data transmission rate changes, the first receiving port is used to receive the control of the first receiving port sent by the opposite end chip Enter the control stream of the low power consumption state and the rate switching state;

The second controller is configured to control the first receiving port to enter the low power consumption state and the rate switching state according to the control code stream; and control the first receiving port to enter the low power consumption state according to the control code stream, And enter the rate switching state after entering the low power consumption state;

The second controller is further configured to, in the rate switching state, control the current parameters of the first receiving port to switch to the parameters matched by the first receiving port when transmitting data according to the changed data transmission rate ;

The second controller is further configured to control the first receiving port to enter the low power consumption state after switching is completed.
The chip of claim 33, wherein the second controller is further configured to switch the current parameter of the first receiving port to when the first receiving port sends data according to a target data transmission rate After matching the parameters, control the first receiving port to receive a control code stream that controls the first receiving port to switch to a high-speed data transmission state or a low-speed data transmission state matching the transmission rate of the target data, and according to the The control code flow controls the first receiving port to switch from the low power consumption state to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data.
The chip according to claim 32 or 34, wherein the second controller is further configured to control the first receiving port to enter a repair state according to the repair control code flow; wherein the repair control code The stream is a repair control code stream generated when the first controller of the opposite end chip detects a data transmission error in the high-speed data transmission state and is used to control the first receiving port to switch to the repair state;

The second controller is further configured to perform data repair on the first receiving port in the repair state, and repair the parameters of the first receiving port to the parameters when the first receiving port is in a data transmission state ; Wherein, the data transmission state includes a high-speed data transmission state and a low-speed data transmission state;

The second controller is further configured to control the first receiving port to enter a low power consumption state or enter the high-speed data transmission state again after completing data restoration on the first receiving port.
The chip of claim 35, wherein the second controller is further configured to control the first receiving port to enter the repair state after detecting the data transmission error and before controlling the first receiving port to enter the repair state. The first receiving port enters a low power consumption state.
A communication system, comprising a first chip and a second chip; wherein the first chip is the chip according to any one of claims 15 to 19; the second chip is the chip according to claim 20 The chip of any one of ~24; or,

The first chip is the chip according to any one of claims 25-30, and the second chip is the chip according to any one of claims 31-36.
A mobile terminal, comprising a first chip and a second chip; wherein the first chip is the chip according to any one of claims 15 to 19; the second chip is the chip according to claim 20 The chip of any one of ~24; or,

The first chip is the chip according to any one of claims 25-30, and the second chip is the chip according to any one of claims 31-36.