WO2022066096A1 - Dispositif de puce intégrée photonique en silicium et son procédé de fabrication - Google Patents

Dispositif de puce intégrée photonique en silicium et son procédé de fabrication Download PDF

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Publication number
WO2022066096A1
WO2022066096A1 PCT/SG2021/050433 SG2021050433W WO2022066096A1 WO 2022066096 A1 WO2022066096 A1 WO 2022066096A1 SG 2021050433 W SG2021050433 W SG 2021050433W WO 2022066096 A1 WO2022066096 A1 WO 2022066096A1
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WO
WIPO (PCT)
Prior art keywords
protective film
silicon
exposed surface
trench
waveguide
Prior art date
Application number
PCT/SG2021/050433
Other languages
English (en)
Inventor
Jiangfeng Chen
Original Assignee
Compoundtek Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compoundtek Pte Ltd filed Critical Compoundtek Pte Ltd
Publication of WO2022066096A1 publication Critical patent/WO2022066096A1/fr

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/26—Optical coupling means
    • G02B6/30—Optical coupling means for use between fibre and thin-film device
    • G02B6/305—Optical coupling means for use between fibre and thin-film device and having an integrated mode-size expanding section, e.g. tapered waveguide
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/122—Basic optical elements, e.g. light-guiding paths
    • G02B6/1223—Basic optical elements, e.g. light-guiding paths high refractive index type, i.e. high-contrast waveguides
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13—Integrated optical circuits characterised by the manufacturing method
    • G02B6/136—Integrated optical circuits characterised by the manufacturing method by etching
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12035—Materials
    • G02B2006/12061—Silicon
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13—Integrated optical circuits characterised by the manufacturing method
    • G02B6/132—Integrated optical circuits characterised by the manufacturing method by deposition of thin films
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/36—Mechanical coupling means
    • G02B6/3628—Mechanical coupling means for mounting fibres to supporting carriers
    • G02B6/3648—Supporting carriers of a microbench type, i.e. with micromachined additional mechanical structures
    • G02B6/3652—Supporting carriers of a microbench type, i.e. with micromachined additional mechanical structures the additional structures being prepositioning mounting areas, allowing only movement in one dimension, e.g. grooves, trenches or vias in the microbench surface, i.e. self aligning supporting carriers

Definitions

  • the disclosures made herein relate generally to the silicon photonics and more particularly to a silicon photonic integrated chip (PIC) device and a fabricating method therefor.
  • PIC silicon photonic integrated chip
  • Monolithically integrated photonic circuits are mainly used as optical data links in applications including high performance computing (HPC), inter-device interconnects and optical memory extension (OME). They are also very much useful as input/output means in mobile devices to enable data exchange between the mobile devices and a host device and/or cloud servers at a rapid rate which is not possible with wireless technology or electrical cables.
  • HPC high performance computing
  • OME optical memory extension
  • silicon photonic integrated circuit (PIC) devices are more advantageous in terms of cost of manufacturing and maturity of technology.
  • silicon PIC devices are prone to damage due to external environmental conditions such as moisture, contamination, scratches, etc.
  • SiCh silicon dioxide
  • SiN silicon nitride
  • United States Patent No.: US 10,416,380 Bl discloses a method for forming an integrated photonic device with one or more suspended structures such as optical mode spot size converter and photonic phase shifter.
  • the suspended structure is formed by removing a part of a substrate such that a cavity is formed under the suspended structure. Furthermore, the cavity is sealed by filling the cavity with a dielectric material such as silicon oxide (SiCh) and silicon oxynitride, so as to prevent or reduce moisture from entering the cavity.
  • a dielectric material such as silicon oxide (SiCh) and silicon oxynitride
  • sealing the cavity imposes other disadvantages including: higher consumption of dielectric material; longer process recipe or too many shorter process recipes; additional stress on semiconductor wafer which leads to wafer bowing and breaking, and therefore inappropriate seating of the wafer in a semiconductor equipment; higher optical signal absorption loss; and limitations in size of the cavity.
  • the present invention relates to a silicon photonic integrated chip (PIC) device, comprising a silicon-on-insulator (SOI) substrate, an optical waveguide, suspended edge coupler and a protective film.
  • SOI silicon-on-insulator
  • the substrate serves as a platform on which one or more device components are fabricated.
  • the optical waveguide is disposed on the SOI substrate for guiding light waves.
  • the suspended edge coupler couples the light waves between the waveguide and an optical fiber.
  • the protective film covers an exposed surface of the device.
  • the suspended edge coupler includes one or more edge facets, lateral cavities and/or trenches, wherein a cross section of an upper surface of the protective film conforms to that of the exposed surface of the device.
  • the protective film is disposed on the device by a plasma enhanced chemical vapor deposition (PECVD) process, wherein a thickness of said protective film is within a range of 10 - 100 nanometers.
  • PECVD plasma enhanced chemical vapor deposition
  • the protective film is formed of an electrically insulative composition comprising a silicon nitride and/or silicon oxynitride.
  • One or more electrical contacts are on the exposed surface, wherein the protective film includes an opening for exposing each electrical contact.
  • a method for fabricating a silicon photonic integrated chip (PIC) device comprises the steps of: disposing an optical waveguide on a silicon-on- insulator (SOI) substrate for guiding light waves, forming one or more device components on the SOI substrate or the waveguide, forming a suspended edge coupler for coupling the light waves between the waveguide and an optical fiber, and disposing a protective film on an exposed surface of the silicon PIC device.
  • SOI silicon-on- insulator
  • the suspended edge coupler is formed with an edge facet, lateral cavity and/or trench, and the protective film is disposed on the exposed surface of the silicon PIC device, such that a cross section of an upper surface of the protective film conforms to that of the exposed surface.
  • the protective film is disposed on the silicon PIC device by a plasma enhanced chemical vapor deposition (PECVD) process, wherein a thickness of the protective film is within a range of 10 - 100 nanometers.
  • PECVD plasma enhanced chemical vapor deposition
  • the protective film is formed of an electrically insulative composition.
  • Figure 1 shows a cross sectional view of the device, in accordance with an exemplary embodiment of the present invention.
  • Figure 2 shows a perspective cross sectional view of the device, in accordance with an exemplary embodiment of the present invention.
  • Figure 3 shows a cross sectional view of the device with electrical contacts, in accordance with an exemplary embodiment of the present invention.
  • Figure 4 shows a flow diagram of the method for fabricating the device, in accordance with the first embodiment of the present invention.
  • the present invention relates to silicon photonic integrated chip (PIC) device and a fabricating method therefor.
  • the device comprising a protective film covering exposed surfaces of the edge facets, trenches and lateral cavities, such that a cross section of an upper surface of the protective film conforms to that of the exposed surfaces.
  • the protective film protects the device from moisture without compromising the light coupling performance of the device, while minimizing time and material consumption for fabricating the device. Since the protective film is thinner, a stress experienced by a semiconductor wafer during fabrication is reduced, and therefore minimizing the chances of wafer bowing. Furthermore, a thinner protective film minimizes absorption loss of an optical signal and allows wider trenches which in turn avoids any lithographic, etching, deposition or wafer cleaning constraints due to narrower trenches.
  • FIG. 1 shows a cross sectional view of the silicon photonic integrated chip (PIC) device, in accordance with an exemplary embodiment of the present invention.
  • the device (10) comprises a silicon-on-insulator (SOI) substrate (11), an optical waveguide (not shown), suspended edge coupler (12) and a protective film (13).
  • SOI substrate (11) serves as a platform on which the device (10) is fabricated, wherein one or more device components are fabricated on the SOI substrate (11).
  • the device components include any conventional PIC device components.
  • the waveguide is disposed on the SOI substrate (11) for guiding light waves, wherein the suspended edge coupler (12) couples the light waves between the waveguide and an optical fiber (not shown). Alternatively, the device components are fabricated over the waveguide.
  • the protective film (13) protects the device (10) from any external environmental conditions including moisture, contamination and scratches.
  • the suspended edge coupler (12) includes at least one edge facet (12a), trench (12b) and/or lateral cavity (12c).
  • the protective film (13) covers an exposed surface (14, as in Figure 2) of the edge facet (12a), trench (12b) and/or lateral cavity (12c), such that a cross section of an upper surface (13a) of the protective film (13) conforms to that of the exposed surface (14) of the edge facet (12a), trench (12b) and/or lateral cavity (12c).
  • the protective film (13) is disposed on the exposed surface (14) by a plasma enhanced chemical vapor deposition (PECVD) process.
  • PECVD plasma enhanced chemical vapor deposition
  • the protective film (13) is formed of an electrically insulative composition comprising silicon nitride and/or silicon oxynitride.
  • a plurality of electrical contacts (15, as in Figure 3) is on the exposed surface (14), wherein the protective film (13) includes an opening (13b, as in Figure 3) for exposing each electrical contact (15).
  • the electrical contacts (15) include bondpads.
  • the protective film (13) is etched to form the openings (13b), wherein the protective film (13) is masked to define one or more portions to be etched to form the openings (13b).
  • the protective film (13) is etched using any conventional etch recipe including an anisotropic composition.
  • the protective film (13) may also be blanket etched to form the openings (13b) without masking the protective film (13).
  • a thickness of the protective film (13) is within a range of 10 - 100 nanometers.
  • the edge facet (12a), the lateral cavity (12c) or the trench (12b) are formed by etching the edge coupler (12) and/or the SOI substrate (11), such that an angle of a sidewall of the edge facet (12a), and/or the trench (12b) with respect to the SOI substrate (11) is within 87 - 90°.
  • the angle of the sidewall is 90°.
  • the protective film (13) protects the device (10) from any external environmental conditions without compromising a light coupling performance of the device (10), while minimizing time and material consumption during fabrication of the device (10). Since the protective film (13) is thinner, a stress experienced by the SOI substrate (11) during fabrication of the device (10) is reduced, and therefore minimizing the chances of wafer bowing or breaking. Furthermore, a thinner protective film minimizes absorption loss of an optical signal and allows wider trenches which in turn avoids any lithographic, etching, deposition or wafer cleaning constraints due to narrower trenches.
  • FIG. 4 shows a flow diagram of the method for fabricating the silicon PIC device, in accordance with the first embodiment of the present invention.
  • the method (20) comprises the steps of: disposing an optical waveguide on a silicon-on-insulator (SOI) substrate for guiding light waves (21), forming one or more device components on the SOI substrate or on the waveguide (22), forming a suspended edge coupler for coupling the light waves between the waveguide and an optical fiber (23), and disposing a protective film for protecting the device from any external environmental conditions (24).
  • SOI silicon-on-insulator
  • the suspended edge coupler is formed with one or more edge facets, lateral cavities and/or trenches, wherein an angle of a sidewall of the edge facet and/or the trench with respect to said substrate is within 87 - 90°.
  • the protective film is disposed on an exposed surface of the edge facets, lateral cavities and/or trenches, such that a cross section of an upper surface of the protective film conforms to that of the exposed surface.
  • a thickness of the protective film is within a range of 10 - 100 nanometers.
  • the protective film is disposed on the device by a plasma enhanced chemical vapor deposition (PECVD) process, wherein the protective film is formed of an electrically insulative composition comprising silicon nitride and/or silicon oxynitride.
  • PECVD plasma enhanced chemical vapor deposition
  • one or more electrical contacts such as bondpads, are disposed on the exposed surface and an opening is etched through the protective film for exposing each electrical contact.
  • the protective film is masked with a photoresist defining one or more portions to be etched to form the openings, before the etching step, wherein the protective film is etched using any conventional etch recipe including an anisotropic composition.
  • the protective film is blanket etched without masking the protective film.
  • the present invention exhibits better moisture resistance without compromising a light coupling performance, while minimizing time and material consumption during fabrication of the device. Since the protective film is thinner, a stress experienced by the silicon substrate during fabrication of the device, particularly during disposing the protective film, is reduced, and therefore minimizing the chances of wafer bowing or breaking. Furthermore, a thinner protective film minimizes absorption loss of an optical signal and allows wider trenches which in turn avoids any lithographic, etching, deposition or wafer cleaning constraints due to narrower trenches.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optical Integrated Circuits (AREA)

Abstract

La présente invention concerne un dispositif de puce intégrée photonique (PIC) en silicium, 5 comprenant un substrat de silicium sur isolant (SOI) (11), un guide d'ondes optique, un coupleur de bord suspendu (12) et un film de protection (13). Le substrat SOI (11) sert de plateforme sur le dispositif qui est fabriqué. Le guide d'ondes optique est disposé sur le substrat SOI (11) pour guider des ondes lumineuses. Le coupleur de bord suspendu (12) couple les ondes lumineuses entre le guide d'ondes et une fibre optique. Le film 10 de protection (13) protège le dispositif (10) de n'importe quelles conditions environnementales externes. Un procédé de fabrication du dispositif est également divulgué.
PCT/SG2021/050433 2020-09-25 2021-07-23 Dispositif de puce intégrée photonique en silicium et son procédé de fabrication WO2022066096A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SG10202009520X 2020-09-25
SG10202009520X 2020-09-25

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WO2022066096A1 true WO2022066096A1 (fr) 2022-03-31

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230273369A1 (en) * 2022-02-25 2023-08-31 Globalfoundries U.S. Inc. Photonics structures having a locally-thickened dielectric layer
CN117805968A (zh) * 2024-02-29 2024-04-02 江苏南里台科技有限公司 一种光子芯片图案结构的制作方法及系统

Citations (5)

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Publication number Priority date Publication date Assignee Title
US20050151144A1 (en) * 2001-10-09 2005-07-14 Infinera Corporation Oxygen-doped al-containing current blocking layers in active semiconductor devices in photonic integrated circuits (PICs)
US20150340273A1 (en) * 2014-05-21 2015-11-26 International Business Machines Corporation Silicon waveguide on bulk silicon substrate and methods of forming
KR20160101234A (ko) * 2015-02-13 2016-08-25 주식회사 우리로 광도파로 내부에 광경로 전환용 마이크로 거울을 내장한 광집적회로 및 그 제조방법
US20160266331A1 (en) * 2013-12-03 2016-09-15 Intel Corporation Monolithic physically displaceable optical waveguides
WO2017148248A1 (fr) * 2016-03-01 2017-09-08 Huawei Technologies Co., Ltd. Intégration de rainures en v sur une plateforme de silicium sur isolant (soi) pour couplage direct de fibres

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050151144A1 (en) * 2001-10-09 2005-07-14 Infinera Corporation Oxygen-doped al-containing current blocking layers in active semiconductor devices in photonic integrated circuits (PICs)
US20160266331A1 (en) * 2013-12-03 2016-09-15 Intel Corporation Monolithic physically displaceable optical waveguides
US20150340273A1 (en) * 2014-05-21 2015-11-26 International Business Machines Corporation Silicon waveguide on bulk silicon substrate and methods of forming
KR20160101234A (ko) * 2015-02-13 2016-08-25 주식회사 우리로 광도파로 내부에 광경로 전환용 마이크로 거울을 내장한 광집적회로 및 그 제조방법
WO2017148248A1 (fr) * 2016-03-01 2017-09-08 Huawei Technologies Co., Ltd. Intégration de rainures en v sur une plateforme de silicium sur isolant (soi) pour couplage direct de fibres

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230273369A1 (en) * 2022-02-25 2023-08-31 Globalfoundries U.S. Inc. Photonics structures having a locally-thickened dielectric layer
US11803009B2 (en) * 2022-02-25 2023-10-31 Globalfoundries U.S. Inc. Photonics structures having a locally-thickened dielectric layer
CN117805968A (zh) * 2024-02-29 2024-04-02 江苏南里台科技有限公司 一种光子芯片图案结构的制作方法及系统
CN117805968B (zh) * 2024-02-29 2024-05-17 江苏南里台科技有限公司 一种光子芯片图案结构的制作方法及系统

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