WO2022062937A1 - 任务调度方法、装置以及计算机系统 - Google Patents

任务调度方法、装置以及计算机系统 Download PDF

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Publication number
WO2022062937A1
WO2022062937A1 PCT/CN2021/117933 CN2021117933W WO2022062937A1 WO 2022062937 A1 WO2022062937 A1 WO 2022062937A1 CN 2021117933 W CN2021117933 W CN 2021117933W WO 2022062937 A1 WO2022062937 A1 WO 2022062937A1
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Prior art keywords
processor
core
information
task
failure information
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PCT/CN2021/117933
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English (en)
French (fr)
Inventor
李玉伟
尹文
栗炜
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华为技术有限公司
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Publication of WO2022062937A1 publication Critical patent/WO2022062937A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load

Definitions

  • the present application relates to the field of computer technology, and in particular, to a task scheduling method, device, and computer system.
  • the central processing unit is the computing and control core of the computer.
  • the operations of all software layers in the computer system will eventually be mapped to the operations of the CPU through the instruction set.
  • modern processors In order to meet the upper-layer work requirements of the operating system (OS), modern processors have further introduced functions such as parallelization, multi-core (that is, integrating two or more cores in one CPU), etc.
  • the upper information system moves forward. With the continuous emergence and increasing complexity of various applications, the industry has proposed a turbo technology to improve CPU performance to meet the application requirements of high workloads.
  • Turbo Mode is the acceleration mode. By analyzing the current CPU load, it intelligently shuts down some unused cores completely, leaving the energy to the cores in use and making them run at a higher frequency. To further improve performance; on the contrary, when multiple cores are needed, the corresponding cores are dynamically turned on and the frequency is adjusted intelligently. In this way, the core operating frequency can be adjusted higher without affecting the thermal design power (TDP) of the CPU.
  • TDP thermal design power
  • the OS kernel adopts a random scheduling mechanism to randomly schedule turbo tasks to run on a core.
  • the use frequency of the core is greatly increased, and correspondingly, the life of the core will be shortened, which will lead to uneven wear of multiple cores of the processor, which will directly affect the life of the processor.
  • the actual processor needs to lower the highest operating frequency, which will cause the performance of the processor to decrease.
  • Embodiments of the present application provide a task scheduling method, device, and computer system, which help to increase the operating frequency for high-load tasks while ensuring the service life of devices.
  • an embodiment of the present application provides a task scheduling method, which can be applied to a computer system with multiple processor cores, and the method may include: acquiring a target task, where the target task requires a processor A task processed by a core in a turbo state; a target core is determined among the plurality of processor cores according to the failure information of the plurality of processor cores; wherein the failure information of any processor core is used to indicate the processing the lifetime of the turbo state of the turbo state; assigning the target task to the target core so that the target core processes the target task in the turbo state.
  • the target tasks that need to be processed by the processor cores in the turbo state can be scheduled according to the failure information of the processor cores, so as to balance the use of multiple processor cores frequency, to achieve wear leveling among multiple processor cores as much as possible, so as to increase the operating frequency for high-load tasks while ensuring the device (including the processor to which the processor core belongs and/or the chip corresponding to the processor and other devices) ) of the service life.
  • determining a target core among the multiple processor cores according to the failure information of the multiple processor cores includes: acquiring the failure information of the multiple processor cores; according to the Failure information of multiple processor cores, among the multiple processor cores, select the target core whose failure information satisfies the first scheduling condition.
  • the failure information of any processor core includes the failure rate of the processor core; the first scheduling condition includes: the failure rate is the smallest; and/or the failure rate is not greater than a first value, wherein the first The value is the average of the failure rates of the plurality of processor cores.
  • the target processor core (referred to as the target core) is selected according to the set first scheduling condition, so as to balance the use frequency of multiple processor cores and achieve multiple Wear leveling between processor cores increases the operating frequency for high-load tasks while maintaining device life.
  • the computer system includes a processor, the multiple processor cores are located in the processor, and the acquiring the target task includes: acquiring a task to be processed; determining the multiple When at least one processor core whose load exceeds the first load threshold exists among the processor cores, the task to be processed is determined to be the target task.
  • the computer system to which this solution is applicable can be a system containing only one multi-core processor, by performing task scheduling among multiple processor cores of the multi-core processor, Achieve wear leveling across multiple processor cores as much as possible, increasing the operating frequency for high-load tasks while maintaining device life.
  • the computer system includes a plurality of processors, and at least one processor core of a first processor located in the plurality of processors exists in the plurality of processor cores; the obtaining The target task includes: acquiring a to-be-processed task; when it is determined that the to-be-processed task is to be allocated to the first processor and the load of the first processor exceeds a second load threshold, determining the to-be-processed task The processing task is the target task.
  • the computer system to which this solution is applicable may be a system including multiple processors, any processor may include at least one processor core, and the computer system may implement task scheduling across processors. Therefore, by performing task scheduling among multiple processors, and by balancing the use frequency of multiple processors, the wear leveling among multiple processors is achieved as much as possible, and the running frequency is increased for high-load tasks while ensuring device lifetime.
  • the multiple processors may have different specifications and capabilities.
  • the benchmarks on which it is based may vary. Different, that is, scheduling can be performed according to the capabilities of different processors, which is not limited in this application.
  • determining a target core among the multiple processor cores according to the failure information of the multiple processor cores includes: acquiring the failure information of the multiple processors, wherein any one of The failure information of the processor is used to indicate the lifetime of the processor in the turbo state; according to the failure information of the multiple processors, the first one whose failure information satisfies the second scheduling condition is selected from the multiple processors.
  • a processor wherein the failure information of any processor includes the failure rate of the processor, and the second scheduling condition includes: the failure rate is the smallest, and/or the failure rate is not greater than the second value, wherein the The second value is the average value of the failure rates of the plurality of processors; among the plurality of processor cores, at least one candidate processor core located in the first processor is determined; according to the at least one candidate processor core; The failure information of the selected processor core is selected, and the target core is determined in the at least one candidate processor core.
  • a processor when scheduling the target task, a processor can be selected according to the set second scheduling condition, and then each processor core of the processor can be used as a backup Select the processor core, and then select the target core from the alternative processor cores, thus, by balancing the use frequency of multiple processors, the wear leveling between multiple processors is achieved as much as possible, and the high load tasks are improved.
  • the operating frequency also ensures the service life of the device.
  • acquiring the failure information of the multiple processor cores includes: determining the first processor core according to the stored state information of the first processor core among the multiple processor cores failure information of the first processor core, wherein the first processor core is any one of the multiple processor cores, and the state information of the first processor core includes the status information of the first processor core running in the turbo state At least one of the following information: operating frequency information, operating voltage information, operating temperature information, and operating duration information.
  • the processor core runs in the turbo state to perform the target task, the heat generation and power consumption of the processor core will affect the lifespan of the processor core.
  • the operating frequency information includes the operating frequencies corresponding to the multiple working gears;
  • the operating voltage information includes operating voltage information corresponding to the multiple working gears;
  • the operating temperature information includes the operating temperature corresponding to the multiple working gears;
  • the running duration includes the running duration corresponding to the multiple working gears;
  • the state information of the first processor core, and determining the failure information of the first processor core including: normalizing the operating frequency, operating voltage, operating temperature and operating duration corresponding to each working gear to obtain The normalized data corresponding to each working gear; the failure information of the first processor core is determined according to the normalized data corresponding to each working gear.
  • the failure information of the first processor core is obtained by normalizing the state information corresponding to the plurality of working gears of the first processor core.
  • the method further includes: saving the state information of the target core when the target core processes the target task.
  • the state information of the target core is saved, so that the failure information of the target core can be obtained correspondingly, which is convenient for task scheduling. It can be understood that, in the embodiment of the present application, for a computer system with multiple processor cores, any processor core can be used as the target core, and correspondingly, any processor core can be run in the turbo state to execute the target core. During the process of the task, the state information of the processor core can be saved.
  • an embodiment of the present application provides a task scheduling apparatus, which can be applied to a computer system having multiple processor cores, and the task scheduling apparatus can specifically implement the function of the task scheduling method behavior in the first aspect.
  • the task scheduling apparatus may be a hardware or software unit in a computer system, and may include at least one module, and the at least one module is used to implement the task scheduling method provided in the first aspect above.
  • an embodiment of the present application provides a task scheduling apparatus, including at least one processor, the at least one processor is coupled with at least one memory: the at least one processor is configured to execute the at least one memory A computer program or instructions stored to cause the apparatus to perform the method in any of the possible designs of the first aspect above.
  • the apparatus further includes a communication interface to which the processor is coupled.
  • the communication interface may be a transceiver or an input/output interface; when the device is a chip included in a network device, the communication interface may be an input/output interface of the chip.
  • the transceiver may be a transceiver circuit, and the input/output interface may be an input/output circuit.
  • an embodiment of the present application provides a computing device, including a processor and a memory, where the processor includes multiple processor cores; the memory is configured to store failure information of the multiple processor cores; The processor is configured to execute the task scheduling method described in any one of the first aspect above.
  • embodiments of the present application provide a computer system, where the computer system may include a scheduler, a power consumption controller, and multiple processor cores, where the scheduler is configured to The failure information of multiple processor cores implements the method described in the first aspect.
  • an embodiment of the present application provides a readable storage medium for storing instructions, and when the instructions are executed, the method described in the first aspect above is implemented.
  • an embodiment of the present application provides a computer program product containing instructions, which, when executed on a computer, cause the computer to execute the method described in the first aspect.
  • an embodiment of the present application provides a chip system, including: a processor, the processor is coupled to a memory, the memory is used to store programs or instructions, the chip system may further include an interface circuit, the interface circuit It is used to receive code instructions and transmit them to a processor; when the program or instructions are executed by the processor, the system-on-a-chip enables the method in any possible design of the first aspect above.
  • the number of processors in the chip system may be one or more.
  • the processor can be implemented by hardware or by software.
  • the processor may be a logic circuit, an integrated circuit, or the like.
  • the processor may be a general-purpose processor implemented by reading software codes stored in memory.
  • the memory may be integrated with the processor, or may be provided separately from the processor, which is not limited in this application.
  • the memory can be a non-transitory processor, such as a read-only memory ROM, which can be integrated with the processor on the same chip, or can be provided on different chips.
  • the setting method of the processor is not particularly limited.
  • the present application may further combine to provide more implementations.
  • FIG. 1 is a schematic diagram of a computer system to which an embodiment of the application is applicable;
  • FIG. 2a is a schematic diagram of a computer system provided by an example of the present application.
  • 2b is a schematic diagram of a computer system provided by another example of the present application.
  • FIG. 3 is a schematic flowchart of a task scheduling method provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a task scheduling apparatus provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a computing device according to an embodiment of the present application.
  • the turbo state of a computer system is implemented by the basic input output system (BIOS)/load utilization. If the turbo mode is enabled in the BIOS, when the load utilization of a single processor core is high, the turbo state is entered, so that the processor core runs at a higher frequency to improve the performance of a single processor core. As the processor core runs at a higher frequency in the turbo state, power consumption increases, further increasing the wear on the processor core. If the usage frequency of a certain processor core in the computer system is higher than that of other processor cores, it will cause uneven wear of multiple processor cores in the computer system, which will directly affect the multiple processors configured with the The life of the device (such as a processor or a chip, etc.) at the core of the device.
  • BIOS basic input output system
  • the embodiments of the present application provide a task scheduling method, device, and computer system, which help to increase the operating frequency for high-load tasks while ensuring the service life of the device.
  • the method and the device are based on the same technical concept. Since the principles of the method and the device to solve the problem are similar, the implementation of the device and the method can be referred to each other, and the repetition will not be repeated.
  • the computer system can schedule the target task according to the failure information of the processor core, so as to balance the use frequency of multiple processor cores, and achieve wear leveling among the multiple processor cores as much as possible, so as to achieve the highest level of wear and tear.
  • the load task increases the operating frequency and balances the service life of all processor cores, thereby ensuring the service life of the entire computer system.
  • a computer system consists of a hardware (sub) system and a software (sub) system.
  • the hardware (sub) system includes the organic combination of various physical components composed of electrical, magnetic, optical, mechanical and other principles, and is the entity on which the system works;
  • the software (sub) system includes various programs and files for Command the whole system to work according to the specified requirements.
  • the computer system in the embodiments of the present application may be a computer system in a terminal device, which is a device that provides business services to users and has a voice or data connectivity function.
  • the terminal device may also be referred to as a terminal device, and may also be referred to as user equipment (UE), a mobile station (mobile station, MS), a mobile terminal (mobile terminal, MT), etc.
  • UE user equipment
  • MS mobile station
  • MT mobile terminal
  • the terminal device may also be a chip.
  • a terminal device is taken as an example for specific description.
  • the terminal device may be a handheld device with a wireless connection function, a vehicle-mounted device, or the like.
  • some examples of terminal devices are: mobile phone (mobile phone), tablet computer, notebook computer, PDA, mobile internet device (MID), smart point of sale (POS), wearable device, Virtual reality (VR) equipment, augmented reality (AR) equipment, wireless terminals in industrial control, wireless terminals in self driving, remote medical surgery wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, Class smart meters (smart water meter, smart electricity meter, smart gas meter), etc.
  • the computer system in this embodiment of the present application may be a server, which is a device that provides a data connection service. Since the server can respond to the service request of the terminal device and process it, generally speaking, the server should have the ability to undertake and guarantee the service.
  • the server may be a server located in a data network (DN), such as a common server, a server in a cloud platform; or a multi-access edge computing (multi-access edge) located in the core network computing, MEC) server, etc.
  • DN data network
  • MEC multi-access edge computing
  • OS Operating system
  • Kernel It is the core of an operating system. It is the first layer of software expansion based on hardware. It provides the most basic functions of the operating system and is the basis for the work of the operating system. It is responsible for managing the processes, memory, Drivers, files and network systems determine the performance and stability of the system.
  • Failure rate refers to the product that has not failed until a certain time. After this time, the probability of failure per unit time can be used to indicate the life of the product.
  • the failure rate is generally denoted as ⁇ , which is also a function of time t, so it is also denoted as ⁇ (t), which is called the failure rate function, and is sometimes also called the failure rate function or the risk function.
  • the failure rate of the processor core refers to the probability that the processor core will fail within a unit time after a certain time
  • the processor failure rate is Refers to the probability that the processor will fail within a unit time after a certain time
  • the product refers to a chip with one or more processors
  • the failure rate of the chip refers to the chip after a certain time in a unit time. probability of failure within the Among them, the failure rate of the processor core, processor, chip, etc. can be obtained by recording the corresponding operating status information during its use, and calculating according to the operating status information and related algorithms. This application does not apply to the operating status information and related algorithms. Do limit.
  • failure rate is only an illustration of the parameters used to represent the life of the product in the embodiments of the present application, and not any limitation. In other embodiments, other parameters and corresponding parameter values may also be used to represent the life of the product. , which is not limited in this application.
  • At least one refers to one or more.
  • FIG. 1 is a schematic diagram of a computer system applicable according to an embodiment of the present application.
  • the computer system may include a scheduler, a power consumption controller and a plurality of processor cores.
  • a scheduler is a unit or module with a task scheduling function in a computer system.
  • the scheduler can run on the processor of the computer system, and can allocate target tasks to be processed in the computer system to the processor cores in the processor for processing according to the task scheduling method in the embodiment of the present application.
  • a processor core also known as a processor core, can be used to implement functions such as computing, accepting/storing commands, and processing data in a computer system.
  • the scheduler may select a target core for a target task among the plurality of processor cores and assign the target task to the target core. After acquiring the target task assigned by the scheduler, the target core can start running and process the target task.
  • the power consumption controller may be a unit or module used for power consumption control, energy saving feature control, etc. in the computer system, and the power consumption controller can monitor the running states of multiple processor cores.
  • the power consumption controller can record and save the relevant state information of the processor core, for example, the running frequency information, the running temperature information, the running voltage information and the running time information and so on.
  • the state information of any processor core can be processed by a related algorithm to obtain the failure information of the processor core, and the failure information can be used to indicate the lifespan of the processor core.
  • the power consumption controller can interact with the scheduler and provide the obtained failure information of multiple processor cores to the scheduler.
  • the failure information of multiple processor cores can be used as one of the basis for the scheduler to schedule tasks.
  • the scheduler performs task scheduling, it can combine the failure information of any processor core among multiple processor cores to determine the target core for the target task, so as to balance the use frequency of multiple processor cores through task scheduling, so as to maximize the frequency of use of multiple processor cores. It can realize wear leveling among multiple processor cores, so as to increase the operating frequency for high-load tasks while ensuring the protection of devices (including processors to which multiple processor cores belong and/or chips corresponding to the processors). service life.
  • the scheduler may use the failure information of multiple processor cores as one of the bases instead of limiting the only basis when scheduling tasks.
  • the computer system is configured with multiple scheduling strategies, for example, based on the application scenarios and business requirements of the computer system, the corresponding priorities or weighting factors can be configured for different scheduling strategies, and the multiple scheduling strategies and their respective The priority or weight factor of , determines the target core for the target task.
  • the target core may be determined among the multiple processor cores according to the failure information of the multiple processor cores based on the task scheduling policy of the present application, which is not limited in the present application.
  • the target task may be any task to be processed in the computer system, or may be a specific task, such as a task that needs to be processed by the processor core in a turbo state.
  • the processor core runs in the turbo state, the lifetime loss of the processor core is more serious than that in the non-turbo state. Therefore, in the embodiments of the present application, the processor core needs to be in the turbo state.
  • the task to be processed is taken as an example of a target task to illustrate the task scheduling scheme of the present application.
  • the scheduler can analyze the tasks to be processed in the computer system and the failure information of multiple processor cores to realize the required processor core. Decision and task scheduling of target tasks processed in the turbo state.
  • the task scheduling method of the present application can also be used to perform tasks that do not require the processor core to be processed in the turbo state. Task scheduling is performed, thereby reducing the lifetime loss of related devices, which is not limited in this application.
  • the computer system may further include other functional modules, and the computer system and each functional module thereof may also have different product forms, which are not limited in this application.
  • the computer system may include a processor, a plurality of processor cores and a power consumption controller (recorder) may be located in the processor, and the scheduler may run on the processor The scheduler in the operating system kernel (OS kernel) on the .
  • OS kernel operating system kernel
  • An application running in the computer system can trigger one or more tasks to be processed.
  • the scheduler in the OS kernel acquires any task to be processed and determines that the task to be processed is a target task that needs to be processed by the processor core in the turbo state, it can use the task scheduling method described in the embodiment of the present application, according to multiple The failure information of each processor core, determine the target core (for example, core1) for the target task, and assign the target task to core1, so that the target task is processed by core1 in the turbo state.
  • the power consumption controller can record and save the state information of the target core in real time, such as operating frequency information, operating voltage information, operating temperature information, and operating duration information.
  • the power consumption controller can obtain the failure information of the core1 according to the state information of the core1 and a related algorithm, and the failure information can be used to indicate the lifespan of the processor core.
  • the power consumption controller can provide the failure information of core1 to the scheduler.
  • the scheduler can update the stored failure information of multiple processor cores according to the failure information of core1 obtained from the power consumption controller, and use the failure information of multiple processor cores as one of the basis to make subsequent newly triggered targets. Tasks perform task scheduling.
  • the computer system may include multiple processors, each processor may include a power consumption controller and at least one processor core, and the multiple processor cores of the computer system may include at least one processor core located in any one of the plurality of processors.
  • the scheduler may be a scheduler in an operating system kernel (OS kernel) running on the plurality of processors.
  • OS kernel operating system kernel
  • the application software (application) running on the computer system can trigger one or more tasks to be processed. After obtaining any task to be processed, the scheduler in the OS kernel can first determine the target processing to be assigned to the task to be processed. device.
  • the first processor can be used as the first processor shown in FIG. 2a. 2a, when it is determined that the task to be processed is a target task that needs to be processed by the processor core in the turbo state, in at least one processor core of the first processor, the target task is determined target core.
  • the scheduler determines that the to-be-processed task is to be allocated to the first processor, and determines that the load utilization rate of the first processor is high and triggers the relevant scheduling condition, it can determine that the to-be-processed task needs to be processed across The target task that is scheduled by the processor and needs to be processed by the processor core in the turbo state.
  • the target processor can be determined among multiple processors, and the target processor can be configured in at least one processor core of the target processor. Determine the target core for the target task in .
  • the scheduler may adopt any suitable allocation strategy to determine the first processor to be allocated the task to be processed, and this allocation strategy is not limited in this application.
  • FIG. 1 , FIG. 2 a , and FIG. 2 b are examples of the structure of the computer system to which the embodiments of the present application are applicable, but not any limitation.
  • the computer system and its related modules may also have different products. form, which is not limited in this application.
  • the power consumption controller can be set in the scheduler, can interact with multiple processor cores, can monitor the operation of multiple processor cores in real time, record status information, and use related algorithms to obtain failure information of multiple processor cores .
  • the power consumption controller can also be a module independent of the scheduler and the processor in the computer system.
  • the power consumption controller can interact with multiple processor cores, monitor the operation of multiple processor cores in real time, and record status information 2. Obtain the failure information of multiple processor cores by using a related algorithm, and provide the failure information of multiple processor cores to the scheduler.
  • the task scheduling method in the embodiment of the present application may be implemented by the computer system and each functional module thereof in the above-mentioned FIG. 1 , FIG. 2 a , and FIG. 2 b .
  • the task scheduling method may include the following steps:
  • S310 The power consumption controller reports failure information of multiple processor cores to the scheduler. Wherein, the failure information of any processor core is used to indicate the lifetime of the processor core in the turbo state.
  • the power consumption controller responsible for monitoring the processor core can record and save the processor core in real time. status information, such as operating frequency information, operating voltage information, operating temperature information, and operating time.
  • the power consumption control can normalize and convert the state information of the processor core, and convert it into failure information of the processor core, and the failure information can be used to represent the lifespan of the processor core.
  • the power consumption controller can report the failure information of any processor core to the scheduler, so that the scheduler can perform task scheduling on the target task based on the failure information.
  • any processor core of the computer system may have multiple working gears.
  • the state information recorded and saved by the power consumption controller may be Including state information corresponding to multiple working gears.
  • the operating frequency information may include operating frequencies corresponding to multiple working gears
  • the operating voltage information may include operating voltages corresponding to multiple working gears
  • the operating temperature information may include operating temperatures corresponding to multiple working gears
  • operating duration information The running duration corresponding to multiple working gears may be included.
  • the multiple working gears of the processor core may be: the operating frequency is divided into L grades, the operating voltage is divided into M grades, and the operating temperature is divided into N grades, wherein L, M, and N are positive numbers.
  • the processor core i i is an integer, used to represent the serial number of the processor core among multiple processor cores in the computer system
  • the power consumption controller can increase the operating frequency and operating voltage corresponding to the core i.
  • the power consumption controller can record the operating frequency, operating voltage, operating temperature and the corresponding operating frequency, operating voltage, and operating temperature of each working gear when the core i is running in each working gear.
  • the running time of the working gear is summarized into the state information table corresponding to the core i.
  • the power consumption controller may perform normalization processing based on the state information table corresponding to the core i to obtain normalized data corresponding to each working gear of the core i.
  • the normalized data may include, for example, relevant information that can reflect the life loss of the processor core, such as operating temperature, operating voltage, and operating time, expressed as core i-[Vm,Tn,t], where V represents the operating voltage , T represents the operating temperature, t represents the operating time, m and n represent the operating voltage and the operating gear corresponding to the operating temperature, respectively.
  • the power consumption controller can determine the failure information of the core i according to the normalized data corresponding to each working gear of the core i, and report the failure information of the core i to the scheduler.
  • the normalized data may be the highest operating voltage, the highest operating temperature, and the corresponding operating duration corresponding to each working gear; A specified operating temperature and corresponding operating duration are used as normalized data; alternatively, the normalized data may be the average operating voltage, average operating temperature, and average operating time obtained for each working gear.
  • the failure information of core i is determined according to the normalized data corresponding to each working gear, the normalized data can be converted into reliable reliability of core i based on a set algorithm (such as a formula, or a calculation model, etc.).
  • Sexual data i.e. failure information, is expressed as core i-Ri, where R is used to represent loss information.
  • S310 only schematically indicates that the power consumption controller has the function of reporting the failure information of the processor core to the scheduler, rather than any limitation on the realization of the function.
  • the computer system includes a plurality of processors, and each power consumption controller load monitors at least one processor core, then S310 may be scheduled by each power consumption controller.
  • the processor reports the failure information of at least one processor core it is loaded with, which will not be repeated here.
  • the power consumption controller may report the failure information of multiple processor cores to the scheduler based on a predetermined time period, or may report the failure information of multiple processor cores to the scheduler when relevant conditions are satisfied (for example, the state of any processor core changes).
  • the failure information of each processor core may also be reporting the failure information of multiple processor cores to the scheduler after receiving the relevant indication information of the scheduler, which is not limited in this application.
  • the interaction between the power consumption controller and the scheduler can be realized in any suitable manner.
  • the power consumption controller can report the failure information of each processor core to the scheduler through the shared memory, which is not limited in this application. .
  • S320 The scheduler acquires a target task, where the target task is a task that needs to be processed by the processor core in a turbo state.
  • the turbo state may be determined by the load utilization rate of at least one processor core or at least one processor.
  • the scheduler may determine that there is at least one processor in the plurality of processor cores whose load exceeds the first load threshold When the core is detected, it is determined that the to-be-processed task is the target task that needs to be processed by the processor core in the turbo state.
  • the scheduler after the scheduler obtains the task to be processed, it can allocate the task to be processed to the first processor among the multiple processors according to the relevant allocation strategy .
  • the scheduler determines that the to-be-processed task is to be allocated to the first processor and the load of the first processor exceeds the second load threshold, the scheduler determines that the to-be-processed task is all that needs to be processed by the processor core in the turbo state. describe the target task.
  • the scheduler may adopt any suitable allocation strategy to allocate the task to be processed to the first processor of the plurality of processors, which is not limited in the present application.
  • the scheduler determines a target core among the multiple processor cores according to the failure information of the multiple processor cores.
  • a related task scheduler of the task scheduling policy may be configured in the scheduler in advance, including a scheduling algorithm and related scheduling conditions.
  • the scheduler may, according to the failure information of the multiple processor cores, select a target core whose failure information satisfies the corresponding scheduling condition among the multiple processor cores.
  • the scheduler may select a target core whose failure information satisfies the first scheduling condition among the multiple processor cores according to the failure information of the multiple processor cores.
  • the failure information of the processor core may be any information used to represent the lifetime of the processor core in the turbo state, for example, it may be the failure rate of the processor core.
  • the first scheduling condition may be the minimum failure rate, or may be that the failure rate is not greater than the first value, and the first value may be the average value of the failure rates of multiple processor cores.
  • the scheduler may acquire failure information of multiple processors, wherein the failure information of any processor is used to indicate the lifetime of the processor in the turbo state, and processing
  • the failure information of the processor may be obtained according to the failure information of at least one processor core located in the processor.
  • a first processor whose failure information satisfies the second scheduling condition is selected from among the multiple processors, and among the multiple processor cores, at least one processor located in the first processor is determined candidate processor core; determining the target core in the at least one candidate processor core according to the failure information of the at least one candidate processor core.
  • the failure information of the processor may also be any information used to represent the lifetime of the processor in the turbo state, for example, the failure information of the processor.
  • the second scheduling condition may be that the failure rate is the smallest, or may be that the failure rate is not greater than a second value, and the second value may be an average value of the failure rates of multiple processors.
  • the scheduler can select at least two processor cores that satisfy the relevant scheduling conditions as targets when performing task scheduling. cores, and assign the threads of the target task to the at least two processor cores respectively, which will not be repeated here.
  • the failure rate of the processor or the processor core is only one of the basis for the scheduler to perform task scheduling without any limitation.
  • the failure information may also include other information except the failure rate.
  • the scheduler may also include a task scheduling policy configured in combination with other information, which will not be repeated here.
  • S340 The scheduler allocates the target task to the target core, so that the target core processes the target task in a turbo state.
  • the scheduler may allocate the target task to the target core in the form of initiating a turbo request to the target core, and the target core may accept the turbo request initiated by the scheduler and start running.
  • the power consumption controller increases the operating frequency and operating voltage of the target core, and records and saves the state information of the target core, including operating frequency information, operating voltage information, and operating temperature information and runtime information, etc.
  • update the failure information of the target core and report the updated failure information to the scheduler, so that the scheduler can perform tasks based on the updated failure information. schedule.
  • For the recording and algorithm of the state information reference may be made to the relevant description of S310 above, which will not be repeated here.
  • the power consumption controller records and saves the processor core in the turbo state.
  • the state information of the processor core is obtained, and the failure information of the processor core is obtained and provided to the scheduler in combination with the relevant algorithm.
  • the failure information can be used to represent the life of the processor core in the turbo state.
  • the scheduler can consider the life wear of different processor cores in the turbo state, so as to balance the frequency of use of multiple processor cores, and to achieve wear balance among multiple processor cores as much as possible, so that the Increase the operating frequency for high-load tasks while ensuring the service life of the device.
  • an embodiment of the present application provides a task scheduling apparatus.
  • the task scheduling device can be applied to a computer system with multiple processor cores, such as the scheduler (or scheduler) in the computer system shown in FIG. 1, FIG. 2a, and FIG. 2b, and can realize the task shown in FIG. 3 scheduling method.
  • the task scheduling apparatus 400 may include an acquiring unit 410 , a determining unit 420 and a scheduling unit 430 .
  • the obtaining unit 410 may be configured to obtain a target task, where the target task is a task that needs to be processed by the processor core in a turbo state.
  • the target task is a task that needs to be processed by the processor core in a turbo state.
  • the determining unit 420 is configured to determine a target core among the multiple processor cores according to the failure information of the multiple processor cores; wherein, the failure information of any processor core is used to indicate that the processor core is in Lifetime in turbo state.
  • the failure information of any processor core is used to indicate that the processor core is in Lifetime in turbo state.
  • the scheduling unit 430 is configured to assign the target task to the target core, so that the target core processes the target task in a turbo state.
  • S340 for a specific implementation manner, please refer to the detailed description of S340 in the embodiment shown in FIG. 3 , which will not be repeated here.
  • the determining unit 420 is configured to: acquire failure information of the multiple processor cores; select failure information among the multiple processor cores according to the failure information of the multiple processor cores the target cores that satisfy the first scheduling condition.
  • the failure information of any processor core includes the failure rate of the processor core;
  • the first scheduling condition includes: the failure rate is the smallest; and/or the failure rate is not greater than a first value, wherein the first The value is the average of the failure rates of the plurality of processor cores.
  • the computer system includes a processor, the multiple processor cores are located in the processor, and the obtaining unit is configured to: obtain a task to be processed; determine the multiple processor cores When there is at least one processor core whose load exceeds the first load threshold, the task to be processed is determined to be the target task.
  • the obtaining unit is configured to: obtain a task to be processed; determine the multiple processor cores When there is at least one processor core whose load exceeds the first load threshold, the task to be processed is determined to be the target task.
  • the computer system includes a plurality of processors, and at least one processor core of a first processor located in the plurality of processors exists in the plurality of processor cores; the obtaining unit Used for: acquiring a task to be processed; when it is determined that the task to be processed is to be allocated to the first processor and the load of the first processor exceeds a second load threshold, determining that the task to be processed is all describe the target task.
  • the obtaining unit Used for: acquiring a task to be processed; when it is determined that the task to be processed is to be allocated to the first processor and the load of the first processor exceeds a second load threshold, determining that the task to be processed is all describe the target task.
  • the determining unit 420 is configured to: obtain the failure information of the multiple processors, wherein the failure information of any processor is used to indicate the lifetime of the processor in the turbo state; according to the failure information of multiple processors, the first processor whose failure information satisfies the second scheduling condition is selected from the multiple processors, wherein the failure information of any processor includes the failure rate of the processor,
  • the second scheduling condition includes: the failure rate is the smallest, and/or the failure rate is not greater than a second value, wherein the second value is an average value of the failure rates of the multiple processors;
  • the processor core at least one candidate processor core located in the first processor is determined; according to the failure information of the at least one candidate processor core, the at least one candidate processor core is determined in the at least one candidate processor core. target core.
  • the obtaining unit 410 is configured to: determine the failure information of the first processor core according to the stored state information of the first processor core among the plurality of processor cores, wherein the first processor core A processor core is any one of the plurality of processor cores, and the state information of the first processor core includes at least one of the following pieces of information that the first processor core operates in a turbo state: operating frequency information , operating voltage information, operating temperature information and operating time information.
  • operating frequency information operating voltage information
  • operating temperature information operating time information
  • the operating frequency information includes the operating frequencies corresponding to the multiple working gears; the operating voltage information includes all the working gears. operating voltage information corresponding to the multiple working gears; the operating temperature information includes the operating temperature corresponding to the multiple working gears; the running duration includes the running duration corresponding to the multiple working gears; the obtaining The unit is used to: normalize the operating frequency, operating voltage, operating temperature and operating duration corresponding to each working gear, and obtain the normalized data corresponding to each working gear; Normalize the data to determine the failure information of the first processor core.
  • S310 for a specific implementation manner, please refer to the detailed description of S310 in the embodiment shown in FIG. 3 , which will not be repeated here.
  • the apparatus further includes: a storage unit, configured to save the state information of the target core when the target core processes the target task.
  • a storage unit configured to save the state information of the target core when the target core processes the target task.
  • an embodiment of the present application also provides a computing device.
  • the device contains a computer system as shown in FIG. 1 , FIG. 2 a and FIG. 2 b , which can implement the task scheduling method shown in FIG. 3 , and includes a device having the function of the task scheduling apparatus shown in FIG. 4 .
  • the computing device 500 may include: at least one processor 520 and a memory 510, and the at least one processor includes multiple processor cores.
  • the memory 510 is configured to store the failure information of the multiple processor cores; the processor 520 is configured to execute the task scheduling method described in the foregoing embodiment.
  • the processor 520 and the memory 510 are connected to each other through a bus 530 .
  • the bus 530 may be a peripheral component interconnect standard (peripheral component interconnect, PCI) bus or an extended industry standard architecture (extended industry standard architecture, EISA) bus or the like.
  • PCI peripheral component interconnect
  • EISA extended industry standard architecture
  • the bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of presentation, only one thick line is used in FIG. 5, but it does not mean that there is only one bus or one type of bus.
  • the at least one processor 520 may include at least one of the following: a CPU, a microprocessor, an application specific integrated circuit (application specific integrated circuit, ASIC), or one or more integrated circuits for controlling the execution of the programs of the present application.
  • the CPU may include a power consumption controller and at least one processor core, and the power consumption controller can acquire the failure information of the at least one processor core, and convert the failure information of the at least one processor core stored in the memory 510 .
  • the memory 510 can be a ROM or other types of static storage devices that can store static information and instructions, a RAM or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (electrically erasable programmable read-only memory).
  • read-only memory EEPROM
  • compact disc read-only memory CD-ROM
  • optical disc storage including compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.
  • magnetic disk A storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, without limitation.
  • the memory may exist independently and be connected to the processor through the bus 530 .
  • the memory can also be integrated with the processor.
  • the memory 510 is used for storing computer-executed instructions for executing the solutions of the present application, and the execution is controlled by the processor 520 .
  • the processor 520 is configured to execute the computer-executed instructions stored in the memory 510, thereby implementing the task scheduling method provided by the foregoing embodiments of the present application.
  • the computer-executed instructions in the embodiment of the present application may also be referred to as application code, which is not specifically limited in the embodiment of the present application.
  • At least one item (single, species) of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.
  • “Plurality” means two or more, and other quantifiers are similar.
  • occurrences of the singular forms "a”, “an” and “the” do not mean “one or only one” unless the context clearly dictates otherwise, but rather “one or more” in one".
  • "a device” means to one or more such devices.
  • the above-mentioned embodiments it may be implemented in whole or in part by software, hardware, firmware or any combination thereof.
  • software it can be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated.
  • the computer may be a general purpose computer, special purpose computer, computer network, or other programmable device.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be downloaded from a website site, computer, server, or data center Transmission to another website site, computer, server, or data center is by wire (eg, coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer-readable storage medium may be any available medium that a computer can access, or a data storage device such as a server, a data center, or the like that includes an integration of one or more available media.
  • the usable media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, DVD), or semiconductor media (eg, Solid State Disk (SSD)), and the like.
  • a general-purpose processor may be a microprocessor, or alternatively, the general-purpose processor may be any conventional processor, controller, microcontroller, or state machine.
  • a processor may also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a digital signal processor core, or any other similar configuration. accomplish.
  • a software unit may be stored in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
  • a storage medium may be coupled to the processor such that the processor may read information from, and store information in, the storage medium.
  • the storage medium can also be integrated into the processor.
  • the processor and storage medium may be provided in the ASIC.

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Abstract

一种任务调度方法、装置以及计算机系统，涉及计算机技术领域。该方法应用于具有多个处理器核心的计算机系统，方法包括：获取目标任务，其中，所述目标任务为需要处理器核心在turbo状态下处理的任务；根据所述多个处理器核心的失效信息，在所述多个处理器核心中确定目标核心；其中，任一处理器核心的失效信息用于表示所述处理器核心在turbo状态下的寿命；将所述目标任务分配给所述目标核心，以使所述目标核心在turbo状态下对所述目标任务进行处理。由此，通过在多个处理器核心之间进行任务调度，有助于在为高负载任务提升运行频率的同时保障器件的使用寿命。

Description

任务调度方法、装置以及计算机系统
本申请要求于2020年9月25日提交中国专利局、申请号为202011024925.1、发明名称为“任务调度方法、装置以及计算机系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，特别涉及一种任务调度方法、装置以及计算机系统。
背景技术
中央处理器(central processing unit，CPU)是计算机的运算和控制核心，计算机系统中所有软件层的操作，最终都将通过指令集映射为CPU的操作。为了满足操作系统(operating system，OS)的上层工作需求，现代处理器进一步引入了诸如并行化、多核(即一个CPU中集成两个或更多个核心(core))化等功能，不断推动着上层信息系统向前发展。随着各种应用程序(application)的不断涌现和日益复杂，业内提出了睿频(turbo)技术，以提升CPU性能以符合高工作负载的应用需求。
Turbo Mode，故名思义，就是加速模式，通过分析当前CPU的负载情况，智能地完全关闭一些用不上的核心，把能源留给正在使用的核心，并使它们运行在更高的频率，进一步提升性能；相反，需要多个核心时，动态开启相应的核心，智能调整频率。这样，在不影响CPU的散热设计功耗(thermal design power，TDP)情况下，能把核心工作频率调得更高。当启动一个运行程序后，处理器会自动加速到合适的频率，而原来的运行速度会提升10％～20％，以保证程序流畅运行；当处理器处理复杂应用程序时，可自动提高运行主频以提速，轻松进行对性能要求更高的多任务处理；当进行工作任务切换时，如果只有内存和硬盘在进行主要的工作，处理器会立刻处于节电状态。这样既保证了能源的有效利用，又使程序速度大幅提升。通过智能化地加快处理器速度，从而根据应用需求最大限度地提升性能，为高负载任务提升运行主频高达20％，以获得最佳性能，即最大限度地有效提升性能以符合高工作负载的应用需求：通过给人工智能、物理模拟和渲染需求等分配多条线程处理，可以给用户带来更流畅、更逼真的游戏体验。
目前，在具备多核处理器的计算机系统中，OS内核(kernel)采用随机调度机制，将turbo任务随机调度到某个core上运行，存在将多个turbo任务分配给同一个core的情形，这会极大地增加该core的使用频率，相应地，该core的寿命会缩短，由此带来处理器的多个core的磨损不均衡，将直接影响处理器的使用寿命。为了保障处理器的使用寿命，实际使用的处理器需要压低最高的运行频率，这样会导致处理器的性能下降。
因此，如何在为高负载任务提升运行频率的同时保障器件的使用寿命，仍为亟需解决的问题。
发明内容
本申请实施例提供一种任务调度方法、装置以及计算机系统，有助于在为高负载任务提升运行频率的同时保障器件的使用寿命。
第一方面，本申请实施例提供了一种任务调度方法，该方法可以应用于具有多个处理器核心的计算机系统，该方法可以包括：获取目标任务，其中，所述目标任务为需要处理器核心在turbo状态下处理的任务；根据所述多个处理器核心的失效信息，在所述多个处理器核心中确定目标核心；其中，任一处理器核心的失效信息用于表示所述处理器核心在turbo状态下的寿命；将所述目标任务分配给所述目标核心，以使所述目标核心在turbo状态下对所述目标任务进行处理。
通过上述设计，在具有多个处理器核心的计算机系统中，可以根据处理器核心的失效信息对需要处理器核心在turbo状态下处理的目标任务进行调度，以通过均衡多个处理器核心的使用频次，尽可能地实现多个处理器核心之间的磨损均衡，以在为高负载任务提升运行频率的同时保障器件(包括处理器核心所属的处理器和/或该处理器对应的芯片等器件)的使用寿命。
在一种可能的设计中，根据所述多个处理器核心的失效信息，在所述多个处理器核心中确定目标核心，包括：获取所述多个处理器核心的失效信息；根据所述多个处理器核心的失效信息，在所述多个处理器核心中，选择失效信息满足第一调度条件的所述目标核心。其中，任一处理器核心的失效信息包括所述处理器核心的失效率；所述第一调度条件包括：失效率最小；和/或，失效率不大于第一值，其中，所述第一值为所述多个处理器核心的失效率的平均值。
通过上述设计，在对目标任务进行调度时，根据设定的第一调度条件选择目标处理器核心(简称为目标核心)，以通过均衡多个处理器核心的使用频次，尽可能地实现多个处理器核心之间的磨损均衡，在为高负载任务提升运行频率的同时保障器件的使用寿命。
在一种可能的设计中，所述计算机系统包含一个处理器，所述多个处理器核心位于所述处理器中，所述获取所述目标任务，包括：获取待处理任务；确定所述多个处理器核心中存在至少一个负载超过第一负载阈值的处理器核心时，确定所述待处理任务为所述目标任务。
通过上述设计，该方案适用的计算机系统可以为仅包含一个多核处理器的系统，通过在该多核处理器的多个处理器核心之间进行任务调度，通过均衡多个处理器核心的使用频次，尽可能地实现多个处理器核心之间的磨损均衡，在为高负载任务提升运行频率的同时保障器件的使用寿命。
在一种可能的设计中，所述计算机系统包括多个处理器，所述多个处理器核心中存在位于所述多个处理器中的第一处理器的至少一个处理器核心；所述获取所述目标任务，包括：获取待处理任务；在确定要将所述待处理任务分配给所述第一处理器，且所述第一处理器的负载超过第二负载阈值时，确定所述待处理任务为所述目标任务。
通过上述设计，该方案适用的计算机系统可以为包含多个处理器的系统，任一处理器可以包括至少一个处理器核心，计算机系统可以跨处理器实现任务调度。由此，通过在多个处理器之间进行任务调度，通过均衡多个处理器的使用频次，尽可能地实现多个处理器之间的磨损均衡，在为高负载任务提升运行频率的同时保障器件的使用寿命。可以理解的是，在具有多个处理器的计算机系统中，多个处理器可以具有不同的规格参数和能力，相应的，计算机系统在跨处理器实现任务调度时，所依据的基准可以有所不同，即可以针对不同的处理器的能力进行调度，本申请对此不做限定。
在一种可能的设计中，根据所述多个处理器核心的失效信息，在所述多个处理器核心中确定目标核心，包括：获取所述多个处理器的失效信息，其中，任一处理器的失效信息用于表示所述处理器在turbo状态下的寿命；根据所述多个处理器的失效信息，在所述多个处理器 中选择失效信息满足第二调度条件的所述第一处理器，其中，任一处理器的失效信息包括所述处理器的失效率，所述第二调度条件包括：失效率最小，和/或，失效率不大于第二值，其中，所述第二值为所述多个处理器的失效率的平均值；在所述多个处理器核心中，确定位于所述第一处理器的至少一个备选处理器核心；根据所述至少一个备选处理器核心的失效信息，在所述至少一个备选处理器核心中确定所述目标核心。
通过上述设计，在包含多个处理器的计算机系统中，在对目标任务进行调度时，可以根据设定的第二调度条件选择一个处理器，然后，将该处理器的各个处理器核心作为备选处理器核心，进而从备选处理器核心中选择目标核心，由此，通过均衡多个处理器的使用频次，尽可能地实现多个处理器之间的磨损均衡，在为高负载任务提升运行频率的同时保障器件的使用寿命。
在一种可能的设计中，获取所述多个处理器核心的失效信息，包括：根据保存的所述多个处理器核心中第一处理器核心的状态信息，确定所述第一处理器核心的失效信息，其中，所述第一处理器核心为所述多个处理器核心中的任一个，所述第一处理器核心的状态信息包括所述第一处理器核心运行在turbo状态下的以下至少一项信息：运行频率信息、运行电压信息、运行温度信息和运行时长信息。
通过上述设计，由于处理器核心在turbo状态下运行以执行目标任务的过程中，处理器核心的发热、功耗等均会对该处理器核心的寿命产生影响。通过根据处理器核心在运行过程中的状态信息确定该处理器核心的失效信息，获得能够较为准确地表示该处理器核心的寿命的失效信息，进而在进行任务调度时，尽可能地实现多个处理器核心之间的磨损均衡。
在一种可能的设计中，在所述第一处理器核心具有多个工作档位的情况下，所述运行频率信息包括所述多个工作档位对应的运行频率；所述运行电压信息包括所述多个工作档位对应的运行电压信息；所述运行温度信息包括所述多个工作档位对应的运行温度；所述运行时长包括所述多个工作档位对应的运行时长；根据保存的第一处理器核心的状态信息，确定所述第一处理器核心的失效信息，包括：对每个工作档位对应的运行频率、运行电压、运行温度和运行时长进行归一化处理，获得每个工作档位对应的归一化数据；根据每个工作档位对应的归一化数据，确定所述第一处理器核心的失效信息。
通过上述设计，通过对第一处理器核心的多个工作档位对应的状态信息进行归一化处理，获得该第一处理器核心的失效信息。
在一种可能的设计中，所述方法还包括：在所述目标核心对所述目标任务进行处理时，保存所述目标核心的所述状态信息。
通过上述设计，在目标核心对目标任务进行处理的过程中，保存该目标核心的状态信息，以便可以相应地获得该目标核心的失效信息，便于进行任务调度。可以理解的是，本申请实施例中，对于具有多个处理器核心的计算机系统，任一处理器核心均可以作为目标核心，相应地，可以在任一处理器核心在turbo状态下运行以执行目标任务的过程中，均可以保存该处理器核心的状态信息。
第二方面，本申请实施例提供了一种任务调度装置，可以应用于具有多个处理器核心的计算机系统，该任务调度装置具体可以实现上述第一方面中任务调度方法行为的功能。该任务调度装置可以为计算机系统中的硬件或软件单元，可以包括至少一个模块，该至少一个模块用于实现上述第一方面所提供的任务调度的方法。
第三方面，本申请实施例提供了一种任务调度装置，包括至少一个处理器，所述至少一个处理器与至少一个存储器耦合：所述至少一个处理器，用于执行所述至少一个存储器中存 储的计算机程序或指令，以使得所述装置执行上述第一方面的任一种可能的设计中的方法。可选地，该装置还包括通信接口，处理器与通信接口耦合。该通信接口可以是收发器或输入/输出接口；当该装置为网络设备中包含的芯片时，该通信接口可以是芯片的输入/输出接口。可选地，收发器可以为收发电路，输入/输出接口可以是输入/输出电路。
第四方面，本申请实施例提供一种计算设备，包括处理器和存储器，所述处理器包括多个处理器核心；所述存储器，用于存储所述多个处理器核心的失效信息；所述处理器，用于执行上述第一方面中任一项所述的任务调度方法。
第五方面，本申请实施例提供一种计算机系统，该计算机系统可以包括调度器、功耗控制器和多个处理器核心，所述调度器用于根据从所述功耗控制器获取的所述多个处理器核心的失效信息，实现上述第一方面所述的方法。
第六方面，本申请实施例提供了一种可读存储介质，用于存储指令，当所述指令被执行时，使上述第一方面所述的方法被实现。
第七方面，本申请实施例提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述第一方面所述的方法。
第八方面，本申请实施例提供一种芯片系统，包括：处理器，所述处理器与存储器耦合，所述存储器用于存储程序或指令，该芯片系统还可包括接口电路，所述接口电路用于接收代码指令并传输至处理器；当所述程序或指令被所述处理器执行时，使得该芯片系统实现上述第一方面的任一种可能的设计中的方法。
可选地，该芯片系统中的处理器可以为一个或多个。该处理器可以通过硬件实现也可以通过软件实现。当通过硬件实现时，该处理器可以是逻辑电路、集成电路等。当通过软件实现时，该处理器可以是一个通用处理器，通过读取存储器中存储的软件代码来实现。
可选地，该芯片系统中的存储器也可以为一个或多个。该存储器可以与处理器集成在一起，也可以和处理器分离设置，本申请并不限定。示例性的，存储器可以是非瞬时性处理器，例如只读存储器ROM，其可以与处理器集成在同一块芯片上，也可以分别设置在不同的芯片上，本申请对存储器的类型，以及存储器与处理器的设置方式不作具体限定。
本申请在上述各方面提供的实现的基础上，还可以进行进一步组合以提供更多实现。
附图说明
图1为本申请实施例适用的计算机系统的示意图；
图2a为本申请一个示例提供的计算机系统的示意图；
图2b为本申请另一个示例提供的计算机系统的示意图；
图3为本申请实施例提供的任务调度方法的流程示意图；
图4为本申请实施例提供的任务调度装置的结构示意图；
图5为本申请实施例提供的一种计算设备的示意图。
具体实施方式
目前，计算机系统的turbo状态由基本输入输出系统(basic input output system，BIOS)/负载利用率实现。若BIOS中启用了turbo mode，在单个处理器核心的负载利用率较高时，进入turbo状态，使处理器核心运行在更高的频率，以提升单个处理器核心的性能。由于处理器核心在turbo状态下运行在更高的频率时，会导致功耗增加，进一步加剧处理器核心的磨损程 度。若计算机系统中的某个处理器核心的使用频次相比于其它处理器核心的使用频次高，会导致计算机系统的多个处理器核心的磨损不均衡，将会直接影响配置有该多个处理器核心的器件(例如处理器或者芯片等器件)的寿命。
为了解决背景技术中提及的问题，本申请实施例提供了一种任务调度方法、装置以及计算机系统，有助于在为高负载任务提升运行频率的同时保障器件的使用寿命。其中，方法和装置是基于同一技术构思的，由于方法及装置解决问题的原理相似，因此装置与方法的实施可以相互参见，重复之处不再赘述。
本申请实施例中，在具有多个处理器核心的计算机系统中，对于需要处理器核心在turbo状态下处理的目标任务，根据多个处理器核心的失效信息，在多个处理器核心中确定目标核心，并将需要处理器核心在turbo状态下处理的目标任务分配给该目标核心，以使该目标核心在turbo状态下对目标任务进行处理。通过该方案，计算机系统可以根据处理器核心的失效信息对目标任务进行调度，以均衡多个处理器核心的使用频次，尽可能地实现多个处理器核心之间的磨损均衡，以在为高负载任务提升运行频率的同时均衡所有处理器核心的使用寿命，进而保证了整个计算机系统的使用寿命。
以下，对本申请中的部分用语进行解释说明，以便于本领域技术人员理解。
(1)、计算机系统，由硬件(子)系统和软件(子)系统组成。其中，硬件(子)系统包括由电、磁、光、机械等原理构成的各种物理部件的有机组合，是系统赖以工作的实体；软件(子)系统包括各种程序和文件，用于指挥全系统按指定的要求进行工作。随着计算机技术的发展，现代计算机系统小到微型计算机和个人计算机，大到巨型计算机及其网络，形态、特性多种多样，已广泛用于科学计算、事务处理和过程控制，日益深入社会各个领域，对社会的进步产生深刻影响。
在一种实现方式中，本申请实施例中的计算机系统，可以为终端装置内的计算机系统，是一种向用户提供业务服务、具有语音或数据连通功能的装置。终端装置又可以称为终端设备，还可以称为用户设备(user equipment，UE)、移动台(mobile station，MS)、移动终端(mobile terminal，MT)等，终端装置也可以为一种芯片。在本申请后续实施例和描述中，以终端设备为例进行具体描述。
例如，终端设备可以为具有无线连接功能的手持式设备、车载设备等。目前，一些终端设备的举例为：手机(mobile phone)、平板电脑、笔记本电脑、掌上电脑、移动互联网设备(mobile internet device，MID)、智能销售终端(point of sale，POS)、可穿戴设备，虚拟现实(virtual reality，VR)设备、增强现实(augmented reality，AR)设备、工业控制(industrial control)中的无线终端、无人驾驶(self driving)中的无线终端、远程手术(remote medical surgery)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端、智慧家庭(smart home)中的无线终端、各类智能仪表(智能水表、智能电表、智能燃气表)等。
在另一种实现方式中，本申请实施例中的计算机系统，可以是服务器，是提供数据连通服务的设备。由于服务器可以响应终端设备的服务请求，并进行处理，因此一般来说服务器应具备承担服务并且保障服务的能力。在本申请中，所述服务器可以为位于数据网络(data network，DN)中的服务器，例如普通服务器，云平台中的服务器；或者为位于核心网内的多接入边缘计算(multi-access edge computing，MEC)服务器等。
(2)操作系统(operating system，OS)：是运行在计算机系统上的最基本的系统软件，例如windows系统、Android系统、IOS系统、windows server系统、Netware系统、Unix系 统、Linux系统。本领域技术人员可以理解，其它操作系统中，也可以采用类似的算法实现，本申请对此不做限定。
(3)内核(kernel)：是一个操作系统的核心，是基于硬件的第一层软件扩充，提供操作系统的最基本的功能，是操作系统工作的基础，它负责管理系统的进程、内存、驱动程序、文件和网络系统，决定着系统的性能和稳定性。
(4)、失效率，是指工作到某一时刻尚未失效的产品，在该时刻后，单位时间内发生失效的概率，可以用于表示产品的寿命。失效率一般记为λ，它也是时间t的函数，故也记为λ(t)，称为失效率函数，有时也称为故障率函数或风险函数。
本申请实施例中，在产品具有不同的形态的情况下，失效率的含义有所差异。例如，若产品是指处理器核心，则处理器核心的失效率是指处理器核心在某一时刻后在单位时间内发生失效的概率；若产品是指处理器，则处理器的失效率是指该处理器在某一时刻后在单位时间内发生失效的概率；若产品是指具有一个或的多个处理器的芯片，则芯片的失效率是指该芯片在某一时刻后在单位时间内发生失效的概率。其中，处理器核心、处理器、芯片等的失效率可以通过在其使用过程中，记录相应的运行状态信息，并根据运行状态信息以及相关算法计算得到，本申请对于运行状态信息以及相关算法不做限定。
应理解的是，失效率仅是对本申请实施例中用于表示产品的寿命的参数的举例说明而非任何限定，在其它实施例中，还可以采用其它参数以及相应的参数值表示产品的寿命，本申请对此不做任何限定。
(5)、多个，是指两个或两个以上。
(6)、至少一个，是指一个或多个。
(7)、“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
下面结合附图及实施例，详细说明本申请的任务调度方案。
图1为根据本申请实施例适用的计算机系统的示意图。参阅图1所示，该计算机系统可以包括调度器、功耗控制器和多个处理器核心。
调度器为计算机系统中具有任务调度功能的单元或模块。该调度器可以运行在计算机系统的处理器上，可以根据本申请实施例的任务调度方法，将计算机系统中待处理的目标任务分配给处理器中的处理器核心进行处理。
处理器核心，又可以称为处理器内核，可以用于实现计算机系统中的计算、接受/存储命令、处理数据等功能。调度器可以在多个处理器核心中为目标任务选择目标核心，并将该目标任务分配给目标核心。目标核心在获取到调度器分配的目标任务后，能够启动运行并对该目标任务进行处理。
功耗控制器可以是计算机系统中用于进行功耗控制、节能特性控制等的单元或模块，该功耗控制器能够监测多个处理器核心的运行状态。在处理器核心的运行过程中，功耗控制器能够记录和保存该处理器核心的相关状态信息，例如，运行频率信息、运行温度信息、运行电压信息和运行时长信息等。任一处理器核心的状态信息可以在经过相关算法处理后获得该处理器核心的失效信息，该失效信息可以用于表示该处理器核心的寿命。功耗控制器可以与 调度器交互，并将所获得的多个处理器核心的失效信息提供给调度器。
多个处理器核心的失效信息可以作为调度器进行任务调度的依据之一。调度器在进行任务调度时，可以结合多个处理器核心中任一处理器核心的失效信息，为目标任务确定目标核心，以便通过任务调度来均衡多个处理器核心的使用频次，从而尽可能地实现多个处理器核心之间的磨损均衡，以在为高负载任务提升运行频率的同时保障器件(包括多个处理器核心所属的处理器和/或该处理器对应的芯片等器件)的使用寿命。
可以理解的是，本申请实施例中，调度器在进行任务调度时可以以多个处理器核心的失效信息作为依据之一而非限定唯一依据。实际应用中，若计算机系统中配置有多种调度策略，例如可以基于计算机系统的应用场景、业务需求等，为不同的调度策略配置相应的优先级或权重因子，综合多种调度策略及其各自的优先级或权重因子，为目标任务确定目标核心。在同等条件下，也可以优先基于本申请的任务调度策略，根据多个处理器核心的失效信息，在多个处理器核心中确定目标核心，本申请对此不做限定。
本申请实施例中，该目标任务可以是计算机系统中任意的待处理任务，也可以是特定任务，例如需要处理器核心在turbo状态下处理的任务。由于处理器核心在turbo状态下运行时，对处理器核心的寿命损耗，相比于非turbo状态下的寿命损耗较为严重，因此，在本申请实施例中，以需要处理器核心在turbo状态下处理的任务作为目标任务为例，来对本申请的任务调度方案进行说明，调度器可以通过对计算机系统中的待处理任务以及多个处理器核心的失效信息进行分析，实现对该需要处理器核心在turbo状态下处理的目标任务的判定和任务调度。
可以理解的是，对于具有多个处理器核心的计算机系统，在保障处理器核心的性能的同时，也可以基于本申请的任务调度方法，来为不需要处理器核心在turbo状态下处理的任务进行任务调度，由此减缓相关器件的寿命损耗，本申请对此不做限定。
本申请实施例中，计算机系统还可以包括其它功能模块，计算机系统及其各个功能模块也可以具有不同的产品形态，本申请对此不做限定。
在一种具体实现中，参阅图2a所示，计算机系统可以包含一个处理器，多个处理器核心以及功耗控制器(recorder)可以位于该处理器中，调度器可以为运行在该处理器上的操作系统内核(OS kernel)中的调度程序(scheduler)。
运行在该计算机系统中的应用软件(application)可以触发一个或多个待处理任务。OS内核中的调度程序在获取到任一个待处理任务并确定该待处理任务为需要处理器核心在turbo状态下处理的目标任务时，可以通过本申请实施例述及的任务调度方法，根据多个处理器核心的失效信息，为该目标任务确定目标核心(例如core1)，并将该目标任务分配给core1，以使core1在turbo状态对该目标任务进行处理。在core1在turbo状态下对目标任务进行处理时，功耗控制器可以实时地记录和保存该目标核心的状态信息，例如运行频率信息、运行电压信息、运行温度信息、运行时长信息等。功耗控制器可以根据core1的状态信息以及相关算法获取该core1的失效信息，该失效信息可以用于表示处理器核心的寿命。功耗控制器可以将core1的失效信息提供给调度程序。调度程序可以根据从功耗控制器获取到的core1的失效信息更新保存的多个处理器核心的失效信息，并以多个处理器核心的失效信息作为依据之一，来对后续新触发的目标任务进行任务调度。
在另一种具体实现中，参阅图2b所示，计算机系统可以包括多个处理器，每个处理器中均可以包括功耗控制器和至少一个处理器核心，计算机系统的多个处理器核心中可以包括位于多个处理器中任一个处理器的至少一个处理器核心。调度器可以为运行在该多个处理器上的操作系统内核(OS kernel)中的调度程序(scheduler)。运行在该计算机系统的应用软件 (application)可以触发一个或多个待处理任务，OS内核中的调度程序在获取到任一个待处理任务后，可以首先确定该待处理任务要分配到的目标处理器。
若调度程序采用相关分配策略确定要将该待处理任务分配给多个处理器中的第一处理器(多个处理器中的任一个)时，可以将该第一处理器作为图2a所示的处理器，参考图2a的描述，在确定该待处理任务为需要处理器核心在turbo状态下处理的目标任务时，在该第一处理器的至少一个处理器核心中，为该目标任务确定目标核心。若调度程序在确定要将待处理任务分配给所述第一处理器，且确定该第一处理器的负载利用率较高而触发相关调度条件时，则可以确定该待处理任务为需要跨处理器调度且需要处理器核心在turbo状态下处理的目标任务，此时，可以基于本申请的任务调度方法，在多个处理器中确定目标处理器，并在目标处理器的至少一个处理器核心中为该目标任务确定目标核心。
需要说明的是，图2b中，调度程序可以采用任何合适的分配策略确定要将待处理任务分配给的第一处理器，本申请对此分配策略不做限定。
可以理解的是，图1、图2a、图2b是对本申请实施例适用的计算机系统的结构的举例说明而非任何限定，在其它实施例中，计算机系统及其相关模块也可以具有不同的产品形态，本申请对此不做限定。例如，功耗控制器可以设置在调度器中，可以与多个处理器核心交互，可以实时地监测多个处理器核心的运行并记录状态信息、采用相关算法获得多个处理器核心的失效信息。或者，功耗控制器也可以是计算机系统中独立于调度器和处理器的模块，该功耗控制器可以与多个处理器核心交互，实时地监测多个处理器核心的运行并记录状态信息、采用相关算法获得多个处理器核心的失效信息，以及将多个处理器核心的失效信息提供给调度器。
本申请实施例的任务调度方法可以由上述图1、图2a、图2b中的计算机系统及其各个功能模块实现。
为了更好地理解本申请的技术方案，下面结合图3所示的方法流程图对图1、图2a、图2b中的计算机系统及其各个功能模块的功能实现的具体过程进行详细说明。如图3所示，该任务调度方法可以包括以下步骤：
S310：功耗控制器向调度器上报多个处理器核心的失效信息。其中，任一处理器核心的失效信息用于表示所述处理器核心在turbo状态下的寿命。
本申请实施例中，任一处理器核心作为目标核心，在turbo状态下启动运行并对目标任务进行处理时，负责监测该处理器核心的功耗控制器可以实时地记录和保存该处理器核心的状态信息，例如运行频率信息、运行电压信息、运行温度信息和运行时长等。功耗控制可以将该处理器核心的状态信息进行归一化转化，折算为该处理器核心的失效信息，该失效信息可以用于表示该处理器核心的寿命。功耗控制器可以将任一处理器核心的失效信息上报给调度器，以便调度器以该失效信息作为依据之一对目标任务进行任务调度。
在一种具体实现方式中，计算机系统的任一处理器核心可以具有多个工作档位，相应地，在每个处理器核心的运行过程中，功耗控制器所记录和保存的状态信息可以包括多个工作档位对应的状态信息。例如，运行频率信息可以包括多个工作档位对应的运行频率，运行电压信息可以包括多个工作档位对应的运行电压，运行温度信息可以包括多个工作档位对应的运行温度，运行时长信息可以包括多个工作档位对应的运行时长。功耗控制器在对处理器核心的状态信息进行归一化转化时，可以对每个工作档位对应的运行频率、运行电压、运行温度和运行时长进行归一化处理，获得每个工作档位对应的归一化数据，然后根据每个工作档位对应的归一化数据，确定该处理器核心的失效信息。
作为示例，假设处理器核心的多个工作档位可以为：运行频率划分为L档、运行电压划分为M档、运行温度划分为N档，其中，L、M、N为正数。假设处理器核心core i(i为整数，用于表示该处理器核心在计算机系统的多个处理器核心中的序号)被调度器确定为目标核心。该core i接受调度器发起的turbo请求而启动运行时，功耗控制器可以升高该core i对应的运行频率和运行电压。在该core i在turbo状态下运行的过程中，功耗控制器可以记录该core i运行在每个工作档位时，每个工作档位对应的运行频率、运行电压、运行温度和在每个工作档位的运行时长，汇总为该core i对应的状态信息表。功耗控制器可以基于该core i对应的状态信息表进行归一化处理，获得core i的每个工作档位对应的归一化数据。该归一化数据例如可以包括能够反映对处理器核心的寿命损耗的相关信息，例如运行温度、运行电压、运行时长，表示为core i-[Vm,Tn,t]，其中，V表示运行电压，T表示运行温度，t表示运行时长，m、n分别表示运行电压、运行温度对应的工作档位。功耗控制器可以根据core i的每个工作档位对应的归一化数据，确定core i的失效信息，并将该core i的失效信息上报给调度器。
需要说明的是，本申请实施例中，功耗控制器在对每个工作档位的状态信息进行归一化处理时，可以采用任何合适的归一化处理方式，本申请对此不做限定。作为示例，可以是以每个工作档位对应的最高运行电压、最高运行温度以及相应的运行时长作为归一化数据；或者，可以是以每个工作档位对应的任一指定运行电压、任一指定运行温度以及相应的运行时长作为归一化数据；或者，可以是以每个工作档位获得的运行电压平均值、运行温度平均值以及运行时长平均值作为归一化数据。并且，在根据每个工作档位对应的归一化数据确定core i的失效信息时，可以基于设定的算法(例如公式、或计算模型等)，将归一化数据转换为core i的可靠性数据，即失效信息，表示为core i-Ri，其中，R用于表示失信息。
可以理解的是，S310中仅示意性地表示功耗控制器具有向调度器上报处理器核心的失效信息的功能，而非对该功能的实现的任何限定。参阅图2a和图2b所示的计算机系统，若计算机系统包括多个处理器，且每个功耗控制器负载监测至少一个处理器核心，则S310则可以是由每个功耗控制器向调度器上报其所负载的至少一个处理器核心的失效信息，在此不再赘述。并且，功耗控制器可以是基于预定时间周期向调度器上报多个处理器核心的失效信息，也可以是在满足相关条件时(例如任一处理器核心的状态发生变化)向调度器上报多个处理器核心的失效信息，也可以是在接收到调度器的相关指示信息后向调度器上报多个处理器核心的失效信息，本申请对此不做限定。并且，功耗控制器与调度器之间可以基于任何合适的方式实现交互，例如功耗控制器可以通过共享内存将每个处理器核心的失效信息上报给调度器，本申请对此不做限定。
S320：调度器获取目标任务，其中，所述目标任务为需要处理器核心在turbo状态下处理的任务。
本申请实施例中，turbo状态可以由至少一个处理器核心或者至少一个处理器的负载利用率决定。
在一种具体实现方式中，参阅图2a所示的计算机系统，调度器在获取到待处理任务后，可以在确定所述多个处理器核心中存在至少一个负载超过第一负载阈值的处理器核心时，确定所述待处理任务为需要处理器核心在turbo状态下处理的所述目标任务。
在一种具体实现方式中，参阅图2b所示的计算机系统，调度器在获取到待处理任务后，可以根据相关分配策略，将该待处理任务分配给多个处理器中的第一处理器。其中，调度器在确定要将该待处理任务分配给第一处理器且第一处理器的负载超过第二负载阈值时，确定所述待处理任务为需要处理器核心在turbo状态下处理的所述目标任务。
可以理解的是，本申请实施例中，调度器可以采取任何合适的分配策略，将待处理任务分配给多个处理器中的第一处理器，本申请对此不做限定。可以根据计算机系统的应用场景、业务需求等设定每个处理器或者每个处理器核心的负载利用率要触发turbo状态应满足的负载阈值，不同处理器或者不同的处理器核心对应的负载阈值可以相同也可以不同，本申请对此不做限定。
S330：所述调度器根据所述多个处理器核心的失效信息，在所述多个处理器核心中确定目标核心。
本申请实施例中，可以预先在调度器中配置任务调度策略的相关任务调度程序，包括调度算法以及相关调度条件。调度器在进行任务调度时，可以根据多个处理器核心的失效信息，在多个处理器核心中，选择失效信息满足相应的调度条件的目标核心。
例如，参阅图2a所示的计算机系统，S330中，调度器可以根据多个处理器核心的失效信息，在多个处理器核心中，选择失效信息满足第一调度条件的目标核心。处理器核心的失效信息可以是用于表示该处理器核心在turbo状态下的寿命的任意信息，例如，可以是处理器核心的失效率。相应的，第一调度条件可以是失效率最小，也可以是失效率不大于第一值，该第一值可以是多个处理器核心的失效率的平均值。
例如，参阅图2b所示的计算机系统，S330中，调度器可以获取多个处理器的失效信息，其中，任一处理器的失效信息用于表示所述处理器在turbo状态下的寿命，处理器的失效信息可以是根据位于该处理器的至少一个处理器核心的失效信息得到的。然后，根据多个处理器的失效信息，在多个处理器中选择失效信息满足第二调度条件的第一处理器，在多个处理器核心中，确定位于所述第一处理器的至少一个备选处理器核心；根据所述至少一个备选处理器核心的失效信息，在所述至少一个备选处理器核心中确定所述目标核心。处理器的失效信息也可以是用于表示该处理器在turbo状态下的寿命的任意信息，例如处理器的失效信息。相应的，第二调度条件可以是失效率最小，也可以是失效率不大于第二值，该第二值可以是多个处理器的失效率的平均值。
可以理解的是，若计算机系统已经设置任务调度程序为在至少两个处理器核心间进行任务调度，则调度器在进行任务调度时，可以选择满足相关调度条件的至少两个处理器核心作为目标核心，并将目标任务的线程分别分配给该至少两个处理器核心，在此不再赘述。并且，处理器或者处理器核心的失效率仅是作为调度器进行任务调度的依据之一而非任何限定，在其他实施例中，失效信息也可以包括除失效率以外的其他信息，相应的，调度器中可以也包括结合其他信息配置的任务调度策略，在此不再赘述。
S340：所述调度器将所述目标任务分配给所述目标核心，以使目标核心在turbo状态下对所述目标任务进行处理。
本申请实施例中，调度器可以以向目标核心发起turbo请求的形式，将目标任务分配给目标核心，目标核心可以接受调度器发起的turbo请求并启动运行。在目标核心在turbo状态下运行的过程中，功耗控制器升高该目标核心的运行频率和运行电压，并记录和保存该目标核心的状态信息，包括运行频率信息、运行电压信息、运行温度信息和运行时长信息等。并基于所记录和保存的该目标核心的状态信息，对该目标核心的失效信息进行更新，将更新后的失效信息上报给调度器，以便调度器以更新后的失效信息作为依据之一进行任务调度。关于状态信息的记录和算法可参阅上文S310的相关描述，在此不再赘述。
至此，通过结合图1、图2a、图2b、图3介绍了本申请实施例的计算机系统以及基于该计算机系统实现的任务调度方法，通过功耗控制器记录和保存处理器核心在turbo状态下的状 态信息，并结合相关算法，获得处理器核心的失效信息后提供给调度器，该失效信息可以用于表示处理器核心在turbo状态下的寿命。调度器在进行任务调度时，可以考虑不同处理器核心在turbo状态下的寿命磨损，以均衡多个处理器核心的使用频次，尽可能地实现多个处理器核心之间的磨损均衡，以在为高负载任务提升运行频率的同时保障器件的使用寿命。
如下表1所示，基于实际仿真数据，对于具有40个核心的处理器，若完全不考虑处理器核心的磨损均衡，并在10个处理器核心间进行turbo任务的调度，该处理器在1.1v-3.6G场景下的使用寿命约为3.3年。相应的，若调度器的调度策略不考虑处理器核心在turbo状态下的使用情况，能够提供给用户(user)的芯片的寿命为3.3年。而若采用本申请实施例的任务调度方法，结合处理器核心的失效信息对turbo任务进行调度，则可以延长芯片的使用寿命至13.2年。由此，若用户对芯片的使用寿命的要求为5年，则基于本申请的任务调度方法，则可以在保障芯片的基本使用寿命的情况下，可以提高处理器核心的运行电压和运行频率，以提供更好的CPU性能。
表1
Figure PCTCN2021117933-appb-000001
基于相同的技术构思，本申请实施例提供了一种任务调度装置。该任务调度装置可以应用于具有多个处理器核心的计算机系统，例如图1、图2a、图2b所示的计算机系统中的调度器(或调度程序)，并可以实现图3所示的任务调度方法。如图4所示，该任务调度装置400可以包括获取单元410、确定单元420和调度单元430。
在一种具体实施方式中，获取单元410，可用于获取目标任务，其中，所述目标任务为需要处理器核心在turbo状态下处理的任务。具体实现方式，请参考图3所示实施例中的S320的详细描述，在此不再赘述。
确定单元420，用于根据所述多个处理器核心的失效信息，在所述多个处理器核心中确定目标核心；其中，任一处理器核心的失效信息用于表示所述处理器核心在turbo状态下的寿命。具体实现方式，请参考图3所示实施例中的S330的详细描述，在此不再赘述。
调度单元430，用于将所述目标任务分配给所述目标核心，以使所述目标核心在turbo状态下对所述目标任务进行处理。具体实现方式，请参考图3所示实施例中的S340的详细描述，在此不再赘述。
在一个具体实施方式中，确定单元420用于：获取所述多个处理器核心的失效信息；根据所述多个处理器核心的失效信息，在所述多个处理器核心中，选择失效信息满足第一调度条件的所述目标核心。其中，任一处理器核心的失效信息包括所述处理器核心的失效率；所述第一调度条件包括：失效率最小；和/或，失效率不大于第一值，其中，所述第一值为所述多个处理器核心的失效率的平均值。具体实现方式，请参考图3所示实施例中的S330的详细描述，在此不再赘述。
在一个具体实施方式中，所述计算机系统包含一个处理器，所述多个处理器核心位于所述处理器中，所述获取单元用于：获取待处理任务；确定所述多个处理器核心中存在至少一个负载超过第一负载阈值的处理器核心时，确定所述待处理任务为所述目标任务。具体实现 方式，请参考图2a以及图3所示实施例中的S330的详细描述，在此不再赘述。
在一个具体实施方式中，所述计算机系统包括多个处理器，所述多个处理器核心中存在位于所述多个处理器中的第一处理器的至少一个处理器核心；所述获取单元用于：获取待处理任务；在确定要将所述待处理任务分配给所述第一处理器，且所述第一处理器的负载超过第二负载阈值时，确定所述待处理任务为所述目标任务。具体实现方式，请参考图2b以及图3所示实施例中的S330的详细描述，在此不再赘述。
在一个具体实施方式中，确定单元420用于：获取所述多个处理器的失效信息，其中，任一处理器的失效信息用于表示所述处理器在turbo状态下的寿命；根据所述多个处理器的失效信息，在所述多个处理器中选择失效信息满足第二调度条件的所述第一处理器，其中，任一处理器的失效信息包括所述处理器的失效率，所述第二调度条件包括：失效率最小，和/或，失效率不大于第二值，其中，所述第二值为所述多个处理器的失效率的平均值；在所述多个处理器核心中，确定位于所述第一处理器的至少一个备选处理器核心；根据所述至少一个备选处理器核心的失效信息，在所述至少一个备选处理器核心中确定所述目标核心。具体实现方式，请参考图2b以及图3所示实施例中的S330的详细描述，在此不再赘述。
在一个具体实施方式中，获取单元410用于：根据保存的所述多个处理器核心中第一处理器核心的状态信息，确定所述第一处理器核心的失效信息，其中，所述第一处理器核心为所述多个处理器核心中的任一个，所述第一处理器核心的状态信息包括所述第一处理器核心运行在turbo状态下的以下至少一项信息：运行频率信息、运行电压信息、运行温度信息和运行时长信息。具体实现方式，请参考图3所示实施例中的S310的详细描述，在此不再赘述。
在一个具体实施方式中，在所述第一处理器核心具有多个工作档位的情况下，所述运行频率信息包括所述多个工作档位对应的运行频率；所述运行电压信息包括所述多个工作档位对应的运行电压信息；所述运行温度信息包括所述多个工作档位对应的运行温度；所述运行时长包括所述多个工作档位对应的运行时长；所述获取单元用于：对每个工作档位对应的运行频率、运行电压、运行温度和运行时长进行归一化处理，获得每个工作档位对应的归一化数据；根据每个工作档位对应的归一化数据，确定所述第一处理器核心的失效信息。具体实现方式，请参考图3所示实施例中的S310的详细描述，在此不再赘述。
在一个具体实施方式中，所述装置还包括：存储单元，用于在所述目标核心对所述目标任务进行处理时，保存所述目标核心的所述状态信息。具体实现方式，请参考图3所示实施例中的S310的详细描述，在此不再赘述。
可以理解的是，该装置用于上述信息接收方法时的具体实现过程以及相应的有益效果，可以参考前述方法实施例中的相关描述，这里不再赘述。
基于相同的技术构思，本申请实施例还提供了一种计算设备。该设备内部包含如图1、图2a和图2b所示的计算机系统，能够实现图3所示的任务调度方法，以及包含具有图4所示的任务调度装置的功能的器件。
参阅图5所示，该计算设备500可以包括：至少一个处理器520和存储器510，所述至少一个处理器包括多个处理器核心。所述存储器510，用于存储所述多个处理器核心的失效信息；所述处理器520，用于执行上述实施例述及的任务调度方法。
可选的，所述处理器520、所述存储器510之间通过总线530相互连接。所述总线530可以是外设部件互连标准(peripheral component interconnect，PCI)总线或扩展工业标准结构(extended industry standard architecture，EISA)总线等。所述总线可以分为地址总线、数据 总线、控制总线等。为便于表示，图5中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
所述至少一个处理器520中可以包含以下至少一项：CPU，微处理器，专用集成电路(application specific integrated circuit，ASIC)，或一个或多个用于控制本申请方案程序执行的集成电路。其中，所述CPU中可以包括功耗控制器和至少一个处理器核心，所述功耗控制器能够获取所述至少一个处理器核心的失效信息，并将所述至少一个处理器核心的失效信息存储至所述存储器510中。
存储器510可以是ROM或可存储静态信息和指令的其他类型的静态存储设备，RAM或者可存储信息和指令的其他类型的动态存储设备，也可以是电可擦可编程只读存储器(electrically erasable programmable read-only memory，EEPROM)、只读光盘(compact disc read-only memory，CD-ROM)或其他光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。存储器可以是独立存在，通过总线530与处理器相连接。存储器也可以和处理器集成在一起。
其中，存储器510用于存储执行本申请方案的计算机执行指令，并由处理器520来控制执行。处理器520用于执行存储器510中存储的计算机执行指令，从而实现本申请上述实施例提供的任务调度方法。
可选的，本申请实施例中的计算机执行指令也可以称之为应用程序代码，本申请实施例对此不作具体限定。
本领域普通技术人员可以理解：本申请中涉及的第一、第二等各种数字编号仅为描述方便进行的区分，并不用来限制本申请实施例的范围，也表示先后顺序。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。“至少一个”是指一个或者多个。至少两个是指两个或者多个。“至少一个”、“任意一个”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b，或c中的至少一项(个、种)，可以表示：a，b，c，a-b，a-c，b-c，或a-b-c，其中a，b，c可以是单个，也可以是多个。“多个”是指两个或两个以上，其它量词与之类似。此外，对于单数形式“a”，“an”和“the”出现的元素(element)，除非上下文另有明确规定，否则其不意味着“一个或仅一个”，而是意味着“一个或多于一个”。例如，“a device”意味着对一个或多个这样的device。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包括一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例 如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘(Solid State Disk，SSD))等。
本申请实施例中所描述的各种说明性的逻辑单元和电路可以通过通用处理器，数字信号处理器，专用集成电路(ASIC)，现场可编程门阵列(FPGA)或其它可编程逻辑装置，离散门或晶体管逻辑，离散硬件部件，或上述任何组合的设计来实现或操作所描述的功能。通用处理器可以为微处理器，可选地，该通用处理器也可以为任何传统的处理器、控制器、微控制器或状态机。处理器也可以通过计算装置的组合来实现，例如数字信号处理器和微处理器，多个微处理器，一个或多个微处理器联合一个数字信号处理器核，或任何其它类似的配置来实现。
本申请实施例中所描述的方法或算法的步骤可以直接嵌入硬件、处理器执行的软件单元、或者这两者的结合。软件单元可以存储于RAM存储器、闪存、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、可移动磁盘、CD-ROM或本领域中其它任意形式的存储媒介中。示例性地，存储媒介可以与处理器连接，以使得处理器可以从存储媒介中读取信息，并可以向存储媒介存写信息。可选地，存储媒介还可以集成到处理器中。处理器和存储媒介可以设置于ASIC中。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管结合具体特征及其实施例对本申请进行了描述，显而易见的，在不脱离本申请的精神和范围的情况下，可对其进行各种修改和组合。相应地，本说明书和附图仅仅是所附权利要求所界定的本申请的示例性说明，且视为已覆盖本申请范围内的任意和所有修改、变化、组合或等同物。显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包括这些改动和变型在内。

Claims (21)

  1. 一种任务调度方法，其特征在于，应用于具有多个处理器核心的计算机系统，所述方法包括：
    获取目标任务，其中，所述目标任务为需要处理器核心在turbo状态下处理的任务；
    根据所述多个处理器核心的失效信息，在所述多个处理器核心中确定目标核心；其中，任一处理器核心的失效信息用于表示所述处理器核心在turbo状态下的寿命；
    将所述目标任务分配给所述目标核心，以使所述目标核心在turbo状态下对所述目标任务进行处理。
  2. 根据权利要求1所述的方法，其特征在于，根据所述多个处理器核心的失效信息，在所述多个处理器核心中确定目标核心，包括：
    获取所述多个处理器核心的失效信息；
    根据所述多个处理器核心的失效信息，在所述多个处理器核心中，选择失效信息满足第一调度条件的所述目标核心。
  3. 根据权利要求2所述的方法，其特征在于，任一处理器核心的失效信息包括所述处理器核心的失效率；所述第一调度条件包括：
    失效率最小；和/或，失效率不大于第一值，其中，所述第一值为所述多个处理器核心的失效率的平均值。
  4. 根据权利要求1-3中任一项所述的方法，其特征在于，所述计算机系统包含一个处理器，所述多个处理器核心位于所述处理器中，所述获取所述目标任务，包括：
    获取待处理任务；
    确定所述多个处理器核心中存在至少一个负载超过第一负载阈值的处理器核心时，确定所述待处理任务为所述目标任务。
  5. 根据权利要求1-3中任一项所述的方法，其特征在于，所述计算机系统包括多个处理器，所述多个处理器核心中存在位于所述多个处理器中的第一处理器的至少一个处理器核心；所述获取所述目标任务，包括：
    获取待处理任务；
    在确定要将所述待处理任务分配给所述第一处理器，且所述第一处理器的负载超过第二负载阈值时，确定所述待处理任务为所述目标任务。
  6. 根据权利要求5所述的方法，其特征在于，根据所述多个处理器核心的失效信息，在所述多个处理器核心中确定目标核心，包括：
    获取所述多个处理器的失效信息，其中，任一处理器的失效信息用于表示所述处理器在turbo状态下的寿命；
    根据所述多个处理器的失效信息，在所述多个处理器中选择失效信息满足第二调度条件的所述第一处理器，其中，任一处理器的失效信息包括所述处理器的失效率，所述第二调度条件包括：失效率最小，和/或，失效率不大于第二值，其中，所述第二值为所述多个处理器的失效率的平均值；
    在所述多个处理器核心中，确定位于所述第一处理器的至少一个备选处理器核心；
    根据所述至少一个备选处理器核心的失效信息，在所述至少一个备选处理器核心中确定所述目标核心。
  7. 根据权利要求2-6中任一项所述的方法，其特征在于，获取所述多个处理器核心的失效信息，包括：
    根据保存的所述多个处理器核心中第一处理器核心的状态信息，确定所述第一处理器核心的失效信息，其中，所述第一处理器核心为所述多个处理器核心中的任一个，所述第一处理器核心的状态信息包括所述第一处理器核心运行在turbo状态下的以下至少一项信息：运行频率信息、运行电压信息、运行温度信息和运行时长信息。
  8. 根据权利要求7所述的方法，其特征在于，在所述第一处理器核心具有多个工作档位的情况下，所述运行频率信息包括所述多个工作档位对应的运行频率；所述运行电压信息包括所述多个工作档位对应的运行电压信息；所述运行温度信息包括所述多个工作档位对应的运行温度；所述运行时长信息包括所述多个工作档位对应的运行时长；
    根据保存的第一处理器核心的状态信息，确定所述第一处理器核心的失效信息，包括：
    对每个工作档位对应的运行频率、运行电压、运行温度和运行时长进行归一化处理，获得每个工作档位对应的归一化数据；
    根据每个工作档位对应的归一化数据，确定所述第一处理器核心的失效信息。
  9. 根据权利要求7或8所述的方法，其特征在于，所述方法还包括：
    在所述目标核心对所述目标任务进行处理时，保存所述目标核心的所述状态信息。
  10. 一种任务调度装置，其特征在于，应用于具有多个处理器核心的计算机系统，包括：
    获取单元，用于获取目标任务，其中，所述目标任务为需要处理器核心在turbo状态下处理的任务；
    确定单元，用于根据所述多个处理器核心的失效信息，在所述多个处理器核心中确定目标核心；其中，任一处理器核心的失效信息用于表示所述处理器核心在turbo状态下的寿命；
    调度单元，用于将所述目标任务分配给所述目标核心，以使所述目标核心在turbo状态下对所述目标任务进行处理。
  11. 根据权利要求10所述的装置，其特征在于，所述确定单元用于：
    获取所述多个处理器核心的失效信息；根据所述多个处理器核心的失效信息，在所述多个处理器核心中，选择失效信息满足第一调度条件的所述目标核心。
  12. 根据权利要求11所述的装置，其特征在于，任一处理器核心的失效信息包括所述处理器核心的失效率；所述第一调度条件包括：
    失效率最小；和/或，失效率不大于第一值，其中，所述第一值为所述多个处理器核心的失效率的平均值。
  13. 根据权利要求10-12中任一项所述的装置，其特征在于，所述计算机系统包含一个处理器，所述多个处理器核心位于所述处理器中，所述获取单元用于：
    获取待处理任务；
    确定所述多个处理器核心中存在至少一个负载超过第一负载阈值的处理器核心时，确定所述待处理任务为所述目标任务。
  14. 根据权利要求10-12中任一项所述的装置，其特征在于，所述计算机系统包括多个处理器，所述多个处理器核心中存在位于所述多个处理器中的第一处理器的至少一个处理器核心；所述获取单元用于：
    获取待处理任务；
    在确定要将所述待处理任务分配给所述第一处理器，且所述第一处理器的负载超过第二负载阈值时，确定所述待处理任务为所述目标任务。
  15. 根据权利要求14所述的装置，其特征在于，所述确定单元用于：
    获取所述多个处理器的失效信息，其中，任一处理器的失效信息用于表示所述处理器在 turbo状态下的寿命；
    根据所述多个处理器的失效信息，在所述多个处理器中选择失效信息满足第二调度条件的所述第一处理器，其中，任一处理器的失效信息包括所述处理器的失效率，所述第二调度条件包括：失效率最小，和/或，失效率不大于第二值，其中，所述第二值为所述多个处理器的失效率的平均值；
    在所述多个处理器核心中，确定位于所述第一处理器的至少一个备选处理器核心；
    根据所述至少一个备选处理器核心的失效信息，在所述至少一个备选处理器核心中确定所述目标核心。
  16. 根据权利要求11-15中任一项所述的装置，其特征在于，所述获取单元用于：
    根据保存的所述多个处理器核心中第一处理器核心的状态信息，确定所述第一处理器核心的失效信息，其中，所述第一处理器核心为所述多个处理器核心中的任一个，所述第一处理器核心的状态信息包括所述第一处理器核心运行在turbo状态下的以下至少一项信息：运行频率信息、运行电压信息、运行温度信息和运行时长信息。
  17. 根据权利要求16所述的装置，其特征在于，在所述第一处理器核心具有多个工作档位的情况下，所述运行频率信息包括所述多个工作档位对应的运行频率；所述运行电压信息包括所述多个工作档位对应的运行电压信息；所述运行温度信息包括所述多个工作档位对应的运行温度；所述运行时长包括所述多个工作档位对应的运行时长；
    所述获取单元用于：
    对每个工作档位对应的运行频率、运行电压、运行温度和运行时长进行归一化处理，获得每个工作档位对应的归一化数据；
    根据每个工作档位对应的归一化数据，确定所述第一处理器核心的失效信息。
  18. 根据权利要求16或17所述的装置，其特征在于，所述装置还包括：
    存储单元，用于在所述目标核心对所述目标任务进行处理时，保存所述目标核心的所述状态信息。
  19. 一种计算设备，其特征在于，包括处理器和存储器，所述处理器包括多个处理器核心；
    所述存储器，用于存储所述多个处理器核心的失效信息；
    所述处理器，用于执行权利要求1-9中任一项所述的任务调度方法。
  20. 一种计算机系统，其特征在于，包括调度器、功耗控制器和多个处理器核心，所述调度器用于根据从所述功耗控制器获取的所述多个处理器核心的失效信息，实现如权利要求1-9中任一项所述的方法。
  21. 一种计算机可读介质，其特征在于，用于存储计算机程序，该计算机程序包括用于执行如权利要求1-9中任一项所述的方法的指令。
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