WO2022062524A1 - 内存管理方法、装置、设备和存储介质 - Google Patents

内存管理方法、装置、设备和存储介质 Download PDF

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Publication number
WO2022062524A1
WO2022062524A1 PCT/CN2021/102857 CN2021102857W WO2022062524A1 WO 2022062524 A1 WO2022062524 A1 WO 2022062524A1 CN 2021102857 W CN2021102857 W CN 2021102857W WO 2022062524 A1 WO2022062524 A1 WO 2022062524A1
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Prior art keywords
target
preset
field
information
memory page
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PCT/CN2021/102857
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English (en)
French (fr)
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周轶刚
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华为技术有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0882—Page mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures

Definitions

  • the present application relates to the field of computer technologies, and in particular, to a memory management method, apparatus, device, and storage medium.
  • the present application provides a memory management method, apparatus, device and storage medium to solve the problem of low memory management efficiency and affecting the overall performance of the system.
  • the present application provides a memory management method, including:
  • the target PTE includes first information, where the first information is used to represent the data access heat of the target memory page; according to the first information, determine the target storage location of the target memory page; exchange the target memory page to the target storage location.
  • the data access heat of the target memory page is determined according to the first information carried in the target PTE, and the target memory page is swapped (Swap) to the data access heat according to the data access heat of the target memory page. matches the target storage location. Since the target PTE carries the first information that can characterize the data access heat, the CPU can directly exchange the corresponding target memory page according to the target PTE to the target memory location that matches the data access heat of the target memory page. There is no need to use the method of polling the page table in the memory to count the page access heat.
  • the method provided by the embodiment of the present application can obtain more memory page information and is more efficient, so it can be based on data
  • the access heat achieves more effective memory management, makes the CPU's memory management more efficient, reduces the CPU workload, and improves the effectiveness of memory management and overall system performance.
  • the data access heat is determined according to the access frequency of the target memory page.
  • the first information includes a field value set in a first preset field of the target PTE, where the first preset field is used to represent the data access heat level of the target memory page; according to the first information, determine The target storage location of the target memory page includes: determining the data access heat level of the target memory page according to the field value of the first preset field; and determining the target storage location matching the data access heat level of the target memory page.
  • the target PTE can carry the information of the data access heat level corresponding to the target memory page, so that the CPU can read the field of the first preset field of the target PTE by reading
  • the data access heat level of the target memory page is determined, and then the target memory page is swapped to the target storage location matching the data access heat level, so as to improve the use efficiency of the local high-speed memory.
  • the data access heat level includes hot data and warm data; if the data access heat level is hot data, the target storage location matching the target memory page is local memory; if the data access heat level is If the data is warm, the target storage location that matches the target memory page is the remote memory. Among them, the delay of the remote memory is greater than that of the local memory.
  • the data access heat level also includes cold data; if the data access heat level is cold data, the target storage location matching the target memory page is persistent memory or hard disk. Among them, the time delay of persistent memory or hard disk is greater than that of remote memory.
  • the target memory pages are divided into three data access heat levels: hot data, warm data and cold data, and according to different data access heat levels, the target memory pages are respectively exchanged to local memory, remote memory and persistent memory.
  • Memory or hard disk since the read and write performance gradually decreases from local memory, remote memory to persistent memory or hard disk, when data is read and written, the delay increases in turn, but at the same time, the cost also gradually decreases. Therefore, accessing different data
  • the target memory pages of the heat level are respectively swapped to different target storage locations, which can optimize the memory usage efficiency, reduce the memory usage cost, and improve the performance under the unit memory cost in the system.
  • the first information includes a field value set in a second preset field of the target PTE, and the second preset field is used to represent the current storage location of the target memory page; swap the target memory page to the target storage location, including: if the target storage location is the same as the current storage location corresponding to the field value of the second preset field, then keep the target memory page in the current storage location; if the target storage location is the current storage location corresponding to the field value of the second preset field If the storage location is different, the target memory page is swapped to the target storage location.
  • the CPU can determine the current value of the target memory page by reading the field value of the second preset field of the PTE. location to determine whether the target memory page needs to be swapped. Since the way that the CPU reads the field value of the preset field in the target PTE is more efficient than the way of obtaining memory information through software, the efficiency of memory management can be improved and the overall performance of the system can be improved.
  • the method further includes: acquiring a TLB entry (TLB entry) corresponding to the target memory page in a translation look-aside buffer (Translation Look-aside Buffer, TLB), wherein the TLB entry includes the first Second information, the second information is used to represent the access frequency of the target memory page; according to the second information, the first information in the target PTE is determined.
  • TLB entry TLB entry
  • TLB buffer Translation Look-aside Buffer
  • the TLB entry can record the access frequency of the target memory page, and the access frequency of the target memory page can indicate the data of the target memory page Access heat, therefore, according to the second information, the first information used to characterize the data access heat in the target PTE can be determined. Since TLB entries are generated by TLB, counting the number of accesses to target memory pages through TLB is more efficient and faster than querying and counting memory information through software, reducing CPU resource consumption and improving memory management. effectiveness.
  • the second information includes a field value of a third preset field of the TLB entry, and the third preset field is used to record the access times of the target memory page within a preset duration.
  • the preset duration is the life cycle of the TLB entry.
  • the method further includes: if the arithmetic logic unit (Arithmetic Logic Unit, ALU) hits (hit) the TLB entry when accessing the TLB, accumulating the number of visits by the field value of the third preset field.
  • ALU Arimetic Logic Unit
  • a third preset field is set in the TLB entry, and when the ALU accesses the TLB and hits the TLB entry corresponding to the target memory page, the number of accesses is accumulated by the field value of the third preset field, thereby determining the target memory page frequency of visits.
  • the field value of the third preset field returns to zero.
  • determining the first information in the target PTE according to the second information includes: determining the first information in the target PTE according to the relationship between the field value of the third preset field and the preset access times threshold first information.
  • the first information includes a field value set in a first preset field of the target PTE, and the field value of the first preset field is used to represent the data access heat level of the target memory page, according to the third preset field value.
  • the preset access times threshold is set in the TLB access count threshold register.
  • the field value of the first preset field in the first information is determined correspondingly through the relationship between the field value of the third preset field and the preset access times threshold, so that the first information can correspond to different data Access the heat rating.
  • the target memory page is divided into hot data and warm data through the first information, so as to perform memory management respectively, which can further improve the accuracy of memory management and improve the efficiency of memory usage.
  • the first information includes a field value set in a first preset field of the target PTE and a field value set in a fourth preset field of the target PTE, the first preset field and the fourth preset field Used to jointly characterize the data access heat level of the target memory page, and determine the first information in the target PTE according to the relationship between the field value of the third preset field and the preset access times threshold, including: the lifetime of the TLB entry At the end of the period, if the field value of the third preset field is greater than the first times threshold, the field value of the first preset field and the field value of the fourth preset field are set as the first preset value; wherein, when When the field value of the first preset field and the field value of the fourth preset field are set to the first preset value, the first information corresponds to hot data; at the end of the life cycle of the TLB entry, if the third preset field The field value is less than or equal to the first time threshold and greater than the second time threshold, then the field
  • the second time threshold is smaller than the first time threshold; when the field value of the first preset field is the second preset value and the field value of the fourth preset field is the first preset value, the first The information corresponds to the temperature data; at the end of the life cycle of the TLB entry, if the field value of the third preset field is less than or equal to the second threshold value, the field value of the fourth preset field is set to the second preset value; Wherein, when the field value of the fourth preset field is the second preset value, the first information corresponds to cold data.
  • the field value of the first preset field and the field value of the fourth preset field in the first information are determined correspondingly through the relationship between the field value of the third preset field and the preset access times threshold, so that the The first information may correspond to different data access heat levels.
  • the target memory page is divided into cold data, hot data and warm data through the first information, so that memory management is performed separately, which can further improve the accuracy of memory management and improve the efficiency of memory use.
  • the present application provides a memory management device, including:
  • an acquisition module configured to acquire the target PTE in the memory, the target PTE includes first information, and the first information is used to represent the data access heat of the target memory page;
  • a determining module configured to determine the target storage location of the target memory page according to the first information
  • the swap module is used to swap the target memory page to the target storage location.
  • the data access heat of the target memory page is determined according to the first information carried in the target PTE, and the target memory page is swapped (Swap) to the data access heat according to the data access heat of the target memory page. matches the target storage location. Since the target PTE carries the first information that can characterize the data access heat, the CPU can directly exchange the corresponding target memory page according to the target PTE to the target memory location that matches the data access heat of the target memory page. There is no need to use the method of polling the page table in the memory to count the page access heat.
  • the method provided by the embodiment of the present application can obtain more memory page information and is more efficient, so it can be based on data
  • the access heat achieves more effective memory management, and at the same time makes the CPU's management of memory more efficient, reduces the workload of the CPU, and improves the effectiveness of memory management and overall system performance.
  • the data access heat is determined according to the access frequency of the target memory page.
  • the first information includes a field value set in a first preset field of the target PTE, and the first preset field is used to represent the data access heat level of the target memory page; the determining module is specifically used for: According to the field value of the first preset field, the data access heat level of the target memory page is determined; the target storage location matching the data access heat level of the target memory page is determined.
  • the target PTE can carry the information of the data access heat level corresponding to the target memory page, so that the CPU can read the field of the first preset field of the target PTE by reading
  • the data access heat level of the target memory page is determined, and then the target memory page is swapped to the target storage location matching the data access heat level, so as to improve the use efficiency of the local high-speed memory.
  • the data access heat level includes hot data and warm data; if the data access heat level is hot data, the target storage location matching the target memory page is local memory; if the data access heat level is If the data is warm, the target storage location that matches the target memory page is the remote memory.
  • the data access heat level further includes cold data. If the data access heat level is cold data, the target storage location matching the target memory page is persistent memory or hard disk.
  • the target memory pages are divided into three data access heat levels: hot data, warm data and cold data, and according to different data access heat levels, the target memory pages are respectively exchanged to local memory, remote memory and persistent memory.
  • the target memory pages with different data access heat levels are respectively swapped to different target storages.
  • the location can optimize the memory usage efficiency, reduce the memory usage cost, and improve the performance under the unit cost of memory in the system.
  • the first information includes a field value set in a second preset field of the target PTE, and the second preset field is used to represent the current storage location of the target memory page;
  • the swap module is specifically used for: if If the target storage location is the same as the current storage location corresponding to the field value of the second preset field, then keep the target memory page in the current storage location; if the target storage location is different from the current storage location corresponding to the field value of the second preset field, then Swap the target memory page to the target storage location.
  • the CPU can determine the current value of the target memory page by reading the field value of the second preset field of the PTE. location to determine whether the target memory page needs to be swapped. Since the way that the CPU reads the field value of the preset field in the target PTE is more efficient than the way of obtaining memory information through software, the efficiency of memory management can be improved and the overall performance of the system can be improved.
  • the apparatus further includes: a processing module configured to: acquire a TLB entry corresponding to the target memory page in the TLB, wherein the TLB entry includes second information, and the second information is used to represent the target The access frequency of the memory page; according to the second information, determine the first information in the target PTE.
  • a processing module configured to: acquire a TLB entry corresponding to the target memory page in the TLB, wherein the TLB entry includes second information, and the second information is used to represent the target The access frequency of the memory page; according to the second information, determine the first information in the target PTE.
  • the TLB entry can record the access frequency of the target memory page, and the access frequency of the target memory page can indicate the data of the target memory page Access heat, therefore, according to the second information, the first information used to characterize the data access heat in the target PTE can be determined. Since TLB entries are generated by TLB, counting the number of accesses to target memory pages through TLB is more efficient and faster than querying and counting memory information through software, reducing CPU resource consumption and improving memory management. effectiveness.
  • the second information includes a field value of a third preset field of the TLB entry, and the third preset field is used to record the access times of the target memory page within a preset duration.
  • the preset duration is the life cycle of the TLB entry.
  • the processing module is further configured to: if the arithmetic logic unit ALU hits a TLB entry when accessing the TLB, accumulate the number of accesses by the field value of the third preset field.
  • a third preset field is set in the TLB entry, and when the ALU accesses the TLB and hits the TLB entry corresponding to the target memory page, the number of accesses is accumulated by the field value of the third preset field, thereby determining the target memory page frequency of visits.
  • the field value of the third preset field returns to zero.
  • the processing module when determining the first information in the target PTE according to the second information, is specifically configured to: according to the relationship between the field value of the third preset field and the preset access times threshold , and determine the first information in the target PTE.
  • the first information includes a field value set in a first preset field of the target PTE, and the field value of the first preset field is used to represent the data access heat level of the target memory page, and the processing module is based on The relationship between the field value of the third preset field and the preset access times threshold, when determining the first information in the target PTE, is specifically used: at the end of the life cycle of the TLB entry, if the value of the third preset field is If the field value is greater than the preset access times threshold, the field value of the first preset field in the first information is set to the first preset value; at the end of the life cycle of the TLB entry, if the field value of the third preset field If it is not greater than the preset access times threshold, the field value of the first preset field in the first information is set as the second preset value.
  • the preset access times threshold is set in the TLB access count threshold register.
  • the first information includes a field value set in a first preset field of the target PTE and a field value set in a fourth preset field of the target PTE, the first preset field and the fourth preset field Used to jointly represent the data access heat level of the target memory page, when the processing module determines the first information in the target PTE according to the relationship between the field value of the third preset field and the preset access times threshold, the processing module is specifically used for: At the end of the life cycle of the TLB entry, if the field value of the third preset field is greater than the first threshold of times, the field value of the first preset field and the field value of the fourth preset field are set as the first preset field value.
  • the field value of the first preset field is set to For the second preset value, the field value of the fourth preset field is set as the first preset value; wherein, the second threshold of times is smaller than the first threshold of times; when the life cycle of the TLB entry ends, if the third preset If the field value of the field is less than or equal to the second time threshold, the field value of the fourth preset field is set as the second preset value.
  • the field value of the first preset field and the field value of the fourth preset field in the first information are determined correspondingly through the relationship between the field value of the third preset field and the preset access times threshold, so that the The first information may correspond to different data access heat levels.
  • the target memory page is divided into cold data, hot data and warm data through the first information, so that memory management is performed separately, which can further improve the accuracy of memory management and improve the efficiency of memory use.
  • an embodiment of the present application provides an electronic device including: a memory, a processor, and a computer program; wherein the computer program is stored in the memory and configured to be provided by the processor executing any implementation manner of the above first aspect Methods.
  • an embodiment of the present application provides an electronic device, including: a processor, a memory, and a transceiver; the processor is used to control the transceiver to send and receive signals; the memory is used to store a computer program; The stored computer program enables the electronic device to execute the method provided by any one of the implementation manners of the above first aspect.
  • an embodiment of the present application provides a computer-readable storage medium, including computer code, which, when executed on a computer, enables the computer to execute the method provided by any one of the implementation manners of the above first aspect.
  • an embodiment of the present application provides a computer program product, including program code.
  • the program code executes the method provided by any one of the implementations of the first aspect above.
  • the present application further provides a chip including a processor.
  • the processor is configured to call and run the computer program stored in the memory, so as to execute corresponding operations and/or processes in the memory management method of the embodiments of the present application.
  • the chip further includes a memory, the memory and the processor are connected to the memory through a circuit or a wire, and the processor is used for reading and executing the computer program in the memory.
  • the chip further includes a communication interface, and the processor is connected with the communication interface.
  • the communication interface is used to receive data and/or information to be processed, and the processor acquires the data and/or information from the communication interface and processes the data and/or information.
  • the communication interface may be an input-output interface.
  • FIG. 1 is a schematic diagram of an application scenario provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a system architecture provided by an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of a memory management method provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of including first information in a target PTE provided by an embodiment of the present application.
  • 5A is a schematic diagram of determining a target storage location of a target memory page according to first information according to an embodiment of the present application
  • 5B is another schematic diagram of determining a target storage location of a target memory page according to first information according to an embodiment of the present application
  • 5C is another schematic diagram of determining a target storage location of a target memory page according to first information according to an embodiment of the present application
  • FIG. 6 is a schematic flowchart of another memory management method provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a TLB entry provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of including second information in a TLB entry according to an embodiment of the present application.
  • FIG. 9 is a schematic flowchart of another memory management method provided by an embodiment of the present application.
  • 9A is a schematic diagram of the composition of a target PTE provided by an embodiment of the present application.
  • FIG. 10 is a schematic flowchart of still another memory management method provided by an embodiment of the present application.
  • FIG. 11 is a schematic block diagram of a memory management apparatus provided by an embodiment of the present application.
  • FIG. 12 is a schematic block diagram of another memory management apparatus provided by an embodiment of the present application.
  • FIG. 13 is a schematic block diagram of the structure of an electronic device according to an embodiment of the present application.
  • FIG. 14 is a schematic block diagram of the structure of another electronic device according to an embodiment of the present application.
  • the Translation Look-aside Buffer also known as the page table buffer, is a buffer of the CPU and is used by the memory management unit to improve the translation speed of virtual addresses to physical addresses.
  • the TLB has a fixed number of space slots for tab page table entries that map virtual addresses to physical addresses. Its search key is virtual address, and its search result is physical address. If the requested virtual address exists in the TLB, a very fast matching result will be obtained, and then the obtained physical address can be used to access the memory; if the requested virtual address is not in the TLB, the tag page table will be used for virtual-real address translation, And the access speed of the tab page table is much slower than TLB.
  • a page table entry is a data structure in the page table (page table) used to represent the mapping relationship between virtual addresses and physical addresses.
  • PTE page table entry
  • Multiple refers to two or more, and other quantifiers are similar.
  • “And/or”, which describes the relationship between the associated objects, means that there can be three kinds of relationships, for example, A and/or B, which can mean that A exists alone, A and B exist at the same time, and B exists alone.
  • the character "/" generally indicates that the associated objects are an "or” relationship.
  • Correspondence may refer to an association relationship or binding relationship, and the correspondence between A and B refers to an association relationship or binding relationship between A and B.
  • FIG. 1 is a schematic diagram of an application scenario provided by an embodiment of the present application.
  • a server or server group that provides cloud services and cloud computing for terminal devices is connected to various types of storage in order to reduce the cost of using memory.
  • Devices such as high-performance memory installed locally and low-cost hard disks installed locally or remotely, for memory data frequently accessed in the system, that is, hot data, are installed in local high-performance memory to improve system performance; For infrequently accessed memory data, that is, cold data, it is set in the hard disk with higher transmission delay but lower cost to reduce the memory cost.
  • low-cost memory such as SCM memory module, can also be set.
  • serial bus memory as an intermediate form between local memory and hard disk in performance and cost, that is, far memory, using remote memory to store between "hot data” and “cold data”
  • the "warm data” between “data” can further refine the memory data management and improve the performance of the system without adding too much cost.
  • the technical solution usually adopted is to query and count memory usage information through software, and perform heat statistics of content data through pure software, which needs to consume CPU resources and increase CPU usage.
  • some memory access information cannot be accessed only through the software level, resulting in inaccurate judgment of memory heat and poor real-time performance. Therefore, the overall performance of the system is reduced and the memory usage efficiency is low.
  • FIG. 2 is a schematic diagram of a system architecture provided by an embodiment of the present application.
  • an ALU responsible for logical operations is provided in the CPU.
  • the ALU sets the corresponding virtual address according to the specific application.
  • the TLB in the CPU is accessed.
  • the TLB entry is cached to represent the mapping relationship between virtual addresses and physical addresses, and a PTE corresponding to the TLB entry.
  • the ALU searches the TLB, if it hits the target TLB entry, you can The physical address corresponding to the virtual address is quickly determined, and further, the access to the memory data stored at the physical address is realized.
  • the target TLB entry is not hit, the PTE in the page table in the local memory is accessed to determine the physical address corresponding to the virtual address, thereby realizing the access to the memory data stored at the physical address.
  • the memory management method provided by the embodiment of the present application, in the system architecture shown in FIG. 2, enables PTE to carry The first information representing the data access heat of the target memory page, so that the target memory page is exchanged to the target storage location according to the first information, so as to realize the differentiated storage of the memory data, improve the memory usage efficiency, and improve the overall performance of the system.
  • the execution body of the method may be an electronic device, specifically, a server, or a memory management system in the electronic device. As shown in Figure 3, the method includes:
  • the PTE is an entry used to represent the mapping relationship between the virtual address and the physical address.
  • the corresponding physical address can be obtained by using the PTE, and then the memory page stored at the physical address can be obtained.
  • the target memory page refers to the memory page to be processed
  • the target PTE is the PTE corresponding to the physical address of the target memory page
  • the target PTE is in one-to-one correspondence with the target memory page.
  • the CPU in the server reads a target PTE every preset cycle; for another example, the CPU in the server reads a target PTE under a preset trigger condition, Specifically, the preset trigger condition is, for example, that the CPU receives a user instruction, which is not specifically limited here.
  • the first information is information used to represent the data access heat of the target memory page, and the first information is carried in the target PTE.
  • FIG. 4 is a schematic diagram of including first information in a target PTE according to an embodiment of the present application.
  • the first information may be implemented by setting a preset field in the target PTE.
  • the target PTE includes a first preset field, and the field value of the first preset field is used to represent the first information. More specifically, for example, when the field value is 0, it represents a type of target memory page. Data access heat; when the value of this field is 1, it indicates another data access heat of the target memory page.
  • the position of the first preset field in the target PTE may be set as required, which is not specifically limited here.
  • the data access heat is determined according to the access frequency of the target memory page.
  • the access frequency of the target memory page is higher, it means that the target memory page has a higher probability of being accessed later.
  • the heat of the target memory page is also higher; on the contrary, when the access frequency of the target memory page is lower, it means that the probability of the target memory page being accessed later is smaller, and the heat of the target memory page is also lower.
  • the data access heat is determined according to the delay requirement information of the target memory page.
  • the delay requirement information represents the maximum delay that can be accepted when the target memory page is accessed; the delay The smaller the required information, the more sensitive the server is to the access delay of the target memory page, and the higher the target memory page heat; on the contrary, the larger the delay requirement information is, the less sensitive the server is to the access delay of the target memory page, the higher the target memory page is. The lower the page heat.
  • the first information can represent the data access heat of the corresponding target memory page, and according to the data access heat of the target storage location, the target memory page is exchanged to the matching target storage location, which can balance system performance and cost.
  • the target memory page is exchanged to a storage medium with higher processing efficiency for high-temperature data, such as local high-speed memory, to improve data processing efficiency;
  • the target memory page is swapped to a storage medium with lower cost for processing low-temperature data, such as a hard disk, so as to reduce the cost of memory usage.
  • the data access heat may include a plurality of data access heat levels.
  • FIG. 5A is a schematic diagram of determining a target storage location of a target memory page according to the first information according to an embodiment of the present application.
  • the data access heat level may include hot data and cold data. According to the preset mapping relationship, the target storage location corresponding to the hot data is the local memory, and the target storage location corresponding to the cold data is the hard disk.
  • 5B is another schematic diagram of determining the target storage location of the target memory page according to the first information provided by the embodiment of the application, as shown in FIG.
  • the data access heat level can include hot data, warm data and cold data
  • the target storage location corresponding to the hot data is the local memory
  • the target storage location corresponding to the cold data is the remote memory
  • the target storage location corresponding to the cold data is the hard disk.
  • the data access heat level can be divided into more levels as needed.
  • FIG. 5C is another schematic diagram of determining the target storage location of the target memory page according to the first information provided by the embodiment of the present application, as shown in FIG. 5C .
  • each data access heat level corresponds to a target storage location, and then the target memory pages of different data access heat levels are stored separately to the matching target storage locations, i.e. "storage medium 1" to "storage medium M".
  • storage medium 1 to “storage medium M” for storing data from "1st heat level” to “Nth heat level”
  • the performance of the equipment also decreases, for example, the data delay gradually increases, and the read and write speed gradually decreases, but at the same time, the equipment cost of "storage medium 1" to “storage medium M” decreases accordingly. In this way, data with different data access heat is correspondingly stored in a matching target storage location, which realizes more refined management of memory and improves memory usage efficiency.
  • Swap may refer to the process of paging, that is, the process of transferring data from the disk to the memory, or the process of transferring data from the memory to the disk.
  • the process of swapping the target memory page to the target storage location that is, the process of scheduling the target memory page to a memory with high read and write performance, or a disk with low read and write performance.
  • This process can be performed by the CPU or the Memory Management Unit (MMU). )implemented.
  • MMU Memory Management Unit
  • the system should not only load data into memory with high read and write performance for access to ensure system performance, but also schedule some infrequently used data to low-cost memory.
  • the system needs to dynamically manage the memory according to the operation of the server, and schedule the data to the best storage location.
  • the target storage location is determined according to the data access heat of the target memory page. Therefore, the target storage location can be considered as the best storage location corresponding to the target memory page, and the target memory page is exchanged to the target storage location. It can improve the overall performance and memory usage efficiency of the system.
  • the data access heat of the target memory page is determined according to the first information carried in the target PTE, and the target memory page is exchanged to the data access heat matching the data access heat according to the data access heat of the target memory page.
  • Target storage location Since the target PTE carries the first information that can characterize the data access heat, the CPU can directly exchange the corresponding target memory page according to the target PTE to the target memory location that matches the data access heat of the target memory page. There is no need to use the method of polling the page table in the memory to count the page access heat.
  • the method provided by the embodiment of the present application can obtain more memory page information and is more efficient, so it can be based on data
  • the access heat achieves more effective memory management, and at the same time makes the CPU's management of memory more efficient, reduces the workload of the CPU, and improves the effectiveness of memory management and overall system performance.
  • FIG. 6 is a schematic flowchart of another memory management method provided by an embodiment of the present application. As shown in FIG. 6 , the memory management method provided by this embodiment is based on the memory management method provided by the embodiment shown in FIG. In order to determine the step of the first information of the target PTE, the method includes:
  • TLB entry corresponding to the target memory page in the TLB, wherein the TLB entry includes second information, and the second information is used to represent the access frequency of the target memory page.
  • FIG. 7 is a schematic diagram of a TLB entry provided by an embodiment of the present application.
  • multiple TLB entries are cached in the TLB to represent the mapping relationship between different virtual addresses and physical addresses.
  • the CPU when it provides a virtual address, it searches through multiple TLB entries in the TLB. If the TLB entry in the TLB can be hit, the corresponding physical address can be quickly obtained and the CPU can quickly access the memory page.
  • TLB entry corresponding to the target memory page in the TLB there may be various timings for acquiring the TLB entry corresponding to the target memory page in the TLB, for example, acquiring a certain TLB entry in the TLB at a preset cycle, and for example, in the At the end of the period, the TLB entry is obtained, which will not be repeated here.
  • the second information is information used to represent the access frequency of the target memory page, and the second information is carried in the TLB entry corresponding to the target memory page.
  • FIG. 8 is a schematic diagram of a TLB entry including second information according to an embodiment of the present application.
  • the second information may be implemented by a preset field set in the TLB entry.
  • the TLB entry includes a third preset field, and the field value of the third preset field is used to record the access times of the target memory page within the preset time period. More specifically, for example, if the value of this field is 28, it means The target memory page is accessed 28 times within the preset duration.
  • the preset duration is the life cycle of the TLB entry.
  • the field value of the third preset field is determined by accumulating the accessed times of the target memory page within the preset duration and, specifically, for example: if the Arithmetic Logic Unit (ALU) is accessing the TLB If the TLB entry corresponding to the target memory page is hit, the field value of the third preset field is incremented by 1, so that the field value of the third preset field is incremented by 1 until the life of the TLB entry corresponding to the target memory page is reached. After the period ends, it is moved out of the TLB, and the total number of field values of the third preset field is counted, and determined as the second information.
  • ALU Arithmetic Logic Unit
  • the life cycle of the TLB entry after the life cycle of the TLB entry ends, it may be loaded into the TLB again after a period of time, and by accumulating the field value of the third preset field, the number of times the TLB entry is accessed is reset. Statistics are performed to realize real-time dynamic adjustment of the target memory page corresponding to the TLB entry. Therefore, when the life cycle of the TLB entry ends, the field value of the third preset field is reset to zero.
  • the second information can represent the access frequency of the target memory page, the higher the access frequency of the target memory page, the higher the probability of the target memory page being accessed later, and the higher the target memory page heat; , when the access frequency of the target memory page is lower, it means that the probability of the target memory page being accessed later is smaller, and the heat of the target memory page is also lower, that is, the access frequency represented by the second information is the same as that represented by the first information.
  • Data access heat with corresponding relationship. Therefore, according to the preset mapping relationship, the data access heatness that matches the access frequency represented by the second information, that is, the first information, can be determined.
  • the second information is "30”, which indicates that the target memory data is accessed 30 times in the life cycle of the TLB entry.
  • One information is “1”, indicating that the data access heat level of the target memory page is "hot data”.
  • the second information is "4", which indicates that the target memory data is accessed 4 times in the life cycle of the TLB entry.
  • the first information of the target PTE corresponding to the second information "4" is: "0" indicates that the data access heat level of the target memory page is "warm data”.
  • the preset mapping relationship between the second information and the first information may be a discrete numerical mapping table or a continuous mapping model, and the mapping relationship may be preset by a user, or may be a
  • the execution subject of the example is determined by self-learning according to historical data, which is not specifically limited here.
  • implementation manners of S203 to S205 are the same as the implementation manners of S101 to S103 in the embodiment shown in FIG. 3 of the present invention, and details are not repeated here.
  • FIG. 9 is a schematic flowchart of another memory management method provided by an embodiment of the present application. As shown in FIG. 9 , the memory management method provided by this embodiment is based on the memory management method provided by the embodiment shown in FIG. 6 . The step of determining the target storage location is further refined, and the method includes:
  • TLB entry corresponding to the target memory page in the TLB, wherein the TLB entry includes a third preset field, and the field value of the third preset field is used to record the number of accesses of the target memory page within a preset duration .
  • the third preset field may be a field set at a specified position in the TLB entry, for example, the field identifier of the third preset field is AC (Access Count), and the length of the AC field is 8 bits (bit), Set the location after the virtual address and the physical address.
  • the identification name, field length, and field position of the third preset field in this embodiment are all exemplary, and the third preset field may also be set in other field positions with other data lengths, and here I won't repeat them one by one.
  • a certain TLB entry in the TLB is obtained at a preset cycle, and the memory page corresponding to the TLB entry is the target. memory page.
  • the life cycle of a certain TLB entry ends, the TLB entry is acquired, and the memory page corresponding to the TLB entry is the target memory page.
  • the TLB entry is obtained, and the field value of the third preset field of the TLB entry is read to obtain the target memory page in the The total number of times the TLB entry was accessed during its lifetime.
  • the TLB no longer caches the mapping relationship between the virtual address and the physical address corresponding to the TLB entry, and the mapping relationship information is set by The corresponding in-memory target PTE is carried.
  • the CPU polls all PTEs in memory to obtain the target PTE.
  • S303 Determine the field value of the first preset field, the field value of the second preset field, and the field value of the fourth preset field of the target PTE, respectively.
  • the field identifier of the first preset field of the target PTE is ACF (Access Count Flag)
  • the first preset field occupies one bit (bit)
  • the field value of the first preset field is 0 or 1
  • the method for determining the field value of the first preset field includes: when the life cycle of the TLB entry corresponding to the target memory page ends, counting the third preset field in the TLB entry If the field value of the third preset field in the TLB entry is greater than the preset access times threshold, the field value of the first preset field of the target PTE is set to the first preset value, such as 1; If the field value of the third preset field in the TLB entry is not greater than the preset access times threshold, the field value of the first preset field of
  • the second preset field of the target PTE is used to represent the current storage location of the target memory page.
  • the second preset field of the target PTE The field identifier is RF (Reside in far memory Flag), the second preset field occupies one bit (bit), and the field value of the second preset field is 0 or 1.
  • the field value of the second preset field is It is determined according to the current storage medium information of the target memory page, more specifically, for example, when the target storage medium is stored in the local memory, the field value of the second preset field is 0; When the terminal memory is used, the field value of the second preset field is 1.
  • the fourth preset field of the target PTE is used to represent the accessed record of the target memory page.
  • the fourth preset field of the target PTE The field identifier is AF (Access Flag), the fourth preset field occupies one bit (bit), and the field value of the fourth preset field is 0 or 1.
  • the field value of the fourth preset field is based on the target PTE. The access situation is determined, for example, when the target PTE is accessed within the preset access duration, the field value of the fourth preset field in the target PET is set to 1, otherwise, the fourth preset field value in the target PET is set to 1. Set the field value of the field to 0.
  • S304 Determine the target storage location according to the field value of the first preset field and/or the field value of the fourth preset field of the target PTE.
  • the field value of the first preset field and the field value of the fourth preset field in the target PTE are respectively used to represent the data access heat level of the target memory page and the accessed record of the target memory page.
  • the accessed record of the target memory page represented by the field value of the fourth preset field if the target memory page has not been accessed out of date within the preset access time period, it means that the target memory page is cold data, and at this time, the target memory page is Swap memory pages to low-cost storage media such as hard disks to reduce memory usage costs; if the target memory page is accessed out of date within the preset access time period, it means that the target memory page is not cold data.
  • the steps in this embodiment illustrate the step of determining the target storage location by using the field value of the first preset field and the field value of the fourth preset field.
  • Field value determine the target storage location that matches the data access heat level represented by the field value of the first preset field, or, determine the value represented by the field value of the fourth preset field only by the field value of the fourth preset field Whether there is a target storage location that matches the access record is not repeated here.
  • S305 Swap the target memory page to the target storage location according to the field value of the second preset field.
  • the target storage location After the target storage location is determined, it is necessary to determine whether the target memory page needs to be interacted with according to the current location of the target memory page. Specifically, for example, if the current location of the target memory page is consistent with the target storage location, it is not necessary to page interaction; if the current location of the target memory page is inconsistent with the target storage location, the target memory page is interacted with the target storage location. More specifically, for example, if the current location of the target memory page is the hard disk; the target storage location is local memory, then the target memory page is swapped to the local memory to improve the speed of accessing the target memory page; The location is local memory; the target storage location is remote memory, then the target memory page is swapped to the remote memory to improve memory usage efficiency. For another example, if the current location of the target memory page is local memory, and the target storage location is also local memory, five teams of target memory pages are exchanged.
  • a schematic flowchart of another memory management method as shown in FIG. 10 , the method includes:
  • the CPU counts and judges whether the preset period has timed out, and if it has timed out, execute S402; if it has not timed out, continue to execute S401.
  • the CPU reads a target PTE from the PTE sequence in the memory.
  • the PTE sequence refers to a sequence composed of PTEs, and the CPU sequentially reads the PTEs in the PTE sequence in a polling manner.
  • step S403 The CPU determines whether the field value of the AF field of the target PTE is 1, and if it is 1, executes step S404; if it is not equal to 1, executes step S406.
  • the AF field of the target PTE is used to represent the accessed record of the target memory page. If the field value of the AF field is 1, then the target PTE has been accessed within the preset period, and then jumps to S404 to further perform the target PTE. The data access heat level of the corresponding target memory page is judged; if the field value of the AF field is 0, the target memory page corresponding to the target PTE is cold data, so no processing is required.
  • step S404 The CPU determines whether the field value of the ACF field of the target PTE is 1, and if it is 1, executes step S405; if it is not equal to 1, executes step S407.
  • the ACF field of the target PTE is used to represent the data access heat level of the target memory page. If the field value of the ACF field is equal to 1, the target memory page corresponding to the target PTE is hot data; if the field value of the ACF field is equal to 0 , the target memory page corresponding to the target PTE is warm data.
  • step S406 the CPU judges whether the target PTE is the last PTE in the PTE sequence, and if so, ends the method; if not, executes step S402.
  • step S407 the CPU determines whether the field value of the RF field of the target PTE is 1, and if it is equal to 1, executes step S406; if it is not equal to 1, executes step S408.
  • the RF field of the target PTE is used to represent the current storage location of the target memory page. If the field value of the RF field is 1, the target memory page is stored in the remote memory; if the field value of the RF field is 0, the target memory page is stored in the remote memory. Memory pages are stored in local memory.
  • the CPU sets the field value of the RF field of the PTE to 1.
  • the CPU deletes the LTB entry corresponding to the PTE from the LTB.
  • FIG. 11 is a schematic block diagram of a memory management apparatus provided by an embodiment of the present application.
  • the memory management apparatus 5 provided in the embodiment of the present application may be the electronic device in the foregoing method embodiments, or may be one or more chips in the electronic device.
  • the memory management apparatus 5 may be used to execute part or all of the functions of the electronic device in the foregoing method embodiments.
  • the memory management device 5 may include the following modules.
  • the obtaining module 51 is used for obtaining the target PTE in the memory, the target PTE includes first information, and the first information is used to characterize the data access heat of the target memory page.
  • the determining module 52 is configured to determine the target storage location of the target memory page according to the first information.
  • the swap module 53 is used to swap the target memory page to the target storage location.
  • the data access heat of the target memory page is determined according to the first information carried in the target PTE, and the target memory page is exchanged to the data access heat matching the data access heat according to the data access heat of the target memory page.
  • Target storage location Since the target PTE carries the first information that can characterize the data access heat, the CPU can directly exchange the corresponding target memory page according to the target PTE to the target memory location that matches the data access heat of the target memory page. There is no need to use the method of polling the page table in the memory to count the page access heat.
  • the method provided by the embodiment of the present application can obtain more memory page information and is more efficient, so it can be based on data
  • the access heat achieves more effective memory management, and at the same time makes the CPU's management of memory more efficient, reduces the workload of the CPU, and improves the effectiveness of memory management and overall system performance.
  • the memory management apparatus 5 of the embodiment shown in FIG. 11 can be used to execute the technical solution of the embodiment shown in FIG. 3 in the above method, and the implementation principle and technical effect thereof are similar, and will not be repeated here.
  • FIG. 12 is a schematic block diagram of another memory management apparatus provided by an embodiment of the present application. On the basis of the device shown in FIG. 11, as shown in FIG. 12, in the memory management device 6:
  • the data access heat is determined according to the access frequency of the target memory page.
  • the first information includes a field value set in a first preset field of the target PTE, and the first preset field is used to represent the data access heat level of the target memory page; the determining module 52 is specifically used for : determine the data access heat level of the target memory page according to the field value of the first preset field; determine the target storage location matching the data access heat level of the target memory page.
  • the determination module 52 may execute step S102 of the method shown in FIG. 3 , or step S204 of the method shown in FIG. 6 , or steps S303 and S304 of the method shown in FIG. 9 .
  • the target PTE can carry the information of the data access heat level corresponding to the target memory page, so that the CPU can read the field of the first preset field of the target PTE by reading
  • the data access heat level of the target memory page is determined, and then the target memory page is swapped to the target storage location matching the data access heat level, so as to improve the use efficiency of the local high-speed memory.
  • the data access heat level includes hot data and warm data; if the data access heat level is hot data, the target storage location matching the target memory page is local memory; if the data access heat level is If the data is warm, the target storage location that matches the target memory page is the remote memory.
  • the data access heat level further includes cold data. If the data access heat level is cold data, the target storage location matching the target memory page is persistent memory or hard disk.
  • the target memory pages are divided into three data access heat levels: hot data, warm data and cold data, and according to different data access heat levels, the target memory pages are respectively exchanged to local memory, remote memory and persistent memory.
  • the target memory pages with different data access heat levels are respectively swapped to different target storages.
  • the location can optimize the memory usage efficiency, reduce the memory usage cost, and improve the performance under the unit cost of memory in the system.
  • the first information includes a field value set in a second preset field of the target PTE, and the second preset field is used to represent the current storage location of the target memory page;
  • the exchange module 53 is specifically used for: If the target storage location is the same as the current storage location corresponding to the field value of the second preset field, the target memory page is kept in the current storage location; if the target storage location is different from the current storage location corresponding to the field value of the second preset field, The target memory page is swapped to the target storage location.
  • the switching module 53 may execute step S103 of the method shown in FIG. 3 , or step S205 of the method shown in FIG. 6 , or step S305 of the method shown in FIG. 9 .
  • the CPU can determine the current value of the target memory page by reading the field value of the second preset field of the PTE. location to determine whether the target memory page needs to be swapped. Since the way that the CPU reads the field value of the preset field in the target PTE is more efficient than the way of obtaining memory information through software, the efficiency of memory management can be improved and the overall performance of the system can be improved.
  • the apparatus further includes: a processing module 61, configured to: obtain a TLB entry corresponding to the target memory page in the TLB, wherein the TLB entry includes second information, and the second information is used to represent The access frequency of the target memory page; according to the second information, determine the first information in the target PTE.
  • the processing module 61 may execute steps S201 to S202 of the method shown in FIG. 6 , or steps S301 to S302 of the method shown in FIG. 9 .
  • the TLB entry can record the access frequency of the target memory page, and the access frequency of the target memory page can indicate the data of the target memory page Access heat, therefore, according to the second information, the first information used to characterize the data access heat in the target PTE can be determined. Since TLB entries are generated by TLB, counting the number of accesses to target memory pages through TLB is more efficient and faster than querying and counting memory information through software, reducing CPU resource consumption and improving memory management. effectiveness.
  • the second information includes a field value of a third preset field of the TLB entry, and the third preset field is used to record the access times of the target memory page within a preset duration.
  • the preset duration is the life cycle of the TLB entry.
  • the processing module 61 is further configured to: if the arithmetic logic unit ALU hits the TLB entry when accessing the TLB, accumulate the number of accesses by the field value of the third preset field. At this time, the processing module 61 may perform step S201 of the method shown in FIG. 6 , or may perform step S301 of the method shown in FIG. 9 .
  • a third preset field is set in the TLB entry, and when the ALU accesses the TLB and hits the TLB entry corresponding to the target memory page, the number of accesses is accumulated by the field value of the third preset field, thereby determining the target memory page frequency of visits.
  • the processing module 61 is further configured to: when the life cycle of the TLB entry ends, return the field value of the third preset field to zero.
  • the processing module 61 when determining the first information in the target PTE according to the second information, is specifically configured to: according to the difference between the field value of the third preset field and the preset access times threshold relationship to determine the first information in the target PTE. At this time, the processing module 61 may execute step S202 of the method shown in FIG. 6 , or may execute step S303 of the method shown in FIG. 9 .
  • the first information includes a field value set in the first preset field of the target PTE, and the field value of the first preset field is used to represent the data access heat level of the target memory page.
  • the processing module 61 may execute step S202 of the method shown in FIG. 6 , or may execute step S303 of the method shown in FIG. 9 .
  • the preset access times threshold is set in the TLB access count threshold register.
  • the first information includes a field value set in a first preset field of the target PTE and a field value set in a fourth preset field of the target PTE, the first preset field and the fourth preset field Used to jointly represent the data access heat level of the target memory page, when the processing module determines the first information in the target PTE according to the relationship between the field value of the third preset field and the preset access times threshold, the processing module is specifically used for: At the end of the life cycle of the TLB entry, if the field value of the third preset field is greater than the first threshold of times, the field value of the first preset field and the field value of the fourth preset field are set as the first preset field value.
  • the processing module 61 may execute step S202 of the method shown in FIG. 6 , or may execute step S303 of the method shown in FIG. 9 .
  • the field value of the first preset field and the field value of the fourth preset field in the first information are determined correspondingly through the relationship between the field value of the third preset field and the preset access times threshold, so that the The first information may correspond to different data access heat levels.
  • the target memory page is divided into cold data, hot data and warm data through the first information, so that memory management is performed separately, which can further improve the accuracy of memory management and improve the efficiency of memory use.
  • the memory management apparatus of the embodiment shown in FIG. 12 can be used to execute the technical solution of any one of the embodiments shown in FIG. 3 or FIG. 6 or FIG. 9 in the above method, and its implementation principle and technical effect are similar, and will not be repeated here.
  • this embodiment does not depend on whether the embodiment shown in FIG. 11 is implemented, and this embodiment can be implemented independently.
  • FIG. 13 is a schematic block diagram of the structure of an electronic device according to an embodiment of the present application.
  • the electronic device 7 includes: a memory 71 , a processor 72 and a computer program; wherein, the computer program is stored in the memory 71 and is configured to execute the steps of FIG. 3 by the processor 72 , or to execute The steps of FIG. 5 , or alternatively, the steps of FIG. 14 are performed.
  • the processor 72 is used to implement the modules of FIGS. 11 and 12 .
  • the memory 71 and the processor 72 are connected through a bus 73 .
  • FIG. 14 is a schematic block diagram of the structure of another electronic device provided by this embodiment of the application.
  • the network device provided by this embodiment includes: a transceiver 81 , a memory 82 , a processor 83 and Computer program.
  • the processor 83 is used to control the transceiver 81 to send and receive signals, and the computer program is stored in the memory 82 and is configured to be executed by the processor 83 to implement the method provided by any of the implementations corresponding to FIG. 3 to FIG. 10 of the present invention .
  • the transceiver 81 , the memory 82 , and the processor 83 are connected through a bus 84 .
  • An embodiment of the present application further provides a server, including a processor, where the processor is configured to execute a computer program to execute the method provided in any of the above implementation manners corresponding to FIGS. 3 to 10 ; the server further includes a communication interface; the processor communicates with interface connection.
  • Embodiments of the present application further provide a computer-readable storage medium, including computer code, which, when executed on a computer, enables the computer to execute the method provided in any of the implementation manners corresponding to FIGS. 3 to 10 .
  • Embodiments of the present application further provide a computer program product, including program code.
  • the program code executes the method provided by any one of the implementations corresponding to FIGS. 3 to 10 .
  • An embodiment of the present application further provides a chip including a processor.
  • the processor is used to call and run the computer program stored in the memory to execute the corresponding operations and/or processes performed by the electronic device in the memory management method provided in any of the implementation manners corresponding to FIGS. 3 to 10 .
  • the chip further includes a memory, the memory and the processor are connected to the memory through a circuit or a wire, and the processor is used for reading and executing the computer program in the memory.
  • the chip further includes a communication interface, and the processor is connected to the communication interface.
  • the communication interface is used to receive data and/or information to be processed, and the processor acquires the data and/or information from the communication interface and processes the data and/or information.
  • the communication interface may be an input-output interface.
  • a computer program product includes one or more computer instructions.
  • the computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • Computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server, or data center over a wire (e.g.
  • a computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, a data center, or the like that includes an integration of one or more available media.
  • Useful media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, DVD), or semiconductor media (eg, Solid State Disk (SSD)), and the like.
  • Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.
  • a storage medium can be any available medium that can be accessed by a general purpose or special purpose computer.

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Abstract

本发明实施例公开了一种内存管理方法、装置、设备和存储介质，通过获取内存中的目标PTE，目标PTE中包括第一信息，该第一信息用于表征目标内存页面的数据访问热度；根据该第一信息，确定目标内存页面的目标存储位置；将目标内存页面交换至目标存储位置。由于目标PTE中携带了能够表征数据访问热度的第一信息，因此CPU可以直接根据该目标PTE，将对应的目标内存页面交换至与该目标内存页面的数据访问热度相匹配的目标存储位置，而无需通过软件轮询内存中页表的方法统计页面访问热度，使CPU对内存的管理效率更高，降低了CPU的工作负载，提高了内存管理的有效性和系统综合性能。

Description

内存管理方法、装置、设备和存储介质
本申请要求于2020年9月22日提交中国专利局、申请号为202011003346.9、发明名称为“内存管理方法、装置、设备和存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，尤其涉及一种内存管理方法、装置、设备和存储介质。
背景技术
随着云计算、云服务的发展和普及，越来越多的用户利用云服务来开展业务。为了给用户提供优质的云服务，云服务运营商承担了巨大的服务器投入成本，其中，内存成本占据了相当大的比重，如何提高内存使用效率，降低内存成本，是目前普遍存在的问题。
现有技术中，为了提高内存的使用效率，设计了相关的内存管理软件，通过统计内存页面的使用情况，对内存进行管理和释放，使内存能够提高使用效率。
然而，通过软件对内存进行统计的方式，需要消耗中央处理器(Central Processing Unit，CPU)的资源，增加CPU负载，同时部分内存访问信息仅通过软件层面无法访问，因此，造成了内存管理效率低下，影响系统综合性能的问题。
发明内容
本申请提供一种内存管理方法、装置、设备和存储介质，以解决内存管理效率低下，影响系统综合性能的问题。
第一方面，本申请提供一种内存管理方法，包括：
获取内存中的目标PTE，目标PTE中包括第一信息，该第一信息用于表征目标内存页面的数据访问热度；根据该第一信息，确定目标内存页面的目标存储位置；将目标内存页面交换至目标存储位置。
本申请中，通过获取目标PTE，根据目标PTE中携带的第一信息确定目标内存页面的数据访问热度，并根据目标内存页面的数据访问热度将目标内存页面交换(Swap)至与该数据访问热度相匹配的目标存储位置。由于目标PTE中携带了能够表征数据访问热度的第一信息，因此CPU可以直接根据该目标PTE，将对应的目标内存页面交换至与该目标内存页面的数据访问热度相匹配的目标存储位置，而无需通过软件轮询内存中页表的方法统计页面访问热度，相比软件轮询的方式，本申请实施例提供的方法更高获取更多的内存页面信息，且效率更高，因此可以基于数据访问热度实现更有效的内存管理，使CPU对内存的管理效率更高，降低了CPU的工作负载，提高了内存管理的有效性和系统综合性能。
在一种可能的实现方式中，数据访问热度是根据目标内存页面的访问频次确定的。
在一种可能的实现方式中，第一信息包括设置于目标PTE第一预设字段的字段值，该第一预设字段用于表征目标内存页面的数据访问热度等级；根据第一信息，确定目标内存页面的目标存储位置，包括：根据第一预设字段的字段值，确定目标内存页面的数据访问热度等级；确定与目标内存页面的数据访问热度等级相匹配的目标存储位置。
本申请中，通过在目标PTE上设置第一预设字段，使目标PTE能够携带目标内存页面对应的数据访问热度等级的信息，从而使CPU能够通过读取目标PTE的第一预设字段的字段值，而确定目标内存页面的数据访问热度等级，进而将目标内存页面交换至与该数据访问热度等级相匹配的目标存储位置，提高本地高速内存的使用效率。
在一种可能的实现方式中，数据访问热度等级包括热数据和温数据；若数据访问热度等级为热数据，则与目标内存页面相匹配的目标存储位置为本地内存；若数据访问热度等级为温数据，则与目标内存页面相匹配的目标存储位置为远端内存。其中，远端内存的时延大于本地内存。
在一种可能的实现方式中，数据访问热度等级还包括冷数据；若数据访问热度等级为冷数据，则与目标内存页面相匹配的目标存储位置为持久内存或硬盘。其中，持久内存或硬盘的时延大于远端内存。
本申请中，通过将目标内存页面分为热数据、温数据和冷数据三种数据访问热度等级，并根据不同的数据访问热度等级，将目标内存页面分别交换至本地内存、远端内存和持久内存或硬盘，由于从本地内存、远端内存至持久内存或硬盘，读写性能逐渐降低，在进行数据读写时，时延依次增加，但同时，成本也逐渐降低，因此，将不同数据访问热度等级的目标内存页面分别交换至不同的目标存储位置，可以起到优化内存使用效率，降低内存使用成本的目的，提高系统中内存单位成本下的效能。
在一种可能的实现方式中，第一信息包括设置于目标PTE第二预设字段的字段值，第二预设字段用于表征目标内存页面的当前存储位置；将目标内存页面交换至目标存储位置，包括：若目标存储位置与第二预设字段的字段值对应的当前存储位置相同，则保留目标内存页面在当前存储位置；若目标存储位置与第二预设字段的字段值对应的当前存储位置不同，则将目标内存页面交换至目标存储位置。
本申请中，通过在目标PTE中设置用于表征目标内存页面的当前存储位置的第二预设字段，使CPU能够通过读取PTE的第二预设字段的字段值，确定目标内存页面的当前位置，进而确定是否需要对目标内存页面进行交换。由于CPU读取目标PTE中预设字段的字段值的方式，相较通过软件获取内存信息的方式，效率更好，因此可以提高内存管理的效率，提高系统综合性能。
在一种可能的实现方式中，方法还包括：获取转译后备缓冲器(Translation Look-aside Buffer，TLB)中与目标内存页面对应的TLB表项(TLB entry)，其中，TLB表项中包括第二信息，第二信息用于表征目标内存页面的访问频次；根据第二信息，确定目标PTE中的第一信息。
本申请中，通过在TLB表项中设置表征目标内存页面的访问频次的第二信息，使TLB表项能够记录目标内存页面的访问频次，而目标内存页面的访问频次能够指示目标内存页面的 数据访问热度，因此，根据第二信息，可以确定目标PTE中的用于表征数据访问热度的第一信息。由于TLB表项是由TLB生成的，通过TLB统计目标内存页面的访问次数，相比通过软件方式查询和统计内存信息，效率更高，速度也更快，降低CPU的资源消耗，提高内存管理的效率。
在一种可能的实现方式中，第二信息包括TLB表项第三预设字段的字段值，第三预设字段用于记录目标内存页面在预设时长内的访问次数。
在一种可能的实现方式中，预设时长为TLB表项的生命周期。
在一种可能的实现方式中，方法还包括：若算数逻辑单元(Arithmetic Logic Unit，ALU)在访问TLB时命中(hit)TLB表项，则通过第三预设字段的字段值累加访问次数。
本申请中，在TLB表项中设置第三预设字段，并在ALU访问TLB命中目标内存页面对应的TLB表项时，通过第三预设字段的字段值累加访问次数，从而确定目标内存页面的访问频次。由于通过TLB统计目标内存页面的访问次数，相比通过软件方式查询和统计内存信息，效率更高，速度也更快，因此可以降低CPU的资源消耗，提高内存管理的效率。
在一种可能的实现方式中，TLB表项的生命周期结束时，第三预设字段的字段值归零。
在一种可能的实现方式中，根据第二信息，确定目标PTE中的第一信息，包括：根据第三预设字段的字段值与预设访问次数阈值之间的关系，确定目标PTE中的第一信息。
在一种可能的实现方式中，第一信息包括设置于目标PTE第一预设字段的字段值，第一预设字段的字段值用于表征目标内存页面的数据访问热度等级，根据第三预设字段的字段值与预设访问次数阈值之间的关系，确定目标PTE中的第一信息，包括：在TLB表项的生命周期结束时，若第三预设字段的字段值大于预设访问次数阈值，则将第一信息中第一预设字段的字段值设置为第一预设值，其中，当第一信息中第一预设字段的字段值设置为第一预设值时，第一信息对应热数据；在TLB表项的生命周期结束时，若第三预设字段的字段值不大于预设访问次数阈值，则将第一信息中第一预设字段的字段值设置为第二预设值，其中，当第一信息中第一预设字段的字段值设置为第二预设值时，第一信息对应温数据。
在一种可能的实现方式中，预设访问次数阈值设置在TLB访问计数阈值寄存器中。
本申请中，通过第三预设字段的字段值与预设访问次数阈值之间的关系，对应确定第一信息中第一预设字段的字段值，从而使第一信息可对应征不同的数据访问热度等级。通过第一信息将目标内存页面分为热数据和温数据，从而分别进行内存管理，可以进一步地提高内存管理的精确性，提高内存使用效率。
在一种可能的实现方式中，第一信息包括设置于目标PTE第一预设字段的字段值和设置于目标PTE第四预设字段的字段值，第一预设字段与第四预设字段用于共同表征目标内存页面的数据访问热度等级，根据第三预设字段的字段值与预设访问次数阈值之间的关系，确定目标PTE中的第一信息，包括：在TLB表项的生命周期结束时，若第三预设字段的字段值大于第一次数阈值，则将第一预设字段的字段值和第四预设字段的字段值设为第一预设值；其中，当第一预设字段的字段值和第四预设字段的字段值设为第一预设值时，第一信息对应热数据；在TLB表项的生命周期结束时，若第三预设字段的字段值小于或等于第一次数阈值，且大于第二次数阈值，则将第一预设字段的字段值设置为第二预设值，将第四预设字段的字 段值设为第一预设值；其中，第二次数阈值小于第一次数阈值；当第一预设字段的字段值为第二预设值且第四预设字段的字段值为第一预设值时，第一信息对应温数据；在TLB表项的生命周期结束时，若第三预设字段的字段值小于或等于第二次数阈值，则将第四预设字段的字段值设为第二预设值；其中，当第四预设字段的字段值为第二预设值时，第一信息对应冷数据。
本申请中，通过第三预设字段的字段值与预设访问次数阈值之间的关系，对应确定第一信息中第一预设字段的字段值和第四预设字段的字段值，从而使第一信息可对应征不同的数据访问热度等级。通过第一信息将目标内存页面分为冷数据、热数据和温数据，从而分别进行内存管理，可以进一步地提高内存管理的精确性，提高内存使用效率。
第二方面，本申请提供一种内存管理装置，包括：
获取模块，用于获取内存中的目标PTE，目标PTE中包括第一信息，第一信息用于表征目标内存页面的数据访问热度；
确定模块，用于根据第一信息，确定目标内存页面的目标存储位置；
交换模块，用于将目标内存页面交换至目标存储位置。
本申请中，通过获取目标PTE，根据目标PTE中携带的第一信息确定目标内存页面的数据访问热度，并根据目标内存页面的数据访问热度将目标内存页面交换(Swap)至与该数据访问热度相匹配的目标存储位置。由于目标PTE中携带了能够表征数据访问热度的第一信息，因此CPU可以直接根据该目标PTE，将对应的目标内存页面交换至与该目标内存页面的数据访问热度相匹配的目标存储位置，而无需通过软件轮询内存中页表的方法统计页面访问热度，相比软件轮询的方式，本申请实施例提供的方法更高获取更多的内存页面信息，且效率更高，因此可以基于数据访问热度实现更有效的内存管理，同时使CPU对内存的管理效率更高，降低了CPU的工作负载，提高了内存管理的有效性和系统综合性能。
在一种可能的实现方式中，数据访问热度是根据目标内存页面的访问频次确定的。
在一种可能的实现方式中，第一信息包括设置于目标PTE第一预设字段的字段值，第一预设字段用于表征目标内存页面的数据访问热度等级；确定模块，具体用于：根据第一预设字段的字段值，确定目标内存页面的数据访问热度等级；确定与目标内存页面的数据访问热度等级相匹配的目标存储位置。
本申请中，通过在目标PTE上设置第一预设字段，使目标PTE能够携带目标内存页面对应的数据访问热度等级的信息，从而使CPU能够通过读取目标PTE的第一预设字段的字段值，而确定目标内存页面的数据访问热度等级，进而将目标内存页面交换至与该数据访问热度等级相匹配的目标存储位置，提高本地高速内存的使用效率。
在一种可能的实现方式中，数据访问热度等级包括热数据和温数据；若数据访问热度等级为热数据，则与目标内存页面相匹配的目标存储位置为本地内存；若数据访问热度等级为温数据，则与目标内存页面相匹配的目标存储位置为远端内存。
在一种可能的实现方式中，数据访问热度等级还包括冷数据，若数据访问热度等级为冷数据，则与目标内存页面相匹配的目标存储位置为持久内存或硬盘。
本申请中，通过将目标内存页面分为热数据、温数据和冷数据三种数据访问热度等级，并根据不同的数据访问热度等级，将目标内存页面分别交换至本地内存、远端内存和持久内存或硬盘，由于从本地内存、远端内存至持久内存或硬盘，读写性能逐渐降低，同时，成本也逐渐降低，因此，将不同数据访问热度等级的目标内存页面分别交换至不同的目标存储位置，可以起到优化内存使用效率，降低内存使用成本的目的，提高系统中内存单位成本下的效能。
在一种可能的实现方式中，第一信息包括设置于目标PTE第二预设字段的字段值，第二预设字段用于表征目标内存页面的当前存储位置；交换模块，具体用于：若目标存储位置与第二预设字段的字段值对应的当前存储位置相同，则保留目标内存页面在当前存储位置；若目标存储位置与第二预设字段的字段值对应的当前存储位置不同，则将目标内存页面交换至目标存储位置。
本申请中，通过在目标PTE中设置用于表征目标内存页面的当前存储位置的第二预设字段，使CPU能够通过读取PTE的第二预设字段的字段值，确定目标内存页面的当前位置，进而确定是否需要对目标内存页面进行交换。由于CPU读取目标PTE中预设字段的字段值的方式，相较通过软件获取内存信息的方式，效率更好，因此可以提高内存管理的效率，提高系统综合性能。
在一种可能的实现方式中，装置还包括：处理模块，用于：获取TLB中与目标内存页面对应的TLB表项，其中，TLB表项中包括第二信息，第二信息用于表征目标内存页面的访问频次；根据第二信息，确定目标PTE中的第一信息。
本申请中，通过在TLB表项中设置表征目标内存页面的访问频次的第二信息，使TLB表项能够记录目标内存页面的访问频次，而目标内存页面的访问频次能够指示目标内存页面的数据访问热度，因此，根据第二信息，可以确定目标PTE中的用于表征数据访问热度的第一信息。由于TLB表项是由TLB生成的，通过TLB统计目标内存页面的访问次数，相比通过软件方式查询和统计内存信息，效率更高，速度也更快，降低CPU的资源消耗，提高内存管理的效率。
在一种可能的实现方式中，第二信息包括TLB表项第三预设字段的字段值，第三预设字段用于记录目标内存页面在预设时长内的访问次数。
在一种可能的实现方式中，预设时长为TLB表项的生命周期。
在一种可能的实现方式中，处理模块还用于：若算数逻辑单元ALU在访问TLB时命中TLB表项，则通过第三预设字段的字段值累加访问次数。
本申请中，在TLB表项中设置第三预设字段，并在ALU访问TLB命中目标内存页面对应的TLB表项时，通过第三预设字段的字段值累加访问次数，从而确定目标内存页面的访问频次。由于通过TLB统计目标内存页面的访问次数，相比通过软件方式查询和统计内存信息，效率更高，速度也更快，因此可以降低CPU的资源消耗，提高内存管理的效率。
在一种可能的实现方式中，TLB表项的生命周期结束时，第三预设字段的字段值归零。
在一种可能的实现方式中，处理模块在根据第二信息，确定目标PTE中的第一信息时，具体用于：根据第三预设字段的字段值与预设访问次数阈值之间的关系，确定目标PTE 中的第一信息。
在一种可能的实现方式中，第一信息包括设置于目标PTE第一预设字段的字段值，第一预设字段的字段值用于表征目标内存页面的数据访问热度等级，处理模块在根据第三预设字段的字段值与预设访问次数阈值之间的关系，确定目标PTE中的第一信息时，具体用于：在TLB表项的生命周期结束时，若第三预设字段的字段值大于预设访问次数阈值，则将第一信息中第一预设字段的字段值设置为第一预设值；在TLB表项的生命周期结束时，若第三预设字段的字段值不大于预设访问次数阈值，则将第一信息中第一预设字段的字段值设置为第二预设值。
在一种可能的实现方式中，预设访问次数阈值设置在TLB访问计数阈值寄存器中。
在一种可能的实现方式中，第一信息包括设置于目标PTE第一预设字段的字段值和设置于目标PTE第四预设字段的字段值，第一预设字段与第四预设字段用于共同表征目标内存页面的数据访问热度等级，处理模块在根据第三预设字段的字段值与预设访问次数阈值之间的关系，确定目标PTE中的第一信息时，具体用于：在TLB表项的生命周期结束时，若第三预设字段的字段值大于第一次数阈值，则将第一预设字段的字段值和第四预设字段的字段值设为第一预设值；在TLB表项的生命周期结束时，若第三预设字段的字段值小于或等于第一次数阈值，且大于第二次数阈值，则将第一预设字段的字段值设置为第二预设值，将第四预设字段的字段值设为第一预设值；其中，第二次数阈值小于第一次数阈值；在TLB表项的生命周期结束时，若第三预设字段的字段值小于或等于第二次数阈值，则将第四预设字段的字段值设为第二预设值。
本申请中，通过第三预设字段的字段值与预设访问次数阈值之间的关系，对应确定第一信息中第一预设字段的字段值和第四预设字段的字段值，从而使第一信息可对应征不同的数据访问热度等级。通过第一信息将目标内存页面分为冷数据、热数据和温数据，从而分别进行内存管理，可以进一步地提高内存管理的精确性，提高内存使用效率。
第三方面，本申请实施例提供一种电子设备包括：存储器，处理器以及计算机程序；其中，计算机程序存储在存储器中，并被配置为由处理器执行以上第一方面的任一实现方式提供的方法。
第四方面，本申请实施例提供一种电子设备，包括：处理器、存储器和收发器；处理器用于控制收发器收发信号；存储器用于存储计算机程序；处理器还用于调用并运行存储器中存储的计算机程序，使得该电子设备执行以上第一方面的任一实现方式提供的方法。
第五方面，本申请实施例提供一种计算机可读存储介质，包括计算机代码，当其在计算机上运行时，使得计算机执行以上第一方面的任一实现方式提供的方法。
第六方面，本申请实施例提供一种计算机程序产品，包括程序代码，当计算机运行计算机程序产品时，该程序代码执行以上第一方面的任一实现方式提供的方法。
第七方面，本申请还提供一种芯片，包括处理器。该处理器用于调用并运行存储器中存储的计算机程序，以执行本申请实施例的内存管理方法中相应操作和/或流程。可选地，该芯片还包括存储器，该存储器与该处理器通过电路或电线与存储器连接，处理器用于读取并执行该存储器中的计算机程序。进一步可选地，该芯片还包括通信接口，处理器与该通信接 口连接。通信接口用于接收需要处理的数据和/或信息，处理器从该通信接口获取该数据和/或信息，并对该数据和/或信息进行处理。该通信接口可以是输入输出接口。
附图说明
图1为本申请实施例提供的一种应用场景示意图；
图2为本申请实施例提供的一种系统架构示意图；
图3为本申请实施例提供的一种内存管理方法的流程示意图；
图4为本申请实施例提供的一种目标PTE中包括第一信息的示意图；
图5A为本申请实施例提供的一种根据第一信息确定目标内存页面的目标存储位置的示意图；
图5B为本申请实施例提供的另一种根据第一信息确定目标内存页面的目标存储位置的示意图；
图5C为本申请实施例提供的再一种根据第一信息确定目标内存页面的目标存储位置的示意图；
图6为本申请实施例提供的另一种内存管理方法的流程示意图；
图7为本申请实施例提供的一种TLB表项的示意图；
图8为本申请实施例提供的一种TLB表项中包括第二信息的示意图；
图9为本申请实施例提供的又一种内存管理方法的流程示意图；
图9A为本申请实施例提供的一种目标PTE的构成示意图；
图10为本申请实施例提供的再一种内存管理方法的流程示意图；
图11为本申请实施例提供的一种内存管理装置的示意性框图；
图12为本申请实施例提供的另一种内存管理装置的示意性框图；
图13为本申请实施例提供的一种电子设备的结构示意性框图；
图14为本申请实施例提供的另一种电子设备的结构示意性框图。
具体实施方式
以下对本申请中的部分用语进行解释说明，以便于本领域技术人员理解。需要说明的是，当本申请实施例的方案应用于5G系统、或者现有的系统、或未来可能出现的其他系统时，本申请实施例的方案执行主体的名称可能发生变化，但这并不影响本申请实施例方案的实施。
1)转译后备缓冲器(Translation Look-aside Buffer，TLB)，也成为了页表缓冲，是CPU的一种缓冲，由存储器管理单元用于改进虚拟地址到物理地址的转译速度。TLB具有固定数目的空间槽，用于存放将虚拟地址映射至物理地址的标签页表条目。其搜索关键字为虚拟地址，其搜索结果为物理地址。如果请求的虚拟地址在TLB中存在，将得到一个非常快速的匹配结果，之后就可以使用得到的物理地址访问存储器；如果请求的虚拟地址不在TLB中，就会使用标签页表进行虚实地址转换，而标签页表的访问速度比TLB慢很多。
2)页表项(page table entry，PTE)，是页表(page table)中的一种用于表征虚拟地址至物理地址映射关系的数据结构，在CPU需要访问某个虚拟地址时，通过使用PTE可以确定该虚拟地址对应的物理地址，从而使CPU可以访问到该物理地址上的数据。
3)“多个”是指两个或两个以上，其它量词与之类似。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和 B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
4)“对应”可以指的是一种关联关系或绑定关系，A与B相对应指的是A与B之间是一种关联关系或绑定关系。
需要指出的是，本申请实施例中涉及的名词或术语可以相互参考，不再赘述。
图1为本申请实施例提供的一种应用场景示意图，如图1所示，为终端设备提供云服务和云计算的服务器或服务器组，为了降低内存的使用成本，连接有多种类型的存储设备，如设置在本地的高性能内存，以及设置在本地或远端的低成本的硬盘，对于系统中经常访问的内存数据，即热数据，设置在本地高性能内存中，以提高系统性能；而对于不经常访问的内存数据，即冷数据，则设置在传输时延较高，但成本更低的硬盘中，以降低内存成本，此外，还可以通过设置低成本的内存，如SCM内存条、串行总线内存、硬件压缩内存等，作为性能和成本介于本地内存与硬盘之间的中间形态，即远端内存(Far Memory)，利用远端内存存储介于“热数据”与“冷数据”之间的“温数据”，以进一步的细化内存数据管理，提高系统的性能，且不用增加太多成本。
然而，现有技术中，在系统确定内存数据的热度时，通常采用的技术方案是通过软件查询并统计内存的使用信息，通过纯软件进行内容数据的热度统计，需要消耗CPU的资源，增加CPU负载，同时部分内存访问信息仅通过软件层面无法访问，导致了内存热度判断不准确，实时性差，因此，造成了系统的综合性能降低，内存使用效率低下的问题。
图2为本申请实施例提供的一种系统架构示意图，如图2所示，CPU中设置有负责逻辑运算的ALU，当CPU需要访问内存时，ALU根据具体应用对应的虚拟地址，对设置在CPU中的TLB进行访问，TLB中缓存有用于表征虚拟地址和物理地址映射关系的TLB表项，TLB表项对应的一个PTE，ALU对TLB进行搜索后，若命中了目标TLB表项，则可以快速确定该虚拟地址对应的物理地址，进而，实现对物理地址处存储的内存数据的访问。若未命中目标TLB表项，则访问本地内存中页表内的PTE，确定与该虚拟地址对应的物理地址，进而实现对物理地址处存储的内存数据的访问。
为了解决上述系统的综合性能降低，内存使用效率低下的问题，本申请实施例提供的内存管理方法，在图2所示的系统架构中，通过对PTE以及LTB表项的改造，使PTE能够携带表征目标内存页面的数据访问热度的第一信息，从而根据该第一信息将目标内存页面交换至目标存储位置，实现对内存数据的差异化存储，提高内存使用效率，提高系统综合性能。
图3为本申请实施例提供的一种内存管理方法的流程示意图，本方法的执行主体可以为一种电子设备，具体地，例如为服务器，或者电子设备内的内存管理系统。如图3所示，该方法包括：
S101、获取内存中的目标PTE，目标PTE中包括第一信息，第一信息用于表征目标内存页面的数据访问热度。
示例性地，PTE是用于表征虚拟地址与物理地址之间映射关系的表项，根据已获知的虚拟地址，利用PTE即可得到对应的物理地址，进而得到物理地址处存储的内存页面。其中，目标内存页面是指待处理的内存页面，目标PTE是与目标内存页面的物理地址相对应的PTE，目标PTE与目标内存页面一一对应。
获取内存中的目标PTE的方式有多种，例如，服务器中的CPU每间隔预设周期，读取一 条目标PTE；再例如，服务器中的CPU在预设触发条件下，读取一条目标PTE，具体地，预设触发条件例如为CPU接收用户指令，此处不做具体限定。
示例性地，第一信息是用于表征目标内存页面的数据访问热度的信息，第一信息携带在目标PTE中。图4为本申请实施例提供的一种目标PTE中包括第一信息的示意图，如图4所示，第一信息可以通过设置在目标PTE中一个预设字段实现。具体地，例如，目标PTE中包括第一预设字段，第一预设字段的字段值用于表示第一信息，更加具体地，例如，该字段值为0时，表示目标内存页面的一种数据访问热度；该字段值为1时，表示目标内存页面的另一种数据访问热度。其中，第一预设字段的在目标PTE中的位置可以根据需要设置，此处不做具体限定。
进一步地，在一种可能的实现方式中，数据访问热度是根据目标内存页面的访问频次确定的，当目标内存页面的访问频次越高，说明该目标内存页面在之后被访问的几率越大，目标内存页面热度也就越高；反之，当目标内存页面的访问频次越低，说明该目标内存页面在之后被访问的几率越小，目标内存页面热度也就越低。
在另一种可能的实现方式中，数据访问热度是根据目标内存页面的时延要求信息确定的，示例性地，延迟要求信息是表征目标内存页面被访问时能够接受的最大时延；时延要求信息越小，说明服务器对目标内存页面的访问时延越敏感，目标内存页面热度越高；反之，时延要求信息越大，说明服务器对目标内存页面的访问时延越不敏感，目标内存页面热度越低。
S102、根据第一信息，确定目标内存页面的目标存储位置。
示例性地，第一信息能够表征对应的目标内存页面的数据访问热度，根据目标存储位置的数据访问热度，将目标内存页面交换至相匹配的目标存储位置，可以起到平衡系统性能与成本的效果，具体地，例如，当第一信息对应高热度数据时，将目标内存页面交换至处理高热度数据效率更高的存储介质中，例如本地高速内存，提高数据处理效率；而当第一信息对应低热度数据时，将目标内存页面交换至处理低热度数据成本更低的存储介质中，例如硬盘中，以降低内存使用成本。
进一步地，在一种可能的实现方式中，数据访问热度可以包括有多个数据访问热度等级，图5A为本申请实施例提供的一种根据第一信息确定目标内存页面的目标存储位置的示意图，如图5A所示，例如，数据访问热度等级可以包括热数据和冷数据，根据预设的映射关系，与热数据对应的目标存储位置为本地内存，与冷数据对应的目标存储位置为硬盘；图5B为本申请实施例提供的另一种根据第一信息确定目标内存页面的目标存储位置的示意图，如图5B所示，例如，数据访问热度等级可以包括热数据、温数据和冷数据，相应地，根据预设的映射关系，与热数据对应的目标存储位置为本地内存，与冷数据对应的目标存储位置为远端内存，与冷数据对应的目标存储位置为硬盘。可以理解的是，数据访问热度等级可以根据需要进行更多级别的划分，图5C为本申请实施例提供的再一种根据第一信息确定目标内存页面的目标存储位置的示意图，如图5C所示，例如“第1热度等级”至“第N热度等级”，根据预设的映射关系，每一数据访问热度等级分别对应一个目标存储位置，进而将不同数据访问热度等级的目标内存页面分别存储至匹配的目标存储位置，即“存储介质1”至“存储介质M”。随着“第1热度等级”至“第N热度等级”数据访问热度的逐渐降低，用于存储“第 1热度等级”至“第N热度等级”数据的“存储介质1”至“存储介质M”的设备性能也随之下降，例如数据时延逐渐升高、读写速度逐渐下降，但同时“存储介质1”至“存储介质M”的设备成本随之下降。从而使不同数据访问热度的数据对应存储至匹配的目标存储位置，实现对内存更加精细化的管理，提高内存使用效率。
S103、将目标内存页面交换至目标存储位置。
示例性地，交换(Swap)可以指页面调度的过程，即从磁盘向内存传输数据，或者从内存向磁盘传输数据的过程。将目标内存页面交换至目标存储位置，即将目标内存页面调度到高读写性能的内存中，或者低读写性能的磁盘的过程，该过程可以是由CPU或者内存管理单元(Memory Management Unit，MMU)执行的。出于成本和性能两方面的考虑，系统既要尽可能的将数据加载到具有高读写性能的内存中进行访问，以保证系统性能，又要将部分不经常使用的数据调度到低成本的读写介质中，以降低成本，因此，系统需要根据服务器的运行情况，动态地对内存进行管理，将数据调度到最佳的存储位置。在上述步骤中，目标存储位置时根据目标内存页面的数据访问热度所确定的，因此，目标存储位置可认为是目标内存页面所对应的最佳存储位置，将目标内存页面交换至目标存储位置，能够提高系统的综合性能和内存使用效率。
本申请中，通过获取目标PTE，根据目标PTE中携带的第一信息确定目标内存页面的数据访问热度，并根据目标内存页面的数据访问热度将目标内存页面交换至与该数据访问热度相匹配的目标存储位置。由于目标PTE中携带了能够表征数据访问热度的第一信息，因此CPU可以直接根据该目标PTE，将对应的目标内存页面交换至与该目标内存页面的数据访问热度相匹配的目标存储位置，而无需通过软件轮询内存中页表的方法统计页面访问热度，相比软件轮询的方式，本申请实施例提供的方法更高获取更多的内存页面信息，且效率更高，因此可以基于数据访问热度实现更有效的内存管理，同时使CPU对内存的管理效率更高，降低了CPU的工作负载，提高了内存管理的有效性和系统综合性能。
图6为本申请实施例提供的另一种内存管理方法的流程示意图，如图6所示，本实施例提供的内存管理方法在图3所示实施例提供的内存管理方法的基础上，增加了确定目标PTE第一信息的步骤，该方法包括：
S201、获取TLB中与目标内存页面对应的TLB表项，其中，TLB表项中包括第二信息，第二信息用于表征目标内存页面的访问频次。
示例性地，图7为本申请实施例提供的一种TLB表项的示意图，如图7所示，TLB中缓存有多个TLB表项，用于表征不同的虚拟地址与物理地址的映射关系，当CPU提供一个虚拟地址后，通过TLB中的多个TLB表项进行搜索，若能命中TLB中的TLB表项，则可以快速得到对应的物理地址，实现CPU对内存页面的快速访问。
进一步地，获取TLB中与目标内存页面对应的TLB表项的时机可以有多种，例如，以预设的周期获取TLB中的某一TLB表项，再例如，在某一TLB表项的生命周期结束时，获取该TLB表项，此处不再一一赘述。
示例性地，第二信息是用于表征目标内存页面的访问频次的信息，第二信息携带在目标内存页面对应的TLB表项中。图8为本申请实施例提供的一种TLB表项中包括第二信息 的示意图，如图8所示，示例性地，第二信息可以通过设置在TLB表项中的一个预设字段实现，例如，TLB表项中包括第三预设字段，第三预设字段的字段值用于记录目标内存页面在预设时长内的访问次数，更加具体地，例如，该字段值为28，则表示目标内存页面在预设时长内被访问了28次。
其中，示例性地，预设时长为TLB表项的生命周期。
进一步地，第三预设字段的字段值是通过累加预设时长内目标内存页面的被访问次数和确定的，具体地，例如：若算数逻辑单元(Arithmet ic Logic Unit，ALU)在访问TLB时命中目标内存页面对应的TLB表项，则对第三预设字段的字段值进行加1操作，使该第三预设字段的字段值累加1，直至该目标内存页面对应的TLB表项的生命周期结束，被移出TLB，统计该第三预设字段的字段值的总数，确定为第二信息。
示例性地，在TLB表项生命周期结束后，在一段时间后可能会被再次加载至TLB中，并通过累加第三预设字段的字段值的方式，重新对该TLB表项的被访问次数进行统计，实现对该TLB表项对应的目标内存页面的实时动态调整，因此，在TLB表项的生命周期结束时，将第三预设字段的字段值归零。
S202、根据第二信息，确定目标PTE中的第一信息。
示例性地，由于第二信息能够表征目标内存页面的访问频次，目标内存页面的访问频次越高，说明该目标内存页面在之后被访问的几率越大，目标内存页面热度也就越高；反之，当目标内存页面的访问频次越低，说明该目标内存页面在之后被访问的几率越小，目标内存页面热度也就越低，即第二信息所表征的访问频次与第一信息所表征的数据访问热度，具有对应关系。因此，可以根据预设的映射关系，确定与第二信息表征的访问频次相匹配的数据访问热度，即第一信息。更加具体地，例如，第二信息为“30”，表征目标内存数据在TLB表项生命周期内被访问30次，根据预设的映射关系，与第二信息“30”对应的目标PTE的第一信息为“1”，表示目标内存页面的数据访问热度等级为“热数据”。再例如，第二信息为“4”，表征目标内存数据在TLB表项生命周期内被访问4次，根据预设的映射关系，与第二信息“4”对应的目标PTE的第一信息为“0”，表示目标内存页面的数据访问热度等级为“温数据”。
其中，第二信息与第一信息之间预设的映射关系，可以是一个离散的数值映射表，或者是一个连续的映射模型，该映射关系可以是用户进行预先设置的，也可以是本实施例的执行主体根据历史数据进行自学习而确定的，此处不进行具体限定。
S203、获取内存中的目标PTE，目标PTE中包括第一信息，第一信息用于表征目标内存页面的数据访问热度。
S204、根据第一信息，确定目标内存页面的目标存储位置。
S205、将目标内存页面交换至目标存储位置。
本实施例中，S203至S205的实现方式与本发明图3所示实施例中的S101至S103的实现方式相同，在此不再一一赘述。
图9为本申请实施例提供的又一种内存管理方法的流程示意图，如图9所示，本实施例 提供的内存管理方法在图6所示实施例提供的内存管理方法的基础上，对确定目标存储位置的步骤进一步细化，该方法包括：
S301、获取TLB中与目标内存页面对应的TLB表项，其中，TLB表项中包括第三预设字段，第三预设字段的字段值用于记录目标内存页面在预设时长内的访问次数。
示例性地，第三预设字段可以是设置在TLB表项中指定位置的一个字段，例如，第三预设字段的字段标识为AC(Access Count)，AC字段长度为8位(bit)，设置在虚拟地址与物理地址之后的位置。可以理解的是，本实施例中的第三预设字段的标识名称、字段长度和字段位置均为示例性地，该第三预设字段还可以以其他数据长度设置在其他字段位置，此处不再一一赘述。
示例性地，获取TLB中与目标内存页面对应的TLB表项的时机可以有多种，例如，以预设的周期获取TLB中的某一TLB表项，该TLB表项对应的内存页面为目标内存页面。再例如，在某一TLB表项的生命周期结束时，获取该TLB表项，该TLB表项对应的内存页面为目标内存页面。
在一种可能的实现方式中，TLB中某一TLB表项的生命周期结束时，获取该TLB表项，并读取该TLB表项的第三预设字段的字段值，得到目标内存页面在TLB表项在生命周期内被访问次数的总次数。
S302、获取内存中的目标PTE。
示例性地，当TLB中与目标内存页面对应的TLB表项的生命周期结束后，TLB不再缓存该TLB表项所对应的虚拟地址与物理地址之间的映射关系，而该映射关系信息由对应的在内存中的目标PTE所承载。在一种可能的实现方式中，CPU轮询内存中的所有PTE，从而获得该目标PTE。
S303、分别确定目标PTE的第一预设字段的字段值、第二预设字段的字段值、第四预设字段的字段值。
图9A为本申请实施例提供的一种目标PTE的构成示意图；其中，示例性地，目标PTE的第一预设字段用于表征目标内存页面的数据访问热度等级，具体地，在一种可能的实现方式中，如图9A所示，目标PTE的第一预设字段的字段标识为ACF(Access Count Flag)，第一预设字段占用一位(bit)，第一预设字段的字段值为0或1，示例性地，确定该第一预设字段的字段值的方法包括：当与目标内存页面对应的TLB表项的生命周期结束时，统计该TLB表项中第三预设字段的字段值，若该TLB表项中第三预设字段的字段值大于预设访问次数阈值，则将目标PTE的第一预设字段的字段值设置为第一预设值，例如为1；若该TLB表项中第三预设字段的字段值不大于预设访问次数阈值，则将目标PTE的第一预设字段的字段值设置为第二预设值，例如为0。
示例性地，目标PTE的第二预设字段用于表征目标内存页面的当前存储位置，具体地，在一种可能的实现方式中，如图9A所示，目标PTE的第二预设字段的字段标识为RF(Reside in far memory Flag)，第二预设字段占用一位(bit)，第二预设字段的字段值为0或1，示例性地，第二预设字段的字段值是根据目标内存页面的当前所处的存储介质信息所确定的，更具体地，例如，当目标存储介质存储在本地内存时，第二预设 字段的字段值为0；当目标存储介质存储在远端内存时，第二预设字段的字段值为1。
示例性地，目标PTE的第四预设字段用于表征目标内存页面的被访问记录，具体地，在一种可能的实现方式中，如图9A所示，目标PTE的第四预设字段的字段标识为AF(Access Flag)，第四预设字段占用一位(bit)，第四预设字段的字段值为0或1，示例性地，第四预设字段的字段值是根据目标PTE的被访问情况确定的，例如，当目标PTE在预设访问时长内被访问过时，则将目标PET中的第四预设字段的字段值设置为1，否则，将目标PET中的第四预设字段的字段值设置为0。
S304、根据目标PTE的第一预设字段的字段值，和/或第四预设字段的字段值，确定目标存储位置。
示例性地，目标PTE中的第一预设字段的字段值、第四预设字段的字段值，分别是用于表征目标内存页面的数据访问热度等级、目标内存页面的被访问记录。其中，根据第四预设字段的字段值表征的目标内存页面的被访问记录，若目标内存页面在预设访问时长内未被访问过时，说明目标内存页面为冷数据，此时，将该目标内存页面交换至硬盘等低成本存储介质中，以降低内存使用成本；若目标内存页面在预设访问时长内被访问过时，说明目标内存页面并非冷数据，此时，再根据第一预设字段的字段值表征的目标内存数据的数据访问热度等级，进一步对目标内存数据进行区分，若目标内存数据为热数据，将该目标内存页面交换至本地内存等高读写性能的存储介质中，以提高系统性能；若目标内存数据为温数据，将该目标内存页面交换至远端内存等均匀均衡性能和成本的存储介质中，以提高系统的综合性能，降低成本。
其中，本实施例步骤举例说明了通过第一预设字段的字段值和第四预设字段的字段值，确定目标存储位置的步骤，可以理解的是，还可以仅通过第一预设字段的字段值，确定与第一预设字段的字段值表征的数据访问热度等级相匹配的目标存储位置，或者，仅通过第四预设字段的字段值，确定第四预设字段的字段值表征的是否存在访问记录相匹配的目标存储位置，此处不再对此一一赘述。
S305、根据第二预设字段的字段值，将目标内存页面交换至目标存储位置。
在确定目标存储位置后，需要根据目标内存页面的当前位置，确定是否需要将目标内存页面进行交互，具体地，例如，若目标内存页面的当前位置与目标存储位置一致，则不需要对目标内存页面进行交互；若目标内存页面的当前位置与目标存储位置不一致，则将目标内存页面交互至目标存储位置。更加具体地，例如，若目标内存页面的当前位置为硬盘；目标存储位置为本地内存，则将该目标内存页面交换至本地内存，以提高访问该目标内存页面的速度；若目标内存页面的当前位置为本地内存；目标存储位置为远端内存，则将该目标内存页面交换至远端内存，以提高内存使用效率。再例如，若目标内存页面的当前位置为本地内存，而目标存储位置也为本地内存，则五队目标内存页面进行交换。
为了更好地说明本申请实施例提供的内存管理方法实现过程，下面以一个更具体地实施例进行说明，本实施例的执行主体为电子设备内的CPU，图10为本申请实施例提供的再一种内存管理方法的流程示意图，如图10所示，该方法包括：
S401、CPU统计并判断预设周期是否超时，若超时，则执行S402；若未超时，则继续执 行S401。
S402、CPU从内存中的PTE序列中读取一条目标PTE。
示例性地，其中，PTE序列是指由PTE组成的序列，CPU以轮询的方式依次读取PTE序列中的PTE。
S403、CPU判断目标PTE的AF字段的字段值是否为1，若为1，则执行步骤S404；若不等于1，则执行步骤S406。
示例性地，目标PTE的AF字段用于表征目标内存页面的被访问记录，若AF字段的字段值若为1，则目标PTE在预设周期内被访问过，则跳转S404进一步对目标PTE对应的目标内存页面的数据访问热度等级进行判断；若AF字段的字段值若为0，则目标PTE对应的目标内存页面为冷数据，因此无需进行处理。
S404、CPU判断目标PTE的ACF字段的字段值是否为1，若为1，则执行步骤S405；若不等于1，则执行步骤S407。
示例性地，目标PTE的ACF字段用于表征目标内存页面的数据访问热度等级，若ACF字段的字段值等于1，则目标PTE对应的目标内存页面为热数据；若ACF字段的字段值等于0，则目标PTE对应的目标内存页面为温数据。
S405、CPU将目标PTE的ACF字段置为0。
S406、CPU判断目标PTE是否为PTE序列中的最后一条PTE，若是，则结束本方法；若不是，则执行步骤S402。
S407、CPU判断目标PTE的RF字段的字段值是否为1，若等于1，则执行步骤S406,；若不等于1，则执行步骤S408。
示例性地，目标PTE的RF字段用于表征目标内存页面的当前存储位置，若RF字段的字段值为1，则目标内存页面存储在远端内存；若RF字段的字段值为0，则目标内存页面存储在本地内存。
S408、CPU将PTE对应的内存页面交换至远端内存。
S409、CPU将PTE的RF字段的字段值设置为1。
S410、CPU将PTE对应的LTB表项从LTB中删除。
本实施例中，S401至S410的实现方式在本发明图3至图9所示实施例中已做过相应介绍，在此不再一一赘述。
上文中详细描述了本申请实施例的内存管理方法，下面将描述本申请实施例的内存管理装置。
在一个示例中，图11为本申请实施例提供的一种内存管理装置的示意性框图。本申请实施例的提供的内存管理装置5可以是上述方法实施例中的电子设备，也可以是电子设备内的一个或多个芯片。该内存管理装置5可以用于执行上述方法实施例中的电子设备的部分或全部功能。该内存管理装置5可以包括下述模块。
获取模块51，用于获取内存中的目标PTE，目标PTE中包括第一信息，第一信息用 于表征目标内存页面的数据访问热度。
确定模块52，用于根据第一信息，确定目标内存页面的目标存储位置。
交换模块53，用于将目标内存页面交换至目标存储位置。
本申请中，通过获取目标PTE，根据目标PTE中携带的第一信息确定目标内存页面的数据访问热度，并根据目标内存页面的数据访问热度将目标内存页面交换至与该数据访问热度相匹配的目标存储位置。由于目标PTE中携带了能够表征数据访问热度的第一信息，因此CPU可以直接根据该目标PTE，将对应的目标内存页面交换至与该目标内存页面的数据访问热度相匹配的目标存储位置，而无需通过软件轮询内存中页表的方法统计页面访问热度，相比软件轮询的方式，本申请实施例提供的方法更高获取更多的内存页面信息，且效率更高，因此可以基于数据访问热度实现更有效的内存管理，同时使CPU对内存的管理效率更高，降低了CPU的工作负载，提高了内存管理的有效性和系统综合性能。
图11所示实施例的内存管理装置5可用于执行上述方法中图3所示实施例的技术方案，其实现原理和技术效果类似，此处不再赘述。
在另一个示例中，图12为本申请实施例提供的另一种内存管理装置的示意性框图。在图11所示装置的基础上，如图12所示，该内存管理装置6中：
在一种可能的实现方式中，数据访问热度是根据目标内存页面的访问频次确定的。
在一种可能的实现方式中，第一信息包括设置于目标PTE第一预设字段的字段值，第一预设字段用于表征目标内存页面的数据访问热度等级；确定模块52，具体用于：根据第一预设字段的字段值，确定目标内存页面的数据访问热度等级；确定与目标内存页面的数据访问热度等级相匹配的目标存储位置。此时，确定模块52可以执行图3所示方法的步骤S102，或者，图6所示方法的步骤S204，或者，图9所示方法的步骤S303和步骤S304。
本申请中，通过在目标PTE上设置第一预设字段，使目标PTE能够携带目标内存页面对应的数据访问热度等级的信息，从而使CPU能够通过读取目标PTE的第一预设字段的字段值，而确定目标内存页面的数据访问热度等级，进而将目标内存页面交换至与该数据访问热度等级相匹配的目标存储位置，提高本地高速内存的使用效率。
在一种可能的实现方式中，数据访问热度等级包括热数据和温数据；若数据访问热度等级为热数据，则与目标内存页面相匹配的目标存储位置为本地内存；若数据访问热度等级为温数据，则与目标内存页面相匹配的目标存储位置为远端内存。
在一种可能的实现方式中，数据访问热度等级还包括冷数据，若数据访问热度等级为冷数据，则与目标内存页面相匹配的目标存储位置为持久内存或硬盘。
本申请中，通过将目标内存页面分为热数据、温数据和冷数据三种数据访问热度等级，并根据不同的数据访问热度等级，将目标内存页面分别交换至本地内存、远端内存和持久内存或硬盘，由于从本地内存、远端内存至持久内存或硬盘，读写性能逐渐降低，同时，成本也逐渐降低，因此，将不同数据访问热度等级的目标内存页面分别交换至不同的目标存储位置，可以起到优化内存使用效率，降低内存使用成本的目的，提高系统中内存单位成本下的效能。
在一种可能的实现方式中，第一信息包括设置于目标PTE第二预设字段的字段值，第二预设字段用于表征目标内存页面的当前存储位置；交换模块53，具体用于：若目标存储位置与第二预设字段的字段值对应的当前存储位置相同，则保留目标内存页面在当前存储位置；若目标存储位置与第二预设字段的字段值对应的当前存储位置不同，则将目标内存页面交换至目标存储位置。此时，交换模块53可以执行图3所示方法的步骤S103，或者，图6所示方法的步骤S205，或者，图9所示方法的步骤S305。
本申请中，通过在目标PTE中设置用于表征目标内存页面的当前存储位置的第二预设字段，使CPU能够通过读取PTE的第二预设字段的字段值，确定目标内存页面的当前位置，进而确定是否需要对目标内存页面进行交换。由于CPU读取目标PTE中预设字段的字段值的方式，相较通过软件获取内存信息的方式，效率更好，因此可以提高内存管理的效率，提高系统综合性能。
在一种可能的实现方式中，装置还包括：处理模块61，用于：获取TLB中与目标内存页面对应的TLB表项，其中，TLB表项中包括第二信息，第二信息用于表征目标内存页面的访问频次；根据第二信息，确定目标PTE中的第一信息。此时，处理模块61可以执行图6所示方法的步骤S201至步骤S202，或者，图9所示方法的步骤S301至步骤S302。
本申请中，通过在TLB表项中设置表征目标内存页面的访问频次的第二信息，使TLB表项能够记录目标内存页面的访问频次，而目标内存页面的访问频次能够指示目标内存页面的数据访问热度，因此，根据第二信息，可以确定目标PTE中的用于表征数据访问热度的第一信息。由于TLB表项是由TLB生成的，通过TLB统计目标内存页面的访问次数，相比通过软件方式查询和统计内存信息，效率更高，速度也更快，降低CPU的资源消耗，提高内存管理的效率。
在一种可能的实现方式中，第二信息包括TLB表项第三预设字段的字段值，第三预设字段用于记录目标内存页面在预设时长内的访问次数。
在一种可能的实现方式中，预设时长为TLB表项的生命周期。
在一种可能的实现方式中，处理模块61还用于：若算数逻辑单元ALU在访问TLB时命中TLB表项，则通过第三预设字段的字段值累加访问次数。此时，处理模块61可以执行图6所示方法的步骤S201，或者，可以执行图9所示方法的步骤S301。
本申请中，在TLB表项中设置第三预设字段，并在ALU访问TLB命中目标内存页面对应的TLB表项时，通过第三预设字段的字段值累加访问次数，从而确定目标内存页面的访问频次。由于通过TLB统计目标内存页面的访问次数，相比通过软件方式查询和统计内存信息，效率更高，速度也更快，因此可以降低CPU的资源消耗，提高内存管理的效率。
在一种可能的实现方式中，处理模块61还用于：TLB表项的生命周期结束时，将第三预设字段的字段值归零。
在一种可能的实现方式中，处理模块61在根据第二信息，确定目标PTE中的第一信息时，具体用于：根据第三预设字段的字段值与预设访问次数阈值之间的关系，确定目标PTE中的第一信息。此时，处理模块61可以执行图6所示方法的步骤S202，或者，可以执行图9所示方法的步骤S303。
在一种可能的实现方式中，第一信息包括设置于目标PTE第一预设字段的字段值，第一预设字段的字段值用于表征目标内存页面的数据访问热度等级，处理模块61在根据第三预设字段的字段值与预设访问次数阈值之间的关系，确定目标PTE中的第一信息时，具体用于：在TLB表项的生命周期结束时，若第三预设字段的字段值大于预设访问次数阈值，则将第一信息中第一预设字段的字段值设置为第一预设值；在TLB表项的生命周期结束时，若第三预设字段的字段值不大于预设访问次数阈值，则将第一信息中第一预设字段的字段值设置为第二预设值。此时，处理模块61可以执行图6所示方法的步骤S202，或者，可以执行图9所示方法的步骤S303。
在一种可能的实现方式中，预设访问次数阈值设置在TLB访问计数阈值寄存器中。
在一种可能的实现方式中，第一信息包括设置于目标PTE第一预设字段的字段值和设置于目标PTE第四预设字段的字段值，第一预设字段与第四预设字段用于共同表征目标内存页面的数据访问热度等级，处理模块在根据第三预设字段的字段值与预设访问次数阈值之间的关系，确定目标PTE中的第一信息时，具体用于：在TLB表项的生命周期结束时，若第三预设字段的字段值大于第一次数阈值，则将第一预设字段的字段值和第四预设字段的字段值设为第一预设值；在TLB表项的生命周期结束时，若第三预设字段的字段值小于或等于第一次数阈值，且大于第二次数阈值，则将第一预设字段的字段值设置为第二预设值，将第四预设字段的字段值设为第一预设值；其中，第二次数阈值小于第一次数阈值；在TLB表项的生命周期结束时，若第三预设字段的字段值小于或等于第二次数阈值，则将第四预设字段的字段值设为第二预设值。此时，处理模块61可以执行图6所示方法的步骤S202，或者，可以执行图9所示方法的步骤S303。
本申请中，通过第三预设字段的字段值与预设访问次数阈值之间的关系，对应确定第一信息中第一预设字段的字段值和第四预设字段的字段值，从而使第一信息可对应征不同的数据访问热度等级。通过第一信息将目标内存页面分为冷数据、热数据和温数据，从而分别进行内存管理，可以进一步地提高内存管理的精确性，提高内存使用效率。
图12所示实施例的内存管理装置可用于执行上述方法中图3或图6或图9所示实施例中任一项的技术方案，其实现原理和技术效果类似，此处不再赘述。
并且，本实施例的实施不依赖于图11所示的实施例是否实施，本实施例可以独立实施。
图13为本申请实施例提供的一种电子设备的结构示意性框图。如图13所示，该电子设备7包括：存储器71，处理器72以及计算机程序；其中，计算机程序存储在存储器71中，并被配置为由处理器72执行图3的各步骤，或者，执行图5的各步骤，或者，执行图14的各步骤。处理器72用于实现图11和图12的各模块。
其中，存储器71和处理器72通过总线73连接。
相关说明可以对应参见图3至图10所对应的实施例中的步骤所对应的相关描述和效果进行理解，此处不做过多赘述。
示例性地，图14为本申请实施例提供的另一种电子设备的结构示意性框图，如图14所示，本实施例提供的网络设备包括：收发器81，存储器82，处理器83以及计算机程序。
其中，处理器83用于控制收发器81收发信号，计算机程序存储在存储器82中，并被 配置为由处理器83执行以实现本发明图3至图10所对应的任一实现方式提供的方法。
其中，收发器81，存储器82，处理器83通过总线84连接。
相关说明可以对应参见图3至图10所对应的实施例中的步骤所对应的相关描述和效果进行理解，此处不做过多赘述。
本申请实施例还提供一种服务器，包括处理器，处理器用于执行计算机程序，以执行以上如图3至10所对应的任一实现方式提供的方法；服务器还包括通信接口；处理器与通信接口连接。
本申请实施例还提供一种计算机可读存储介质，包括计算机代码，当其在计算机上运行时，使得计算机执行如图3至10所对应的任一实现方式提供的方法。
本申请实施例还提供一种计算机程序产品，包括程序代码，当计算机运行计算机程序产品时，该程序代码执行如图3至10所对应的任一实现方式提供的方法。
本申请实施例还提供一种芯片，包括处理器。该处理器用于调用并运行存储器中存储的计算机程序，以执行如图3至10所对应的任一实现方式提供的内存管理方法中由电子设备执行的相应操作和/或流程。可选地，该芯片还包括存储器，该存储器与该处理器通过电路或电线与存储器连接，处理器用于读取并执行该存储器中的计算机程序。进一步可选地，该芯片还包括通信接口，处理器与该通信接口连接。通信接口用于接收需要处理的数据和/或信息，处理器从该通信接口获取该数据和/或信息，并对该数据和/或信息进行处理。该通信接口可以是输入输出接口。在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行计算机程序指令时，全部或部分地产生按照本申请实施例的流程或功能。计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如，同轴电缆、光纤、数字用户线(Digital Subscriber Line，DSL))或无线(例如，红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如，固态硬盘(Solid State Disk，SSD))等。
本领域技术人员应该可以意识到，在上述一个或多个示例中，本申请实施例所描述的功能可以用硬件、软件、固件或它们的任意组合来实现。当使用软件实现时，可以将这些功能存储在计算机可读介质中或者作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是通用或专用计算机能够存取的任何可用介质。

Claims (30)

  1. 一种内存管理方法，其特征在于，所述方法包括：
    获取内存中的目标页表项PTE，所述目标PTE中包括第一信息，所述第一信息用于表征目标内存页面的数据访问热度；
    根据所述第一信息，确定所述目标内存页面的目标存储位置；
    将所述目标内存页面交换至所述目标存储位置。
  2. 根据权利要求1所述的方法，其特征在于，所述数据访问热度是根据所述目标内存页面的访问频次确定的。
  3. 根据权利要求1或2所述的方法，其特征在于，所述第一信息包括设置于所述目标PTE第一预设字段的字段值，所述第一预设字段用于表征所述目标内存页面的数据访问热度等级；根据所述第一信息，确定所述目标内存页面的目标存储位置，包括：+
    根据所述第一预设字段的字段值，确定所述目标内存页面的数据访问热度等级；
    确定与所述目标内存页面的数据访问热度等级相匹配的目标存储位置。
  4. 根据权利要求3所述的方法，其特征在于，所述数据访问热度等级包括热数据和温数据；
    若所述数据访问热度等级为热数据，则与所述目标内存页面相匹配的目标存储位置为本地内存；若所述数据访问热度等级为温数据，则与所述目标内存页面相匹配的目标存储位置为远端内存。
  5. 根据权利要求4所述的方法，其特征在于，所述数据访问热度等级还包括冷数据；热度等级
    若所述数据访问热度等级为冷数据，则与所述目标内存页面相匹配的目标存储位置为持久内存或硬盘。
  6. 根据权利要求1-5任一项所述的方法，其特征在于，所述第一信息包括设置于所述目标PTE第二预设字段的字段值，所述第二预设字段用于表征所述目标内存页面的当前存储位置；将所述目标内存页面交换至所述目标存储位置，包括：
    若所述目标存储位置与所述第二预设字段的字段值对应的当前存储位置相同，则保留所述目标内存页面在所述当前存储位置；
    若所述目标存储位置与第二预设字段的字段值对应的当前存储位置不同，则将所述目标内存页面交换至所述目标存储位置。
  7. 根据权利要求1-6任一项所述的方法，其特征在于，所述方法还包括：
    获取转译后备缓冲器TLB中与所述目标内存页面对应的TLB表项，其中，所述TLB表项中包括第二信息，所述第二信息用于表征所述目标内存页面的访问频次；
    根据所述第二信息，确定所述目标PTE中的第一信息。
  8. 根据权利要求7所述的方法，其特征在于，所述第二信息包括所述TLB表项第三预设字段的字段值，所述第三预设字段用于记录所述目标内存页面在预设时长内的访问次数。
  9. 根据权利要求8所述的方法，其特征在于，所述预设时长为所述TLB表项的生命周期。
  10. 根据权利要求7-9任一项所述的方法，其特征在于，所述方法还包括：
    若算数逻辑单元ALU在访问所述TLB时命中所述TLB表项，则通过所述第三预设字段的字段值累加所述访问次数。
  11. 根据权利要求7-10任一项所述的方法，其特征在于，所述TLB表项的生命周期结束时，所述第三预设字段的字段值归零。
  12. 根据权利要求7-11任一项所述的方法，其特征在于，根据所述第二信息，确定所述目标PTE中的第一信息，包括：
    根据所述第三预设字段的字段值对应的所述目标内存页面在预设时长内的访问次数与预设访问次数阈值之间的关系，确定所述目标PTE中的第一信息。
  13. 根据权利要求12所述的方法，其特征在于，所述第一信息包括设置于所述目标PTE第一预设字段的字段值，所述第一预设字段的字段值用于表征所述目标内存页面的数据访问热度等级，根据所述第三预设字段的字段值与预设访问次数阈值之间的关系，确定所述目标PTE中的第一信息，包括：
    在所述TLB表项的生命周期结束时，若所述第三预设字段的字段值对应的所述目标内存页面在预设时长内的访问次数大于所述预设访问次数阈值，则将所述第一信息中第一预设字段的字段值设置为第一预设值；
    在所述TLB表项的生命周期结束时，若所述第三预设字段的字段值对应的所述目标内存页面在预设时长内的访问次数不大于所述预设访问次数阈值，则将所述第一信息中第一预设字段的字段值设置为第二预设值。
  14. 根据权利要求12所述的方法，其特征在于，所述第一信息包括设置于所述目标PTE第一预设字段的字段值和设置于所述目标PTE第四预设字段的字段值，所述第一预设字段与所述第四预设字段用于共同表征所述目标内存页面的数据访问热度等级，根据所述第三预设字段的字段值与预设访问次数阈值之间的关系，确定所述目标PTE中的第一信息，包括：
    在所述TLB表项的生命周期结束时，若所述第三预设字段的字段值大于第一次数阈值，则将所述第一预设字段的字段值和所述第四预设字段的字段值设为第一预设值；
    在所述TLB表项的生命周期结束时，若所述第三预设字段的字段值小于或等于所述第一次数阈值，且大于第二次数阈值，则将所述第一预设字段的字段值设置为第二预设值，将所述第四预设字段的字段值设为所述第一预设值；其中，所述第二次数阈值小于所述第一次数阈值；
    在所述TLB表项的生命周期结束时，若所述第三预设字段的字段值小于或等于所述 第二次数阈值，则将所述第四预设字段的字段值设为所述第二预设值。
  15. 一种内存管理装置，其特征在于，包括：
    获取模块，用于获取内存中的目标PTE，所述目标PTE中包括第一信息，所述第一信息用于表征目标内存页面的数据访问热度；
    确定模块，用于根据所述第一信息，确定所述目标内存页面的目标存储位置；
    交换模块，用于将所述目标内存页面交换至所述目标存储位置。
  16. 根据权利要求15所述的装置，其特征在于，所述数据访问热度是根据所述目标内存页面的访问频次确定的。
  17. 根据权利要求15或16所述的装置，其特征在于，所述第一信息包括设置于所述目标PTE第一预设字段的字段值，所述第一预设字段用于表征所述目标内存页面的数据访问热度等级；所述确定模块，具体用于：
    根据所述第一预设字段的字段值，确定所述目标内存页面的数据访问热度等级；
    确定与所述目标内存页面的数据访问热度等级相匹配的目标存储位置。
  18. 根据权利要求17所述的装置，其特征在于，所述数据访问热度等级包括热数据和温数据；
    若所述数据访问热度等级为热数据，则与所述目标内存页面相匹配的目标存储位置为本地内存；
    若所述数据访问热度等级为温数据，则与所述目标内存页面相匹配的目标存储位置为远端内存。
  19. 根据权利要求18所述的装置，其特征在于，所述数据访问热度等级还包括冷数据，若所述数据访问热度等级为冷数据，则与所述目标内存页面相匹配的目标存储位置为持久内存或硬盘。
  20. 根据权利要求15-19任一项所述的装置，其特征在于，所述第一信息包括设置于所述目标PTE第二预设字段的字段值，所述第二预设字段用于表征所述目标内存页面的当前存储位置；所述交换模块，具体用于：
    若所述目标存储位置与所述第二预设字段的字段值对应的当前存储位置相同，则保留所述目标内存页面在所述当前存储位置；
    若所述目标存储位置与第二预设字段的字段值对应的当前存储位置不同，则将所述目标内存页面交换至所述目标存储位置。
  21. 根据权利要求15-20任一项所述的装置，其特征在于，所述装置还包括：处理模块，用于：
    获取TLB中与所述目标内存页面对应的TLB表项，其中，所述TLB表项中包括第二信息，所述第二信息用于表征所述目标内存页面的访问频次；
    根据所述第二信息，确定所述目标PTE中的第一信息。
  22. 根据权利要求21所述的装置，其特征在于，所述第二信息包括所述TLB表项第三预设字段的字段值，所述第三预设字段用于记录所述目标内存页面在预设时长内的访问次数。
  23. 根据权利要求22所述的装置，其特征在于，所述预设时长为所述TLB表项的生命周期。
  24. 根据权利要求21-23任一项所述的装置，其特征在于，所述处理模块还用于：
    若算数逻辑单元ALU在访问所述TLB时命中所述TLB表项，则通过所述第三预设字段的字段值累加所述访问次数。
  25. 根据权利要求21-24任一项所述的装置，其特征在于，所述TLB表项的生命周期结束时，所述第三预设字段的字段值归零。
  26. 根据权利要求21-25任一项所述的装置，其特征在于，所述处理模块在根据所述第二信息，确定所述目标PTE中的第一信息时，具体用于：
    根据所述第三预设字段的字段值与预设访问次数阈值之间的关系，确定所述目标PTE中的第一信息。
  27. 根据权利要求26所述的装置，其特征在于，所述第一信息包括设置于所述目标PTE第一预设字段的字段值，所述第一预设字段的字段值用于表征所述目标内存页面的数据访问热度等级，所述处理模块在根据所述第三预设字段的字段值与预设访问次数阈值之间的关系，确定所述目标PTE中的第一信息时，具体用于：
    在所述TLB表项的生命周期结束时，若所述第三预设字段的字段值大于所述预设访问次数阈值，则将所述第一信息中第一预设字段的字段值设置为第一预设值；
    在所述TLB表项的生命周期结束时，若所述第三预设字段的字段值不大于所述预设访问次数阈值，则将所述第一信息中第一预设字段的字段值设置为第二预设值。
  28. 根据权利要求26所述的装置，其特征在于，所述第一信息包括设置于所述目标PTE第一预设字段的字段值和设置于所述目标PTE第四预设字段的字段值，所述第一预设字段与所述第四预设字段用于共同表征所述目标内存页面的数据访问热度等级，所述处理模块在根据所述第三预设字段的字段值与预设访问次数阈值之间的关系，确定所述目标PTE中的第一信息时，具体用于：
    在所述TLB表项的生命周期结束时，若所述第三预设字段的字段值大于第一次数阈值，则将所述第一预设字段的字段值和所述第四预设字段的字段值设为第一预设值；
    在所述TLB表项的生命周期结束时，若所述第三预设字段的字段值小于或等于所述第一次数阈值，且大于第二次数阈值，则将所述第一预设字段的字段值设置为第二预设值，将所述第四预设字段的字段值设为所述第一预设值；其中，所述第二次数阈值小于所述第一次数阈值；
    在所述TLB表项的生命周期结束时，若所述第三预设字段的字段值小于或等于所述第二次数阈值，则将所述第四预设字段的字段值设为所述第二预设值。
  29. 一种电子设备，其特征在于，包括：存储器，处理器以及计算机程序；
    其中，所述计算机程序存储在所述存储器中，并被配置为由所述处理器执行以实现如权利要求1至14中任一项所述的内存管理方法。
  30. 一种计算机可读存储介质，其特征在于，包括计算机代码，当其在计算机上运行时，使得计算机执行所述权利要求1至14中任一项所述的内存管理方法。
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