WO2022061016A1

WO2022061016A1 - Microstructure enhanced absorption photosensitive devices

Info

Publication number: WO2022061016A1
Application number: PCT/US2021/050717
Authority: WO
Inventors: Shih-Yuan Wang; Shih-Ping Wang
Original assignee: W&Wsens Devices, Inc.
Priority date: 2020-09-16
Filing date: 2021-09-16
Publication date: 2022-03-24
Also published as: EP4214540A1

Abstract

Microstructure enhanced photodector arrangements use a CMOS image sensor (CIS) wafer of crystalline Si and a CMOS Logic Processor (CLP) wafer stacked on each other for electrical interaction. The wafers can be fabricated separately and stacked or can be regions of the same monolithic chip. The image can be a time- of-flight image. Bayer arrays are enhanced with microstructure holes. Pixels can be photodiodes, avalanche photodiodes, single photon avalanche photodiodes and phototransistors can be on the same array and or germanium or silicon pixels.

Description

MICROSTRUCTURE ENHANCED ABSORPTION PHOTOSENSITIVE DEVICES

REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation-in-part of each of: U.S. Patent Appl. Ser. No. 17/182,954 filed February 23, 2021 ; International Patent Appl. No. PCT/US20/51733 filed September 21 , 2020; U.S. Patent Appl. Ser. No. 16/528,958 filed August 1 , 2019; International Patent Appl. No. PCT/US18/43289 filed July 23, 2018; and International Patent Appl. No. PCT/US 18/57963 filed October 29, 2019. [0002] This application incorporates by reference the entirety of the foregoing patent applications and claims the benefit of the filing date of each of the aboveidentified patent applications, as well as of the applications that they incorporate by reference, directly or indirectly, and the benefit of which they claim, including U.S. provisional applications, U.S. non-provisional applications, and International applications.

[0003] This patent application claims the benefit of and incorporates by reference each of the following provisional applications:

U.S. Prov. Ser. No. 63/241 ,414 filed September 7, 2021 ;

U.S. Prov. Ser. No. 63/236,195 filed August 13, 2021 ;

U.S. Prov. Ser. No. 63/228,491 filed August 2, 2021 ;

U.S. Prov. Ser. No. 63/223,508 filed July 19, 2021 ;

U.S. Prov. Ser. No. 63/218,855 filed July 6, 2021 ;

U.S. Prov. Ser. No. 63/208,358 filed June 8, 2021 ;

U.S. Prov. Ser. No. 63/194,059 filed May 27, 2021 ; U.S. Prov. Ser. No. 63/192,971 filed May 25, 2021 ; U.S. Prov. Ser. No. 63/175,026 filed April 14, 2021 ; U.S. Prov. Ser. No. 63/174,008 filed April 12, 2021 ; U.S. Prov. Ser. No. 63/172,078 filed April 7, 2021 ; U.S. Prov. Ser. No. 63/167,007 filed March 27, 2021 ; U.S. Prov. Ser. No. 63/161 ,915 filed March 16, 2021 ; U.S. Prov. Ser. No. 63/160,799 filed March 13, 2021 ; U.S. Prov. Ser. No. 63/157,703 filed March 6, 2021 ; U.S. Prov. Ser. No. 63/154,598 filed February 26, 2021 ; U.S. Prov. Ser. No. 63/143,004 filed January 28, 2021 ; U.S. Prov. Ser. No. 63/141 ,948 filed January 26, 2021 ; U.S. Prov. Ser. No. 63/136,101 filed January 11 , 2021 ;

U.S. Prov. Ser. No. 63/128,702 filed December 21 , 2020;

U.S. Prov. Ser. No. 63/125,349 filed December 14, 2020;

U.S. Prov. Ser. No. 63/117,449 filed November 23, 2020;

U.S. Prov. Ser. No. 63/116,387 filed November 20, 2020;

U.S. Prov. Ser. No. 63/110,345 filed November 6, 2020;

U.S. Prov. Ser. No. 63/104,358 filed October 22, 2020;

U.S. Prov. Ser. No. 63/090,669 filed October 12, 2020;

U.S. Prov. Ser. No. 63/083,705 filed September 25, 2020; and

U.S. Prov. Ser. No. 63/079,409 filed September 16, 2020.

[0004] All of the above-referenced provisional and non-provisional patent applications are collectively referenced herein as “the commonly assigned incorporated applications.”

FIELD

[0005] This patent specification relates mainly to photosensitive devices. More particularly, some embodiments relate to photosensitive devices having microstructure enhanced absorption characteristics and photosensitive devices being bonded or stacked with CMOS circuits.

BACKGROUND AND SUMMARY OF THE DISCLOSURE

[0006] Complementary metal oxide semiconductor (CMOS) image sensors (CIS) are used in many products including cameras for smartphones, tablets, laptops, smart television, interactive devices such as Amazon Alexa, gaming, virtual reality, augmented reality, home and business security, automotive products such as advanced driver assist systems (ADAS), and in medical imaging such as in endoscopy. Higher spatial resolution, smaller chip size, and /or extended range of wavelength responses are desired for such products, to the near infrared (NIR) region of 850 nm, 905 nm, 940 nm in silicon (Si) and 1350-1550 nm with germanium (Ge) on Si.

[0007] Other applications include three dimensional (3D) imaging using two or more cameras such as in human or insect vision, or time of flight (T oF), frequency modulation constant wave (FMCW), and/or light distance and ranging (LiDAR), using a light source in constant wave mode (CW) for indirect ToF or a pulse of light mode for direct ToF measurement of distance and topology of objects. Applications include facial recognition, LiDAR for ADAS, virtual and augmented reality, gaming, robotics, machine vision, medical imaging, drones.

[0008] T o satisfy higher spatial resolutions with smaller chip size, low jitter and high modulation frequency (for ToF), pixels dimensions are in the microns and submicron range where each pixel is a square in most cases and the thickness of Si ranges from 1 to 6 microns and in some cases is sub-micron. The thin silicon allows for a fast rise time and therefore a low jitter time that can be in the range of tens of picosecond and in some cases 10 picosecond or less and modulation in the GHz range for FMCW. Depths of millimeters and in some cases sub millimeter can be resolved. However, with thin silicon the external quantum efficiency is degraded and technology such as photon or light or lightwave trapping can be used to enhance photon absorption and therefore increase the external quantum efficiency (EQE) when EQE is directly proportional to photon absorption. This is particularly important at NIR wavelengths where the Si absorption coefficient is low; for example at 800 nm the absorption coefficient is 850/cm and at 980 nm the absorption coefficient is 96/cm as compared to blue 400 nm at 95000/cm, green 530 nm at 7800/cm and red 700 nm at 1900/cm. As the pixels size approaches one micron or less, a single microstructure hole can significantly enhance absorption and therefor EQE as disclosed in this patent specification, compared to the use of multiple inverted pyramids, see reference. Yokogawal , IR sensitivity enhancement of CMOS Image Sensor with diffractive light trapping pixels, or multiple rectangular holes or trenches; see also reference Park et el, Pixel Technology for Improving IR Quantum Efficiency of Backside- illuminated CMOS Image Sensor. In some cases, a composite microhole can be used where the composite microhole consists of multiple smaller holes.

[0009] CIS can be monolithically integrated; however, for high density pixels stacking technologies are often used such that connecting electrodes from the CMOS application specific integrated circuits (ASIC) electronics would not interfere with packing density of the pixels nor partially block incident light. The photosensors or pixels are fabricated on one wafer and the CMOS ASICs on another wafer and matching bonding electrodes are formed on each wafer and bonded together, as discussed in reference Kagawa et al, Novel Stacked CMOS Image Sensor with Advanced Cu2Cu Hybrid Bonding; Haruta et al, A 1/2.3inch 20Mpixel 3-Layer Stacked CMOS Image Sensor with DRAM.

[0010] With a single microstructure hole per pixel, the red green blue (RGB) pixel EQE can be enhanced in addition to NIR wavelengths in a standard Bayer pattern, see reference Yokogawal for example. In this patent specification a modified Bayer pattern is described in which RGB and NIR have their own filters and NIR can be seen in bright light for example. In addition, the microhole can have different shapes and or dimensions for different ranges of wavelengths for each RGB and NIR pixels.

[0011] Stacking technologies used for CIS can be applied to very high speed optical receivers for data center optical interconnect, 5G optical links, enterprise optical interconnects where arrays of 56Gb/s photodetectors are fabricated on one wafer and 112Gb/s CMOS or BiCMOS ASICs on another wafer with matching bonding electrodes and bonded together. Different Si layer thicknesses can be used for high speed photodetectors and for CMOS ASICs. The 112Gb/s CMOS ASICs can use a 20 nm thick Si on SOI (Si on insulator) wafer and photodetectors can use 100-3000 nm thick Si on oxide. Using multiple bits in each clock cycle such as pulse amplitude modulation (PAM), for 2 bits per clock cycle, or PAM4, 112Gb/s can be transmitted and received with a 56 Gb/s photodetector array. A 2x5 array of 56Gb/s photodetectors can have an aggregated data bandwidth of 1120 Gb/s. At these millimeter wavelengths parasitic circuit elements such as capacitance, inductance and resistance can degrade the optical receiver performance, for example see reference. Shi, Ultrahigh Speed Transceiver Package with Stacked Silicon Integration Technology. By using Stack technology together with microstructure holes and with photodetector (PD) arrays ranging in size from 5 micron by 5 micron to 30 micron by 30 micron and Si layer thickness from 100 nm to 3000 nm, 56Gb/s can be achieved with optical absorption ranging from 30 to 85 % or more at certain wavelengths in the range 800-950 nm. In this particular example the microholes are doped in the sidewalls and adjacent holes are doped in opposite polarity. With Ge on Si, the wavelength range can be extended to 1350 nm and 1550 nm for medium and long reach optical interconnects. [0012] Photosensors with a single or plural microstructure holes to enhance sensitivity, EQE, photon absorption can improve products in three major multibillion USD business sectors. Market size for CIS imaging 13D/ ToF is a multibillion USD market growing at CAGR of 44%; see reference 3D Imaging & Sensing - Market and Technology www.yole.fr 2018. Market size for LiDAR for ADAS is also multi-billion USD; The Automotive LiDAR Market April 2018, Yole. Optical interconnect for Data Center is also a multi-billion USD market. See e.g., Light Counting April 2018, https://www.lightcounting.com, all of which are incorporatated by reference herein.

SUMMARY OF INITIALLY CLAIMED SUBJECT MATTER

[0013] According to some embodiments, a microstructure enhanced absorption photosensitive device comprises: a CMOS ASIC wafer and a CMOS image sensor wafer (CIS) stacked to each other such that the CMOS ASIC wafer is configured to receive and process signals that the CIS wafer produces, wherein the CIS wafer comprises: a semiconductor material in which an array is formed of both Si pixels and Ge pixels; wherein each Si pixel comprises an upper and a lower region of Si doped to opposite polarities and a region of undoped or low-doped Si between said doped Si regions, and a single microhole extending into the Si pixel; wherein each Ge pixel comprises an upper and a lower region of Ge or an alloy thereof doped to opposite polarities and a region of undoped or low-doped Ge or an alloy thereof between said doped regions of Ge or an alloy thereof, and a single microhole extending into the Ge pixel; deep trench insulation (2580) between adjacent Si pixels and Ge pixels in said array and an electrically and optically isolating material in said deep trench insulation and in said microholes in the Si and Ge pixels; and pixel electrodes coupled to said Si and Ge pixels, connecting electrodes coupled to at least some of the pixel electrodes, and bonding electrodes coupled to at least some of the connected electrodes, configured to convey electrical signals between said pixels and said CMOS ASIC wafer.

[0014] According to some embodiments, the device further includes one or more of the following: (a) said Si pixels are configured to operate at shorter wavelengths of light and said Ge pixels are configured to operate at longer wavelengths of light, wherein said array of Si and Ge pixels is responsive to light in at least portions of the 400 nm to 1700 nm wavelength range with absorption greater than 50%; (b) each of at least some of said microholes comprises a closely spaced group of nanoholes, said groups having cross-sectional shapes matching those of said single holes; (c) each of at least some of said microholes comprises two or more nanoholes that partly overlap to thereby form a single microhole; (d) said array includes additional pixels that are otherwise as said Si and/or Ge pixels but are free of said microholes; (e) at least some of the pixels in the array are electrically coupled with each other to combine electrical output of a plurality of the coupled pixels into a single combined output, whereby a group of pixels is configured to capture the same incident beam of light and improve a signal-to- noise ratio; (f) each of at least some of said microholes comprises a group of closely spaced nanoholes that differ from each other in size and serve as the single hole of a pixel; (g) at least some of the microholes in the array differ from each other in size and/or shape; (h) two or more of said CMOS ASIC wafers and/or two or more of said CMOS image sensor wafers are stacked to each other; (i) each of at least some of said pixels is formed with other of said doped regions conformally lining said mirohole an extending along at least one sidewall of the undoped or low-doped region to connect to one of said anode and cathode, and said anode and cathode are at a side of said CIS wafer facing said CMOS ASIC wafer; (j) in each of at least some of said pixels one of the doped regions conformally lines the pixel’s microhole and differs in polarity between adjacent pixels; (k) further including Bayer pattern color filters over at least some of said pixels, said color filters in the Bayer pattern including NIR filters for visible light over some pixels and NIR ToF filters over other pixels, wherein said array of pixels is configured for simultaneous imaging by the pixels under all said filters; (I) said deep trench insulation includes an amorphous semiconductor material between adjacent pixels to reduce optical crosstalk.

[0015] According to some embodiments, a method comprises: stacking and bonding to each other a CMOS ASIC wafer and a CMOS image sensor wafer (CIS) such that the CMOS ASIC wafer is configured to receive and process signals that the CIS wafer produces; forming the CIS wafer in a semiconductor material by fabricating an array of pixels therein; forming at each pixel an upper and a lower region of semiconductor material doped to opposite polarities and a region of undoped or low-doped semiconductor material between said doped regions, and a single microhole extending into the pixel; forming deep trench insulation between adjacent pixels in said array and an electrically and optically isolating material in said deep trench insulation and in said microholes in the pixels; and forming pixel electrodes coupled to said pixels, connecting electrodes coupled to at least some of the pixel electrodes, and bonding electrodes coupled to at least some of the connected electrodes, configured to convey electrical signals between said pixels and said CMOS ASIC wafer.

[0016] According to some embodiments, the forming of said array comprises forming some of the pixels in the array of Si doped and undoped or low-doped regions and some of the pixels in the array of doped and undoped or low-doped regions that comprise Ge or alloys thereof.

[0017] According to some embodiments, a microstructure enhanced absorption photosensitive device comprises: a CMOS ASIC wafer and a CMOS image sensor wafer (CIS) stacked to each other such that the CMOS ASIC wafer is configured to receive and process signals that the CIS wafer produces, wherein the CIS wafer comprises: a semiconductor material in which an array of pixels is formed; wherein each pixel comprises an upper and a lower region of Si doped to opposite polarities and a region of undoped or low-doped Si between said doped Si regions, and a single microhole extending into the Si pixel; deep trench insulation between adjacent pixels in said array and an electrically and optically isolating material in said deep trench insulation and in said microholes; and pixel electrodes coupled to said Si and Ge pixels, connecting electrodes coupled to at least some of the pixel electrodes, and bonding electrodes coupled to at least some of the connected electrodes, configured to convey electrical signals between said pixels and said CMOS ASIC wafer.

[0018] According to some embodiments, the device that the immediately preceding paragraph describes further includes one or more of the following: (a) said pixels comprise both Si pixels and Ge pixels and (i) each Si pixel comprises an upper and a lower region of Si doped to opposite polarities and a region of undoped or low-doped Si between said doped Si regions, and a single microhole extending into the Si pixel, and (ii) each Ge pixel comprises an upper and a lower region of Ge or an alloy thereof doped to opposite polarities and a region of undoped or low-doped Ge or an alloy thereof between said doped regions of Ge or an alloy thereof, and a single microhole extending into the Ge pixel; (b) each of at least some of said microholes comprises a closely spaced group of nanoholes, said groups having cross-sectional shapes matching those of said single holes; (c) further including in said array pixels additional pixels that are free of said microholes; and (d) at least some of the microholes in the array differ from each other in size and/or shape.

[0019] The term “hole” refers in this patent specification to a deliberately formed volume of material shaped and dimensions as specified, that differs from surrounding material in specified electrical and/or optical properties. The material of a hole can be solid, such as a semiconductor with such different electrical/optical properties, or a dielectric, or a gas such as air, or even vacuum. A hole can be into a top surface of a layer, or into a bottom surface, or can be an internal volume that is between a top layer and a bottom layer of a device. Numerous examples of such holes are described in detail infra., and some are interchangeably called protrusions, for example when a hole in the underside of an l-layer is an indentation filled with material protruding from a layer below.

[0020] The term “electrode” refers in this specification to material that serves to create desired electrical fields in the disclosed devices and to extract desired electrical signals that the devices produce in response to light illumination.

Numerous examples of electrodes are described in detail infra., for example electrodes that comprise electrically conductive material in ohmic contact with doped regions of a device, or electrically conductive material that makes other types of contact such as Schottky junctions.

[0021 ] The terms “top” and “bottom” and similar terms refer to a specified orientation of a device so that, for example, the top of a device being described below becomes its bottom when the device is flipped over or becomes its left or right side when the device is turned 90 degrees.

[0022] The term “inverted pyramid” refers to a hole that is pyramid-shaped and has a square top from which it tapers downwardly to a point or a smaller area. For example, anisotropic wet etch of crystalline silicon (100) surface along (111) crystal facets forms an angle of 54.7 degrees with respect to the (100) crystal plane and can result in an inverted pyramid hole. An inverted pyramid often has a square base (top area) but in some cases can have a rectangular base, for example when several inverted pyramids are in contact or very close proximity.

[0023] As used herein, the terms “BOX” and “buried oxide” can refer in this patent specification to a buried silicon dioxide material, as in silicon-on-insulator (SOI) structures where the BOX layer is between the Si device layer and the Si handle substrate, but also can encompass any insulating and /or dielectric material. Examples of such insulating materials include, without limitation, silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, molybdenum oxide, titanium oxide, aluminum nitride, and also amorphous semiconductor material and combinations of said materials. Furthermore, the terms “BOX” and “buried oxide” can refer to material that is not yet buried, or never buried, such as material that is deposited or formed on a surface.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To further clarify the above and other advantages and features of the subject matter of this patent specification, specific examples of embodiments thereof are illustrated in the appended drawings. It should be appreciated that these drawings depict only illustrative embodiments and are therefore not to be considered limiting of the scope of this patent specification or the appended claims. The subject matter hereof will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:

[0025] FIG. 1A shows a partial simple schematic cross section of high speed Si photodetector array stacked to a high speed complementary metal oxide semiconductor (CMOS) application specific integrated circuits (ASICs), according to some embodiments;

[0026] FIG. 1 B is a simple schematic cross section similar to FIG. 1 A with the addition of a stacking layer on top of the PD I PD array wafer that can guide optical fiber precisely to the photodetector(s), according to some embodiments;

[0027] FIG. 1C shows a simple partial schematic cross section a lll-V photodetector and I or Photodector array that can be a flip chip bonded and I or wafer bonded to a Si interposer that is stacked to a high speed CMOS ASICs wafer, according to some embodiments; [0028] FIG. 2A shows a partial simple schematic cross section of a photodetector array wafer stacked to CMOS ASICs wafer, according to some embodiments

[0029] FIG. 2B shows a simple partial cross section schematic of a high speed phototransistor, according to some embodiments;

[0030] FIGs. 2C to 2F are simple partial schematic top views of various arrangements of microholes in a high speed photodetector, according to some embodiments;

[0031] FIGs. 2G and 2H show simple partial schematic cross sections of high speed photodetector or photodetector arrays, according to some embodiments;

[0032] FIG. 3A-3H are simple partial schematic of top views and cross sectional views of pixels examples used for Lumerical simulation of complete CMOS image sensors with Bayer RGB pattern (Red , Green, Blue), according to some embodiments;

[0033] FIGs. 4A-4E are simple partial cross section schematics of various arrangements of photosensors, according to some embodiments;

[0034] FIGs. 5A- 5F are plots of Lumerical simulations of structures shown in FIGs. 4A-4C;

[0035] FIGs. 6A-6C show simple partial schematic cross sections of a CMOS image sensor wafer bonded to CMOS logic ASICs wafer, according to some embodiments;

[0036] FIG. 7 is a plot showing a Lumerical simulation of absorption vs wavelength from 300 - 1000 nm of pixels with a single funnel hole as in FIGs. 3G and 3H, according to some embodiments;

[0037] FIG. 8 is a plot showing a further Lumerical simulation of absorption vs wavelength 300 - 1000 nm of pixels with a single funnel hole as shown in FIGs. 3G and 3H, according to some embodiments;

[0038] FIGs. 9A-9C show modified Bayer patterns, according to some embodiments;

[0039] FIGs. 10A-10I are simple partial cross-sectional views of microstructure hole(s), according to some embodiments;

[0040] FIGs. 11 A-111 are simple schematic top view examples of microstructure holes, according to some embodiments; [0041] FIGs. 12A-12C are simple partial schematic cross section views of microstructure hole formed by a series of smaller micro or nano holes, according to some embodiments;

[0042] FIG. 13A shows a simple, partial schematic of a top view of a single pixel with a composite hexagonal shaped hole that is comprised of multiple nanoholes, according to some embodiments;

[0043] FIG. 13B shows a simple partial cross section schematic of FIG. 13A, according to some embodiments;

[0044] FIG. 13D shows a Lumerical simulation of absorption of a complete CMOS image sensor with microlens and RGB filters as discussed in Devine et al., according to some embodiments;

[0045] FIG. 13E shows a simple partial schematic top view of a square pixel 1.12 micron per side with a trench of 250 width and a depth of 2.5 microns filled with Si dioxide, according to some embodiments;

[0046] FIG. 14A shows a Lumerical simulation of absorption of a complete CMOS image sensor with microlens and RGB filter as discussed in Devine et al. ; [0047] FIG. 14B shows a simple partial schematic top view of a square pixel with 1.1 micron per side with a large 400 nm diameter cylindrical hole in the center surrounded by 6 equally spaced cylindrical holes with 200 nm diameter;

[0048] FIG. 14C shows a simple partial cross section schematic of FIG. 14B where the 400 nm cylindrical hole is etched to a depth of 2 microns and the 200 nm cylindrical hole is etched to a depth of 1 micron, and the spacing between the 200 nm hole and 400 nm hole is 20 nm;

[0049] FIGs. 15A and 15B show simple partial schematic cross sections of a CMOS image sensor, according to some embodiments;

[0050] FIGs. 16A and 16B show simple partial schematic cross section of Ge or GeSi alloys on Si, according to some embodiments;

[0051 ] FIGs. 17A-17C are partial simple schematic cross sections of a photosensor or pixel wafer stacked to CMOS ASICs, according to some embodiments;

[0052] FIGs. 18A-18F are partial schematic top views of pixels for CMOS image sensors, according to some embodiments; [0053] FIGs. 19A-19C are simple partial schematic of the top views of a single pixel, according to some embodiments;

[0054] FIGs. 20A-20C are simple partial cross section schematics of a pixel or photosensor or photodetector with different microhole or holes, according to some embodiments;

[0055] FIGs. 21 A-21 D are plots showing FDTD Lumerical simulation of a single inverted pyramid in a pixel similar to FIG. 3F;

[0056] FIG. 21 E plots the absorption or optical efficiency vs base dimension of the inverted pyramid for 800 nm wavelength;

[0057] FIGs. 22A-22C are plots showing a FDTD Lumerical simulation of a single cylindrical hole in a pixel similar to FIG. 3B, according to some embodiments;

[0058] FIG. 22D shows a single cylindrical hole with a diameter of 800 nm in a pixel as described above with respect to FIG. 22A at 850 nm wavelength where the plot shows a variation of absorption / OE as a function of the etched depth of the cylindrical hole;

[0059] FIG. 23 shows a table of percentage of volume of crystalline semiconductor of a pixel reduced by the introduction of a single microhole etched into the pixel;

[0060] FIG. 24 shows a simple partial schematic top view of a single 3-D integrated chip using stacking technology of a high speed optical receiver, according to some embodiments; and

[0061] FIG. 25 shows a partial simple schematic cross section of a pixel array that can consist of both Si pixels 2530 and Ge/Ge alloy on Si pixels 2532, according to some embodiments.

DETAILED DESCRIPTION

[0062] A detailed description of examples of preferred embodiments is provided below. While several embodiments are described, it should be understood that the new subject matter described in this patent specification is not limited to any one embodiment or combination of embodiments described herein, but instead encompasses numerous alternatives, modifications, and equivalents. In addition, while numerous specific details are set forth in the following description in order to provide a thorough understanding, some embodiments can be practiced without some or all of these details. Moreover, for the purpose of clarity, certain technical material that is known in the related art has not been described in detail in order to avoid unnecessarily obscuring the new subject matter described herein. It should be clear that individual features of one or several of the specific embodiments described herein can be used in combination with features or other described embodiments. Further, like reference numbers and designations in the various drawings indicate like elements.

[0063] All publications cited in this patent specification are hereby incorporated by reference. Some of the figures described herein are simplified in that for clarity they may omit elements of structures that skilled persons would understand need not be shown expressly and the figures may show only a portion of a structure that comprises repeated patterns of the shown portions. For example, a figure may show a device with a single pair of laterally spaced electrodes where the actual device being described includes a collection of two or more such regions on or in the same substrate. The Greek letters v (nu) and TT (pi) denote in this specification semiconductor material that is low doped to N and P doping, respectively, e.g., to no more that about 10¹² per cm³ doping. The semiconductor material regions described in this patent specification are material that is single-crystal or essentially single-crystal except for the deliberately formed “holes” described below, unless otherwise specified. The terms “partial” or “partially” regarding the depth of holes or of etching refer in this specification to holes that extend partway into a region rather than through the entire region.

[0064] The photodetectors described herein can be pixels I photosensors for CMOS imaging, and for 3D Time-of-Flight imaging and for high speed photodetectors for optical data communication. These photodetectors can operate as a photodiode (PD), avalanche photodiode (APD), and/or single photon avalanche photodiode (SPAD) with a reverse external bias voltage. In some cases, the photodetectors can operate in a photo transistor mode where forward source drain voltage can be applied with or without a gate voltage which normally is reverse bias. In some cases, the photodetectors can operate in a photoconductor mode where it can be biased either in the forward or reverse direction. In addition to external bias used for the operation of these photodetectors, a time constant is normally associated with each application. For example, for CMOS image sensors, the time constant can range from seconds to milliseconds, for 3D imaging or Time-of-Flight applications the time constant can range from 10’s of nano seconds to pico seconds, and for optical data communication applications the time constant can range from nanoseconds to picoseconds, or from 1 Gb/s to 100 Gb/s or more. In addition, each application can be associated with a 2D array size; for example for 3D imaging the array can range from 1 million to 100 million pixels or more. For Time-of-Flight the array size can range from 1000 to 10 million or more, and for optical data communication the array can be 1 D or 2D, and can range in size from 4 to 100 or more. For high spatial resolution CMOS imaging and 3D imaging the pixel size can range from 0.5 microns to 5 microns, and in some cases for lower spatial resolution the pixel size can range from 10 microns - 100 microns or more, and for optical data center applications the photodetector can have a lateral dimension ranging from 2 microns to 100 microns, and in some cases 5 microns to 30 microns. In most cases pixels are in a square configuration, however other configurations are possible, and the dimensions given represent a typical lateral dimension of the pixels for example a pixel can be triangular or polygonal in which the lateral dimension can be the height of the triangle or a diagonal of the polygonal shape. For optical data communications the photodetectors are typically circular, and the dimensions represent the diameter, and in some cases can be polygonal in which case the lateral dimension can represent the largest diagonal for example.

[0065] Throughout this description, it is understood that P and/or N type doped regions can be formed in the photodetector such as PN, PIPN, PIP, NIN, PNP, NPN, to name a few to operate in a PD / APD I SPAD I photoconductor I phototransistor modes for example. A voltage bias range can be 0.1 - 3.3 volts for photodiodes, 3 volts - 35 volts for APD, SPAD, and 1 volt - 15 volts for phototransistors. The bias voltages can be applied to P and N regions, and in some cases to P and P, N and N.

[0066] Throughout this description, it is understood that the photodetectors can be front side illuminated or back side illuminated, and in some cases front side and back side illuminated. These photodetectors can be monolithically integrated with CMOS (complementary metal oxide semiconductor) ASICs (application specific integrated circuits) where the ASICs can be designed for specific applications such as image sensors, Time-of-Flight, or optical data communication. In some cases, the photodetector array can be stacked with CMOS ASICs where the photodetector array are fabricated on a separate wafer from the CMOS ASICs wafer, and then the wafers are bonded together and interconnect metal electrodes and I or silicide electrodes are formed between the detector array and CMOS ASICs.

[0067] In some cases, multiple P and N regions can be formed in or on a photodetector which can be a pixel photosensor, photodiode, photoconductor, phototransistor, photogating, APD, SPAD, silicon photomultiplier to name a few and is some cases there can be multiple pn junctions. In some cases, metal oxide semiconductor (MOS) junctions and or Schottky junctions can be formed. In some cases, the photodetector can have an i or intrinsic or low doped region.

[0068] Photodetectors such as pixel-photosensors, photodiodes, APDs, SPADs, photoconductors, phototransistors with a microstructure hole or holes or with composite micro hole or holes can have a higher external quantum efficiency than a comparable photodetectors without microstructure hole or holes or composite micro hole or holes at certain wavelength ranges. Some small photodetectors with lateral dimensions of approximately equal to or less than 3 microns and in some cases approximately equal to or less than 5 microns with only a single microstructure hole or single composite microstructure hole can have an external quantum efficiency greater than a comparable photodetector without a microstructure hole or composite micro structure hole at certain wavelength ranges. [0069] FIG. 1A shows a partial simple schematic cross section of high speed Si photodetector array stacked to a high speed complementary metal oxide semiconductor (CMOS) application specific integrated circuits (ASICs), according to some embodiments. According to some embodiments, the CMOS ASICs wafer 120 can include one or more of the following circuits: trans impedance amplifiers (TIA) clock data recovery circuits (CDR), and other circuits such as equalizers and secondary amplifiers, and in some cases logic processors, buffer memories and transmitting electronics for completing an optical receiver for data center applications. The stacked technology can be similar to CMOS image sensors stacked with CMOS ASICs, such as discussed in Haruta et al, A 1/2.3 20Mpixel 3- Layer Stacked CMOS Image Sensor with DRAM, IEEE International Solid-State Circuits Conference 2017, which is incorporated by reference herein.

[0070] Microstructure holes 140 are formed in the high speed Si photodetector 130 to enhance absorption and therefore the external quantum efficiency (EQE) since EQE is directly proportional to optical absorption. In this example cylindrical holes 140 are formed in Si on insulator (SOI) where the Si layer 102 can have a thickness ranging from 100 nm - 3,000 nm, and in some cases more than 3,000 nm. The cylindrical holes 140 are etched partially or fully into the Si device layer 102 and are conformally doped P type (134) or N type (136) such that adjacent microstructure holes have opposite polarity doping. Anodes 154 are formed on the P type holes, and cathodes are formed on the N type holes (not shown) and a reverse bias is applied between the anode and cathode. The P type holes can be connected together using connecting electrodes 152 and the N type holes can be connected together by connecting electrodes (not shown). The anode and cathodes are then connected through the oxide I dielectric layers 106 and 104 by connecting electrodes 152 and to the bonding electrodes where the high speed CMOS ASICs can have corresponding bonding electrodes 150, and the photodetector wafer 110 can be bonded at bond interface 160 to the CMOS ASICs wafer 120 using stacked technology as discussed in Haruta et al.

[0071 ] The photodetector wafer 110 is fabricated separately from the CMOS ASICs wafer 120, and the photodetector wafer 110 can have a Si layer 102 thickness optimized for high speed photodetectors. The microstructure cylindrical holes 140 can have a diameter ranging from 600 - 1 ,300 nm and in some cases 800 - 900 nm. The cylindrical holes 140 can be arranged in a square or hexagonal or aperiodic pattern, and in the case of a square or hexagonal pattern the spacing between the holes can range from 100 - 500 nm, and in some cases 200 - 400 nm. For example, for a 800 nm diameter cylindrical hole the period can be 1000 nm - 1100 nm in a square lattice for example with a Si device layer thickness of 500 - 2000 nm. In the case where microstructure holes 140 are not circular the lateral dimension of the hole can include a range from 600 - 1600 nm, and in some cases greater than 1600 nm. The photodetector 130 can have a lateral dimension of 5 microns x 5 microns to 30 microns x 30 microns or more. In the case where the photodetector 130 is not a square, for example circular, rectangular, polygonal, to name a few, the lateral dimension of the photodetector can include a dimension in the range of 5 micron - 100 microns, and in some cases greater than 100 microns. Data rate for the high speed optical detector can range from 28 Gb/s - 56 Gb/s and in some cases 112 Gb/s or more. Wavelength range that can be detected by the high speed optical detector can range from 700 - 1000 nm, and in some cases 800 - 950 nm.

[0072] The high speed CMOS ASICs wafer 120 can have a data rate of 112 Gb/s and in some cases greater than 112 Gb/s and the SOI wafer can be optimized for high data rate with the Si device layer thickness of approximately 20 nm and in some cases less than 20 nm. By using stacked technology the photodetector can be optimized separately from the CMOS ASICs wafer and each wafer can be optimized for its specific application. By using the stacked technology the parasitic of the connecting electrodes from the high speed photodetector to the high speed CMOS ASICs can be minimized and the electrodes length can be controlled to a few microns. Such reduction in parasitics such as inductance, capacitance, resistance between the high speed photodetector and the high speed CMOS ASICs is critical to ensure reproducible, repeatable and uniform high performance which can result in high yield and therefore reduce manufacturing cost.

[0073] As shown the microstructure holes 140 are cylindrical; however other shapes of the microstructure hole 140 can be inverted pyramids, funnel, trapezoidal cross sections and in addition the shape of the hole can be circular, square, rectangular, polygonal, clover leaf amoebic and I or any combination of shapes and sizes. In addition, as shown the photodetector is a photodiode however with other doped regions such as PIPIN, PN, NINIP, PNP, NPN, NIN, PIP to name a few can be used for avalanche photodiode (APD), single photon avalanche photodiode (SPAD) and I or phototransistors.

[0074] As shown the photodetector array with the CMOS ASICs can operate at high data rates for optical interconnects in data centers, 5G networks, XG networks where X can be a number greater than 5, enterprise, high performance computing to name a few. In addition with a larger array this configuration of stacked photodetector array and CMOS ASICs can be used for LiDAR and LiDAR imaging, Time-of-Flight (ToF) imaging for applications in robotics, machine vision, virtual reality (VR), augmented reality (AR), autonomous vehicles to name a few. The time jitter or rise time for ToF applications can be in the pico second range. The wavelength range can be from 800 - 1000 nm, and for some applications a wavelength range including 905 nm and a wavelength range including 940 nm. Wavelength 905 nm is commonly used for ToF such as LiDAR and wavelength 940 nm is commonly used for facial recognition, AR/VR.

[0075] As shown in FIG. 1A optical filters 170 and microlens 172 are integrated with the photodetector array, however in some cases the optical filter (not shown) and microlens 172 may not be needed and stand alone optical filters 170 and microlens 172 can be packaged with the photodetector array. Integration of optical components such as optical filter 170 and microlens 172 with the photodetector array can significantly reduce packaging costs. The optical filters 170 are important for applications such as ToF, LiDAR ToF imaging, applications where the ambient light needs to be filtered out to maximize signal to noise ratio of the optical signal. The optical filter 170 can be customized for each or sets of photodetectors in the array and in some cases can be single blanket optical filter common to all photodetectors in the array. For data center applications optical filters 170 may not be needed, however in cases where multiple optical signals with different wavelengths optical filters tuned to each specific wavelength range of the optical signal may be used to minimize cross talk between the optical channels. Also shown in FIG. 1A is isolation trench(es) 180.

[0076] According to some embodiments, stacking of multiple wafers can be implemented, which can include logic, memory, and data signal communication functionalities for example.

[0077] FIG. 1 B is a simple schematic cross section similar to FIG. 1 A with the addition of a stacking layer on top of the PD I PD array wafer that can guide optical fiber precisely to the photodetector(s), according to some embodiments. The precision optical fiber guide can be vertical, and in some cases can be horizontal as shown in FIG. 1 B. Si stacked wafer 198 can includes optical fiber guides 194. The optical fiber 192 can be multimode fiber (MMF) or singlemode fiber (SMF) and in some cases can be fiber ribbon. The fiber guides 194 can be made of an Si wafer 198 and bonded at bond interface 196, for example. [0078] FIG. 1C shows a simple partial schematic cross section a lll-V photodetector and I or Photodector array that can be a flip chip bonded and I or wafer bonded to a Si interposer that is stacked to a high speed CMOS ASICs wafer, according to some embodiments. The lll-V photodetector and I or Photodector array 171 can be GaAs, InP, and/or InGaAs to name a few. The PD/PD array 171 can be a flip chip bonded and I or wafer bonded to a Si interposer 111 that is stacked at bond interface 160 to a high speed CMOS ASICs wafer 120 which can include TIA, CDR, amplifiers, normalizers, and in some cases can include multiple stacking of CMOS ASICs wafers that can include logic, memory and data signal communication functionalities. The Si interposer 11 includes connecting electrodes 151.

[0079] In some cases, trans silicon via (TSV) can be used as connecting high speed electrodes and I or bias electrodes to the lll-V photodetectors which can be photodiode, APD, SPAD, phototransistors array to name a few.

[0080] FIG. 2A shows a partial simple schematic cross section of a photodetector array wafer stacked to CMOS ASICs wafer, according to some embodiments. The structures shown are similar to those shown in FIG. 1A. In this example, Ge and I or Ge alloy such as GeSn, GeSi, GeSiSn 230 to name a few can be selective area grown on a SOI wafer 210 where the Si device layer 208 can have a thickness ranging from 10 - 100 nm, and in some cases greater than 100 nm, and where the Ge or Ge alloy 230 can have a thickness of 200 nm - 3000 nm, and in some cases greater than 3000 nm. Microstructure holes 140 such as cylindrical hole, funnel shaped hole, trapezoidal shaped hole cross section can be etched into the Ge 230 partially or fully to enhance optical absorption in Ge and therefore enhance EQE since EQE is directly proportional to optical absorption.

The microstructure holes are conformally doped with N type dopant (136) and I or P type dopant (134) such that adjacent holes can have opposite doped polarities. The microhole 140 can be circular, rectangular, square, polygonal, clover, amoebic or any combination of shapes. In the case of cylindrical holes as shown in this example can have a diameter ranging from 600 - 1500 nm, and in some cases 1000 - 1300 nm. In the case where the microstructure hole 140 is not circular the lateral dimension can include dimensions in the range of 600 - 1600 nm, and in some cases greater than 1600 nm. The spacing between adjacent microstructure holes can range from 300 - 600 nm, and in some cases greater than 600 nm. The holes can be arranged in a periodic manner such as a square or hexagonal lattice, and in some cases can be an aperiodic arrangement. The photodetector size can range from 5 microns x 5 microns to 30 microns x 30 microns, and in some cases greater than 50 microns x 50 microns. In the case where the photodetector is not a square, for example circular, rectangular, polygonal, to name a few, the lateral dimension of the photodetector can include a dimension in the range of 5 microns - 100 microns, and in some cases greater than 100 microns. The wavelength can range from 800 nm - 1700 nm, and in some cases from 1000 nm - 2200 nm. In certain applications the wavelength can be at 1310 - 1350 nm, and a wavelength range including 1550 nm.

[0081] For high speed data communication the photodetector can operate at 56 Gb/s - 112 Gb/s and in some cases greater than 112 Gb/s. The CMOS ASICs can consist of TIA, CDR, and other necessary electronics for data processing and transmission, operating at data rates of 56 Gb/s - 112 Gb/s and in some cases greater than 112 Gb/s. For LiDAR and ToF imaging the jitter and I or rise time can be in the pico second range with applications in autonomous vehicles, machine vision, AR/VR, robotics, to name a few.

[0082] As shown in FIG. 2A optical filters 170 and microlens 172 are integrated with the photodetector array, however in some cases the optical filter and microlens may not be needed and stand alone optical filters and microlens can be packaged with the photodetector array. Integration of optical components such as optical filter and microlens with the photodetector array can significantly reduce packaging costs. The optical filters are important for applications such as ToF, LiDAR ToF imaging, applications where the ambient light needs to be filtered out to maximize signal to noise ratio of the optical signal. The optical filter 170 can be customized for each or sets of photodetectors in the array and in some cases can be single blanket optical filter common to all photodetectors in the array. For data center applications optical filters may not be needed, however in cases where multiple optical signals with different wavelengths optical filters tuned to each specific wavelength range of the optical signal may be used to minimize cross talk between the optical channels. See, e.g. Song et al, High-efficiency and high-speed germanium photodetector enabled by multiresonant photonic crystal, De Gruyter, Nanophotonics 2020; 20200455, which is incorporated by reference. Song et al discusses a 56Gb/s Ge on Si photodetector at 1550 nm wavelength. In Song et al, the microholes were arranged in a photonic crystal pattern to enhance the absorption efficiency at 1550 nm wavelength.

[0083] Microholes 140 can be arranged in a variety of patterns, one of which is a photonic crystal pattern that can exabit a resonance at the target wavelength of interest, or can be arranged in a non photonic crystal pattern that can be periodic and I or aperiodic and can be a broad band over a wide wavelength range of 100 nm or more and does not exabit resonance for example at a target wavelength. [0084] FIG. 2B shows a simple partial cross section schematic of a high speed phototransistor, according to some embodiments. The contoured doping 236 of the microholes 140 is N type and the space 230 between the microholes 140 can be I or low dope P type Si. P region 234 is provided below the microholes 140. A bias is applied between adjacent holes 140, and the bias can be a forward bias or a reverse bias to saturation current between the two N type adjacent holes such that NPN or NIN phototransistor structure is fabricated and without incoming photons the dark current is low. With illumination there will be an increase of current between the adjacent N type holes. The effect is similar to a fully pinched off transistor that with the application of illumination can behave like a gate and the current between the adjacent N type holes can increase. The gain of the phototransistor can range from 3dB to 30dB or more, and the frequency of the transistor can range from 1GHz to 100GHz or more. The wavelength can range from 400 nm - 1100 nm, the bias voltage can range from 0.1 volt - 10 volts or more, the spacing between the adjacent holes can range from 100 nm - 1000 nm, and in some cases greater than 1000 nm.

[0085] The examples shown is a NIN or NPN phototransistor and in some cases can be a PIP or PNP phototransistor. In addition, the phototransistor can also be implemented with Ge and I or GeSi crystalline material in region 230 as in FIG. 2A. As shown the holes are conformal doped N type in an I or low dope Si, and the P region 234 is beneath the holes. The microholes 140 can be cylindrical, inverted pyramids, conical, trapezoidal to name a few, and can be arranged in a periodic and I or aperiodic fashion, and in some cases random, and in some cases the holes can be different size and shapes. An NIP doping configuration is shown and in some cases NP, and in some cases PIPN, PIPIN, PNP, NPN, NIN, PIP for avalanche photodetector and I or phototransistors and where the P and N regions can be interchanged.

[0086] In some cases, the photodetector I photosensor can be a Ge or GeSi alloys on Si and can extend the working wavelength to 2000 nm, and in some cases 2200 nm. As compared to Si photodetector / photosensor the longest wavelength is 1100 nm.

[0087] Applications can include LiDAR for automotive applications, image sensors, and optical interconnect for data centers. Data rate can range from 56Gb/s - 112 Gb/s or more per photodetector I photosensor or optical interconnects, and the timing jitter or the electrical impulse response rise time to an optical pulse can be 15 picoseconds or less and in some cases 10 picoseconds or less and in some cases sub picoseconds. For Si the wavelength range can range from 400 - 1100 nm and for Ge or GeSi alloys the wavelength range can be from 400 - 2200 nm.

[0088] FIGs. 2C to 2F are simple partial schematic top views of various arrangements of microholes in a high speed photodetector, according to some embodiments. Shown are arrangements of contoured doped holes for the structures shown in FIGs. 2A and 2B for a high speed photodetector. The lateral dimension of the photodetector can range from 2 - 30 microns, and in some cases the diameters can range from 5 - 25 microns, and in some cases less than 5 microns, and in some cases greater than 25 microns. The material can be crystalline Si on silicon on insulator (SOI) wafer, and in some cases can be Ge on Si on SOI wafer, and the thickness of the Si for the Si photodetector can range from 100 nm - 1000 nm, and in some cases from 300 nm - 3000 nm. For Ge on Si or GeSi or GeSi alloy I Ge on Si photodetector the Si can have a thickness ranging from 5 nm - 200 nm, and in some cases greater than 200 nm, and the Ge thickness can have a thickness ranging from 100 nm - 1000 nm, and in some cases greater than 1000 nm.

[0089] FIG. 2C shows microholes 140 with alternating P (134) and N (136) contoured doping, and the semiconductor 230 between the microholes can be I or low dope P or N dopant. In this case the microholes 140 are circular and can be cylindrical and arranged in a periodic fashion, however in some cases the microholes can be non-circular, and can be a combination of geometric or nongeometric shapes. Not shown are ohmic contacts and connecting electrodes nor surface passivation.

[0090] FIG. 2D is similar to FIG. 2C with the exception that a connecting doped region between similarly doped holes connects them together. As shown in this schematic the contoured doped P holes are connected by a P region 201 between the P holes.

[0091] FIG. 2E is similar to FIG. 2C with the exception that the microholes 140 are rectangular and can be an inverted pyramid in some cases, and in some cases can be a dry etched rectangular hole.

[0092] FIG. 2F is similar to FIG. 2D showing a doped connected region connecting similarly doped holes. The doped region connecting the similarly doped holes can be doped to the same depth as the microhole, and in some cases can be to a fraction of the depth of the microhole for example ! - % the depth of the microhole.

[0093] FIGs. 2D-2F show microholes arranged in a periodic manner, however in some cases the microholes can be arranged in an aperiodic manner, and the microholes can be irregularly shaped, and in some cases the microholes can have different lateral dimensions, and in some cases the microholes can be comprised of a variety of lateral dimensions, shapes geometrical and non-geometrical, regular and I or irregular.

[0094] FIGs. 2G and 2H show simple partial schematic cross sections of high speed photodetector or photodetector arrays, according to some embodiments. The high speed photodetector or photodetector arrays are stacked to a CMOS ASICs using stacking technology as shown in FIGs. 1A-1C and 2A-2B. In some cases it may be desirable to remove the dielectric stacking material over the high speed CMOS ASICs where the stacking material can interfere with the performance of the high speed integrated circuits.

[0095] FIG. 2G shows a region where the stacking material is selectively removed over certain parts of the high speed CMOS integrated circuit.

[0096] FIG. 2H shows the partial or entire removal of both stacking material and the unutilized photodetector wafer material over parts of the high speed CMOS integrated circuits to avoid degradation of the performance of the high speed CMOS integrated circuits - which can comprise a transimpedance amplifier, clock data recovery circuits, normalization circuits, amplifier circuits to name a few. [0097] FIG. 3A-3H are simple partial schematic of a top views and cross sectional views of pixels examples used for Lumerical simulation of complete CMOS image sensors with Bayer RGB pattern (Red , Green, Blue), according to some embodiments. The material is crystalline Si on Si dioxide or oxide or nitride or dielectric or any combinations there of for bonding using stacked technology as in reference Haruta ETA al.

[0098] FIG. 3A shows a simple partial schematic top view of a square pixel with a lateral dimension of 1.12 microns and with a cylindrical microhole of 900 nm diameter etched to a depth of 2 microns. The cylindrical hole and the surface of the Si pixel are filled and covered with Si dioxide or a dielectric. The purpose of the microhole is to enhance the optical absorption and external quantum efficiency (EQE) is directly proportional to the optical absorption. The enhancement of optical absorption with microhole or holes can have a higher EQE than a comparable pixel without microhole or holes at certain wavelengths in the range from 400 nm - 1000 nm.

[0099] FIG. 3B shows a simple partial schematic of the cross section of FIG. 3A which includes an isolation trench 250 nm wide and 2900 nm deep filled with Si oxide or dielectrics and where the Si thickness for the pixel is 3000 nm and where the cylindrical microhole is etched to a depth of 2000 nm. The oxide or dielectric layer beneath the Si is approximately 1000 nm.

[00100] FIG. 3C shows a simple partial schematic top view of an inverted pyramid array 2 x 2 where the lateral dimension of each pyramid is 400 nm. The size of the square Si pixel is 1.12 microns x 1.12 microns. The isolation trench is 250 nm wide and the inverted pyramids are filled with Si oxide and I or dielectrics. The inverted pyramids are formed on (100) crystalline Si using anisotropic etch such as KOH (potassium hydroxide) and I or similar etch. Such inverted pyramids are discussed in Yokogawa et al, IR sensitivity enhancement of CMOS Image Sensor with diffractive light trapping pixels, Nature Scientific Reports, June 19, 2017, which is incorporated herein by reference. [00101] FIG. 3D shows a simple partial cross section schematic of FIG. 3C where the Si thickness is 3000 nm on approximately 1000 nm of Si oxide I nitride I dielectric. The isolation trench is etched to a depth of 2900 nm.

[00102] FIG. 3E shows a simple partial schematic top view of a crystalline Si square pixel with lateral dimension of 1.12 surrounded with an isolation trench of 250 nm where the microstructure hole is a single square inverted pyramid with a base dimension of 900 nm and where the pyramid and the Si pixel are filled or covered with Si oxide. As in FIG. 3C, the inverted pyramid is formed by wet anisotropic etch such as KOH or TMAH for example.

[00103] FIG. 3F shows a simple partial cross section schematic of FIG. 3E where the Si has a thickness of 3 microns and the isolation trench etched to a depth of 2900 nm filled with Si oxide where the bottom dielectric layer is Si oxide or nitride or other dielectrics that are used for stacking technology.

[00104] FIG. 3G is a simple partial top view of a funnel hole pixel with an outer hole of 900 nm diameter and an inner hole of 800 nm diameter.

[00105] FIG. 3H is a simple partial cross sectional view of a funnel pixel where the top hole is 900 nm and the inner hole is 800 nm, and where the funnel is 60 degree angle from the plane of the surface and the height of the funnel is 2000 nm. The funnel can be filled with a dielectric such as Si dioxide.

[00106] The funnel hole can be formed using dry etch compatible with CMOS processing. As in the case of the holes shown in FIGs. 3A-3F, contoured doping of N or P dopants can be applied and in some cases hyper doping or degenerate doping levels can be applied to the side walls of the microhole or holes. In some cases, passivation such as Si dioxide can be applied in conjunction with side wall doping of the holes, and in some cases not in conjunction with side wall doping of the holes to reduce leakage currents or dark current.

[00107] FIGs. 4A-4E are simple partial cross section schematics of various arrangements of photosensors, according to some embodiments. The sensor wafer is shown without any connecting electrodes to the anode or cathode of the imaging pixels or photosensors. Also not shown are the connecting electrodes nor the bonding electrodes to the CMOS logic processor wafer. The CIS wafer (CMOS image sensor) is fabricated separately from the CMOS logic processor wafer as in Haruta et al. The CIS wafer and the CMOS logic processor wafer are then bonded together to form a complete CMOS image sensor with CMOS logic processor electronics.

[00108] FIG. 4A shows a simple partial cross section schematic of a CIS wafer used for Lumerical simulation where each pixel or photosensor 130 has a single cylindrical microhole 140 as in FIGs. 3A and 3B. RGB filters 170 in the Bayer pattern are included together with microlens 172. For further details including the parameters for the microlens, see, Han ETA al, Deep Trench Isolation and Inverted Pyramid Array Structures Used to Enhance Optical Efficiency of Photodiode in CMOS Image Sensor via Simulations, Sensors, May 28, 2020, which is incorporated by reference herein. The pixels are isolated with an isolation trench 250 nm in width and 2900 nm in depth. Not included in the Lumerical simulation is the NIR (near infrared) filter as shown but where a modified Bayer pattern can be implemented.

[00109] FIG. 4B similar to FIG. 4A shows a simple cross section schematic of a CMOS image sensor used for Lumerical simulation with Bayer RGB pattern, where the pixels are as shown in FIGs. 3C and 3D. The NIR filter was not included in the Lumerical simulation; however a modified Bayer RGB pattern including an NIR filter can be implemented. The microholes in this example is a 2 x 2 inverted pyramid array with a base diameter of 400 nm.

[00110] FIG. 4C shows a simple partial cross section schematic of a CIS wafer with RGB filters and in some cases with an NIR filter with a single inverted pyramid with a base diameter of 900 nm and whose top and cross sectional view are discussed in FIG. 3E and 3F. In some cases the NIR pixel can be optional, in most current CIS NIR pixel is not included. The addition of the NIR pixel with appropriate NIR filter allow the sensing of NIR light in bright visible environments.

[00111] FIG. 4D is similar to FIG. 4C where only Red, Green, Blue pixels are shown and where in some cases a microhole associated with the Blue filter pixel may not be necessary as the optical absorption coefficient in the blue wavelength is greater than 10,0001 cm which can provide high optical efficiency without the addition of absorption enhancing holes. In some cases the green filtered pixel can also do without an absorption enhancing microhole. However with the microhole in the Blue and Green pixels can improve the image quality at NIR wavelengths as these pixels can contribute to the overall image at the NIR wavelength since the RGB filters are mostly transparent beyond 800 nm wavelength.

[00112] FIG. 4E is similar to FIG. 4D except instead of having a microlens over each pixel as shown in FIG. 4D a single microlens covering the Bayer pattern of 4 pixels, 2 Green, 1 Blue, 1 Red can be implemented.

[00113] FIGs. 5A- 5F are plots of Lumerical simulations of structures shown in FIGs. 4A-4C. The Bayer RGB pattern filters and microlens, as discussed Han ETA al, are shown for pixels with 1.12 micron x 1 .12 micron dimension, 3 micron Si thickness, 250 nm width isolation trench between the pixels and where the trenches are etched to a depth of 2900 nm with a bottom oxide layer of approximately 1000 nm. The trenches and microholes are all filled with Si dioxide and where the surface of the pixel is also covered with 250 nm of Si dioxide (not shown).

[00114] FIG. 5A shows the Red, Green, Blue filter response used in the Lumerical simulation for CMOS image sensors. These filter responses are comparable to the filters available commercially such as the Hoya filters.

[00115] FIG. 5B shows Lumerical simulation of absorption vs wavelength from 300 nm - 1000 nm of a flat pixel (no microstructure holes) of dimensions shown in FIG. 3 using the filter response of FIG. 5a.

[00116] The vertical axis is absorption or equivalently optical efficiency (OE) where absorption can be defined as 1 - reflection - transmission and where the optical efficiency can be defined as (optical power in - optical power out) I optical power in.

[00117] FIG. 5C shows the absorption vs wavelength and where absorption is directly proportional to EQE for 1.12 micron square pixel with a single 900 nm diameter cylindrical microhole as in FIG. 3A,B. The solid curve is the blue pixel, the dotted curve is the green pixel, and the dashed curve is the red pixel absorption vs wavelength where white light impinges on the microlens. As can be seen absorption is greater than 40%, and as much as 60% for the RGB wavelengths. In addition at NIR wavelengths for example 850 nm over 40% absorption can be observed and at 940 nm similarly over 40% absorption can be observed. EQE is equal to absorption if all the photogenerated carriers are collected. The Si thickness of each pixel is 3 microns. Filter response shown in FIG. 5a are used in this simulation.

[00118] FIG. 5D is a Lumerical simulation of optical absorption vs wavelength for structures shown in FIG. 4b where the microholes is 2x2 inverted pyramid array with a base diameter of 400 nm. Filter response shown in FIG. 5A are used in this simulation.

[00119] FIG. 5E is a Lumerical simulation of a structure shown in FIG. 4c where a single inverted pyramid with a base of 900 nm and where the pixel has a dimension of 1 .12 microns x 1 .12 microns with a Si thickness of 3 microns. The RGB absorption is greater than 60% and in some cases 80%, and the NIR wavelength for example 850 nm can range from 50% - 80%, and at 940 nm approximately 50% - 60%. From these Lumerical simulations of examples of microholes shown in FIG. 3 and FIG. 4 shows great improvements of pixels with microstructure hole or holes over comparable pixels without microstructure hole or holes in the EQE of RGB and NIR wavelengths in the range of 400 - 1000 nm.

[00120] These examples may not be optimized in terms of EQE vs wavelength and further optimization may be possible to enhance the absorption I EQE vs wavelength of the RGB Bayer pattern filers with pixels of approximately 1 micron in lateral dimension. For example conical or funnel shaped microholes may show higher EQE vs wavelength at the RGB and NIR wavelengths for Si CMOS image sensors. Filter response shown in FIG. 5A are used in this simulation.

[00121] FIG. 5F shows the Lumerical simulation of a pixel with a single funnel hole as shown in FIG. 3G,H of its absorption vs wavelength from 300 nm - 1000 nm using the color filters response of FIG. 5A. The enhancement of the absorption at the Blue and Green wavelengths can be significant as well as at the NIR wavelengths of 850 nm, 905 nm, and 940 nm with absorption which is directly proportional to EQE of 40% or greater, and in some cases 60% or greater.

[00122] Specific microhole or microholes dimensions were used in the Lumerical simulation which may or may not be optimized for absorption vs wavelength. Other shape holes or cross sections are possible that can further optimize absorption vs wavelength for the CIS structure. Lateral dimension of the microhole can range from 300 nm - 1200 nm, and in some cases 400 nm - 1000 nm. The microhole can be circular, oval, square, rectangular, polygonal, star, cross, amoebic, and / or any combination of geometric shapes. The cross section of the microhole can have a single and I or multiple slopes of its sidewalls and in some cases can have positive and I or negative slopes. The depth of the microhole can range from 200 nm - 2000 nm, and in some cases more than 2000 nm, and in some cases from 400 nm - 2000 nm, and in some cases the microhole can be etched to the oxide layer. In some cases the depth of the microhole can range from 1/10^th to % the thickness of Si, and in some cases from ! to % the thickness of Si. The microhole such as inverted pyramids formed on crystalline Si by anisotropic wet etch, and in some cases conical or funnel shaped holes or trapezoidal can be formed by dry etch of crystalline Si. The thickness of the Si in the CIS structure can range from 1000 nm - 5000 nm.

[00123] Ponizovskaya Devine et al, Single Microhole per Pixel in CMOS Image Sensors With Enhanced Optical Sensitivity in Near-Infrared, IEEE SENSORS JOURNAL, VOL. 21 , NO. 9, MAY 1 , 2021 , incorporated by reference herein, and referred to herein as “Devine et al.” at table 1 shows a single funnel shaped hole gave the highest NIR (8501940 nm) sensitivities.

[00124] Optical efficiency, optical sensitivity, optical absorption, absorption are equivalent and corresponds to the generation of electron hole pairs in the semiconductor and is directly proportional to external quantum efficiency.

[00125] Devine et al. shows cross talk between the RGB pixels and the optical efficiency which is equivalent to absorption and which in addition is directly proportional to external quantum efficiency at 850 and 940 nm for various pixel structures such as flat pixel, inverted pyramid array pixel, single inverted pyramid pixel, single cylindrical hole pixel and a single funnel hole pixel. All the pixels with a single microhole per pixel showed higher optical efficiency than the flat pixel or the inverted pyramid array pixel.

[00126] FIGs. 6A-6C show a simple partial schematic cross sections of a CMOS image sensor wafer bonded to CMOS logic ASICs wafer, according to some embodiments. Color filters in Bayer patterns are shown and in some cases a modified Bayer pattern with NIR filters can be implemented. The square Si pixels can have a dimension ranging from 0.5 - 2.2 microns and where a single inverted pyramid per pixel can significantly enhance the EQE of the CMOS image sensors at RGB and NIR wavelengths over a comparable CMOS image sensor without microstructure hole or holes or a flat CIS pixel. In these examples, the microstructure hole is a single inverted pyramid formed by wet etching and in some cases the micro structure hole can be formed by dry etching and can have a conical or funnel cross section where the slope of the conical and the depth of the conical can be optimized further to increase the EQE at RGB and I or NIR wavelengths. In some cases, a modified Bayer pattern may be desirable where pixels with NIR filters can be included such that the NIR filter can filter out ambient light for example visible light such that NIR signal can be observed in ambient visible light. [00127] FIG. 6A shows a partial simple cross section of a stacked CMOS image sensor wafer with CMOS logic ASICs processor wafer with connecting electrodes and bonding electrodes with a single inverted pyramid per pixel. The filter can be a Bayer RGB filter pattern or a modified Bayer RGB filter pattern with the addition of a NIR filter where the NIR can have a wavelength range of 850 nm and I or 940 nm, and in some cases greater than 800 nm for example. The NIR filter can be Bandpass and can be selective to certain NIR wavelength ranges and in some cases can filter out visible wavelengths.

[00128] Doping regions for example N and P doping regions are not shown and a variety of doping schemes of PIN, PN, PIPN, NIN, PIP, PNP, NPN to name a few can be implemented to allow the pixels to operate in a photodiode or photoconductor or phototransistor mode and can be used in an avalanche photodiode or single photon avalanche photodiode (SPAD) or phototransistor or photodiode mode. Elisabeth et al, Sony IMX400 Tri-layer stacked CMOS Image Sensor (CIS) with Integrated DRAM and DSP, https://www.systemplus.fr/wp- content/uploads/2017/07/SP17343_Sony_IMX400_Tri- layer_Stacked_CIS_Flyer_System_Plus_Consulti.pdf is incorporated by reference herein. Elisabeth et al discusses a CMOS image sensor wafer bonded to a memory wafer (DRAM), dynamic random access memory, and a digital signal processing wafer (DSP). In stacking technology two or more wafers comprising a pixel wafer and an additional wafer that can comprise of a memory wafer, CMOS logic wafer, DSP wafer, and any other CMOS ASICs wafers to enable additional functionalities for this single CIS chip that can include artificial intelligence for example. [00129] In some cases, multiple CMOS ASICs wafers can be stacked to include functionalities such as memory, machine learning, artificial intelligence, edge computing to name a few.

[00130] FIG. 6B is similar to FIG. 6A with the exception that P and N region dopants are shown for example the P region 134 can be deeply implanted such as with Boron ions, and the N region 136 can be diffused and I or implanted with Phosphorous ions for example (other P and N ions in the periodic table can be used), and in some cases the N region can be hyperdoped or doped to degeneracy to form NIP diode with N is a cathode and P is an anode (connecting electrodes to the cathode are not shown for simplicity). However, in some cases the N and / or P dopant can diffuse to form a PN junction. A reverse bias is applied between the cathode and anode with bias voltages ranging from 0.1 - 3.3 volts, and in some cases 0.8 - 3.3 volts for photodiode operation. In the case of APD I SPAD operation bias voltages can range from 3 - 15 volts, and in some cases 5 - 10 volts; other biasing schemes for phototransistors or photoconductors can include a reverse bias and I or forward bias and in some cases a combination of forward and reverse biases. For time-of-flight operation the rise time can range from a few picoseconds to 10s of picoseconds for example from 5 picoseconds to 25 picoseconds and in some cases from 3 picoseconds to 100 picoseconds, and in some cases greater than 100 picoseconds. In some cases subpicoseconds to a few pico seconds.

[00131] Isolation trenches between the pixels are used to reduce cross talk and improve optical confinement within the pixels. The isolation trenches are used for optical and I or electrical isolation of the pixels and passivation layer or layers such as Si dioxide and I or other dielectrics can be used to reduce leakage and I or dark current, and in some cases doping of the sidewalls of the pixels can be used to further reduce leakage or dark current.

[00132] As shown as an example the structure is a PIN photodiode, in some cases it can be doped such that its NIN or NPN phototransistor, and in some cases it can be doped as a PIP or PNP phototransistor, and in some cases it can be a PN junction, PIPN avalanche photodiode structure to name a few.

[00133] FIG. 6C is similar to FIG. 6B where the RGB pixels have a P region, I or low dope region, and an N region, and where the microhole, in this case an inverted pyramid, is contoured doped, or in other words, the side walls of the microhole is doped with a P or N type dopant. In this figure the NIR pixel is doped with multiple P and N regions (P region 634 and N region 636) to from an avalanche photodiode or single photon avalanche photodiode with doping PIPN configuration as shown, and in some cases can have a PN doping, PIN, PIPIN doping configuration, and in some cases the P and N regions can be interchanged. The avalanche gain allows the NIR pixel to operate at a higher sensitivity, and since the Si layer is thin, 3 microns or less, it can have high speed for example the electrical rise time in response to light pule can be 15 picoseconds or less, and in some cases less than 10 picosenconds to impinging NIR wavelengths of 700 - 1100 nm. With the addition of Ge or Ge alloy such as GeSi the wavelength can be extended to 2000 nm.

[00134] FIG. 7 is a plot showing a Lumerical simulation of absorption vs wavelength from 300 - 1000 nm of pixels with a single funnel hole as in FIGs. 3G and 3H, according to some embodiments. For the simulation, the width of the isolation trench is 250 nm, the trench depth is varied from 2.5, 2, 1.5, 1 microns. The trenches are filled with Si dioxide. The solid curves are for blue pixels, the dotted curves are for green pixels, and the dashed curves are for red pixels. The thinnest curves are for a trench depth of 2.5 microns, the dotted medium curves curve is for trench depth of 2 microns, the dot-dashed thickest curves are for a trench depth of 1 .5 microns, and the dashed curve is for a trench depth of 1 micron. Curve 710 is for a blue pixel, trench depth 1.5 microns. Curve 712 is for a blue pixel, trench depth 2 microns. Curve 720 is for a green pixel, trench depth 1 .5 microns. Curve 722 is for a green pixel, trench depth 2 microns. Curve 724 is for a green pixel, trench depth 2.5 microns. Curve 730 is for a red pixel, trench depth 1.5 microns. Curve 732 is for a red pixel, trench depth 2 microns. Curve 734 is for a red pixel, trench depth 2.5 microns. As the trench depth decreases there is a slow degradation of absorption vs wavelength, and an increase in cross talk. For each group of curves, the thick curve represents 1 .5 microns, the medium curve 2 microns, and the thin curve, 2.5 microns.

[00135] The highest response or absorption, optical efficiency is given by the trench of a depth 2.5 microns and the weakest absorption, OE is given by a trench depth of 1.5 microns. [00136] FIG. 8 is a plot showing a further Lumerical simulation of absorption vs wavelength 300 - 1000 nm of pixels with a single funnel hole as shown in FIGs. 3G and 3H, according to some embodiments. For the simulation, an isolation trench depth is 2.5 microns and the trench width is varied from 250 nm, 200 nm, 150 nm. The solid curves are for blue pixels; the dashed curve is for green pixels; and the dotted curve is for red pixels. Trench width of 250 - 150 nm gave low cross talk and minor degradation in the absorption vs wavelength. For each group of curves, the thick curve represents 250 nm, the medium curve 200 nm, and the thin curve, 150 nm. Curve 810 is for a blue pixel, trench width 250 nm. Curve 812 is for a blue pixel, trench width 200 nm. Curve 814 is for a blue pixel, trench width 150 nm. Curve 820 is for a green pixel, trench width 250 nm. Curve 824 is for a green pixel, trench width 150 nm. Curve 830 is for a red pixel, trench width 250 nm. Curve 832 is for a red pixel, trench width 200 nm. Curve 824 is for a red pixel, trench width 150 nm.

[00137] Trench depth and width can be optimized for certain applications in CMOS image sensors, Time-of-Flight, LiDAR to name a few.

[00138] The strongest absorption, OE is given by a trench width of 250 nm, and the weakest absorption, OE is given by a trench width of 100 nm. As can be seen from this family of plots trench width of 250, 200, 150 gives similar absorption, OE with approximately 5% variation. Devine et al. shows Lumerical simulations of single microhole per pixel where the microhole can be cylindrical, inverted pyramid or funnel with higher NIR sensitivities than 2 x 2 inverted pyramid array.

[00139] FIGs. 9A-9C show modified Bayer patterns, according to some embodiments. FIG. 9A shows a modified Bayer pattern which includes dedicated IR or NIR pixel, and in some cases there can be multiple IR or NIR pixels within the Bayer pattern. In this example the Green pixel is replaced by an IR or NIR pixel such that within a 3 x 3 Bayer pattern array the I R or NIR pixel are in a diagonal for example. Other configurations are possible and in some cases 1 or more IR pixels can be included in a 3 x 3 Bayer pattern array.

[00140] The Red (R), Green (G) and Blue (B) pixels have their respective RGB filters that can in some cases include NIR or IR blocking filters and the IR or NIR pixels include a bandpass filter that allows only IR and / or NIR wavelengths to impinge on the IR or NIR pixel. In the case of Si the IR / NIR wavelengths can be defined in the range from 700 - 1100 nm.

[00141] The advantage of including IR I NIR pixels that block visible light allows the CMOS image sensor to detect the IR / NIR wavelengths in bright visible light. [00142] FIG. 9B is similar to FIG. 9A with the exception that the IR pixel can be periodic, aperiodic and I or random within an array of Bayer patterns. The aperiodic and random arrangement of the IR pixel can avoid the effect of streaking or appearance of lines in the image. In some cases, the IR pixel can replace a green pixel and / or a red pixel and / or a blue pixel. The density of the IR pixel within an array of Bayer patterns can range from 1 % - 50% and in some cases greater than 50% and in some cases less than 50%.

[00143] FIG. 9C shows a simple schematic of a modified Bayer Pattern similar to FIGs. 9A and 9B with the addition of Time-of-Flight pixels that can be combined with or not combined with the IR pixel. The density of the Time-of-Flight IR or NIR Pixel can range from less than 1 % to 50% or more. The RGB pixels and IR I NIR pixels can have a density ranging from 10001 mm or more to 100 / mm or less and where the ToF pixels can range from 1 - 100 / mm or more. Note that according to some embodiments, ToF pixels might be wired differently then other pixels. For example, the ToF pixels may be wired for higher voltage to improve the rise time in order to operate at higher frequencies.

[00144] FIGs. 10A-10I are simple partial cross-sectional views of microstructure hole(s), according to some embodiments. The views are for at least a single slice and slices at different directions for example orthogonal can have different cross sections. The microstructure hole can be a single hole for small pixels or Photosensors for example with lateral dimensions less than 2 microns. In some cases, for pixels or Photosensors with lateral dimensions ranging from 0.6 microns

- 100 microns multiple microstructure holes can be formed to enhance optical absorption. In some cases, all the micro structure holes can have similar cross sections and in some cases can have a mixture of different cross sections in the same sensor array of CIS layer. The lateral dimension at least in 1 direction of the microstructure hole can range from 200 nm - 2000 nm and in some cases from 500 nm - 2500 nm. The depth of the microstructure hole(s) can range from 500 nm

- 3000 nm and in some cases the microstructure hole can be 1/3 the thickness of the crystalline semiconductor, and in some cases 1 the thickness of the crystalline semiconductor, and in some cases 2/3 the thickness of the crystalline semiconductor, and in some cases % the thickness of the crystalline semiconductor, and in some cases can extend through the crystalline semiconductor. The crystalline semiconductor can have a thickness ranging from 0.2 microns - 5 microns, and in some cases 0.5 - 3 microns, and in some cases greater than 3 microns.

[00145] FIG. 10A shows an inverted pyramid microstructure hole. FIG. 10B shows a conical microstructure hole. FIG. 10C shows a trapezoidal microstructure hole. FIG. 10D shows a rectangular or cylindrical micro structure hole. FIG. 10E shows a double funnel microstructure hole, and in some cases can be more than 2 funnels. FIG. 10F shows a funnel microstructure hole. FIG. 10G shows a diamond cross section microstructure hole. FIG. 10H shows a spherical cross section microstructure hole. FIG. 101 shows an oval or tear drop cross section microstructure hole.

[00146] The thickness of the crystalline Si layer can range from 0.3 - 5 microns, and in some cases 0.5 - 3 microns. The pixel dimension in the case of a square pixel, the lateral side dimension can range from 0.3 - 3 microns, and in some cases 0.3 - 10 microns, and in some cases 0.3 - 2 microns. In some cases the pixel need not be a square, and can be any arbitrary shape in which case at least 1 lateral dimension can range from 0.1 - 10 microns.

[00147] FIGs. 11A-111 are simple schematic top view examples of micro structure holes, according to some embodiments. In some cases, for small pixels or Photosensors with lateral dimensions less than 2 microns a single microstructure hole can be used to enhance optical absorption efficiency in the wavelength range of 300 - 1100 nm for crystalline Si with a thickness range of 0.2 - 5 microns, and in some cases greater than 5 microns. Microstructure hole or holes can also be used in conjunction with other crystalline semiconductor for example Ge alloys on Si, and in some cases lll-V alloys formed on Si. For pixels or Photosensors with lateral dimensions ranging from 0.5 microns - 100 microns or more multiple micro structure holes can be used to enhance optical absorption in crystalline semiconductor, and in some cases can be similar holes, and in some cases can be a combination of different shaped holes, and can be arranged in a periodic or aperiodic or random manner. At least 1 lateral dimension of the microstructure hole can range from 200 nm - 2000 nm, and in some cases from 400 nm - 2000 nm, and in some cases greater than 2000 nm.

[00148] FIG. 11 A shows a circular microstructure hole. FIG. 11 B shows an elliptical or oval microstructure hole. FIG. 11C shows an inverted pyramid microstructure hole. FIG. 11 D shows a rectangular microstructure hole oriented in a certain direction. FIG. 11 E shows a rectangular microstructure hole oriented in a different direction. FIG. 11 F shows a hexagonal microstructure hole.

[00149] FIG. 11 G shows a diamond microstructure hole. FIG. 11 H shows an irregular or amoebic microstructure hole. FIG. 111 shows intersecting microstructure holes, which in this case is two circles.

[00150] These are just a few examples microstructure holes and other geometric forms and combination of geometric forms can be included for the microstructure holes.

[00151] FIGs. 12A-12C are simple partial schematic cross section views of microstructure hole formed by a series or group of smaller micro or nano holes, according to some embodiments. The series smaller micro or nano holes are arranged such that the effective cross section is that of a single larger microstructure hole. This arrangement can also be referred to as composite nanoholes. The smaller micro I nano holes formed in this composite structure can have any geometric shapes or cross sections and can have at least 1 lateral dimension ranging from 50 nm - 500 nm, and in some cases 100 nm - 400 nm. The micro I nano composite holes can have similar or different lateral dimensions, can have similar or different geometric shapes, and in addition can have similar or different depth in the same sensor array or CIS layer. FIG. 12A shows a rectangular or cylindrical cross section micro structure hole formed with a series of smaller microstructure holes. FIG. 12B shows an inverted pyramid or conical shape cross section microstructure hole formed with a series of smaller micro I nano holes. FIG. 12C shows a funnel microstructure hole formed with a series of micro I nano holes.

[00152] In some cases, the pixel I Photosensor can be composed of amorphous semiconductor and I or poly crystalline semiconductor and I or crystalline semiconductor into which microstructure hole or holes or composite micro / nano holes can be formed. In some cases a thin layer of amorphous and I or poly crystalline semiconductor can be formed on crystalline semiconductor and the micro structure hole I holes and I or micro I nano holes can be formed in any of the semiconductor layers and I or in all the semiconductor layers.

[00153] FIG. 13A shows a simple, partial schematic of a top view of a single pixel with a composite hexagonal shaped hole that is comprised of multiple nanoholes, according to some embodiments. Both the isolation trenches 1380 and the nanoholes 1342 and isolation trenches are filled with Si dioxide. The pixel is 1.12 microns x 1 .12 microns and the hexagonal microhole is 800 nm, and the nanoholes are 100 nm in diameter spaced by 20 nm.

[00154] The shape of the composite microhole which is comprised of multiple nanoholes can be circular, oval, rectangular, square, polygonal, hexagonal, irregular, amoebic and or any combinations of shapes. The lateral dimension at least in one direction of the composite microhole can range from 100 nm to 3000 nm and in some cases greater than 3000 nm. In some cases for a square shaped composite microhole the lateral dimension can be the same as the lateral dimension of a pixel or almost the same. In some cases the lateral dimension of the composite microhole can range from 60%-95% that of the lateral dimension of a pixel.

[00155] The nanoholes within the composite microhole can have depths ranging from 100 nm to 3000 nm and in some cases 1/4 to 3/4 the thickness of the Si and in some cases through the Si or semiconductor which can include Ge and or GeSi alloy on Si. The cross sectional shape of the nanoholes can be cylindrical, trapezoidal, conical, funnel, triangular, square, polygonal, inverted pyramidal, irregular, amoebic to name a few. In some cases a combination of differently shaped nanoholes can be within a composite microhole. The nanoholes can have a lateral dimension ranging from 20 nm to 300 nm and in some cases greater than 300 nm and can be arranged periodically, and I or aperiodically and I or randomly. The nanoholes can have a spacing ranging from 10 nm to 100 nm and in some cases greater than 100 nm.

[00156] In some cases, for a large pixel or photodetector, multiple composite microholes can be etched or formed on the pixel or photodetector in a periodic and or aperiodic arrangement. The spacing between the composite microhole can range from 100 nm to 500 nm and in some cases less than 100 nm.

[00157] For Si pixels or photodetectors, photons with wavelength range from 300-1070 nm can be detected and with Ge on Si the wavelength range can be extended to 2150 nm.

[00158] FIG. 13B shows a simple partial cross section schematic of FIG. 13A, according to some embodiments. The cylindrical nanoholes 1342 are etched to a depth of 2 microns and the Si thickness is 3 microns on top of a Si dioxide layer that is 1 micron thick and the trenches are etched to a depth of 2.5 microns with a trench width of 250 nm.

[00159] In some cases, the nanoholes can have a lateral dimensions ranging from 50 - 300 nm, and in some cases more than 300 nm, and in some cases the hole shape can be non circular or can be polygonal or can be irregular and I or combination of various shapes. In some cases, the holes can be periodic, aperiodic, and I or random, and I or combination thereof. And in some cases the depth of the holes can be uniform, and I or non uniform and I or combination thereof.

[00160] FIG. 13C shows a Lumerical simulation of a complete CMOS image sensor structure with RGB filters, according to some embodiments. The microlens range from 300 nm - 1000 nm wavelength and the NIR optical efficiency I absorption is approximately 60% at 850 nm, 905 nm, and 940 nm.

[00161] FIG. 13D shows a Lumerical simulation of absorption of a complete CMOS image sensor with microlens and RGB filters as discussed in Devine et al., according to some embodiments. Absorption is proportional to optical efficiency vs wavelength from 300 - 1000 nm of a pixel with hexagonal lattice nanoholes where the nanoholes diameters are 100nm spaced by 20nm between adjacent nanoholes etched to a depth of 2 microns.

[00162] FIG. 13E shows a simple partial schematic top view of a square pixel 1.12 microns per side with a trench of 250 width and a depth of 2.5 microns filled with Si dioxide, according to some embodiments. The cylindrical nanoholes with a 100nm diameter in a hexagonal lattice spaced 20 nm etched to a depth of 2 microns and filled with Si dioxide were simulated as shown in FIG. 13D using Lumerical simulation for absorption vs wavelength. [00163] FIG. 14A shows a Lumerical simulation of absorption of a complete CMOS image sensor with microlens and RGB filter as discussed in Devine et al. Absorption which is proportional to optical efficiciency vs wavelength from 300nm - 1000 nm of a pixel shown in FIGs. 14B and 14C. As can be seen at NIR wavelengths of 850 nm and 940 nm the absorption or optical efficiency is approximately 60%.

[00164] FIG. 14B shows a simple partial schematic top view of a square pixel 1.1 microns per side with a large 400 nm diameter cylindrical hole in the center surrounded by 6 equally spaced cylindrical holes with 200 nm diameter. A deep trench isolation surrounds the pixel with a width of 250nm and a depth of 2500nm filled with Si dioxide as are the nanoholes.

[00165] FIG. 14C shows a simple partial cross section schematic of FIG. 14B where the 400 nm cylindrical hole is etched to a depth of 2 microns and the 200 nm cylindrical holes are etched to a depth of 1 micron, and the spacing between the 200 nm hole and 400 nm hole is 20 nm. The thickness of the Si pixel is 3 microns. [00166] These simulations and schematics of the pixel are examples of a composite hole consisting of multiple nanoholes as shown in FIGs. 13A, 13B, 14B and 14C where the absorption or optical efficiency at near infrared (NIR) wavelengths can be greater than a comparable flat pixel. Other examples such as nanoholes that are periodic or aperiodic with a mixture of small and large nanoholes can also be applicable for a composite hole that can in some cases span the entire surface of the pixel as shown in FIG. 13E for example.

[00167] Nanoholes can have lateral dimensions ranging from 50 - 500 nm and spacing between nanoholes can range from 10 - 200 nm, and the etch depth of the nanoholes can range from 500 - 3000 nm, and in some cases less than 500 nm, and the nanoholes can be circular, oval, rectangular, polygonal, square, hexagonal, ameobic, and I or any combination of hole shapes that can include linear and curved lines and can be arranged in periodic and I or aperiodic and I or random nature and I or any combination thereof, and can occupy the entire surface of a pixel, partially occupy the surface of a pixel, and can be centered or off centered. The nanoholes and microholes can be filled entirely or partially with a dielectric such as Si dioxide, Si nitride, Hf oxide, to name a few and I or any combination of oxide, nitride, and other dielectrics. [00168] FIGs. 15A and 15B show simple partial schematic cross sections of a CMOS image sensor, according to some embodiments. In FIG. 15A, the deep trench isolation 1580 is provided optical and electrical isolation between adjacent pixels a combination of Si dioxide 1512, metal 1540 and amorphous or polycrystalline semiconductor 1510. The combination of materials is used to fill the deep trench isolation section to reduce cross talk between adjacent pixels. As shown in FIG. 15A the pixel has a single microhole 1540, in this example an inverted pyramid for pixel sizes of 2 - 0.8 microns. The pixel can be a square pixel, however other pixel sizes are also applicable and can have multiple microholes. Crosstalk between pixels can degrade resolution and image quality and therefore techniques to isolate optical crosstalk using metal in combination with an optical absorber such as amorphous Si, or polycrystalline Si, or amorphous Ge, or polycrystalline Ge, other non crystalline semiconductor such as lll-V semiconductor can also be used. The optical absorber can also be organic such as a die or nano particles of metal and I or semiconductor suspended in a medium. The sidewalls of the pixel and the microholes are passivated with a material such as Si dioxide. Metal reflectors 1540 can be deposited in the deep trench isolation to reflect light back into the pixel and for any light that transmits through the metal an absorber such as amorphous or polycrystalline Si can be used to further reduce optical crosstalk. The height of the pixel can range from 1 micron to 10 microns and in some cases greater than 10 microns, and in some cases less than 1 micron. The pixel can be etched to the oxide or dielectric layer and in some cases a layer of crystalline Si under the pixels to provide a common electrode. Doping profiles of P (anode) and N (cathode) are not shown for simplicity. PN junctions or PIN junctions or PIPN junctions can be used for photodiode or avalanche photodiode operation. In some cases PNP or NPN doping profiles can be used for operation as a phototransistor. Also not shown are connecting electrodes to the cathode and anode and to the bonding electrodes used for stacking the pixel wafer to CMOS electronic wafer for image processing.

[00169] FIG. 15B is similar to FIG. 15A with the exception that only an absorber is inserted between adjacent pixels to reduce crosstalk without metal reflectors. It also includes a passivation dielectric such as Si dioxide on the side walls of the pixels as shown. The thickness of the passivation sidewall layer can range from 1 - 50 nm and can include multiple dielectrics such as Si dioxide, Si nitride, Al oxide, Hf oxide to name a few. The absorber which can consist of amorphous semiconductor or polycrystalline semiconductor of Si, Ge, lll-V to name a few is deposited between the pixels which include the passivation and any additional transparent dielectric at the wavelength from 300 - 1100 nm.

[00170] In some cases, the absorber can intersect the surface of the bottom layer Si such that the passivation and I or any other dielectric covers only the sidewall of the pixel, and the absorber layer can extend to the bottom such that it is in contact with the surface of the bottom Si layer.

[00171] The optical isolation can also be extended to pixels containing Ge on Si for example or any Ge alloy on Si to extend the pixel wavelength to 1700 nm. [00172] With the addition of Ge on Si or any Ge alloy on Si the disclosed pixels in this application can have their wavelength extended to 1300 nm.

[00173] FIGs. 16A and 16B show simple partial schematic cross section of Ge or GeSi alloys on Si, according to some embodiments. In FIG. 16A the pixel is comprised of Ge or GeSi alloys. A conformal doping of the microhole 1640 with N dopant 1634 and a buried P dopant 1636 in the Si which can extend into the Ge I GeSi pixel are shown. The doping configuration can be a PN junction, in some cases a PIN structure where the P and N can be interchanged. In some cases, additional gain such as from an avalanche photodiode or phototransistor with doping configuration of PIPN, PIN, PNP, NPN, NIN, PIP to name a few and the gain can be implemented in the Si layer for example. In the case with an avalanche gain, the avalanche region PN or PIN can be in the Si such that the P can be in the Ge I GeSi and I region in the Ge I GeSi and a PN junction in Si. The Ge I GeSi pixel can detect wavelengths ranging from visible to 2000 nm wavelength, and in some cases to 2200 nm wavelength. Not shown in this simplified drawings are filters, lens, connecting electrodes for stacking technology, passivation and other elements required to fabricate a reliable Ge I GeSi CMOS image sensor. In the case of larger pixels multiple microholes can be used that can be arranged in a periodic or aperiodic fashion. Light impinges on the surface with the microhole or microholes. Also shown in FIG. 16A is deep trench isolation region 1680 that includes passivation regions 1610. [00174] FIG. 16B is similar to FIG. 16A and shows a simple partial schematic cross section of Ge and I or GeSi and I or GeSn and I or any Ge alloy on Si for extending the wavelength to 2200 nm. As shown a single microhole is formed in the photosensor or pixel; however for larger photosensors or pixels multiple microholes can be formed. In this example conformal doping 1634 along all exposed Ge or Ge alloys and Si surfaces are doped with either N or P type dopant including the walls of the microhole or holes 1640 as shown. The dopant can be formed conformally by ion diffusion using rapid thermal flash lamps to form highly doped shallow doped regions. The surfaces can then be passivated with a dielectric such as Si dioxide, Si nitride, Al oxide, Al nitride to name a few, and in some cases can be amorphous semiconductor such as amorphous Si or polycrystalline Si. Doping exposed surfaces can reduce leakage or dark current that can degrade the performance of the photosensor or pixel. Dopant of the opposite polarity is formed in a region that can be Si and I or both Si and Ge and I or Ge (“Ge” includes all alloys of Ge) such that a PN or PIN or P low dope P or N and N regions are formed. In some cases the doped regions can also be formed by ion implantation and / or a combination of ion implantation and rapid thermal diffusion of dopant ions. Not shown are connecting electrodes to the doped regions to form cathode and anode contacts. A reverse bias is applied between the anode and cathode contacts for each photosensor or pixels. The reverse bias voltage can range from 0.2 volts to 10 volts or more and in some cases to 15 volts. The photosensor depending on its doped regions which in some cases can have multiple doped regions to form PN or PIN or PIPN or PIPIN regions and can operate as a photodiode or avalanche photodiode or single photon avalanche photodiode. Also not shown are any optical filters and micro lenses that can be optional depending on the application of the photosensor or pixel. Light impinges on the surface where the microholes are formed. The lateral dimension of the microhole can range from 200 nm - 2000 nm and in some cases from 400 nm - 1500 nm. The cross sectional shape of the microhole can be conical, trapezoidal, rectangular, cylindrical, funnel or any combination thereof. The microhole can be circular, square, rectangular, polygonal, hexagonal, amoebic to name a few and can be arranged in the case of multiple microholes in a periodic or aperiodic or random manner and in some cases a single photosensor or pixel can have different size and shape holes, and in some cases photosensors or pixels can have different sizes in an imaging array and in some cases the photosensor or pixel can have different size holes and different shaped holes than adjacent or neighboring pixels. For example in an imaging array certain pixels or photosensors can have holes of a certain lateral dimension and other photosensors or pixels in the imaging array can have a different shape and I or lateral dimensions of microhole or holes. [00175] Also not shown are metal pads for stacking the photosensor or pixel wafer to CMOS logic wafers which in some cases can consist of multiple stacking that can include CMOS ASICs, memory, signal processing wafers, image processing and artificial intelligence to name a few and the stacked chip can include edge computing.

[00176] FIGs. 17A-17C are partial simple schematic cross sections of a photosensor or pixel wafer stacked to CMOS ASICs, according to some embodiments. The arrangements can include multiple stacked wafers to enhance the chip functionality and can include digital signal processing memory, data communication, artificial intelligence to name a few. In addition, to control the dark current or leakage current contoured doping of either P or N type species can be applied to exposed semiconductor surfaces. In these examples Si surfaces includes the microhole, in this case an inverted pyramid. In FIG. 17A, an opposite polarity dopant 1734 is buried in the photosensor or pixel for example as shown the opposite polarity buried dopant 1734 can be P type and the contoured dopant covering exposed surfaces can be N type 1736 and further can be passivated with a dielectric such as Si dioxide 1710. The P and N region can be interchanged such that the contoured doping of the exposed surfaces can be P type and the buried dopant within the photosensor or pixel can be N type. Cathodes and anodes can be formed to the N and P region and a reverse bias can be applied to the anode and cathode with a reverse bias voltage ranging from 0.1 - 2 volts, and in some cases 1 - 10 volts or more. Multiple P and N regions can be formed within the photosensor or pixel such that a PN junction, PIN, PIPN, PIPIN junctions such that the photosensor or pixel can operate as a photodiode or avalanche photodiode or single photon avalanche photodiode with associated circuits in the CMOS ASICs for biasing and conditioning the photosensor. In some cases the photosensor or pixel can operate in a phototransistor mode with doping regions consisting of NIN, PIP, PNP, NPN for example. Also as shown an NIR pixel or photosensor is included with the Red, Green, Blue pixels to improve NIR detection sensitivity in bright visible light and in some cases the NIR pixel may not be needed. The red, green, blue pixels are arranged in a Bayer pattern and with the addition of a NIR pixel the Bayer pattern may be modified, and the image sensor can include both the standard unmodified Bayer pattern and modified Bayer pattern to create both a visible image and a NIR image simultaneously. The NIR wavelength can range from 700 nm - 1100 nm, and in some cases 850 nm, 905 nm, and 940 nm for applications in security, LiDAR, facial recognition, augmented reality, virtual reality, robotics, machine vision, and medical imaging to name a few. As shown a single inverted pyramid per pixel is formed by wet etching however in some cases dry etching can be used for conical, cylindrical, funnel shaped holes, and in some cases both dry and wet etching can be used where the wet etching can remove surface damages due to dry etching. In some cases for larger photosensors or pixels multiple microholes can be used and the microholes can have different lateral dimensions or hole patterns and can be periodic, aperiodic or random. The microhole can be a geometric shape such as circular, square, rectangular, hexagonal, polygonal, and in some cases can be amoebic. The cross section of the hole can be inverted pyramid, trapezoidal, conical, cylindrical, funnel and / or any combination thereof.

[00177] The thickness of the Si device layer or the Ge layer can range from 300 nm - 3000 nm, and in some cases to 5000 nm, and due to the thinness of the semiconductor layer the rise time or jitter time due to an optical impulse response can be 20 picoseconds or less, and in some cases 10 picoseconds or less, and in some cases can be 0.1 - 6 picoseconds, and the bandwidth can range from 50 GHz - 200 GHz and the transit time of the electron-hole can range from 0.1 - 30 picoseconds, and in some cases 1 - 50 picoseconds. The gain from avalanche or transistor operations can range from 2 - 2000 or more.

[00178] A voltage can be applied between the anode and cathode electrode such that an electric field is established between the N and P doped regions to sweep out photo generated electron-holes. The applied voltage can be a reverse bias for a PN junction with voltage ranges from 0.1 - 2 volts and in some cases 1 - 3 volts, and in some cases greater than 3 volts. As shown the buried P dopant is connected to an anode electrode and the contoured side wall dopant of the sidewall of the pixel and the microhole is N dopant and connected to a cathode electrode at 1 or multiple places in the pixel array. The P and N in some cases can be interchanged such that the buried P dopant can be a buried N dopant and the contoured dopant of the pixel and microhole can be the opposite polarity for example P dopant. As shown only 2 doped regions are shown, and in some cases there can be more than 2 doped N and / or P regions. The Si can be I or low dope P or N, and the doped regions for the contour and the buried doped region can be heavily doped such as P+, P++, N+, N++ or P and N where the doping range can be 10¹⁶ - 10²¹ per cm³ for example. Degenerate doping ranges are also possible, in some cases hyper degenerate doping of greater than 10²¹ cm³. Other doping configurations such as PIPIN, PIPN for avalanche photodiodes and NIN, PIP for phototransistor doping, and the P and N can be interchanged.

[00179] FIG. 17B is a simple schematic cross section similar to FIG. 17A except all the filters are NIR (near infrared) and the infrared filters can be all at similar wavelengths, and in some cases can be different wavelengths for example NIR1 and NIR2 can be at 850nm, and NIR3 and NIR4 can be at 940nm and I or any combination in the wavelength range from 700 - 1100 nm.

[00180] FIG. 17C is similar to FIG. 17A without the added NIR filter and the RGB (Red Green Blue) pixels are arranged in a standard Bayer pattern.

[00181] In some cases, multiple image sensor wafers can be stacked where the sensors can have same or different pixel density and or pixel dimensions, shapes and can detect same or different wavelength ranges. For example an RGB image sensor wafer can be stacked on top of a NIR image sensor wafer and the NIR sensor wafer can detect light with wavelength ranges 750-1100 nm and in some cases 800-1000 nm for silicon image sensors and 750-2000 nm and in some cases 1000-1700 nm for germanium on silicon, Ge on Si, image sensors and the Ge can be Ge alloy such GeSn, GeSi, GeX where X can be other elements or combination of elements. Ge on Si can have multiple layers of Ge and Ge alloys such as GeX. In addition Ge/GeX can be selective area epitaxially grown on crystalline silicon and can be crystalline and or polycrystalline.

[00182] Silicon CMOS ( complementary metal oxide semiconductor) image sensors (CIS) can be fabricated on crystalline silicon. In some cases CIS can be polycrystalline and or a combination of crystalline and polycrystalline silicon. In some cases Ge on Si CIS can be epitaxial. In some cases Ge on Si CIS can be epitaxially grown on crystalline and I or poly crystalline Si.

[00183] FIGs. 18A-18F are partial schematic top view of pixels for CMOS image sensors, according to some embodiments. FIG. 18A shows a flat pixel without any photon absorption enhancement structures. The pixel size can range from 600 nm - 3000 nm lateral dimension, and in some cases less than 600 nm, and the pixel can be a square or rectangular or hexagonal or polygonal. The thickness of the Si for the pixel can range from 3 microns - 5 microns and in some cases from 1 micron - 3 microns, and in some cases less than 1 micron.

[00184] As shown the rectangular microholes are rectilinear; however in some cases the microhole can have curves and / or a combination of curves and linear segments. The thickness of the Si for the pixel I photosensor wafer using stacked technology also known as 3D technology can range from 1 - 5 microns or more, and in some cases 3 - 5 microns. The drawing represents a single pixel in a pixel array that can range from 100,000 pixels I photosensors - 1 billion or more pixels I photosensors, with the size of the pixel I photo sensor array varying from a few millimeters x a few millimeters to 10s of millimeters x 10s of millimeters. The deep trench isolation (DTI) can have a width ranging from 50 nm - 250 nm, and in some cases 100 nm - 200 nm, and in some cases greater than 250 nm.

[00185] FIG. 18B shows two rectangular intersecting microholes 1840 for photon absorption enhancement as disclosed in US 2020/0028000 A1 and the rectangular holes are partially etched into the Si pixel. The etch depth can range from 300 - 2500 nm and I or ! the thickness of the Si layer or 1 or % of the Si thickness. The width of the rectangle microhole can range from 20 - 600 nm and in some cases 100 - 800 nm, and the length of the rectangular hole can range from 400 - 3000 nm. The pixel size ranges can be as in FIG. 18A, and in some cases can be 2400 nm².

[00186] The rectangular holes can intersect at any point however as shown in FIG. 18B it intersects at the midpoint to form a cross and the cross can be asymmetric or symmetric and the rectangular holes can extend partially in the Si pixel and I or entirely to the edge of the Si pixel, and the quadrant can be of the same size or different size depending on the intersecting point of the rectangular holes. As shown the rectangular holes intersect at a perpendicular angle and in some cases can intersect at a non perpendicular angle in which case the quadrants can be polygonal. The cross structure which consists of 2 intersecting rectangular holes in some cases can be considered as a single hole and can have a width ranging from 50 - 700 nm, and in some cases 100 - 400 nm, and can have a depth ranging from 0.5 microns - 2.5 microns, and in some cases can have a depth ranging from 1 - % of the Si thickness. The pixel size can range from 3 microns x 3 microns - 0.5 microns x 0.5 microns, and in some cases 2.4 microns x 2.4 microns. The rectangular holes can extend partially across the surface of the pixel, and in some cases can extend entirely across the surface of the pixel, and in some cases 1 end of the rectangular hole can intersect the DTI and the other end of the rectangular hole can be partially across the surface of the pixel and not intersect the DTI.

[00187] FIG. 18C is similar to FIG. 18B with the addition of a single inverted pyramid 1842 in each of the 4 quadrants of the pixel. The base of the inverted pyramid can range from 100 - 1000 nm, and in some cases 400 - 800 nm, and in some cases 600 - 1200 nm, and the inverted pyramid can be a square or rectangle, and in some cases the inverted pyramid can be an inverted trapezoid that can be formed using anisotropic wet etch on crystalline Si with chemicals such as KOH or TMAH. The quadrants can have different size inverted pyramids or in some cases no inverted pyramid on one or more of the quadrants.

[00188] FIG. 18D is similar to FIG. 18C with the exception that the inverted pyramids can be replaced with a cylindrical hole or a funnel hole 1844. The diameter of the cylindrical hole 1844 can range from 200 - 1000 nm, and the depth can range from 200 - 2500 nm or it can range from 1 of 14 or % the thickness of Si.

[00189] FIG. 18E shows a single irregular hole 1846. The lateral dimension of the irregular hole can range from 20 - 1200 nm and the depth can range from 100 - 2500 nm, and in some cases 14 or 14 or % the thickness of Si. The irregular holes can also be formed in place of inverted pyramid, inverted trapezoid, cylindrical, funnel holes as shown in FIG. 18B - FIG. 18D.

[00190] FIG. 18F shows multiple intersecting rectangular holes 1848 that can intersect at 1 or more points and can extend partially across the pixel or extend entirely across the pixel and where each rectangular hole can have different length and in some cases different depth, and in some cases different width.

[00191] The pixel size can range from 3 microns x 3 microns to 0.8 micron x 0.8 micron or less and the rectangular trenches for photon absorption enhancement can have a width ranging from 20 nm - 400 nm. The length of the rectangular holes can extend entirely across the pixel or partially across the pixel. The depth of the rectangular holes can be partially etched into the Si pixel such that there can be a common P or N region for each of the 4 quadrants so that smaller Si photosensors contribute photocurrent to a single pixel. A microhole can be etched in 1 or more of the rectangular quadrants and can be an inverted pyramid or cylindrical hole or funnel hole or conical hole, and in addition in some cases the hole can be irregular. The lateral dimension of the microhole in each of the quadrants can range from 400 nm - 1000 nm or more and in some cases 400 nm - 800 nm, and in some cases 20 - 400 nm. Not shown are passivation layers within the microhole and additional doping regions of that can be P or N dopant that can be conformal doping along exposed surfaces of the Si semiconductor and a dopant of the opposite polarity buried within the pixel to provide a P and N region such that a reverse bias voltage can be applied to the anode and cathode to generate an electric field to collect the electron hole pairs generated by the incident photons. Also not shown are anode, cathode electrodes, connecting electrodes, optical filters for RGB and NIR wavelengths and microlens. This structure can form the photosensors using stacked technology with 1 or more CMOS logic wafers, memory wafers, Al wafers to name a few. Also not shown are planarization layers. The rectangular holes as shown has a tic-tac-toe pattern, however in some cases the spacing between the rectangular holes can be uniform or non-uniform. The rectangular hole or holes can extend fully or partially across the surface of the pixel. In some cases the criss-cross pattern can have N rectangular horizontal holes and M rectangular vertical holes and where N and M can be an integer of 1 or greater than 1 . And in some cases N or M can be zero. The width of the rectangular hole(s) can range from 20 nm - 700 nm, and in some cases greater than 700 nm, and the depth of the rectangular hole(s) can range from 0.5 microns - 2.5 microns, and in some cases the depth of the microhole can range from ! - % the thickness of Si, and in some cases greater than % the thickness of Si. [00192] FIGs. 19A-19C are simple partial schematic of the top views of a single pixel, according to some embodiments. The pixel can include a single cross or X microhole which can be part of a larger array for CMOS image sensors. A cross microhole is as shown, however the cross can be rotated by 45 degrees such that it can look like an X and in some cases the cross can be rotated to any angle between 0 and 360 degrees.

[00193] FIG. 19A shows a cross microhole 1940 where the cross is stubby and can have lateral dimension of the width ranging from 20 nm - 700 nm and the length can range from 200 nm - 1000 nm and in some cases greater than 1000 nm. The pixel is surrounded by a deep trench isolation and the sidewall is passivated and the trench planarized. Similarly the cross microhole is passivated and planarized. Not shown are doped regions of N and P type dopant to from a cathode and anode for voltage biasing and extracting the optically generated photocurrents.

[00194] FIG. 19B is similar to FIG. 19A with the cross 1940 extended symmetrically but within the pixel but not to the pixel boundaries. In some cases the cross can be extended asymmetrically.

[00195] FIG. 19C is similar to FIG. 19A with the cross 1940 extended to the boundary of the pixel symmetrically.

[00196] The crosses 1940 shown in Figs. 19A-19C are symmetric in that they intersect at the midpoint, however the crosses can be asymmetric and intersect at points other than the midpoint. In addition, the crosses in FIG. 19A and 19B are placed at the center of the pixel and in some cases the crosses can be placed off center in respect to the pixel.

[00197] FIGs. 20A-20C are simple partial cross section schematics of a pixel or photosensor or photodetector with different microholes or holes, according to some embodiments. In etching the microholes or holes the surface area of the pixel I photosensor is increased compared to that of a flat pixel or a pixel without any features on the surface. The increase in surface area due to the etching of microholes or holes to enhance photo absorption in the red to near infrared wavelengths to a depth of 300 nm - 2000 nm, and in some cases from 500 nm - 2500 nm, and in some cases 1000 nm - 2500 nm or more than 2500 nm can increase the surface area significantly. [00198] In FIG. 20A an inverted pyramid 2040 is etched into a pixel where the pixel can be a square or rectangular with lateral dimensions ranging from 400 nm - 3000 nm, and in some cases 600 nm - 2400 nm. By etching a single inverted pyramid with dimensions ranging from 700 - 1000 nm the surface area can increase by 100% or more.

[00199] FIG. 20B is similar to FIG. 20A except the inverted pyramid microhole is replaced by two interersecting rectangular microholes 2042 (one of which is not visible) etched to a depth of between 1 and 2 microns and extends between the length and width of the pixel. The increase in the surface area can range from 100 - 300% or more, and in some cases 150% - 300% or more.

[00200] FIG. 20C is similar to FIG. 20A except that for an inverted pyramid it has a cylindrical hole 1846 of 800 nm diameter etched to a depth of 1 -2 microns. The increase in surface area can range from 200 - 500 % and in some cases greater than 500%.

[00201] As can be seen in FIGs. 20A-20C, other microholes or holes can be etched into the pixel I photosensor I photodetector I avalanche photodetector and by etching microholes or holes to increase optical sensitivity or quantum efficiency of the pixel I photosensor I photodetector, the surface area is significantly increased compared to that of a comparable flat pixel I photosensor / photodetector without surface features on the Si. Depending on the kind of microholes or holes etched into the Si using either wet or dry etch or a combination of wet and dry etch the surface area can increase by 50% - 100%, and in some cases from 100% - 200%, and in some cases 200% - 300%, and in some cases 300% - 500%, and in some cases greater than 500%. This increase in surface area is independent to the position of the microholes or holes, the shape and cross section of the microhole or hole.

[00202] FIGs. 21 A-21 D are plots showing FDTD Lumerical simulation of a single inverted pyramid in a pixel similar to FIG. 3F. The pixel size is 1.12 microns x 1.12 microns and the Si thickness is 3 microns surrounded by a deep trench isolation with a width of 150 nm and a depth of 2.5 microns and the deep trench isolation (DTI) is filled with a dielectric such as Si dioxide and so is the inverted pyramid. The inverted pyramid is a square pyramid with a sidewall angle of 54.7 degrees and where the lateral dimension of the base of the pyramid is varied from 200 nm - 1000 nm. The vertical axis is absorption or optical efficiency and the horizontal is wavelength in microns from 300 nm - 1100 nm. The various plots shown are for different sizes of inverted pyramid etched into the pixel. As can be seen in the plots different size pyramid can maximize different wavelengths for example for blue a base dimension of 900 nm gave the highest optical efficiency or absorption, for green a base dimension of 1 micron inverted pyramid gave the highest optical efficiency I absorption and similarly for red a base dimension of 1 micron have the highest optical efficiency I absorption, and for NIR wavelengths a base dimension of 900 nm and 1000 nm gave the highest optical efficiency I absorption.

[00203] The simulation is of a Bayer pattern that can be part of an array of photosensors in a high performance CMOS image sensor.

[00204] FIG. 21 E plots the absorption or optical efficiency vs base dimension of the inverted pyramid for 800 nm wavelength. As can be seen a base dimension of 700 - 1000 nm gave an absorption or optical efficiency of 60% or more.

[00205] FIGs. 22A-22C are plots showing a FDTD Lumerical simulation of a single cylindrical hole in a pixel similar to FIG. 3B, according to some embodiments. The pixel size is 1.12 microns x 1.12 microns and the Si thickness is 3 microns and the pixel is surrounded by DTI with a width of 150 nm and a depth of 2.5 microns, and both the DTI and the cylindrical hole are filled with a dielectric and the dielectric can be Si dioxide. The vertical axis is absorption or optical efficiency (OE) and the horizontal axis is wavelength in microns from 0.3 microns - 1.1 microns. The cylindrical hole has a diameter of 800 nm and the depth of the hole is varied from 0.25 micron - 3 microns. From the plots a depth of 2 micron cylindrical hole and a diameter of 800 nm gave the best absorption I OE for blue, green and red wavelength ranges and also the NIR wavelength ranges.

[00206] The simulation is of a Bayer pattern that can be part of an array of photosensors in a high performance CMOS image sensor.

[00207] FIG. 22D shows a single cylindrical hole with a diameter of 800 nm in a pixel as described above with respect to FIG. 22A at 850 nm wavelength where the plot shows a variation of absorption / OE as a function of the etched depth of the cylindrical hole. In this case an optimum depth of 2 microns can be seen and where the absorption / OE begins to decrease at depth greater than 2 microns. [00208] FIG. 23 shows a table of percentage of volume of crystalline semiconductor of a pixel reduced by the introduction of a single microhole etched into the pixel. The pixel in this example is a square pixel of 1 micron x 1 micron and has a depth ranging from 1 - 5 microns. In this example the semiconductor is crystalline Si, however it can also be crystalline Ge, and in some cases a combination of crystalline Si and crystalline Ge, and I or combination of any alloys of Ge and Si and in some cases Sn and I or other elements.

[00209] The reduction of the material volume of a pixel due to a single microhole can range from 1 % - 50%, and in some cases less than 1 % and in some cases greater than 50%, and in some cases multiple microholes in a pixel can similarly reduce the material volume of a pixel from 0.5% - 50% or more. As shown in the table 3 different pixel volumes are shown in the first column, for example 1x1x1 micron³, 1x1x3 micron³, and 1x1x5 micron³. Other pixel volume for example pixel sizes less than 1 micron x 1 micron and with thickness ranging from 0.5 microns - 5 microns can similarly result in pixel volume reduction ranging from approximately 1 % - 50% or more with the etching of microhole or holes independent of the shape and cross section of the microhole or holes. In the table 3 different kinds of microhole are shown, inverted pyramid with a sidewall angle of 54.7 degress, with a base dimension of 700 nm x 700 nm, a conical microhole with a 800 nm diameter and 60 degree cone, and a cylindrical hole 800 nm in diameter and a depth of 1 micron for the 1x1x1 micron³ pixel and a depth of 2 microns for the 1x1x3 and 1x1x5 pixels. These hole shapes were chosen as an example, however other hole shapes can be included to show the reduction in pixel material volume.

[00210] FIG. 24 shows a simple partial schematic top view of a single 3-D integrated chip using stacking technology of a high speed optical receiver, according to some embodiments. The high speed PD array can be stacked to CMOS ASICs for form a single chip 2400. The high speed PD array 2440 is shown in the center, surrounded by alignment PDs 2402. In some cases, this can be a time-of-flight receiver for LiDAR applications. The high speed photodetector or pixel can be fabricated from Si, and in some cases Ge on Si, where the Ge can be alloys of Ge, Si, Sn, and other materials that can alloy with Ge to operate at one or more wavelengths from 800 nm - 2000 nm, and in some cases the high speed photodetector can be PIN, APD, SPAD, phototransistors to name a few. In the case of APD or SPAD the photons are absorbed in the Ge and I or Ge alloy layer, and the amplification takes place in the Si region such as avalanche in a PN or PIN or I PIN structure and the Ge and its alloy can be P doped. Microholes can be formed in the Ge or Ge alloy layers to increase the absorption efficiency. The microholes can be of any geometric shapes and in some cases non-geometric shapes, and in some cases can consist of one or more microholes. The microholes can be intersecting such as long rectangular holes intersecting with other long rectangular holes at the midpoint for example. Each high speed photodetector can be electrically and optically isolated from adjacent high speed optical detectors and the signals from the optical detectors are connected to corresponding CMOS ASICs and in some cases the photocurrent can be summed together to form a large optical signal. The ASICs can have trans impedance amplifiers, clock data recovery, linear amplifiers, normalization circuits, memory, logic, RF transmitter, and any other ASICs necessary to process the signal and send the signal to other processing units. The chip can also include alignment photodetectors which can be large area - in this case as shown 4 large detectors assist in alignment of optical beam in free space optics communication at 1550 nm wavelength for example, and data rates can be from 1Gb/s - 100 Gb/s, and in some cases greater than 100 Gb/s.

[00211] By using a multitude of smaller high speed pixels in a large array is formed where the pixel size can range from 5 microns linear dimension to 100 microns linear dimension, and in some cases greater than 100 microns linear dimension, and the overall chip size can range from 200 micron linear dimension to 1000 microns linear dimension, and in some cases greater than 1000 micron. By using an array of smaller fast photodetectors, a signal from a large beam can be detected and processed at a higher data rate than by a corresponding single large area photodetector for example.

[00212] This technology can also apply to time-of-flight, LiDAR applications with appropriate CMOS ASICs distance, speed, and direction of objects can be formed in an image than can be further processed by artificial intelligence (Al) processors to determine potential obstacles and I or hazards.

[00213] Microstructure hole or holes for light /photon trapping enhance optical sensitivity and speed in thin silicon PD/APD/SPAD for applications in addition to LiDAR for time of flight imaging at NIR wavelengths, biomedical imaging applications using silicon APD and or SPAD for high temporal resolution at UV to visible wavelengths, 300 nm to 650 nm and in some cases 200 nm to 1100 nm and in some cases 400 nm to 560 nm wavelengths and with temporal resolution of 100 picosecond (ps) or less and in some cases a few ps to 50 ps.

[00214] Fluorescence lifetime imaging (FLIM), time of flight positron emission tomography (TOF-PET), also are suitable applications of devices described in this patent specification. See reference, Bartolo-Perez et al, Avalanche photodetectors with photon trapping structures for biomedical imaging applications, Optics Express, Vol. 29, No. 12/7 June 2021 , incorporated as part of this disclosure. The microstructure hole or holes in APD and or SPAD for UV-visible applications can be optimized, see for example reference Ahamed et al, Controlling light penetration depth to amplify the gain in ultra-fast silicon APDs and SPADs using photontrapping nanostructures, SPIE 2021. For high spatial and temporal resolutions, APD/SPAD pixel dimensions can be sub micron to several microns, in some cases from 0.5 micron to 5 microns. In some cases for pixels lateral dimension can be approximately one micron or less and one microhole per pixel can be used where the microhole can be an inverted pyramid, or cylindrical. See Devine et al. In some cases the microhole can be a cross or intersecting trenches with rectangular or triangular cross section for example. In some cases, larger pixels can use a single and or multiple microholes of any geometric or non geometric or amoebic shapes and can intersect or not intersect. Deep trench isolation between pixels can be used for electrical and optical isolation.

[00215] The array of photodetector shown in FIG. 24 can be phototransistors, photoconductors, photodiodes, avalanche photodiodes, single photon avalanche photodiode and or combination thereof and can operate at the same or different bias voltages ranging from 0.1 to 35 volts for-wad and or reverse bias. The photodetectors in the array can be square, hexagonal, rectangular, triangular, trapezoid, polygonal, star, circular, oval, amoebic or any combination of geometric and or nn geometric shapes. The largest lateral dimension of the photodetector can range from 0.5 to 10000 microns and in some cases 1 to 100 microns and spacing between adjacent photodetector from 10 to 1000 nm. [00216] Not shown are microhole or microholes on the photodetectors, where the microhole(s) can be invented pyramids, inverted trapezoids, cylindrical, funnel, intersecting rectangles, amoebic to or holes can be name a few and any combination thereof. The microholes can be passivated and filled with material of low optical refractive index than Si, Ge and any alloys of Si and or Ge. The microholes can be periodic or aperiodic.

[00217] The photodetector can have a modulation bandwidth ranging from 0.1- 50 GHz at NIR wavelengths 700-1000 nm for Si and 700-1700 nm for Ge on Si ot Ge alloy, Ge on Si . Rise times (jitter) in response to an optical impulse can range from 1-100 pico second (ps). External quantum efficients at certain NIR wavelengths 850, 905, 940, 1350, 1550 nm for example can be 20% or greater. |A photodetector with microhole(s) has a higher external quantum efficiency than a comparable photodetector without microhole(s) and in some case the ratio of EQE of photodetector with microhole(s) to the EQE of photodetector without microhole(s), EQEhole/EQEnohole is greater than 1 and in some cases greater than or equal to 2 at certain NIR wavelenghts such as 850, 904, 940, 1550 nm for example.

[00218] In some cases, certain applications such as free space optical communication, frequency modulation constant wave , FMCW, tLiDARme of flight, ToF, LiDAR some or all of the photodetectors can be wired to CMOS ASICs such that the individual photodetectors contribute to a common signal or mage. The advantage is that the photodetector array can be fast and high sensitivity, whereas a single large area, similar to the combined area of the photodetector array, is slower due to its large capacitance resulting in large RC time where R is load resistance and C is capacitance.

[00219] The photodetector array can operate all in PD or APD or SPAD mode and in some cases operate in any combinations of PD, APD, SPAD mode and in some cases the photodetector array can have a single type of PD or APD or SPAD and in some cases any mixture of PD, APD, SPAD. Photodiodes depending on doping profiles can operate in any of the 3 modes, PD, APD, SPAD depending on the reverse bias and biasing circuitry.

[00220] The ensemble of high speed photodetectors can be thought of as a phased array photodetectors with the same photon capture cross section of an equivalent large area but lower speed photodetector. In some cases the photodetector array can be on a curved surface to capture photons at a larger or a narrower field of view and in some cases micro-lens can be on each photodetector in addition to optical filters. Micro-lens can also be formed on multiple photodetectors and can have same or different lens characteristics, fish eye, wide angle, telephoto, simple, to name a few.

[00221] The photodetector array can consist of 2 or more photodetectors and in some cases 10-10000 or more and in some cases 1-100 million or more.

[00222] Multiple, 2 or more, LiDAR, light distance and ranging, receiver (Rx) chips can be used, either as a single photodetector or an array of multiple photodetectors, to improve field of view and or improve capturing of reflected ToF, time of flight, or FMCW, frequency modulated constant wave , LiDAR signals or photons. Multiple LiDAR Rx can be connected in a phase array of Rx chips. In some cases multiple LiDAR transmitters, Tx, and or multiple synchronous light sources can be used together with multiple Rx.

[00223] FIG. 25 shows a partial simple schematic cross section of a pixel array that can have of both Si pixels 2530 and Ge/Ge alloy on Si pixels 2532, according to some embodiments. The Ge and or Ge alloy can be grown on Si using selective area epitaxial growth (SAEG) technology. The thickness of the germanium and or germanium alloy layer or layers can range from 10-5000 nm and in some cases 300-3000 nm. The hole or holes 2540 to enhance photon absorption or quantum efficiency can be formed after the growth of germanium/germanium alloy(s) (Ge/Ge alloy) in some cases using selective area epitaxial growth (SAEG) the hole(S) can be formed by depositing a dielectric material such as silicon dioxide or silicon nitride to prevent epitaxial growth of Ge, Ge alloy(s) and can only grow epitaxially on exposed silicon surfaces. The hole(s) 2540 can be dielectric pillar(s) for example. The pixels 2530 and 2532 are isolated with deep trench isolation 2580 that includes Si oxide I dielectric 2510. The pixels have an upper doped region 2534 and a lower doped region 2536 being of opposite polarity.

[00224] The Ge and or Ge alloy (GeSi, GeSn, GeC, GeSiSn, GeSiC to name a few) can have one or more layers grown on Si for lattice matching using SAEG. Hole or holes can be formed on the pixels with lateral dimensions ranging from 100-2000 nm and in some cases 600-1200 nm and where hole or holes can have various shapes and cross sections as discussed in this application.

[00225] The pixels 2530 and 2532 can be photodiodes, MAPDs, SPAD, phototransisters and or any combinations thereof.

[00226] Not shown are optical filters, microlens, ohmic contacts to n and p regions, connecting electrodes, bond metals for stacking or 3D integration to CMOS ASICs and external biasing circuitry to name a few.

[00227] Optical filters can be used to select desired sensing wavelengths and block undesirable wavelengths. For example a 1550 nm bandpass filter can be used on the Ge Ge alloy pixel 2532 and block visible wavelengths RGB filters, and 850 nm, 905 nm, 940 nm bandpass filters on Si pixels 2530 in the same array as the Ge based pixels, for example, for applications where multiple visible and NIR wavelengths can be detected simultaneously and images of both visible and NIR wavelengths can be formed in some cases overlapping mages. As in FIGs. 9A-9C, NIR filters can be distributed in the RGB Bayer or modified Bayer patterns. Any combinations of red, green, blue, NIR filters can be used depending on applications.

[00228] The pixels in the array can be the same size or different size and or any combinations of sizes and shapes.

[00229] Applications include stereoscopic and non stereoscopic imaging at multiple wavelengths for autonomous vehicles, robot, augmented reality, virtual reality, machine learning, artificial intelligence, security, facial recognition, LiDAR to name a few.

[00230] With germanium based material selectively area grown on silicon to allow both silicon and germanium and or germanium alloy(s) pixels fabricated on the same wafer and in some cases same array can extend CMOS image sensors wavelengths to 1700 nm and in some cases to 2200 nm. For LiDAR applications imaging arrays with silicon and germanium based pixels allow Imaging at multiple near infrared, NIR, wavelengths that can result in greater information content and higher accuracy of 3D, three dimensional, resolution. In particular longer wavelengths can penetrate further in adverse weather conditions such as fog, rain, smoke, snow to name a few. LiDAR can operate in time of flight, ToF, mode or frequency modulation constant wave, FMCW, mode, or a coherent constant wave mode and can use one or more wavelength for increases distance resolution.

[00231] In some cases for optical interconnect applications, photodetectors of both Si and Ge, Ge alloy can be fabricated in an array to detect multiple wavelengths for high aggregated data bandwidths in corse wavelength division multiplexing, CWDM, in one or more optical fiber for example.

[00232] Although the foregoing has been described in some detail for purposes of clarity, it will be apparent that certain changes and modifications may be made without departing from the principles thereof. It should be noted that there are many alternative ways of implementing both the processes and apparatuses described herein. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the body of work described herein is not to be limited to the details given herein, which may be modified within the scope and equivalents of the appended claims.

Claims

- 59 - CLAIMS

1 . A microstructure enhanced absorption photosensitive device comprising: a CMOS ASIC wafer (120) and a CMOS image sensor wafer (CIS) (110) stacked to each other such that the CMOS ASIC wafer is configured to receive and process signals that the CIS wafer produces, wherein the CIS wafer comprises: a semiconductor material (102) in which an array is formed of both Si pixels (2530) and Ge pixels (2532); wherein each Si pixel (2530) comprises an upper and a lower region of Si doped to opposite polarities (2534, 2536) and a region of undoped or low-doped Si between said doped Si regions, and a single microhole (2540) extending into the Si pixel; wherein each Ge pixel (2532) comprises an upper and a lower region of Ge or an alloy thereof doped to opposite polarities (2534, 2536) and a region of undoped or low-doped Ge or an alloy thereof between said doped regions of Ge or an alloy thereof, and a single microhole (2540) extending into the Ge pixel; deep trench insulation (2580) between adjacent Si pixels and Ge pixels in said array and an electrically and optically isolating material in said deep trench insulation and in said microholes in the Si and Ge pixels; and pixel electrodes (154) coupled to said Si and Ge pixels, connecting electrodes (152) coupled to at least some of the pixel electrodes, and bonding electrodes coupled to at least some of the connected electrodes, configured to convey electrical signals between said pixels and said CMOS ASIC wafer.

2. The device of claim 1 , in which said Si pixels are configured to operate at shorter wavelengths of light and said Ge pixels are configured to operate at longer wavelengths of light, wherein said array of Si and Ge pixels is responsive to light in at least portions of the 400 nm to 1700 nm wavelength range with absorption greater than 50%. - 60 -

3. The device of claim 1 , in which each of at least some of said microholes comprises a closely spaced group of nanoholes (FIGs. 12A-13E), said groups having cross-sectional shapes matching those of said single holes.

4. The device of claim 1 , in which each of at least some of said microholes comprises two or more nanoholes that partly overlap to thereby form a single microhole (Figs. 18A-20C).

5. The device of claim 1 , further including in said array pixels additional pixels that are otherwise as said Si and/or Ge pixels but are free of said microholes (FIG. 4D).

6. The device of claim 1 , in which at least some of the pixels in the array are electrically coupled with each other to combine electrical output of a plurality of the coupled pixels into a single combined output (FIG. 24), whereby a group of pixels is configured to capture the same incident beam of light and improve a signal-to- noise ratio.

7. The device of claim 1 , in which each of at least some of said microholes comprises a group of closely spaced nanoholes (FIGs. 14A, 14B) that differ from each other in size and serve as the single hole of a pixel.

8. The device of claim 1 , in which at least some of the microholes in the array differ from each other in size and/or shape (FIGs. 20A-20C).

9. The device of claim 1 , further comprising two or more of said CMOS ASIC wafers (120) and/or two or more of said CMOS image sensor wafers (110).

10. The device of claim 1 , in which each of at least some of said pixels is formed with other of said doped regions conformally lining said mirohole an extending along at least one sidewall of the undoped or low-doped region to connect to one of said anode and cathode (FIGs. 17A 17B), and said anode and cathode are at a side of said CIS wafer facing said CMOS ASIC wafer. - 61 -

11 . The device of claim 1 , in which in each of at least some of said pixels one of the doped regions conformally lines the pixel’s microhole and differs in polarity between adjacent pixels (FIGs. 1 , 2).

12. The device of claim 1 , further including Bayer pattern color filters over at least some of said pixels, said color filters in the Bayer pattern including NIR filters for visible light over some pixels and NIR ToF filters over other pixels, wherein said array of pixels is configured for simultaneous imaging by the pixels under all said filters (FIGs. 6, 9).

13. The device of claim 1 , in which said deep trench insulation includes an amorphous semiconductor material between adjacent pixels to reduce optical crosstalk (FIG. 15B).

14. A method comprising: stacking and bonding to each other a CMOS ASIC wafer (120) and a CMOS image sensor wafer (CIS) (110) such that the CMOS ASIC wafer is configured to receive and process signals that the CIS wafer produces; forming the CIS wafer in a semiconductor material (102) by fabricating an array of pixels (2530 and/or 2532) therein ; forming at each pixel an upper and a lower region of semiconductor material doped to opposite polarities (2534, 2536) and a region of undoped or low-doped semiconductor material between said doped regions, and a single microhole (2540) extending into the pixel; forming deep trench insulation (2580) between adjacent pixels in said array and an electrically and optically isolating material in said deep trench insulation and in said microholes in the pixels; and forming pixel electrodes (154) coupled to said pixels, connecting electrodes (152) coupled to at least some of the pixel electrodes, and bonding electrodes coupled to at least some of the connected electrodes, configured to convey electrical signals between said pixels and said CMOS ASIC wafer. - 62 -

15. The method of claim 14, in which the forming of said array comprises forming some of the pixels (2530) in the array of Si doped and undoped or low- doped regions and some of the pixels (2532) in the array of doped and undoped or low-doped regions that comprise Ge or alloys thereof (FIG. 25).

16. A microstructure enhanced absorption photosensitive device comprising: a CMOS ASIC wafer (120) and a CMOS image sensor wafer (CIS) (110) stacked to each other such that the CMOS ASIC wafer is configured to receive and process signals that the CIS wafer produces, wherein the CIS wafer comprises: a layer (102) in which an array of pixels (2530, 2532) is formed; wherein each pixel comprises an upper and a lower region of semiconductor material doped to opposite polarities (2534, 2536), a region of undoped or low-doped semiconductor material between said doped regions, and a single microhole (2540) extending into the pixel; deep trench insulation (2580) between adjacent pixels in said array and an electrically and optically isolating material in said deep trench insulation and in said microholes; and pixel electrodes (154) coupled to said pixels, connecting electrodes (152) coupled to at least some of the pixel electrodes, and bonding electrodes coupled to at least some of the connected electrodes, configured to convey electrical signals between said pixels and said CMOS ASIC wafer.

17. The device of claim 16, in which said pixels comprise both Si pixels (2530) and Ge pixels (2532) and: (a) each Si pixel (2530) comprises an upper and a lower region of Si doped to opposite polarities and a region of undoped or low-doped Si between said doped Si regions, and a single microhole (2540) extending into the Si pixel, and (b) each Ge pixel (2532) comprises an upper and a lower region of Ge or an alloy thereof doped to opposite polarities and a region of undoped or low-doped Ge or an alloy thereof between said doped regions of Ge or an alloy thereof, and a single microhole (2540) extending into the Ge pixel. - 63 -

18. The device of claim 16, in which each of at least some of said microholes comprises a closely spaced group of nanoholes (FIGs. 12A-13E), said groups having cross-sectional shapes matching those of said single holes.

19. The device of claim 16, further including in said array of pixels additional pixels that are free of said microholes (FIG. 4D).

20. The device of claim 16, in which at least some of the microholes in the array differ from each other in size and/or shape (FIGs. 20A-20C).

21. The device of claim 16, in which said doped regions and said undoped or low doped regions comprise Ge or alloys thereof.

22. The device of claim 16, further including one or more additional microholes extending into each of at least some of the pixels in the array (Figs. 3C, 3D).