WO2022055479A1

WO2022055479A1 - Microcontroller chips employing mapped register files, and methods and wireless communication devices using the same

Info

Publication number: WO2022055479A1
Application number: PCT/US2020/049775
Authority: WO
Inventors: Jian Wei
Original assignee: Zeku Inc.
Priority date: 2020-09-08
Filing date: 2020-09-08
Publication date: 2022-03-17

Abstract

Embodiments of apparatus and methods for data processing may be applicable to wireless communication devices. In an example, a microcontroller chip includes a microprocessor, a control unit, and a primary memory. The control unit is configured to direct at least one set of instruction to the microprocessor. The microprocessor is operatively coupled to the primary memory and the control unit. The microprocessor is configured to map a first register file to a first part of a memory address space based on a register base window of a predetermined size. It is also configured to access a first set of data in the primary memory via the first register file based on a first set of instruction.

Description

MICROCONTROLLER CHIPS EMPLOYING MAPPED REGISTER FILES, AND METHODS AND WIRELESS COMMUNICATION DEVICES USING THE SAME

BACKGROUND

[0001] Embodiments of the present disclosure relate to microcontroller chips and methods for data processing, which may be applicable to computers and communication systems, such as a wireless communication device.

[0002] Computers and communication systems are commonly used electronic products in our daily lives, replacing human beings for various types of work, and providing a wide range of convenience. For example, wireless communication devices, such as mobile phones, enable long-distance, instant telecommunications between users and allow internet access almost anywhere in the world. Users may talk to each other and transmit video, audio, images, and data over cellular networks. The telecommunication technologies have evolved significantly in recent years, from cellular networks compatible with the second-generation (2G) and third- generation (3G) standards that only provide a modest speed of wireless data transmission to now widely deployed, more advanced, high-speed fourth-generation (4G) and fifth-generation (5G) cellular networks that are hundreds or even thousands of times faster in data transmission. Users are now able to stream high-definition videos or conduct video conferencing with their wireless communication devices over such high-speed networks.

[0003] Because of the increased amount of data received and transmitted, the data processing capability of the computers and communication systems also need corresponding improvement. Current data processing capability is constrained by the relatively low data operation throughput, high response latency, and inflexible control flow of the microcontroller chips used in computers and communication systems. Thus, there exists a need for a microcontroller chip with more powerful data processing capability in order to catch up with the advanced cellular networks and other new applications of these electronic products.

SUMMARY

[0004] Embodiments of microcontroller chips and methods for data processing are disclosed herein. [0005] In one example, a microcontroller chip can include a microprocessor, a control unit, and a primary memory. The control unit can be configured to direct at least one set of instruction to the microprocessor. The microprocessor can be operatively coupled to the primary memory and the control unit. The microprocessor can be configured to map a first register file to a first part of a memory address space based on a register base window of a predetermined size. It can also be configured to access a first set of data in the primary memory via the first register file based on a first set of instruction.

[0006] In another example, a method for data processing can be implemented by a microcontroller chip. The method can include loading data into a primary memory of the microcontroller chip. The method can also include directing at least one set of instruction to a microprocessor of the microcontroller chip. The method can further include mapping a first register file to a first part of a memory address space based on a register base window of a predetermined size. The method can further include accessing a first set of data in the primary memory via the first register file based on a first set of instruction.

[0007] In a further example, a wireless communication device can include a user interface configured to receive user instructions, a transceiver configured to send and receive wireless data via wireless communication networks, a memory configured to store the wireless data and the user instructions, and a processor, implemented as a microcontroller chip, configured to process the wireless data based upon the user instructions. The microcontroller chip can include a microprocessor, a control unit, and a primary memory. The control unit can be configured to direct at least one set of instruction to the microprocessor. The microprocessor can be operatively coupled to the primary memory and the control unit. The microprocessor can be configured to map a first register file to a first part of a memory address space based on a register base window of a predetermined size. It can also be configured to access a first set of data in the primary memory via the first register file based on a first set of instruction.

[0008] In yet another example, a non-transitoiy computer-readable medium may encode instructions that, when executed by a microcontroller chip, perform a process for data processing. The process may include loading data into a primary memory of the microcontroller chip. The method can also include directing at least one set of instruction to a microprocessor of the microcontroller chip. The method can further include mapping a first register file to a first part of a memory address space based on a register base window of a predetermined size. The method can further include accessing a first set of data in the primary memory via the first register file based on a first set of instruction.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0010] FIG. 1 illustrates a block diagram of a microcontroller chip according to certain embodiments of the present disclosure.

[0011] FIG. 2 illustrates a vector array according to certain embodiments of the present disclosure.

[0012] FIG. 3 A illustrates a register-file architecture according to certain embodiments of the present disclosure.

[0013] FIG. 3B illustrates a register file mapped to a part of the memory address space according to certain embodiments of the present disclosure.

[0014] FIG. 3C illustrates another mapped register file according to certain embodiments of the present disclosure.

[0015] FIG. 4 illustrates a method for data processing according to certain embodiments of the present disclosure.

[0016] FIG. 5 illustrates an exemplary wireless network, in which certain aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure.

[0017] FIG. 6 illustrates a node that may be used for data processing, according to certain embodiments of the present disclosure.

DETAILED DESCRIPTION

[0018] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0019] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that one or more embodiments described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0020] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the terms “based on,” “based upon,” and terms with similar meaning may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[0021] Various aspects of the present disclosure will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system.

[0022] The techniques described herein may be used for various apparatus used in wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC-FDMA) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT) such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E- UTRA), CDMA 2000, etc. A TDMA network may implement a RAT such as GSM. An OFDMA network may implement a RAT, such as long-term evolution (LTE) or new radio (NR). The techniques, apparatus, methods, and systems described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs which may be developed in the future. Likewise, the techniques, apparatus, methods, and systems described herein may also be applied to wired networks, such as networks based on optical fibers, coaxial cables, or twisted-pairs, or to satellite networks.

[0023] Certain embodiments may have various benefits and/or advantage as to various technical aspects. For example, certain embodiments may enhance hardware efficiency. Instead of using the register arrays, register files according to these embodiments are implemented by primary memory (also known as main memory or system memory) based on a register base window. Since the primary memory uses a simpler circuitry (such as fewer electronic components) than the register array, the silicon area cost in the microcontroller chips employing such register files is relatively low.

[0024] Certain embodiments may also provide benefits to software efficiency. In order to process the large amount of data received or transmitted via the high-speed cellular networks (e.g., 4G, 5G, or any future generation of wireless communication networks), the wireless communication devices adopt parallel processing of those data, such as executing a number of instructions on an array of data (e.g., vector array). As a result, a wide data path becomes necessary when transporting data between and within different components of the wireless communication devices. In the case of a microcontroller chip, heavy data traffic is introduced between memory and register arrays, and the microprocessors thereon also need a wider data processing path. The embodiments described herein may tackle this problem by mapping register files to the primary memory, thus eliminating most of the data loading and storing operations and significantly reducing data traffic within the microcontroller chip.

[0025] Although embodiments in the present disclosure are primarily described in the context of the applications in the wireless communication field, a person skilled in the pertinent art would understand that they can also be used in other scenarios where high-performance computing is involved. Examples of such high-performance computing include SIMD (single instruction, multiple data), MIMD (multiple instructions, multiple data), other types of data- level or instruction-level parallelism processing, and the like. In these examples, one or more microprocessors simultaneously compute multiple data points and/or execute multiple instructions. These embodiments can be used in many electronic products and apparatus, including cellphones (smartphones, feature phones, etc.), portable computers (tablets, laptops, etc.), desktop computers (all-in-one computers, gaming machines, etc.), servers (cloud servers, enterprise servers, etc.), wearable gadgets (smart watches, smart fitness bracelets, smart glasses, etc.), loT systems and devices (security systems, home appliances, industrial tools, etc.), automobiles, and many others.

[0026] In some embodiments of the present disclosure, the microprocessor can be a vector processor, which is designed to perform vector processing. Vector processing refers to a data processing method that implements a set of computer instructions on one-dimensional arrays of data, as compared to on single-data items. Such data array is also known as vectors. It is noted that computer instructions are also represented in the form of data, so where no specific distinction is made between data and instructions, the term “data” in the present disclosure may refer to both the instructions and the data depending on the context.

[0027] According to some other embodiments, to reduce latency in fetching data or instructions for processing by the microprocessor from the memory, a register array can be provided and operatively coupled to the microprocessor and the primary memory. A register array according to the present disclosure may be made from a plurality of physical registers on a microcontroller chip, which serve as temporary storage areas for data or instructions to be accessed by the on-chip microprocessor. Because of their architecture design and proximity to the microprocessor, registers allow the microprocessor to access data, execute instructions, and transfer computation results faster than the primary memory. Typically, the registers can be implemented by a special type of static random-access memory (SRAM) consisting of multiple transistors and multiple dedicated read and write ports for high-speed processing and simultaneous read and/or write operations, thus distinguishing from the on-chip primary memory and the secondary memory external to the microcontroller chip (such as a dynamic random-access memory (DRAM), a hard drive, or the like).

[0028] Modern-day computing systems are generally capable of multitasking, which means the microprocessor is able to be shared by multiple processes. When a process is being performed by the microprocessor and another process of higher priority needs immediate attention, the first process can be interrupted and the interim state (or context) of the first process, such as data and/or instructions, can be stored in a memory for later execution. This process switching is also known as context switch. Because of its advantage in access speed, register arrays are traditionally used as the storage place for the context of these processes. After the high-priority process is executed or after another interruption is received, the microprocessor may again load the context of the first process to resume its execution.

[0029] According to the present disclosure, the context of each process being run by the microprocessor can be defined logically by a register file. Each register file may be associated with one or more physical registers fabricated on the microcontroller chip. In order for the microprocessor to know where the context of the process is temporarily stored in the register array, the register files may contain the address of the registers that store the context. Thus, the context of each process can be promptly located via the associated register file. Thereafter, the data or instruction stored therein can be loaded back for the microprocessor to further process.

[0030] When the register files are mapped to the registers in the register array, a wider data path between the microprocessor and the register array becomes the typical choice of accelerating the processing speed. This is because each register file may contain a large number of registers, and also because the multitasking may require simultaneous computation of multiple data with one or more instructions (e.g., using SIMD or MIMD). As an example, a register file may contain 32 vector registers. Each vector register may contain an implementation-independent number of bits, such as 1,024 bits. Thus, the register files of this type can accommodate parallel access by architectures with data and instructions of significant length, such as the VLIW (Very Long Instruction Word) architecture.

[0031] Although the performance of the microprocessor can be enhanced by widening the data path, there are also trade-offs that need to be considered. For instance, as discussed above, the registers in the register array are made of a special type of SRAM consisting of multiple transistors and multiple dedicated read ports and write ports, therefore occupying a larger silicon area per storage unit (e.g., register) than the simpler primary memory which has fewer transistors and read/write ports for each memory cell storing data and instructions. Moreover, for context switch that requires physically moving data and instructions to and from the registers, additional functional units in the microcontroller chip, such as the multiplexer, are needed. This further increases the silicon area cost, which means a larger chip size for processing the same amount of data.

[0032] Another trade-off for mapping register files to the register array is that the peak data bandwidth in such implementations needs to be very high; otherwise, data availability will become the performance bottleneck as the microprocessor has to wait for the incoming data before it can execute any instructions on those data. For example, when the microprocessor contains one or more arithmetic logic units (ALUs), floating-point units (FPUs), or multiplexers, the data to be loaded to these electronic circuits have to keep pace with their processing speed, or the processing by these circuits are idled during certain waiting cycles. As a temporary storage place, the register array has only limited storing capability, and the data and instructions being operated on by the microprocessor thus have to be exchanged between the register array and the primary memory. As a result, heavy bandwidth between the register array and the primary memory is required. This becomes even more alerting in vector processing, where most of the time the data are brought into the register array from the primary memory for just one operation, and then the interim results of this operation are immediately stored back to the primary memory because of, for example, the context switch. The constant transporting of data is also a cause for huge power consumption of the microcontroller chip, which is undesirable considering the limited power supply in those battery-powered apparatus.

[0033] Latency is another issue to be avoided when processing the data. When data and instructions are being loaded or stored between the register array and the primary memory during the context switch, a huge amount of extra cycles may be created. Sometimes the extra cycles are so long that the latency could become fatal for certain critical interrupt in the context switch. As a result, the entire process may have to be restarted, which is a huge waste of processing resources. The present disclosure will address these problems by proposing a novel and advanced memory architecture in the microcontroller chip.

[0034] FIG. 1 illustrates a block diagram of a microcontroller chip 100 according to certain embodiments of the present disclosure. Microcontroller chip 100 can be applied or integrated into various systems and apparatus capable of high-speed data processing, such as computers and wireless communication devices. Using a wireless communication device as an example, microcontroller chip 100 serves as the main computing unit that imports data and instructions from a memory provided inside the system but outside the chip, executing instructions to perform various mathematical and logical calculations on the data, and exporting the calculation results for further processing and transmission over cellular networks.

[0035] An example of the above memory is shown in FIG. 1 as a secondary memory 10. Secondary memory 10 may be provided within the apparatus or system that incorporates microcontroller chip 100. Secondary memory 10 may be located outside microcontroller chip 100 and operatively coupled to it. It may receive and store data of different types from various sources via communication channels (e.g., an internal bus). For example, it may receive and store digital imaging data captured by a camera of the wireless communication device, voice data transmitted via cellular networks, such as a phone call from another user, or text data input by the user of the system through an interactive input device, such as a touch panel, a keyboard, or the like. Secondary memory 10 may also receive and store computer instructions to be loaded to the microprocessor for data processing. Such instructions may be in the form of an instruction set, which contains discrete instructions that teach the microprocessor or other functional components of the microcontroller chip to perform one or more of the following types of operations — data handling and memory operations, arithmetic and logic operations, control flow operations, co-processor operations, etc. Secondary memory 10 may be provided as a standalone component in or attached to the apparatus, such as a hard drive, a flash drive, a solid-state drive (SSD), or the like. Other types of memory compatible with the current disclosure may also be conceived. Note that secondary memory 10 is not the only component capable of storing data and instructions. A primary memory 120 may also store data and instructions and, unlike secondary memory 10, have direct access to the microprocessor. Secondary memory 10 may be implemented by ROM, which can keep the stored data even though power is lost. In contrast, primary memory 120 may be implemented by RAM, and the data may be lost once the power is lost. Because of this difference in structure and design, each type of memory may have its own dedicated use within the system.

[0036] Data between secondary memory 10 and microcontroller chip 100 may be transmitted via a bus 20. Bus 20 functions as a highway that allows data to move between various nodes, e.g., memory, microprocessor, transceiver, user interface, or other subcomponents in the apparatus or system. Bus 20 can be serial or parallel. It can also be implemented by hardware (such as electrical wires, optical fiber, etc.) or software. Taught by the present disclosure, regardless of what types of buses are used, a person skilled in the pertinent art would learn to choose bus 20 that has sufficient bandwidth for storing and loading a large amount of data between secondary memory 10 and primary memory 120 without delay to the data processing by microcontroller chip 100.

[0037] In some embodiments according to the present disclosure, microcontroller chip 100 may be fabricated using the systems-on-chip (SoC) design. SoC design may integrate one or more components for computation and processing on an integrated-circuit (IC) substrate. For applications where chip size matters, such as smartphones and wearable gadgets, SoC design is an ideal design choice because of its compact area. It further has an advantage of small power consumption. In some embodiments, as shown in Fig. 1, a microprocessor 110, primary memory 120, a control unit 130, and a register array 140 may be integrated on a microcontroller chip. It is understood that in some embodiments, primary memory 120 or register array 140 may not be integrated on the same chip, but instead on separate chips.

[0038] Microprocessor 110 according to the present disclosure may include one or more functional units that perform various data operations. For example, microprocessor 110 may include an ALU that performs arithmetic and bitwise operations on data (also known as “operand”), such as addition, subtraction, increment, decrement, AND, OR, Exclusive-OR, etc. It may also include an FPU that performs similar arithmetic operations but on a type of operands (e.g., floating-point numbers) different from those operated by the ALU (e.g., binary numbers). The operations may be addition, subtraction, multiplication, etc. Microprocessor 110 may further include a multiplexer that selects between multiple input data for it to process. This functionality is particularly useful when microprocessor 110 has to decide processing priority with limited computing resources.

[0039] Microprocessor 110 according to the present disclosure may be implemented by one or more microprocessor cores (or simply “cores”). Each core may be one of the functional units discussed above and may carry out data and instruction operations in serial or in parallel. This multi-core processor design effectively enhances the processing speed of microprocessor 110 and multiplies its performance. In some embodiments, microprocessor 110 may be a vector processor that operates on vector array, which will be discussed in more detail in conjunction with FIG. 2 below.

[0040] In some embodiments, as shown in FIG. 1, primary memory 120 may be provided on microcontroller chip 100 and operatively coupled to other components on the same chip, such as microprocessor 110, control unit 130, and register array 140. Primary memory 120 may receive and store data from secondary memory 10 via the bus. Such data include operands and instructions. Primary memory 120 may further provide these data to microprocessor 110 for processing and receive the processing results to be forwarded to secondary memory 10 for storing and downstream transmission.

[0041] In the case where the data being processed are vector array, as illustrated in FIG. 2, microprocessor 110 may need vector processing capability. A vector array 200 may be a onedimensional array of vectors. Each vector may have multiple registers that are used to store data or instructions. In the example shown in FIG. 2, vector array 200 contains 32 different vectors (from V0 to V31), and each vector (e.g., vector 210) has a number of registers defined by a maximum vector length (VLM). VLM may vary according to different implementations, the total number of vector registers used, and the type of each vector. For example, vector array 200 may be designed for an extension with custom datatypes and widths. In other embodiments not shown in FIG. 2, the number of registers may be different, such as 2, 4, 8, 16, 64, or even more. In certain embodiments, multiple vectors can be combined to form longer vectors. This may reduce instruction bandwidth or support mixed-precision operations. However, the bigger the number, the wider data path is required for vector processing of the data stored in those vectors.

[0042] Referring back to Fig. 1, microcontroller chip 100 may further include control unit 130. Control unit 130 may be implemented by circuitry fabricated on the same semiconductor chip as microprocessor 110. Control unit 130 may be operably coupled to other components, such as microprocessor 110 and primary memory 120. In some embodiments, control unit 130 may be integrated with microprocessor 110 in a central processing unit (CPU). In other embodiments, control unit 130 may be separately designed from microprocessor 110 on microcontroller chip 100. Either way, data can be transmitted between these two components. Additionally, a communication channel may also be established between primary memory 120 and control unit 130, as shown in FIG. 1.

[0043] According to the present disclosure, control unit 130 may serve a role similar to a command tower. For example, it may instruct primary memory 120 to receive data from secondary memory 10. It may also direct various computer instructions to be sent from primary memory 120 to microprocessor 110 and tell microprocessor 110 what processes to be carried out on operands loaded from primary memory 120. Computer instructions may be in the form of a computer instruction set. Different computer instructions may have a different impact on the performance of microprocessor 110. For example, instructions from a reduced instruction set computer (RISC) are generally simpler than those from a complex instruction set computer (CISC) and thus may be used to achieve fewer cycles per instruction, therefore reducing the processing time by microprocessor 110. Examples of processes carried out by microprocessor 110 include setting a register to a fixed value, copying data from a memory location to a register, adding, subtracting, multiplying, and dividing comparing values stored on two different registers, etc. In some embodiments, control unit 130 may further include an instruction decoder (not shown) that decodes the computer instructions into instructions readable by other components on microcontroller chip 100, such as microprocessor 110. The decoded instructions may be subsequently provided to microprocessor 110.

[0044] According to the present disclosure, register array 140 may be an optional component of microcontroller chip 100. Register array 140 may contain a plurality of physical registers fabricated on microcontroller chip 100. The register size may be measured by the number of bits they can hold (e.g., 4 bits, 8 bits, 16 bits, 32 bits, 64 bits, etc.). In some operations, it may serve as an intermediary memory placed between primary memory 120 and microprocessor 110. For example, register array 140 may hold frequently used programs or processing tools so that access time to these data can be reduced, thus increasing the processing speed of microprocessor 110 while also reducing power consumption of microcontroller chip 100. In another example, it may store data being operated by microprocessor 110 during context switch, thus reducing delay in accessing the data from primary memory 120. This type of register is known as data registers. Another type is address registers, which may hold addresses and may be used by instructions for indirect access of primary memory 120. There are also status registers that decide whether a certain instruction should be executed.

[0045] The present disclosure provides a novel register file architecture in a microcontroller chip that maps register files to a first part of the memory address space of the primary memory, rather than the register array, to access data through load and store instructions. The mapping is based on a register base window of a predetermined size, which can be moved within the register file array in order to map additional register files. As a result, the data exchange between the register array and the microprocessor, which requires a great number of registers, is no longer needed. This leads to smaller silicon areas occupied by the register file architecture in the microcontroller chip and also dramatically reduces data traffic between register files and on-chip memory (e.g., register array, primary memory, etc.). The context switch can also be realized via just one instruction that controls the movement of the register base window, thus effectively eliminating latency thereof and ensuring timing-critical control functions. Last but not least, it also saves a lot of power consumption by the microcontroller chip, as no physical data is moved during the context switch.

[0046] FIG. 3 A illustrates a register file architecture 300 according to certain embodiments of the present disclosure. Architecture 300 may include a register file array 310 hosting a large number of registers 311. Each register 311 may correspond to data stored in one memory cell of the primary memory. Therefore, register file array 310 may correspond to an array of memory cells of the primary memory. In some embodiments, the aggregated number of memory cells corresponding to register file array 310 may not exceed a maximum proportion as compared to the total storage capacity of the primary memory; otherwise, the primary memory may lose so much storage capacity that it can no longer serve as the fast accessible on-chip memory. In one example, the maximum proportion may be set at 0.5.

[0047] Although registers 311 of register file array 310 are shown in a rectangular fashion in FIG. 3 A, it is understood that this is simplified for illustration purposes only and not intended to limit the implementation of the present disclosure in any way (e.g., requiring that adjacent registers occupy physically adjacent memory cells).

[0048] An example of the primary memory is primary memory 120 in microcontroller chip

100 shown in FIG. 1, and the same descriptions and functions of primary memory 120 may also be applicable to the primary memory in architecture 300. The primary memory may be made of RAM. The physical composition of a memory cell of the primary memory may include latching circuitry that stores one bit of data and one port for both read and write operations. This is simpler than that of a register in a register array, which is made of a special type of RAM consisting of multiple transistors and multiple dedicated read ports and write ports. Therefore, the silicon area for one memory cell in the primary memory in architecture 300 is smaller than one register in the register array.

[0049] In some embodiments according to the present disclosure, architecture 300 may also include a memory address space 320 implemented by a microprocessor compatible with an instruction set architecture (ISA) having memory access instructions. Although the present disclosure is described in the context of a RISC-compatible microprocessor, it is understood that other ISAs may also be used, including complex instruction set computer (CISC). Memory address space 320 may be a scalar space with a large collection of address data 321 that can be mapped to the register files in register file array 310. Each data 321 may be a scalar associated with the address of a vector data indicating where in register file array 310 that data is located.

[0050] Microprocessors according to the present disclosure may directly access data in the primary memory via register files implemented by memory cells of the primary memory, as opposed to via those implemented by registers of the register array. FIG. 3B illustrates a register file 315 mapped to a part of memory address space 320 according to certain embodiments of the present disclosure. In some embodiments, register file 315 may be associated with vectors and/or scalars. Vectors may be in the form of a data array that stores data or instructions. Scalars may be in the form of a single-item data that represents a real number, such as the address bit of a register file.

[0051] In some embodiments, register file 315 may be defined by several parameters, such as its size, the maximum length of data contained in it, etc. As an example, FIG. 3B illustrates one register file 315 that has a size w and a maximum data length (VDM) 1. Accordingly, the number N of memory cells in the primary memory occupied by one register file 315 may be calculated by the equation below:

N = w X I (Eq. 1) wherein w is an integer that equals to 2^k (k = 1, 2, . . . , n), and 1 is a natural number. In the case of processing vector data, size w may indicate or equal the number of vectors contained in register file 315 while 1 may be defined by VLM, which represents the maximum vector length of the vector data. In one example, register file 315 may have a size of 32, which is equal to 32 vectors contained therein. Additionally, each vector may have a VLM of 10 and thus (2¹⁰=) 1024 bits in value.

[0052] Rather than overwhelming the register array with such a large scale of register files, which is especially undesirable during the context switch due to its requirement of an extraordinarily wide data path, register file architecture 300 according to the present disclosure may employ a register base window 318 of a predetermined size to locate register file 315 through a part of memory address space 320. This eliminates the need of transporting data back and forth between the register array and the primary memory, thus reducing data processing cycles and improving data processing performance. The size of register base window 318 may be set as the size of one register file, namely size w. It is also conceived that the size of register base window 318 may be set to be larger than the size of one register file so that it can cover an area larger than one register file. Note that neither “register file” nor “register base window” as used herein requires that the data being processed come from physical registers. Rather, these terms are used to indicate that the present disclosure teaches a novel way to allow microprocessors to access and process data from memory cells of the primary memory at a speed similar to or even higher than that of accessing and processing data using register array as an intermediate.

[0053] In some embodiments, the microprocessor (e.g., microprocessor 110 shown in FIG. 1) may access the data of register file 315 in the primary memory based on a set of instruction directed to it by a control unit (e.g., control unit 130 shown in FIG. 1). An example of the set of instruction includes load/store instructions found in RISC, which directs the microprocessor to access the data of register file 315.

[0054] Register base window 318 may be implemented by software. To create a register base window, in addition to the file size and maximum data length, the address of register file 315 with respect to the primary memory may be needed. In some embodiments, an address may be associated with each register file to be accessed by microprocessor. For example, register file 315 has its address stored in the first vector (V0). In other embodiments, an address may be associated with each data array included in the register file. For example, when there are 32 vector data in one register file (namely, w equals 32 in FIG. 3B), 32 addresses may be used and respectively stored in each of vectors (V0 through V31) in the register file.

[0055] In some embodiments according to the present disclosure, the address or addresses of one register file may be mapped to a part of memory address space 320. For example, as shown in FIG. 3B, the address or addresses of register file 315 may be mapped to a data array 325 of memory address space 320. Thus, a logical relationship may be established between data array 325 and register file 315. This enables the microprocessor to quickly locate the data in register file 315 through moving register base window 318 according to data array 325. In some embodiments, each data array of memory address space 320 mapped with a particular register file in register file array 310 may be selected to have sufficient bits to hold the addresses associated with that register file. As shown in FIG. 3B, data array 325 may consist of k data (e.g., scalars), thus capable of holding 2^k bits of value. In one example of the present disclosure where 32 vector data are included in one register file, data array 325 may have a VDM of 5, thus holding (2⁵=) 32 bits of value that correspond to the number of vector data in that register file. With this mapping mechanism (between memory address space 320 and register file array 310), when the microprocessor receives certain instructions (such as load/store instructions), it is able to access the data of register files through moving register base window 318 according to data arrays in memory address space 320.

[0056] The present disclosure also makes it possible for other components in the microcontroller chip to access these register files through direct memory access (DMA). DMA allows these components to access register files, and thus the data associated therewith, independent of the microprocessor.

[0057] In some embodiments, the address of each register file may correspond to a fixed data array in memory address space 320. This means the address stored in that data array do not change after data associated with the register file are accessed and processed by the microprocessor. In some other embodiments, the address may correspond to a variable data array in memory address space 320. This means the address stored in that data array is updated after data associated with the register file are accessed and processed by the microprocessor. This may allow flexible allocation of memory address space 320.

[0058] FIG. 3C illustrates another mapped register file according to certain embodiments of the present disclosure. In these embodiments, register base window 318 may be moved to activate a second register file 316 in register file array 310 based on a change of corresponding data array in memory address space 320. Thus, data stored in the primary memory and associated with register file 316 may be accessed by the microprocessor for processing.

[0059] According to the present disclosure, register file 316 may have the same characteristics and implementation (e.g., file size and maximum data length) as register file 315 shown in FIG. 3B, except that it is associated with different data array in the primary memory. Therefore, the same description for those characteristics and implementation will not be repeated herein. Similarly, because the size of the register files has not changed when register base window 318 is moved to associate with different register files, the size of register base window 318 does not need to be changed.

[0060] In some embodiments, register file 316 may have one address stored in the first vector (V’0). In other embodiments, register file 316 may have multiple addresses associated with each data array included in register file 316 that are stored in multiple vectors. The address or addresses of register file 316 may be mapped to data array 326 in memory address space 320. Data array 326 may occupy a part of memory address space 320 distinct from data array 325 (shown in FIG. 3B). Similar to register file 315, this logical relationship between data array 326 and register file 316 allows the microprocessor to quickly locate and access the data in register file 316 through moving register base window 318 according to data arrays.

[0061] According to the present disclosure, since data in register files are no longer stored in the register array, access of different register files including data stored in the primary memory can be simply achieved by one or more operations that control the movement of the register base window. In particular, the control can be made based on a change of data array in the memory address space corresponding to the register file. Therefore, during context switch, no physical movement or transfer of data is needed between the register array and the primary array.

[0062] In some embodiments according to the present disclosure, register base window 318 may be programmed by a control/ status register (CSR). The CSR may be a register that stores and provides instructions that control the load and store instructions executed on memory address space 320. Thus, register base window 318 may be applied and moved as a result of the change of data arrays (e.g., data array 325 in FIG. 3B, data array 326 in FIG. 3C, etc.) in memory address space 320. In some embodiments, a control unit similar to control unit 130 in FIG. 1 may be provided to direct a microprocessor to carry out the instructions stored in the CSR. The CSR may include a number of parameters, including one that indicates the size of the register base window, and a parameter associated with the address of the register file.

[0063] FIG. 4 illustrates a method 400 for data processing according to certain embodiments of the present disclosure. The steps on the right side of FIG. 4 may be implemented by a microcontroller chip, such as microcontroller chip 100 in FIG. 1. It is to be appreciated that some of the steps may be optional to perform the disclosure provided herein, and that some steps may be inserted in the flowchart of method 400 that are consistent with other embodiments according to the current disclosure. Further, some of the steps may be performed simultaneously, or in an order different from that shown in FIG. 4. It is further understood that the components used in performing method 400 may be implemented by any of the similar or same components described above in more details.

[0064] In some embodiments according to the present disclosure, at step 402, data may be loaded into a primary memory of the microcontroller chip. The primary memory may be implemented as primary memory 120 in FIG. 1. The data may be single-item data, vector data, or any other types of data compatible with the apparatus, method, and systems disclosed herein. [0065] At step 404, at least one set of instruction is directed to a microprocessor of the microcontroller chip. The microprocessor may be implemented as microprocessor 110 in FIG. 1. The set of instruction may include computer instructions that direct the microprocessor to perform certain functions. The instruction set may be executed on one or more data. When multiple instructions are executed simultaneously, the microcontroller chip is deemed to be able to do high-performance computing, such as SIMD and MIMD.

[0066] At step 406, a first register file is mapped to a first part of a memory address space based on a register base window of a predetermined size. The first register file may be implemented as register file 315 in FIG. 3B. The memory address space may be implemented as memory address space 320 in FIGs. 3 A-3C. The first part of the memory address space may be implemented as data array 325 in FIG. 3B. The register base window of a predetermined size may be implemented as register base window 318 in FIGs. 3B-3C. Therefore, detailed descriptions of the functions and compositions of these components in step 406 will not be repeated here.

[0067] At step 408, a first set of data in the primary memory is accessed via the first register file based on a first set of instruction. In some embodiments according to the present disclosure, the first set of data may be stored in the primary memory and associated with the first register file. The first set of instruction may be a set of load and store instructions found in RISC, which directs the microprocessor to access the first set of data via the first register file. It may also be instructions that may map the register file to the memory address space.

[0068] At step 410, the register base window may be moved to map a second register file with a second part of the memory address space. The second register file may be implemented as register file 316 in FIG. 3C. The second part of the memory address space may be implemented as data array 326 in FIG. 3C. Therefore, detailed descriptions of the functions and compositions of these components in step 410 will not be repeated here.

[0069] At step 412, a second set of data in the primary memory may be accessed via the second register file based on a second set of instruction. In some embodiments according to the present disclosure, like the first set of data, the second set of data may also be stored in the primary memory and associated with the second register file. The second set of instruction may or may not be the same as the first set of instruction. However, since the addresses of the two sets of data differ, the second set of instruction should be able to direct the microprocessor to access data at a different location in the primary memory. [0070] At step 414, a maximum ratio may be set between the aggregated amount of data associated with the one or more register files and the total storage capacity of the primary memory. The maximum ratio is similar to the maximum proportion between the aggregated number of memory cells and the total storage capacity of the primary memory, as discussed above. Similarly, the maximum ration may be set at 0.5.

[0071] The hardware and software data processing technology disclosed herein, such as microcontroller chip 100 in FIG. 1 and method 400 in FIG. 4, may be implemented by any suitable nodes in a wireless network. For example, FIG. 5 illustrates an exemplary wireless network 500, in which certain aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure.

[0072] As shown in FIG. 5, wireless network 500 may include a network of nodes, such as a user equipment (UE) 502, an access node 504, and a core network element 506. User equipment 502 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Intemet-of-Things (loT) node. It is understood that user equipment 502 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0073] Access node 504 may be a device that communicates with user equipment 502, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 504 may have a wired connection to user equipment 502, a wireless connection to user equipment 502, or any combination thereof. Access node 504 may be connected to user equipment 502 by multiple connections, and user equipment 502 may be connected to other access nodes in addition to access node 504. Access node 504 may also be connected to other UEs. It is understood that access node 504 is illustrated by a radio tower by way of illustration and not by way of limitation.

[0074] Core network element 506 may serve access node 504 and user equipment 502 to provide core network services. Examples of core network element 506 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 506 includes an access and mobility management function (AMF) device, a session management function (SMF) device, or a user plane function (UPF) device, of a core network for the NR system. It is understood that core network element 506 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[0075] Core network element 506 may connect with a large network, such as the Internet 508, or another IP network, to communicate packet data over any distance. In this way, data from user equipment 502 may be communicated to other UEs connected to other access points, including, for example, a computer 510 connected to Internet 508, for example, using a wired connection or a wireless connection, or to a tablet 512 wirelessly connected to Internet 508 via a router 514. Thus, computer 510 and tablet 512 provide additional examples of possible UEs, and router 514 provides an example of another possible access node.

[0076] A generic example of a rack-mounted server is provided as an illustration of core network element 506. However, there may be multiple elements in the core network including database servers, such as a database 516, and security and authentication servers, such as an authentication server 518. Database 516 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 518 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the specific entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 506, authentication server 518, and database 516, may be local connections within a single rack.

[0077] Although the above-description used uplink and downlink processing of a packet in a user equipment as examples in various discussions, similar techniques may likewise be used for the other direction of processing and for processing in other devices, such as access nodes, and core network nodes. For example, any device that processes packets through a plurality of layers of a protocol stack may benefit certain embodiments of the present disclosure, even if not specifically listed above or illustrated in the example network of FIG. 5.

[0078] Each of the elements of FIG. 5 may be considered a node of wireless network 500. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 600 in FIG. 6 below. Node 600 may be configured as user equipment 502 or any other wireless communication device explicitly or implicitly disclosed in FIG. 5.

[0079] As shown in FIG. 6, node 600 may include a processor 602, a memory 604, a transceiver 606, and a user interface 608. These components are shown as connected to one another by bus 620, but other connection types are also permitted. When node 600 is user equipment 502, additional components may also be included, such as sensors and the like. Similarly, node 600 may be implemented as computer 510 or tablet 512 which are cable of transmitting data via wireless communication networks. Other implementations are also possible.

[0080] User interface 608 may include any suitable device for receiving user instructions. User instructions may be input in various forms, such as by keyboard strokes, mouse clicks, display touches, voices, human gestures, eye movements, etc. Consequently, there are many user input devices that can be compatible with one or more of the abovementioned forms of input, such as keyboard, mouse, touch panel, microphone, etc, Device output may also be in various forms, such as images (motion and still), sound, data, etc. Therefore, various output devices can be used as user interface 608, such as display, speaker, headphone, etc.

[0081] Transceiver 606 may include any suitable device for sending and/or receiving data. Data received via wireless communication networks may be referred to herein as wireless data. Node 600 may include one or more transceivers, although only one transceiver 606 is shown for simplicity of illustration. An antenna 610 is shown as a possible communication mechanism for node 600. Multiple antennas and/or arrays of antennas may be utilized. Additionally, examples of node 600 may also communicate using wired techniques in addition to wireless techniques. For example, computer 510 may communicate both by a wireless connection (for example, Wi-Fi) and by a wired connection (for example, by optical or coaxial cable) to Internet 508. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0082] As shown in FIG. 6, node 600 may also include memory 604. Although only one memory is shown, it is understood that multiple memories can be included. Memory 604 can broadly include both memory and storage. For example, memory 604 may include randomaccess memory (RAM), read-only memory (ROM), SRAM, dynamic RAM (DRAM), ferroelectric RAM (FRAM), electrically erasable programmable ROM (EEPROM), CD-ROM or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 602. Broadly, memory 604 may be embodied by any computer- readable medium, such as a non-transitory computer-readable medium. In particular, memory 604 may be implemented as secondary memory 10 as described above, the detail of which will not be repeated here.

[0083] As shown in FIG. 6, node 600 may include processor 602. Although only one processor is shown, it is understood that multiple processors can be included. Processor 602 may include microprocessors, microcontrollers, DSPs, ASICs, field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 602 may be a hardware device having one or many processing cores. Processor 602 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. In particular, processor 602 may be implemented as microcontroller chip 100 as described above, the detail of which will not be repeated here.

[0084] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 600 in FIG. 6. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, DVD, and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer- readable media.

[0085] According to one aspect of the present disclosure, a microcontroller chip can include a microprocessor, a control unit, and a primary memory. The control unit can be configured to direct at least one set of instruction to the microprocessor. The microprocessor can be operatively coupled to the primary memory and the control unit. The microprocessor can be configured to map a first register file to a first part of a memory address space based on a register base window of a predetermined size. It can also be configured to access a first set of data in the primary memory via the first register file based on a first set of instruction.

[0086] In some embodiments, the microprocessor can further be configured to move the register base window to map a second register file to a second part of the memory address space. It can also be configured to access a second set of data in the primary memory via the second register file based on a second set of instruction.

[0087] In some embodiments, each register file can contain at least one address. The microprocessor can be further configured to access the data of each register file through at least one address of that register file.

[0088] In some embodiments, at least one address of each register file can correspond to a fixed data array in the memory address space.

[0089] In some embodiments, at least one address of each register file can correspond to a variable data array in the memory address space.

[0090] In some embodiments, the microcontroller chip can further include a plurality of registers that can form a register array operatively coupled to the microprocessor and the primary memory. The register array does not access the data being processed by the microprocessor.

[0091] In some embodiments, the microcontroller chip can further include an instruction decoder that can decode at least one set of instruction and provide the decoded instruction to the microprocessor.

[0092] In some embodiments, during context switch, no data is transported between the register array and the primary memory. [0093] In some embodiments, each register file can host a predetermined number of memory cells in the primary memory. The memory cells can be formed by static randomaccess memory.

[0094] In some embodiments, the register base window can be of a predetermined size w, and w = 2^Ak (k = 1, 2, . . . , n).

[0095] In some embodiments, the predetermined size of the register base window does not change when it is moved to associate with different register files.

[0096] In some embodiments, the register base window can be applied and moved by a control/status register (CSR).

[0097] In some embodiments, the CSR can include at least one of the following parameters: a parameter indicating the size of the register base window, and a parameter associated with the address of the register file.

[0098] In some embodiments, the one or more register files can be accessed through direct memory access.

[0099] According to another aspect of the present disclosure, a method for data processing can be implemented by a microcontroller chip. The method can include loading data into a primary memory of the microcontroller chip. The method can also include directing at least one set of instruction to a microprocessor of the microcontroller chip. The method can further include mapping a first register file to a first part of a memory address space based on a register base window of a predetermined size. The method can further include accessing a first set of data in the primary memory via the first register file based on a first set of instruction.

[0100] In some embodiments, the method can also include moving the register base window to map a second register file with a second part of the memory address space. The method can further include accessing a second set of data in the primary memory via the second register file based on a second set of instruction.

[0101] In some embodiments, each register file can contain at least one address. The data of each register file can be accessed through at least one address of that register file.

[0102] In some embodiments, at least one address of each register file can correspond to a fixed data array in the memory address space.

[0103] In some embodiments, at least one address of each register file can correspond to a variable data array in the memory address space. [0104] In some embodiments, the method can also include decoding the at least one set of instruction. The method can further include providing the decoded instruction to the microprocessor.

[0105] In some embodiments, during context switch, no data is transported between the register array and the primary memory. The register array can be formed by a plurality of registers and operatively coupled to the microprocessor and the primary memory.

[0106] In some embodiments, each register file can host a predetermined number of memory cells in the primary memory. The memory cells can be formed by static randomaccess memory.

[0107] In some embodiments, the register base window can be of a predetermined size w, and w = 2^Ak (k = 1, 2, . . . , n).

[0108] In some embodiments, the predetermined size of the register base window does not change when it is moved to associate with different register files.

[0109] In some embodiments, the register base window can be applied and moved by a control/status register (CSR).

[0110] In some embodiments, the CSR can include at least one of the following parameters: a parameter indicating the size of the register base window, and a parameter associated with the address of the register file.

[OHl] In some embodiments, the one or more register files can be accessed through direct memory access.

[0112] In some embodiments, the method can also include setting a maximum ratio between the aggregated amount of data associated with the one or more register files and the total storage capacity of the primary memory.

[0113] According to a further aspect of the present disclosure, a wireless communication device can include a user interface configured to receive user instructions, a transceiver configured to send and receive wireless data via wireless communication networks, a memory configured to store the wireless data and the user instructions, and a processor, implemented as a microcontroller chip, configured to process the wireless data based upon the user instructions. The microcontroller chip can include a microprocessor, a control unit, and a primary memory. The control unit can be configured to direct at least one set of instruction to the microprocessor. The microprocessor can be operatively coupled to the primary memory and the control unit. The microprocessor can be configured to map a first register file to a first part of a memory address space based on a register base window of a predetermined size. It can also be configured to access a first set of data in the primary memory via the first register file based on a first set of instruction.

[0114] In some embodiments, the microprocessor can further be configured to move the register base window to map a second register file to a second part of the memory address space. It can also be configured to access a second set of data in the primary memory via the second register file based on a second set of instruction.

[0115] In some embodiments, each register file can contain at least one address. The microprocessor can be further configured to access the data of each register file through at least one address of that register file.

[0116] In some embodiments, the microcontroller chip can further include a plurality of registers that can form a register array operatively coupled to the microprocessor and the primary memory. The register array does not access the data being processed by the microprocessor.

[0117] In some embodiments, the register base window can be of a predetermined size w, and w = 2^Ak (k = 1, 2, . . . , n).

[0118] According to yet another aspect of the present disclosure, a non-transitoiy computer-readable medium may encode instructions that, when executed by a microcontroller chip, perform a process for data processing. The process may include loading data into a primary memory of the microcontroller chip. The method can also include directing at least one set of instruction to a microprocessor of the microcontroller chip. The method can further include mapping a first register file to a first part of a memory address space based on a register base window of a predetermined size. The method can further include accessing a first set of data in the primary memory via the first register file based on a first set of instruction.

[0119] The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0120] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0121] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0122] Various functional blocks, modules, and steps are disclosed above. The particular arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted.

[0123] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

- 28 - WHAT IS CLAIMED IS:

1. A microcontroller chip, comprising: a microprocessor; a control unit configured to direct at least one set of instruction to the microprocessor; and a primary memory configured to store data; wherein the microprocessor is operatively coupled to the primary memory and the control unit and configured to: map a first register file to a first part of a memory address space based on a register base window of a predetermined size; and access a first set of data in the primary memory via the first register file based on a first set of instruction.

2. The microcontroller chip of claim 1, wherein the microprocessor is further configured to move the register base window to map a second register file to a second part of the memory address space; and access a second set of data in the primary memory via the second register file based on a second set of instruction.

3. The microcontroller chip of any of claims 1-2, wherein each register file contains at least one address; and wherein the microprocessor is configured to access the data of each register file through the at least one address of that register file.

4. The microcontroller chip of claim 3, wherein the at least one address of each register file corresponds to a fixed data array in the memory address space.

5. The microcontroller chip of claim 3, wherein the at least one address of each register file corresponds to a variable data array in the memory address space.

6. The microcontroller chip of any of claims 1-5, further comprising: a plurality of registers that form a register array operatively coupled to the microprocessor and the primary memory; wherein the register array does not access the data being processed by the microprocessor.

7. The microcontroller chip of any of claims 1-6, further comprising: an instruction decoder that decodes the at least one set of instruction and provides the decoded instruction to the microprocessor.

8. The microcontroller chip of any of claims 6-7, wherein, during context switch, no data is transported between the register array and the primary memory.

9. The microcontroller chip of any of claims 1-8, wherein each register file hosts a predetermined number of memory cells in the primary memory; and wherein the memory cells are formed by static random-access memory.

10. The microcontroller chip of any of claims 1-9, wherein the register base window is of a predetermined size w; and wherein w = 2^k (k = 1, 2, . . . , n).

11. The microcontroller chip of claim 10, wherein the predetermined size of the register base window does not change when it is moved to associate with different register files.

12. The microcontroller chip of claim 2-11, wherein the register base window is applied and moved by a control/ status register (CSR).

13. The microcontroller chip of claim 12, wherein the CSR comprises at least one of the following parameters: a parameter indicating the size of the register base window; and a parameter associated with the address of the register file.

14. The microcontroller chip of any of claims 1-13, wherein the one or more register files are accessed through direct memory access.

15. A method implemented by a microcontroller chip for data processing, comprising: loading data into a primary memory of the microcontroller chip; directing at least one set of instruction to a microprocessor of the microcontroller chip; mapping a first register file to a first part of a memory address space based on a register base window of a predetermined size; and accessing a first set of data in the primary memory via the first register file based on a first set of instruction.

16. The method of claim 15, further comprising: moving the register base window to map a second register file with a second part of the memory address space; and accessing a second set of data in the primary memory via the second register file based on a second set of instruction.

17. The method of any of claims 15-16, wherein each register file contains at least one address; and wherein accessing the data of each register file is through the at least one address of that register file.

18. The method of claim 17, wherein the at least one address of each register file corresponds to a fixed data array in the memory address space.

19. The method of claim 17, wherein the at least one address of each register file corresponds to a variable data array in the memory address space.

20. The method of any of claims 15-19, further comprising: decoding the at least one set of instruction; and providing the decoded instruction to the microprocessor.

21. The method of any of claims 19-20, wherein, during context switch, no data is transported between a register array and the primary memory; and wherein the register array is formed by a plurality of registers and operatively coupled to the microprocessor and the primary memory.

22. The method of any of claims 15-21, wherein each register file hosts a predetermined number of memory cells in the primary memory; and wherein the memory cells are formed by static random-access memory.

23. The method of any of claims 15-22, wherein the register base window is of a predetermined size w; and wherein w = 2^k (k = 1, 2, . . . , n).

24. The method of claim 23, wherein the predetermined size of the register base window does not change when being moved to associate with different register files.

25. The method of any of claims 16-24, wherein the register base window is applied and moved by a control/ status register (CSR).

26. The method of claim 25, wherein the CSR comprises at least one of the following parameters: a parameter indicating the size of the register base window; and a parameter associated with the address of the register file.

27. The method of any of claims 15-26, wherein the one or more register files are accessed through direct memory access.

28. The method of any of claims 16-27, further comprising: setting a maximum ratio between the aggregated amount of data associated with the one or more register files and the total storage capacity of the primary memory.

29. A wireless communication device, comprising: a user interface configured to receive user instructions; a transceiver configured to send and receive wireless data via wireless communication networks; a memory configured to store the wireless data and the user instructions; and a processor, implemented as a microcontroller chip, configured to process the wireless data based upon the user instructions; - 32 - wherein the microcontroller chip comprises: a microprocessor; a control unit configured to direct at least one set of instruction to the microprocessor; and a primary memory configured to store data; wherein the microprocessor is operatively coupled to the primary memory and the control unit and configured to: map a first register file to a first part of a memory address space based on a register base window of a predetermined size; and access a first set of data in the primary memory via the first register file based on a first set of instruction.

30. The wireless communication device of claim 29, wherein the microprocessor is further configured to move the register base window to map a second register file to a second part of the memory address space; and access a second set of data in the primary memory via the second register file based on a second set of instruction.

31. The wireless communication device of any of claims 29-30, wherein each register file contains at least one address; and wherein the microprocessor is configured to access the data of each register file through the at least one address of that register file.

32. The wireless communication device of any of claims 29-31, wherein the microcontroller chip further comprises a plurality of registers that form a register array operatively coupled to the microprocessor and the primary memory; and wherein the register array does not access the data being processed by the microprocessor.

33. The wireless communication device of any of claims 29-32, wherein the register base window is of a predetermined size w; and wherein w = 2^k (k = 1, 2, . . . , n). - 33 -

34. A non-transitory computer-readable medium encoding instructions that, when executed by a microcontroller chip, perform a process for data processing, the process comprising: loading data into a primary memory of the microcontroller chip; directing at least one set of instruction to a microprocessor of the microcontroller chip; mapping a first register file to a first part of a memory address space based on a register base window of a predetermined size; and accessing a first set of data in the primary memory via the first register file based on a first set of instruction.