WO2022055004A1

WO2022055004A1 - Transmission interface device and signal processing device including same

Info

Publication number: WO2022055004A1
Application number: PCT/KR2020/012382
Authority: WO
Inventors: 박영길
Original assignee: 엘지전자 주식회사
Priority date: 2020-09-14
Filing date: 2020-09-14
Publication date: 2022-03-17

Abstract

The present invention relates to a transmission interface device and a signal processing device including same. A transmission interface device according to an embodiment of the present invention comprises: a random number generator which generates a random number; a first switch which operates on the basis of a random number from the random number generator; a flip flop which operates on the basis of an output signal from the first switch; and a second switch which operates on the basis of an output signal from the flip flop, and an input first valid signal, and outputs a second valid signal, wherein input data is bypassed and then output. Therefore, the device can detect a reconvergence glitch at the time of non-synchronous data transmission.

Description

Transmission interface device and signal processing device having same

The present invention relates to a transmission interface apparatus and a signal processing apparatus having the same, and more particularly, to a transmission interface apparatus capable of detecting a reconvergence glitch in asynchronous data transmission, and a signal processing apparatus having the same.

A signal processing device is a device for processing a signal, and is a hardware device in which various types of circuit elements are integrated.

Meanwhile, when designing the first circuit and the second circuit inside the signal processing apparatus, the clock signal of the first circuit and the clock signal of the second circuit may be asynchronous, and in the second circuit, the clock signal of the first circuit To synchronize the desynchronization, a synchronization processing circuit is used.

A synchronization processing circuit according to the prior art includes a plurality of flip-flops and a switch.

According to the synchronization processing circuit according to the prior art, since a delay of one clock difference is generated for every clock for synchronization processing, data loss occurs during transmission of gray multi-bits.

In addition, there is a disadvantage in that it does not properly detect a reconvergence glitch.

It is an object of the present invention to provide a transmission interface device capable of detecting a reconvergence glitch during asynchronous data transmission and a signal processing device having the same.

On the other hand, another object of the present invention is to provide a transmission interface device capable of detecting a reconvergence glitch during asynchronous data transmission at a register transistor level (Register Transfer Level), and a signal processing device having the same.

Meanwhile, another object of the present invention is to provide a transmission interface device capable of bypassing data during asynchronous data transmission and changing a valid signal or a ready signal, and a signal processing device having the same.

A transmission interface apparatus and a signal processing apparatus having the same according to an embodiment of the present invention for achieving the above object include a random number generator for generating a random number, and a first operating system based on the random number from the random number generator. a first switch, a flip-flop operating based on an output signal from the first switch, an output signal from the flip-flop, and an input first valid signal, and outputting a second valid signal; A second switch is included, and input data is output by bypassing it.

Meanwhile, the second valid signal output from the second switch may be varied for each clock cycle unit.

Meanwhile, the random number generator may generate a variable random number for each clock cycle unit.

Meanwhile, the random number generator may generate a variable random number for each clock cycle unit by varying the start value in units of clock cycles.

On the other hand, based on the second valid signal further comprises a logic element for outputting a first ready signal, the logic element, based on the input second ready signal and the second valid signal, output the first ready signal can do.

On the other hand, according to the variation of the clock cycle unit of the second valid signal, the first ready signal may be varied for each clock cycle unit.

A signal processing apparatus according to an embodiment of the present invention for achieving the above object includes a first circuit that operates based on a first clock signal and transmits data, and a second clock signal different from the first clock signal and a second circuit for receiving data from the first circuit, and a transmission interface device, the transmission interface device being disposed between the first circuit and the second circuit.

Meanwhile, the first circuit may output the first valid signal and receive the first ready signal, and the second circuit may receive the second valid signal and output the second ready signal.

Meanwhile, the transmission interface device may vary at least one of the second valid signal and the second ready signal for each clock cycle unit.

Meanwhile, the second circuit may include a synchronization processor for synchronizing input data.

Meanwhile, the synchronization processing unit includes a first flip-flop, a third switch connected to an output terminal of the first flip-flop, a second flip-flop connected to an output terminal of the third switch, and a second flip-flop connected to an output terminal of the second flip-flop. and a third flip-flop, and a fourth switch connected between an output terminal of the second flip-flop and an input terminal of the second flip-flop.

Meanwhile, the second circuit may further include a memory, and the synchronization processing unit may delay the update of the address address of the memory based on the variation of the second valid signal for each clock cycle unit.

Meanwhile, the synchronization processing unit may randomly delay the output of data based on the second clock signal based on the variation of the second valid signal for each clock cycle unit.

A signal processing apparatus according to another embodiment of the present invention for achieving the above object includes a first circuit that operates based on a first clock signal and transmits data, and a second clock signal different from the first clock signal and a second circuit for receiving data from the first circuit, wherein the transmission interface device is disposed in the first circuit and transmits at least one of a second valid signal or a second ready signal, every clock cycle can be variable.

Meanwhile, the first circuit may further include a circuit core, a middle interface device, and a second transmission interface device disposed between the circuit core and the middle interface device.

A transmission interface apparatus and a signal processing apparatus having the same according to an embodiment of the present invention include a random number generator for generating a random number, a first switch operating based on the random number from the random number generator, and a first a flip-flop operating based on an output signal from the switch; and a second switch operating based on an output signal from the flip-flop and an input first valid signal and outputting a second valid signal; , the input data is bypassed and output. Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission. In particular, it is possible to detect a reconvergence glitch during asynchronous data transfer at the register transistor level. In addition, it is possible to bypass the data during asynchronous data transmission and change the valid signal or the ready signal.

Meanwhile, the second valid signal output from the second switch may be varied for each clock cycle unit. Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission.

Meanwhile, the random number generator may generate a variable random number for each clock cycle unit. Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission.

Meanwhile, the random number generator may generate a variable random number for each clock cycle unit by varying the start value in units of clock cycles. Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission.

On the other hand, based on the second valid signal further comprises a logic element for outputting a first ready signal, the logic element, based on the input second ready signal and the second valid signal, output the first ready signal can do. Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission.

On the other hand, according to the variation of the clock cycle unit of the second valid signal, the first ready signal may be varied for each clock cycle unit. Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission.

Meanwhile, the signal processing apparatus according to an embodiment of the present invention operates based on a first clock signal and operates based on a first circuit for transmitting data and a second clock signal different from the first clock signal, A second circuit for receiving data from the first circuit, and a transmission interface device, the transmission interface device being disposed between the first circuit and the second circuit. Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission. In particular, it is possible to detect a reconvergence glitch during asynchronous data transfer at the register transistor level. In addition, it is possible to bypass the data during asynchronous data transmission and change the valid signal or the ready signal.

Meanwhile, the first circuit may output the first valid signal and receive the first ready signal, and the second circuit may receive the second valid signal and output the second ready signal. Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission.

Meanwhile, the transmission interface device may vary at least one of the second valid signal and the second ready signal for each clock cycle unit. Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission.

Meanwhile, the second circuit may include a synchronization processor for synchronizing input data. Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission.

Meanwhile, the synchronization processing unit includes a first flip-flop, a third switch connected to an output terminal of the first flip-flop, a second flip-flop connected to an output terminal of the third switch, and a second flip-flop connected to an output terminal of the second flip-flop. and a third flip-flop, and a fourth switch connected between an output terminal of the second flip-flop and an input terminal of the second flip-flop. Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission.

Meanwhile, the second circuit may further include a memory, and the synchronization processing unit may delay the update of the address address of the memory based on the variation of the second valid signal for each clock cycle unit. Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission.

Meanwhile, the synchronization processing unit may randomly delay the output of data based on the second clock signal based on the variation of the second valid signal for each clock cycle unit. Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission.

On the other hand, the signal processing apparatus according to another embodiment of the present invention operates based on a first clock signal, a first circuit for transmitting data, and a second clock signal different from the first clock signal, A second circuit for receiving data from the first circuit, the transmission interface device being disposed in the first circuit, at least one of the second valid signal and the second ready signal may be varied in units of clock cycles . Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission. In particular, it is possible to detect a reconvergence glitch during asynchronous data transfer at the register transistor level. In addition, it is possible to bypass the data during asynchronous data transmission and change the valid signal or the ready signal.

Meanwhile, the first circuit may further include a circuit core, a middle interface device, and a second transmission interface device disposed between the circuit core and the middle interface device. Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission.

1 is a diagram illustrating an image display device according to an embodiment of the present invention.

FIG. 2 is an example of an internal block diagram of the image display device of FIG. 1 .

FIG. 3 is an example of an internal block diagram of the signal processing unit of FIG. 2 .

4 is a diagram illustrating a first circuit and a second circuit in a signal processing apparatus according to an embodiment of the present invention.

5 is an example of an internal block diagram of a signal processing apparatus according to an embodiment of the present invention.

6 is an example of an internal circuit diagram of a transmission interface device according to an embodiment of the present invention.

7A is another example of an internal block diagram of a signal processing apparatus according to an embodiment of the present invention.

7B is an example of an internal circuit diagram of the synchronization processing unit of FIG. 7A .

8A and 8B are diagrams referred to in the description of the signal processing apparatus related to the present invention.

9 is another example of an internal block diagram of a signal processing apparatus according to an embodiment of the present invention.

10 is another example of an internal block diagram of a signal processing apparatus according to an embodiment of the present invention.

11 to 13 are diagrams referenced in the description of FIGS. 6 to 10 .

Hereinafter, the present invention will be described in more detail with reference to the drawings.

The suffixes "module" and "part" for the components used in the following description are given simply in consideration of the ease of writing the present specification, and do not impart a particularly important meaning or role by themselves. Accordingly, the terms “module” and “unit” may be used interchangeably.

Referring to the drawings, the image display apparatus 100 may include a display 180 .

The image display apparatus 100 may receive image signals from various external devices, process them, and display them on the display 180 .

Various external devices may be, for example, a computer (PC), a mobile terminal 600 such as a smart phone, a set-top box (STB), a game console (GSB), a server (SVR), and the like.

Meanwhile, the display 180 may be implemented as any one of various panels. For example, the display 180 may be any one of self-luminous panels such as an organic light emitting panel (OLED panel), an inorganic light emitting panel (LED panel), and a micro LED panel.

Meanwhile, the image display device 100 of FIG. 1 may be a TV, a monitor, a tablet PC, a mobile terminal, a vehicle display device, and the like.

Referring to FIG. 2 , an image display device 100 according to an embodiment of the present invention includes an image receiving unit 105 , an external device interface unit 130 , a storage unit 140 , a user input interface unit 150 , It may include a sensor unit (not shown), a signal processing unit 170 , a display 180 , and an audio output unit 185 .

The image receiver 105 may include a tuner unit 110 , a demodulator unit 120 , a network interface unit 130 , and an external device interface unit 130 .

Meanwhile, the image receiving unit 105 may include only the tuner unit 110 , the demodulator 120 , and the external device interface unit 130 , unlike the drawing. That is, the network interface unit 130 may not be included.

The tuner unit 110 selects an RF broadcast signal corresponding to a channel selected by a user or all channels previously stored among RF (Radio Frequency) broadcast signals received through an antenna (not shown). In addition, the selected RF broadcast signal is converted into an intermediate frequency signal or a baseband video or audio signal.

Meanwhile, the tuner unit 110 may include a plurality of tuners in order to receive broadcast signals of a plurality of channels. Alternatively, a single tuner that simultaneously receives broadcast signals of a plurality of channels is also possible.

The demodulator 120 receives the digital IF signal DIF converted by the tuner 110 and performs a demodulation operation.

The demodulator 120 may output a stream signal TS after demodulation and channel decoding are performed. In this case, the stream signal may be a signal obtained by multiplexing an image signal, an audio signal, or a data signal.

The stream signal output from the demodulator 120 may be input to the signal processing unit 170 . The signal processing unit 170 outputs an image to the display 180 after performing demultiplexing, image/audio signal processing, and the like, and outputs an audio to the audio output unit 185 .

The external device interface unit 130 may transmit or receive data with a connected external device (not shown), for example, a set-top box (STB). To this end, the external device interface unit 130 may include an A/V input/output unit (not shown).

The external device interface unit 130 may be connected to an external device such as a DVD (Digital Versatile Disk), Blu-ray, game device, camera, camcorder, computer (laptop), set-top box, and the like by wire/wireless, , it is also possible to perform input/output operations with an external device.

The A/V input/output unit may receive video and audio signals from an external device. Meanwhile, the wireless communication unit (not shown) may perform short-range wireless communication with other electronic devices.

Through such a wireless communication unit (not shown), the external device interface unit 130 may exchange data with the adjacent mobile terminal 600 . In particular, the external device interface unit 130 may receive device information, executed application information, an application image, and the like, from the mobile terminal 600 in the mirroring mode.

The network interface unit 135 provides an interface for connecting the image display device 100 to a wired/wireless network including an Internet network. For example, the network interface unit 135 may receive content or data provided by the Internet or a content provider or network operator through a network.

Meanwhile, the network interface unit 135 may include a wireless communication unit (not shown).

The storage unit 140 may store a program for processing and controlling each signal in the signal processing unit 170 , or may store a signal-processed image, audio, or data signal.

Also, the storage unit 140 may perform a function for temporarily storing an image, audio, or data signal input to the external device interface unit 130 . Also, the storage unit 140 may store information about a predetermined broadcast channel through a channel storage function such as a channel map.

Although the embodiment in which the storage unit 140 of FIG. 2 is provided separately from the signal processing unit 170 is illustrated, the scope of the present invention is not limited thereto. The storage unit 140 may be included in the signal processing unit 170 .

The user input interface unit 150 transmits a signal input by the user to the signal processing unit 170 or transmits a signal from the signal processing unit 170 to the user.

For example, transmit/receive user input signals such as power on/off, channel selection, and screen setting from the remote control device 200, or local keys (not shown) such as power key, channel key, volume key, and setting value transmits a user input signal input to the signal processing unit 170 , or transmits a user input signal input from a sensor unit (not shown) for sensing a user's gesture to the signal processing unit 170 , or from the signal processing unit 170 . may be transmitted to the sensor unit (not shown).

The signal processing unit 170 demultiplexes an input stream or processes the demultiplexed signals through the tuner unit 110 or the demodulator 120 , the network interface unit 135 or the external device interface unit 130 . Thus, it is possible to generate and output a signal for video or audio output.

For example, the signal processing unit 170 receives the broadcast signal or HDMI signal received from the image receiving unit 105 , and performs signal processing based on the received broadcast signal or HDMI signal to receive the signal-processed image signal. can be printed

The image signal processed by the signal processing unit 170 may be input to the display 180 and displayed as an image corresponding to the image signal. Also, the image signal processed by the signal processing unit 170 may be input to an external output device through the external device interface unit 130 .

The audio signal processed by the signal processing unit 170 may be outputted to the audio output unit 185 . Also, the audio signal processed by the signal processing unit 170 may be input to an external output device through the external device interface unit 130 .

Although not shown in FIG. 2 , the signal processing unit 170 may include a demultiplexer, an image processing unit, and the like. That is, the signal processing unit 170 may perform various signal processing, and thus may be implemented in the form of a system on chip (SOC). This will be described later with reference to FIG. 3 .

In addition, the signal processing unit 170 may control overall operations in the image display apparatus 100 . For example, the signal processing unit 170 may control the tuner unit 110 to select (tuning) a channel selected by the user or an RF broadcast corresponding to a pre-stored channel.

Also, the signal processing unit 170 may control the image display apparatus 100 according to a user command input through the user input interface unit 150 or an internal program.

Meanwhile, the signal processing unit 170 may control the display 180 to display an image. In this case, the image displayed on the display 180 may be a still image or a moving image, and may be a 2D image or a 3D image.

Meanwhile, the signal processing unit 170 may cause a predetermined object to be displayed in the image displayed on the display 180 . For example, the object may be at least one of an accessed web screen (newspaper, magazine, etc.), an Electronic Program Guide (EPG), various menus, widgets, icons, still images, moving pictures, and text.

Meanwhile, the signal processing unit 170 may recognize the location of the user based on the image captured by the photographing unit (not shown). For example, the distance (z-axis coordinate) between the user and the image display apparatus 100 may be determined. In addition, an x-axis coordinate and a y-axis coordinate in the display 180 corresponding to the user's location may be identified.

The display 180 converts an image signal, a data signal, an OSD signal, a control signal, or an image signal, a data signal, and a control signal received from the external device interface unit 130 processed by the signal processing unit 170 to a driving signal to create

Meanwhile, the display 180 may be configured as a touch screen and used as an input device in addition to an output device.

The audio output unit 185 receives the audio signal processed by the signal processing unit 170 and outputs the audio signal.

The photographing unit (not shown) photographs the user. The photographing unit (not shown) may be implemented with one camera, but is not limited thereto, and may be implemented with a plurality of cameras. Image information captured by the photographing unit (not shown) may be input to the signal processing unit 170 .

The signal processing unit 170 may detect a user's gesture based on each or a combination of an image captured by a photographing unit (not shown) or a signal sensed from a sensor unit (not shown).

The power supply unit 190 supplies the corresponding power to the entire image display device 100 . In particular, the power supply unit 190 includes a signal processing unit 170 that may be implemented in the form of a system on chip (SOC), a display 180 for displaying an image, and an audio output unit for outputting audio (185), etc. can be supplied with power.

Specifically, the power supply unit 190 may include a converter that converts AC power into DC power, and a dc/dc converter that converts the level of DC power.

The remote control device 200 transmits a user input to the user input interface unit 150 . To this end, the remote control device 200 may use Bluetooth (Bluetooth), Radio Frequency (RF) communication, infrared (IR) communication, Ultra Wideband (UWB), ZigBee, or the like. In addition, the remote control device 200 may receive an image, audio, or data signal output from the user input interface unit 150 , and display it or output the audio signal from the remote control device 200 .

Meanwhile, the above-described image display device 100 may be a digital broadcasting receiver capable of receiving fixed or mobile digital broadcasting.

Meanwhile, the block diagram of the image display device 100 shown in FIG. 2 is a block diagram for an embodiment of the present invention. Each component of the block diagram may be integrated, added, or omitted according to the specifications of the image display device 100 that are actually implemented. That is, two or more components may be combined into one component, or one component may be subdivided into two or more components as needed. In addition, the function performed by each block is for explaining the embodiment of the present invention, and the specific operation or device does not limit the scope of the present invention.

Referring to the drawings, the signal processing unit 170 according to an embodiment of the present invention may include a demultiplexer 310 , an image processing unit 320 , a processor 330 , and an audio processing unit 370 . . In addition, it may further include a data processing unit (not shown).

The demultiplexer 310 demultiplexes an input stream. For example, when MPEG-2 TS is input, it can be demultiplexed and separated into video, audio and data signals, respectively. Here, the stream signal input to the demultiplexer 310 may be a stream signal output from the tuner unit 110 , the demodulator 120 , or the external device interface unit 130 .

The image processing unit 320 may perform signal processing on an input image. For example, the image processing unit 320 may perform image processing on the image signal demultiplexed by the demultiplexer 310 .

To this end, the image processing unit 320 includes an image decoder 325 , a scaler 335 , an image quality processing unit 635 , an image encoder (not shown), an OSD processing unit 340 , a frame rate converter 350 , and a formatter. (360) and the like.

The image decoder 325 decodes the demultiplexed image signal, and the scaler 335 performs scaling to output the resolution of the decoded image signal on the display 180 .

The video decoder 325 may include decoders of various standards. For example, it may include an MPEG-2, H,264 decoder, a 3D image decoder for a color image and a depth image, a decoder for a multi-view image, and the like.

The scaler 335 may scale an input image signal that has been decoded by the image decoder 325 or the like.

For example, the scaler 335 may upscale when the size or resolution of the input image signal is small, and downscale when the size or resolution of the input image signal is large.

The image quality processing unit 635 may perform image quality processing on an input image signal that has been decoded by the image decoder 325 or the like.

For example, the image quality processing unit 635 performs noise removal processing on the input image signal, expands the resolution of the gray scale of the input image signal, improves image resolution, or performs high dynamic range (HDR)-based signal processing. , the frame rate can be varied, and panel characteristics, in particular, image quality processing corresponding to the organic light emitting panel can be performed.

The OSD processing unit 340 generates an OSD signal according to a user input or by itself. For example, a signal for displaying various types of information as graphics or text on the screen of the display 180 may be generated based on a user input signal. The generated OSD signal may include various data such as a user interface screen of the image display device 100 , various menu screens, widgets, and icons. Also, the generated OSD signal may include a 2D object or a 3D object.

Also, the OSD processing unit 340 may generate a pointer that can be displayed on a display based on a pointing signal input from the remote control device 200 . In particular, such a pointer may be generated by a pointing signal processing unit, and the OSD processing unit 240 may include such a pointing signal processing unit (not shown). Of course, the pointing signal processing unit (not shown) may be provided separately instead of being provided in the OSD processing unit 240 .

A frame rate converter (FRC) 350 may convert a frame rate of an input image. On the other hand, the frame rate converter 350 may output as it is without a separate frame rate conversion.

Meanwhile, the formatter 360 may change the format of an input image signal into an image signal for display on a display and output the changed format.

In particular, the formatter 360 may change the format of the image signal to correspond to the display panel.

The processor 330 may control overall operations in the image display device 100 or in the signal processing unit 170 .

For example, the processor 330 may control the tuner unit 110 to select a channel selected by the user or an RF broadcast corresponding to a pre-stored channel (tuning).

Also, the processor 330 may control the image display apparatus 100 according to a user command input through the user input interface unit 150 or an internal program.

In addition, the processor 330 may perform data transmission control with the network interface unit 135 or the external device interface unit 130 .

Also, the processor 330 may control operations of the demultiplexer 310 and the image processor 320 in the signal processor 170 .

Meanwhile, the audio processing unit 370 in the signal processing unit 170 may perform audio processing of the demultiplexed audio signal. To this end, the audio processing unit 370 may include various decoders.

In addition, the audio processing unit 370 in the signal processing unit 170 may process a base (Base), a treble (Treble), volume control, and the like.

A data processing unit (not shown) in the signal processing unit 170 may perform data processing of the demultiplexed data signal. For example, when the demultiplexed data signal is an encoded data signal, it may be decoded. The encoded data signal may be electronic program guide information including broadcast information such as start time and end time of a broadcast program aired on each channel.

Meanwhile, a block diagram of the signal processing unit 170 shown in FIG. 3 is a block diagram for an embodiment of the present invention. Each component of the block diagram may be integrated, added, or omitted according to the specifications of the signal processing unit 170 that are actually implemented.

In particular, the frame rate converter 350 and the formatter 360 may be separately provided in addition to the image processor 320 .

Referring to the drawings, the signal processing apparatus 170 according to an embodiment of the present invention implemented in the form of a system on chip (SOC) operates based on a first clock signal and transmits data. It includes a first circuit 410 , a second circuit 420 that operates based on a second clock signal different from the first clock signal, and receives data from the first circuit 410 , and a transmission interface device 920 . can do.

When the first circuit 410 and the second circuit 420 operate with different clock signals, it is necessary to synchronize the asynchronous processing timing.

In particular, when the signal processing apparatus 170 is designed at the register transistor level, error checking may be performed by the verification apparatus for RTL simulation.

Meanwhile, the verification apparatus for RTL simulation may be included in the signal processing apparatus 170a of FIG. 5 .

Referring to the drawings, the signal processing apparatus 170a according to an embodiment of the present invention includes a first circuit 410a that operates based on a first clock signal and transmits data, and a second circuit 410a that is different from the first clock signal. A second circuit 420a that operates based on a clock signal and receives data from the first circuit 410a, and a transmission interface device 920 disposed between the first circuit 410a and the second circuit 420a to provide

On the other hand, the first circuit 410a, outputs a first valid signal (mvalid), receives a first ready signal (mready), the second circuit 420a, the second valid signal (svalid) Receive and output a second ready signal (sready).

Meanwhile, the first circuit 410a may output a clock signal clk and data data.

The first valid signal mvalid and the clock signal clk output from the first circuit 410a are input to the transmission interface device 920, and the data output from the first circuit 410a is, By bypassing the transmission interface device 920 , it may be directly input to the second circuit 420a.

Meanwhile, the transmission interface device 920 may vary at least one of a second valid signal (svalid) and a second ready signal (sready) for each clock cycle unit.

Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission. In particular, it is possible to detect a reconvergence glitch during asynchronous data transfer at the register transistor level. In addition, it is possible to bypass the data during asynchronous data transmission and change the valid signal or the ready signal.

Meanwhile, since the first circuit 410a and the second circuit 420a operate at different clock frequencies, a delay may occur during data transmission, and a glitch may occur accordingly.

To this end, the second circuit 420a may include a synchronization processing unit ( 525 of FIG. 7B ) that synchronizes input data.

However, even if the second circuit 420a includes the synchronization processing unit 525, it is delayed only by +1 or -1 in units of the second clock cycle, and consequently, it cannot cope with various delays, resulting in a bug.

Accordingly, in the present invention, the synchronization processing unit 525 for data delay compensation is used as it is, and between the first circuit 410a and the second circuit 420a, a valid signal used for data transmission or reception or A transmission interface device 920 that varies the ready signal is used.

The transmission interface device 920 bypasses data, and variously varies a valid signal or a ready signal used for data transmission or reception using a random number, thereby reducing a reconvergence glitch during asynchronous data transmission. can be detected. In particular, it is possible to detect a reconvergence glitch during asynchronous data transfer at the register transistor level. In addition, it is possible to bypass the data during asynchronous data transmission and change the valid signal or the ready signal.

The transmission interface device 920 will be described in more detail with reference to FIG. 6 .

Referring to the drawings, a transmission interface device 920 according to an embodiment of the present invention includes a random number generator 710 for generating a random number, and a first operation based on the random number from the random number generator 710 . One switch 712 , a flip-flop 715 operating based on an output signal from the first switch 712 , an output signal from the flip-flop 715 , and an input first valid signal mvalid Based on , the second switch 718 may include a second switch 718 that operates and outputs a second valid signal svalid.

On the other hand, the transmission interface device 920 according to an embodiment of the present invention may bypass the input data and vary the input valid signal or the ready signal to output. Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission. In particular, it is possible to detect a reconvergence glitch during asynchronous data transfer at the register transistor level.

Meanwhile, the transmission interface device 920 may include an input valid terminal s_valid, an output valid terminal m_valid, an input ready terminal s_ready, and an output ready terminal m_ready.

On the other hand, the input valid terminal s_valid of the transmission interface device 920 receives the first valid signal mvalid from the first circuit 410a, and the output valid terminal m_valid of the transmission interface device 920 . may output the second valid signal svalid to the second circuit 420a.

On the other hand, the input ready terminal (s_ready) of the transmission interface device 920 receives a second ready signal (sready) from the second circuit 420a, the output ready terminal (m_ready) of the transmission interface device 920 is the first A first ready signal (mready) may be output to the circuit 410a.

Meanwhile, the random number generator 710 may generate a variable random number for each clock cycle unit.

Meanwhile, the random number generator 710 may generate a variable random number in units of clock cycles by varying the start value in units of clock cycles.

The random number generated by the random number generator 710 may be input to the first switch 712 .

On the other hand, a selection signal may be input to the first switch 712 , and when the level of the selection signal is a high level or '1', the first switch 712 generates a random number from the random number generator 710 . can be printed out.

Meanwhile, when the level of the selection signal is a low level or '0', the first switch 712 may output a bit signal that is not a random number from the random number generator 710 .

The flip-flop 715 may operate based on an output signal from the first switch 712 .

For example, when the flip-flop 715 receives a random number from the first switch 712 , the random number may be delayed.

As another example, when the flip-flop 715 receives the bit signal from the first switch 712 , the bit signal may be delayed.

Next, the second switch 718 may receive the output signal of the flip-flop 715 .

Meanwhile, the first valid signal mvalid may be input to the second switch 718 through the input valid terminal s_valid, and the level of the first valid signal mvalid is a high level or '1'. In the case of , the second switch 718 may output a signal based on the delayed random number. At this time, the output signal may correspond to the second valid signal (svalid).

Meanwhile, when the level of the first valid signal mvalid is a low level or '0', the second switch 718 may output a delayed bit signal.

Meanwhile, the second valid signal svalid output from the second switch 718 may be transmitted to the second circuit 420a through the output valid terminal m_valid.

Meanwhile, the transmission interface device 920 according to an embodiment of the present invention may further include a logic element 720 for outputting a first ready signal (mready) based on a second valid signal (svalid).

The second valid signal (svalid) output from the second switch 718 is input to the logic device 720 , and the logic device 720 includes the input second ready signal (sready) and the second valid signal. Based on (svalid), it is possible to output a first ready signal (mready).

On the other hand, according to the variation of the clock cycle unit of the second valid signal (svalid), the first ready signal (mready) may be varied for each clock cycle unit. Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission.

On the other hand, the second valid signal (svalid) output from the second switch 718 may vary for each clock cycle unit.

Referring to the drawings, a signal processing apparatus 170a1 according to an embodiment of the present invention includes a first circuit 410a1 operating based on a first clock signal and a second circuit 420a1 operating based on a second clock signal. ), a transmission interface device 920 separately disposed between the first circuit 410a1 and the second circuit 420a1 may be provided.

In this case, the transmission interface device 920 may operate based on the first clock signal.

The transmission interface device 920 of FIG. 7A may be the same as the description of FIG. 6 .

On the other hand, in the signal processing apparatus 170a1 according to an embodiment of the present invention, multi-bit transmission is possible between the first circuit 410a1 and the second circuit 420a1, and the second circuit 420a1 includes a FIFO memory ( 540) may be provided.

The memory 540 may store multi-bit data that is bypassed and input by the transmission interface device 920 .

Meanwhile, the second circuit 420a1 receives a second valid signal (svalid) or a push signal (push) received from the transmission interface device 920 to provide an interface for writing in the memory 540 . A write interface 522 that provides a write interface 522, a first comparator 524 that performs a comparison operation based on a signal from the write interface 522, and a read interface 532 that provides an interface for reading the memory 540 , a second comparator 534 for performing a comparison operation based on a signal from the read interface 532 , a read address processor 526 for processing a read address, and a synchronization processor 525 .

Meanwhile, the synchronization processing unit 525 may include a write address processor (not shown) for writing address processing therein.

The write interface 522 outputs a write address signal, and the write address signal may be input to the memory 540 and the read address processor 526 .

The read interface 532 outputs a read address signal, and the read address signal may be input to the memory 540 and the synchronization processing unit 525 .

On the other hand, according to the signal processing apparatus 170a1 of FIG. 7A , the second circuit 420a includes a memory 540 and a synchronization processing unit 525 , and the second valid signal svalid is variable for each clock cycle unit. Based on , output of data may be randomly delayed based on the second clock signal. Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission.

Referring to the drawing, on the other hand, the synchronization processing unit 525, the first flip-flop (FFa), the third switch 610 connected to the output terminal of the first flip-flop (FFa), and the third switch (610) The second flip-flop FFb connected to the output terminal, the third flip-flop FFc connected to the output terminal of the second flip-flop FFb, the output terminal of the second flip-flop FFb, and the second flip-flop FFb ) may include a fourth switch 620 connected between the input terminals.

Data may be input through the input terminal d_in and transferred to the first flip-flop FFa and the third switch 610 .

The clock signal input to the clock terminal clk may be transmitted to the first flip-flops FFa to the third flip-flops FFc.

The third switch 610 operates based on the input selection signal Srca, and the output signal output from the third switch 610 may be input to the second flip-flop FFb.

The output signal output from the second flip-flop FFb may be input to the third flip-flop FFc and the fourth switch 620 .

The output signal output from the third flip-flop FFc may be input to the fourth switch 620 .

The fourth switch 620 may selectively output an output signal output from the second flip-flop FFb or an output signal output from the third flip-flop FFc based on the input selection signal Srcb. there is.

In addition, the output signal output from the fourth switch 620 may be externally output through the output terminal d_out.

By the operation of the synchronization processing unit 525, the delay in units of the second clock cycle is possible.

First, FIG. 8A illustrates a signal processing apparatus 170x related to the present invention.

A first circuit 410x in the signal processing device 170x includes two flip-

flops

810 and 812 operated by a first clock signal Clk_A, and the second circuit 420x includes a second clock signal (Clk_A). Four flip-

flops

820, 822, 830, and 832 operated by Clk_b) may be provided.

Meanwhile, due to the delay factors 80a and 80b between the first circuit 410x and the second circuit 420x, a delay occurs when data is transmitted between the first circuit 410x and the second circuit 420x. .

FIG. 8B is a diagram illustrating each flip-flop operation waveform and clock signal of FIG. 8A.

Referring to the drawing, a signal delay occurs in the flip-

flops

820, 822, 830, and 832 in the second circuit 420x, and in particular, delays such as Ara and Arb in the drawing occur.

To resolve this delay, the synchronization processing unit 525 of FIG. 7B may be used. Furthermore, in the present invention, in spite of the operation of the synchronization processing unit 525 of FIG. 7B , the transmission interface device 920 as shown in FIG. 6 is used for the clock cycle-by-clock variation.

Referring to the drawings, a signal processing apparatus 170a2 according to an embodiment of the present invention includes a first circuit 410a2 operating based on a first clock signal and a second circuit 420a2 operating based on a second clock signal. ), a transmission interface device 920 separately disposed between the first circuit 410a2 and the second circuit 420a2 may be provided.

The transmission interface device 920 of FIG. 9 may be the same as the description of FIG. 6 .

Meanwhile, in the signal processing apparatus 170a2 according to an embodiment of the present invention, multi-bit transmission is possible between the first circuit 410a2 and the second circuit 420a2, and the second circuit 420a2 includes a data transmission unit. It may include a 560 and a data receiver 570 .

In addition, the data receiving unit 570 may include a handshake multi-bit synchronization processing unit 525b.

Meanwhile, the transmission interface device 920 may be disposed at the front end of the data transmission unit 560 .

The synchronization processing unit 525b may include two flip-flops, and data delay using them is possible.

Meanwhile, according to the signal processing apparatus 170a2, the output of data may be randomly delayed based on the second clock signal based on the variation of the second valid signal svalid for each clock cycle unit. Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission.

Referring to the drawings, a signal processing apparatus 170b according to an embodiment of the present invention includes a first circuit 410b operating based on a first clock signal and a second circuit 420b operating based on a second clock signal. ) can be provided.

Meanwhile, the first circuit 410b may include a circuit core 1110 and a transmission interface device 920a.

The circuit core 1110 may include a valid-ready protocol processor 1132 , and by the valid-ready protocol processor 1132 , a first valid signal (mvalid) is output, and a first ready signal (mready) ) can be entered.

On the other hand, the second circuit 420b, may include a valid-ready protocol processor 1130, by the valid-ready protocol processor 1130, a second valid signal (svalid) is input, the second ready A signal (ready) may be output.

The transmission interface device 920a may be disposed in the first circuit 410 to vary at least one of a second valid signal (svalid) and a second ready signal (sready) for each clock cycle unit. Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission. In particular, it is possible to detect a reconvergence glitch during asynchronous data transfer at the register transistor level. In addition, it is possible to bypass the data during asynchronous data transmission and change the valid signal or the ready signal.

Meanwhile, the second circuit 420b may further include a middle interface device 1140 .

Meanwhile, the first circuit 410 may further include a middle interface device 1120 and a second transmission interface device 920b disposed between the circuit core 1110 and the middle interface device 1120 . Accordingly, it is possible to detect a reconvergence glitch during asynchronous data transmission.

Meanwhile, the signal processing apparatus 170b according to an embodiment of the present invention may further include a third circuit 1150 for exchanging data with the first circuit 410b and the second circuit 420b.

In addition, the third circuit 1150 performs data exchange between the third transmission interface device 920c that varies a valid signal or a ready signal for data exchange with the first circuit 410b and the second circuit 420b. A fourth transmission interface device 920d for changing a valid signal or a ready signal for this purpose may be further included.

11 to 13 are diagrams referenced in the description of FIGS. 6 to 10 .

11 is another example of an internal block diagram of a signal processing apparatus according to an embodiment of the present invention.

Referring to the drawings, a signal processing apparatus 170m according to an embodiment of the present invention includes a first circuit 410m operating based on a first clock signal and a second circuit 420m operating based on a second clock signal. ), a transmission interface device 920 separately disposed between the first circuit 410m and the second circuit 420m may be provided.

Meanwhile, the first circuit 410m according to an embodiment of the present invention may be capable of multi-bit transmission, and the second circuit 420m may be capable of multi-bit reception.

The first circuit 410m may include a valid-ready protocol processor (not shown), and may output a first valid signal (mvalid) and receive a first ready signal (mready).

Meanwhile, the second circuit 420b may include a valid-ready protocol processor (not shown), may receive a second valid signal (svalid), and may output a second ready signal (sready).

Meanwhile, the transmission interface device 920 checks a bug based on a first valid signal (mvalid), a second valid signal (svalid), a first ready signal (mready), and a second ready signal (sready). can do.

For example, when only the first valid signal (mvalid) and the second valid signal (svalid) are input to the transmission interface device 920 without the first ready signal (mready) and the second ready signal (sready) , can be checked as a bug.

Meanwhile, the first circuit 410m may increase the count value according to the first clock signal.

On the other hand, in a general RTL simulation situation without the transmission interface device 920 , there is a case where the first ready signal (mready) is always 1'b1, and accordingly, a bug may not be checked.

In order to solve this problem, the signal processing device 170m according to the embodiment of the present invention utilizes the transmission interface device 920 .

Due to the transmission interface device 920, the output second valid signal (svalid) or the first ready signal (mready), etc. can be randomly shaken, so that a malfunction of the count value of the first circuit 410m can be checked be able to

12 is an example of an internal block diagram of the image quality processing unit 1300 in the signal processing apparatus.

Referring to the drawing, the image quality processing unit 1300 includes a first buffer 1310 , a first color processing unit 1315 connected to the first buffer 1310 , a second buffer 1320 , and a second buffer 1320 . A connected second color processing unit 1325 may be provided.

On the other hand, when a valid signal is input/output to the first buffer 1310 and the second buffer 1320 , and a ready signal is floated to the second buffer 1320 , that is, the second buffer 1320 is not connected. In this case, reconvergence may occur in the arm region.

13B is a diagram referred to in the description of FIG. 13A.

Referring to the drawings, (a) of FIG. 13B shows an example of an image 1350 displayed on the display 180 when there is no transmission interface device 920 in the signal processing device 170 .

As shown in (a) of FIG. 13B , when there is no transmission interface device 920 in the signal processing device 170 , reconvergence occurs, and eventually, a part of the image 1350 is shaken.

13B (b) illustrates an example of an image 1360 displayed on the display 180 when the transmission interface device 920 is provided in the signal processing device 170 .

As shown in (b) of FIG. 13B , even when the transmission interface device 920 is provided in the signal processing device 170 , reconvergence may occur, and eventually, a part of the image 1360 is shaken.

13B (c) illustrates another example of the image 1370 displayed on the display 180 when the transmission interface device 920 is provided in the signal processing device 170 .

As shown in (c) of FIG. 13B , when there is no transmission interface device 920 in the signal processing device 170 and reconvergence does not occur, the image 1370 is not shaken and is stably displayed.

In addition, although preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and the technical field to which the present invention belongs without departing from the gist of the present invention as claimed in the claims In addition, various modifications are possible by those of ordinary skill in the art, and these modifications should not be individually understood from the technical spirit or perspective of the present invention.

Claims

a random number generator for generating a random number;

a first switch operative based on the random number from the random number generator;

a flip-flop operating based on an output signal from the first switch;

a second switch operating based on an output signal from the flip-flop and an input first valid signal and outputting a second valid signal;

Transmission interface device, characterized in that the input data is output by bypassing it.
According to claim 1,

The second valid signal output from the second switch is variable for each clock cycle unit.
According to claim 1,

The random number generator is

Transmission interface device, characterized in that for generating the random number that varies for each clock cycle unit.
According to claim 1,

The random number generator is

The transmission interface device of claim 1, wherein the random number is generated by varying a start value in units of clock cycles, and is variable in units of clock cycles.
According to claim 1,

It further comprises a; logic element for outputting a first ready signal based on the second valid signal,

The logic element is

Based on the input second ready signal and the second valid signal, the transmission interface device, characterized in that for outputting the first ready signal.
6. The method of claim 5,

Transmission interface device, characterized in that according to the variation of the clock cycle unit of the second valid signal, the first ready signal is changed for each clock cycle unit.
A signal processing apparatus comprising a; the transmission interface device according to any one of claims 1 to 6.
8. The method of claim 7,

a first circuit operating based on a first clock signal and transmitting the data;

a second circuit that operates based on a second clock signal different from the first clock signal and receives the data from the first circuit;

and the transmission interface device is disposed between the first circuit and the second circuit.
8. The method of claim 7,

The first circuit is

Outputting the first valid signal, receiving a first ready signal,

The second circuit is

Signal processing apparatus, characterized in that receiving the second valid signal, and outputting a second ready signal.
10. The method of claim 9,

The transmission interface device,

At least one of the second valid signal and the second ready signal is varied for each clock cycle unit.
8. The method of claim 7,

The second circuit is

and a synchronization processing unit for synchronizing the input data.
12. The method of claim 11,

The synchronization processing unit,

a first flip-flop;

a third switch connected to an output terminal of the first flip-flop;

a second flip-flop connected to an output terminal of the third switch;

a third flip-flop connected to an output terminal of the second flip-flop;

and a fourth switch connected between an output terminal of the second flip-flop and an input terminal of the second flip-flop.
12. The method of claim 11,

The second circuit is

memory; further comprising

The synchronization processing unit,

and delaying the update of the address address of the memory based on the variation of the second valid signal for each clock cycle unit.
12. The method of claim 11,

The synchronization processing unit,

The signal processing apparatus of claim 1, wherein the output of data is delayed randomly based on a second clock signal based on the variation of the second valid signal for each clock cycle unit.
8. The method of claim 7,

a first circuit operating based on a first clock signal and transmitting the data;

a second circuit that operates based on a second clock signal different from the first clock signal and receives the data from the first circuit;

The transmission interface device is disposed in the first circuit, the signal processing device, characterized in that the at least one of the second valid signal and the second ready signal, each clock cycle to vary.
16. The method of claim 15,

The first circuit is

circuit core;

middle interface device;

and a second transmission interface device disposed between the circuit core and the middle interface device.