WO2022048407A1

WO2022048407A1 - Method and apparatus for mixed scheduling of messages, and electronic device and storage medium

Info

Publication number: WO2022048407A1
Application number: PCT/CN2021/111540
Authority: WO
Inventors: 文林; 马汝胜; 朱超国; 祖翔
Original assignee: 中兴通讯股份有限公司
Priority date: 2020-09-04
Filing date: 2021-08-09
Publication date: 2022-03-10
Also published as: CN114221911A

Abstract

Embodiments of the present invention relate to the field of data transmission. Disclosed are a method and apparatus for mixed scheduling of messages, and an electronic device and a storage medium. The method for mixed scheduling of messages comprises: transmitting a determinacy message stored in a first scheduling queue to an egress queue, and after a condition that no determinacy message is stored in the first scheduling queue is satisfied, transmitting a normal message stored in a second scheduling queue to the egress queue; and sending the messages stored in the egress queue.

Description

Method, device, electronic device and storage medium for mixed scheduling of messages

cross reference

This application is based on the Chinese patent application with the application number "202010923671.0" and the application date is September 4, 2020, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby incorporated by reference. Apply.

technical field

Embodiments of the present invention relate to the field of data transmission, and in particular, to a mixed scheduling method, device, electronic device, and storage medium for messages.

Background technique

With the rise of the Industrial Internet, Deterministic Network proposes to guarantee the deterministic transmission delay for specific packets, to ensure the specific packet delay of the Industrial Internet, and to achieve the purpose of Industrial Internet control. In a deterministic network, deterministic packets and ordinary packets are scheduled on the same data forwarding line to ensure mixed scheduling of deterministic delay packets and ordinary packets, which has become a key technology in deterministic network research.

In traditional packet scheduling, in order to achieve mixed scheduling of deterministic packets and ordinary packets, deterministic packets are added to the transmission path of ordinary packets, which complicates the scheduling structure, blurring deterministic packets and high-priority ordinary packets. The transmission order of packets, and there is a priority setting added to the original ordinary packet transmission path in order to reflect the priority of deterministic packets, but the priority setting is incompatible with the original transmission path, so it cannot be determined efficiently. Mixed scheduling of private packets and ordinary packets.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a mixed scheduling method for messages, including the following steps: transmitting deterministic messages stored in a first scheduling queue to an egress queue, and transferring common messages stored in a second scheduling queue to an egress queue. After the preset conditions are met, it is transmitted to the egress queue; wherein, the preset conditions include: no deterministic messages are stored in the first scheduling queue; messages stored in the egress queue are sent.

Embodiments of the present invention also provide a mixed scheduling device for messages, including: a first transmission unit, configured to transmit the deterministic message stored in the first scheduling queue to the egress queue; a second transmission unit, used for The ordinary message stored in the second scheduling queue is transmitted to the egress queue after satisfying the preset condition; wherein, the preset condition includes: no deterministic message is stored in the first scheduling queue; the sending unit is used to send the message in the egress queue stored message.

Embodiments of the present invention also provide an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by at least one processor. One processor executes, so that at least one processor can execute the above-mentioned mixed scheduling method of the message.

Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, including: when the computer program is executed by a processor, the foregoing hybrid scheduling method for packets is implemented.

Description of drawings

FIG. 1 is a flowchart of a mixed scheduling method for packets according to a first embodiment of the present invention;

FIG. 2 is a schematic diagram of a mixed scheduling method for packets provided according to the first embodiment of the present invention;

3 is a flowchart of a post-scheduler execution in the method for hybrid scheduling of messages provided according to the first embodiment of the present invention;

FIG. 4 is a flowchart of a mixed scheduling method for packets according to a second embodiment of the present invention;

5 is a schematic diagram of a mixed scheduling device for messages provided according to a third embodiment of the present invention;

FIG. 6 is a schematic diagram of a mixed scheduling device for messages according to a third embodiment of the present invention in an example;

FIG. 7 is a schematic diagram of an electronic device according to a fourth embodiment of the present invention.

detailed description

In order to make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can appreciate that, in the various embodiments of the present invention, many technical details are set forth in order for the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can be realized. The following divisions of the various embodiments are for the convenience of description, and should not constitute any limitation on the specific implementation of the present invention, and the various embodiments may be combined with each other and referred to each other on the premise of not contradicting each other.

The purpose of the embodiments of the present invention is to provide a mixed scheduling method for messages, so as to realize efficient mixed scheduling of deterministic messages and ordinary messages.

The embodiments of the present invention divide deterministic packets and ordinary packets into two scheduling queues for storage. Using the mixed egress queue mode, combined with the preset judgment conditions, the priority scheduling of deterministic packets is realized, and the common packets can share the scheduling resources of deterministic packets, and the mixed scheduling of deterministic packets and ordinary packets can be efficiently realized.

The first embodiment of the present invention relates to a method for mixed scheduling of packets. The schematic diagram is shown in FIG. 2 , and the flow is shown in FIG. 1 , including:

Step 101: Transmit the deterministic message stored in the first scheduling queue to the egress queue, and transmit the ordinary message stored in the second scheduling queue to the egress queue after satisfying preset conditions; wherein the preset conditions include: Deterministic packets are not stored in the first scheduling queue.

Step 102: Send the packets stored in the egress queue.

Specifically, as shown in FIG. 2 , in this embodiment, independent scheduling queues are set for deterministic packets and ordinary packets, respectively, the deterministic packet scheduling queue lead time gate wheel, and the ordinary data packet scheduling queue Post scheduling controller. That is to say, deterministic packets are transmitted to the first scheduling queue set for deterministic packets through the time gate wheel, so as to control the delay of deterministic packets, so as to ensure the scheduling of different deterministic packets with different delays. Purpose. A scheduling controller is placed behind the second scheduling queue set for ordinary data packets, so as to constrain the egress scheduling of ordinary data packets. The constraint condition is the deterministic packet scheduling queue signal. When the packet outputs the scheduling queue signal, the scheduling of ordinary data packets must be stopped.

The embodiments of the present invention are mainly executed by electronic equipment. The processor sends deterministic messages to the first scheduling queue through the time gate wheel, and sends ordinary messages to the second scheduling queue. If there is a deterministic message in the first scheduling queue message, the first scheduling queue sends a scheduling queue signal to the scheduling controller, the scheduling controller restricts the operation of sending ordinary messages in the second scheduling queue to the egress queue, and the first scheduling queue sends the stored deterministic messages to egress queue; if there is no deterministic message in the first scheduling queue, the scheduling controller sends the ordinary message in the second scheduling queue to the egress queue message. When the egress queue receives a packet, the processor sends the packet in the egress queue, so that while ensuring the priority scheduling of deterministic packets, ordinary data packets can share the scheduling resources of deterministic packets and ensure the second priority of ordinary packets. schedule.

The implementation details of the mixed scheduling method for messages in this embodiment will be specifically described below. The following content is only provided for the convenience of understanding, and is not necessary for implementing this solution.

In an example, before step 101 is executed, the deterministic packet is transmitted to the first scheduling queue through the time gate wheel, so as to achieve the purpose of ensuring the scheduling delay of the deterministic packet. Specifically, the opening period of the time gate wheel is controlled according to the delay requirement of the deterministic message; the deterministic message is transmitted to the first scheduling queue through the opened time gate wheel; wherein, the delay requirement of the deterministic message The higher it is, the shorter the allowable transmission delay time is, and the shorter the time gate wheel opening period is. That is, according to the deterministic packet delay configured by the user, the time gate wheel is opened at a specific time interval to achieve the purpose of scheduling the delay execution.

During the execution of step 101, the post-scheduling controller is used to transmit the ordinary message stored in the second scheduling queue to the egress queue. The specific execution flow chart is shown in Figure 3:

Step 1011: Acquire common packets in the second scheduling queue.

Step 1012: Detect whether there is a deterministic message in the current first scheduling queue; if yes, go to Step 1013; if not, go to Step 1014.

In one example, according to the scheduling queue signal generated by the first scheduling queue, it is detected whether there is a deterministic packet in the current first scheduling queue; wherein the scheduling queue signal is used to indicate that there is a deterministic packet in the first scheduling queue. If there is a deterministic packet in the first scheduling queue, a scheduling queue signal will be generated; if there is no deterministic packet in the first scheduling queue, no scheduling queue signal will be generated. Therefore, whether there is a deterministic packet in the current first scheduling queue can be detected by whether the scheduling queue signal is detected.

Step 1013: Forbid the transmission of ordinary packets in the second scheduling queue to the egress queue.

Step 1014: Transmit the ordinary packets in the second scheduling queue to the egress queue.

In this embodiment, deterministic packets and ordinary packets are divided into two scheduling queues for storage. Using the mixed egress queue mode, combined with the preset judgment conditions, the priority scheduling of deterministic packets is realized, and the common packets can share the scheduling resources of deterministic packets, and the mixed scheduling of deterministic packets and ordinary packets can be efficiently realized.

The second embodiment of the present invention relates to a method for mixed scheduling of packets. The specific process is shown in FIG. 4 , including:

Step 201 , according to a preset scheduling mechanism, transmit the deterministic message stored in the first scheduling queue to the egress queue.

Step 202, transmitting the ordinary message stored in the second scheduling queue to the egress queue after satisfying the preset condition; wherein, the preset condition includes: no deterministic message is stored in the first scheduling queue.

It should be noted that step 201 and step 202 do not have a definite sequence relationship. Step 201 and step 202 are essentially two independent steps executed in parallel. FIG. 4 is only an example, and does not constitute an execution sequence. constraint.

Step 203: Send the message stored in the egress queue.

Step 203 in this embodiment is substantially the same as that in the first embodiment, and will not be described again.

Steps

201 and 202 of this embodiment will be specifically described below.

In step 201, according to a preset scheduling mechanism, the deterministic message stored in the first scheduling queue is transmitted to the egress queue. The preset scheduling mode can be configured for deterministic network requirements and users, so that the transmission process is suitable for actual situations and user experience is improved.

The preset scheduling mechanism includes any one of the following scheduling mechanisms: a PQ scheduling mechanism, a WFQ scheduling mechanism, and a CBWFQ scheduling mechanism.

In one example, the PQ scheduling mechanism is used to transmit the deterministic packets in the first scheduling queue to the egress queue by using four sub-queues, and the priorities of the four sub-queues are high, medium, normal, and low, respectively. The scheduling mechanism will first serve the high-priority deterministic packet queue. If there is no data in the high-priority deterministic packet queue, it will serve the medium-priority deterministic packet queue, and so on. If the PQ is serving the medium priority deterministic message queue, but data is entered in the high priority deterministic message queue, the PQ interrupts the service of the medium priority deterministic message queue in favor of serving the high priority deterministic message queue message queue. By using the PQ scheduling mechanism to schedule the deterministic messages stored in the first scheduling queue, an absolute priority can be given to the deterministic messages with high priority.

In one example, the WFQ scheduling mechanism may also be used to transmit the deterministic packets in the first scheduling echelon to the egress queue. It can ensure fairness among deterministic packets of the same priority, and implement weighting between deterministic packets of different priorities. The number of queues can be pre-configured, and the weights are reflected on the basis of ensuring delay fairness. The weights depend on the IP precedence carried in the packet header. WFQ classifies deterministic packets by flow, and each deterministic packet flow is assigned to a queue. The HASH algorithm is used to automatically complete the enqueue process. When dequeuing, the bandwidth that each deterministic packet flow should occupy at the exit is allocated according to the priority. The lower the priority value, the less bandwidth you get. The WFQ scheduling mechanism is used to schedule the deterministic packets stored in the first scheduling queue, and the HASH algorithm automatically classifies the deterministic packets without user operation; all deterministic packet flows have transmission bandwidth.

In an example, the CBWFQ scheduling mechanism may also be used to transmit the deterministic packets in the first scheduling echelon to the egress queue. CBWFQ typically defines deterministic packet flow classes using access control list ACLs, which allow categorization of deterministic packets based on criteria such as access control lists, input interface names, protocols, and quality of service flags. The CBWFQ scheduling mechanism is an extension of the WFQ scheduling mechanism, which supports user-defined classification of deterministic packet flows, and the number and type of queues are in one-to-one correspondence, guaranteeing bandwidth for each deterministic packet flow.

In this embodiment, a scheduling mechanism is preset for deterministic network requirements and user configuration to transmit deterministic packets in the first scheduling echelon, which can ensure the priority of deterministic packets in the process of transmission, and ensure the priority of deterministic packets during transmission. Reasonable allocation of path resources in the process of transmitting deterministic packets to egress queues.

The third embodiment of the present invention relates to a mixed scheduling device for messages, as shown in FIG. 5 , including:

The first transmission unit 301 is configured to transmit the deterministic message stored in the first scheduling queue to the egress queue.

The second transmission unit 302 is configured to transmit the ordinary message stored in the second scheduling queue to the egress queue after satisfying a preset condition; wherein the preset condition includes: no deterministic message is stored in the first scheduling queue.

Sending unit 303: used for sending the message stored in the egress queue.

In an example, the apparatus for mixed scheduling of packets further includes a third transmission unit 304, as shown in FIG. 6 . The third transmission unit 304 is configured to transmit the deterministic message to the first scheduling queue through the time gate wheel, so as to achieve the purpose of ensuring the scheduling delay of the deterministic message. For example, control the opening period of the time gate wheel according to the delay requirement of the deterministic message; transmit the deterministic message to the first scheduling queue through the opened time gate wheel; wherein, the longer the delay requirement of the deterministic message is, the more high, the turn-on period is shorter.

In one example, the second transmission unit 302 is specifically configured to acquire ordinary messages in the second scheduling queue; detect whether there is a deterministic message in the current first scheduling queue; if there is a deterministic message in the current first scheduling queue , then it is forbidden to transmit the common message in the second scheduling queue to the egress queue; if there is no deterministic message in the current first scheduling queue, the common message in the second scheduling queue is transferred to the egress queue.

In one example, detecting whether there is a deterministic packet in the current first scheduling queue is to detect whether there is a deterministic packet in the current first scheduling queue according to a scheduling queue signal generated by the first scheduling queue; wherein, the scheduling queue signal It is used to indicate that there is a deterministic packet in the first scheduling queue.

In addition, transmitting the deterministic packets stored in the first scheduling queue to the egress queue includes: according to a preset scheduling mechanism, transmitting the deterministic packets stored in the first scheduling queue to the egress queue.

In an example, the preset scheduling mechanism includes any one of the following scheduling mechanisms: a PQ scheduling mechanism, a WFQ scheduling mechanism, and a CBWFQ scheduling mechanism.

It is not difficult to find that this embodiment is a device example corresponding to the above-mentioned embodiment, and this embodiment can be implemented in cooperation with the above-mentioned embodiment. The related technical details mentioned in the foregoing embodiment are still valid in this embodiment, and are not repeated here in order to reduce repetition. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the above-mentioned embodiments.

The fourth embodiment of the present invention relates to an electronic device, as shown in FIG. 7, comprising at least one processor 401; and,

A memory 402 connected in communication with the at least one processor 401; wherein the memory 402 stores instructions executable by the at least one processor 401, the instructions being executed by the at least one processor 402 to enable the at least one processor 401 to perform the above-described embodiments The mixed scheduling method of the packets.

The memory 402 and the processor 401 are connected by a bus, and the bus may include any number of interconnected buses and bridges, and the bus connects one or more processors and various circuits of the memory. The bus may also connect together various other circuits, such as peripherals, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. The bus interface provides the interface between the bus and the transceiver. A transceiver may be a single element or multiple elements, such as multiple receivers and transmitters, providing a means for communicating with various other devices over a transmission medium. The data processed by the processor is transmitted on the wireless medium through the antenna, and further, the antenna also receives the data and transmits the data to the processor.

Processor 401 is responsible for managing the bus and general processing, and may also provide various functions including timing, peripheral interface, voltage regulation, power management, and other control functions. The memory 402 may be used to store data used by the processor in performing operations.

A fifth embodiment of the present invention relates to a computer-readable storage medium storing a computer program. The above method embodiments are implemented when the computer program is executed by the processor.

That is, those skilled in the art can understand that all or part of the steps in the method for implementing the above embodiments can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium and includes several instructions to make a device ( It may be a single chip microcomputer, a chip, etc.) or a processor (processor) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, Read-Only Memory (ROM, Read-Only Memory), Random Access Memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes .

Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present invention, and in practical applications, various changes in form and details can be made without departing from the spirit and the spirit of the present invention. Scope.

Claims

A method for mixed scheduling of packets, comprising:

The deterministic message stored in the first scheduling queue is transmitted to the egress queue, and the ordinary message stored in the second scheduling queue is transferred to the egress queue after satisfying a preset condition; wherein the preset condition includes : no deterministic message is stored in the first scheduling queue;

Send the packets stored in the egress queue.
The method for mixed scheduling of packets according to claim 1, wherein the transmitting the ordinary packets stored in the second scheduling queue to the egress queue after satisfying a preset condition comprises:

obtaining common packets in the second scheduling queue;

Detecting whether the deterministic message exists in the current first scheduling queue;

If the deterministic packet currently exists in the first scheduling queue, the transmission of ordinary packets in the second scheduling queue to the egress queue is prohibited;

If the deterministic message does not currently exist in the first scheduling queue, the ordinary message in the second scheduling queue is transmitted to the egress queue.
The method for mixed scheduling of packets according to claim 2, wherein the detecting whether the deterministic packet exists in the current first scheduling queue comprises:

Detecting whether the deterministic message currently exists in the first scheduling queue according to the scheduling queue signal generated based on the first scheduling queue;

The scheduling queue signal is used to indicate that the deterministic packet exists in the first scheduling queue.
The method for mixed scheduling of packets according to any one of claims 1 to 3, wherein before the transmitting the deterministic packets stored in the first scheduling queue to the egress queue, the method further comprises:

The deterministic message is transmitted to the first scheduling queue through the time gate wheel.
The method for mixed scheduling of messages according to claim 4, wherein the transmitting the deterministic message to the first scheduling queue through a time gate wheel comprises:

Control the opening cycle of the time gate wheel according to the delay requirement of the deterministic message;

transmitting the deterministic message to the first scheduling queue through the opened time gate wheel;

Wherein, the higher the delay requirement of the deterministic message, the shorter the opening period.
The method for hybrid scheduling of packets according to any one of claims 1 to 5, wherein the transmitting the deterministic packets stored in the first scheduling queue to the egress queue comprises:

According to the preset scheduling mechanism, the deterministic message stored in the first scheduling queue is transmitted to the egress queue.
The method for mixed scheduling of packets according to claim 6, wherein the preset scheduling mechanism includes any one of the following scheduling mechanisms:

Priority queue scheduling PQ mechanism, weighted fair queue WFQ scheduling mechanism, class-based weighted fair queue CBWFQ scheduling mechanism.
A message hybrid scheduling device, characterized in that it includes:

a first transmission unit, configured to transmit the deterministic message stored in the first scheduling queue to the egress queue;

The second transmission unit is configured to transmit the ordinary message stored in the second scheduling queue to the egress queue after satisfying a preset condition; wherein the preset condition includes: no confirmation is stored in the first scheduling queue sex message;

A sending unit, configured to send the packets stored in the egress queue.
An electronic device, comprising:

at least one processor; and,

a memory communicatively coupled to the at least one processor; wherein,

The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the execution of any of claims 1 to 7 The hybrid scheduling method for the described packets.
A computer-readable storage medium storing a computer program, characterized in that, when the computer program is executed by a processor, the hybrid scheduling method for messages according to any one of claims 1 to 7 is implemented.