WO2022048285A1 - 一种高可靠性多相供电系统及方法 - Google Patents

一种高可靠性多相供电系统及方法 Download PDF

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WO2022048285A1
WO2022048285A1 PCT/CN2021/103407 CN2021103407W WO2022048285A1 WO 2022048285 A1 WO2022048285 A1 WO 2022048285A1 CN 2021103407 W CN2021103407 W CN 2021103407W WO 2022048285 A1 WO2022048285 A1 WO 2022048285A1
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Prior art keywords
processing unit
detection module
power supply
current
management controller
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English (en)
French (fr)
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罗嗣恒
李辉
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Suzhou Wave Intelligent Technology Co Ltd
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Suzhou Wave Intelligent Technology Co Ltd
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Priority to US18/024,735 priority Critical patent/US11817696B2/en
Publication of WO2022048285A1 publication Critical patent/WO2022048285A1/zh
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
    • H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
    • H02H7/1203—Circuits independent of the type of conversion
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H1/00—Details of emergency protective circuit arrangements
    • H02H1/0092—Details of emergency protective circuit arrangements concerning the data processing means, e.g. expert systems, neural networks

Definitions

  • the present application relates to the field of multi-phase power supplies, and in particular, to a high-reliability multi-phase power supply system and method.
  • the power supply for the CPU chip generally adopts a multi-phase power supply mode.
  • the power supply is controlled by the controller by sending a PWM (Pulse Width Modulation) signal to control multiple field effect transistor switches.
  • PWM Pulse Width Modulation
  • the output of the field effect transistor switches is connected in parallel to form a large current output.
  • the current of the field effect transistor is too large, and under long-term high-load working conditions, the field effect transistor is prone to breakdown and failure, resulting in the risk of short circuit to ground and power failure or board burning. It affects the normal operation of the customer's business, and also brings hidden dangers to the fire safety of the data center computer room due to the burning of the board.
  • R&D engineers often invest resources to locate and analyze the problem on site. Moreover, the burning board will make it difficult to reproduce the problem on site, and it will be difficult to locate the root cause of the burning board.
  • the present application provides a high-reliability multi-phase power supply system, which aims to solve the problem that when a FET that specifically controls current supply in a multi-phase power supply in the prior art fails, the faulty FET cannot be quickly located.
  • the present invention provides a high-reliability polyphase power supply system, comprising a second processing unit and a baseboard management controller, wherein,
  • the second processing unit is configured with a first field effect transistor, the drain of the first field effect transistor is connected to a power supply, the source of the first field effect transistor is connected to the drain of the second field effect transistor, the The source of the second field effect transistor is grounded, and the gates of the first field effect transistor and the second field effect transistor are connected to the first processing unit;
  • the second processing unit is configured with a first current detection module, and the first current The detection module detects the source output current of the first field effect transistor;
  • the second processing unit is configured with a second current detection module, and the second current detection module detects the source current of the second field effect transistor;
  • the first current detection module and the second current detection module are electrically connected to a bus unit, and the bus unit is electrically connected to the baseboard management controller;
  • the baseboard management controller is electrically connected to the storage unit, and the baseboard management controller is electrically connected to the first processing unit.
  • the second processing unit is configured with a first voltage detection module, the first voltage detection module detects the voltage of the power supply, and the first voltage detection module is electrically connected to the bus unit.
  • the bus unit is connected to the baseboard management controller through a bus, and transmits the measurements of the first current detection module, the second current detection module and the first voltage detection module to the baseboard management controller data; the second current detection module is electrically connected to the first processing unit, and transmits measurement data to the first processing unit.
  • the first processing unit is configured with at least two PWM generation modules, any one of the PWM generation modules is electrically connected to the gate of the first FET in the second processing unit, and the PWM generation module is reversed.
  • the phase device is electrically connected to the grid of the second field effect transistor in a second processing unit.
  • the source of any one of the first FETs is connected to one end of the filter inductor, the other ends of all the filter inductors are electrically connected to the grounded filter capacitor, and the other ends of all the filter inductors are commonly connected to the CPU load .
  • the CPU load is configured with a second voltage detection module
  • the second voltage detection module detects the voltage division of the CPU load driven by the current provided by the high-reliability polyphase power supply system
  • the second voltage detection module is electrically Connect the first processing unit.
  • the present invention also provides a method for detecting and locating faults in a multi-phase power supply system and a processing method, which is applied to the described high-reliability multi-phase power supply system, including:
  • the first current detection module of the second processing unit measures and obtains the first current data
  • the second current detection module measures and obtains the second current data
  • the baseboard management controller obtains the first current through the bus unit. data and second current data
  • the baseboard management controller compares the first current data with the first threshold, and compares the second current data with the second threshold, if the first current data is greater than the first threshold or the If the second current data is greater than the second threshold, the second processing unit is abnormal.
  • mapping relationship is stored in the storage unit
  • the baseboard management controller acquires the identification of the abnormal second processing unit and the mapping relationship
  • the baseboard management controller determines according to the identification and the mapping relationship The location of the second handling unit of the exception.
  • the protection action includes:
  • the power supply input of the abnormal second processing unit is turned off; when the second current data is greater than the second threshold, the abnormal second processing unit is turned off.
  • the signal output of the connected PWM generation module, the CPU frequency is reduced to reduce the current demand;
  • the baseboard management controller When the baseboard management controller obtains from the bus unit the overcurrent information of the first field effect transistor on the second processing unit, the baseboard management controller is triggered to send a first signal to the power supply to turn off the power supply The output voltage of the supplier, so as to avoid burning out the CPU; when the baseboard management controller obtains from the bus unit the overcurrent information of the second FET on the second processing unit, the baseboard management controller is triggered to send to the first A processing unit sends out a second signal to turn off the corresponding PWM generating module in the first processing unit, and at the same time triggers the baseboard management controller to send a third signal to the CPU to control the CPU to work under frequency reduction, thereby ensuring that The CPU can work normally when the abnormal second processing unit does not supply power.
  • FIG. 1 is a schematic structural diagram of a high-reliability multi-phase power supply system in an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a second processing unit in an embodiment of the present invention.
  • FIG. 3 is a flowchart of a method for detecting, locating, and processing a fault in a polyphase power supply system according to an embodiment of the present invention.
  • the second processing unit 201, the first field effect transistor, 202, the second field effect transistor, 203, the first current detection module, 204, the second current detection module, 205, the bus unit, 206, the first voltage detection module,
  • the second voltage detection module includes
  • the present invention provides a high-reliability polyphase power supply system, including a first processing unit 100, a second processing unit 200, a baseboard management controller 300, a storage unit 400, a filter inductor 500, a filter capacitor 600, The second voltage detection module 700 and the power supply 800 .
  • the first processing unit 100 may be a voltage regulator control chip, the first processing unit 100 is configured with five PWM generating modules 101, and the PWM generating modules 101 are electrically connected to the second processing unit 200, control the second processing unit 200 by outputting pulse signals of different duty ratios; the first processing unit 100 is configured with a PMbus (Power Management Bus, power management bus) interface, and all the first processing unit 100 The PMbus interface is connected to the baseboard management controller 300 through a bus. There is a communication connection between the first processing unit 100 and the second processing unit 200 .
  • PMbus Power Management Bus, power management bus
  • the second processing unit 200 is configured with a first field effect transistor 201 , the drain of the first field effect transistor 201 is connected to the power supply 800 , and the source of the first field effect transistor 201 is connected to The drain of the second field effect transistor 202, the source of the second field effect transistor 202 is grounded, the gate of the first field effect transistor 201 is electrically connected to the output end of the PWM generating module 101, the The gates of the two field effect transistors 202 are electrically connected to the output end of the PWM generating module 101 through an inverter.
  • the second processing unit 200 is configured with a first current detection module 203, and the first current detection module 203 detects the source output current of the first FET 201; the second processing unit 200 is configured with a second current detection module Module 204, the second current detection module detects the source current of the second field effect transistor 202; in the specific implementation process, the first current detection module 203 and the second current detection module 204 use Hall current sensors or any one of the mutual inductance current sensors; the second processing unit 200 is configured with a first voltage detection module 206, the first voltage detection module 206 detects the voltage of the power supply 800, and the first voltage detection module 206
  • the bus unit 205 is electrically connected.
  • the first current detection module 203 and the second current detection module 204 are electrically connected to the bus unit 205, the bus unit 205 is configured with a PMbus interface, and the PMbus interface of the bus unit 205 is electrically connected to the substrate through the bus
  • the management controller 300 realizes the communication between the second processing unit 200 and the baseboard management controller 300, and the bus unit 205 stores the measurement data of the first current detection module 203 and the second current detection module 204
  • the second current detection module 204 is connected to the first processing unit 100 in communication, and the second current detection module 204 sends the second field to the first processing unit 100
  • the source current value of the effect transistor 202 (related to the PWM pulse); the first processing unit 100 adjusts the amplitude of the PWM pulse according to the source current value of the second field effect transistor 202 in the second processing unit 200 , so that the current outputs of different second processing units 200 are equal.
  • the baseboard management controller 300 is electrically connected to the storage unit 400 , the baseboard management controller 300 is electrically connected to the power supply 800 , the baseboard management controller 300 is electrically connected to the CPU, and the baseboard management controller 300
  • the first processing unit 100 and the second processing unit 200 are connected through a bus.
  • the source of any one of the first FETs 201 is connected to one end of the filter inductor 500 , the other ends of all the filter inductors 500 are electrically connected to the grounded filter capacitor 600 in common, and all the filter inductors 500 are electrically connected to the ground.
  • the other end of 500 is commonly connected to the CPU.
  • the AC part of the output signal is filtered by the filter inductor 500 and the filter capacitor 600 to ensure stable power supply to the CPU.
  • the CPU is configured with a second voltage detection module 700, the second voltage detection module 700 detects the voltage division of the CPU driven by the current provided by the high-reliability polyphase power supply system, and the second voltage detection module 700 electrically
  • the first processing unit 100 is sexually connected, and the transmission is transmitted to the first processing unit 100 .
  • the present invention provides a fault detection, location and processing method for a multi-phase power supply system.
  • the high-reliability multi-phase power supply system includes:
  • the identifier may be an address byte in a data packet for PMbus communication; the address bytes used by any two of the second processing units to communicate with the baseboard management controller are different. The address bytes are sorted according to the actual sorting of the second processing unit and stored in the storage unit.
  • the baseboard management controller acquires the identifier, the first current data and the second current data from the second processing unit. Specifically, the first current detection module of the second processing unit measures and acquires the first current data, The second current detection module measures and obtains the second current data, the first current detection module and the second current detection module send the measurement data to the bus unit, and the bus unit encapsulates the measurement data into PMbus protocol data packets sent to the baseboard management controller.
  • S3 Determine whether the second processing unit is abnormal according to the first current data and the second current data. Specifically, the baseboard management controller configures a first threshold for measuring the first current data and a second threshold for measuring the second current data;
  • the baseboard management controller compares the first current data with the first threshold, and compares the second current data with the second threshold, if the first current data is greater than the first threshold or the If the second current data is greater than the second threshold, the second processing unit is abnormal.
  • the baseboard management controller acquires the position of the second processing unit according to the identifier of the second processing unit. Specifically, the baseboard management controller obtains the content of the address byte by parsing the data packet sent by the bus unit to obtain the identifier of the abnormal second processing unit, and the baseboard management controller reads the mapping from the storage unit relationship, the baseboard management controller determines the location of the abnormal second processing unit according to the identifier and the mapping relationship.
  • the protection action includes: turning off the power supply input of the abnormal second processing unit;
  • the baseboard management controller is triggered to send a first signal to the power supply to turn off the output voltage of the power supply, thereby avoiding the first
  • the breakdown of the field effect transistor causes the output of the power supply to directly enter the CPU, resulting in burnout of the CPU;
  • the baseboard management controller When the second current data is greater than the second threshold, the baseboard management controller is triggered to send a second signal to the first processing unit to turn off the corresponding PWM generating module in the first processing unit, so that The first field effect transistor is turned off, and the abnormal second processing unit no longer outputs current; at the same time, the baseboard management controller is triggered to send a third signal to the CPU to control the CPU to perform frequency reduction, and the third signal includes The degree of CPU frequency reduction, the degree of CPU frequency reduction in the third signal is determined according to the number of abnormal second processing units, or the degree of CPU frequency reduction in the third signal is determined according to the second voltage detection module. The CPU partial pressure is determined.
  • the first processing unit sends the input voltage and output voltage of the voltage regulator to the baseboard management controller through the PMbus interface, and each second processing unit sends the power supply input voltage VIN to the baseboard management controller, first current data and second current data.
  • the baseboard management controller records the information when the abnormality occurs in the storage unit.
  • the baseboard management controller sends the abnormal type and location information of the abnormal second processing unit to the system.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the word “comprising” does not exclude the presence of elements or steps not listed in a claim.
  • the word “a” or “an” preceding an element does not preclude the presence of a plurality of such elements.
  • the invention can be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by one and the same item of hardware.
  • the use of the words first, second, and third, etc. do not denote any order. These words can be interpreted as names.

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Abstract

一种高可靠性多相供电系统及方法。第二处理单元配置第一场效应管，所述第一场效应管的漏极连接电源供应器，所述第一场效应管的源极连接第二场效应管的漏极，所述第二场效应管的源极接地，所述第一场效应管和第二场效应管的栅极连接第一处理单元；所述第二处理单元配置第一电流检测模块和第二电流检测模块，所述第一电流检测模块和第二电流检测模块电性连接总线单元，所述总线单元电性连接所述基板管理控制器；述基板管理控制器电性连接存储单元，所述基板管理控制器电性连接所述第一处理单元，所述基板管理控制器电性连接所述电源供应器。本发明能通过所述基板管理控制器快速对第二处理单元故障进行判断，定位并根据异常执行保护动作。

Description

一种高可靠性多相供电系统及方法
本申请要求于2020年09月04日提交中国专利局、申请号为202010925430.X、发明名称为“一种高可靠性多相供电系统及方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及多相电源领域，尤其涉及一种高可靠性多相供电系统及方法。
背景技术
伴随着云计算技术的不断兴起，互联网业务量不断增加。要求服务器计算节点的数据处理能力越来越强，部署密度越来越高，工作负荷也越来越大。尤其对于服务器内部的CPU芯片，其工作负载电流越来越大，电流多达100至200A。因此，要满足如此大电流的供电要求，给CPU芯片供电电源一般采用多相供电方式。
当前的多相供电方案中，供电电源由控制器通过发出PWM(Pulse Width Modulation，脉宽调制)信号来控制多颗场效应管开关，场效应管开关输出并联形成大电流输出，而当流过所述场效应管的电流过大，在长时间高负荷工作条件下，容易出现场效应管击穿失效，造成对地短路掉电或烧板的风险。影响客户业务的正常运行，同时也因烧板，对数据中心机房的消防安全带来隐患。同时，一旦出现烧板问题，研发工程师往往会投入资源在现场对问题进行定位分析，而且烧板会导致问题现场很难再复现，定位烧板根因也会存在较大的难度。
发明内容
本申请提供高可靠性多相供电系统，旨在解决现有技术中多相电源内具体控制电流供给的场效应管的发生故障时，无法快速对故障的场效应管进行定位。
为实现上述目的，本发明提供一种高可靠性多相供电系统，包括第二 处理单元和基板管理控制器，其中，
所述第二处理单元配置第一场效应管，所述第一场效应管的漏极连接电源供应器，所述第一场效应管的源极连接第二场效应管的漏极，所述第二场效应管的源极接地，所述第一场效应管和第二场效应管的栅极连接第一处理单元；所述第二处理单元配置第一电流检测模块，所述第一电流检测模块检测所述第一场效应管的源极输出电流；所述第二处理单元配置第二电流检测模块，所述第二电流检测模块检测所述第二场效应管的源极电流；所述第一电流检测模块和所述第二电流检测模块电性连接总线单元，所述总线单元电性连接所述基板管理控制器；
所述基板管理控制器电性连接存储单元，所述基板管理控制器电性连接所述第一处理单元。
优选地，所述第二处理单元配置第一电压检测模块，所述第一电压检测模块检测所述电源供应器的电压，所述第一电压检测模块电性连接所述总线单元。
优选地，所述总线单元通过总线连接所述基板管理控制器，向所述基板管理控制器传输所述第一电流检测模块、所述第二电流检测模块以及所述第一电压检测模块的测量数据；所述第二电流检测模块电性连接所述第一处理单元，向所述第一处理单元传输测量数据。
优选地，所述第一处理单元配置至少两个PWM发生模块，任一所述PWM发生模块电性连接一个第二处理单元中的第一场效应管的栅极，所述PWM发生模块经反相器电性连接一个第二处理单元中的第二场效应管的栅极。
优选地，任一所述第一场效应管的源极连接滤波电感的一端，所有的所述滤波电感另一端共同电性连接接地的滤波电容，所有的所述滤波电感另一端共同连接CPU负载。
优选地，所述CPU负载配置第二电压检测模块，所述第二电压检测模块检测由高可靠性多相供电系统提供的电流驱动的CPU负载的分压，所述第二电压检测模块电性连接所述第一处理单元。
本发明还提供一种多相供电系统故障检测定位及处理方法，应用于所 述的高可靠性多相供电系统，包括：
配置第二处理单元的标识，将所述第二处理单元的位置与标识建立映射关系；
从所述第二处理单元获取所述标识、第一电流数据和第二电流数据，并根据所述第一电流数据和第二电流数据判断所述第二处理单元是否异常以及异常类型；
如果所述第二处理单元异常则根据所述第二处理单元的标识获取所述第二处理单元的位置；
如果所述第二处理单元异常则执行保护动作。
更进一步地，第二处理单元的第一电流检测模块测量获取所述第一电流数据、第二电流检测模块测量获取所述第二电流数据，基板管理控制器通过总线单元获取所述第一电流数据和第二电流数据；
在所述基板管理控制器配置衡量所述第一电流数据的第一阈值和衡量所述第二电流数据的第二阈值；
所述基板管理控制器比较所述第一电流数据与所述第一阈值，比较所述第二电流数据与所述第二阈值，如果所述第一电流数据大于所述第一阈值或者所述第二电流数据大于所述第二阈值则所述第二处理单元异常。
更进一步地，在存储单元存储所述映射关系，所述基板管理控制器获取异常的第二处理单元的标识和所述映射关系，所述基板管理控制器根据所述标识和所述映射关系确定异常的第二处理单元的位置。
更进一步地，所述保护动作包括：
当所述第一电流数据大于所述第一阈值时，关断异常第二处理单元的电源供应器输入；当所述第二电流数据大于所述第二阈值时，关断异常第二处理单元连接的PWM发生模块信号输出，CPU降频减少电流需求；
记录异常信息。
本申请提出的一种高可靠性多相供电系统及方法具体有以下有益效果：
当基板管理控制器从所述总线单元获取到第二处理单元上第一场效应管出现过流信息，触发所述基板管理控制器向所述电源供应器发出第一信 号以关断所述电源供应器的输出电压，从而避免烧坏CPU；当基板管理控制器从所述总线单元获取到第二处理单元上第二场效应管出现过流信息，触发所述基板管理控制器向所述第一处理单元发出第二信号以关断所述第一处理单元中相应的PWM发生模块，同时触发所述基板管理控制器向所述CPU发送第三信号，控制所述CPU降频工作，从而保证在异常第二处理单元不供电的情况下CPU能正常工作。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1是本发明实施例中高可靠性多相供电系统的架构示意图；
图2是本发明实施例中第二处理单元的架构示意图；
图3是本发明实施例中多相供电系统故障检测定位及处理方法的流程图。
图中标号及含义如下：
100、第一处理单元，101、PWM发生模块，
200、第二处理单元，201、第一场效应管，202、第二场效应管，203、第一电流检测模块，204、第二电流检测模块，205、总线单元，206、第一电压检测模块，
300、基板管理控制器，
400、存储单元，
500、滤波电感，
600、滤波电容，
700、第二电压检测模块，
800、电源供应器。
本发明目的的实现、功能特点及优点将结合实施例，参照附图做进一 步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
参阅图1所示，本发明提供一种高可靠性多相供电系统，包括第一处理单元100、第二处理单元200、基板管理控制器300、存储单元400、滤波电感500、滤波电容600、第二电压检测模块700以及电源供应器800。
其中，具体实施时，所述第一处理单元100可以为电压调整器控制芯片，所述第一处理单元100配置有五个PWM发生模块101，所述PWM发生模块101电性连接第二处理单元200，通过输出不同占空比的脉冲信号控制所述第二处理单元200；所述第一处理单元100配置有PMbus(Power Management Bus，电源管理总线)接口，所述第一处理单元100的所述PMbus接口通过总线连接所述基板管理控制器300。所述第一处理单元100与所述第二处理单元200之间通信连接。
参阅图2所示，所述第二处理单元200配置第一场效应管201，所述第一场效应管201的漏极连接电源供应器800，所述第一场效应管201的源极连接第二场效应管202的漏极，所述第二场效应管202的源极接地，所述第一场效应管201的栅极电性连接所述PWM发生模块101的输出端，所述第二场效应管202的栅极经反相器电性连接所述PWM发生模块101的输出端。所述第二处理单元200配置第一电流检测模块203，所述第一电流检测模块203检测所述第一场效应管201的源极输出电流；所述第二处理单元200配置第二电流检测模块204，所述第二电流检测模块检测所述第二场效应管202的源极电流；具体实施过程中所述第一电流检测模块203和所述第二电流检测模块204采用霍尔电流传感器或者互感电流传感器的任一种；所述第二处理单元200配置第一电压检测模块206，所述第一电压检测模块206检测所述电源供应器800的电压，所述第一电压检测模块206电性连接所述总线单元205。所述第一电流检测模块203和所述第二电流检测模块204电性连接总线单元205，所述总线单元205配置有 PMbus接口，所述总线单元205的PMbus接口通过总线电性连接所述基板管理控制器300，实现所述第二处理单元200与所述基板管理控制器300之间的通信，所述总线单元205将所述第一电流检测模块203和第二电流检测模块204的测量数据传输给所述基板管理控制器300；另外所述第二电流检测模块204与所述第一处理单元100通信连接，所述第二电流检测模块204向所述第一处理单元100发送第二场效应管202的源极电流值(与PWM脉冲相关)；所述第一处理单元100根据不同的所述第二处理单元200中第二场效应管202的源极电流值对PWM脉冲进行振幅调节，实现不同的所述第二处理单元200的电流输出相等。
所述基板管理控制器300电性连接存储单元400，所述基板管理控制器300电性连接所述电源供应器800，所述基板管理控制器300电性连接CPU，所述基板管理控制器300通过总线连接所述第一处理单元100和第二处理单元200。
具体实施过程中，任一所述第一场效应管201的源极连接滤波电感500的一端，所有的所述滤波电感500另一端共同电性连接接地的滤波电容600，所有的所述滤波电感500另一端共同连接所述CPU。通过所述滤波电感500和滤波电容600过滤输出信号中的交流部分，保证对所述CPU供电稳定。所述CPU处配置第二电压检测模块700，所述第二电压检测模块700检测由高可靠性多相供电系统提供的电流驱动的所述CPU的分压，所述第二电压检测模块700电性连接所述第一处理单元100，向所述第一处理单元100传输。
此外，本发明提供一种多相供电系统故障检测定位及处理方法，所述的高可靠性多相供电系统，包括：
S1，配置第二处理单元的标识，将所述第二处理单元的位置与标识建立映射关系。具体的，所述标识可以为进行PMbus通信的数据包中的地址字节；任意两个所述第二处理单元用于与基板管理控制器通信的地址字节不同。将所述地址字节按所述第二处理单元的实际排序进行排序保存于存储单元。
S2，基板管理控制器从所述第二处理单元获取所述标识、第一电流数 据和第二电流数据，具体的，第二处理单元的第一电流检测模块测量获取所述第一电流数据、第二电流检测模块测量获取所述第二电流数据，所述第一电流检测模块和所述第二电流检测模块向总线单元发送测量数据，所述总线单元将测量数据封包成PMbus协议的数据包发送给所述基板管理控制器。
S3，根据所述第一电流数据和第二电流数据判断所述第二处理单元是否异常。具体的，在所述基板管理控制器配置衡量所述第一电流数据的第一阈值和衡量所述第二电流数据的第二阈值；
所述基板管理控制器比较所述第一电流数据与所述第一阈值，比较所述第二电流数据与所述第二阈值，如果所述第一电流数据大于所述第一阈值或者所述第二电流数据大于所述第二阈值则所述第二处理单元异常。
如果所述第二处理单元异常则S4，基板管理控制器根据所述第二处理单元的标识获取所述第二处理单元的位置。具体的，所述基板管理控制器通过解析总线单元发送的数据包获取地址字节的内容从而获取异常的第二处理单元的标识，所述基板管理控制器从所述存储单元读取所述映射关系，所述基板管理控制器根据所述标识和所述映射关系确定异常的第二处理单元的位置。
如果所述第二处理单元异常则S5，执行保护动作。
所述保护动作包括：关断异常第二处理单元的电源供应器输入；
关断异常第二处理单元连接的PWM发生模块信号输出，CPU降频减少电流
记录异常信息。
具体的，当所述第一电流数据大于所述第一阈值时，触发所述基板管理控制器向所述电源供应器发出第一信号以关断所述电源供应器的输出电压，从而避免第一场效应管击穿导致电源供应器的输出直接进入CPU而导致烧坏CPU；
当所述第二电流数据大于所述第二阈值时，触发所述基板管理控制器向所述第一处理单元发送第二信号以关断所述第一处理单元中相应的PWM发生模块，使得第一场效应管截止，异常的第二处理单元不再输出 电流；同时，触发所述基板管理控制器向所述CPU发送第三信号，控制所述CPU降频工作，所述第三信号包含CPU降频的程度，所述第三信号中CPU降频的程度根据异常的第二处理单元的数量来确定或者所述第三信号中CPU降频的程度根据所述第二电压检测模块测量的CPU分压确定。
所述第一处理单元通过PMbus接口向所述基板管理控制器发送电压调整器的输入电压和输出电压，每个所述第二处理单元向所述基板管理控制器发送电源供应器输入电压VIN，第一电流数据和第二电流数据。异常发生，所述基板管理控制器将异常发生时的信息记录于所述存储单元。所述基板管理控制器向系统发送异常的第二处理单元的异常类型和位置信息。
应当注意的是，在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的部件或步骤。位于部件之前的单词“一”或“一个”不排除存在多个这样的部件。本发明可以借助于包括有若干不同部件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (10)

  1. 一种高可靠性多相供电系统，其特征在于，包括第二处理单元(200)和基板管理控制器(300)，其中，
    所述第二处理单元(200)配置第一场效应管(201)，所述第一场效应管(201)的漏极连接电源供应器(800)，所述第一场效应管(201)的源极连接第二场效应管(202)的漏极，所述第二场效应管(202)的源极接地，所述第一场效应管(201)和第二场效应管(202)的栅极连接第一处理单元(100)；所述第二处理单元(200)配置第一电流检测模块(203)，所述第一电流检测模块(203)检测所述第一场效应管(201)的源极输出电流；所述第二处理单元(200)配置第二电流检测模块(204)，所述第二电流检测模块检测所述第二场效应管(202)的源极电流；所述第一电流检测模块(203)和所述第二电流检测模块(204)电性连接总线单元(205)，所述总线单元(205)电性连接所述基板管理控制器(300)；
    所述基板管理控制器(300)电性连接存储单元(400)，所述基板管理控制器(300)电性连接所述第一处理单元(100)，所述基板管理控制器(300)电性连接所述电源供应器(800)。
  2. 根据权利要求1所述的高可靠性多相供电系统，其特征在于，所述第二处理单元(200)配置第一电压检测模块(206)，所述第一电压检测模块(206)检测所述电源供应器(800)的电压，所述第一电压检测模块(206)电性连接所述总线单元(205)。
  3. 根据权利要求2所述的高可靠性多相供电系统，其特征在于，所述总线单元(205)通过总线连接所述基板管理控制器(300)，向所述基板管理控制器(300)传输所述第一电流检测模块(203)、所述第二电流检测模块(204)以及所述第一电压检测模块(206)的测量数据；所述第二电流检测模块(204)电性连接所述第一处理单元(100)，向所述第一处理单元(100)传输测量数据用于实现不同的第二处理单元输出电流均衡。
  4. 根据权利要求3所述的高可靠性多相供电系统，其特征在于，所述第一处理单元(100)配置至少两个PWM发生模块(101)，任一所述PWM发生模块(101)电性连接一个第二处理单元(200)中的第一场效应管(201) 的栅极，所述PWM发生模块(101)经反相器电性连接一个第二处理单元(200)中的第二场效应管(202)的栅极。
  5. 根据权利要求1所述的高可靠性多相供电系统，其特征在于，任一所述第一场效应管(201)的源极连接滤波电感(500)的一端，所有的所述滤波电感(500)另一端共同电性连接接地的滤波电容(600)，所有的所述滤波电感(500)另一端共同连接CPU负载。
  6. 根据权利要求5所述的高可靠性多相供电系统，其特征在于，所述CPU处配置第二电压检测模块(700)，所述第二电压检测模块(700)检测由高可靠性多相供电系统提供的电流驱动的所述CPU的分压，所述第二电压检测模块(700)电性连接所述第一处理单元(100)。
  7. 一种多相供电系统故障检测定位及处理方法，应用于如权利要求1-6任一所述的高可靠性多相供电系统，其特征在于，包括：
    配置第二处理单元的标识，将所述第二处理单元的位置与标识建立映射关系；
    从所述第二处理单元获取所述标识、第一电流数据和第二电流数据，并根据所述第一电流数据和第二电流数据判断所述第二处理单元是否异常以及异常类型；
    如果所述第二处理单元异常则根据所述第二处理单元的标识获取所述第二处理单元的位置；
    如果所述第二处理单元异常则执行保护动作。
  8. 根据权利要求7所述的多相供电系统故障检测定位及处理方法，其特征在于，第二处理单元的第一电流检测模块测量获取所述第一电流数据、第二电流检测模块测量获取所述第二电流数据，基板管理控制器通过总线单元获取所述第一电流数据和第二电流数据；
    在所述基板管理控制器配置衡量所述第一电流数据的第一阈值和衡量所述第二电流数据的第二阈值；
    所述基板管理控制器比较所述第一电流数据与所述第一阈值，比较所述第二电流数据与所述第二阈值，如果所述第一电流数据大于所述第一阈值或者所述第二电流数据大于所述第二阈值则所述第二处理单元异常。
  9. 根据权利要求8所述的多相供电系统故障检测定位及处理方法，其特征在于，在存储单元存储所述映射关系，所述基板管理控制器获取异常的第二处理单元的标识和所述映射关系，所述基板管理控制器根据所述标识和所述映射关系确定异常的第二处理单元的位置。
  10. 根据权利要求9所述的多相供电系统故障检测定位及处理方法，其特征在于，所述保护动作包括：
    当所述第一电流数据大于所述第一阈值时，关断异常第二处理单元的电源供应器输入；当所述第二电流数据大于所述第二阈值时，关断异常第二处理单元连接的PWM发生模块信号输出，CPU降频减少电流需求；
    记录异常信息。
PCT/CN2021/103407 2020-09-04 2021-06-30 一种高可靠性多相供电系统及方法 Ceased WO2022048285A1 (zh)

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