WO2022046122A1

WO2022046122A1 - System configuration restoration

Info

Publication number: WO2022046122A1
Application number: PCT/US2020/048831
Authority: WO
Inventors: Chia-Cheng Lin; Yu-Chen Lin; Wei-Yu Chen
Original assignee: Hewlett-Packard Development Company, L.P.
Priority date: 2020-08-31
Filing date: 2020-08-31
Publication date: 2022-03-03

Abstract

Examples of the present disclosure relate to system configuration restoration. In some examples, a computing device includes a processor and a memory resource storing instructions that when executed by the processor cause the processor to monitor, by a basic input/output system (BIOS) and an embedded controller of the computing device, power limit settings associated with the processor. The instructions can be executable to take control, by the BIOS, of an interface between the embedded controller and the processor to restore a default system configuration to the interface responsive to an indication of a first adverse event by the BIOS and a second adverse event by the embedded controller.

Description

SYSTEM CONFIGURATION RESTORATION

Background

[0001] A processor is an electronic circuit which performs operations on an external data source such as a memory resource. A central processing unit (CPU) is electronic circuitry within a computing device that executes instructions that make up a computer program. The CPU performs operations specified by the instructions. The CPU can refer to a processor, which may include a processing unit and control unit.

Brief Description of the Drawings

[0002] Figure 1 illustrates an example computing device having a processor and memory resource for system configuration restoration in accordance with the present disclosure.

[0003] Figure 2 illustrates an example of a memory resource for system configuration restoration in accordance with the present disclosure.

[0004] Figure 3 illustrates an example system including a basic input/output system (BIOS) and an embedded controller for system configuration restoration in accordance with the present disclosure.

[0005] Figure 4 illustrates an example flow chart of a method for system configuration restoration in accordance with the present disclosure.

Detailed Description

[0006] A computing device can utilize a BIOS to perform certain actions. As used herein, the term “BIOS” refers to a non-volatile firmware component to perform hardware initialization during a startup sequence of the computing device and to provide runtime services for operating systems (OSes) and/or other programs. For example, as a computing device is started (i.e., booted), the BIOS can initialize hardware of the computing device.

[0007] As used herein, the term “embedded controller” refers to a microcontroller in a computing device that handles various system tasks that the OS does not handle. Example tasks include turning the computing device on and off, performing requested CPU resets, thermal measurements of the CPU, and responses including fan control, CPU throttling, and emergency shutdown in response to rising temperatures, among others. An embedded controller remains on when power is supplied to the computing device. The embedded controller can have its own memory resource. BIOS updates may include upgrades for embedded controller firmware, in some examples.

[0008] As used herein, the term “computing device” refers to a mechanical or electrical device that transmits or modifies energy to perform or assist in the performance of human tasks. Example computing devices include a laptop computer, a notebook computer, a desktop computer, an all-in-one (AIO) computer, and/or a mobile device, among other types of computing devices. As used herein, a mobile device can include computing devices that are (or can be) carried and/or worn by a user. For example, a mobile device can be a phone (e.g., a smart phone), a tablet, a personal digital assistant (PDA), smart glasses, and/or a wrist-worn device (e.g., a smart watch), among other types of mobile devices. As used herein, the term “operating system” (OS) refers to software that supports a computing device’s basic functions, such as scheduling tasks, executing applications, and/or controlling peripheral devices. As used herein, the term “firmware” refers to software that provides control of particular hardware of a computing device. As used herein, the term “firmware component” refers to a device containing the firmware and/or utilizing (e.g., being controlled by) the firmware.

[0009] A plurality of power limits (also known as power limit levels) can be modified by drivers or applications to adjust CPU power to limit CPU performance for temperature reduction. For instance, a CPU can be throttled to conserve energy and/or reduce generated heat to preserve and/or extend a life of the computing device. Power limits, for instance, can include an expected long-term steady state power consumption of a processor (e.g. , a first power level having a first power level limit threshold), and a short-term maximum power draw for the processor (e.g., a second power level having a second power level limit threshold). The second power level may be higher than the first power level, and the processor can go into the second power level when a workload is applied, allowing the processor to use power up to the second power level limit threshold. In some examples, the first power level is a thermal design power (TDP) of the processor.

[0010] Power limits can also include a third power level having a higher power level limit threshold than the first and the second power levels, and a fourth power level having a higher power level limit threshold than the first, the second, and the third power levels. For instance, a highest CPU power level cannot exceed the power level limit threshold of the fourth power level. While four power levels are described herein, examples are not so limited. The BIOS, in some examples, can control the first, the second, and the third power levels, while the embedded controller can control the fourth power level. For instance, the embedded controller remains on to make sure the fourth power level limit threshold is not exceeded by the CPU, even if the BIOS has failed or is not performing.

[0011] In order to adjust CPU power, an interface (e.g., a processor performance interface) may be modified; however, if during modification the interface is compromised due to an attack (e.g., malicious attack on the interface), a performance tuning driver crash, or uninstallation of the performance tuning driver, among others, the CPU may fail or underperform (e.g., decreased performance, lag, overheat, hang, Blue Screen of Death, etc.). A performance tuning driver, as used herein, can customize power settings to adapt power policies based on usage mode and temperature and make adjustments.

[0012] Some CPU power adjustment approaches include the use of an OS policy scheme to manage power adjustments and/or begin managing power adjustments using BIOS setup options at boot. Other approaches use temperature sensors and BIOS power-on self-tests to monitor temperature and other CPU performance aspects. [0013] The present disclosure relates to system configuration restoration using both a BIOS and an embedded controller separated from a processor (e.g. , CPU) by an interface. The present disclosure allows for monitoring of performance settings (e.g., low performance, overheating, lag, hang, etc.) and/power limit settings (first, second, third, fourth, power level and associated internal operation configurations) for the processor. Such examples of the present disclosure can provide self-health monitoring for an error state of an interface associated with a processor such as a CPU performance interface with reduced additional hardware costs while being implementable into an existing computing device. Examples of the present disclosure can include the use of checkpoints and/or routines during monitoring, and responsive to adverse events, the BIOS, in some examples, can execute a processor handler (e.g., CPU handler) to restore a default system configuration and/or set a policy for system configuration.

[0014] Checkpoints, as used herein, are snapshots of an application or system state, and that state can be used so the application or system can restart from that point in case of failure. Different checkpointing techniques can be used, for instance including collaborative checkpointing, checkpoint libraries, and/or fault tolerance interface libraries, among others. A routine, as used herein, can include a code that can be called and executed repeatedly during execution of instructions. A processor handler, also known as an interrupt or CPU handler, can implement device drivers or transitions between protected modes of operation.

[0015] Figure 1 illustrates an example computing device 102 having a processor 104 and memory resource 106 for system configuration restoration in accordance with the present disclosure. In some examples the device 102 can be a computing device that includes a processor 104 communicatively coupled to the memory resource 106. “Communicatively coupled,” as used herein, can include coupled via various wired and/or wireless connections between devices such that data can be transferred in various directions between the devices. The coupling may not be a direct connection, and in some examples can be an indirect connection. As described further herein, the memory resource 106 can include instructions 108, 110 that can be executed by the processor 104 to perform particular functions. [0016] The device 102 can be a component of a computing device such as a processor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a metal-programmable cell array (MPCA), or other combination of circuitry and/or logic to orchestrate execution of instructions 108, 110. In other examples, the device 102 can be a computing device that can include instructions 108, 110 stored on a machine-readable medium (e.g., memory resource 106, non-transitory computer-readable medium, etc.) and executable by a processor 104.

[0017] In some examples, the device 102 can include instructions 108 that can be executed by a processor 104 to monitor, by a BIOS and an embedded controller of the computing device, power limit settings associated with the processor (e.g., for adverse events). For instance, the processor 104 may define its TDP and a particular power limit (e.g., first power level, second power level, third power level, fourth power level). During overclocking (e.g., increasing the clock rate of the computing device 102 to exceed a manufacturer’s recommendation), the processor 104 may set a power limit higher than the TDP (e.g., a fourth power level). A power limit setting can be monitored to determine whether adverse events are occurring no matter the power limit. As used herein, “power limit” refers to a threshold power amount (e.g., the power limit is X) and “power limit level” may refer to a particular power level such as a first or a second power level. Each power limit level may have a different power limit (e.g., the first power level has a lower power limit than the second power level).

[0018] In some examples, a first and/or a second power limit level setting associated with the processor 104 can be monitored. The power limit level settings may include different power levels, which may be monitored by either the BIOS or the embedded controller. For instance, the BIOS may monitor and/or control the first, the second, and the third power levels, while the embedded controller may monitor and/or control the fourth power level.

[0019] In some examples, the instructions executable to monitor power limit settings further comprise Instructions executable to set a checkpoint and/or a routine to detect a first adverse event, a second adverse event, or both. An adverse event, for instance, can include a performance tuning driver crash, a malicious attack on the interface, or a combination thereof. An adverse event may cause the processor 104 to underperform or fail . The first adverse event, for instance may be detected by the BIOS, while the second adverse event is detected by the embedded controller. For example, a checkpoint and/or a routine may detect the processor 104 underperforming due to an adverse event detected by the BIOS (e.g., associated with the first, the second, or the third power level) and a checkpoint and/or a routine may detect the processor 104 underperforming due to an adverse event detected by the embedded controller (e.g., associated with the fourth power level).

[0020] In some examples, a checkpoint and/or routine may include the BIOS checking an advanced configuration and power interface (ACPI) method to determine if the performance tuning driver is performing properly and has not crashed. In some examples with respect to malicious attacks, a checkpoint and/or routine may include the BIOS checking the interface (e.g., performance interface) to monitor power limit level modifications.

[0021] In some examples, the device 102 can include instructions 110 that can be executed by the processor 104 to take control, by the BIOS, of an interface between the embedded controller and the processor to restore a default system configuration to the interface responsive to an indication of the first adverse event by the BIOS and the second adverse event by the embedded controller. For instance, the BIOS can execute a processor handler to restore the fault system configuration and/or set a policy for configuration of the system configuration at the time of the indication of the first and the second adverse events. Setting a policy can include the BIOS restoring power limit levels to a default setting (e.g., factory setting) on the interface when the interface experiences an adverse event (e.g., an Invalid value).

[0022] In some instances, the memory resource 106 can Include Instructions executable to take control, by the BIOS, of the Interface responsive to the first (e.g., a fourth power level) and/or the second power limit level setting (e.g., a first, second, or third power level) being outside of its respective particular internal operation configuration. In response, the default system configuration can be restored to the interface including a default processor power limit level. For instance, if the first power limit level setting corresponds to a fourth power limit level, and the second power limit level setting corresponds to one of a first, a second, or a third power level, if the limit of the first power level is approaching a level outside of its determined internal operation configuration, the BIOS can take control and restore it to a default processor power limit level. This is the same for internal operation configurations within a second power level and a third power level. With respect to a fourth power limit level, the embedded controller may instruct the BIOS to take control and restore it to a default processor power limit level responsive to the first power limit level setting being outside of an internal operation configuration associated with the fourth power limit level.

[0023] The embedded controller, in some examples, can also monitor and/or controller thermal settings, such as fan speeds, associated with the processor 104. For instance, the memory resource 106 can include instructions executable by the processor 104 to monitor, by the embedded controller, a fan speed associated with the processor, notify the BIOS responsive to the fan speed exceeding a particular threshold, and take control, by the BIOS, of the interface to restore the default system configuration to the interface including a default fan speed. The default fan speed, in some examples, is restored by the embedded controller itself. For instance, if the processor 104 is running hot, the fan speed may be above a particular threshold, which can trigger the BIOS to restore the default system configuration to reduce processor underperformance and trigger the embedded controller to take the fan back down to a default fan speed.

[0024] In some examples, the BIOS can initiate hardware of a computing device and determine a system configuration to use as a default system configuration including a default platform policy associated with performance tuning. The system configuration can include alternating current (AC)/direct current (DC) mode, a total graphics power (TGP) of internal and external graphics adapters, an AC adapter rating, and processor (e.g., CPU) TDP, among others. In some examples, the BIOS can provide an interface (e.g., a performance interface) for software to adjust processor (e.g., processor 104) power. The Interface can include, for instance memory mapped input/output (MM IO) and/or power interface non-volatile sleeping (ACPI NVS) memory.

[0025] In some instances, adverse events can occur at a software layer of a computing device. For instance, an application or driver may have access to the interface to configure a power limit setting of the processor 104. In a non-adverse event situation, the software can take control of thermal and performance tuning, if the software is corrupt, crashed, unsupported, or uninstalled by the user while running, the software can lose control of thermal and performance tuning. In such an example, if malware is present or other adverse events occur, the power limit setting of the processor 104 can be negatively impacted, and the computing device can become unstable. Thermal and performance tuning can include a slider tool to adjust system performance in AC and DC modes including, for example, “better performance”, “best performance”, “best battery”, etc. The performance tuning driver can determine a position of the slider tool, and the BIOS can communicate with the performance tuning driver to perform tuning as the slider tool position changes.

[0026] Responsive to booting to the OS, the BIOS can begin monitoring the interface periodically (e.g., at particular intervals) with system configurations to determine if processor performance or thermal tuning has been cracked by a crashed performance tuning driver or malware. Responsive to an adverse event such as the crashed performance tuning driver or malware, the BIOS can take control and restore a default system configuration and/or default platform policy to a more stable performance setting.

[0027] The embedded controller, in some examples, can handle a thermal event for performance tuning. The thermal events can include overheating of the processor 104, among others, and may come from the BIOS or software. In the OS, the embedded controller can monitor thermal performance of the interface and/or the processor 104, for instance to determine if the speed of a fan used to cool the processor 104 Is exceeding a particular threshold fan speed (e.g., running out of valid range). Responsive to the threshold being exceeded, the embedded controller can notify the BIOS to check if the interface has experienced an adverse event (e.g., modified with an invalid value), and if it has, restore the default system configuration and/or default platform policy to a more stable performance setting. In some examples, the embedded controller can restore a default fan speed to the fan that exceeded the particular threshold fan speed.

[0028] Figure 2 illustrates an example of a memory resource 206 for system configuration restoration in accordance with the present disclosure, in accordance with the present disclosure. In some examples, the memory resource 206 can be a part of a computing device or controller such as device 102 referenced in Figure 1 . In some examples, the memory resource 206 can be communicatively coupled to a processor 204 that can execute instructions 212, 214, 216 stored on the memory resource 206. For example, the memory resource 206 can be communicatively coupled to the memory resource 206 through a communication path 215. As used herein, a communication path 215 can include a wired or wireless connection that can allow communication between devices.

[0029] The memory resource 206 may be electronic, magnetic, optical, or other physical storage device that stores executable instructions. For example, the memory resource 206 can be a non-transitory machine-readable medium comprising Random Access Memory (RAM), an Electrically-Erasable Programmable ROM (EEPROM), a storage drive, an optical disc, and the like. The non-transitory machine readable medium (e.g., a memory resource 206) may be disposed within a controller and/or computing device. In this example, the executable instructions 212, 214, 216 can be “installed” on the device. Additionally, and/or alternatively, the non-transitory machine readable medium (e.g., a memory resource 206) can be a portable, external or remote storage medium, for example, that allows a system to download the instructions 212, 214, 216 from a portable/external/remote storage medium. In this situation, the executable instructions may be part of an “installation package”. As described herein, the non-transitory machine readable medium (e.g., a memory resource 206) can be encoded with executable instructions for system configuration restoration.

[0030] The instructions 212, when executed by a processor such as the processor 204, can include instructions to monitor, using a BIOS and an embedded controller, performance of an interface located between the processor 204 and the embedded controller and a thermal setting for the processor 204. The Interface can be used to monitor a temperature of the processor 204 and set system configurations associated with processor power limits and processor fan speeds. For Instance, the BIOS can monitor the interface for power level limits for a first set of power limits including lower power limits (e.g., a first power level, a second power level, a third power level), and the embedded controller can monitor the interface for thermal aspects (e.g. , a temperature of the processor 204) of the interface and/or the processor 204. For instance, the embedded controller can access information associated with the processor 204 via the interface, in some examples, more than one interface may be present. For instance, the embedded controller may have an interface associated therewith, and the BIOS may have an interface associated therewith.

[0031] The instructions 214, when executed by a processor such as the processor 204, can Include instructions to enable the BIOS to execute a processor handler to set a policy for a system power limit configuration responsive to detection of failure at the interface. For instance, responsive to the interface experiencing an adverse event such as a third power level falling outside of a particular internal operation configuration, the BIOS can take control of the interface and set a policy for a system power limit configuration that restores stability to the system (e.g., processor 204, computing device, etc.). In some examples, the BIOS can take control and restore a default system configuration.

[0032] The instructions 216, when executed by a processor such as the processor 204, can include instructions to instruct the embedded controller to restore a default fan speed responsive to detection of a fan speed above a particular threshold. For instance, such a fan speed may indicate the processor 204 is overheating. The embedded controller can notify the BIOS of the overheating, and in response, the BIOS can restore a default system configuration. The embedded controller can restore the default fan speed because the processor 204 may cool down responsive to the default system configuration.

[0033] In some examples, the memory resource 206 can include instructions executable by the processor 204 to detect, using the embedded controller, system power limit configuration changes responsive to restoration of the default fan speed. For instance, if the default fan speed is restored before a default system configuration is restored, power limits may increase and may potentially fall outside of a particular internal operation configuration. The BIOS may use a checkpoint and/or routine (e.g., timer polling) to check the Interface periodically to determine if a system power limit configuration change has occurred, and the BIOS may take control of the interface. If a system power limit configuration change is not detected (e.g., the power limits remain within the particular internal operation configuration), a particular time period may be allowed to pass, and monitoring of the thermal settings associated with the processor 204 can resume.

[0034] Figure 3 illustrates an example system including a BIOS 318 and an embedded controller 320 for system configuration restoration in accordance with the present disclosure. In some examples, the system can include some of the same or similar elements as computing device 102 referenced in Figure 1 and/or memory resource 206 referenced in Figure 2.

[0035] The BIOS 318 can be communicatively coupled to the embedded controller 320, and an interface 322 can be located between the embedded controller and the processor 304. The interface 322, in some examples, can include MMIO and can be a processor performance interface. The processor 304 can be communicatively coupled the memory resource 306 (e.g., a non-transitory machine-readable medium, etc.), which can include instructions 324, 326, 328, 330 stored thereon and executable by the processor 304 to perform particular functions.

[0036] In some examples, the memory resource 306 can include instructions 324 that can be executed by the processor 304 to monitor, using the BIOS 318, a power level setting stored in the interface 322. The memory resource 306 can include instructions 326 that can be executed by the processor 304 to monitor, using the embedded controller 320, a fan speed performance associated with a thermal setting for the processor 304. For instance, the interface 322 may store a plurality of power levels. Some of those power levels can be monitored by the BIOS 318, while a power level associated with a highest processor power level (e.g., a power level of the processor 304 cannot exceed) may be monitored by the embedded controller 320. This may occur because the embedded controller may operate while the OS is not running and/or when the computing device experiences an adverse event, meaning monitoring can occur despite the occurrence of an adverse event. The embedded controller 320 can also monitor temperatures of the processor 304 via the interface 322. For example, based on the fan speed, the embedded controller 320 can determine if the processor 304 is running hot, cool, or as desired. In some examples, the power limit and the fan speed performance can be monitored using a checkpoint, a routine, or a combination thereof.

[0037] In some instances, the memory resource 306 can include instructions 328 that can be executed by the processor 304 to instruct the BIOS 318 to set a power limit policy for a system configuration responsive to detection of the power limit being outside of a particular internal operation configuration. For instance, if during monitoring, it is determined that a second power level limit is outside of a particular internal operation configuration, the BIOS may take control of the interface and set a power limit policy. For instance, the power limit policy may instruct a jump to the third power level, as the third power level may have a higher power level limit and can remain within a particular internal operation configuration. The embedded controller 320 can monitor a fourth power level and notify the BIOS should a power level limit approach or reach an internal operation configuration. With the fourth power limit, it may not be possible to go outside of the internal operation configuration without failure of the processor 304. While four power levels are described herein, more or fewer may be present in some examples. [0038] In some examples, the memory resource 306 can include instructions 330 that can be executed by the processor 304 to instruct the embedded controller to restore a default fan speed responsive to detection of a fan speed above a particular threshold, and in some examples, the embedded controller 320 can notify the BIOS 318 to change the system configuration responsive to the embedded controller 320 restoring the default fan speed. For instance, if it is determined the fan speed is too high, such that the processor 304 may be overheating, the embedded controller can restore the default fan speed and notify the BIOS 318 so the processor 304 does not overheat at the lower fan speed. For instance, restoration of a default system configuration may stabilize the processor 304, allowing it to run at a desired temperature with the default fan speed or lower fan speed.

[0039] Figure 4 illustrates an example flow chart of a method 440 for system configuration restoration in accordance with the present disclosure. At 442, the BIOS powers on, and at 458, the embedded controller powers on. This can occur simultaneously, near-simultaneously, or at different times. This can be triggered, for instance, when a computing device is booted. At 444, the BIOS can set and save processor (e.g., CPU) and system power limits and other performance configurations at saved to the interface. For instance, the BIOS can set power level limits for different power levels available to the processor. At 446, the OS can be booted.

[0040] At 448, the BIOS can monitor the interface and determine if a performance tuning driver is supported and working. If it is, the performance tuning driver can take control of thermal and performance tuning on the computing device at 450, and a period of time can pass at 452 before monitoring begins by the BIOS again at 448.

[0041] If the performance tuning driver is not supported and/or is not working, a current system configuration (e.g., AC/DC mode) can be checked at 454, and at 456, a policy and system power limit and other performance configurations can be set at 456. For instance, responsive to adverse events, the BIOS can take control of the interface and set policies and configurations to restore and improve performance of the processor and associated computing device. In some instances, the configurations may be restored default configurations. At 452, a period of time can pass before the BIOS resumes monitoring of the interface.

[0042] At 460, the embedded controller can set fan speed and other thermal configurations. For instance, the embedded controller can create thermal settings to maintain desired processor temperatures. The embedded controller can access thermal information and settings associated with the processor via the interface, which may be located between the processor and the embedded controller. At 462, the embedded controller can control fan speed performance such that the fan can operate at a default fan speed or other fan speed thermal setting. At 464, a determination can be made if the fan speed is exceeding a particular threshold, for instance if it increased from a default fan speed responsive to increased processor temperature, or if the processor temperature has risen above a particular threshold, and the fan speed cannot cool the processor effectively.

[0043] If it is determined that thresholds have not been crossed, the fan can continue to perform at its current speed for a particular period of time at 470 before monitoring of the interface and associated thermal settings resumes. If a particular threshold is exceeded, a fan speed and/or other thermal configurations can be restored at 466. For instance, if the fan speed has increased to account for increased processor temperature, the embedded controller can restore the fan speed to a default fan speed. At 468, the embedded controller can determine if a system configuration has changed responsive to the restoration at 466. For instance, if the processor is running hot, the system configuration can be changed (e.g., the BIOS can restore a default system configuration) so the processor does not run hot while the fan is operating at a default fan speed. If a system configuration changes, the BIOS can be notified, and the interface can be monitored by the BIOS. If the system configuration does not change, the fan can continue to perform at its current speed for a particular period of time at 470 before monitoring of the interface and associated thermal settings resumes.

[0044] The figures herein follow a numbering convention in which the first digit corresponds to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures can be identified by the use of similar digits. For instance, element “06” in Figure 2 may be referenced as “206” in Figure 2 and “306” in Figure 3. Elements shown in the various figures herein can be added, exchanged, and/or eliminated so as to provide a number of additional examples of the present disclosure. In addition, the proportion and the relative scale of the elements provided in the figures are intended to illustrate the examples of the present disclosure and should not be taken in a limiting sense. It is also to be understood that the terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” can include both singular and plural referents, unless the context clearly dictates otherwise. The designators can represent the same or different numbers of the particular features. Further, as used herein, "a number of an element and/or feature can refer to one or more of such elements and/or features.

[0045] In the foregoing detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how examples of the disclosure may be practiced. These examples are described in sufficient detail to enable those of ordinary skill In the art to practice the examples of this disclosure, and it is to be understood that other examples may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure.

Claims

What is claimed:

1. A computing device, comprising: a processor; and a memory resource storing instructions that when executed by the processor cause the processor to: monitor, by a basic input/output system (BIOS) and an embedded controller of the computing device, power limit settings associated with the processor; and responsive to an indication of a first adverse event by the BIOS and a second adverse event by the embedded controller, take control, by the BIOS, of an interface between the embedded controller and the processor to restore a default system configuration to the interface.

2. The computing device of claim 1 , further comprising the instructions executable to: monitor, by the embedded controller, a first power limit level setting associated with the processor; and monitor, by the BIOS, a second power limit level setting associated with the processor.

3. The computing device of claim 2, further comprising the instructions executable to: take control, by the BIOS, of the interface responsive to the first power limit level setting, the second power limit level setting, or both being outside of a respective particular internal operation configuration; and restore the default system configuration to the interface including a default processor power limit level.

4. The computing device of claim 1 , further comprising the instructions executable to: monitor, by the embedded controller, a fan speed associated with the processor; notify the BIOS responsive to the fan speed exceeding a particular threshold; and take control, by the BIOS, of the interface to restore the default system configuration to the interface including a default fan speed.

5. The computing device of claim 1 , wherein the interface comprises memory mapped input/output (MMIO).

6. The computing device of claim 1 , wherein the instructions executable to monitor power limit settings further comprise instructions executable to set a checkpoint to detect the first adverse event, the second adverse event, or both.

7. The computing device of claim 1 , wherein the instructions executable to monitor power limit settings further comprise instructions executable to set a routine to detect the first adverse event, the second adverse event, or both.

8. The computing device of claim 1 , wherein the first adverse event and the second adverse event comprises a performance tuning driver crash, a malicious attack on the interface, or a combination thereof.

9. A non-transitory machine-readable storage medium comprising instructions executable by a processor to: monitor, using a basic input/output system (BIOS) and an embedded controller, performance of an interface located between the processor and the embedded controller and a thermal setting for the processor; responsive to detection of failure at the interface, enable the BIOS to execute a processor handler to set a policy for a system power limit configuration; and responsive to detection of a fan speed associated with the processor above a particular threshold, instruct the embedded controller to restore a default fan speed.

10. The medium of claim 9, wherein the interface memory mapped input/output (MMIO).

11 . The medium of claim 9, further comprising the instructions executable to: detect, using the embedded controller, system power limit configuration changes responsive to restoration of the default fan speed; and responsive to detection of a system power limit configuration change, notify the BIOS.

12. The medium of claim 9, further comprising the instructions executable to: detect, using the embedded controller, system power limit configuration changes responsive to restoration of the default fan speed; and responsive to no detection of the system power limit configuration change, wait for a particular time period and resume monitoring of the thermal setting.

13. A system, comprising: a basic input/output system (BIOS); an embedded controller communicatively coupled to the BIOS; an interface between the embedded controller and a processor; a memory resource storing instructions that when executed by the processor cause the processor to: monitor, using the BIOS, a power level setting stored in the interface; monitor, using the embedded controller, a fan speed performance associated with a thermal setting for the processor; responsive to detection of the power limit being outside of a particular internal operation configuration, instruct the BIOS to set a power limit policy for a system configuration; and responsive to detection of a fan speed above a particular threshold, instruct the embedded controller to restore a default fan speed.

14. The system of claim 13, further comprising the embedded controller to notify the BIOS to change the system configuration responsive to the embedded controller restoring the default fan speed.

15. The system of claim 13, further comprising the instructions executable to monitor the power limit and the fan speed performance using a checkpoint, a routine, or a combination thereof.