WO2022042245A1 - 确定物理地址的方法及芯片系统 - Google Patents

确定物理地址的方法及芯片系统 Download PDF

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Publication number
WO2022042245A1
WO2022042245A1 PCT/CN2021/110624 CN2021110624W WO2022042245A1 WO 2022042245 A1 WO2022042245 A1 WO 2022042245A1 CN 2021110624 W CN2021110624 W CN 2021110624W WO 2022042245 A1 WO2022042245 A1 WO 2022042245A1
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Prior art keywords
address
virtual address
page table
entry
index
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PCT/CN2021/110624
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English (en)
French (fr)
Inventor
李开龙
梁辉
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华为技术有限公司
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Priority to US18/042,974 priority Critical patent/US12086071B2/en
Priority to EP21860085.6A priority patent/EP4191421B1/en
Publication of WO2022042245A1 publication Critical patent/WO2022042245A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/109—Address translation for multiple virtual address spaces, e.g. segmentation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1441—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a range
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/145—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G06F12/1491—Protection against unauthorised use of memory or access to memory by checking the subject access rights in a hierarchical protection system, e.g. privilege levels, memory rings
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G06F2212/1044—Space efficiency improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/651—Multi-level translation tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/657—Virtual address space management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]

Definitions

  • the present application relates to the field of operating systems, and in particular, to a method for determining a physical address and a chip system.
  • a chip system in an electronic device usually includes a central processing unit (CPU), a memory, and a coprocessor.
  • the CPU accesses the memory during operation to obtain or store data.
  • the coprocessor is used to perform functions that the CPU cannot or is not necessary. action performed.
  • the access address of the CPU accessing the memory is a virtual address, and the memory management unit (MMU) in the coprocessor can convert the virtual address to the corresponding physical address. Therefore, how to determine the physical address has received more and more attention.
  • MMU memory management unit
  • the MMU when the MMU receives a virtual address access request from the CPU to a certain virtual address space, the MMU can obtain the first-level page table corresponding to the virtual address space from the memory, and the first-level page table includes a plurality of Table entries, each table entry includes an association relationship between the table entry index address and the physical address.
  • the MMU obtains the corresponding entry index address from the primary page table based on the virtual address, and then determines the physical address corresponding to the virtual address from the primary page table based on the entry index address.
  • the starting virtual address of the virtual address space may not start from 0, and the entries included in the first-level page table are usually allocated according to the virtual address 0 to the maximum virtual address of the virtual address space, resulting in the first-level page table.
  • the number of entries in the page table is greater than the number of entries actually required by the virtual address space, and some entries with lower addresses in the first-level page table will not be used, and the memory space occupied by these entries will be Wasteful, low memory utilization.
  • the present application provides a method and a chip system for determining a physical address, so as to save memory occupied by page tables and improve memory utilization.
  • a first aspect provides a method for determining a physical address, comprising: when a first virtual address in a first virtual address space is obtained, determining an index address of a first table entry corresponding to the first virtual address; According to the index address of the first table entry, the first target physical address corresponding to the first virtual address is determined from the first page table;
  • the first page table is used to determine the physical address corresponding to each virtual address in the first virtual address space, and the starting virtual address of the first virtual address space is the same as the first virtual address in the first page table.
  • Two table entry index addresses correspond, the second table entry index address is greater than or equal to the base address of the first page table, and less than the quotient of dividing the starting virtual address by the size of the second virtual address space and the The sum of the base addresses of the first page table, the maximum entry index address of the first page table is less than the quotient of the maximum virtual address of the first virtual address space divided by the size of the second virtual address space and the The sum of the base addresses of the first page table, the second virtual address space is the virtual address space associated with any entry in the first page table, that is, the second virtual address space may be the first virtual address space. Subset.
  • a page table is a special data structure stored in memory.
  • the page table can be used as an index of the virtual address space and can include a plurality of table entries, each table entry includes an association relationship between the table entry index address and the physical address, wherein the physical address can be carried in the page table description of the table entry
  • the page table descriptor can be used to indicate the base address of the next-level page table or the base address of the physical address corresponding to the virtual address.
  • the MMU when the MMU obtains the first virtual address of the first virtual address space, it can determine the index address of the first entry corresponding to the first virtual address in the first page table, and according to the index address of the first entry , and determine the first target physical address corresponding to the first virtual address from the first page table.
  • the starting virtual address of the first virtual address space corresponds to the index address of the second entry in the first page table
  • the index address of the second table entry is greater than or equal to the base address of the first page table, and less than the sum of the quotient of the starting virtual address divided by the size of the second virtual address space and the base address of the first page table, and the maximum value of the first page table
  • the table entry index address is less than the sum of the quotient of the maximum virtual address of the first virtual address space divided by the size of the second virtual address space and the base address of the first page table, where the second virtual address space is the same as that in the first page table
  • the virtual address space associated with any table entry, so the first page table may at least include only table entries actually required by the first virtual address space, thereby saving memory and improving memory utilization.
  • the index address of the fourth entry is the index address of the entry corresponding to the starting virtual address of the first virtual address space in the second page table.
  • the number of the first entry may be greater than 0 and less than or equal to the number of the second entry.
  • the memory saved by the first page table compared with the second page table the number of first table entries * the amount of each table entry in the second page table (or the first page table) The size of the memory occupied.
  • the first virtual address space can also be obtained first. If the starting virtual address of the first virtual address space is greater than 0, the index address of the fourth entry in the second page table may be greater than the second page. The base address of the table, therefore, the page table descriptor of the second page table may be sequentially shifted downward by the number of table entries corresponding to the first table entry of the second page table to obtain the first page table.
  • the determining the index address of the first table entry corresponding to the first virtual address includes: determining a second virtual address based on the first virtual address and a first offset value, the first virtual address is greater than the second virtual address, and the first offset value is less than or equal to the starting virtual address of the first virtual address space; based on the second virtual address, the index address of the first entry is determined.
  • the first offset value the number of first entries corresponding to the first page table * the size of the second virtual address space associated with each entry of the first page table.
  • the MMU can determine the base address of the first page table, based on the base address of the first page table and the second virtual address.
  • Two virtual addresses which determine the index address of the first entry.
  • the search is performed sequentially from the first-level page table, the second-level page table, the third-level page table, etc., until the corresponding first target physical address is found. Therefore, the index address of the first table entry can be determined based on the base address of the first page table and the second virtual address in the following two possible implementation manners:
  • the first virtual address when the first page table is a first-level page table, the first virtual address may be compared with the virtual address space corresponding to each translation table base register (TTBR) . If the first virtual address belongs to a virtual address space corresponding to a certain TTBR (the first virtual space may be a subset of the virtual address space corresponding to the TTBR), the base of the first page table is obtained from the TTBR corresponding to the virtual address space site. The sum of the base address of the first page table and the index bits of the first-level page table in the second virtual address is determined as the index address of the first table entry.
  • TTBR translation table base register
  • the base address of the first page table may be determined based on the third page table, based on the base address of the first page table and the second virtual page table. address, to determine the index address of the first table entry, wherein the third page table is the previous page table adjacent to the first page table.
  • the MMU may need to look up multiple levels of page tables, and the first page table may be a page table of any level, that is, any page table can be Offset may occur. Then if the MMU first offsets the first virtual address through the ALU pair to obtain the second virtual address, and then determines the corresponding index address of the first table entry from the first page table based on the second virtual address, no matter the number of Those page tables in the hierarchical page table are offset, and the second virtual address obtained can be matched with the shifted page table by at least one offset of the first virtual address.
  • the MMU first determines the index address of the third table entry to be offset from the first virtual address, and then offsets the index address of the third table entry to obtain the index address of the first table entry, the offset can occur at each level.
  • the index address of the first entry is determined in the page table, the index address of the first entry is obtained by offsetting the index address of the third entry for the page table alone.
  • the method before the determining the index address of the first table entry corresponding to the first virtual address, the method further includes: acquiring page table offset flag information, where the page table offset flag information is used to indicate a The first page table determines the first target physical address corresponding to the first virtual address.
  • the page table offset flag information is indicated by an offset indicator bit in the translation table base control register (translation table base control register, TTBCR), and the acquiring page table offset flag information includes: when all When the value of the offset indication bit in the TTBCR is the first indicator, it is determined that the page table offset flag information is obtained.
  • TTBCR translation table base control register
  • the method further includes:
  • the value of the offset indicator bit in the TTBCR is set to the first indicator.
  • the first page table is a primary page table or a secondary page table.
  • the first virtual address space is a kernel-mode address space.
  • the address range of the kernel-mode address space may be 0x80000000-0xFFFFFFFF.
  • a second aspect provides a chip system, the chip system includes: at least one CPU, at least one memory and at least one coprocessor, the at least one coprocessor includes at least one MMU; the at least one MMU is used for: When an access request to the at least one memory initiated by the at least one CPU is received, and the access request carries the first virtual address of the first virtual address space, determine the first virtual address corresponding to the first virtual address The entry index address; according to the first entry index address, the first target physical address corresponding to the first virtual address is determined from the first page table; wherein the first page table is used to determine the first target physical address.
  • the address is greater than or equal to the base address of the first page table and less than the sum of the quotient of the starting virtual address divided by the size of the second virtual address space and the base address of the first page table.
  • the maximum entry index address of the page table is less than the sum of the quotient of the maximum virtual address of the first virtual address space divided by the size of the second virtual address space and the base address of the first page table, the second The virtual address space is a virtual address space associated with any entry in the first page table.
  • the at least one MMU includes at least one ALU:
  • the at least one ALU is configured to, based on the first virtual address and the first offset value, determine a second virtual address, where the first virtual address is greater than the second virtual address;
  • the at least one MMU is further configured to: determine the index address of the first table entry based on the second virtual address.
  • the at least one MMU is further configured to: determine, based on the first virtual address, the index address of the third entry to be offset; determine, based on the index address of the third entry and the second offset value, to determine The index address of the first entry and the index address of the third entry are greater than the index address of the first entry.
  • the at least one MMU further includes at least one TTBCR, and the at least one MMU is further used for:
  • Acquire page table offset flag information where the page table offset flag information is indicated by an offset indication bit in the at least one TTBCR.
  • the MMU further includes at least one TTBR, and each of the TTBRs may store a base address of a first-level page table.
  • the TTBCR may be used to indicate the selected TTBR when determining the physical addresses corresponding to the virtual addresses in different virtual address spaces, that is, to determine the TTBRs corresponding to different virtual address spaces.
  • the at least one coprocessor may be integrated in the at least one CPU.
  • a third aspect provides an electronic device, the electronic device comprising the chip system according to any one of the second aspect.
  • a fourth aspect provides a computer program product that, when the computer program product runs on an electronic device, causes the electronic device to perform the method described in any one of the above-mentioned first aspects.
  • 1 is a schematic structural diagram of an electronic device provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of a logical relationship between a virtual address space, a page table, and a physical address space provided by an embodiment of the present application;
  • FIG. 3 is a schematic structural diagram of a page table descriptor of a first-level page table provided by an embodiment of the present application
  • FIG. 4 is a schematic structural diagram of a page table descriptor of a two-level page table provided by an embodiment of the present application
  • FIG. 5 is a schematic diagram of another logical relationship between a virtual address space, a page table, and a physical address space provided by an embodiment of the present application;
  • mapping initialization setting provided by an embodiment of the present application
  • FIG. 7 is a schematic diagram of a logical relationship between a virtual address space and a page table according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a page table provided by an embodiment of the present application.
  • FIG. 9 is a flowchart of a method for determining a physical address provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of another logical relationship between a virtual address space, a page table, and a physical address space provided by an embodiment of the present application;
  • FIG. 11 is a schematic diagram of another logical relationship between a virtual address space, a page table, and a physical address space provided by an embodiment of the application;
  • FIG. 12 is a schematic structural diagram of a chip system provided by an embodiment of the application.
  • FIG. 13 is a schematic structural diagram of another chip system provided by an embodiment of the present application.
  • the method for determining a physical address provided by the embodiments of the present application can be applied to mobile phones, tablet computers, wearable devices, in-vehicle devices, augmented reality (AR)/virtual reality (VR) devices, laptop computers, super mobile devices
  • AR augmented reality
  • VR virtual reality
  • electronic devices such as a personal computer (ultra-mobile personal computer, UMPC), netbook, personal digital assistant (personal digital assistant, PDA), server, etc.
  • the embodiments of the present application do not impose any restrictions on the specific type of the electronic device.
  • FIG. 1 is a schematic structural diagram of an electronic device 100 provided by an embodiment of the present application.
  • the electronic device 100 may include a CPU 110, an external memory interface 120, an internal memory 121, and a universal serial bus (USB) interface 130, Charging management module 140, power management module 141, battery 142, antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, audio module 170, speaker 170A, receiver 170B, microphone 170C, headphone jack 170D, sensor module 180, Button 190, motor 191, indicator 192, camera 193, display screen 194, and user identification module (subscriber identification module, SIM) card interface 195 and so on.
  • SIM subscriber identification module
  • the sensor module 180 may include a pressure sensor, a gyroscope sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor L, a bone conduction sensor, and the like.
  • the structures illustrated in the embodiments of the present application do not constitute a specific limitation on the electronic device 100 .
  • the electronic device 100 may include more or less components than shown, or combine some components, or separate some components, or arrange different components.
  • the illustrated components may be implemented in hardware, software, or a combination of software and hardware.
  • the CPU 110 may include one or more processing units, for example, the CPU 110 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processor) , ISP), controller, memory, video codec, digital signal processor (digital signal processor, DSP), baseband processor, and/or neural-network processing unit (neural-network processing unit, NPU), etc.
  • application processor application processor, AP
  • modem processor graphics processor
  • graphics processor graphics processor
  • image signal processor image signal processor
  • ISP image signal processor
  • controller memory
  • video codec digital signal processor
  • DSP digital signal processor
  • baseband processor baseband processor
  • neural-network processing unit neural-network processing unit
  • the controller may be the nerve center and command center of the electronic device 100 .
  • the controller can generate an operation control signal according to the instruction operation code and timing signal, and complete the control of fetching and executing instructions.
  • CPU 110 may include one or more interfaces.
  • the interface may include an integrated circuit (inter-integrated circuit, I2C) interface, an integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous transceiver (universal asynchronous transmitter) receiver/transmitter, UART) interface, mobile industry processor interface (MIPI), general-purpose input/output (GPIO) interface, subscriber identity module (SIM) interface, and / or universal serial bus (universal serial bus, USB) interface, etc.
  • I2C integrated circuit
  • I2S integrated circuit built-in audio
  • PCM pulse code modulation
  • PCM pulse code modulation
  • UART universal asynchronous transceiver
  • MIPI mobile industry processor interface
  • GPIO general-purpose input/output
  • SIM subscriber identity module
  • USB universal serial bus
  • the I2C interface is a bidirectional synchronous serial bus that includes a serial data line (SDA) and a serial clock line (SCL).
  • CPU 110 may contain multiple sets of I2C buses.
  • the CPU 110 can be respectively coupled to a touch sensor, a charger, a flash, a camera 193 and the like through different I2C bus interfaces.
  • the CPU 110 can couple the touch sensor through the I2C interface, so that the CPU 110 communicates with the touch sensor through the I2C bus interface, so as to realize the touch function of the electronic device 100 .
  • the I2S interface can be used for audio communication.
  • CPU 110 may contain multiple sets of I2S buses.
  • the CPU 110 can be coupled with the audio module 170 through the I2S bus to implement communication between the CPU 110 and the audio module 170 .
  • the audio module 170 can transmit audio signals to the wireless communication module 160 through the I2S interface, so as to realize the function of answering calls through a Bluetooth headset.
  • the PCM interface can also be used for audio communications, sampling, quantizing and encoding analog signals.
  • the audio module 170 and the wireless communication module 160 may be coupled through a PCM bus interface.
  • the audio module 170 can also transmit audio signals to the wireless communication module 160 through the PCM interface, so as to realize the function of answering calls through the Bluetooth headset. Both the I2S interface and the PCM interface can be used for audio communication.
  • the UART interface is a universal serial data bus used for asynchronous communication.
  • the bus may be a bidirectional communication bus. It converts the data to be transmitted between serial communication and parallel communication.
  • a UART interface is typically used to connect the CPU 110 and the wireless communication module 160 .
  • the CPU 110 communicates with the Bluetooth module in the wireless communication module 160 through the UART interface to realize the Bluetooth function.
  • the audio module 170 can transmit audio signals to the wireless communication module 160 through the UART interface, so as to realize the function of playing music through the Bluetooth headset.
  • the MIPI interface can be used to connect the CPU 110 with peripheral devices such as the display screen 194 and the camera 193 .
  • MIPI interfaces include camera serial interface (CSI), display serial interface (DSI), etc.
  • the CPU 110 and the camera 193 communicate through a CSI interface to implement the photographing function of the electronic device 100 .
  • the CPU 110 communicates with the display screen 194 through the DSI interface to realize the display function of the electronic device 100 .
  • the GPIO interface can be configured by software.
  • the GPIO interface can be configured as a control signal or as a data signal.
  • the GPIO interface can be used to connect the CPU 110 with the camera 193 , the display screen 194 , the wireless communication module 160 , the audio module 170 , the sensor module 180 and the like.
  • the GPIO interface can also be configured as I2C interface, I2S interface, UART interface, MIPI interface, etc.
  • the USB interface 130 is an interface that conforms to the USB standard specification, and may specifically be a Mini USB interface, a Micro USB interface, a USB Type C interface, and the like.
  • the USB interface 130 can be used to connect a charger to charge the electronic device 100, and can also be used to transmit data between the electronic device 100 and peripheral devices. It can also be used to connect headphones to play audio through the headphones.
  • the interface can also be used to connect other electronic devices 100, such as AR devices and the like.
  • the interface connection relationship between the modules illustrated in the embodiments of the present application is only a schematic illustration, and does not constitute a structural limitation of the electronic device 100 .
  • the electronic device 100 may also adopt different interface connection manners in the foregoing embodiments, or a combination of multiple interface connection manners.
  • the charging management module 140 is used to receive charging input from the charger.
  • the charger may be a wireless charger or a wired charger.
  • the charging management module 140 may receive charging input from the wired charger through the USB interface 130 .
  • the charging management module 140 may receive wireless charging input through a wireless charging coil of the electronic device 100 . While the charging management module 140 charges the battery 142 , the electronic device 100 can also be powered by the power management module 141 .
  • the power management module 141 is used to connect the battery 142 , the charging management module 140 and the CPU 110 .
  • the power management module 141 receives input from the battery 142 and/or the charging management module 140 and supplies power to the CPU 110 , the internal memory 121 , the external memory, the display screen 194 , the camera 193 , and the wireless communication module 160 .
  • the power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle times, battery health status (leakage, impedance).
  • the power management module 141 may also be provided in the CPU 110 .
  • the power management module 141 and the charging management module 140 may also be provided in the same device.
  • the wireless communication function of the electronic device 100 may be implemented by the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modulation and demodulation processor, the baseband processor, and the like.
  • Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals.
  • Each antenna in electronic device 100 may be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization.
  • the antenna 1 can be multiplexed as a diversity antenna of the wireless local area network. In other embodiments, the antenna may be used in conjunction with a tuning switch.
  • the mobile communication module 150 may provide wireless communication solutions including 2G/3G/4G/5G etc. applied on the electronic device 100 .
  • the mobile communication module 150 may include at least one filter, switch, power amplifier, low noise amplifier (LNA) and the like.
  • the mobile communication module 150 can receive electromagnetic waves from the antenna 1, filter and amplify the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation.
  • the mobile communication module 150 can also amplify the signal modulated by the modulation and demodulation processor, and then turn it into an electromagnetic wave for radiation through the antenna 1 .
  • at least part of the functional modules of the mobile communication module 150 may be provided in the CPU 110 .
  • at least part of the functional modules of the mobile communication module 150 may be provided in the same device as at least part of the modules of the CPU 110 .
  • the modem processor may include a modulator and a demodulator.
  • the modulator is used to modulate the low frequency baseband signal to be sent into a medium and high frequency signal.
  • the demodulator is used to demodulate the received electromagnetic wave signal into a low frequency baseband signal. Then the demodulator transmits the demodulated low-frequency baseband signal to the baseband processor for processing.
  • the low frequency baseband signal is processed by the baseband processor and passed to the application processor.
  • the application processor outputs sound signals through audio devices (not limited to the speaker 170A, the receiver 170B, etc.), or displays images or videos through the display screen 194 .
  • the modem processor may be a stand-alone device.
  • the modulation and demodulation processor may be independent of the CPU 110, and may be provided in the same device as the mobile communication module 150 or other functional modules.
  • the wireless communication module 160 can provide applications on the electronic device 100 including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), bluetooth (BT), global navigation satellites Wireless communication solutions such as global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared technology (IR).
  • WLAN wireless local area networks
  • BT Bluetooth
  • GNSS global navigation satellite system
  • FM frequency modulation
  • NFC near field communication
  • IR infrared technology
  • the wireless communication module 160 may be one or more devices integrating at least one communication MMU.
  • the wireless communication module 160 receives electromagnetic waves via the antenna 2 , frequency modulates and filters the electromagnetic wave signals, and sends the processed signals to the CPU 110 .
  • the wireless communication module 160 can also receive the signal to be sent from the CPU 110 , perform frequency modulation on it, amplify the signal, and then convert it into an electromagnetic wave for radiation through the antenna 2 .
  • the antenna 1 of the electronic device 100 is coupled with the mobile communication module 150, and the antenna 2 is coupled with the wireless communication module 160, so that the electronic device 100 can communicate with the network and other devices through wireless communication technology.
  • the wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), broadband Code Division Multiple Access (WCDMA), Time Division Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), BT, GNSS, WLAN, NFC , FM, and/or IR technology, etc.
  • the GNSS may include a global positioning system (global positioning system, GPS), a global navigation satellite system (GLONASS), a Beidou navigation satellite system (BDS), a quasi-zenith satellite system (quasi -zenith satellite system, QZSS) and/or satellite based augmentation systems (SBAS).
  • GPS global positioning system
  • GLONASS global navigation satellite system
  • BDS Beidou navigation satellite system
  • QZSS quasi-zenith satellite system
  • SBAS satellite based augmentation systems
  • the electronic device 100 implements a display function through a GPU, a display screen 194, an application processor, and the like.
  • the GPU is a microprocessor for image processing, and is connected to the display screen 194 and the application processor.
  • the GPU is used to perform mathematical and geometric calculations for graphics rendering.
  • CPU 110 may include one or more GPUs that execute program instructions to generate or change display information.
  • Display screen 194 is used to display images, videos, and the like.
  • Display screen 194 includes a display panel.
  • the display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode or an active-matrix organic light-emitting diode (active-matrix organic light).
  • LED diode AMOLED
  • flexible light-emitting diode flexible light-emitting diode (flex light-emitting diode, FLED), Miniled, MicroLed, Micro-oLed, quantum dot light-emitting diode (quantum dot light emitting diodes, QLED) and so on.
  • the electronic device 100 may include one or N display screens 194 , where N is a positive integer greater than one.
  • the electronic device 100 may implement a shooting function through an ISP, a camera 193, a video codec, a GPU, a display screen 194, an application processor, and the like.
  • the ISP is used to process the data fed back by the camera 193 .
  • the shutter is opened, the light is transmitted to the camera photosensitive element through the lens, the light signal is converted into an electrical signal, and the camera photosensitive element transmits the electrical signal to the ISP for processing, and converts it into an image visible to the naked eye.
  • ISP can also perform algorithm optimization on image noise, brightness and skin tone.
  • ISP can also optimize the exposure, color temperature and other parameters of the shooting scene.
  • the ISP may be provided in the camera 193 .
  • Camera 193 is used to capture still images or video.
  • the object is projected through the lens to generate an optical image onto the photosensitive element.
  • the photosensitive element may be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor.
  • CMOS complementary metal-oxide-semiconductor
  • the photosensitive element converts the optical signal into an electrical signal, and then transmits the electrical signal to the ISP to convert it into a digital image signal.
  • the ISP outputs the digital image signal to the DSP for processing.
  • DSP converts digital image signals into standard RGB, YUV and other formats of image signals.
  • the electronic device 100 may include 1 or N cameras 193 , where N is a positive integer greater than 1.
  • a digital signal processor is used to process digital signals, in addition to processing digital image signals, it can also process other digital signals. For example, when the electronic device 100 selects a frequency point, the digital signal processor is used to perform Fourier transform on the frequency point energy and so on.
  • Video codecs are used to compress or decompress digital video.
  • the electronic device 100 may support one or more video codecs.
  • the electronic device 100 can play or record videos of various encoding formats, such as: Moving Picture Experts Group (moving picture experts group, MPEG) 1, MPEG2, MPEG3, MPEG4 and so on.
  • MPEG Moving Picture Experts Group
  • MPEG2 moving picture experts group
  • MPEG3 MPEG4
  • MPEG4 Moving Picture Experts Group
  • the NPU is a neural-network (NN) computing processor.
  • NN neural-network
  • Applications such as intelligent cognition of the electronic device 100 can be implemented through the NPU, such as image recognition, face recognition, speech recognition, text understanding, and the like.
  • the external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100 .
  • the external memory card communicates with the CPU 110 through the external memory interface 120 to realize the data storage function. For example to save files like music, video etc in external memory card.
  • Internal memory 121 may be used to store computer executable program code, which includes instructions.
  • the CPU 110 executes various functional applications and data processing of the electronic device 100 by executing the instructions stored in the internal memory 121 .
  • the internal memory 121 may include a storage program area and a storage data area.
  • the storage program area can store an operating system, an application program required for at least one function (such as a sound playback function, an image playback function, etc.), and the like.
  • the storage data area may store data (such as audio data, phone book, etc.) created during the use of the electronic device 100 and the like.
  • the internal memory 121 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, universal flash storage (UFS), and the like.
  • the MMU 111 may be provided in a coprocessor (not shown in FIG. 1 ), which may be provided between the CPU 110 and the buses of the internal memory 121 and the external memory interface 120 .
  • a virtual address can be provided, and the MMU maps the virtual address to a physical address, so that the CPU 110 can read or write to the internal memory 121 based on the physical address. input data.
  • the virtual address is a certain address in the address space that can be recognized or generated by the operating system in the electronic device, and its size range can be determined by the number of bits of the operating system running in the CPU 110 . For example, if the operating system running in the CPU 110 is 32 bits, the virtual address is also 32 bits, and its address range is 0-0xFFFFFFFF (4GB); if the operating system running in the CPU 110 is 64 bits, the virtual address is also 64 bits, its The address space is 0-0xFFFFFFFFFFFFFFFFFF (16EB).
  • the virtual address may be divided into multiple virtual address spaces according to actual needs, such as a user-mode address space and a kernel-mode address space.
  • User mode address space can be accessed by user mode programs (such as read, write, open, close or draw) and kernel mode programs (such as process management, storage management, file management or device management), and kernel mode address space can be accessed only by kernel mode. Program access at runtime.
  • the physical address may be a certain address in the address space actually possessed by hardware storage devices such as the internal memory 121 .
  • the address space of the physical address may be smaller than the address space of the virtual address. For example, when the size of the address space of the virtual address may be 4GB, the size of the address space of the physical address may be 256MB.
  • the MMU 111 may include several ALUs 112 (only 1 is shown in FIG. 1 ), TTBCR 113 and several TTBRs 114 (only 2 are shown in FIG. 1 ).
  • TTBCR113 can be used to store TTBR-related control information, such as specifying the TTBR114 corresponding to the kernel-mode address space and the user-mode address space.
  • TTBR-related control information such as specifying the TTBR114 corresponding to the kernel-mode address space and the user-mode address space.
  • the reserved bits in TTBCR113 Whether to offset the virtual address address before mapping.
  • the TTBR 114 can be used to indicate the base address of the first-level page table (ie, the entry index address of the first entry in the first-level page table).
  • the ALU 112 can be used to perform logical operations, such as shifting virtual addresses up or down.
  • the electronic device 100 may implement audio functions through an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, an application processor, and the like. Such as music playback, recording, etc.
  • the audio module 170 is used for converting digital audio information into analog audio signal output, and also for converting analog audio input into digital audio signal. Audio module 170 may also be used to encode and decode audio signals. In some embodiments, the audio module 170 may be provided in the CPU 110 , or some functional modules of the audio module 170 may be provided in the CPU 110 .
  • Speaker 170A also referred to as a "speaker" is used to convert audio electrical signals into sound signals.
  • the electronic device 100 can listen to music through the speaker 170A, or listen to a hands-free call.
  • the receiver 170B also referred to as "earpiece" is used to convert audio electrical signals into sound signals.
  • the voice can be answered by placing the receiver 170B close to the human ear.
  • the microphone 170C also called “microphone” or “microphone” is used to convert sound signals into electrical signals.
  • the user can make a sound by approaching the microphone 170C through a human mouth, and input the sound signal into the microphone 170C.
  • the electronic device 100 may be provided with at least one microphone 170C. In other embodiments, the electronic device 100 may be provided with two microphones 170C, which can implement a noise reduction function in addition to collecting sound signals. In other embodiments, the electronic device 100 may further be provided with three, four or more microphones 170C to collect sound signals, reduce noise, identify sound sources, and implement directional recording functions.
  • the earphone jack 170D is used to connect wired earphones.
  • the earphone interface 170D may be a USB interface 130, or a 3.5mm open mobile terminal platform (open mobile terminal platform, OMTP) standard interface, a cellular telecommunications industry association of the USA (CTIA) standard interface.
  • OMTP open mobile terminal platform
  • CTIA cellular telecommunications industry association of the USA
  • the keys 190 include a power-on key, a volume key, and the like. Keys 190 may be mechanical keys. It can also be a touch key.
  • the electronic device 100 may receive key inputs and generate key signal inputs related to user settings and function control of the electronic device 100 .
  • Motor 191 can generate vibrating cues.
  • the motor 191 can be used for vibrating alerts for incoming calls, and can also be used for touch vibration feedback.
  • touch operations acting on different applications can correspond to different vibration feedback effects.
  • the motor 191 can also correspond to different vibration feedback effects for touch operations on different areas of the display screen 194 .
  • Different application scenarios for example: time reminder, receiving information, alarm clock, games, etc.
  • the touch vibration feedback effect can also support customization.
  • the indicator 192 can be an indicator light, which can be used to indicate the charging state, the change of the power, and can also be used to indicate a message, a missed call, a notification, and the like.
  • the SIM card interface 195 is used to connect a SIM card.
  • the SIM card can be contacted and separated from the electronic device 100 by inserting into the SIM card interface 195 or pulling out from the SIM card interface 195 .
  • the electronic device 100 may support 1 or N SIM card interfaces, where N is a positive integer greater than 1.
  • the SIM card interface 195 can support Nano SIM card, Micro SIM card, SIM card and so on. Multiple cards can be inserted into the same SIM card interface 195 at the same time. The types of the plurality of cards may be the same or different.
  • the SIM card interface 195 can also be compatible with different types of SIM cards.
  • the SIM card interface 195 is also compatible with external memory cards.
  • the electronic device 100 interacts with the network through the SIM card to implement functions such as call and data communication.
  • the electronic device 100 employs an eSIM, ie: an embedded SIM card.
  • the eSIM card can be embedded in the electronic device 100 and cannot be separated from the electronic device 100 .
  • the software system of the electronic device 100 may adopt a layered architecture, an event-driven architecture, a microkernel architecture, a microservice architecture, or a cloud architecture.
  • the MMU converts the virtual address mapping into the corresponding physical address, that is, the access to the virtual address is converted to the access to the physical memory, the purpose is to save the physical address space and protect the physical address space.
  • the MMU may adopt a paging mechanism to manage the virtual address space in units of pages, and each page may include a virtual address space of a preset size.
  • the virtual address space may include more than one virtual address, and one virtual address space may correspond to one page table set.
  • the page table set may be used to determine the physical address corresponding to the virtual address of the virtual address space, and the page table set may include a primary page table, or the page table set may include a primary page table and at least one secondary page table A level page table, the secondary page table may include a level two page table, a level three page table or even a lower level page table.
  • the MMU may determine the physical address corresponding to the virtual address through at least one level of mapping, and the number of levels of the mapping is consistent with the number of levels of the page table set.
  • the first-level mapping when the physical address corresponding to the virtual address is determined through the first-level mapping, the first-level mapping is called segment mapping, and the page table set may only include the first-level page table; when the two-level mapping is used to determine the physical address corresponding to the virtual address In the case of physical addresses, the two-level mapping is called page mapping, and the page table set may include one first-level page table and at least one second-level page table.
  • the page table is a special data structure stored in memory.
  • the page table can be used as an index of the virtual address space and can include a plurality of table entries, each table entry includes an association relationship between the table entry index address and the physical address, wherein the physical address can be carried in the page table description of the table entry
  • the page table descriptor can be used to indicate the base address of the next-level page table or the base address of the physical address corresponding to the virtual address.
  • the page table descriptor in the first-level page table is used to indicate the segment base address, which is the base address of the physical address corresponding to the virtual address; in the second-level mapping, the first-level The page table descriptor in the page table is used to indicate the base address of the secondary page table, and the page table descriptor in the secondary page table can be used to indicate the page base address, which is the page base address corresponding to the virtual address. Physical address base address.
  • the page table descriptor can also be used to indicate more information related to virtual-real mapping of addresses.
  • the page table descriptor also includes a mapping level indication bit and a granularity indication bit, where the mapping level number
  • the indication bit can be used to indicate the number of mapping levels of the current mapping or whether there is a mapping level indication bit of the next level of mapping (that is, one-level mapping or two-level mapping), and the granularity indication bit can be used to indicate the granularity of segment mapping or page mapping Indicates the bit (ie the size of the virtual address space associated with the page table).
  • FIG. 2 is a schematic diagram of a logical relationship among a virtual address space, a page table, and a physical address space according to an embodiment of the present application.
  • the address range of the virtual address space is [0x00000000, 0xFFFFFF], and the size of the virtual address space is 4GB.
  • the address range of the user mode address space is [0x00000000, 0x80000000) (that is, the 0th GB-2nd GB), the kernel mode address space
  • the address range is [0x80000000-0xFFFFFFFF] (that is, the 2nd GB-4th GB), the address range of the physical address space (0x40000000 ⁇ 0XBFFFFFFF), and the size is 2GB.
  • the base address of page table 1 stored in TTBR1 is set through TTBCR, and the virtual address of the kernel-mode address space 201 is determined by page table 1 to map to the physical address of the physical address space, based on the base address of page table 2 stored in TTBR0, by Page Table 2 determines the mapping of virtual addresses in the user mode address space to physical addresses in the physical address space.
  • FIG. 3 is a schematic diagram of a page table descriptor of a first-level page table provided by an embodiment of the present application.
  • the 0-1 bits of the page table descriptor are the mapping level indication bits, when the [1:0] bits (that is, the [1] and [0] bits) are 10
  • the current mapping is a first-level mapping (ie segment mapping)
  • the segment base address stored in the highest 12 or 8 bits in the page table descriptor
  • the [1:0] bit is 01
  • the current mapping is a two-level mapping ( That is, page mapping)
  • the highest 22 bits in the page table descriptor store the base address of the secondary page table.
  • the 18th bit of the page table descriptor can be the mapping granularity indicator bit.
  • the mapping granularity is 1MB.
  • the highest 12-bit segment base address stored in the page table descriptor when the [18 When the ] bit is 1, the mapping granularity is 16MB, and the segment base address stored in the highest 8 bits in the page table descriptor.
  • FIG. 4 is a schematic structural diagram of a page table descriptor of a two-level page table according to an embodiment of the present application.
  • bits [1:0] in the page table descriptor are mapping granularity indication bits. Among them, when the [1:0] bit is 10 or 11, the mapping granularity is 4KB, and the highest 20 bits of the page descriptor are the page base address; when the [1:0] bit is 01, the mapping granularity is 64KB, and the page The highest 16 bits of the descriptor are the page base address.
  • each bit of the virtual address in the virtual address space also has different meanings according to the different mapping stages.
  • the virtual address may include at least one level of page table index bits and physical address offset bits.
  • the index bits of each level can be used to indicate the page table descriptor corresponding to the virtual address in the page table of this level
  • the physical address offset bit can be used to indicate the corresponding position of the virtual address in the specific position of the page table of this level.
  • the offset of the physical address, the sum of the physical address offset bit and the physical address base address (such as segment base address or page base address) determined by the page table set corresponding to the virtual address space is the virtual address. the corresponding physical address.
  • the operating system in the electronic device is 32 bits, and the first-level mapping is adopted, and the mapping granularity is 1MB.
  • the bits [31:20] in the virtual address are the first-level page table index bits, and the bits [19:0] are the segment offsets shift.
  • the mapping granularity is 4KB
  • the bits [31:20] in the second virtual address are the index bits of the first-level page table
  • the bits [19:12] are the index bits of the second-level page table
  • the bits [19:12] are the index bits of the second-level page table.
  • Bits [11:0] are page offset bits.
  • the starting virtual address of the virtual address space may not start from 0, and in some embodiments, the page table is used as an index of the virtual address space, and the entries included are from 0 to this according to the virtual address.
  • the maximum virtual address of the virtual address space is allocated, so the number of entries in the page table will be greater than the number of entries actually required by the virtual address space, and some entries in the page table with lower entry index addresses will not be If they are used, the memory space occupied by these entries will be wasted, and the memory utilization rate will be low.
  • FIG. 5 is a schematic diagram of a logical relationship among a virtual address space, a page table and a physical address space.
  • the address range of the kernel state address space 501 is [0x80000000, 0xFFFFFFFF]
  • the address range of the physical address space 503 is [0x40000000, 0XBFFFFFFF]
  • the first-level page table 502 is used for mapping (ie, the first-level page table 502 Corresponding to the kernel state address space 501)
  • These 2K entries include page table descriptors, and the 2K entries in the low address direction [0X000, 0X7FF] are not used, so the 2K entries in the low address direction occupy 8KB Memory is wasted.
  • secondary page tables such as the second-level page table and the third-level page table.
  • an embodiment of the present application provides a method for determining a physical address.
  • the MMU when the MMU obtains the first virtual address of the first virtual address space, it can determine the index address of the first entry corresponding to the first virtual address in the first page table, and according to the index address of the first entry , and determine the first target physical address corresponding to the first virtual address from the first page table.
  • the starting virtual address of the first virtual address space corresponds to the index address of the second entry in the first page table
  • the index address of the second table entry is greater than or equal to the base address of the first page table, and less than the sum of the quotient of the starting virtual address divided by the size of the second virtual address space and the base address of the first page table, and the maximum value of the first page table
  • the table entry index address is less than the sum of the quotient of the maximum virtual address of the first virtual address space divided by the size of the second virtual address space and the base address of the first page table, where the second virtual address space is the same as that in the first page table
  • the virtual address space associated with any table entry, so the first page table may at least include only table entries actually required by the first virtual address space, thereby saving memory and improving memory utilization.
  • the MMU Before the MMU executes the method for determining a physical address provided by the embodiment of the present application for the first time, the MMU needs to be initialized.
  • FIG. 6 is a flowchart of a mapping initialization setting provided by an embodiment of the present application.
  • the page table descriptors in the page table can be descended according to their positions in the page table. (ie low address direction) offset, thereby reducing the number of unused entries, and the saved storage space can be released or used as ordinary memory.
  • the second page table corresponding to the first virtual address space can be obtained, and if the index address of the fourth table entry is greater than the base address of the second page table, it can be determined that there is an unused table entry in the second page table,
  • the page table descriptor in the second page table can be shifted downward by the number of entries of the first table in turn, and the number of table entries of the first table in the high address part of the second page table can be deleted, so as to obtain the same number as the first table entry.
  • a first page table corresponding to a virtual address space can be obtained, and if the index address of the fourth table entry is greater than the base address of the second page table, it can be determined that there is an unused table entry in the second page table.
  • the page table descriptor in the second page table can be shifted downward by the number of entries of the first table in turn, and the number of table entries of the first table in the high address part of the second page table can be deleted, so as to obtain the same number as the first table entry.
  • the first page table and the second page table may be used to determine the physical address corresponding to each virtual address in the first virtual address space.
  • the index address of the fourth table entry is the index address of the table entry corresponding to the starting virtual address of the first virtual address space in the second page table.
  • the first page table may include at least one entry, the starting virtual address of the first virtual address space corresponds to the index address of the second entry of the first page table, and the index address of the second entry is greater than or equal to the base of the first page table. address, and is less than the sum of the quotient of the starting virtual address of the first virtual address space and the size of the second virtual address space associated with the entry and the base address of the first page table, the largest entry index address of the first page table Less than the sum of the quotient of the maximum virtual address of the first virtual address space divided by the size of the second virtual address space and the base address of the first page table, the second virtual address space may be the first page table or every second page table.
  • the virtual address space corresponding to each entry, and the second virtual address space may be a subset of the first virtual address space.
  • the number of the first entry may be greater than 0 and less than or equal to the number of the second entry.
  • the memory saved by the first page table compared with the second page table the number of first table entries * the amount of each table entry in the second page table (or the first page table) The size of the memory occupied.
  • FIG. 7 is a schematic diagram of a logical relationship between a virtual address space and a page table according to an embodiment of the present application.
  • the virtual address space associated with the second page table 720 is the first virtual address space 710
  • the second page table 720 includes a plurality of table entries 721
  • the virtual address space associated with each table entry 721 is the first virtual address space 710.
  • Two virtual address spaces 711, the second virtual address space is a subset of the first virtual address space
  • the size of the first virtual address space the number of entries 721*the size of the second virtual address space.
  • the first virtual address space can also be obtained first. If the starting virtual address of the first virtual address space is greater than 0, the index address of the fourth entry in the second page table may be greater than the second page.
  • the base address of the table therefore, the page table descriptor of the second page table can be sequentially shifted downward by the number of table entries corresponding to the first table entry of the second page table to obtain the first page table.
  • the first virtual address space is a kernel state address space.
  • its storage space is 2GB
  • the address range is [0x80000000-0xFFFFFFFF]
  • the starting virtual address is 0x80000000
  • the first virtual address space corresponding to this kernel state address space is 2GB.
  • the two page tables are the first-level page table 502, in which each table entry corresponds to a second virtual address space of 1MB, each table entry occupies 4B of memory, and the fourth table in the first-level page table 502 corresponds to the starting virtual address
  • the item index address is 0x800.
  • the first page table 801 is obtained as the first-level page table 801, as shown in FIG. 8 .
  • the index address of the second entry is 0X00
  • the physical address associated with 0X00 is the same as the physical address associated with 0X800 in the first-level page table 502 in FIG.
  • the offset manner of the secondary page tables may be similar to the offset manner of the primary page table, which is not repeated in this embodiment of the present application.
  • the register configuration may include adding an offset indication bit to the reserved bits of the TTBCR and setting the offset indication bit as the first indicator or the second indicator, and may also include specifying the TTBR that is currently performing virtual address mapping.
  • an ALU for implementing virtual address offset operations can be added to the MMU.
  • the TTBR currently used for address virtual-real mapping can also be indicated by TTBCR.
  • the offset indication bit can be configured through the following command to indicate that the offset function is enabled.
  • orr is the position 1 instruction, which is used to perform logical OR operation on two operands, and put the result into the destination register, orr r12, #(1 ⁇ 3) can indicate that r12 is set to 1;
  • mcr is co-processing
  • the operation instruction of the processor CP15, TTBCR can be located in the coprocessor CP15, mcr p15, 0, r12, c2, c0, 2 means to write r12 into c1 of CP15.
  • the offset1 of the TTBCR113 can be set to 1, thereby instructing to enable the offset function.
  • the offset indication bit in the TTBCR is used to indicate whether to offset the virtual address.
  • the offset indication bit is 1, it can be used as an indication to offset the virtual address.
  • Moved page table offset flag information it can be understood that, in practical applications, other forms of information may be used as the page table offset flag information, and the embodiment of the present application does not specifically limit the form of the page table offset flag information.
  • S601 may also be executed at any timing before S603.
  • the MMU can determine the physical address through the following steps.
  • FIG. 9 is a flowchart of a method for determining a physical address provided by an embodiment of the present application. It should be noted that the method is not limited to the specific sequence shown in FIG. 9 and the following, and it should be understood that, in other embodiments, the sequence of some steps of the method may be exchanged with each other according to actual needs, or some steps of the method may be exchanged. It can also be omitted or deleted.
  • the method includes the following steps:
  • the MMU acquires a first virtual address in a first virtual address space.
  • the MMU can obtain the virtual address from the CPU. And since for the first virtual address space, the associated first page table is the page table after the offset, then determining the first target physical address corresponding to the first virtual address in the first virtual address space is the same as determining When the physical addresses corresponding to the virtual addresses that do not belong to the first virtual address space, different methods may also be adopted. Therefore, in order to facilitate the subsequent method of determining the physical address corresponding to the virtual address, it may be determined whether the virtual address is the first virtual address in the first virtual address space.
  • the MMU may determine the address range of the first virtual address space in advance, and compare the obtained virtual address with the starting virtual address and ending virtual address of the first virtual address space. If the virtual address is greater than or equal to the starting virtual address and If it is less than or equal to the end virtual address, the virtual address may be determined as the first virtual address.
  • the first virtual address space is the kernel state address space, and its address range is [0x80000000-0xFFFFFF], and the corresponding first page table is the first-level page table 801.
  • the first-level page table 801 is It is obtained by migration from the first-level page table 502. Therefore, if the obtained first virtual address is any one of [0x80000000-0xFFFFFF], S902 can be executed.
  • the MMU acquires page table offset flag information. If the page table offset flag information is obtained, execute S903; otherwise, execute S905.
  • the embodiment of the present application can offset the page table, then correspondingly, the method of determining the physical address corresponding to the first virtual address will be different from that when the page table is not offset.
  • the page table offset flag information can be set, and the page table offset flag information can be obtained when the physical address corresponding to the first virtual address is determined. If the page table offset flag information is obtained when the physical address corresponding to the first virtual address is determined, it can be determined that the page table is offset, and an appropriate manner can be adopted to determine the physical address in subsequent steps.
  • the MMU can acquire the offset indication bit in the TTBCR, and if the offset indication bit is the first indicator (for example, 1), it can determine that the page table offset flag information is acquired, so as to execute S903; If the shift indication bit is the second indicator (for example, 0), it can be determined that the page table offset flag information has not been acquired, so that S905 is performed.
  • the first indicator for example, 1
  • the shift indication bit is the second indicator (for example, 0)
  • an offset indicating module may be additionally set in the MMU, and the offset indicating module may include a specific character string that can be used as the page table offset flag information, and can indicate from the offset The specific character string is obtained in the module. If the specific character string is obtained, it can be determined that the page table offset flag information has been obtained, otherwise it can be determined that the page table offset flag information has not been obtained.
  • the MMU determines the index address of the first entry corresponding to the first virtual address in the first page table.
  • the table entry in the page table includes the association relationship between the table entry index address and the physical address. Therefore, in order to determine the first target physical address corresponding to the first virtual address, it is possible to first determine the first target physical address in the first page table.
  • the MMU determines the index address of the first entry corresponding to the first virtual address in the first page table
  • the page table descriptor stored in the entry before and after the offset of the first page table There may be changes, and the physical address associated with the entry will also change, that is, the entry index associated with the same physical address has changed. Therefore, the first entry index corresponding to the first virtual address in the first page table is determined. address, it can be implemented by the following way 1 or way 2:
  • Manner 1 The MMU determines the second virtual address based on the first virtual address and the first offset value.
  • the MMU determines the index address of the first entry based on the second virtual address. Wherein, the first virtual address is greater than the second virtual address. In other words, the second virtual address is equal to the first virtual address minus the first offset value.
  • the MMU first performs an adaptive offset on the first virtual address.
  • the MMU may determine the second virtual address based on the first virtual address and the first offset value through the ALU.
  • the first offset value may be determined in advance, and the first offset value may be less than or equal to the starting virtual address of the first virtual address space.
  • the operating system of the electronic device is 32 bits.
  • the first page table is a first-level page table, and the first-level page table is shifted downward by 2K entries, where each entry
  • the base address of the first page table can be determined, and the first table entry index can be determined based on the base address of the first page table and the second virtual address address.
  • the search is performed sequentially from the first-level page table, the second-level page table, the third-level page table, etc., until the corresponding first target physical address is found. Therefore, the index address of the first table entry can be determined based on the base address of the first page table and the second virtual address in the following two possible implementation manners:
  • the first virtual address when the first page table is a first-level page table, the first virtual address may be compared with the virtual address space corresponding to each TTBR. If the first virtual address belongs to the virtual address space corresponding to a certain TTBR address space (the first virtual space may be a subset of the virtual address space corresponding to the TTBR), the base address of the first page table is obtained from the TTBR corresponding to the virtual address space. The sum of the base address of the first page table and the index bits of the first-level page table in the second virtual address is determined as the index address of the first table entry.
  • FIG. 10 is a schematic diagram of a logical relationship among a virtual address space, a page table, and a physical address space according to an embodiment of the present application.
  • the operating system in the electronic device is 32 bits
  • the first virtual address space is the kernel state address space 501
  • the address range is [0x80000000-0xFFFFFF].
  • the MMU may determine that the TTBR corresponding to the kernel state address space 501 is TTBR1, and obtain the base address of the first-level page table 801 from TTBR1 as 0X000.
  • mapping level indicator bits [1:0] of the page table descriptor are 10, and the granularity indicator bit [18] is 0, then it is determined that the current is a first-level mapping, and the mapping granularity It is 1MB, so the first virtual address is shifted downward by 0x80000000, and the second virtual address is 0x00100000.
  • the [31:20] bit in the second virtual address is the first-level page table index bit, and the [19:0] bit is the segment offset bit.
  • the MMU determines the sum of the first virtual address bit [31:20] 0X001 and the base address 0X000 of the first-level page table and 0X001 as the index address of the first entry, and the page table descriptor in the 0X001 entry can indicate the location of 0x80100000.
  • the associated first target physical address is 0x40100000.
  • mapping level indication bits [1:0] of the page table descriptor are 01, it is determined that the secondary page table is also included, and the [31-20] bit of the page table descriptor is the base address of the secondary page table,
  • the [31:20] bits in the second virtual address are the first-level page table index bits, the [19:12] bits are the second-level page table index bits, and the [11:0] bits are the page offset bits .
  • the base address of the first page table may be determined based on the third page table, based on the base address of the first page table and the second virtual page table. address, to determine the index address of the first table entry, wherein the third page table is the previous page table adjacent to the first page table.
  • the MMU can obtain the second-level page table from the page table descriptor based on the granularity indicator bit of the page table descriptor in the third page table.
  • the index bit of the secondary page table is obtained from the first virtual address space, and the sum of the base address of the secondary page table and the index bit of the secondary page table is determined as the index address of the first table entry.
  • the operating system in the electronic device is 32-bit
  • the MMU determines that the mapping level indicator bits [1:0] of the page table descriptor corresponding to the first virtual address in the first-level page table are 01, that is, it is determined that the second-level page table is also included.
  • Page table then obtain the [31-20] bits of the page table descriptor as the base address of the second-level page table, obtain the second virtual address [19:12] bits as the second-level page table index bit, and use the second-level page table index bits.
  • the sum of the base address of the page table and the index bits of the secondary page table is determined as the index address of the first table entry.
  • the method of determining the index address of the first table entry based on the second virtual address can be the same as the method when the first page table is a secondary page table. Similar, and will not be repeated here.
  • Manner 2 The MMU determines the index address of the third entry to be offset based on the first virtual address, and determines the index address of the first entry based on the index address of the third entry and the second offset value.
  • the MMU can determine the base address of the first-level page table in a similar manner to the above, and obtain the index bit of the first-level page table from the first virtual address, and convert the first-level page table
  • the sum of the page table index bit and the base address of the first-level page table determines the index address of the third table entry, and then the index address of the third table entry can be offset, including subtracting the second offset from the index address of the third table entry value, so as to obtain the index address of the first entry.
  • FIG. 11 is a schematic diagram of a logical relationship among a virtual address space, a page table, and a physical address space according to an embodiment of the present application.
  • the operating system in the electronic device is 32 bits
  • the first virtual address space is the kernel state address space 501
  • the address range is [0x80000000, 0xFFFFFF].
  • the MMU may determine that the TTBR corresponding to the kernel-mode address space 501 is TTBR1, and the base address of the first-level page table 801 obtained from TTBR1 is 0X000.
  • the bits [31:20] in 0x80100000 in the first virtual address are the first-level page table index bits, and the bits [19:0] are the segment offset bits.
  • the MMU determines the sum of the first virtual address bit [31:20] 0X801 and the base address 0X000 of the first-level page table and 0X801 as the index address of the third table entry, and then subtracts the index address of the third table entry (0X801) from the first
  • the difference between the number of entries 0X800 (the hexadecimal value corresponding to the binary value 2K) is determined as the index address 0X001 of the first entry.
  • the MMU determines the first target physical address corresponding to the first virtual address from the first page table according to the index address of the first table entry.
  • the entry corresponding to the first virtual address in the first page table can be determined based on the first entry index address, and based on the entry A first target physical address is determined.
  • the page table description in the entry corresponding to the index address of the first entry can indicate the base address of the first target physical address, so the MMU can obtain the base address of the first target physical address from the page table descriptor, and obtain the physical address offset from the first virtual address or the second virtual address. By shifting, the sum of the base address of the first target physical address and the offset bits of the physical address is determined as the first target physical address.
  • the first representation index address may indicate the base address of the next level page table.
  • the MMU may continue to search for the index address of the first entry corresponding to the first virtual address in the next-level page table until it finds the last-level page table, thereby determining the first target physical address. That is, the MMU may execute S903 and S904 at least once to determine the first target physical address corresponding to the first virtual address by sequentially acquiring the first-level page table, the second-level page table, and the third-level page table.
  • the offset is actually at least one level of page table index bits in the first virtual address, and the physical address offset bit has not changed, so the MMU can start from the first virtual address.
  • a physical address offset bit is obtained from a virtual address or a second virtual address.
  • the page table descriptor in the 0X001 entry in the first-level page table 801 indicates the first virtual address corresponding to 0x80100000.
  • the base address of a target physical address is 0x40100000
  • mapping level indication bits [1:0] of the page table descriptor are 01, it is determined that the second-level page table is also included, and the [31-20] bit of the page table descriptor is the base of the second-level page table. address, then return to S605 to determine the first target physical address from the secondary page table.
  • the first page table may be any level of page table, that is, any page table may be offset occurs. Then, if the MMU first offsets the first virtual address to obtain the second virtual address, and then determines the corresponding index address of the first table entry from the first page table based on the second virtual address, no matter the multiple levels of pages Those page tables in the table are offset, and at least the first virtual address needs to be offset once, and the obtained second virtual address can be matched with the offset page table.
  • the MMU first determines the index address of the third table entry from the first virtual address, and then offsets the index address of the third table entry to obtain the index address of the first table entry, it can be determined in the page table where the offset occurs at each level When the index address of the first table entry is used, the index address of the first table entry is obtained by offsetting the index address of the third table entry for the page table alone.
  • S905 Determine the index address of the third table entry corresponding to the first virtual address in the second page table corresponding to the first page table, and determine from the second page table corresponding to the first page table according to the index address of the third table entry The second target physical address corresponding to the first virtual address.
  • the operation mode of S905 may be similar to the aforementioned S903 and S904, except that in S905, the first virtual address or the third table entry address does not need to be offset.
  • the first page table is obtained by offsetting entries in the second page table. Therefore, the first target determined from the first page table through S903-S904
  • the physical address may be the same as the second target physical address determined from the second page table through S905.
  • Only the first page table or the second page table may be stored in the memory of the electronic device. If the first page table is stored, the MMU can obtain the page table offset flag information in S902, thereby executing S903-S904. If the second page table is stored, the MMU cannot obtain the page table offset flag information in S902, and thus executes S905.
  • the MMU determines the first target physical address and the second target physical address from the same page table (the first page table or the second page table) based on S903-S304 and S905 respectively, then the determined first target The physical address and the second target physical address may be different.
  • the MMU when the MMU obtains the first virtual address of the first virtual address space, it can determine the index address of the first entry corresponding to the first virtual address in the first page table, and according to the index address of the first entry , and determine the first target physical address corresponding to the first virtual address from the first page table.
  • the starting virtual address of the first virtual address space corresponds to the index address of the second entry in the first page table
  • the index address of the second table entry is greater than or equal to the base address of the first page table, and less than the sum of the quotient of the starting virtual address divided by the size of the second virtual address space and the base address of the first page table, and the maximum value of the first page table
  • the table entry index address is less than the sum of the quotient of the maximum virtual address of the first virtual address space divided by the size of the second virtual address space and the base address of the first page table, where the second virtual address space is the same as that in the first page table
  • the virtual address space associated with any table entry, so the first page table may at least include only table entries actually required by the first virtual address space, thereby saving memory and improving memory utilization.
  • the page table descriptor in the second page table including redundant entries is shifted downward, thereby reducing or eliminating redundant entries, and obtaining a first page including fewer entries Page table.
  • the second page table can also be shifted upward (ie, the high address direction).
  • the second page table can be is an arbitrary page table, and the number of third table entries offset upward can also be any value, and the obtained first page table can include more table entries.
  • the MMU determines the first virtual address corresponding to the first virtual address.
  • the sum of the first virtual address and the first offset value can be determined as the second virtual address (that is, the first virtual address is also shifted to the higher address direction), and then the first virtual address is determined based on the second virtual address.
  • the index address of the entry, or the index address of the third entry to be offset can be determined based on the first virtual address, and the sum of the index address of the third entry and the second offset value is determined as the index address of the first entry ( That is, the index address of the third table entry is also shifted to the high address direction).
  • the index address of the first entry is determined, the first target physical address corresponding to the first virtual address is determined from the first page table based on the index address of the first entry.
  • the first offset value the number of third entries * the size of the second virtual address space associated with each entry in the first page table
  • the second offset value the number of third entries
  • the first virtual address can be Less than the second virtual address
  • the index address of the third entry may be less than the index address of the first entry.
  • an embodiment of the present application further provides a chip system 1200 .
  • the chip system 1200 includes at least one CPU 110 (only one is shown in FIG. 12 ), at least one memory 115 (only one is shown in FIG. 12 ) and at least one coprocessor 116 (only one is shown in FIG. 12 ) 1), at least one coprocessor 116 includes at least one MMU 111 (only 1 is shown in FIG. 12 ), and the MMU 111 includes at least one ALU 112 (only 1 is shown in FIG. 12 ), at least one TTBCR 113 (shown in FIG. 12 ) Only 1 is shown) and at least one TTBR 114 (only 1 is shown in Figure 12).
  • At least one MMU111 is used for:
  • the first target physical address corresponding to the first virtual address is determined from the first page table
  • the first page table is used to determine the physical address corresponding to each virtual address in the first virtual address space, the starting virtual address of the first virtual address space corresponds to the index address of the second entry in the first page table, the first virtual address
  • the index address of the second table entry is greater than or equal to the base address of the first page table, and less than the sum of the quotient of the starting virtual address divided by the size of the second virtual address space and the base address of the first page table, and the maximum value of the first page table
  • the index address of the table entry is less than the sum of the quotient of the maximum virtual address of the first virtual address space divided by the size of the second virtual address space and the base address of the first page table, and the second virtual address space is the same as any one of the first page table The virtual address space associated with the entry.
  • At least one ALU 112 is configured to, based on the first virtual address and the first offset value, determine a second virtual address, where the first virtual address is greater than the second virtual address;
  • the at least one MMU 110 is further configured to: determine the index address of the first entry based on the second virtual address.
  • At least one MMU 110 is also used to:
  • the index address of the first entry is determined, and the index address of the third entry is greater than the index address of the first entry.
  • At least one MMU 110 is also used to:
  • each TTBR 114 may store a base address of a first-level page table.
  • the TTBCR 113 can be used to indicate the selected TTBR 114 when determining the physical addresses corresponding to the virtual addresses in different virtual address spaces, that is, determine the TTBR 114 corresponding to the different virtual address spaces.
  • At least one coprocessor 116 may be integrated into at least one CPU 1210 .
  • the memory 115 may include the internal memory 121 in FIG. 1 .
  • FIG. 13 is a schematic structural diagram of another chip system 1300 provided by an embodiment of the present application.
  • the system 1300 includes a CPU 110, an ALU 112, a TTBCR 113, a virtual memory conversion module 117 and a memory 115, wherein the TTBCR 113, the ALU 112 and the virtual memory conversion module 117 can be set in the MMU 111, and the MMU 111 can be set in a coprocessor or integrated in the CPU 110.
  • the CPU 110 may issue an access request to the memory 115, where the access request carries the first virtual address of the kernel-mode address space.
  • the ALU 112 acquires the first virtual address and determines that the offset indicator bit in the TTBCR 113 is the first indicator (eg, offset1)
  • the ALU 112 offsets the first virtual address to the second virtual address.
  • the virtual memory conversion module 117 determines the index address of the first table entry based on the second virtual address from the page table set corresponding to the kernel state address space, and then determines the first target physical address, and the CPU 110 can access the internal memory based on the first target physical address. 1350.
  • the ALU 112 , the TTBCR 113 , and the virtual memory conversion module 117 may be provided in the MMU 111 , and the MMU 111 may further include the TTBR 114 .
  • the virtual memory conversion module 117 may be configured to determine the index address of the first entry based on the index address of the third entry and the second offset value.
  • an embodiment of the present application also provides an electronic device, the electronic device including any one of the aforementioned chip systems.
  • Embodiments of the present application further provide a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method described in the foregoing method embodiment is implemented.
  • the embodiments of the present application further provide a computer program product, when the computer program product runs on the electronic device, the electronic device implements the method described in the above method embodiments when executed.
  • the above-mentioned integrated units are implemented in the form of software functional units and sold or used as independent products, they may be stored in a computer-readable storage medium.
  • the present application realizes all or part of the processes in the methods of the above embodiments, which can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium.
  • the steps of each of the above method embodiments can be implemented.
  • the computer program includes computer program code
  • the computer program code may be in the form of source code, object code, executable file or some intermediate form, and the like.
  • the computer-readable storage medium may include at least: any entity or device capable of carrying computer program codes to the photographing device/terminal device, recording medium, computer memory, read-only memory (ROM), random access Memory (random access memory, RAM), electrical carrier signals, telecommunication signals, and software distribution media.
  • ROM read-only memory
  • RAM random access Memory
  • electrical carrier signals telecommunication signals
  • software distribution media For example, U disk, mobile hard disk, disk or CD, etc.
  • computer readable media may not be electrical carrier signals and telecommunications signals.
  • the disclosed apparatus/device and method may be implemented in other manners.
  • the apparatus/equipment embodiments described above are only illustrative.
  • the division of the modules or units is only a logical function division.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • the term “if” may be contextually interpreted as “when” or “once” or “in response to determining” or “in response to detecting “.
  • the phrases “if it is determined” or “if the [described condition or event] is detected” may be interpreted, depending on the context, to mean “once it is determined” or “in response to the determination” or “once the [described condition or event] is detected. ]” or “in response to detection of the [described condition or event]”.
  • references in this specification to "one embodiment” or “some embodiments” and the like mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application.
  • appearances of the phrases “in one embodiment,” “in some embodiments,” “in other embodiments,” “in other embodiments,” etc. in various places in this specification are not necessarily All refer to the same embodiment, but mean “one or more but not all embodiments” unless specifically emphasized otherwise.
  • the terms “including”, “including”, “having” and their variants mean “including but not limited to” unless specifically emphasized otherwise.

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Abstract

本申请提供一种确定物理地址的方法及芯片系统，涉及操作系统领域。该方法包括当获取到第一虚拟地址空间的第一虚拟地址时，确定第一虚拟地址对应的第一表项索引地址；根据第一表项索引地址，从第一页表中确定第一虚拟地址对应的第一目标物理地址。第一虚拟地址空间的起始虚拟地址对应的第二表项索引地址，大于或等于第一页表的基址，且小于起始虚拟地址除以第二虚拟地址空间的大小的商与第一页表的基址的和，第一页表的最大表项索引地址小于第一虚拟地址空间的最大虚拟地址除以第二虚拟地址空间的大小的商与第一页表的基址的和，第二虚拟地址空间与第一页表中任一表项关联。本申请提供的技术方案能够节省页表所占的内存，提高内存利用率。

Description

确定物理地址的方法及芯片系统
本申请要求于2020年8月27日提交国家知识产权局、申请号为202010881378.2、申请名称为“确定物理地址的方法及芯片系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及操作系统领域，尤其涉及一种确定物理地址的方法及芯片系统。
背景技术
电子设备中的芯片系统通常包括中央处理器(central processing unit，CPU)、内存和协处理器，CPU在运行过程中访问内存，来获取或存储数据，协处理器用于执行CPU所不能或不必要执行的操作。目前，CPU访问内存的访问地址为虚拟地址，协处理器中的内存管理单元(memory management unit，MMU)，可以将该虚拟地址转换为对应的物理地址。因此，如何确定物理地址也越来越受到广泛的关注。
现有技术中，当MMU收到来自CPU对某个虚拟地址空间的虚拟地址访问请求时，MMU可以从内存中获取与该虚拟地址空间对应的一级页表，该一级页表包括多个表项，各表项包括表项索引地址和物理地址之间的关联关系。MMU基于该虚拟地址从该一级页表中的获取对应的表项索引地址，再基于该表项索引地址，从该一级页表中确定与该虚拟地址对应的物理地址。
但由于虚拟地址空间的起始虚拟地址可能并不是从0开始的，而一级页表包括的表项通常是按照虚拟地址0到该虚拟地址空间的最大虚拟地址分配的，从而导致该一级页表中的表项数目大于该虚拟地址空间所实际需要的表项数目，该一级页表中地址较低的部分表项不会被利用到，这些表项所占据的内存空间便会被浪费，内存利用率较低。
发明内容
有鉴于此，本申请提供一种确定物理地址的方法及芯片系统，以节省页表所占内存，提高内存利用率。
为了实现上述目的，第一方面提供一种确定物理地址的方法，包括：当获取到第一虚拟地址空间的第一虚拟地址时，确定所述第一虚拟地址对应的第一表项索引地址；根据所述第一表项索引地址，从第一页表中确定所述第一虚拟地址对应的第一目标物理地址；
其中，所述第一页表用于确定所述第一虚拟地址空间中每个虚拟地址对应的物理地址，所述第一虚拟地址空间的起始虚拟地址与所述第一页表中的第二表项索引地址对应，所述第二表项索引地址大于或等于所述第一页表的基址，且小于所述起始虚拟地址除以第二虚拟地址空间的大小的商与所述第一页表的基址的和，所述第一页表的最大表项索引地址小于所述第一虚拟地址空间的最大虚拟地址除以所述第二虚拟地址空 间的大小的商与所述第一页表的基址的和，所述第二虚拟地址空间为与所述第一页表中任一表项关联的虚拟地址空间，即第二虚拟地址空间可以是第一虚拟地址空间的子集。
需要说明的是，页表是一种存储在内存中的特殊数据结构。该页表可以作为虚拟地址空间的索引并可以包括多个表项，每个表项包括表项索引地址以及物理地址之间的关联关系，其中，物理地址可以承载在该表项的页表描述符中，该页表描述符可以用于指示下一级页表的基址或与虚拟地址对应的物理地址的基址。
在本申请实施例中，当MMU获取到第一虚拟地址空间的第一虚拟地址时，可以确定第一页表中第一虚拟地址对应的第一表项索引地址，根据第一表项索引地址，从第一页表中确定第一虚拟地址对应的第一目标物理地址。由于第一页表可以用于确定第一虚拟地址空间中每个虚拟地址对应的物理地址，第一虚拟地址空间的起始虚拟地址与第一页表中的第二表项索引地址对应，第二表项索引地址大于或等于第一页表的基址，且小于起始虚拟地址除以第二虚拟地址空间的大小的商与第一页表的基址的和，第一页表的最大表项索引地址小于第一虚拟地址空间的最大虚拟地址除以第二虚拟地址空间的大小的商与第一页表的基址的和，第二虚拟地址空间为与所述第一页表中任一表项关联的虚拟地址空间，因此第一页表最少可以只包括第一虚拟地址空间实际所需的表项，从而能够节省内存，提高内存的利用率。
可选地，可以在事先(比如在当获取到第一虚拟地址空间的第一虚拟地址时，确定所述第一虚拟地址对应的第一表项索引地址之前)，获取第一虚拟地址空间对应的第二页表，如果第四表项索引地址大于第二页表的基址，那么可以确定第二页表中存在未被利用的表项，可以将第二页表中的页表描述符依次向下偏移第一表项数目个表项，并将第二页表中高址部分的第一表项数目个表项删除，从而得到与第一虚拟地址空间对应的第一页表。
其中，第四表项索引地址为第一虚拟地址空间的起始虚拟地址在第二页表中所对应表项索引地址，当将第二页表中的页表描述符依次向下偏移第一表项数目个表项时，第四表项索引地址与第二表项索引地址相同。
可选地，第一表项数目可以大于0且小于或等于第二表项数目。
其中，第二表项数目可以为第二页页表中的页表描述符可向下偏移的最大值。第二表项数目的计算方式可以有多种，但多种计算方式下的计算结果可以是相同的，比如第二表项数目＝第一虚拟地址空间的起始虚拟地址/第二虚拟地址空间的大小，或者，第二表项数目＝第二页表的表项数目-第一虚拟地址空间的大小/第二虚拟地址空间的大小。
需要说明的是，第一表项数目越大，则表示表项偏移的幅度越大，所节省的内存的越大。以第二页表和第一页表为例，第一页表比第二页表所节省的内存＝第一表项数目*第二页表(或第一页表)中每个表项所占据的内存大小。
当然，在实际应用中，也可以先获取第一虚拟地址空间，如果第一虚拟地址空间的起始虚拟地址大于0，则第二页表中的第四表项索引地址可能会大于第二页表的基址，则因此可以将第二页表的页表描述符依次向下偏移与第二页表对应的第一表项数目个表项，得到第一页表。
可选地，所述确定所述第一虚拟地址对应的第一表项索引地址，包括：基于所述第一虚拟地址和第一偏移值，确定第二虚拟地址，所述第一虚拟地址大于所述第二虚拟地址，所述第一偏移值小于或等于所述第一虚拟地址空间的起始虚拟地址；基于所述第二虚拟地址，确定所述第一表项索引地址。其中，第一偏移值＝第一页表对应的第一表项数目*第一页表各表项关联的第二虚拟地址空间的大小。
当计算逻辑单元(arithmetic logic unit，ALU)对第一虚拟地址完成了偏移并确定了第二虚拟地址时，MMU可以确定第一页表的基址，基于第一页表的基址和第二虚拟地址，确定第一表项索引地址。且由于在确定第一虚拟地址对应的第一目标物理地址时，是依次从一级页表、二级页表、三级页表……进行查找，直至查找到对应的第一目标物理地址。因此可以通过下述两种可能的实现方式来基于第一页表的基址和第二虚拟地址，确定第一表项索引地址：
在一种可能的实现方式中，当第一页表为一级页表时，可以将第一虚拟地址与各转换页表基址寄存器(translation table base register，TTBR)对应的虚拟地址空间进行比较。如果第一虚拟地址属于某个TTBR对应的虚拟地址空间(第一虚拟空间可以是该TTBR对应的虚拟地址空间的子集)，则从该虚拟地址空间对应的TTBR中获取第一页表的基址。将第一页表的基址与第二虚拟地址中的一级页表索引位的和，确定为第一表项索引地址。
在另一种可能的实现方式中，当第一页表为次级页表时，可以基于第三页表，确定第一页表的基址，基于第一页表的基址和第二虚拟地址，确定第一表项索引地址，其中，第三页表为与第一页表相邻的前一级页表。
可选地，所述确定所述第一虚拟地址对应的第一表项索引地址，包括：基于所述第一虚拟地址，确定待偏移的第三表项索引地址；基于所述第三表项索引地址和第二偏移值，确定所述第一表项索引地址，所述第三表项索引地址大于所述第一表项索引地址，所述第二偏移值＝第一表项数目。
由前述可知，MMU在确定第一虚拟地址对应的第一目标物理地址的过程中，可能需要查找多个层级的页表，第一页表可能是任一级页表，即任一页表均可能发生偏移。那么如果MMU是通过ALU对先对第一虚拟地址进行偏移得到第二虚拟地址，再基于第二虚拟地址，从第一页表中确定对应的第一表项索引地址，则无论该多个层级的页表中那些页表发生了偏移，最少只要对第一虚拟地址进行一次偏移，所得到的第二虚拟地址就可以与偏移后的页表相配。如果MMU先由第一虚拟地址确定待偏移的第三表项索引地址，再对第三表项索引地址进行偏移，得到第一表项索引地址，则可以在每一层级发生偏移的页表中确定第一表项索引地址时，单独针对该页表对第三表项索引地址进行偏移来得到第一表项索引地址。
可选地，在所述确定所述第一虚拟地址对应的第一表项索引地址之前，所述方法还包括：获取页表偏移标志信息，所述页表偏移标志信息用于指示基于所述第一页表确定与所述第一虚拟地址对应的所述第一目标物理地址。
可选地，所述页表偏移标志信息通过转换页表基址控制寄存器(translation table base control register，TTBCR)中偏移指示位指示，所述获取页表偏移标志信息，包括：当所述TTBCR中偏移指示位的值为第一指示符时，确定获取到所述页表偏移标志信 息。
可选地，所述方法还包括：
将所述TTBCR中所述偏移指示位的值设置为所述第一指示符。
可选地，所述第一页表为一级页表或二级页表。
可选地，所述第一虚拟地址空间为内核态地址空间。
其中，内核态地址空间的地址范围可以为0x80000000-0xFFFFFFFF。
第二方面提供一种芯片系统，所述芯片系统包括：至少一个CPU，至少一个存储器和至少一个协处理器，所述至少一个协处理器中包括至少一个MMU；所述至少一个MMU用于：当收到所述至少一个CPU发起的对所述至少一个存储器的访问请求，且所述访问请求中携带第一虚拟地址空间的第一虚拟地址时，确定所述第一虚拟地址对应的第一表项索引地址；根据所述第一表项索引地址，从第一页表中确定所述第一虚拟地址对应的第一目标物理地址；其中，所述第一页表用于确定所述第一虚拟地址空间中每个虚拟地址对应的物理地址，所述第一虚拟地址空间的起始虚拟地址与所述第一页表中的第二表项索引地址对应，所述第二表项索引地址大于或等于所述第一页表的基址，且小于所述起始虚拟地址除以第二虚拟地址空间的大小的商与所述第一页表的基址的和，所述第一页表的最大表项索引地址小于所述第一虚拟地址空间的最大虚拟地址除以所述第二虚拟地址空间的大小的商与所述第一页表的基址的和，所述第二虚拟地址空间为与所述第一页表中任一表项关联的虚拟地址空间。
可选地，所述至少一个MMU包括至少一个ALU：
所述至少一个ALU用于，基于所述第一虚拟地址和第一偏移值，确定第二虚拟地址，所述第一虚拟地址大于所述第二虚拟地址；
所述至少一个MMU还用于：基于所述第二虚拟地址，确定所述第一表项索引地址。
可选地，所述至少一个MMU还用于：基于所述第一虚拟地址，确定待偏移的第三表项索引地址；基于所述第三表项索引地址和第二偏移值，确定所述第一表项索引地址，所述第三表项索引地址大于所述第一表项索引地址。
可选地，所述至少一个MMU还包括至少一个TTBCR，所述至少一个MMU还用于：
获取页表偏移标志信息，所述页表偏移标志信息通过所述至少一个TTBCR中的偏移指示位指示。
可选地，所述MMU还包括至少一个TTBR，各所述TTBR中可以存储一个一级页表的基址。相应的，所述TTBCR中可以用于指示在确定不同虚拟地址空间中的虚拟地址所对应的物理地址时，所选用的TTBR，即确定不同虚拟地址空间所对应的TTBR。
可选地，所述至少一个协处理器可以集成在所述至少一个CPU中。
第三方面提供一种电子设备，所述电子设备包括第二方面任一所述的芯片系统。
第四方面提供一种计算机程序产品，当计算机程序产品在电子设备上运行时，使得电子设备执行上述第一方面中任一项所述的方法。
可以理解的是，上述第二方面至第四方面的有益效果可以参见上述第一方面中的 相关描述，在此不再赘述。
附图说明
图1为本申请实施例所提供的一种电子设备的结构示意图；
图2为本申请实施例所提供的一种虚拟地址空间、页表和物理地址空间之间的逻辑关系的示意图；
图3为本申请实施例所提供的一种一级页表的页表描述符的结构示意图；
图4为本申请实施例所提供的一种二级页表的页表描述符的结构示意图；
图5为本申请实施例所提供的另一种虚拟地址空间、页表和物理地址空间之间的逻辑关系的示意图；
图6为本申请实施例所提供的一种映射初始化设置的流程图；
图7为本申请实施例所提供的一种虚拟地址空间与页表的逻辑关系示意图；
图8为本申请实施例所提供的一种页表的示意图；
图9为本申请实施例所提供的一种确定物理地址的方法的流程图；
图10为本申请实施例所提供的另一种虚拟地址空间、页表和物理地址空间之间的逻辑关系的示意图；
图11为本申请实施例所提供的另一种虚拟地址空间、页表和物理地址空间之间的逻辑关系的示意图；
图12为本申请实施例所提供的一种芯片系统的结构示意图；
图13为本申请实施例所提供的另一种芯片系统的结构示意图。
具体实施方式
本申请实施例提供的确定物理地址的方法可以应用于手机、平板电脑、可穿戴设备、车载设备、增强现实(augmented reality，AR)/虚拟现实(virtual reality，VR)设备、笔记本电脑、超级移动个人计算机(ultra-mobile personal computer，UMPC)、上网本、个人数字助理(personal digital assistant，PDA)、服务器等电子设备上，本申请实施例对电子设备的具体类型不作任何限制。
请参照图1，以本申请实施例提供的电子设备100的结构示意图，该电子设备100可以包括CPU110，外部存储器接口120，内部存储器121，通用串行总线(universal serial bus，USB)接口130，充电管理模块140，电源管理模块141，电池142，天线1，天线2，移动通信模块150，无线通信模块160，音频模块170，扬声器170A，受话器170B，麦克风170C，耳机接口170D，传感器模块180，按键190，马达191，指示器192，摄像头193，显示屏194，以及用户标识模块(subscriber identification module，SIM)卡接口195等。其中传感器模块180可以包括压力传感器，陀螺仪传感器，气压传感器，磁传感器，加速度传感器，距离传感器，接近光传感器，指纹传感器，温度传感器，触摸传感器，环境光传感器L，骨传导传感器等。
可以理解的是，本申请实施例示意的结构并不构成对电子设备100的具体限定。在本申请另一些实施例中，电子设备100可以包括比图示更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
CPU110可以包括一个或多个处理单元，例如：CPU110可以包括应用处理器 (application processor，AP)，调制解调处理器，图形处理器(graphics processing unit，GPU)，图像信号处理器(image signal processor，ISP)，控制器，存储器，视频编解码器，数字信号处理器(digital signal processor，DSP)，基带处理器，和/或神经网络处理器(neural-network processing unit，NPU)等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。
其中，控制器可以是电子设备100的神经中枢和指挥中心。控制器可以根据指令操作码和时序信号，产生操作控制信号，完成取指令和执行指令的控制。
在一些实施例中，CPU110可以包括一个或多个接口。接口可以包括集成电路(inter-integrated circuit，I2C)接口，集成电路内置音频(inter-integrated circuit sound，I2S)接口，脉冲编码调制(pulse code modulation，PCM)接口，通用异步收发传输器(universal asynchronous receiver/transmitter，UART)接口，移动产业处理器接口(mobile industry processor interface，MIPI)，通用输入输出(general-purpose input/output，GPIO)接口，用户标识模块(subscriber identity module，SIM)接口，和/或通用串行总线(universal serial bus，USB)接口等。
I2C接口是一种双向同步串行总线，包括一根串行数据线(serial data line，SDA)和一根串行时钟线(derail clock line，SCL)。在一些实施例中，CPU110可以包含多组I2C总线。CPU110可以通过不同的I2C总线接口分别耦合触摸传感器，充电器，闪光灯，摄像头193等。例如：CPU110可以通过I2C接口耦合触摸传感器，使CPU110与触摸传感器通过I2C总线接口通信，实现电子设备100的触摸功能。
I2S接口可以用于音频通信。在一些实施例中，CPU110可以包含多组I2S总线。CPU110可以通过I2S总线与音频模块170耦合，实现CPU110与音频模块170之间的通信。在一些实施例中，音频模块170可以通过I2S接口向无线通信模块160传递音频信号，实现通过蓝牙耳机接听电话的功能。
PCM接口也可以用于音频通信，将模拟信号抽样，量化和编码。在一些实施例中，音频模块170与无线通信模块160可以通过PCM总线接口耦合。在一些实施例中，音频模块170也可以通过PCM接口向无线通信模块160传递音频信号，实现通过蓝牙耳机接听电话的功能。所述I2S接口和所述PCM接口都可以用于音频通信。
UART接口是一种通用串行数据总线，用于异步通信。该总线可以为双向通信总线。它将要传输的数据在串行通信与并行通信之间转换。在一些实施例中，UART接口通常被用于连接CPU110与无线通信模块160。例如：CPU110通过UART接口与无线通信模块160中的蓝牙模块通信，实现蓝牙功能。在一些实施例中，音频模块170可以通过UART接口向无线通信模块160传递音频信号，实现通过蓝牙耳机播放音乐的功能。
MIPI接口可以被用于连接CPU110与显示屏194，摄像头193等外围器件。MIPI接口包括摄像头串行接口(camera serial interface，CSI)，显示屏串行接口(display serial interface，DSI)等。在一些实施例中，CPU110和摄像头193通过CSI接口通信，实现电子设备100的拍摄功能。CPU110和显示屏194通过DSI接口通信，实现电子设备100的显示功能。
GPIO接口可以通过软件配置。GPIO接口可以被配置为控制信号，也可被配置为 数据信号。在一些实施例中，GPIO接口可以用于连接CPU110与摄像头193，显示屏194，无线通信模块160，音频模块170，传感器模块180等。GPIO接口还可以被配置为I2C接口，I2S接口，UART接口，MIPI接口等。
USB接口130是符合USB标准规范的接口，具体可以是Mini USB接口，Micro USB接口，USB Type C接口等。USB接口130可以用于连接充电器为电子设备100充电，也可以用于电子设备100与外围设备之间传输数据。也可以用于连接耳机，通过耳机播放音频。该接口还可以用于连接其他电子设备100，例如AR设备等。
可以理解的是，本申请实施例示意的各模块间的接口连接关系，只是示意性说明，并不构成对电子设备100的结构限定。在本申请另一些实施例中，电子设备100也可以采用上述实施例中不同的接口连接方式，或多种接口连接方式的组合。
充电管理模块140用于从充电器接收充电输入。其中，充电器可以是无线充电器，也可以是有线充电器。在一些有线充电的实施例中，充电管理模块140可以通过USB接口130接收有线充电器的充电输入。在一些无线充电的实施例中，充电管理模块140可以通过电子设备100的无线充电线圈接收无线充电输入。充电管理模块140为电池142充电的同时，还可以通过电源管理模块141为电子设备100供电。
电源管理模块141用于连接电池142，充电管理模块140与CPU110。电源管理模块141接收电池142和/或充电管理模块140的输入，为CPU110，内部存储器121，外部存储器，显示屏194，摄像头193，和无线通信模块160等供电。电源管理模块141还可以用于监测电池容量，电池循环次数，电池健康状态(漏电，阻抗)等参数。在其他一些实施例中，电源管理模块141也可以设置于CPU110中。在另一些实施例中，电源管理模块141和充电管理模块140也可以设置于同一个器件中。
电子设备100的无线通信功能可以通过天线1，天线2，移动通信模块150，无线通信模块160，调制解调处理器以及基带处理器等实现。
天线1和天线2用于发射和接收电磁波信号。电子设备100中的每个天线可用于覆盖单个或多个通信频带。不同的天线还可以复用，以提高天线的利用率。例如：可以将天线1复用为无线局域网的分集天线。在另外一些实施例中，天线可以和调谐开关结合使用。
移动通信模块150可以提供应用在电子设备100上的包括2G/3G/4G/5G等无线通信的解决方案。移动通信模块150可以包括至少一个滤波器，开关，功率放大器，低噪声放大器(low noise amplifier，LNA)等。移动通信模块150可以由天线1接收电磁波，并对接收的电磁波进行滤波，放大等处理，传送至调制解调处理器进行解调。移动通信模块150还可以对经调制解调处理器调制后的信号放大，经天线1转为电磁波辐射出去。在一些实施例中，移动通信模块150的至少部分功能模块可以被设置于CPU110中。在一些实施例中，移动通信模块150的至少部分功能模块可以与CPU110的至少部分模块被设置在同一个器件中。
调制解调处理器可以包括调制器和解调器。其中，调制器用于将待发送的低频基带信号调制成中高频信号。解调器用于将接收的电磁波信号解调为低频基带信号。随后解调器将解调得到的低频基带信号传送至基带处理器处理。低频基带信号经基带处理器处理后，被传递给应用处理器。应用处理器通过音频设备(不限于扬声器170A， 受话器170B等)输出声音信号，或通过显示屏194显示图像或视频。在一些实施例中，调制解调处理器可以是独立的器件。在另一些实施例中，调制解调处理器可以独立于CPU110，与移动通信模块150或其他功能模块设置在同一个器件中。
无线通信模块160可以提供应用在电子设备100上的包括无线局域网(wireless local area networks，WLAN)(如无线保真(wireless fidelity，Wi-Fi)网络)，蓝牙(bluetooth，BT)，全球导航卫星系统(global navigation satellite system，GNSS)，调频(frequency modulation，FM)，近距离无线通信技术(near field communication，NFC)，红外技术(infrared，IR)等无线通信的解决方案。无线通信模块160可以是集成至少一个通信MMU的一个或多个器件。无线通信模块160经由天线2接收电磁波，将电磁波信号调频以及滤波处理，将处理后的信号发送到CPU110。无线通信模块160还可以从CPU110接收待发送的信号，对其进行调频，放大，经天线2转为电磁波辐射出去。
在一些实施例中，电子设备100的天线1和移动通信模块150耦合，天线2和无线通信模块160耦合，使得电子设备100可以通过无线通信技术与网络以及其他设备通信。所述无线通信技术可以包括全球移动通讯系统(global system for mobile communications，GSM)，通用分组无线服务(general packet radio service，GPRS)，码分多址接入(code division multiple access，CDMA)，宽带码分多址(wideband code division multiple access，WCDMA)，时分码分多址(time-division code division multiple access，TD-SCDMA)，长期演进(long term evolution，LTE)，BT，GNSS，WLAN，NFC，FM，和/或IR技术等。所述GNSS可以包括全球卫星定位系统(global positioning system，GPS)，全球导航卫星系统(global navigation satellite system，GLONASS)，北斗卫星导航系统(beidou navigation satellite system，BDS)，准天顶卫星系统(quasi-zenith satellite system，QZSS)和/或星基增强系统(satellite based augmentation systems，SBAS)。
电子设备100通过GPU，显示屏194，以及应用处理器等实现显示功能。GPU为图像处理的微处理器，连接显示屏194和应用处理器。GPU用于执行数学和几何计算，用于图形渲染。CPU110可包括一个或多个GPU，其执行程序指令以生成或改变显示信息。
显示屏194用于显示图像，视频等。显示屏194包括显示面板。显示面板可以采用液晶显示屏(liquid crystal display，LCD)，有机发光二极管(organic light-emitting diode，OLED)，有源矩阵有机发光二极体或主动矩阵有机发光二极体(active-matrix organic light emitting diode的，AMOLED)，柔性发光二极管(flex light-emitting diode，FLED)，Miniled，MicroLed，Micro-oLed，量子点发光二极管(quantum dot light emitting diodes，QLED)等。在一些实施例中，电子设备100可以包括1个或N个显示屏194，N为大于1的正整数。
电子设备100可以通过ISP，摄像头193，视频编解码器，GPU，显示屏194以及应用处理器等实现拍摄功能。
ISP用于处理摄像头193反馈的数据。例如，拍照时，打开快门，光线通过镜头被传递到摄像头感光元件上，光信号转换为电信号，摄像头感光元件将所述电信号传递给ISP处理，转化为肉眼可见的图像。ISP还可以对图像的噪点，亮度，肤色进行 算法优化。ISP还可以对拍摄场景的曝光，色温等参数优化。在一些实施例中，ISP可以设置在摄像头193中。
摄像头193用于捕获静态图像或视频。物体通过镜头生成光学图像投射到感光元件。感光元件可以是电荷耦合器件(charge coupled device，CCD)或互补金属氧化物半导体(complementary metal-oxide-semiconductor，CMOS)光电晶体管。感光元件把光信号转换成电信号，之后将电信号传递给ISP转换成数字图像信号。ISP将数字图像信号输出到DSP加工处理。DSP将数字图像信号转换成标准的RGB，YUV等格式的图像信号。在一些实施例中，电子设备100可以包括1个或N个摄像头193，N为大于1的正整数。
数字信号处理器用于处理数字信号，除了可以处理数字图像信号，还可以处理其他数字信号。例如，当电子设备100在频点选择时，数字信号处理器用于对频点能量进行傅里叶变换等。
视频编解码器用于对数字视频压缩或解压缩。电子设备100可以支持一种或多种视频编解码器。这样，电子设备100可以播放或录制多种编码格式的视频，例如：动态图像专家组(moving picture experts group，MPEG)1，MPEG2，MPEG3，MPEG4等。
NPU为神经网络(neural-network，NN)计算处理器，通过借鉴生物神经网络结构，例如借鉴人脑神经元之间传递模式，对输入信息快速处理，还可以不断的自学习。通过NPU可以实现电子设备100的智能认知等应用，例如：图像识别，人脸识别，语音识别，文本理解等。
外部存储器接口120可以用于连接外部存储卡，例如Micro SD卡，实现扩展电子设备100的存储能力。外部存储卡通过外部存储器接口120与CPU110通信，实现数据存储功能。例如将音乐，视频等文件保存在外部存储卡中。
内部存储器121可以用于存储计算机可执行程序代码，所述可执行程序代码包括指令。CPU110通过运行存储在内部存储器121的指令，从而执行电子设备100的各种功能应用以及数据处理。内部存储器121可以包括存储程序区和存储数据区。其中，存储程序区可存储操作系统，至少一个功能所需的应用程序(比如声音播放功能，图像播放功能等)等。存储数据区可存储电子设备100使用过程中所创建的数据(比如音频数据，电话本等)等。此外，内部存储器121可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件，闪存器件，通用闪存存储器(universal flash storage，UFS)等。
MMU111可以设置在协处理器(图1中未示出)中，该协处理器设可以设置于CPU110与内部存储器121以及外部存储器接口120的总线之间。当CPU110需要访问内部存储器121(即前述中的内存)时，可以提供一个虚拟地址，MMU将该虚拟地址映射为物理地址，进而使CPU110能够基于该物理地址，向内部存储器121中读取或写入数据。
虚拟地址为电子设备中的操作系统能够识别或产生的地址空间中的某个地址，其大小范围可以由CPU110中运行的操作系统的位数确定。比如，如果CPU110中运行的操作系统为32位，虚拟地址也为32位，其地址范围为0-0xFFFFFFFF(4GB)；如 果CPU110中运行的操作系统为64位，虚拟地址也为64位，其地址空间为0-0xFFFFFFFFFFFFFFFF(16EB)。
其中，虚拟地址可以根据实际需要被划分为多个虚拟地址空间，比如用户态地址空间和内核态地址空间。用户态地址空间可以由用户态程序(比如读、写、打开、关闭或绘图)和内核态程序(比如进程管理、存储管理、文件管理或设备管理)访问，内核态地址空间可以仅由内核态程序在运行时访问。
物理地址可以为内部存储器121等硬件存储设备实际所具有的地址空间中的某个地址。物理地址的地址空间可以小于虚拟地址的地址空间，比如当虚拟地址的地址空间的大小可以为4GB时，物理地址的地址空间的大小可以为256MB。
MMU111可以包括若干个ALU112(图1中仅示出了1个)、TTBCR113和若干个TTBR114(图1中仅示出了2个)。
TTBCR113可以用于存储TTBR的相关控制信息，比如指定内核态地址空间和用户态地址空间所对应的TTBR114，在本申请实施例中，TTBCR113中的预留位还可以用于指示在对虚拟地址进行映射之前是否对虚拟地址地址进行偏移。
TTBR114可以用于指示一级页表的基址(即该一级页表中第一个表项的表项索引地址)。ALU112可以用于进行逻辑运算，比如将虚拟地址向上或下偏移。
电子设备100可以通过音频模块170，扬声器170A，受话器170B，麦克风170C，耳机接口170D，以及应用处理器等实现音频功能。例如音乐播放，录音等。
音频模块170用于将数字音频信息转换成模拟音频信号输出，也用于将模拟音频输入转换为数字音频信号。音频模块170还可以用于对音频信号编码和解码。在一些实施例中，音频模块170可以设置于CPU110中，或将音频模块170的部分功能模块设置于CPU110中。
扬声器170A，也称“喇叭”，用于将音频电信号转换为声音信号。电子设备100可以通过扬声器170A收听音乐，或收听免提通话。
受话器170B，也称“听筒”，用于将音频电信号转换成声音信号。当电子设备100接听电话或语音信息时，可以通过将受话器170B靠近人耳接听语音。
麦克风170C，也称“话筒”，“传声器”，用于将声音信号转换为电信号。当拨打电话或发送语音信息时，用户可以通过人嘴靠近麦克风170C发声，将声音信号输入到麦克风170C。电子设备100可以设置至少一个麦克风170C。在另一些实施例中，电子设备100可以设置两个麦克风170C，除了采集声音信号，还可以实现降噪功能。在另一些实施例中，电子设备100还可以设置三个，四个或更多麦克风170C，实现采集声音信号，降噪，还可以识别声音来源，实现定向录音功能等。
耳机接口170D用于连接有线耳机。耳机接口170D可以是USB接口130，也可以是3.5mm的开放移动终端平台(open mobile terminal platform，OMTP)标准接口，美国蜂窝电信工业协会(cellular telecommunications industry association of the USA，CTIA)标准接口。
按键190包括开机键，音量键等。按键190可以是机械按键。也可以是触摸式按键。电子设备100可以接收按键输入，产生与电子设备100的用户设置以及功能控制有关的键信号输入。
马达191可以产生振动提示。马达191可以用于来电振动提示，也可以用于触摸振动反馈。例如，作用于不同应用(例如拍照，音频播放等)的触摸操作，可以对应不同的振动反馈效果。作用于显示屏194不同区域的触摸操作，马达191也可对应不同的振动反馈效果。不同的应用场景(例如：时间提醒，接收信息，闹钟，游戏等)也可以对应不同的振动反馈效果。触摸振动反馈效果还可以支持自定义。
指示器192可以是指示灯，可以用于指示充电状态，电量变化，也可以用于指示消息，未接来电，通知等。
SIM卡接口195用于连接SIM卡。SIM卡可以通过插入SIM卡接口195，或从SIM卡接口195拔出，实现和电子设备100的接触和分离。电子设备100可以支持1个或N个SIM卡接口，N为大于1的正整数。SIM卡接口195可以支持Nano SIM卡，Micro SIM卡，SIM卡等。同一个SIM卡接口195可以同时插入多张卡。所述多张卡的类型可以相同，也可以不同。SIM卡接口195也可以兼容不同类型的SIM卡。SIM卡接口195也可以兼容外部存储卡。电子设备100通过SIM卡和网络交互，实现通话以及数据通信等功能。在一些实施例中，电子设备100采用eSIM，即：嵌入式SIM卡。eSIM卡可以嵌在电子设备100中，不能和电子设备100分离。
电子设备100的软件系统可以采用分层架构，事件驱动架构，微核架构，微服务架构，或云架构。
当电子设备中的CPU访问内存时，CPU向MMU发送虚拟地址。由MMU将虚拟地址映射转换为对应的物理地址，即将对虚拟地址的访问转换为对物理内存的访问，其目的是为了节省物理地址空间以及对物理地址空间进行保护。其中，MMU可以采用分页机制，将虚拟地址空间以页为单位进行管理，每页可以包括预设大小的虚拟地址空间。
虚拟地址空间可以包括一个以上的虚拟地址，且一个虚拟地址空间可以对应一个页表集合。该页表集合可以用于确定该虚拟地址空间的虚拟地址所对应的物理地址，该页表集合可以包括一个一级页表，或者，该页表集合可以包括一个一级页表和至少一个次级页表，该次级页表可以包括二级页表、三级页表甚至更低层级的页表。相应的，MMU可以通过至少一级映射来确定与虚拟地址对应的物理地址，映射的级数与页表集合的级数一致。比如，当通过一级映射来确定与虚拟地址对应的物理地址时，该一级映射称为段映射，页表集合可以只包括一级页表；当通过两级映射来确定与虚拟地址对应的物理地址时，该两级映射称为页映射，页表集合可以包括一个一级页表和至少一个二级页表。
其中，页表是一种存储在内存中的特殊数据结构。该页表可以作为虚拟地址空间的索引并可以包括多个表项，每个表项包括表项索引地址以及物理地址之间的关联关系，其中，物理地址可以承载在该表项的页表描述符中，该页表描述符可以用于指示下一级页表的基址或与虚拟地址对应的物理地址的基址。比如，在一级映射中，一级页表中的页表描述符用于指示段基址，该段基址即为与虚拟地址对应的物理地址的基址；在二级映射中，一级页表中的页表描述符用于指示二级页表的基址，二级页表中的页表描述符可以用于指示页基址，该页基址即为与虚拟地址对应的页的物理地址基址。
当然，在实际应用中，页表描述符还可以用于指示更多与地址虚实映射的相关信息，比如页表描述符还包括用于映射级数指示位和粒度指示位，其中，映射级数指示位可以用于指示当前映射的映射级数或是否存在下一级映射的映射级数指示位(即一级映射还是两级映射)，粒度指示位可以用于指示段映射或页映射的粒度指示位(即页表所关联的虚拟地址空间的大小)。
请参照图2，为本申请实施例所提供的一种虚拟地址空间、页表和物理地址空间之间的逻辑关系的示意图。虚拟地址空间的地址范围为[0x00000000,0xFFFFFFFF]，虚拟地址空间的大小为4GB，其中，用户态地址空间的地址范围为[0x00000000,0x80000000)(即第0GB-第2GB)，内核态地址空间的地址范围为[0x80000000-0xFFFFFFFF](即第2GB-第4GB)，物理地址空间的地址范围(0x40000000～0XBFFFFFFF)，大小为2GB。通过TTBCR设置基于TTBR1中存储的页表1的基址，由页表1确定内核态地址空间201的虚拟地址映射至物理地址空间的物理地址，基于TTBR0中存储的页表2的基址，由页表2确定用户态地址空间的虚拟地址映射至物理地址空间的物理地址。
请参照图3，为本申请实施例所提供的一种一级页表的页表描述符的示意图。在32位的操作系统中，该页表描述符的第0-1位为映射级数指示位，当第[1:0]位(即第[1]位和第[0]位)为10时，当前映射为一级映射(即段映射)，该页表描述符中最高12或8位存储的段基址；当第[1:0]位为01时，当前映射为两级映射(即页映射)，该页表描述符中最高22位存储的是二级页表的基址。该页表描述符的第18位可以为映射粒度指示位，当第[18]位为0时，映射粒度为1MB，该页表描述符中最高12位存储的段基址，当第[18]位为1时，映射粒度为16MB，该页表描述符中最高8位存储的段基址。
请参照图4，为本申请实施例所提供的一种二级页表的页表描述符的结构示意图。在32位的操作系统中，该页表描述符中的第[1:0]位为映射粒度指示位。其中，当第[1:0]位为10或11时，映射粒度为4KB，页面描述符最高20位为页基址；当第[1:0]位为01时，映射粒度为64KB，页面描述符最高16位为页基址。
另外，根据映射级数的不同，虚拟地址空间中虚拟地址的各比特位也会有不同的含义。虚拟地址可以包括至少一级页表索引位和物理地址偏移位。其中，各级索引位可以用于指示该级页表中与该虚拟地址对应的页表描述符，在该级页表中的具体位置，物理地址偏移位可以用于指示该虚拟地址所对应的物理地址的偏移量，该物理地址偏移位与由该虚拟地址空间对应的页表集合所确定的物理地址基址(比如段基址或页基址)的和，即为该虚拟地址对应的物理地址。
例如，电子设备中的操作系统为32位，采用一级映射，映射粒度为1MB，虚拟地址中第[31:20]位为一级页表索引位，第[19:0]位为段偏移位。或者，当采用两级映射时，映射粒度为4KB，第二虚拟地址中第[31:20]位为一级页表索引位，第[19:12]位为二级页表索引位，第[11:0]位为页偏移位。
由前述可知，虚拟地址空间的起始虚拟地址可能并不是从0开始的，而在一些实施例中，页表作为虚拟地址空间的索引，其所包括的表项是按照虚拟地址从0到该虚拟地址空间的最大虚拟地址分配的，因此会导致该页表中的表项数目大于该虚拟地址 空间实际所需要的表项数目，该页表中表项索引地址较低的部分表项不会被利用到，这些表项所占据的内存空间便会被浪费，内存利用率较低。
请参照图5，为一种虚拟地址空间、页表和物理地址空间之间的逻辑关系的示意图。在32位操作系统中，内核态地址空间501的地址范围为[0x80000000，0xFFFFFFFF]，物理地址空间503地址范围为[0x40000000，0XBFFFFFFF]，采用一级页表502进行映射(即一级页表502与内核态地址空间501对应)，该一级页表中的每个表项关联1MB的虚拟地址，那么总共需要4GB/1MB＝4K(即4096)个表项，且由于每个表项需要占用4B的内存，该一级页表402一共需要占用16KB的内存。内核态地址空间501的起始地址为0x80000000，对应的表项索引为0x80000000/0x100000＝0x800，基于该表项索引0x800可以确定0x80000000所对应的物理地址为0x40000000。但由图5可知，在该一级页表501中，在确定内核态地址空间501中虚拟地址所对应的物理地址时，实际只占用了高地址方向大于或等于0x800之后的2K(即2048)个表项，这2K个表项中包括页表描述符，而低址方向[0X000，0X7FF]处的2K个表项并未被利用到，因此低址方向的2K个表项所占据的8KB内存被浪费。相似的，在二级页表和三级页表等次级页表中也会存在相同的问题。
为解决这一技术问题，本申请实施例提供了一种确定物理地址的方法。
在本申请实施例中，当MMU获取到第一虚拟地址空间的第一虚拟地址时，可以确定第一页表中第一虚拟地址对应的第一表项索引地址，根据第一表项索引地址，从第一页表中确定第一虚拟地址对应的第一目标物理地址。由于第一页表可以用于确定第一虚拟地址空间中每个虚拟地址对应的物理地址，第一虚拟地址空间的起始虚拟地址与第一页表中的第二表项索引地址对应，第二表项索引地址大于或等于第一页表的基址，且小于起始虚拟地址除以第二虚拟地址空间的大小的商与第一页表的基址的和，第一页表的最大表项索引地址小于第一虚拟地址空间的最大虚拟地址除以第二虚拟地址空间的大小的商与第一页表的基址的和，第二虚拟地址空间为与所述第一页表中任一表项关联的虚拟地址空间，因此第一页表最少可以只包括第一虚拟地址空间实际所需的表项，从而能够节省内存，提高内存的利用率。
下面以具体地实施例对本申请的技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
在MMU首次执行本申请实施例所提供的一种确定物理地址的方法之前，需要对MMU进行初始化设置。
请参照图6，为本申请实施例所提供的一种映射初始化设置的流程图。
S601，对页表进行配置。
为了减少页表所占的内存，对于包括的表项数目大于对应虚拟地址空间实际需要的页表数目的页表，可以将该页表中的页表描述符按照在页表中的位置向下(即低址方向)偏移，从而减少未被利用的表项数目，所节省的存储空间可以被释放或者作为普通内存使用。
可选地，可以获取第一虚拟地址空间对应的第二页表，如果第四表项索引地址大于第二页表的基址，那么可以确定第二页表中存在未被利用的表项，可以将第二页表中的页表描述符依次向下偏移第一表项数目个表项，并将第二页表中高址部分的第一 表项数目个表项删除，从而得到与第一虚拟地址空间对应的第一页表。
其中，第一页表和第二页表可以用于确定第一虚拟地址空间中每个虚拟地址对应的物理地址。第四表项索引地址为第一虚拟地址空间的起始虚拟地址在第二页表中所对应表项索引地址，当将第二页表中的页表描述符依次向下偏移第一表项数目个表项时，第四表项索引地址与第二表项索引地址相同，第二表项索引地址为第一虚拟地址空间的起始地址在第一页表中所对应表项索引地址。第一页表可以包括至少一个表项，第一虚拟地址空间的起始虚拟地址与第一页表的第二表项索引地址对应，第二表项索引地址大于或等于第一页表的基址，且小于第一虚拟地址空间的起始虚拟地址与表项所关联的第二虚拟地址空间的大小的商与第一页表的基址的和，第一页表的最大表项索引地址小于第一虚拟地址空间的最大虚拟地址除以第二虚拟地址空间的大小的商与第一页表的基址的和，第二虚拟地址空间可以为第一页表或第二页表中每个表项所对应的虚拟地址空间，且第二虚拟地址空间可以是第一虚拟地址空间的子集。
可选地，第一表项数目可以大于0且小于或等于第二表项数目。
其中，第二表项数目可以为第二页页表中的页表描述符可向下偏移的最大值。第二表项数目的计算方式可以有多种，但多种计算方式下的计算结果可以是相同的，比如第二表项数目＝第一虚拟地址空间的起始虚拟地址/第二虚拟地址空间的大小，或者，第二表项数目＝第二页表的表项数目-第一虚拟地址空间的大小/第二虚拟地址空间的大小。
需要说明的是，第一表项数目越大，则表示表项偏移的幅度越大，所节省的内存的越大。以第二页表和第一页表为例，第一页表比第二页表所节省的内存＝第一表项数目*第二页表(或第一页表)中每个表项所占据的内存大小。
请参照图7，为本申请实施例所提供的一种虚拟地址空间与页表的逻辑关系示意图。由图7可知，第二页表720所关联的虚拟地址空间为第一虚拟地址空间710，第二页表720包括多个表项721，且每个表项721所关联的虚拟地址空间为第二虚拟地址空间711，第二虚拟地址空间为第一虚拟地址空间的子集，第一虚拟地址空间的大小＝表项721的数目*第二虚拟地址空间的大小。
当然，在实际应用中，也可以先获取第一虚拟地址空间，如果第一虚拟地址空间的起始虚拟地址大于0，则第二页表中的第四表项索引地址可能会大于第二页表的基址，因此可以将第二页表的页表描述符依次向下偏移与第二页表对应的第一表项数目个表项，得到第一页表。
可选地，第一虚拟地址空间为内核态地址空间，由于图5可知，其存储空间为2GB，地址范围为[0x80000000-0xFFFFFFFF]，起始虚拟地址为0x80000000，该内核态地址空间对应的第二页表为一级页表502，其中每个表项对应1MB的第二虚拟地址空间，每个表项占据4B的内存，一级页表502中与该起始虚拟地址对应的第四表项索引地址为0X800。由于0X800大于一级页表的基址0X00，因此一级页表502中0X00-0X7FF共2GB/1MB＝2K个表项未被利用，那么若对一级页表502进行偏移，最多可以偏移2K个表项。当将一级页表502中的页表描述符向下偏移2K个表项时，得到第一页表为一级页表801，如图8所示。在一级页表801中，第二表项索引地址为0X00，0X00关联的物理地址与图5一级页表502中0X800所关联的物理地址相同，均为0x40000000， 但与一级页表502相比可知，一级页表801节省了2K*4B＝8KB的内存。
需要说明的是，二级页表和三级页表等次级页表的偏移方式，可以与一级页表的偏移方式相似，本申请实施例对此不再一一赘述。
S602，对寄存器进行配置。
其中，寄存器配置可以包括在TTBCR的预留位中增加偏移指示位并将偏移指示位设置为第一指示符或第二指示符，还可以包括指定当前进行地址虚拟映射的TTBR。
可选地，可以在MMU中增加用于实现虚拟地址偏移运算的ALU。
S603，开启MMU功能。
为了与现有技术进行兼容并减少用户感知，可以在TTBCR的预留位中增加偏移指示位(记为offset1)来指示是否对虚拟地址进行偏移。如果offset1＝1，则表示开启偏移功能，ALU对虚拟地址进行偏移运算。如果offset1＝0，则表示关闭偏移功能，ALU不对虚拟地址进行偏移运算，或者将虚拟地址直接传输给后续的功能模块。另外，还可以通过TTBCR指示当前用于地址虚实映射的TTBR。
例如，可以在操作系统启动的过程中，通过下述指令配置偏移指示位，以指示开启偏移功能。
orr r12，#(1<<3)；
mcr p15，0，r12，c2，c0，2；
其中，orr为位置1指令，用于在两个操作数进行逻辑或运算，并把结果放入目的寄存器中，orr r12，#(1<<3)可以表示将r12置1；mcr为协处理器CP15的操作指令，TTBCR可以位于该协处理器CP15中，mcr p15，0，r12，c2，c0，2表示将r12写入CP15的c1中。那么通过上述指令，即可以将TTBCR113的offset1设置为1，从而指示开启偏移功能。
需要说明的是，在本申请实施例中，是通过TTBCR中的偏移指示位来指示是否对虚拟地址进行偏移，当该偏移指示位为1时，即能够作为指示对虚拟地址进行偏移的页表偏移标志信息。但可以理解的是，在实际应用中，可以通过其他形式的信息作为页表偏移标志信息，本申请实施例对此页表偏移标志信息的形式不做具体限定。
另外，在另一种可能的实现方式中，也可以不设置页表偏移标志信息，包括不在TTBCR的预留位中增加偏移指示位，那么在后续确定物理地址的过程中，也就不需要再获取页表偏移标志信息。
需要说明的是，在实际应用中，S601也可以在S603之前的任一时机执行。
当对MMU初始化设置完成时，MMU可以通过下述步骤来确定物理地址。
请参照图9，为本申请实施例所提供的一种确定物理地址的方法的流程图。需要说明的是，该方法并不以图9以及以下所述的具体顺序为限制，应当理解，在其它实施例中，该方法其中部分步骤的顺序可以根据实际需要相互交换，或者其中的部分步骤也可以省略或删除。该方法包括如下步骤：
S901，MMU获取第一虚拟地址空间的第一虚拟地址。
由于CPU在运行过程中需要访问内存，但CPU直接访问的是虚拟地址，为了将该访问转换为针对内存物理地址的访问，MMU可以从CPU获取虚拟地址。且由于对于第一虚拟地址空间，其所关联的第一页表是经过偏移之后的页表，那么在确定第一 虚拟地址空间中的第一虚拟地址对应的第一目标物理地址，与确定不属于第一虚拟地址空间的虚拟地址对应的物理地址时，也可以分别采取不同的方式。因此，为了便于后续确定虚拟地址对应的物理地址所采取的方式，可以确定该虚拟地址是否为第一虚拟地址空间中的第一虚拟地址。
MMU可以事先确定第一虚拟地址空间的地址范围，将获取到的虚拟地址与第一虚拟地址空间的起始虚拟地址和结束虚拟地址进行比较，如果该虚拟地址大于或等于该起始虚拟地址且小于或等于该结束虚拟地址，则可以将该虚拟地址确定为第一虚拟地址。
例如，请再次参考图5和图8第一虚拟地址空间为内核态地址空间，其地址范围为[0x80000000-0xFFFFFFFF]，对应的第一页表为一级页表801，一级页表801是由一级页表502迁移得到的，因此若获取到的第一虚拟地址为[0x80000000-0xFFFFFFFF]中的任一个，则可以执行S902。
S902，MMU获取页表偏移标志信息。若获取页表偏移标志信息到则执行S903，否则执行S905。
由前述可知，本申请实施例可以对页表进行偏移，那么相应的，在确定第一虚拟地址对应的物理地址的方式，也会与不对页表进行偏移时有所不同，为了使MMU兼容偏移和不偏移页表时两种不同的确定物理地址方式，可以设置页表偏移标志信息，并在确定与第一虚拟地址对应的物理地址时获取该页表偏移标志信息。如果在确定与第一虚拟地址对应的物理地址时获取到该页表偏移标志信息，则可以确定页表发生了偏移，那么在后续步骤中可以采取相适应的方式来确定该物理地址。
可选地，MMU可以获取TTBCR中的偏移指示位，若该偏移指示位为第一指示符(比如1)，则可以确定获取到页表偏移标志信息，从而执行S903；若该偏移指示位为第二指示符(比如0)，可以确定未获取到页表偏移标志信息，从而执行S905。
当然，在实际应用中，若页表偏移标志信息还存在其他形式，那么也可以通过其他相应的方式来判断是否获取到页表偏移标志信息。比如，在另一种可能的实现方式中，可以在MMU中额外设置偏移指示模块，该偏移指示模块可以包括可作为该页表偏移标志信息的特定字符串，可以从该偏移指示模块中获取该特定字符串，若获取到该特定字符串则可以确定获取到该页表偏移标志信息，否则可以确定未获取到该页表偏移标志信息。
需要说明的是，在实际应用中，也可以不考虑对页表不偏移情况的兼容，也就不执行S902，而是在S901之后直接执行S903，即S902是可选地步骤。
S903，MMU确定第一页表中第一虚拟地址对应的第一表项索引地址。
由前述可知，页表中的表项包括表项索引地址与物理地址之间的关联关系，因此，为了确定与第一虚拟地址对应的第一目标物理地址，可以先确定第一页表中第一虚拟地址对应的第一表项索引地址。
在一种可能的实现方式中，当MMU来确定第一页表中第一虚拟地址对应的第一表项索引地址时，由于第一页表在偏移前后表项所存储的页表描述符可能发生了改变，该表项所关联的物理地址也会发生改变，即关联同一物理地址的表项索引发生了改变，因此在确定第一页表中第一虚拟地址对应的第一表项索引地址时，可以通过下述方式 1或方式2实现：
方式1、MMU基于第一虚拟地址和第一偏移值，确定第二虚拟地址。MMU基于第二虚拟地址，确定第一表项索引地址。其中，第一虚拟地址大于第二虚拟地址。换言之，第二虚拟地址等于第一虚拟地址减去第一偏移值得到。
在方式1中MMU先对第一虚拟地址进行相适应的偏移。
其中，MMU可以通过ALU来基于第一虚拟地址和第一偏移值，确定第二虚拟地址。
需要说明的是，第一偏移值可以事先确定，且第一偏移值可以小于或等于第一虚拟地址空间的起始虚拟地址。其中，第一偏移值＝第一页表对应的第一表项数目*第一页表各表项关联的第二虚拟地址空间的大小，第二虚拟地址＝第一虚拟地址-第一偏移值。
例如，电子设备的操作系统为32位，如图5和图8所示，第一页表为一级页表，该一级页表向下偏移了2K个表项，其中每个表项中的页表描述符关联1MB的虚拟地址空间，那么第一偏移值＝2K*1MB＝2GB，即0x80000000。
当MMU对第一虚拟地址完成了偏移并确定了第二虚拟地址时，可以确定第一页表的基址，基于第一页表的基址和第二虚拟地址，确定第一表项索引地址。且由于在确定第一虚拟地址对应的第一目标物理地址时，是依次从一级页表、二级页表、三级页表……进行查找，直至查找到对应的第一目标物理地址。因此可以通过下述两种可能的实现方式来基于第一页表的基址和第二虚拟地址，确定第一表项索引地址：
在一种可能的实现方式中，当第一页表为一级页表时，可以将第一虚拟地址与各TTBR对应的虚拟地址空间进行比较，如果第一虚拟地址属于某个TTBR对应的虚拟地址空间(第一虚拟空间可以是该TTBR对应的虚拟地址空间的子集)，则从该虚拟地址空间对应的TTBR中获取第一页表的基址。将第一页表的基址与第二虚拟地址中的一级页表索引位的和，确定为第一表项索引地址。
为了详细说明方式1，现请参照图10，为本申请实施例所提供的一种虚拟地址空间、页表和物理地址空间之间的逻辑关系的示意图。电子设备中的操作系统为32位，第一虚拟地址空间为内核态地址空间501，地址范围为[0x80000000-0xFFFFFFFF]。以第一虚拟地址空间中的第一虚拟地址为0x80100000为例，MMU可以确定与内核态地址空间501对应的TTBR为TTBR1，从TTBR1中获取一级页表801的基址为0X000。由0X000表项中的页表描述符可知，页表描述符的映射级数指示位[1:0]为10，粒度指示位[18]为0，则确定当前为一级映射，且映射粒度为1MB，因此将第一虚拟地址向下偏移0x80000000，得到第二虚拟地址为0x00100000，第二虚拟地址中第[31:20]位为一级页表索引位，第[19:0]位为段偏移位。MMU将第一虚拟地址第[31:20]位0X001和一级页表的基址0X000的和0X001，确定为第一表项索引地址，0X001表项中的页表描述符即能够指示0x80100000所关联的第一目标物理地址为0x40100000。当然，如果页表描述符的映射级数指示位[1:0]为01，则确定还包括二级页表，页表描述符第[31-20]位为二级页表的基址，相应的，第二虚拟地址中第[31:20]位为一级页表索引位，第[19:12]位为二级页表索引位，第[11:0]位为页偏移位。
在另一种可能的实现方式中，当第一页表为次级页表时，可以基于第三页表，确 定第一页表的基址，基于第一页表的基址和第二虚拟地址，确定第一表项索引地址，其中，第三页表为与第一页表相邻的前一级页表。
以第一页表为二级页表，第三页表为一级页表为例，MMU可以基于第三页表中页表描述符的粒度指示位，从该页表描述符中获取二级页表的基址，从第一虚拟地址空间获取二级页表索引位，将二级页表的基址和二级页表索引位的和，确定为第一表项索引地址。
例如，电子设备中的操作系统为32位，MMU确定一级页表中与第一虚拟地址对应的页表描述符地映射级数指示位[1:0]为01，即确定还包括二级页表，则获取该页表描述符的第[31-20]位作为二级页表的基址，获取第二虚拟地址第[19:12]位作为二级页表索引位，将二级页表的基址和二级页表索引位的和确定为第一表项索引地址。
需要说明的是，当第一页表为其他次级页表时，其基于第二虚拟地址，确定第一表项索引地址的方式，可以与当第一页表为二级页表时的方式相似，此处不再一一赘述。
方式2、MMU基于第一虚拟地址，确定待偏移的第三表项索引地址，基于第三表项索引地址和第二偏移值，确述第一表项索引地址。
其中，当第一页表为一级页表时，MMU可以按照与前述相似的方式，确定一级页表的基址，并从第一虚拟地址中获取一级页表索引位，将一级页表索引位和一级页表的基址的和，确定第三表项索引地址，之后可以对第三表项索引地址进行偏移，包括将第三表项索引地址减去第二偏移值，从而得到第一表项索引地址。
需要说明的是，第二偏移值可以事先确定，且第二偏移值＝第一表项数目。
为了详细说明方式2，现参照图11，为本申请实施例所提供的一种虚拟地址空间、页表和物理地址空间之间的逻辑关系的示意图。电子设备中的操作系统为32位，第一虚拟地址空间为内核态地址空间501，地址范围为[0x80000000，0xFFFFFFFF]。对于第一虚拟地址空间的第一虚拟地址0x80100000，MMU可以确定与内核态地址空间501对应的TTBR为TTBR1，从TTBR1中获取一级页表801的基址为0X000。由0X000表项中的页表描述符可知，页表描述符的映射级数指示位[1:0]为10，粒度指示位[18]为0，则确定当前为一级映射，且映射粒度为1MB。因此，第一虚拟地址中的0x80100000中第[31:20]位为一级页表索引位，第[19:0]位为段偏移位。MMU将第一虚拟地址第[31:20]位0X801和一级页表的基址0X000的和0X801，确定为第三表项索引地址，再将第三表项索引地址(0X801)减去第一表项数目0X800(二进制数值2K对应的16进制数值)的差，确定为第一表项索引地址0X001。
S904，MMU根据第一表项索引地址，从第一页表中确定第一虚拟地址对应的第一目标物理地址。
由于第一表项索引地址是与第一虚拟地址对应的表项索引地址，因此可以基于第一表项索引地址，确定第一页表中与第一虚拟地址对应的表项，基于该表项确定第一目标物理地址。
当第一页表为最后一级页表(比如一级映射中的一级页表或二级映射中的二级页表)时，第一表项索引地址对应的表项中的页表描述符可以指示第一目标物理地址的基址，因此，MMU可以获取从该页表描述符中获取第一目标物理地址的基址，并从 第一虚拟地址或第二虚拟地址中获取物理地址偏移位，将第一目标物理地址的基址与物理地址偏移位的和，确定为第一目标物理地址。当第一页表不为最后一级页表时，第一表现索引地址可以指示下一级页表的基址。MMU可以继续查找下一级页表中与第一虚拟地址对应的第一表项索引地址，直至查找到最后一级页表，从而确定第一目标物理地址。也即是，MMU可以至少执行一次S903和S904，从依次获取一级页表、二级页表、三级页表……来确定第一虚拟地址对应的第一目标物理地址。
需要说明的是，由于对第一虚拟地址进行偏移时，偏移的实际是第一虚拟地址中的至少一级页表索引位，而物理地址偏移位并未改变，所以MMU可以从第一虚拟地址或第二虚拟地址中获取物理地址偏移位。
请继续参照图10和图11，由于第一页表为一级页表801，因此一级页表801中0X001表项中的页表描述符所指示的就是与第一虚拟地址0x80100000对应的第一目标物理地址的基址0x40100000，且第一虚拟地址0x80100000与第二虚拟地址的第[19:0]位都是0，即物理地址偏移位为0，因此第一目标物理地址为0x40100000+0x00000000＝0x40100000。当然，若该页表描述符的映射级数指示位[1:0]为01，则确定还包括二级页表，该页表描述符第[31-20]位为二级页表的基址，则可以返回S605，以从二级页表确定第一目标物理地址。
由前述可知，在确定第一虚拟地址对应的第一目标物理地址的过程中，可能需要查找多个层级的页表，第一页表可能是任一级页表，即任一页表均可能发生偏移。那么如果MMU是先对第一虚拟地址进行偏移得到第二虚拟地址，再基于第二虚拟地址，从第一页表中确定对应的第一表项索引地址，则无论该多个层级的页表中那些页表发生了偏移，最少只要对第一虚拟地址进行一次偏移，所得到的第二虚拟地址就可以与偏移后的页表相配。如果MMU先由第一虚拟地址确定第三表项索引地址，再对第三表项索引地址进行偏移，得到第一表项索引地址，则可以在每一层级发生偏移的页表中确定第一表项索引地址时，单独针对该页表对第三表项索引地址进行偏移来得到第一表项索引地址。
S905，确定与第一页表对应的第二页表中第一虚拟地址对应的第三表项索引地址，根据第三表项索引地址，从与第一页表对应的第二页表中确定第一虚拟地址对应的第二目标物理地址。
其中，S905的操作方式，可以与前述S903和S904相似，区别在于，在S905中，不需要对第一虚拟地址或第三表项地址进行偏移。
需要说明的是，在本申请实施例中，第一页表是经过对第二页表中的表项进行偏移得到的，因此，通过S903-S904从第一页表所确定的第一目标物理地址与通过S905从第二页表所确定的第二目标物理地址可以相同。电子设备的内存中可以只存储第一页表或第二页表，如果存储的是第一页表，则MMU在S902中能够获取到页表偏移标志信息，从而执行S903-S904。如果存储的是第二页表，则MMU在S902获取不到页表偏移标志信息，从而执行S905。
可以理解的是，若MMU分别基于S903-S304以及S905，从同一页表(第一页表或第二页表)确定第一目标物理地址和第二目标物理地址，则所确定的第一目标物理地址和第二目标物理地址可以是不同的。
在本申请实施例中，当MMU获取到第一虚拟地址空间的第一虚拟地址时，可以确定第一页表中第一虚拟地址对应的第一表项索引地址，根据第一表项索引地址，从第一页表中确定第一虚拟地址对应的第一目标物理地址。由于第一页表可以用于确定第一虚拟地址空间中每个虚拟地址对应的物理地址，第一虚拟地址空间的起始虚拟地址与第一页表中的第二表项索引地址对应，第二表项索引地址大于或等于第一页表的基址，且小于起始虚拟地址除以第二虚拟地址空间的大小的商与第一页表的基址的和，第一页表的最大表项索引地址小于第一虚拟地址空间的最大虚拟地址除以第二虚拟地址空间的大小的商与第一页表的基址的和，第二虚拟地址空间为与所述第一页表中任一表项关联的虚拟地址空间，因此第一页表最少可以只包括第一虚拟地址空间实际所需的表项，从而能够节省内存，提高内存的利用率。
另外，在本申请实施例中，是将包括冗余表项的第二页表中的页表描述符向下偏移，从而减少或消除冗余表项，得到包括更少表项的第一页表，在实际应用中，为了使设置页表以及确定物理地址的方式更加灵活，也可以将第二页表向上(即高址方向)偏移，在这种情况下，第二页表可以是任意的页表，向上偏移的第三表项数目也可以是任意数值，所得到的第一页表可以包括更多的表项，相应的，MMU在确定第一虚拟地址对应的第一表项索引地址时，可以将第一虚拟地址与第一偏移值的和确定为第二虚拟地址(即将第一虚拟地址也向高址方向偏移)，再基于第二虚拟地址确定第一表项索引地址，或者，可以基于第一虚拟地址确定待偏移的第三表项索引地址，将第三表项索引地址和第二偏移值的和，确定为第一表项索引地址(即将第三表项索引地址也向高址方向偏移)。当确定第一表项索引地址时，再基于第一表项索引地址，从第一页表中确定第一虚拟地址对应的第一目标物理地址。
其中，第一偏移值＝第三表项数目*第一页表中各表项所关联的第二虚拟地址空间的大小，第二偏移值＝第三表项数目，第一虚拟地址可以小于第二虚拟地址，第三表项索引地址可以小于第一表项索引地址。
基于同一发明构思，本申请实施例还提供了一种芯片系统1200。
请参照图12，芯片系统1200包括至少一个CPU110(图12中仅示出1个)，至少一个存储器115(图12中仅示出1个)和至少一个协处理器116(图12中仅示出1个)，至少一个协处理器116中包括至少一个MMU111(图12中仅示出1个)，MMU111包括至少一个ALU112(图12中仅示出1个)、至少一个TTBCR113(图12中仅示出1个)和至少一个TTBR114(图12中仅示出1个)。
至少一个MMU111用于：
当收到至少一个CPU110发起的对至少一个存储器115的访问请求，且访问请求中携带第一虚拟地址空间的第一虚拟地址时，确定第一虚拟地址对应的第一表项索引地址；
根据第一表项索引地址，从第一页表中确定第一虚拟地址对应的第一目标物理地址；
其中，第一页表用于确定第一虚拟地址空间中每个虚拟地址对应的物理地址，第一虚拟地址空间的起始虚拟地址与第一页表中的第二表项索引地址对应，第二表项索引地址大于或等于第一页表的基址，且小于起始虚拟地址除以第二虚拟地址空间的大 小的商与第一页表的基址的和，第一页表的最大表项索引地址小于第一虚拟地址空间的最大虚拟地址除以第二虚拟地址空间的大小的商与第一页表的基址的和，第二虚拟地址空间为与第一页表中任一表项关联的虚拟地址空间。
可选地，至少一个ALU112用于，基于第一虚拟地址和第一偏移值，确定第二虚拟地址，第一虚拟地址大于第二虚拟地址；
至少一个MMU110还用于：基于第二虚拟地址，确定第一表项索引地址。
可选地，至少一个MMU110还用于：
基于第一虚拟地址，确定待偏移的第三表项索引地址；
基于第三表项索引地址和第二偏移值，确定第一表项索引地址，第三表项索引地址大于第一表项索引地址。
可选地，至少一个MMU110还用于：
获取页表偏移标志信息，页表偏移标志信息通过至少一个TTBCR113中的偏移指示位指示。
可选地，各TTBR114中可以存储一个一级页表的基址。相应的，TTBCR113中可以用于指示在确定不同虚拟地址空间中的虚拟地址所对应的物理地址时，所选用的TTBR114，即确定不同虚拟地址空间所对应的TTBR114。
可选地，至少一个协处理器116可以集成在至少一个CPU1210中。
需要说明的是，存储器115可以包括图1中的内部存储器121。
请参照图13，本申请实施例所提供的另一种芯片系统1300的结构示意图。该系统1300包括CPU110、ALU112、TTBCR113、虚拟内存转换模块117和存储器115，其中，TTBCR113、ALU112和虚拟内存转换模块117可以设置在MMU111中，且该MMU111可以设置在协处理器中，也可以集成在CPU110中。
CPU110可以发出对存储器115的访问请求，该访问请求中携带内核态地址空间的第一虚拟地址。ALU112在获取到第一虚拟地址，且确定TTBCR113中的偏移指示位为第一指示符(如offset1)时，将第一虚拟地址偏移至第二虚拟地址。虚拟内存转换模块117从内核态地址空间对应的页表集合中，基于第二虚拟地址确定第一表项索引地址，进而确定第一目标物理地址，CPU110便可以基于第一目标物理地址访问内部存储器1350。
需要说明的是，ALU112、TTBCR113、虚拟内存转换模块117可以是设置在MMU111中的，且MMU111还可以包括TTBR114。
还需要说明的是，虚拟内存转换模块117可以用于基于第三表项索引地址和第二偏移值，确定第一表项索引地址。
基于同一发明构思，本申请实施例还提供了一种电子设备，该电子设备包括前述任一种的芯片系统。
本申请实施例还提供一种计算机可读存储介质，其上存储有计算机程序，计算机程序被处理器执行时实现上述方法实施例所述的方法。
本申请实施例还提供一种计算机程序产品，当计算机程序产品在电子设备上运行时，使得电子设备执行时实现上述方法实施例所述的方法。
上述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时， 可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请实现上述实施例方法中的全部或部分流程，可以通过计算机程序来指令相关的硬件来完成，所述的计算机程序可存储于一计算机可读存储介质中，该计算机程序在被处理器执行时，可实现上述各个方法实施例的步骤。其中，所述计算机程序包括计算机程序代码，所述计算机程序代码可以为源代码形式、对象代码形式、可执行文件或某些中间形式等。所述计算机可读存储介质至少可以包括：能够将计算机程序代码携带到拍照装置/终端设备的任何实体或装置、记录介质、计算机存储器、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、电载波信号、电信信号以及软件分发介质。例如U盘、移动硬盘、磁碟或者光盘等。在某些司法管辖区，根据立法和专利实践，计算机可读介质不可以是电载波信号和电信信号。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述或记载的部分，可以参见其它实施例的相关描述。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的实施例中，应该理解到，所揭露的装置/设备和方法，可以通过其它的方式实现。例如，以上所描述的装置/设备实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通讯连接可以是通过一些接口，装置或单元的间接耦合或通讯连接，可以是电性，机械或其它的形式。
应当理解，当在本申请说明书和所附权利要求书中使用时，术语“包括”指示所描述特征、整体、步骤、操作、元素和/或组件的存在，但并不排除一个或多个其它特征、整体、步骤、操作、元素、组件和/或其集合的存在或添加。
还应当理解，在本申请说明书和所附权利要求书中使用的术语“和/或”是指相关联列出的项中的一个或多个的任何组合以及所有可能组合，并且包括这些组合。
如在本申请说明书和所附权利要求书中所使用的那样，术语“如果”可以依据上下文被解释为“当...时”或“一旦”或“响应于确定”或“响应于检测到”。类似地，短语“如果确定”或“如果检测到[所描述条件或事件]”可以依据上下文被解释为意指“一旦确定”或“响应于确定”或“一旦检测到[所描述条件或事件]”或“响应于检测到[所描述条件或事件]”。
另外，在本申请说明书和所附权利要求书的描述中，术语“第一”、“第二”、“第三”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
在本申请说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个 或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (10)

  1. 一种确定物理地址的方法，其特征在于，包括：
    当获取到第一虚拟地址空间的第一虚拟地址时，确定所述第一虚拟地址对应的第一表项索引地址；
    根据所述第一表项索引地址，从第一页表中确定所述第一虚拟地址对应的第一目标物理地址；
    其中，所述第一页表用于确定所述第一虚拟地址空间中每个虚拟地址对应的物理地址，所述第一虚拟地址空间的起始虚拟地址与所述第一页表中的第二表项索引地址对应，所述第二表项索引地址大于或等于所述第一页表的基址，且小于所述起始虚拟地址除以第二虚拟地址空间的大小的商与所述第一页表的基址的和，所述第一页表的最大表项索引地址小于所述第一虚拟地址空间的最大虚拟地址除以所述第二虚拟地址空间的大小的商与所述第一页表的基址的和，所述第二虚拟地址空间为与所述第一页表中任一表项关联的虚拟地址空间。
  2. 根据权利要求1所述的方法，其特征在于，所述确定所述第一虚拟地址对应的第一表项索引地址，包括：
    基于所述第一虚拟地址和第一偏移值，确定第二虚拟地址，所述第一虚拟地址大于所述第二虚拟地址；
    基于所述第二虚拟地址，确定所述第一表项索引地址。
  3. 根据权利要求1所述的方法，其特征在于，所述确定所述第一虚拟地址对应的第一表项索引地址，包括：
    基于所述第一虚拟地址，确定待偏移的第三表项索引地址；
    基于所述第三表项索引地址和第二偏移值，确定所述第一表项索引地址，所述第三表项索引地址大于所述第一表项索引地址。
  4. 根据权利要求1-3任一所述的方法，其特征在于，在所述确定所述第一虚拟地址对应的第一表项索引地址之前，所述方法还包括：
    获取页表偏移标志信息，所述页表偏移标志信息通过转换页表基址控制寄存器TTBCR中的偏移指示位指示。
  5. 根据权利要求1-4任一所述的方法，其特征在于，所述第一页表包括：一级页表或二级页表；或者，
    所述第一虚拟地址空间为内核态地址空间。
  6. 一种芯片系统，其特征在于，所述芯片系统包括：至少一个中央处理器CPU，至少一个存储器和至少一个协处理器，所述至少一个协处理器中包括：至少一个内存管理单元MMU；
    所述至少一个MMU用于：
    当收到所述至少一个CPU发起的对所述至少一个存储器的访问请求，且所述访问请求中携带第一虚拟地址空间的第一虚拟地址时，确定所述第一虚拟地址对应的第一表项索引地址；
    根据所述第一表项索引地址，从第一页表中确定所述第一虚拟地址对应的第一目标物理地址；
    其中，所述第一页表用于确定所述第一虚拟地址空间中每个虚拟地址对应的物理地址，所述第一虚拟地址空间的起始虚拟地址与所述第一页表中的第二表项索引地址对应，所述第二表项索引地址大于或等于所述第一页表的基址，且小于所述起始虚拟地址除以第二虚拟地址空间的大小的商与所述第一页表的基址的和，所述第一页表的最大表项索引地址小于所述第一虚拟地址空间的最大虚拟地址除以所述第二虚拟地址空间的大小的商与所述第一页表的基址的和，所述第二虚拟地址空间为与所述第一页表中任一表项关联的虚拟地址空间。
  7. 根据权利要求6所述的芯片系统，其特征在于，所述至少一个MMU包括至少一个计算逻辑单元ALU：
    所述至少一个ALU用于，基于所述第一虚拟地址和第一偏移值，确定第二虚拟地址，所述第一虚拟地址大于所述第二虚拟地址；
    所述至少一个MMU还用于：基于所述第二虚拟地址，确定所述第一表项索引地址。
  8. 根据权利要求6所述的芯片系统，其特征在于，所述至少一个MMU还用于：
    基于所述第一虚拟地址，确定待偏移的第三表项索引地址；
    基于所述第三表项索引地址和第二偏移值，确定所述第一表项索引地址，所述第三表项索引地址大于所述第一表项索引地址。
  9. 根据权利要求6-8任一所述的芯片系统，其特征在于，所述至少一个MMU还包括至少一个转换页表基址控制寄存器TTBCR，所述至少一个MMU还用于：
    获取页表偏移标志信息，所述页表偏移标志信息通过所述至少一个TTBCR中的偏移指示位指示。
  10. 一种电子设备，其特征在于，包括如权利要求6至9任一项所述的芯片系统。
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