WO2022042127A1 - 一种协程切换的方法、装置及设备 - Google Patents

一种协程切换的方法、装置及设备 Download PDF

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Publication number
WO2022042127A1
WO2022042127A1 PCT/CN2021/106729 CN2021106729W WO2022042127A1 WO 2022042127 A1 WO2022042127 A1 WO 2022042127A1 CN 2021106729 W CN2021106729 W CN 2021106729W WO 2022042127 A1 WO2022042127 A1 WO 2022042127A1
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Prior art keywords
coroutine
thread
context
running
recovery
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PCT/CN2021/106729
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English (en)
French (fr)
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程宏才
崔英利
郭海涛
张斌
周罗青
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华为技术有限公司
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Publication of WO2022042127A1 publication Critical patent/WO2022042127A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/485—Task life-cycle, e.g. stopping, restarting, resuming execution
    • G06F9/4856—Task life-cycle, e.g. stopping, restarting, resuming execution resumption being on a different machine, e.g. task migration, virtual machine migration
    • G06F9/4862—Task life-cycle, e.g. stopping, restarting, resuming execution resumption being on a different machine, e.g. task migration, virtual machine migration the task being a mobile agent, i.e. specifically designed to migrate
    • G06F9/4875—Task life-cycle, e.g. stopping, restarting, resuming execution resumption being on a different machine, e.g. task migration, virtual machine migration the task being a mobile agent, i.e. specifically designed to migrate with migration policy, e.g. auction, contract negotiation

Definitions

  • the present application relates to the field of computer technologies, and in particular, to a method, apparatus, and device for coroutine switching.
  • the operating system supports running in multi-threaded mode.
  • a large number of concurrent threads may be set in a business process. Multiple concurrent threads are executed sequentially in a round-robin scheduling manner within a time slice.
  • a thread further includes one or more coroutine tasks, and within the time slice to which the thread belongs, multiple coroutine tasks included in the thread are executed alternately in turn. Coroutine tasks are used to execute function groups including sub-functions, and each coroutine task can be used to execute one or more sub-functions.
  • the present application provides a coroutine switching method and device, which are used to implement fair switching between coroutine tasks and improve system operation stability.
  • the present application provides a coroutine switching method, the method comprising: determining a first coroutine as a timeout coroutine, and the timeout coroutine is a coroutine whose running duration reaches a first threshold; interrupting the first protocol process; switch the second coroutine as the currently executing coroutine.
  • the time-out coroutine when a time-out coroutine is identified, the time-out coroutine can be forcibly switched and switched to the second coroutine to run, so as to avoid a coroutine running for too long and other coroutines not getting the chance to execute the coroutine. Fair and stable operation between the two, and improve system performance.
  • the determining that the first coroutine is a timeout coroutine includes: starting timing when the first coroutine is started; when the running duration of the first coroutine reaches a first threshold , determine that the first coroutine is a timeout coroutine.
  • the timing is turned on, and when the timing time reaches the first threshold, the timeout coroutine of the coroutine is determined to ensure that each coroutine can be switched when the running time reaches the first threshold, ensuring that the coroutine can be switched. fair play between.
  • the switching the second coroutine as the currently executing coroutine includes: selecting the second coroutine, where the second coroutine is a task queue adjacent to the first coroutine Coroutine; take the second coroutine as the current execution coroutine.
  • the first coroutine is a time-out coroutine
  • switch to the second coroutine to avoid the first coroutine running for too long, and give other coroutines other than the first coroutine the opportunity to run to ensure the coroutine.
  • the selecting the second coroutine includes any one of the following manners: the second coroutine is randomly selected from the to-be-executed coroutines included in the first thread a coroutine; or, the second coroutine is the coroutine with the highest priority among the coroutines to be executed included in the first thread; or, the second coroutine is a pending coroutine included in the first thread Among the executed coroutines, the coroutine with the highest order at the current moment.
  • the interrupting the first coroutine includes: triggering interrupt processing, and the interrupt processing includes: saving, according to the thread state where the first coroutine is located, when the first coroutine is interrupted
  • the context is used to indicate the running information when the first thread is interrupted.
  • the first coroutine when the first coroutine is a timeout coroutine, the first coroutine can be forced to be interrupted, thereby switching to another coroutine. Further, the interrupted context of the first coroutine is saved, so that when the first coroutine is rescheduled, the current context can be restored to continue running the coroutine.
  • the storing the context when the first thread is interrupted according to the state of the first coroutine includes: when the first thread where the first coroutine is located is in an interrupted state, then The register value of the first thread is stored in a kernel shared space, where the kernel shared space is a kernel storage space corresponding to the first thread, and the register value is used to record the operation information of the first thread.
  • the method further includes: modifying the context of the interrupt return to the context of the coroutine handler; executing the interrupt return, and running the coroutine handler; wherein, running the coroutine handler uses The restoration coroutine corresponding to the first coroutine is generated at the application layer, and the restoration coroutine is executed to restore the scene when the first coroutine is interrupted.
  • the storing the context when the first thread is interrupted according to the state of the first coroutine includes: when the first thread where the first coroutine is located is in a waiting state, storing The context of the first thread stored in the first thread control block is stored in the kernel shared space, and the kernel shared space is the kernel storage space corresponding to the first thread, and the register value is used to record the first thread.
  • the running information of a thread includes: when the first thread where the first coroutine is located is in a waiting state, storing The context of the first thread stored in the first thread control block is stored in the kernel shared space, and the kernel shared space is the kernel storage space corresponding to the first thread, and the register value is used to record the first thread.
  • the running information of a thread includes: when the first thread where the first coroutine is located is in a waiting state, storing The context of the first thread stored in the first thread control block is stored in the kernel shared space, and the kernel shared space is the kernel storage space corresponding to the first thread, and the register value is used to record
  • the context in the first thread control block is stored in the kernel shared space, and the context of the thread control block is modified to the context of the coroutine handler, so that the first thread
  • the context operation of the coroutine handler is restored according to the context stored in the thread control block of the first thread, and the restoration coroutine corresponding to the first thread is generated.
  • the scheduler reschedules the restoration coroutine, the first thread can be restored.
  • the context running when the coroutine is interrupted does not need to switch the CPU to the operating permission level corresponding to the kernel mode.
  • the method further includes: modifying the context stored in the first thread control block to the context of the coroutine handler, so as to restore the first thread when the first thread is scheduled again
  • the context of the coroutine handler, running the coroutine handler running the coroutine handler; wherein, running the coroutine handler is used to generate a restoration coroutine corresponding to the first coroutine at the application layer, and executing the restoration coroutine is used for Resume the scene when the first coroutine was interrupted.
  • running the coroutine processing program includes: acquiring the register value of the first thread from the kernel shared space, and converting the register value of the first coroutine according to a preset format Save to the data structure corresponding to the first coroutine; the preset format is used to indicate the storage order of the register values of the first coroutine; according to the saved data structure, generate the first protocol The above recovery coroutine corresponding to the process.
  • the method further includes: running the recovery coroutine: reading the register value of the first coroutine from a data structure corresponding to the first coroutine according to a preset format, Write the register value to the corresponding register.
  • the above-mentioned recovery coroutine corresponding to the first coroutine is generated Before, it also includes: saving the context of the coroutine restoration program into the data structure; running the restoration coroutine, further comprising: reading the context of the coroutine restoration program from the data structure, and running the A coroutine restoration program, wherein running the coroutine restoration program is used to read the register value of the first coroutine from the data structure corresponding to the first coroutine according to a preset format, and write the register value into the corresponding register.
  • an embodiment of the present application further provides a device, the device includes a plurality of functional units, and the functional units can perform the functions performed by each step in the method of the first aspect. These functional units can be implemented by hardware or by software.
  • the device includes a detection unit and a processing unit. For the beneficial effects achieved by the device, please refer to the description of the first aspect, which will not be repeated here.
  • an embodiment of the present application further provides a device, the device includes a processor and a memory, the memory stores program instructions, and the processor executes the program instructions in the memory to implement the first aspect. provided method.
  • the device includes a processor and a memory
  • the memory stores program instructions
  • the processor executes the program instructions in the memory to implement the first aspect. provided method.
  • the present application further provides a computer-readable storage medium, where instructions are stored in the computer-readable storage medium, when the computer-readable storage medium runs on a computer, the computer executes the method provided in the first aspect.
  • the present application further provides a computer chip, where the chip is connected to a memory, and the chip is used to read and execute a software program stored in the memory, and execute the method provided in the first aspect.
  • FIG. 1 is a schematic diagram of a scenario of multi-thread concurrent execution provided by the present embodiment
  • FIG. 2 is a schematic diagram of a scenario in which a thread actively applies for switching according to this embodiment
  • FIG. 3 is a schematic diagram of the relationship between a thread and a coroutine provided by the present embodiment
  • FIG. 4 is a schematic diagram of the architecture of a possible network system provided in this embodiment.
  • FIG. 5 is a schematic diagram of a CPU workflow provided by the present embodiment
  • FIG. 6 is a schematic diagram of a scene of a stack operation provided by the present embodiment.
  • FIG. 7 is a schematic structural diagram of a coroutine switching apparatus provided in this embodiment.
  • FIG. 8 is a schematic flowchart of a coroutine switching provided by this embodiment.
  • FIG. 9 is a schematic flowchart corresponding to a coroutine switching method provided in this embodiment.
  • FIG. 10 is a schematic structural diagram of a coroutine switching device provided in this embodiment.
  • FIG. 11 is a schematic structural diagram of a coroutine switching device provided in this embodiment.
  • a process can refer to a running activity of a program with certain independent functions, and it is the carrier of the application running. It can also be understood that a process is a running instance of an application and a dynamic execution of an application. For example, when a user runs the Notepad program (Notepad), the user creates a process for accommodating the code that composes Notepad.exe and the dynamic link library it needs to call.
  • a process is an independent unit for the system to allocate and schedule resources. Each process has its own memory space, and different processes are independent of each other.
  • Threads are included in the process, created in the process, and can share the resources of the process.
  • a process contains at least one thread.
  • a thread is the basic unit for the system to allocate processor time resources, or a thread is a unit that executes independently within a process. .
  • Threads have concurrency, that is, a single process supports the execution of multiple concurrent threads, the memory space of the process is shared among each thread, and each thread executes different tasks concurrently. For example, one thread can be used to write files to disk, and another thread can be used to receive user keystrokes and respond in time, without interfering with each other.
  • FIG. 1 is a schematic diagram of concurrent execution of threads. As shown in the figure, each thread runs for a fixed duration in turn, and each thread executes in turn. Since the execution efficiency of the central processing unit (CPU) is very high, it can be done When the time slice is very short, the CPU can quickly switch between various threads, showing an effect of multiple tasks being performed at the same time, which is the so-called thread concurrency.
  • CPU central processing unit
  • the period of thread execution (fixed duration) can be called a time slice, and the state that the thread is executing is recorded as the running state; when the time slice is exhausted, the thread will be scheduled out of the running state, which can also be understood as the thread is suspended and waiting The arrival of the next time slice belonging to the thread, the state of the thread at this time can be recorded as the ready state (or the waiting state).
  • a task with a higher priority may be temporarily interrupted within the time slice of the thread running, and after the task with a higher priority is executed, resume when the thread is interrupted
  • the state continues to run until the time slice user, the state when the thread is interrupted can be recorded as the interrupted state.
  • Coroutines can refer to lightweight threads. Threads are the carriers of coroutines. Multiple coroutines can share a thread. Different coroutines also have different independent contexts, including code segments and stacks. Through coroutines Frames are executed sequentially in threads. Similarly, the context of a coroutine mainly consists of register values.
  • Threads are scheduled and managed by the operating system. At present, most operating systems schedule threads in two triggering methods: preemptive scheduling with time slice rotation and threads actively applying for scheduling.
  • the scheduling mode of time slice rotation means that the thread running time reaches a predetermined time and is forced to be switched by the operating system.
  • the way that a thread actively applies for scheduling means that the thread actively informs the operating system to switch, and the operating system determines to switch to a new thread.
  • the following is an example of the thread's active application for scheduling to introduce the thread switching process. Please refer to Figure 2 for a schematic diagram of the thread's active request for scheduling. Assuming that user program A is the currently executing thread, user program A can actively apply for scheduling.
  • the next thread to be executed is selected from the task queue, such as application B, the context of thread B is restored from memory, and the CPU is controlled from the kernel state.
  • the permissions are switched back to the running permissions corresponding to the user mode again, and application B is executed.
  • the so-called user mode and kernel mode refer to the operating state of the operating system.
  • hierarchical protection is generally implemented in computer systems, that is, according to the severity of the impact in the computer system, certain operations must be performed by certain roles with corresponding permissions, such as direct access to hardware and modification of hardware working modes and other operations require the highest permission to execute.
  • Modern CPUs generally provide a variety of operating permission levels, and the operating system is generally divided into multiple operating states to cooperate with the CPU.
  • the common states of the operating system are user mode and kernel mode.
  • the kernel mode generally has the highest authority, and all instructions and operations are allowed to be executed by the CPU; while the user mode generally has lower authority, in this state, software programs can only execute limited instructions and operations, and high-risk operations are not executed by the CPU.
  • Hardware allows, such as configuring CPU internal control registers, accessing memory addresses in the kernel section, etc.
  • a coroutine can be regarded as a function group, consisting of several sub-functions to form a relatively independent task.
  • the jump calling relationship of the function is also between the coroutine tasks, but the calling address of the next task is not specified by the current coroutine task, but determined by the scheduler.
  • the scheduler can be regarded as a special Task, the scheduler will always exist and will not exit. After the current coroutine task is completed, it will automatically jump to the context of the scheduler to run.
  • the scheduler selects the appropriate coroutine task from the currently waiting coroutine tasks and jumps Go to run in the context of the coroutine task.
  • the metadata of each coroutine task may include a coroutine control block, where the coroutine control block is used to identify the coroutine task and record the context of the coroutine task (for example, related register values) , the scheduler obtains the context of the coroutine task from the metadata of the coroutine task.
  • the conditions for triggering the above-mentioned scheduler to perform the coroutine switching include that the coroutine actively applies for scheduling, and in order to prevent a certain coroutine from taking a long time, currently, the prior art also provides a coroutine switching method of timeout detection. For example: set the timeout detection at the call entry of the sub-function of the coroutine. Each time the function is called, the total running time of the current coroutine will be calculated. If the total running time exceeds the set time, the coroutine switching interface will be actively called for coroutine program switching.
  • the present application proposes a method for switching between coroutine tasks over time. Specifically, it is used to determine whether the currently executing coroutine is a timeout coroutine. Coroutine, forcibly interrupt the first coroutine, and cut off the second coroutine as the current execution coroutine.
  • FIG. 4 is a schematic structural diagram of a network system provided by an embodiment of the present application, and the method is applied to the system.
  • the network system includes a server, a network device, and a storage device.
  • the server and memory can communicate through a network device.
  • the network device includes, but is not limited to: a switch, a router, and other devices for network connection between devices.
  • Servers and storage devices may include processors, memory, storage, and network adapters. The functions of some components are described below.
  • the memory can mainly include a storage program area and a storage data area.
  • the storage program area can store the operating system, various application programs (such as a camera application), etc.;
  • the storage data area can store data created according to the application program (such as images and videos collected by the camera application) and the like.
  • Memory includes internal memory (also known as memory, also known as main memory) and external memory.
  • External memory includes non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device, which has the characteristics of large capacity, slow speed, and no data loss after power failure, and is used for long-term or permanent use. Store programs and data.
  • the memory can include registers, high-speed random access memory, and has the characteristics of small capacity, fast speed, and volatile when power off. It is used to store currently executing data and programs. It can be understood that the memory is a channel between the CPU and the external memory, which can be used to first read the programs and data stored in the external memory into the memory, and then the programs in the memory will be read into the processor one by one for execution.
  • the register can also be integrated in the processor as a part of the processor, which will be described in detail below.
  • the processor can be a central processing unit (CPU), or a specific integrated circuit (application specific integrated circuit, ASIC), or a field programmable gate array (field programmable gate array, FPGA).
  • CPU central processing unit
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • the processor is described below by taking the CPU as an example.
  • the CPU is mainly composed of an operation unit, a control unit, a storage unit and a bus, wherein the operation unit, the control unit and the storage unit are connected to each other through the bus.
  • control unit is used to analyze the program instructions to generate control instructions.
  • control unit includes a program register (program counter, PC), an instruction register (instruction register, IR), an instruction decoder (instruction decoder, ID), an operation control unit (operation controller, OC) and the like.
  • the program register PC is used to store the address of the instruction to be read. Based on the pre-programmed program, the control unit obtains the instruction of the corresponding address according to the value of the program register PC and puts it in the instruction register IR.
  • the operation code of the instruction is sent to the instruction decoder ID for decoding, and the operation control unit OC, according to the decoding of the instruction operation code by the instruction decoder ID, generates the control instructions for all the actions required to realize the function of the instruction, and According to the determined execution sequence of the control instruction, the control instruction is sent to the corresponding component, and the control instruction is used to indicate the operation to be performed. After the execution of the current instruction is completed, the address of the next instruction is calculated and sent to the program counter PC.
  • the arithmetic unit is used for performing corresponding arithmetic operations, such as various arithmetic operations and/or logical operations, in response to the control instructions issued by the control unit.
  • the storage unit including the register group, has the characteristics of less storage information and fast access speed, etc., and is usually used by the CPU to temporarily store data, such as data waiting to be processed, or data that has been processed. Because the access speed of the register is fast, the time it takes the CPU to access the register is shorter than the time it takes to access the memory.
  • the use of registers can effectively reduce the number of times the CPU accesses the memory and improve the working speed of the CPU.
  • the register group includes special registers and general registers.
  • the processor is used to execute the operating system and application programs.
  • the operating system and the application program may be executed on the same CPU, or may be executed on different CPUs.
  • the computer is a multi-core processor, a single processor may be used to execute the operating system, and use Another processor to run the application.
  • a process can refer to an application running in the operating system. As shown in the figure, when a process is running, the operating system allocates resources such as CPU and memory to the process, wherein the memory is used to store the code of the process (for example, the process shown in the figure). code segment in ) and data (such as the data segment in the figure). It should be understood that the data segment contains the data required to complete the instructions of the code segment.
  • the program counter of the CPU is used to record the address of the code in progress (instruction address in the figure).
  • the code address may be the segment number and/or the line number of the code segment.
  • the instruction register is used to implement the function of the program counter, and is specifically used to record the instruction corresponding to the instruction address.
  • the control unit reads the instruction corresponding to the instruction address in the memory according to the instruction address of the program counter, and stores it in the instruction register.
  • control unit decodes the instruction, determines the control instruction corresponding to the operation required by the instruction according to the operation code, and sends it to the corresponding unit, such as a storage unit and/or an arithmetic unit.
  • corresponding unit such as a storage unit and/or an arithmetic unit.
  • each instruction has an opcode that identifies the nature of the operation that the instruction should perform. In short, it tells the CPU what to do.
  • control unit sends the control instruction 1 to the storage unit, and sends the control instruction 2 to the operation unit.
  • control instruction 1 includes an operation instruction and an operand address.
  • the control instruction 1 is used to instruct the storage unit to read the data of the operand address from the memory. After the storage unit reads the data, it can be temporarily stored in the corresponding register.
  • the operation unit performs operations according to the data in the register.
  • the control instruction 2 is used to instruct the operation unit to obtain data from the storage unit to perform operation.
  • the data structure in the data storage area in the memory may be a stack
  • the storage unit may also include a stack pointer (SP), which is used to save the address information of the data in the stack of the currently running application, and the storage unit is based on the stack.
  • SP stack pointer
  • the address confidence recorded by the pointer is to obtain the data in the stack corresponding to the address information in the memory.
  • the stack is a data structure in which data items are arranged in order. It consists of stack frames one by one. Each stack frame can correspond to a function call.
  • the stack frame can contain function parameter values and local variables (including register values) and some temporary data etc.
  • the way data is stored on the stack can only insert and delete data items at one end of the stack (called the top of the stack).
  • Pointers or other forms can be used to indicate the position of the top of the stack at the current moment. When new data needs to be stored, the data or the information of the data is stored to the top of the stack. At this time, the pointer indicating the top of the stack can point to the new top of the stack. s position.
  • the storage method of the stack is a logical structure, and the stack can be simply understood as a data structure with one end fixed and the other floating.
  • the way of storing and reading data can be handled according to the principle of "first in, last out”.
  • PUSH the operation stored in the stack
  • POP the operation taken out from the stack
  • the stacking operation includes: the stack pointer (SP) initially indicates the location where si is stored. When new data bp is stored in the stack, the pointer is incremented by 1. At this time, the pointer points to the location where bp is stored.
  • the process of popping is the opposite of the process of pushing.
  • the current position of the top of the stack is first determined, and then the contents of the internal memory (for example, the ram unit) indicated by the pointer are sent to the destination (for example, ram unit). , the unit addressed by the direct address), and then decrements the stack pointer (SP) by 1.
  • the internal memory for example, the ram unit
  • SP stack pointer
  • the way of storing or reading data in the stack may also adopt the principle of "first in, last out", which can be set according to business requirements during specific implementation.
  • the above is a schematic flow chart of executing an instruction. After an instruction is executed, the program counter is +1, which points to the next instruction, and the execution of the next instruction is continued through the above process.
  • the work flow of the CPU includes: sequentially reading each instruction and corresponding data from the memory, and performing arithmetic processing on the data according to the instruction operation code until the program is executed.
  • the operating system can also control the CPU to read the data stored in the specified stack address, for example, the PC value, and fill the obtained PC value into the PC register, and the CPU reads and executes the program instruction corresponding to the PC register value. , so as to achieve program switching.
  • the operating system and the application program may be executed on the same CPU, or may be executed on different CPUs.
  • a single processor may be used to execute the operating system, and use Another processor to run a service, such as an application (including a process, a thread, and a coroutine), which is not limited in this embodiment of the present application, but it should be noted that the processor that executes the embodiment of the present application is the processor that runs the service .
  • a service such as an application (including a process, a thread, and a coroutine), which is not limited in this embodiment of the present application, but it should be noted that the processor that executes the embodiment of the present application is the processor that runs the service .
  • the coroutine task control block to be executed is stored in the coroutine task queue, and the context after the last execution of the coroutine is recorded in the coroutine task control block, and the context includes register values, such as the current PC value, SP value. etc.
  • the CPU restores the context of the coroutine according to the coroutine task control block of the coroutine, for example, writes the PC value recorded in the coroutine task control block into the PC register, and writes the SP value Push the stack pointer to continue execution from the point where the last run of the coroutine stopped.
  • the context of the coroutine may also include a register value, which is not limited in this embodiment of the present application.
  • a network adapter refers to a device or device with a communication interface, which can also be called a network card, and is used to realize the connection between devices.
  • a server can realize the connection with a storage device through a network adapter.
  • the network system shown in FIG. 4 is only an example, and the network system may further include more or less network devices, for example, may also include a computing server (not shown in FIG. 4 ). Each network device in the network system may also include more or fewer components. In addition, the present application does not limit the number of network devices such as servers, gateway devices, and storage servers included in the network system.
  • the coroutine switching method provided in this embodiment of the present application may be deployed in the network system shown in FIG. 4 , specifically, may be deployed in one of the devices in the network system, such as a server, a network device, or a storage device.
  • the embodiment of the present application does not limit the form of the processor in the deployed device, for example, it may be a CPU, an FPGA, etc., where the CPU may adopt an ARM or X86 architecture, which is not limited in the embodiment of the present application.
  • ARM is a 32-bit reduced instruction set (RISC) processor architecture, suitable for equipment in the field of mobile communications, such as portable devices (mobile phones, multimedia players, handheld electronic games and computers), computer peripherals (hard drives, desktop routers), etc.
  • RISC reduced instruction set
  • the X86 architecture is a computer language instruction set executed by a microprocessor. It refers to a standard numbering abbreviation of an intel general-purpose computer series, and also identifies a set of general-purpose computer instructions.
  • registers include but are not limited to: program counter (PC), stack pointer (SP), base pointer (BP), general-purpose registers, and timers.
  • general-purpose registers include but are not limited to bp, si, di, etc.
  • the program counter in the x86 CPU, may also be called an instruction pointer (IP) or an instruction address register (IAR).
  • IP instruction pointer
  • IAR instruction address register
  • BP is generally used in the function to save the top base address of the SP stack when entering the function. It is usually used in conjunction with SP. It can be considered that BP records the stack bottom of the stack, and SP records the stack top of the stack. According to BP and SP, the inside of the stack can be determined. a range of data.
  • a schematic structural diagram of a coroutine switching apparatus includes: a clock module 700 , an interrupt processing module 701 , a timeout coroutine processing module 702 , and a scheduler module 703 .
  • the timeout coroutine processing module 702 specifically includes a coroutine saving module 7021 and a coroutine recovery module 7022 .
  • the clock module 700 is used for timing the running time of the current coroutine, and when the timing time reaches the set time, an interrupt signal is triggered.
  • the clock module may be a hardware timer, such as a CPU clock.
  • the interrupt processing module 701 stores an interrupt processing program, which is used to respond to an interrupt signal and execute interrupt processing.
  • the interrupt processing module 701 performs different processing according to the state of the thread where the timeout coroutine is located.
  • the interrupt processing includes saving the context of the time-out coroutine to the kernel shared space, and when the address is modified so that the thread where the time-out coroutine is located resumes execution, jumping to the coroutine saving module 7021 .
  • the coroutine saving module 7021 is configured to generate a recovery coroutine corresponding to the timeout coroutine, re-hang the recovery coroutine into the task queue, and jump to the scheduler module 703 .
  • the scheduler module 703 is configured to select a second coroutine in the task queue, the second coroutine is a new coroutine to be executed, and switch the second coroutine to the currently running coroutine.
  • the apparatus further includes a coroutine recovery module 7022, which is configured to start the execution of the coroutine recovery module 7022 when the scheduler reschedules the recovery coroutine corresponding to the overtime coroutine to recover the context when the overtime coroutine is interrupted.
  • a coroutine recovery module 7022 which is configured to start the execution of the coroutine recovery module 7022 when the scheduler reschedules the recovery coroutine corresponding to the overtime coroutine to recover the context when the overtime coroutine is interrupted.
  • the above method can forcibly switch the time-out coroutine when the time-out coroutine is identified, thereby realizing fair and stable operation between the coroutines.
  • the above-mentioned modules may be hardware modules or logical modules.
  • the above-mentioned modules may also be virtual modules, which are not limited in this embodiment of the present application.
  • the complete switching process of the time-out coroutine will be introduced through the apparatus shown in FIG. 7 .
  • the complete switching process may include an initialization process, a coroutine switching process and a coroutine recovery process.
  • the above-mentioned processes are respectively introduced as follows.
  • FIG. 8 a schematic diagram of a complete switching process of a timeout protocol provided by an embodiment of the present application, the process includes:
  • the first thread Before the first thread starts running (for example, when the first thread is created), the first thread is initialized, and the initialization includes but is not limited to the following operations:
  • each thread has a shared memory space corresponding to it, and all the coroutines of the thread share the shared memory space.
  • each coroutine in the same thread corresponds to different areas of the shared storage space, and each area can store the context of the coroutine.
  • the current thread includes coroutine A, coroutine B, and coroutine C, and the shared storage space can also be divided into coroutine A area, coroutine B area, and coroutine C area.
  • each coroutine in the same thread may share the same area of the shared storage space, and the same area may be used to store the context of the coroutine.
  • the first thread includes coroutine A, coroutine B, and coroutine C.
  • the running process of the first thread may be executing coroutine A, then switching to coroutine B, executing coroutine B, and finally switching To coroutine C, execute coroutine C.
  • the coroutine A is a timeout coroutine, in the process of switching the coroutine A, the context of the coroutine A may be stored in the shared storage space of the first thread.
  • the coroutine A When the coroutine A is switched and the coroutine B is executed, it is determined that the coroutine B is a timeout coroutine. At this time, the context of the coroutine A is stored in the shared storage space of the first thread, and the context of the coroutine B can be overwritten. The context of coroutine A.
  • the timing time of the clock module 700 is set, that is, the first threshold in the embodiment of the present application.
  • an interrupt signal is triggered.
  • the threads correspond to the clock modules one-to-one, that is, each thread has a one-to-one corresponding clock module.
  • the name of the clock module corresponding to the first thread is clock A
  • the name of the clock module corresponding to the second thread is clock B
  • the interrupt signal triggered by clock A is triggered when it is detected that the first thread is a timeout coroutine
  • the clock B triggers The interrupt signal is triggered when it detects that the second thread is a timeout coroutine.
  • some or all threads share a clock module.
  • the first thread and the second thread each correspond to one clock module.
  • the timeout coroutine processing module After the clock module triggers the interrupt signal, when responding to the interrupt signal, the timeout coroutine processing module also needs to determine for which thread the interrupt signal is triggered. Therefore, in the initialization process, the identifier (ID) of the to-be-executed coroutine can also be configured to the interrupt processing module 701, and after receiving the response signal, it is determined which coroutine is the timeout coroutine according to the identifier. For details, please refer to the introduction of 3) below.
  • the relevant information of the coroutine saving module 7021 is configured to the interrupt processing module 701 corresponding to the configuration clock module 700 .
  • the relevant information of the coroutine storage module 7021 includes but is not limited to: the code entry address (such as PC value) of the timeout coroutine storage module 702, and the stack address (eg, stack top SP value) corresponding to the timeout coroutine storage module 702.
  • the identifier (ID) of the first thread may also be configured to the interrupt processing module 701, and other information may also be configured, which is not limited in this application.
  • the identifier (ID) of the first thread can also be configured to the interrupt processing module 701, so as to reduce the thread identification time in response to the interrupt signal, or the interrupt processing module 701
  • the thread is identified according to the clock module that sends the interrupt signal, which is not limited in this embodiment of the present application.
  • the scheduler module 703 stores a task queue, and the task queue includes all the coroutines to be executed of the first thread. Assuming that the scheduler module 703 selects the first coroutine in the task queue as the coroutine to be executed, the scheduler module 703 records the information of the first coroutine, which mainly includes the location information of the coroutine control block of the first coroutine.
  • each coroutine has its own corresponding coroutine control block, for example, similar to the thread control block, the coroutine control block is used to record the information of the coroutine task, for example, the sp value of the coroutine task, It can also include information such as the stack size of the coroutine task, and the coroutine control block can be used to uniquely identify the coroutine, that is, to determine the currently running coroutine according to the coroutine control block.
  • the location information of the coroutine control block of the first coroutine may be an index value of the coroutine control block, the scheduler module 703 may find the coroutine control block according to the index value, and determine the first coroutine control block according to the index value. The currently running coroutine within the thread.
  • the scheduler module 703 starts to execute the first coroutine, and at the same time starts the clock module 700 to start timing. Exemplarily, when the first coroutine actively applies for scheduling, the clock module 700 is turned off.
  • the first coroutine is a timeout coroutine, and an interrupt signal is triggered.
  • the timing duration of the clock module 700 reaches the first threshold, it is determined that the first coroutine is a timeout coroutine, and an interrupt signal is triggered.
  • the interrupt processing module 701 when running the interrupt processing program, performs the following interrupt processing:
  • the context of the current coroutine is saved by different methods.
  • the state of the thread includes: the execution state, the ready state and the interrupted state.
  • Mode 1 when the thread where the first coroutine is located is in an interrupted state, the context when the first coroutine is interrupted is saved to the shared storage space.
  • the thread where the first coroutine is located is still in the running state, but because the running time of the first coroutine times out, it needs to switch to other coroutines of the first thread to run, so the thread is interrupted. It can be understood that the thread can still run, but the running time has not reached the time slice. For example, if the thread is still in its own time slice, but the running time of the first coroutine exceeds the first threshold, the first coroutine needs to be suspended. Switch to other coroutines of the thread. At this time, the state where the thread is suspended by the interrupt signal is the interrupt state.
  • the interrupt processing module 102 executes the first processing program, including:
  • the context information includes the values of registers such as PC and SP.
  • the interrupt handler is located in the kernel space, and the coroutine runs in the user space. When responding to the interrupt signal, the coroutine being executed in the user space will be forcibly interrupted, and the interrupt handler will be executed instead.
  • the shared storage space can also be located in the kernel space, and the size of the shared storage space can be dynamically adjusted or fixed, for example, to store the maximum memory required when the context information of the coroutine is interrupted.
  • each interrupt handler there is an instruction to interrupt and return to the previous program, such as iret (or iretd).
  • the interrupt return restores the context when the current coroutine was interrupted, so as to continue the interrupted execution.
  • the interrupt return address defaults to the code address when the current thread is interrupted
  • the interrupt return stack address defaults to the stack when the current thread was interrupted.
  • the interrupt return instruction is executed, the previously saved suspended thread is restored. context. For example, if the current thread is executing coroutine A when it is interrupted, when the interrupt returns, the context when coroutine A was interrupted is restored.
  • Mode 2 When the first thread is in the ready state, the context of the first thread recorded in the first thread control block is stored in the shared storage space.
  • the interrupt processing module 102 executes the second processing program, including:
  • the first thread may have been scheduled out of the execution state.
  • the CPU will record the context of the first thread when it is suspended.
  • the first thread control block when the first thread is scheduled again, the context recorded in the first thread control block is restored, and the first thread continues to be executed.
  • the register value of the first goroutine cannot be obtained from the register of the CPU, but the context information of the first goroutine is obtained from the thread control block of the first thread.
  • the context recorded in the first thread control block is modified to the context of the coroutine saving module 7021.
  • the modified first thread control block records context, jump to the coroutine storage module 7021, so as to execute the program stored in the coroutine storage module 7021, and realize subsequent coroutine switching.
  • the coroutine ie, the first coroutine that is being executed when the first thread is interrupted is queried.
  • the first coroutine is determined according to the information of the coroutine control block.
  • the context of the first coroutine is acquired from the shared storage space.
  • the context of the first coroutine is one or more register values, for example, including a PC value and an SP value. As shown in FIG. 8 , first, the acquired one or more register values are stored in the first space of the stack of the first coroutine according to the preset storage format, and then the context of the coroutine recovery module 7022 is saved to the stack in the second space, wherein the first space is adjacent to the second space.
  • the context when the first coroutine is interrupted includes the value of register A, the value of register B, and the value of register C.
  • the preset storage format may be to push the value of register A, the value of register B, and the value of register C into the stack in sequence.
  • the preset storage format may also be that the value of the register C, the value of the register B, and the value of the register A are sequentially pushed into the stack.
  • the context information is stored in a preset storage format, that is, according to the number of registers that may be included when the first coroutine is interrupted, it is stored in the stack according to a self-defined storage method, and then the coroutine restore module 7022 may sequentially read one or more register values of the coroutine in the stack according to the preset storage format, thereby restoring the context of the first thread.
  • the storage format of the context of the coroutine recovery module 7022 may be stored in accordance with the storage format in the prior art when the coroutine task actively applies for scheduling, or may be in other formats, which are not limited in the embodiments of the present application.
  • the recovery coroutine corresponding to the timeout coroutine is generated according to the updated data stack, and the recovery coroutine is re-suspended in the task queue, waiting for subsequent scheduling and execution.
  • the coroutine saving module 7021 also stores the address of the scheduler module 703 , and after the above process is executed, it is adjusted to the scheduler module 703 .
  • the scheduler module 703 selects a new coroutine (denoted as the second coroutine) in the task queue except the recovery coroutine according to the scheduling policy, records the information of the new coroutine, and starts to execute the new coroutine coroutines.
  • the coroutine with the highest priority may be selected among the coroutines to be executed, or the coroutine with the highest position may be selected in sequence by queuing, or a random coroutine may be selected.
  • a coroutine which is not limited in this embodiment of the present application.
  • a logical exception when responding to an interrupt signal, a logical exception may also be generated, and the interrupt processing module 701 may directly execute an interrupt return, and return to the interrupted thread to continue running.
  • the interrupt processing module 701 may directly execute an interrupt return, and return to the interrupted thread to continue running.
  • the first coroutine actively applies for scheduling, and the clock module 700 is turned off.
  • the switching process of the timeout coroutine is described above. It should be understood that the recovery coroutine corresponding to the timeout coroutine may also be scheduled. The following describes the process of scheduling and executing the recovery coroutine.
  • the stack data of the recovery coroutine includes the first space and the second space.
  • the second space of the second space reads out each register value of the coroutine recovery module 7022 in turn, writes each register value into the corresponding CPU register, and when the BP value is read, the stack bottom address of the second space is determined according to the BP value, Then read the PC value, the PC value is the code entry PC address of the coroutine recovery module 7022, write the PC value into the program counter of the CPU, and jump to the code segment of the coroutine recovery module 7022 to execute the coroutine recovery module 7022.
  • the coroutine recovery module 7022 sequentially reads one or more register values of the first coroutine from the first space of the stack according to the preset storage format, assuming that the value of register C and the value of register B are sequentially stored in the first space , the value of register A, the coroutine recovery module 7022 can determine, according to the preset storage format, the value of register A, the value of register B, and the value of register C that are sequentially read from the stack, and the read register The values of s are sequentially written into the corresponding CPU registers to restore the scene when the coroutine was interrupted.
  • the coroutine recovery module 7022 writes the SP value read from the first space into the SP register; determines the stack bottom of the first space according to the read BP value; writes the read PC value into the SP register A program counter, where the PC value is the code address when the first thread is interrupted when running the first coroutine, and jumps to the code address to resume the execution of the first coroutine.
  • the following describes the coroutine switching method of this embodiment through components related to the coroutine switching method provided by this embodiment.
  • FIG. 9 a schematic flowchart of a method for switching between coroutines provided in this embodiment can be applied to the device shown in FIG. 7 .
  • FIG. 9 when the thread where the timeout coroutine is located is in an interrupted state
  • the specific switching method is introduced, and the method includes the following steps:
  • Step 901 initialize the thread.
  • Step 902 Determine the first coroutine to be executed, and the scheduler module records the information of the first coroutine.
  • Step 903 the scheduler module starts and executes the coroutine, and simultaneously starts the clock module.
  • the timeout value of the clock module may be fixed or set before each turn-on.
  • step 901 to step 903 For the specific execution flow of step 901 to step 903, please refer to the above related description, which will not be repeated here.
  • Step 904 the clock module 700 times out and the first coroutine does not actively apply for scheduling, and sends an interrupt signal to the interrupt processing module 701 .
  • Step 905 in response to the interrupt signal, if the first thread is in an interrupted state, the interrupt processing module 701 saves the context when the first thread is interrupted to the shared storage space.
  • the interrupt processing module 701 may also control the clock module to turn off and clear the interrupt signal.
  • Step 906 the interrupt processing module 701 modifies the relevant information returned by the interrupt to the relevant information corresponding to the coroutine storage module 7021 .
  • Step 907 the interrupt processing module 701 performs an interrupt return, restores the context of the coroutine storage module 7021 , and jumps to the coroutine storage module 7021 .
  • step 908 the coroutine saving module 7021 determines, according to the information of the coroutine control block, which is running when the first thread is interrupted.
  • the scheduler module records the position information of the coroutine control block of the coroutine being executed by the first thread, and the position information of the coroutine control block is indexed to the coroutine control block, so that according to the coroutine control block Determines the coroutine that was running before the first thread was interrupted, in this case the first coroutine.
  • Step 909 the coroutine saving module 7021 obtains the context of the first coroutine from the shared storage space.
  • Step 910 The timeout coroutine processing module 702 saves the context acquired from the shared storage space to the stack corresponding to the first coroutine according to the preset storage format.
  • Step 911 the timeout coroutine processing module 702 saves the context sequence of the coroutine restoration module 7022 into the stack of the first coroutine.
  • Step 912 The timeout coroutine processing module 702 generates a recovery coroutine corresponding to the first coroutine, and adds the recovery coroutine to the task queue.
  • Step 913 Restore the context of the scheduler module and jump to the scheduler module.
  • Step 914 The scheduler module selects a new coroutine in the task queue, and starts executing the new coroutine.
  • the interrupt processing module 701 responds to the interrupt signal, and if the first thread has been scheduled out of the running state, for example, when the first thread is in the ready state, the interrupt processing module 701 executes the second process described above
  • the program is to save the register context information saved in the thread control block of the first thread to the shared storage space corresponding to the first thread.
  • the interrupt processing module 701 modifies the PC address recorded in the thread control block to the entry PC address of the coroutine storage module 7021 , and modifies the SP address recorded in the thread control block to the stack top SP address of the coroutine storage module 7021 .
  • the interrupt processing module 701 executes an interrupt return and returns to the suspended thread.
  • the time-out coroutine when a time-out coroutine is identified, the time-out coroutine can be forcibly switched and switched to the second coroutine to run, so as to avoid a coroutine running for too long and other coroutines not getting the chance to execute the coroutine. Fair and stable operation between the two, and improve system performance.
  • the priority of interrupt processing is high, when the first coroutine is a timeout coroutine, the first coroutine can be forcibly interrupted, thereby switching to another coroutine. Further, the interrupted context of the first coroutine is saved, so that when the first coroutine is rescheduled, the current context can be restored to continue running the coroutine.
  • the embodiments of the present application further provide a device for executing the methods performed in the foregoing method embodiments.
  • the device includes a determination unit 1001 and a processing unit 1002 .
  • Determining unit 1001 configured to determine that the first coroutine is a timeout coroutine, and the timeout coroutine is a coroutine whose running duration reaches a first threshold;
  • the processing unit 1002 is configured to interrupt the first coroutine and switch the second coroutine as the currently executing coroutine.
  • the device of this embodiment may be implemented by an application-specific integrated circuit (ASIC), or a programmable logic device (programmable logic device, PLD), and the above-mentioned PLD may be a complex program logic device (complex program logic device).
  • programmable logical device, CPLD field-programmable gate array
  • FPGA field-programmable gate array
  • GAL general array logic
  • the determining unit 1001 is specifically configured to start timing when the first coroutine is started; when the running duration of the first coroutine reaches a first threshold, determine the first coroutine A coroutine is a timeout coroutine.
  • the processing unit 1002 is specifically configured to select the second coroutine, where the second coroutine is a coroutine adjacent to the first coroutine in the task queue; The second coroutine is the currently executing coroutine.
  • the second coroutine is a randomly selected coroutine from the to-be-executed coroutines included in the first thread; or the second coroutine is a coroutine that the first thread includes The coroutine with the highest priority among the coroutines to be executed; or, the second coroutine is the coroutine with the highest ranking at the current moment among the coroutines to be executed included in the first thread.
  • the processing unit 1002 is specifically configured to trigger interrupt processing, and the interrupt processing includes: saving the context when the first coroutine is interrupted according to the thread state where the first coroutine is located, The context is used to indicate running information when the first thread is interrupted.
  • the processing unit 1002 is specifically configured to save the register value of the first thread to the kernel shared space when the first thread where the first coroutine is located is in an interrupted state
  • the kernel shared space is a kernel storage space corresponding to the first thread
  • the register value is used to record the running information of the first thread.
  • the processing unit 1002 is further configured to modify the context returned from the interrupt to the context of the coroutine handler; execute the interrupt return, and run the coroutine handler; wherein, run the coroutine
  • the process handler is used for generating a recovery coroutine corresponding to the first coroutine at the application layer, and executing the recovery coroutine is used to recover the scene when the first coroutine is interrupted.
  • the processing unit 1002 is specifically configured to: when the first thread where the first coroutine is located is in a waiting state, store the first thread stored in the first thread control block The context of a thread is saved in a kernel shared space, where the kernel shared space is a kernel storage space corresponding to the first thread, and the register value is used to record the running information of the first thread.
  • the processing unit 1002 is further configured to: modify the context stored in the first thread control block to the context of the coroutine handler, so that the first thread is scheduled again , restore the context of the coroutine handler, and run the coroutine handler; wherein, running the coroutine handler is used to generate a recovery coroutine corresponding to the first coroutine at the application layer, and execute the coroutine handler.
  • the resume coroutine is used to resume the scene when the first coroutine is interrupted.
  • the processing unit 1002 is specifically configured to: obtain the register value of the first thread from the kernel shared space, and save the register value of the first coroutine according to a preset format to the data structure corresponding to the first coroutine; the preset format is used to indicate the storage order of the register values of the first coroutine; according to the saved data structure, the first coroutine is generated Corresponding to the above recovery coroutine.
  • the processing unit 1002 is further configured to run the recovery coroutine: read the register of the first coroutine from the data structure corresponding to the first coroutine according to a preset format value, write the register value into the corresponding register.
  • the processing unit 1002 is further configured to save the context of the coroutine restoration program into the data structure; when the processing unit runs the restoration coroutine, it is further configured to retrieve the context of the coroutine restoration program from the data structure. Read the context of the coroutine restoration program in the data structure, and run the coroutine restoration program, wherein running the coroutine restoration program is used to read from the data structure corresponding to the first coroutine according to a preset format Get the register value of the first goroutine, and write the register value into the corresponding register.
  • the apparatus according to the embodiments of the present application may correspond to executing the methods described in the embodiments of the present application, and the above-mentioned and other operations and/or functions of the respective units in the apparatus are to implement the corresponding methods of the respective methods in FIG. 8 to FIG. 9 , respectively.
  • the process, for the sake of brevity, will not be repeated here.
  • the present application provides a device 1100.
  • the device 1100 can be applied to one of the network devices in the scenario shown in FIG. 4, and executes the method shown in FIG. 8 or FIG. Execute the steps performed by the principal.
  • Device 1100 may include processor 1101 and memory 1102 . Further, the apparatus may further include a communication interface 1104, which may be a transceiver, or the communication interface may be a network card. Further, the device 1100 may further include a bus system 1103 .
  • the processor 1101, the memory 1102 and the communication interface 1104 can be connected through the bus system 1103, the memory 1102 can be used to store instructions, and the processor 1101 can be used to execute the instructions stored in the memory 1102 to control the communication interface 1104 to receive or send signals, Complete the steps of executing the main body in the method shown in FIG. 8 or FIG. 9 above.
  • the memory 1102 may be integrated in the processor 1101 , or may be a physical entity different from the processor 1101 .
  • processor 1101 can be a CPU, and the processor 1101 can also be other general-purpose processors, digital signal processors (digital signal processing, DSPDSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) Or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general purpose processor may be a microprocessor or any conventional processor or the like.
  • the memory 1102 may include read only memory and random access memory, and provides instructions and data to the processor 1101 .
  • Memory 1102 may also include non-volatile random access memory.
  • the memory 1102 may also store information of device type.
  • the memory 1102 may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically programmable Erase programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • Volatile memory may be random access memory (RAM), which acts as an external cache.
  • RAM random access memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • Double data rate synchronous dynamic random access memory double data date SDRAM, DDR SDRAM
  • enhanced synchronous dynamic random access memory enhanced SDRAM, ESDRAM
  • synchronous link dynamic random access memory direct rambus RAM, DR RAM
  • bus 1103 may also include a power bus, a control bus, a status signal bus, and the like. However, for the sake of clarity, the various buses are labeled as bus 1103 in the figure.
  • the function of the communication interface 1104 can be considered to be implemented by a transceiver circuit or a dedicated chip for transceiver.
  • the processor 1101 can be considered to be implemented by a dedicated processing chip, a processing circuit, a processor or a general-purpose chip.
  • a computer manner may be considered to implement the first computing node or the function of the first computing node provided by the embodiments of the present application.
  • Program codes that will implement the functions of the processor 1101 and the communication interface 1104 are stored in the memory 1102, and a general-purpose processor can implement the functions of the processor 1101 and the communication interface 1104 by executing the codes in the memory.
  • the device 1100 may be used to execute the steps of the execution body in the above-mentioned process shown in FIG. 8 or FIG. 9 .
  • the communication interface 1104 can receive and detect the first data packet; the processor 1101 can respond to the first data packet detected by the communication interface 1104, and there is no space to record the first data packet in the first data structure When it belongs to the information of the first data stream, determine whether there is a second data stream whose information has not been updated for more than a preset time in the data stream recorded in the first data structure and having the same hash value as the first data stream; If so, replace the information of the second data stream with the information of the first data stream.
  • the device 1100 according to the embodiment of the present application may correspond to the device in FIG. 10 in the embodiment of the present application, and may correspond to the corresponding subject in executing the method 100 according to the embodiment of the present application, and each module in the device 1100
  • the above and other operations and/or functions are respectively to implement the corresponding processes of the respective methods in FIG. 8 to FIG. 9 , and are not repeated here for brevity.
  • the above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination.
  • the above-described embodiments may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated.
  • the computer may be a general purpose computer, special purpose computer, computer network, or other programmable device.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be downloaded from a website site, computer, server, or data center Transmission to another website site, computer, server, or data center is by wire (eg, coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, a data center, or the like that contains one or more sets of available media.
  • the usable media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, DVDs), or semiconductor media.
  • the semiconductor medium may be a solid state drive (SSD).

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Abstract

一种协程切换的方法、装置及设备，包括：识别到超时协程，例如，在当前运行的第一协程启动时开始计时，当计时时间达到第一阈值时，触发中断信号，响应于该中断信号切换至第二协程为当前运行协程。上述方法能够在识别到超时协程时，强行切换该超时协程，切换至第二协程运行，避免某一协程运行时长过长，其他协程得不到执行机会，实现协程之间的公平、稳定运行，提升系统性能。

Description

一种协程切换的方法、装置及设备 技术领域
本申请涉及计算机技术领域，尤其涉及一种协程切换的方法、装置及设备。
背景技术
操作系统支持多线程模式运行，为了提升业务性能，可能会在一个业务进程中设置大量的并发线程。多个并发线程通过时间片内以轮询的调度方式依次执行。一个线程又包含一个或多个协程任务，在该线程所属的时间片内，线程包含的多个协程任务依次交替执行。协程任务用于执行包括子函数的函数群，每个协程任务可以用于执行一个或多个子函数。由于当前协程任务处理的方式是顺序执行，不同协程任务和同一协程任务的不同子函数均需按照顺序完成，也就是说，对于同一协程任务而言，只有当前一个子函数完成执行，才会继续下一个子函数的执行过程，当某个子函数因为网络等原因导致执行时间过程时，该协程任务的执行时间会过长，其他协程任务或同一协程任务的子函数无法执行，影响整个系统中线程调度处理的性能。
发明内容
本申请提供一种协程切换方法及装置，用于实现协程任务之间的公平切换，提高系统运行稳定性。
第一方面，本申请提供一种协程切换方法，该方法包括：确定第一协程为超时协程，所述超时协程为运行时长达到第一阈值的协程；中断所述第一协程；切换第二协程作为当前执行协程。
通过上述设计，能够在识别到超时协程时，强行切换该超时协程，切换至第二协程运行，避免某一协程运行时长过长，其他协程得不到执行机会，实现协程之间的公平、稳定运行，提升系统性能。
在一种可能的实现方法中，所述确定第一协程为超时协程，包括：在所述第一协程启动时开始计时；当所述第一协程的运行时长达到第一阈值时，确定所述第一协程为超时协程。
通过上述设计，在启动协程时，开启计时，计时时间达到第一阈值时，确定该协程的超时协程，保证每个协程的运行时间达到第一阈值时可以被切换，保证协程之间的公平运行。
在一种可能的实现方法中，所述切换第二协程作为当前执行协程，包括：选择所述第二协程，所述第二协程为任务队列中与所述第一协程相邻的协程；将所述第二协程作为当前执行协程。
通过上述设计，确定第一协程为超时协程，则切换至第二协程，避免第一协程运行时长过长，给予除第一协程之外的其他协程运行机会，保证协程之间的公平切换。
在一种可能的实现方法中，所述选择所述第二协程，包括以下方式中任意一种：所述第二协程为所述第一线程包含的待执行的协程中随机选择的一个协程；或者，所述第二协程为所述第一线程包含的待执行的协程中优先级最高的协程；或者，所述第二协程为所述第一线 程包含的待执行的协程中当前时刻排序最前的协程。
在一种可能的实现方法中，所述中断所述第一协程，包括：触发中断处理，所述中断处理包括：根据所述第一协程所在的线程状态保存第一协程被中断时的上下文，所述上下文用于指示所述第一线程被中断时的运行信息。
通过上述设计，由于中断处理的优先级较高，因此在第一协程为超时协程时，可以强制将第一协程中断，从而切换至其他协程。进一步，保存第一协程被中断的上下文，使得再次调度第一协程时能够恢复当前的上下文继续运行该协程。
在一种可能的实现方法中，所述根据所述第一协程的状态保存第一线程被中断时的上下文，包括：当所述第一协程所在的第一线程为中断状态，则将所述第一线程的寄存器值保存至内核共享空间，所述内核共享空间为所述第一线程对应的内核存储空间，所述寄存器值用于记录所述第一线程的所述运行信息。
在一种可能的实现方法中，该方法还包括：将中断返回的上下文修改为协程处理程序的上下文；执行中断返回，运行所述协程处理程序；其中，运行所述协程处理程序用于在应用层生成所述第一协程对应的恢复协程，执行所述恢复协程用于恢复所述第一协程被中断时的现场。
通过上述设计，通过修改中断返回地址，使得执行中断返回时直接跳转至应用层的协程处理程序，执行协程处理程序可以生成第一协程对应的恢复协程，当调度器再次调度恢复协程时，能够恢复第一协程被中断时的上下文运行，无须使CPU切换至内核态对应的运行权限级别。
在一种可能的实现方法中，所述根据所述第一协程的状态保存第一线程被中断时的上下文，包括：当所述第一协程所在的第一线程为等待状态，则将所述第一线程控制块内存储的所述第一线程的上下文保存至内核共享空间，所述内核共享空间为所述第一线程对应的内核存储空间，所述寄存器值用于记录所述第一线程的所述运行信息。
通过上述设计，若第一协程为等待状态，则将第一线程控制块内的上下文存储至内核共享空间，并且将线程控制块的上下文修改为协程处理程序的上下文，以使第一线程再次被调度时，根据第一线程的线程控制块内存储的上下文恢复协程处理程序的上下文运行，生成第一线程对应的恢复协程，当调度器再次调度恢复协程时，能够恢复第一协程被中断时的上下文运行，无须使CPU切换至内核态对应的运行权限级别。
在一种可能的实现方法中，该方法还包括：将所述第一线程控制块内存储的上下文修改为协程处理程序的上下文，以便在所述第一线程再次被调度时，恢复所述协程处理程序的上下文，运行所述协程处理程序；其中，运行所述协程处理程序用于在应用层生成所述第一协程对应的恢复协程，执行所述恢复协程用于恢复所述第一协程被中断时的现场。
在一种可能的实现方法中，运行所述协程处理程序，包括：从所述内核共享空间获取所述第一线程的寄存器值，并按照预设格式将所述第一协程的寄存器值保存至所述第一协程对应的数据结构；所述预设格式用于指示所述第一协程的寄存器值的保存顺序；根据进行保存后的所述数据结构，生成所述第一协程对应的上述恢复协程。
在一种可能的实现方法中，该方法还包括：运行所述恢复协程：按照预设格式从所述第一协程对应的数据结构读取所述第一协程的寄存器值，将所述寄存器值写入对应的寄存器。
在一种可能的实现方法中，按照预设格式将所述第一协程的寄存器值保存至所述第一协程对应的数据结构之后，生成所述第一协程对应的上述恢复协程之前，还包括：将协程恢复程序的上下文保存至所述数据结构中；运行所述恢复协程，还包括：从所述数据结构中读取 所述协程恢复程序的上下文，运行所述协程恢复程序，其中，运行所述协程恢复程序用于按照预设格式从所述第一协程对应的数据结构读取所述第一协程的寄存器值，将所述寄存器值写入对应的寄存器。
第二方面，本申请实施例还提供了一种设备，该设备包括多个功能单元，这些功能单元可以执行第一方面的方法中各个步骤所执行的功能。这些功能单元可以通过硬件实现，也可以通过软件实现。在一个可能的设计中，该设备包括侦测单元以及处理单元。关于该设备实现的有益效果，请参考第一方面的描述，在此不再赘述。
第三方面，本申请实施例还提供了一种设备，该设备包括处理器和存储器，所述存储器中存储有程序指令，所述处理器运行所述存储器中的程序指令以实现第一方面所提供的方法。关于该设备实现的有益效果，请参考第一方面的描述，在此不再赘述。
第四方面，本申请还提供一种计算机可读存储介质，计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述第一方面所提供的方法。
第五方面，本申请还提供一种计算机芯片，芯片与存储器相连，芯片用于读取并执行存储器中存储的软件程序，执行上述第一方面所提供的方法。
附图说明
图1为本实施例提供的一种多线程并发执行的场景示意图；
图2为本实施例提供的一种线程主动申请切换的场景示意图；
图3为本实施例提供的一种线程与协程的关系示意图；
图4为本实施例提供的一种可能的网络系统的架构示意图；
图5为本实施例提供的一种CPU工作流程示意图；
图6为本实施例提供的一种堆栈操作的场景示意图；
图7为本实施例提供的一种协程切换装置的结构示意图；
图8为本实施例提供的一种协程切换的流程示意图；
图9为本实施例提供的一种协程切换方法所对应的流程示意图；
图10为本实施例提供的一种协程切换设备的结构示意图；
图11为本实施例提供的一种协程切换设备的结构示意图。
具体实施方式
为了使本申请更容易被理解，下面首先对本申请实施例涉及的一些基本概念进行解释。需要说明的是，这些解释是为了便于本领域技术人员理解，并不是对本申请所要求的保护范围构成限定。
1，进程，可以是指具有一定独立功能的程序的一次运行活动，是应用程序运行的载体，也可以理解为，进程为应用程序的运行实例，是应用程序的一次动态执行。例如，当用户运行记事本程序(Notepad)时，该用户就创建了一个用来容纳组成Notepad.exe的代码及其所需调用动态链接库的进程。进程是系统进行资源分配和调度的一个独立单位，每一个进程都有自己的内存空间，不同的进程之间相互独立。
2，线程，包含于进程，在进程中创建，可以共享进程的资源，一个进程包含至少一个线程，线程是系统分配处理器时间资源的基本单元，或者说线程是进程之内独立执行的一个单元。线程具有并发性，即单个进程内支持执行多个并发线程，各个线程之间共享进程的内存 空间，每条线程并发执行不同的任务。比如，一个线程可以用于向磁盘写入文件，另一个线程可以用于接收用户的按键操作并及时做出反应，线程之间互相不干扰。
参见图1，为线程并发执行的示意图，如图所示，每个线程依次运行固定时长，每个线程轮流执行，由于中央处理器(central processing unit，CPU)的执行效率非常高，因此可以做到时间片非常短，CPU可以在各个线程之间快速地切换，呈现出一种多个任务在同时进行的效果，这也就是所谓的线程的并发性。其中，线程执行的那段时间(固定时长)可以称为时间片，线程正在执行的状态记为运行状态；时间片用尽，线程会被调度出运行状态，也可以理解为线程被暂停，等待下一个属于该线程的时间片的到来，此时线程的状态可以记为就绪状态(或者等待状态)。示例性地，在一种可能的场景中，在线程运行的时间片内，还可能被优先级更高的任务临时中断，待该优选级更高的任务执行完毕后，再次恢复线程被中断时的状态继续运行，直到时间片用户，线程被中断时的状态可以记为中断状态。
3，协程，可以是指轻量化线程，线程是协程的载体，多个协程可以共享一个线程，不同的协程也具有不同的独立的上下文环境，包括代码段和堆栈，通过协程框架在线程中依次被执行。类似的，协程的上下文主要包括寄存器值。
为了更好的理解本申请技术方案，接下来对线程和协程的调度方式进行介绍。
线程由操作系统负责调度和管理，目前，大部分操作系统对线程进行调度包括两种触发方式：时间片轮转的抢占式调度方式和线程主动申请调度的方式。
其中，时间片轮转的调度方式，是指线程运行时间达到预定时间而被操作系统强制切换。线程主动申请调度的方式，是指线程主动通知操作系统进行切换，由操作系统确定切换至新的线程。下面以线程主动申请调度为例，对线程的切换流程进行介绍，请参考图2，为线程主动请求调度的流程示意图，假设用户程序A为当前正在执行的线程，用户程序A可以主动申请调度，通知操作系统内核放弃当前的CPU资源(例如，寄存器和内存资源)，申请使用操作系统提供服务程序以完成线程切换工作，同时操作系统控制CPU从用户态对应的运行权限切换至内核态对应的运行权限，执行中断处理，暂停用户程序A，其中，中断处理包括例如：将当前用户程序A(即用户程序A的某一线程)的上下文(上下文包括寄存器值，用于指示线程被暂停时的运行信息)保存至内存中(例如线程控制块中)，然后，从任务队列中选择下一个待执行的线程，例如应用程序B，从内存中恢复线程B的上下文，控制CPU从内核态对应的运行权限再次切换回用户态对应的运行权限，执行应用程序B。
所谓的用户态和内核态是指操作系统的运行状态。目前，计算机系统中一般实行分级保护，即根据计算机系统中受影响的严重程度而区分某些操作必须由某些具有相应权限的角色来执行，例如直接访问硬件和修改硬件工作模式等操作需要最高权限来执行。
计算机的这种保护需要CPU和操作系统共同配合完成，现代CPU一般会提供多种运行权限级别，操作系统一般也分为多个运行状态以与CPU配合，操作系统常见的状态是用户态和内核态，其中内核态一般拥有最高权限，所有指令和操作都被CPU允许执行；而用户态一般都是较低权限，在此状态下软件程序只能执行有限的指令和操作，高危操作不被CPU硬件允许，例如配置CPU内部控制寄存器、访问内核部分的内存地址等。操作系统需要执行处于不同权限下的程序时，通常会先将CPU的权限状态切换到对应状态，再执行对应的程序。
下面对协程的调度方式进行介绍。参见图3为线程与协程的关系示意图，如图所示，示例性地，一个协程可以看作一个函数群，由若干子函数构成一个相对独立的任务，协程任务内的函数之间为调用关系，协程任务之间的也是函数的跳转调用关系，但下一个任务的调用地址不由当前协程任务指定，而是由调度器来选择确定，调度器可以看成是一个特殊的任务， 调度器将一直存在而不会退出，当前协程任务运行完成之后，将自动跳转到调度器的上下文运行，调度器在当前等待运行的协程任务中选择合适的协程任务并跳转到该协程任务的上下文中运行。在一种可实施的方式中，每个协程任务的元数据中可以包括协程控制块，协程控制块用于标识协程任务，并记录该协程任务的上下文(例如相关寄存器值)，调度器从该协程任务的元数据中获取该协程任务的上下文。
触发上述调度器进行协程切换的条件包括协程主动申请调度，以及为了防止某一协程占用较长时间，目前，现有技术中还提供了一种超时检测的协程切换方式。例如：在协程的子函数的调用入口设置超时检测，每次进行函数调用时，会计算当前协程的总运行时间，若总运行时间超过设定时间，则主动调用协程切换接口进行协程切换。
然而，如果线程不进行子函数调用，例如，恶意循环执行某一子函数，或者在子函数中执行时间过长，这种情况下其他协程任务便得不到执行机会，还可能因此得不到执行机会而被饿死，影响其他协程的正常、稳定运行。
鉴于此，为了提升整个系统的处理性能，本申请提出一种协程任务超时切换方法，具体利用确定当前正在执行的协程是否为超时协程，超时协程是指运行时长达到第一阈值的协程，强制中断第一协程，切断第二协程为当前执行协程。
接下来，结合附图详细介绍本申请提供的协程任务切换方法。图4为本申请实施例提供的一种网络系统的架构示意图，该方法应用于该系统，如图所示，该网络系统包括服务器，网络设备和存储设备。其中，服务器可以存储器可以通过网络设备通信，示例性地，网络设备包括但不限于：交换机、路由器等设备间网络连接的设备。
服务器、存储设备可以包括处理器、内存、存储器以及网络适配器，下面以对部分组件的功能进行介绍。
一、存储器
存储器，可以主要包括存储程序区和存储数据区。其中，存储程序区可存储操作系统、各种应用程序(比如相机应用)等；存储数据区可存储根据使用该应用程序所创建的数据(比如相机应用采集的图像、视频)等。
存储器包括内存储器(又称内存，也可以称为主存(main memory))和外存储器。外存储器包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他易失性固态存储器件，具有容量大，速度慢，断电后数据不会丢失等特点，用于长期或永久存放程序和数据。
内存可以包括寄存器、高速随机存取存储器，具有容量小、速度快、掉电易失等特点，用于存放当前正在执行的数据和程序。可以理解为，内存是CPU和外存储器之间的通道，可以用于首先将外存储器存储的程序以及数据读入内存中，然后内存中的程序会被一条一条的读到处理器中被执行。一般的，寄存器也可以集成于处理器内，作为处理器的一部分，下文将会进行详细介绍。
二、处理器
处理器，可以是中央处理器(central processing unit，CPU)，或者是特定集成电路(application specific integrated circuit，ASIC)，或者是现场可编程门阵列(field programmable gate array，FPGA)。
下面以CPU为例对处理器进行描述。示例性地，CPU主要由运算单元、控制单元、存储单元和总线组成，其中，运算单元、控制单元和存储单元通过总线互相连接。
其中，控制单元，用于对程序指令进行解析，产生控制指令。具体的，控制单元包括程序寄存器(program counter，PC)、指令寄存器(instruction register，IR)、指令译码器(instruction  decoder，ID)和操作控制单元(operation controller，OC)等。程序寄存器PC用于存储待读取的指令的地址，控制单元基于预先编制好的程序，根据程序寄存器PC值获取对应地址的指令，放在指令寄存器IR中。指令的操作码被送到指令译码器ID中译码，操作控制单元OC，根据指令译码器ID对于指令操作码的译码，产生出实现指令功能所需要的全部动作的控制指令，并按确定的控制指令的执行时序，向相应的部件发送控制指令，控制指令用于指示需要进行的操作。在当前指令执行完成后，计算下条指令的地址，并送入程序计数器PC。
运算单元，用于响应控制单元发出的控制指令，执行相应的运算操作，例如各种算术运算和/或逻辑运算。
存储单元，包括寄存器组，寄存器具有存储信息少，存取速度快等特点，通常用于CPU暂时存放数据，例如等待处理的数据，或已经处理过的数据。由于寄存器的存取速度快，因此，CPU访问寄存器所用的时间要比访问内存的时间短。采用寄存器，可以有效减少CPU访问内存的次数，提高CPU的工作速度。其中，寄存器组包括专用寄存器和通用寄存器。
具体的，处理器用于执行操作系统与应用程序。本申请实施例中，操作系统和应用程序可以在同一个CPU上执行，也可以在不同的CPU上执行，例如，计算机为多核处理器时，使用单独一个处理器可以用于执行操作系统，使用另一个处理器来运行应用程序。
参见图5，为CPU工作流程示意图。进程可以是指操作系统中正在运行的一个应用程序，如图所示，在运行一个进程时，操作系统为该进程分配CPU、内存等资源，其中，内存用于存储该进程的代码(例如图中的代码段)和数据(例如图中的数据段)。应理解，数据段包含完成代码段的指令所需的数据。
CPU的程序计数器用于记录进行中的代码地址(图中的指令地址)，示例性地，代码地址可以是代码段的段号和/或行号等。指令寄存器用于实现程序计数器的功能，具体用于记录的指令地址对应的指令。示例性地控制单元根据程序计数器的指令地址，读取内存中该指令地址对应的指令，存放至指令寄存器。
随后，控制单元对该指令进行译码，根据操作码确定出成该指令所需的操作对应的控制指令，并发送给对应的单元，例如存储单元和/或运算单元。应理解的是，每一条指令都有一个操作码，标识该指令应进行什么性质的操作。简而言之，即指示CPU需要做什么样的操作。
示例性地，控制单元向存储单元发出控制指令1，向运算单元发出控制指令2。其中，控制指令1包含操作指示和操作数地址，例如，控制指令1用于指示存储单元从内存中读操作数地址的数据，存储单元读取该数据后可以暂时存放至相应的寄存器中，用于运算单元根据该寄存器中的数据进行运算。控制指令2用于指示运算单元从存储单元获取数据进行运算。示例性地，内存中的数据存储区内的数据结构可以是堆栈，存储单元还可以包含堆栈指针(SP)，用来保存当前运行的应用程序在堆栈中数据的地址信息，存储单元根据该堆栈指针记录的地址信心，在内存中获取该地址信息对应的堆栈中的数据。
其中，堆栈是一种数据项按序排列的数据结构，由一个一个的栈帧组成，每一个栈帧可对应一次函数调用，栈帧中可以包含函数的参数值、局部变量(包括寄存器值)和一些临时数据等。数据存储至栈的方式只能在栈的一端(称为栈顶(top))对数据项进行插入和删除。可以利用指针或其他形式指示当前时刻栈顶的位置，当有新数据需要存储时，即将该数据或该数据的信息存储至栈顶位置，此时，指示栈顶的指针可以指向新的栈顶的位置。应理解的是，堆栈的存储方式是一种逻辑结构，可以简单将堆栈理解为一端是固定，另一端浮动的数据结构，堆栈内所有的数据存入或取出，只能在浮动的一端(称栈顶)进行，数据的存储和读取的方式可以按照“先进后出”的原则处理。参见图6，为定义的一些堆栈操作的示意图，存 入堆栈的操作(即插入)称为入栈(PUSH)，从堆栈取出的操作称为出栈(POP)。如图所示，入栈操作包括：堆栈指针(stack pointer，SP)初始指示存储si的位置，当有新的数据bp存入堆栈时，指针加1，此时，指针指向存储bp的位置。出栈操作(即删除)过程与入栈操作过程相反，出栈则先确定当前栈顶所在位置，然后，将指针所指示的内部存储器(例如，ram单元)中的内容送入目的位置(例如，直接地址寻址的单元)，然后再将堆栈指针(SP)减1。
可选地，堆栈存储或读取数据的方式还可以采用“先进后出”的原则，具体实施时可以根据业务需求设置。
上述为执行一条指令的流程示意图，当执行完一条指令后，程序计数器+1，即指向下一条指令，通过上述流程继续执行下一条指令。
总而言之，CPU的工作流程包括：从内存中依次读取各条指令和相应的数据，按照指令操作码的规定，对数据进行运算处理，直到程序执行完毕。
示例性地，操作系统还可以控制CPU读取指定堆栈地址内存储的数据，例如，PC值，并将获取的PC值填入PC寄存器中，CPU读取并执行该PC寄存器值对应的程序指令，以此实现程序的切换。本申请实施例中，操作系统和应用程序可以在同一个CPU上执行，也可以在不同的CPU上执行，例如，计算机为多核处理器时，使用单独一个处理器可以用于执行操作系统，使用另一个处理器来运行业务，例如应用程序(包括进程、线程和协程)，本申请实施例对此不作限定，但需要注意的是，执行本申请实施例的处理器为运行业务的处理器。
示例性地，协程任务队列中存储有待执行的协程任务控制块，协程任务控制块内记录着该协程上一次执行后的上下文，该上下文包括寄存器值，例如当前PC值、SP值等，当切换到一个协程任务时，CPU根据该协程的协程任务控制块恢复该协程的上下文，例如，将协程任务控制块记录的PC值写入PC寄存器，将SP值写入堆栈指针，从该协程上一次运行停止的位置继续执行。应理解，上述仅为举例，实际上协程的上下文可能还包括寄存器值，本申请实施例对此不作限定。
三、网络适配器，是指带有通信接口的器件或设备，也可以称为网卡，用于实现设备之间的连接，例如，服务器可以通过网络适配器实现与存储设备的连接。
需要说明的是，图4所示的网络系统仅为举例，该网络系统中还可以包括更多或者更少的网络设备，例如，还可以包括计算服务器(图4中未示出)。该网络系统中的每一网络设备还可以包括更多或者更少的部件。另外，本申请对该网络系统中包括的服务器、网关设备和存储服务器等网络设备的数量不做限定。
本申请实施例提供的协程切换方法，可以部署于图4所示的网络系统中，具体的，可以部署在该网络系统中的其中一个设备中，例如：服务器、网络设备或存储设备中。
本申请实施例对于部署的设备中处理器的形态不做限定，例如，可以为CPU、FPGA等，其中，CPU可以采用ARM或X86架构，本申请实施例对此不作限定。其中，ARM是一种32位精简指令集(RISC)处理器架构，适用于移动通讯领域的设备，例如可携式装置(移动电话、多媒体播放器、掌上型电子游戏和计算机)，电脑外设(硬盘、桌上型路由器)等。X86架构是微处理器执行的计算机语言指令集，指一个intel通用计算机系列的标准编号缩写，也标识一套通用的计算机指令集合。
应理解，在不同的架构下，CPU内的寄存器的种类、数量、名称可能完全不同，或不完全相同。例如，在X86CPU中，寄存器包括但不限于：程序计数器(PC)、堆栈指针(SP)、基数指针(BP)、通用寄存器、定时器。在X86CPU中，通用寄存器包括但不限于bp、si、di等。其中，程序计数器，在x86CPU中，也可以称为指令指针(instruction pointer，IP)， 或称为指令地址寄存器(instruction address register，IAR)。BP，一般在函数中用来保存进入函数时的SP的栈顶基址，通常与SP联合使用，可以认为BP记录堆栈的栈底，SP记录堆栈的栈顶，根据BP和SP可以确定堆栈内的一段范围的数据。
下文为方便描述，以X86架构的CPU为例，对本申请实施例提供的技术方案进行具体描述。
参见图7，为本申请实施例提供的一种协程切换装置的结构示意图，该装置包括：时钟模块700、中断处理模块701、超时协程处理模块702和调度器模块703。其中，超时协程处理模块702具体包括协程保存模块7021、协程恢复模块7022。
时钟模块700，用于对当前协程的运行时间进行计时，当计时时间达到设定时间时，触发中断信号。示例性地，时钟模块可以为一个硬件定时器，例如CPU时钟。
中断处理模块701，存储有中断处理程序，用于响应中断信号，执行中断处理。示例性地，中断处理模块701根据超时协程所在线程的状态，执行不同的处理。示例性地，中断处理包括将超时协程的上下文保存至内核共享空间，修改地址使超时协程所在的线程恢复执行时，跳转至协程保存模块7021。
协程保存模块7021，用于生成超时协程对应的恢复协程，将恢复协程重新挂入任务队列中，并跳转至调度器模块703。
调度器模块703，用于在任务队列中选择一个第二协程，第二协程为新的待执行的协程，并将第二协程切换为当前运行的协程。
该装置还包括协程恢复模块7022，协程恢复模块7022用于在调度器再次调度超时协程对应的恢复协程时，启动执行协程恢复模块7022，恢复超时协程被中断时的上下文。
上述方式能够在识别到超时协程时，强行切换该超时协程，从而实现协程之间的公平、稳定运行。
需要说明的是，上述模块可以是硬件模块也可以是逻辑模块，当上述装置部署于虚拟机时，上述模块还可以是虚拟模块，本申请实施例对此不做限定。
下面结合图7所示的装置和具体的实施例对本申请实施例的协程切换流程进行介绍。
在该实施例中，将通过图7所示的装置对超时协程的完整切换过程进行介绍，示例性地，完整切换过程可以包括：初始化过程、协程切换过程和协程恢复过程。如下以第一线程，第一线程当前运行的协程为第一协程为例，分别对上述各过程进行介绍。
参见图8，为本申请实施例提供的超时协程的完整切换流程示意图，该流程包括：
一、初始化过程。
在第一线程启动运行之前(例如，可以是在创建第一线程时)，对第一线程进行初始化，初始化包括但不限于下列操作：
1)创建第一线程对应的共享存储空间。
示例性地，每个线程具有一个与其对应的共享存储空间，该线程的所有协程共享该共享存储空间。一种实施方式中，同一个线程内的各协程分别对应于该共享存储空间的不同区域，每一区域内可存储有该协程的上下文。例如，当前线程包含协程A、协程B、协程C，该共享存储空间也可以划分为协程A区域、协程B区域以及协程C区域。另一种实施方式中，同一线程内的各协程可以共享该共享存储空间的同一区域，该同一区域可用于存储协程的上下文。举例来说，对于同一线程的所有协程，由于线程内协程之间是串行方式运行的，而此共享存储空间可以是用于在协程切换过程中使用的，协程切换完成后，该共享存储空间内的信息即可被覆盖重复使用。例如，第一线程包含协程A、协程B和协程C，示例性地，该第一 线程的运行过程可以为执行协程A，之后切换到协程B，执行协程B，最后切换至协程C，执行协程C。若协程A为超时协程，则可以在切换协程A的过程中，将协程A的上下文存储于该第一线程的共享存储空间。当协程A切换完成后，执行协程B时，确定协程B为超时协程，此时第一线程的共享存储空间内存储有协程A的上下文，则可以将协程B的上下文覆盖协程A的上下文。
2)初始化第一线程的时钟模块。
设置时钟模块700的定时时间，即本申请实施例中的第一阈值。在时钟模块700计时时长达到该第一阈值时，触发中断信号。
在一种可实施的方式中，线程与时钟模块一一对应，即每个线程具有一一对应的时钟模块。例如，第一线程对应的时钟模块名称为时钟A，第二线程对应的时钟模块名称为时钟B，时钟A触发的中断信号是在检测到第一线程为超时协程时触发的，时钟B触发的中断信号为是在检测到第二线程为超时协程时触发的。在另一种可实施的方式中，部分或全部线程共享一个时钟模块。例如，第一线程和第二线程均对应于一个时钟模块。该时钟模块触发中断信号后，超时协程处理模块在响应该中断信号时，还需要确定该中断信号是针对哪个线程触发的。因此，在初始化过程中，还可以将即将执行的协程的标识(ID)配置给中断处理模块701，当接收到响应信号后，根据该标识确定哪个协程为超时协程。具体参见下文3)的介绍。
3)初始化中断处理模块701。
具体的，将协程保存模块7021的相关信息配置给配置时钟模块700对应的中断处理模块701。其中，协程保存模块7021的相关信息包括但不限于：超时协程保存模块702的代码入口地址(如PC值)、超时协程保存模块702对应的堆栈地址(如栈顶SP值)。另外，若多个线程共享一个时钟模块，则还可以将第一线程的标识(ID)配置给中断处理模块701，还可以配置其他信息，本申请对此不作限定。
需要说明的是，若线程与时钟模块一一对应，也可以将第一线程的标识(identifier，ID)配置给中断处理模块701，从而在响应中断信号，减少线程识别时间，或者中断处理模块701根据发送中断信号的时钟模块来识别线程，本申请实施例对此不作限定。
二、启动执行第一协程。
调度器模块703存储有任务队列，任务队列内包含第一线程的全部待执行的协程。假设调度器模块703在任务队列中选择第一协程为即将执行的协程，调度器模块703记录第一协程的信息，该信息主要包括第一协程的协程控制块的位置信息。应说明的是，每个协程具有各自对应的协程控制块，示例性地，类似于线程控制块，协程控制块用于记录协程任务的信息，例如，协程任务的sp值，还可以包括协程任务的堆栈大小等信息，协程控制块可以用于唯一标识协程，即根据协程控制块确定当前运行的协程。示例性地，第一协程的协程控制块的位置信息可以是该协程控制块的索引值，调度器模块703可以根据该索引值找到协程控制块，根据协程控制块确定第一线程内当前运行的协程。
调度器模块703启动执行第一协程，同时启动时钟模块700开始计时。示例性地，当第一协程主动申请调度时，时钟模块700关闭。
三、检测到第一协程为超时协程，触发中断信号。
示例性地，当时钟模块700的计时时长达到第一阈值时，确定第一协程为超时协程，触发中断信号。
四、响应中断信号，跳转至中断处理模块701执行中断处理。
具体的，当运行中断处理程序时，中断处理模块701执行下列中断处理：
根据当前协程所在的线程的状态，通过不同的方法保存当前协程的上下文，示例性地，如前所述，线程的状态包括：执行状态、就绪状态和中断状态，具体实施过程中，可以采用以下方式中任一种保存当前协程的上下文，包括：
方式1：当第一协程所在线程为中断状态时，将第一协程被中断时的上下文保存至共享存储空间。
示例性地，第一协程所在的线程仍在运行态，但由于第一协程的运行时间超时，需要切换至第一线程的其他协程运行，因此，该线程被中断。可以理解，线程仍可以运行，运行时间未达到时间片的时长，例如，线程仍处于自身的时间片内，但第一协程的运行时间超过了第一阈值，则需要暂停第一协程，切换至线程的其他协程，此时线程被中断信号暂停的状态即为中断状态。
对应的，中断处理模块102执行第一处理程序，包括：
1)将第一线程被中断时的上下文保存至第一线程对应的共享存储空间中，其中，上下文信息包括PC、SP等寄存器的值。中断处理程序位于内核空间，协程运行于用户空间，在响应中断信号时，用户空间正在执行的协程会被强行中断，转而执行中断处理程序。对应的，共享存储空间也可以位于内核空间，共享存储空间的大小可以是动态调整的，也可以是固定大小，例如，为存储协程被中断时上下文信息时，所需要的内存最大值。
2)将中断返回地址修改为协程保存模块7021的入口PC地址，将中断返回堆栈地址修改为协程保存模块7021的堆栈栈顶SP地址。
一般的，在每个中断处理程序的最后，有中断返回先前程序的指令，例如iret(或iretd)，当需要中断返回时，中断返回恢复当前协程被中断时的上下文，以继续执行被中断的程序，举例来说，中断返回地址默认为当前线程被中断时的代码地址，中断返回的堆栈地址默认为当前线程被中断时的堆栈，执行中断返回指令时，恢复先前保存的被暂停线程的上下文。例如，若当前线程被中断时正在执行协程A，则中断返回时，恢复协程A被中断时的上下文。
3)执行中断返回，恢复协程保存模块7021的上下文，跳转至协程保存模块7021的上下文运行。这里，将中断返回的上下文修改为协程保存模块7021的上下文，执行中断返回，便可以跳转至协程保存模块7021的代码段和数据段，以运行协程保存模块7021的程序。
方式2：当第一线程为就绪状态，则将第一线程控制块内记录的该第一线程的上下文保存于共享存储空间。
若在触发中断信号时，第一线程为就绪状态，对应的，中断处理模块102执行第二处理程序，包括：
1)将该第一线程的线程控制块内保存的寄存器上下文信息保存至第一线程对应的共享存储空间。
应理解的是，在时钟模块700计时完成之前，第一线程可能已被调度出执行状态，为了使后续第一该线程能恢复执行当前的任务，CPU会将第一线程被暂停时的上下文记录至第一线程控制块内，当再次调度该第一线程时，恢复第一线程控制块内记录的上下文，继续执行第一线程。
因此，当响应中断信号时，不能去CPU的寄存器获取第一协程的寄存器值，而是从第一线程的线程控制块内获取第一协程的上下文信息。
2)将该线程控制块内记录的PC地址修改为协程保存模块7021的入口PC地址，将线程控制块内记录的SP地址修改为协程保存模块7021的堆栈栈顶SP地址。
本申请实施例中，将第一线程控制块内记录的上下文修改为协程保存模块7021的上下 文，通过上述修改，当再次调度第一线程时，根据修改后的第一线程控制块内记录的上下文，跳转至协程保存模块7021，从而执行协程保存模块7021存储的程序，实现后续的协程切换。
3)执行中断返回。假设响应中断信号前正在运行的线程为第二线程，则响应该中断信号在跳转至中断处理模块701运行时，第二线程会被暂停，当中断处理模块701执行中断返回时，若未修改中断返回的相关信息，则会恢复第二线程被暂停时的上下文，以继续执行第二线程。应理解的是，当第一线程再次被调度后，根据第一线程的线程控制块内记录的PC值和SP值，会跳转至协程保存模块7021。
五、调转至协程保存模块7021。
跳转至协程保存模块7021后，执行下列操作：
1)生成超时协程对应的恢复协程。
示例性地，查询第一线程被中断时正在执行的协程(即第一协程)，示例性地，根据协程控制块的信息确定第一协程。从共享存储空间获取第一协程的上下文，示例性地，第一协程的上下文为一个或多个寄存器值，例如包括PC值、SP值。如图8所示，首先，按照预设存储格式将获取到的一个或多个寄存器值保存至第一协程的堆栈的第一空间中，然后将协程恢复模块7022的上下文保存至该堆栈的第二空间中，其中，第一空间与第二空间相邻。
举例来说，假设第一协程被中断时的上下文包括寄存器A的值、寄存器B的值、寄存器C的值。例如，预设存储格式可以是，依次将寄存器A的值、寄存器B的值、寄存器C的值压入堆栈。又例如，预设存储格式还可以是，依次将寄存器C的值、寄存器B的值、寄存器A的值依次压入堆栈。
应理解的是，由于第一线程是被中断信号中断的，因此，相对于正常的第一线程主动申请调度的方式，第一线程需要保存的寄存器的数量是不同的，一般的，前者需要保存的寄存器数量大于后者。因此，本申请实施例通过预设存储格式对上下文信息进行保存，即根据第一协程被中断时可能包含的寄存器的数量，按照自定义的保存方式存储至堆栈中，之后，协程恢复模块7022可以按照预设存储格式依次在堆栈中读取该协程的一个或多个寄存器值，从而恢复该第一线程的上下文。对于协程恢复模块7022的上下文的存储格式，可以是按照现有技术中协程任务主动申请调度时的存储格式进行保存，也可以是其他格式，本申请实施例不作限定。
根据更新后的数据堆栈生成超时协程对应的恢复协程，将恢复协程再次挂入任务队列中，等待后续再次被调度执行。
2)跳转至调度器模块703的上下文运行。
协程保存模块7021还存储有调度器模块703的地址，上述流程执行完毕后，调整至调度器模块703。
六、跳转至调度器模块703，选择第二协程，切换为当前运行协程。
调度器模块703，按照调度策略在任务队列中选择即除恢复协程之外的一个新的协程(记为第二协程)，记录该新的协程的信息，并启动执行该新的协程。
其中，调度策略有多种，例如，可以是按照协程的优先级，在待执行的协程中选择优先级最高的协程，或者通过排队方式顺序选择位置最前的协程，或者随机选择一个协程，本申请实施例对此不作限定。
在一种可能的实施例中，在响应中断信号时，还可以产生逻辑异常，则中断处理模块701可以直接执行中断返回，返回被中断的线程继续运行。或者，在时钟模块700超时前，第一协程主动申请调度，则关闭时钟模块700。
如上介绍了超时协程的切换过程，应理解，超时协程对应的恢复协程还可能会被调度，下面对调度执行恢复协程的过程进行介绍。
如前所述的恢复协程的堆栈数据包含第一空间和第二空间，当该恢复协程被调度器模块703再次调度恢复协程时，结合图8所示，首先，从该恢复协程的第二空间依次读取出协程恢复模块7022的各寄存器值，将各寄存器值写入对应的CPU寄存器，在读取到BP值时，根据该BP值确定第二空间的栈底地址，随后读取PC值，该PC值为协程恢复模块7022的代码入口PC地址，将该PC值写入CPU的程序计数器，跳转至协程恢复模块7022的代码段执行协程恢复模块7022。
协程恢复模块7022，按照预设存储格式从该堆栈的第一空间依次读取第一协程的一个或多个寄存器值，假设第一空间内依次存储有寄存器C的值、寄存器B的值、寄存器A的值，则协程恢复模块7022按照预设存储格式，可以确定从堆栈中依次读取出的为寄存器A的值，寄存器B的值、寄存器C的值，并将读取的寄存器的值依次写入对应的CPU寄存器中，恢复协程被中断时的现场。示例性地，协程恢复模块7022将从第一空间读取出的SP值写入SP寄存器；根据读取出的BP值，确定第一空间的栈底；将读取出的PC值写入程序计数器，该PC值为第一线程运行第一协程时被中断时的代码地址，跳转至该代码地址恢复执行第一协程。
为了方便描述本实施例提供的协程切换方法，下文将通过与本实施例提供的协程切换方法相关的部件介绍本实施例的协程切换方法。
参见图9，为本实施例提供的一种协程切换方法的流程示意图，该方法可以应用于图7所示的装置中，在图9中，将对超时协程所在的线程为中断状态时的具体切换方式进行介绍，该方法包括如下步骤：
步骤901，初始化线程。
步骤902，确定即将执行的第一协程，调度器模块记录第一协程的信息。
步骤903，调度器模块启动执行该协程，同时开启时钟模块。
其中，时钟模块的超时值可以是固定的，或者是每次开启前设置的。
步骤901至步骤903的具体执行流程请参见上文相关描述，此处不再赘述。
步骤904，时钟模块700超时，且第一协程未主动申请调度，向中断处理模块701发送中断信号。
步骤905，响应于该中断信号，若第一线程为中断状态，则中断处理模块701将第一线程被中断时的上下文保存至共享存储空间。
可选的，时钟模块发送中断信号后，中断处理模块701还可以控制时钟模块关闭，清除中断信号。
步骤906，中断处理模块701将中断返回的相关信息修改为协程保存模块7021对应的相关信息。
步骤907，中断处理模块701执行中断返回，恢复协程保存模块7021的上下文，跳转至协程保存模块7021。
步骤908，协程保存模块7021根据协程控制块的信息确定第一线程被中断时正在运行的。
如前所述，调度器模块内记录有第一线程正在执行的协程的协程控制块的位置信息，该协程控制块的位置信息索引到协程控制块，从而根据该协程控制块确定第一线程被中断前正在运行的协程，此示例里为第一协程。
步骤909，协程保存模块7021从共享存储空间获取该第一协程的上下文。
步骤910：超时协程处理模块702按照预设存储格式，将从共享存储空间获取的上下文保存至第一协程对应的堆栈中。
步骤911：超时协程处理模块702将协程恢复模块7022的上下文顺序保存至该第一协程的堆栈中。
步骤912：超时协程处理模块702生成该第一协程对应的恢复协程，并将该恢复协程加入任务队列。
步骤913：恢复调度器模块的上下文，跳转至调度器模块。
步骤914：调度器模块在任务队列中选择一个新的协程，启动执行该新的协程。
作为一种可能的实施例，中断处理模块701响应于该中断信号，若第一线程已被调度出运行状态，例如第一线程为就绪状态时，中断处理模块701执行前文所述的第二处理程序，即将该第一线程的线程控制块内保存的寄存器上下文信息保存至第一线程对应的共享存储空间。中断处理模块701将该线程控制块内记录的PC地址修改为协程保存模块7021的入口PC地址，将线程控制块内记录的SP地址修改为协程保存模块7021的堆栈栈顶SP地址。中断处理模块701执行中断返回，返回被暂停的线程。第一线程再次被调度时，根据第一线程的线程控制块恢复协程保存模块7021的上下文，跳转至协程保存模块7021。后续流程可以参见步骤908至步骤914的具体描述，以及中断处理模块701在响应中断信号之前的步骤可以参见步骤901至步骤904的具体描述，在此处不再重复说明。
通过上述设计，能够在识别到超时协程时，强行切换该超时协程，切换至第二协程运行，避免某一协程运行时长过长，其他协程得不到执行机会，实现协程之间的公平、稳定运行，提升系统性能。另一方面，由于中断处理的优先级较高，因此在第一协程为超时协程时，可以强制将第一协程中断，从而切换至其他协程。进一步，保存第一协程被中断的上下文，使得再次调度第一协程时能够恢复当前的上下文继续运行该协程。
基于与方法实施例同一发明构思，本申请实施例还提供了一种设备，用于执行上述方法实施例中执行的方法，相关特征可参见上述方法实施例，此处不再赘述，如图10所示，该设备包括确定单元1001以及处理单元1002。
确定单元1001，用于确定第一协程为超时协程，所述超时协程为运行时长达到第一阈值的协程；
处理单元1002，用于中断所述第一协程，切换第二协程作为当前执行协程。
应理解的是，本实施例的设备可以通过专用集成电路(application-specific integrated circuit，ASIC)实现，或可编程逻辑器件(programmable logic device，PLD)实现，上述PLD可以是复杂程序逻辑器件(complex programmable logical device，CPLD)，现场可编程门阵列(field-programmable gate array，FPGA)，通用阵列逻辑(generic array logic，GAL)或其任意组合。也可以通过软件实现图8至图9所示的方法时，设备及其各个模块也可以为软件模块。
在一种可能的实施方式中，所述确定单元1001，具体用于在所述第一协程启动时开始计时；当所述第一协程的运行时长达到第一阈值时，确定所述第一协程为超时协程。
在一种可能的实施方式中，所述处理单元1002，具体用于选择所述第二协程，所述第二协程为任务队列中与所述第一协程相邻的协程；将所述第二协程作为当前执行协程。
在一种可能的实施方式中，所述第二协程为所述第一线程包含的待执行的协程中随机选择的一个协程；或者所述第二协程为所述第一线程包含的待执行的协程中优先级最高的协程；或者，所述第二协程为所述第一线程包含的待执行的协程中当前时刻排序最前的协程。
在一种可能的实施方式中，所述处理单元1002，具体用于触发中断处理，所述中断处理包括：根据所述第一协程所在的线程状态保存第一协程被中断时的上下文，所述上下文用于指示所述第一线程被中断时的运行信息。
在一种可能的实施方式中，所述处理单元1002，具体用于当所述第一协程所在的第一线程为中断状态，则将所述第一线程的寄存器值保存至内核共享空间，所述内核共享空间为所述第一线程对应的内核存储空间，所述寄存器值用于记录所述第一线程的所述运行信息。
在一种可能的实施方式中，所述处理单元1002，还用于将中断返回的上下文修改为协程处理程序的上下文；执行中断返回，运行所述协程处理程序；其中，运行所述协程处理程序用于在应用层生成所述第一协程对应的恢复协程，执行所述恢复协程用于恢复所述第一协程被中断时的现场。
在一种可能的实施方式中，所述处理单元1002，具体用于：当所述第一协程所在的第一线程为等待状态，则将所述第一线程控制块内存储的所述第一线程的上下文保存至内核共享空间，所述内核共享空间为所述第一线程对应的内核存储空间，所述寄存器值用于记录所述第一线程的所述运行信息。
在一种可能的实施方式中，所述处理单元1002，还用于：将所述第一线程控制块内存储的上下文修改为协程处理程序的上下文，以便在所述第一线程再次被调度时，恢复所述协程处理程序的上下文，运行所述协程处理程序；其中，运行所述协程处理程序用于在应用层生成所述第一协程对应的恢复协程，执行所述恢复协程用于恢复所述第一协程被中断时的现场。
在一种可能的实施方式中，所述处理单元1002具体用于：从所述内核共享空间获取所述第一线程的寄存器值，并按照预设格式将所述第一协程的寄存器值保存至所述第一协程对应的数据结构；所述预设格式用于指示所述第一协程的寄存器值的保存顺序；根据进行保存后的所述数据结构，生成所述第一协程对应的上述恢复协程。
在一种可能的实施方式中，所述处理单元1002，还用于运行所述恢复协程：按照预设格式从所述第一协程对应的数据结构读取所述第一协程的寄存器值，将所述寄存器值写入对应的寄存器。
在一种可能的实施方式中，所述处理单元1002，还用于将协程恢复程序的上下文保存至所述数据结构中；所述处理单元运行所述恢复协程时，还用于从所述数据结构中读取所述协程恢复程序的上下文，运行所述协程恢复程序，其中，运行所述协程恢复程序用于按照预设格式从所述第一协程对应的数据结构读取所述第一协程的寄存器值，将所述寄存器值写入对应的寄存器。
根据本申请实施例的设备可对应于执行本申请实施例中描述的方法，并且装置设备中的各个单元的上述和其它操作和/或功能分别为了实现图8至图9中的各个方法的相应流程，为了简洁，在此不再赘述。
与上述构思相同，如图11所示，本申请提供一种设备1100，设备1100可应用于上述图4所示场景中的其中一个网络设备上，执行如图8或图9所示的方法中执行主体执行的步骤。
设备1100可包括处理器1101和存储器1102。进一步的，该装置还可包括通信接口1104，该通信接口可为收发器，或者该通信接口可为网卡。进一步的，该设备1100还可包括总线系统1103。
其中，处理器1101、存储器1102和通信接口1104可通过总线系统1103相连，该存储器1102可用存储指令，该处理器1101可用于执行该存储器1102存储的指令，以控制通信接口1104接收或发送信号，完成上述图8或图9所示方法中执行主体的步骤。
其中，存储器1102可以集成在处理器1101中，也可以是与处理器1101不同的物理实体。
应理解，该处理器1101可以是CPU，该处理器1101还可以是其他通用处理器、数字信号处理器(digital signal processing，DSPDSP)、专用集成电路(ASIC)、现场可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者是任何常规的处理器等。
该存储器1102可以包括只读存储器和随机存取存储器，并向处理器1101提供指令和数据。存储器1102还可以包括非易失性随机存取存储器。例如，存储器1102还可以存储设备类型的信息。
该存储器1102可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data date SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。
该总线1103除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图中将各种总线都标为总线1103。
作为一种实现方式，通信接口1104的功能可以考虑通过收发电路或收发的专用芯片实现。处理器1101可以考虑通过专用处理芯片、处理电路、处理器或通用芯片实现。
作为另一种实现方式，可以考虑使用计算机的方式，来实现本申请实施例提供的第一计算节点或第一计算节点的功能。即将实现处理器1101和通信接口1104功能的程序代码存储在存储器1102中，通用处理器可通过执行存储器中的代码来实现处理器1101和通信接口1104的功能。
该设备1100所涉及的与本申请提供的技术方案相关的概念、解释和详细说明以及其他步骤，可参见前述方法或其它实施例中关于这些内容的描述，此处不作赘述。
在本申请的一示例中，所述设备1100可用于执行上述图8或图9所示流程中，执行主体的步骤。比如，通信接口1104可以接收侦测第一数据报文；处理器1101可以响应通信接口1104侦测到的第一数据报文，且在第一数据结构中没有空间记录所述第一数据报文所属的第一数据流的信息时，确定第一数据结构中记录的与第一数据流具有相同哈希值的数据流中是否有超过一预设时间，信息没有被更新的第二数据流；如果有，则用第一数据流的信息替换第二数据流的信息。
关于处理器1101和通信接口1104的介绍，可参见上述图8或图9所示流程的介绍，在此不再赘述。
应理解，根据本申请实施例的设备1100可对应于本申请实施例中的图10中设备，并可以对应于执行根据本申请实施例的方法100中的相应主体，并且设备1100中的各个模块的上述和其它操作和/或功能分别为了实现图8至图9中的各个方法的相应流程，为了简洁，在此不再赘述。
上述实施例，可以全部或部分地通过软件、硬件、固件或其他任意组合来实现。当使用软件实现时，上述实施例可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载或执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以为通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集合的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质。半导体介质可以是固态硬盘(solid state drive，SSD)。
以上所述，仅为本申请的具体实施方式。熟悉本技术领域的技术人员根据本申请提供的具体实施方式，可想到变化或替换，都应涵盖在本申请的保护范围之内。

Claims (19)

  1. 一种协程切换方法，其特征在于，包括：
    确定第一协程为超时协程，所述超时协程为运行时长达到第一阈值的协程；
    中断所述第一协程；
    切换第二协程作为当前执行协程。
  2. 如权利要求1所述的方法，其特征在于，所述确定第一协程为超时协程，包括：
    在所述第一协程启动时开始计时；
    当所述第一协程的运行时长达到第一阈值时，确定所述第一协程为超时协程。
  3. 根据权利要求1或2所述的方法，其特征在于，所述切换第二协程作为当前执行协程，包括：
    选择所述第二协程，所述第二协程为任务队列中与所述第一协程相邻的协程；
    将所述第二协程作为当前执行协程。
  4. 根据权利要求3所述的方法，其特征在于，所述选择所述第二协程，包括以下方式中任意一种：
    所述第二协程为所述第一线程包含的待执行的协程中随机选择的一个协程；
    所述第二协程为所述第一线程包含的待执行的协程中优先级最高的协程；或者，
    所述第二协程为所述第一线程包含的待执行的协程中当前时刻对所述协程进行排序获得的协程。
  5. 如权利要求1至4中任一所述的方法，其特征在于，所述中断所述第一协程，包括：
    触发中断处理，所述中断处理包括：
    根据所述第一协程所在的线程状态保存第一协程被中断时的上下文，所述上下文用于指示所述第一线程被中断时的运行信息。
  6. 根据权利要求5所述的方法，其特征在于，所述根据所述第一协程的状态保存第一线程被中断时的上下文，包括：
    当所述第一协程所在的第一线程为中断状态，则将所述第一线程的寄存器值保存至内核共享空间，所述内核共享空间为所述第一线程对应的内核存储空间，所述寄存器值用于记录所述第一线程的所述运行信息。
  7. 根据权利要求6所述的方法，其特征在于，该方法还包括：
    将中断返回的上下文修改为协程处理程序的上下文；
    执行中断返回，运行所述协程处理程序；其中，运行所述协程处理程序用于在应用层生成所述第一协程对应的恢复协程，执行所述恢复协程用于恢复所述第一协程被中断时的现场。
  8. 如权利要求7所述的方法，其特征在于，该方法还包括：
    运行所述恢复协程：
    按照预设格式从所述第一协程对应的数据结构读取所述第一协程的寄存器值，将所述寄存器值写入对应的寄存器。
  9. 如权利要求8所述的方法，其特征在于，按照预设格式将所述第一协程的寄存器值保存至所述第一协程对应的数据结构之后，生成所述第一协程对应的上述恢复协程之前，还包括：
    将协程恢复程序的上下文保存至所述数据结构中；
    运行所述恢复协程，还包括：
    从所述数据结构中读取所述协程恢复程序的上下文，运行所述协程恢复程序，其中，运 行所述协程恢复程序用于按照预设格式从所述第一协程对应的数据结构读取所述第一协程的寄存器值，将所述寄存器值写入对应的寄存器。
  10. 一种设备，其特征在于，该设备包括确定单元、处理单元：
    所述确定单元，用于确定第一协程为超时协程，所述超时协程为运行时长达到第一阈值的协程；
    所述处理单元，用于中断所述第一协程，切换第二协程作为当前执行协程。
  11. 如权利要求10所述的设备，其特征在于，所述确定单元，具体用于在所述第一协程启动时开始计时；当所述第一协程的运行时长达到第一阈值时，确定所述第一协程为超时协程。
  12. 如权利要求10或11所述的设备，其特征在于，所述处理单元，具体用于选择所述第二协程，所述第二协程为任务队列中与所述第一协程相邻的协程；将所述第二协程作为当前执行协程。
  13. 如权利要求12所述的设备，其特征在于，所述第二协程为所述第一线程包含的待执行的协程中随机选择的一个协程；
    所述第二协程为所述第一线程包含的待执行的协程中优先级最高的协程；或者，
    所述第二协程为所述第一线程包含的待执行的协程中当前时刻排序最前的协程。
  14. 如权利要求10-13任一项所述的设备，其特征在于，所述处理单元，具体用于触发中断处理，所述中断处理包括：根据所述第一协程所在的线程状态保存第一协程被中断时的上下文，所述上下文用于指示所述第一线程被中断时的运行信息。
  15. 如权利要求14所述的设备，其特征在于，所述处理单元，具体用于当所述第一协程所在的第一线程为中断状态，则将所述第一线程的寄存器值保存至内核共享空间，所述内核共享空间为所述第一线程对应的内核存储空间，所述寄存器值用于记录所述第一线程的所述运行信息。
  16. 如权利要求15所述的设备，其特征在于，所述处理单元还用于将中断返回的上下文修改为协程处理程序的上下文；执行中断返回，运行所述协程处理程序；其中，运行所述协程处理程序用于在应用层生成所述第一协程对应的恢复协程，执行所述恢复协程用于恢复所述第一协程被中断时的现场。
  17. 如权利要求16所述的设备，其特征在于，所述处理单元，还用于运行所述恢复协程：按照预设格式从所述第一协程对应的数据结构读取所述第一协程的寄存器值，将所述寄存器值写入对应的寄存器。
  18. 如权利要求17所述的设备，其特征在于，所述处理单元，还用于将协程恢复程序的上下文保存至所述数据结构中；
    所述处理单元运行所述恢复协程时，还用于从所述数据结构中读取所述协程恢复程序的上下文，运行所述协程恢复程序，其中，运行所述协程恢复程序用于按照预设格式从所述第一协程对应的数据结构读取所述第一协程的寄存器值，将所述寄存器值写入对应的寄存器。
  19. 一种设备，其特征在于，包括一个或多个处理器和一个或多个存储器；
    所述一个或多个存储器与所述一个或多个处理器耦合，所述一个或多个存储器用于存储计算机程序代码，所述计算机程序代码包括计算机指令，当所述一个或多个处理器执行所述计算机指令时，所述终端设备执行如权利要求1-9任一项所述的方法。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117032844A (zh) * 2023-10-07 2023-11-10 北京集度科技有限公司 一种协程链路追踪装置、方法及智能车辆
US11954472B2 (en) * 2021-01-25 2024-04-09 Vmware, Inc. Conflict resolution for device-driven management

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104142858A (zh) * 2013-11-29 2014-11-12 腾讯科技（深圳）有限公司 阻塞任务调度方法及装置
CN105760237A (zh) * 2016-02-05 2016-07-13 南京贝伦思网络科技股份有限公司 一种基于协程机制的通讯方法
CN106980546A (zh) * 2016-01-18 2017-07-25 阿里巴巴集团控股有限公司 一种任务异步执行方法、装置及系统
CN107943577A (zh) * 2016-10-12 2018-04-20 百度在线网络技术（北京）有限公司 用于调度任务的方法和装置
WO2020024469A1 (zh) * 2018-07-31 2020-02-06 平安科技（深圳）有限公司 一种业务处理方法、调用管理系统和计算机设备

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104142858A (zh) * 2013-11-29 2014-11-12 腾讯科技（深圳）有限公司 阻塞任务调度方法及装置
CN106980546A (zh) * 2016-01-18 2017-07-25 阿里巴巴集团控股有限公司 一种任务异步执行方法、装置及系统
CN105760237A (zh) * 2016-02-05 2016-07-13 南京贝伦思网络科技股份有限公司 一种基于协程机制的通讯方法
CN107943577A (zh) * 2016-10-12 2018-04-20 百度在线网络技术（北京）有限公司 用于调度任务的方法和装置
WO2020024469A1 (zh) * 2018-07-31 2020-02-06 平安科技（深圳）有限公司 一种业务处理方法、调用管理系统和计算机设备

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11954472B2 (en) * 2021-01-25 2024-04-09 Vmware, Inc. Conflict resolution for device-driven management
CN117032844A (zh) * 2023-10-07 2023-11-10 北京集度科技有限公司 一种协程链路追踪装置、方法及智能车辆
CN117032844B (zh) * 2023-10-07 2024-01-09 北京集度科技有限公司 一种协程链路追踪装置、方法及智能车辆

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