WO2022042015A1 - Data processing method and apparatus for performance monitoring of system on a chip - Google Patents

Abstract

A data processing method and apparatus for performance monitoring of a system on a chip. The method comprises: when a first transaction request is detected, obtaining information of the first transaction request, the information comprising a first tag of the first transaction request (101); and on the basis of the first tag of the first transaction request, storing the information of the first transaction request in a first linked list corresponding to the first tag, wherein the first linked list comprises at least one node, and a storage unit corresponding to each node of the first linked list stores information of one transaction request having the first tag (102).

Description

Data processing method and device for system chip performance monitoring

CROSS-REFERENCE TO RELATED APPLICATIONS

The present disclosure claims the priority of the Chinese patent application entitled "Data Processing Method and Apparatus for System-on-Chip Performance Monitoring", filed on August 31, 2020, with application number 202010899040.X, the entire contents of which are hereby incorporated by reference. into this article.

technical field

The present disclosure relates to the technical field of chip design, and in particular, to a data processing method and apparatus for system chip performance monitoring.

Background technique

In the system chip design process, the main system and each subsystem are connected through the data path to realize the functions of the entire chip system. The data path is implemented as a bus, one subsystem can send a transaction request to another subsystem through the data path, and the other subsystem can respond to the transaction request. Various information can be counted through the system bus performance monitoring module, such as the delay information of each transaction request and the data bandwidth occupied by each subsystem. In one example, each time the system bus performance monitoring module monitors a transaction request, it stores the information of the transaction request in the storage space. However, due to the large number of subsystems, each subsystem has a different period of preparing data for different transmission transactions, and the number of requests supported by the chip system is large. When monitoring the performance of the chip system, a large number of arithmetic operations and logical operations are required. To determine the storage location of the information requested by each transaction from the storage space, the complexity of the system bus performance monitoring module is high.

SUMMARY OF THE INVENTION

The present disclosure provides a data processing method and device for system chip performance monitoring.

According to a first aspect of the embodiments of the present disclosure, there is provided a data processing method for system chip performance monitoring, the method comprising: when a first transaction request is detected, acquiring information of the first transaction request, The information includes a first tag of the first transaction request; based on the first tag of the first transaction request, the information of the first transaction request is stored in a first linked list corresponding to the first tag , wherein the first linked list includes at least one node, and a storage unit corresponding to each node of the first linked list stores information about a transaction request with the first label.

According to a second aspect of the embodiments of the present disclosure, there is provided a data processing method for system chip performance monitoring, the method comprising: when a first transaction request is detected, in the first linked list, the first The transaction request creates a first node; and the information of the first transaction request is stored in a storage unit allocated for the first node, wherein the nodes of at least two linked lists share a plurality of storage units.

According to a third aspect of the embodiments of the present disclosure, there is provided a data processing apparatus for monitoring system chip performance, the apparatus comprising: a controller module, an insert polling module, and a linked list storage unit, wherein the controller modules are respectively Connected with the insert polling module and the linked list storage unit, the linked list storage unit is connected with the insert polling module; the controller module is configured to obtain all the information when the first transaction request is detected. the information of the first transaction request, the information includes the first tag of the first transaction request; the insertion polling module module is configured to, based on the first tag of the first transaction request, The information of the transaction request is stored in the first linked list corresponding to the first label in the linked list storage unit; wherein, the first linked list includes at least one node, and the storage unit corresponding to each node of the first linked list Information about a transaction request with the first tag is stored.

According to a fourth aspect of the embodiments of the present disclosure, there is provided a data processing apparatus for system chip performance monitoring, the apparatus comprising: a creation module for, when a first transaction request is detected, in the first linked list Create a first node for the first transaction request; a storage module, configured to store the information of the first transaction request in a storage unit allocated for the first node, wherein the nodes of at least two linked lists share multiple storage unit.

According to a fifth aspect of the embodiments of the present disclosure, there is provided a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, implements the method of the first aspect or the second aspect.

According to a sixth aspect of the embodiments of the present disclosure, there is provided a computer device including a memory, a processor, and a computer program stored in the memory and executable on the processor, the processor implementing the first aspect when the program is executed or the method described in the second aspect.

In the embodiment of the present disclosure, the information of the transaction request is stored in the linked list based on the tag of the transaction request, wherein the information of multiple transaction requests with the same tag is stored in multiple nodes of the same linked list, so that complex arithmetic and logical operations are not required. , the transaction request information of the same tag can be read from the same linked list, which reduces the complexity and storage space requirements of the system bus performance monitoring module, and at the same time improves the efficiency of system bus performance monitoring.

It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.

Description of drawings

FIG. 1 is a flowchart of a data processing method for system chip performance monitoring according to an embodiment of the present disclosure.

FIG. 2 is a schematic diagram of a linked list structure according to an embodiment of the present disclosure.

FIG. 3 is a schematic diagram of a process of inserting and extracting a transaction request according to an embodiment of the present disclosure.

FIG. 4 is a schematic diagram of a tail node of a parallel polling linked list according to an embodiment of the present disclosure.

FIG. 5 is a flowchart of a data processing method for system chip performance monitoring according to another embodiment of the present disclosure.

FIG. 6 is a block diagram of a data processing apparatus for system chip performance monitoring according to an embodiment of the present disclosure.

FIG. 7 is a block diagram of a data processing apparatus for SoC performance monitoring according to another embodiment of the present disclosure.

FIG. 8 is a schematic structural diagram of a computer device according to an embodiment of the present disclosure.

detailed description

Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. Where the following description refers to the drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the illustrative examples below are not intended to represent all implementations consistent with this disclosure. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present disclosure as recited in the appended claims.

The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used in this disclosure and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items. Additionally, the term "at least one" herein refers to any one of a plurality or any combination of at least two of a plurality.

It should be understood that although the terms first, second, third, etc. may be used in this disclosure to describe various pieces of information, such information should not be limited by these terms. These terms are only used to distinguish the same type of information from each other. For example, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information, without departing from the scope of the present disclosure. Depending on the context, the word "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determining."

In order for those skilled in the art to better understand the technical solutions in the embodiments of the present disclosure, and to make the above objects, features and advantages of the embodiments of the present disclosure more clearly understood, the following describes the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings. The program is described in further detail.

In the system chip design process, the system bus performance monitoring module is often used to monitor the performance of the chip system. Each subsystem in the chip system will generate transaction requests when working. Each time a transaction request is generated, the information of the transaction request will be stored in a storage unit. The system bus performance monitoring module reads the transaction request from the storage unit. information, and statistics the information in a specific way, so as to monitor the performance of the chip system. Each transaction request may be assigned a corresponding label for identifying the transaction request. In the event that a transaction request fails to receive a timely response, the same transaction request may be repeatedly generated and sent multiple times, in which case these repeatedly generated transaction requests may be assigned the same tag. When the protocols adopted by the chip system are different, the maximum number of unanswered transaction requests supported by the chip system is also different. The above-mentioned unanswered transaction requests may all be transaction requests of the same label, or may include multiple transaction requests of different labels. The solution of the embodiment of the present disclosure will be described below by taking an example that the maximum number of unanswered transaction requests may be 128. Those skilled in the art can understand that the maximum number is only an exemplary illustration and is not intended to limit the present disclosure.

Exemplarily, the maximum number of unanswered transaction requests may be called an outstanding number in the bus protocol, and the bus protocol may be AXI (Advanced eXtensible Interface) that supports outstanding transaction and multi-transaction out-of-order. ) bus protocol. To improve system performance, the processor subsystem can start the next transfer transaction before the current transfer transaction is completed. Therefore, there may be multiple transmission transactions in progress in the system, that is, advanced transmissions. However, for different subsystems, the time for preparing data is different, and it is possible that the data ready order is inconsistent with the transaction arrival order. Therefore, the processor subsystem needs a corresponding mechanism to identify the transaction to which the data belongs, such as using tags to identify transactions. , and the label can be defined according to the attribute of the bus, wherein the attribute of the bus can be the transmission channel information. In this way, the chip system can support out-of-order (no ordering restriction) requests and responses for transactions of different tags.

In one example, each time the system bus performance monitoring module monitors a transaction request, it stores the information of the transaction request in the storage space. However, due to the large number of subsystems, each subsystem has a different period of preparing data for different transmission transactions, and the number of requests supported by the chip system is large. When monitoring the performance of the chip system, a large number of arithmetic operations and logical operations are required. The storage location and/or storage information of the information requested by each transaction is determined from the storage space, resulting in low monitoring efficiency. For example, when calculating the delay between the response time and the generation time of the transaction request of the same tag, it is necessary to determine the time when the first transaction request of the tag occurs. The system bus performance monitoring module generally determines the order in which the transaction requests are generated according to the time stamps of each transaction request of the same tag. Therefore, it is necessary to determine the type of the first transaction request based on the timestamps of all valid transaction requests of the same tag in the storage space. In the worst case, the transaction request with the smallest timestamp needs to be selected from 128 transaction requests, that is, 127 comparison operations need to be performed. A large number of arithmetic operations and logical operations will consume more hardware resources and computing power, and the time required for statistical information is long, resulting in low monitoring efficiency.

Based on this, an embodiment of the present disclosure provides a data processing method for system chip performance monitoring. As shown in FIG. 1 , the method includes the following steps.

Step 101: In the case of detecting a first transaction request, obtain information of the first transaction request, where the information includes a first tag of the first transaction request.

Step 102: Based on the first label of the first transaction request, store the information of the first transaction request in a first linked list corresponding to the first label, wherein the first linked list includes at least one node, and the first linked list includes at least one node. A storage unit corresponding to each node of a linked list stores information of a transaction request with the first label.

The method of the embodiment of the present disclosure can be applied to a system bus performance monitoring module. The design of the module focuses on the transmission of large amounts of data. The design will consider a variety of bus protocols. Here, the bus protocol with tags (TAG ID, abbreviated as xID) is supported here. The bus protocol supports out-of-order requests and responses of different xID transactions. And sequential requests and replies for the same xID transaction. Among them, the out-of-order requests and responses of different xID transactions mean that the response sequences of different xID transactions may be different from their request sequences. The sequential request and response of the same xID transaction means that multiple transaction requests of the same xID are answered in sequence according to the order in which the requests are generated.

For example, a transaction request with xID of 1 includes transaction request 1, transaction request 2 and transaction request 3. During the generation process of the above three transaction requests, a transaction request with xID of 2 can also be generated, for example, including transaction request 4 and transaction request Request 5. The generation process of transaction requests of different xIDs may be independent of each other. Assuming that the order of generation of the above transaction requests is from early to late: transaction request 1, transaction request 4, transaction request 2, transaction request 3 and transaction request 5, then the transaction requests of the same xID need to be answered in order, for example, The response time of transaction request 1 should be earlier than transaction request 2, the response time of transaction request 2 should be earlier than transaction request 3, and the response time of transaction request 4 should be earlier than transaction request 5. The response times of transaction requests with different xIDs may be in any order. For example, the response time of transaction request 4 may be earlier than transaction request 1, or may be later than transaction request 2. Therefore, the response sequence of each of the above transaction requests can be: transaction request 1, transaction request 2, transaction request 4, transaction request 5 and transaction request 3, or transaction request 4, transaction request 5, transaction request 1, transaction request 2 and Transaction request 3 and so on.

Each time a transaction request is received, the information of the transaction request can be stored in a node of the linked list, that is, in a storage unit corresponding to the node. Among them, the linked list is a non-consecutive and non-sequential storage structure on the physical storage unit, and the logical order of data elements is realized by the link order of pointers in the linked list. Each node in a linked list can store the information of multiple transaction requests of the same label. Exemplarily, the information may include one or more kinds of information, wherein one kind of information represents the information of the bus transaction request, including but not limited to at least one of the type of the transaction request, the tag, and the timestamp when the event is requested. . The information may also include information indicating the position of the next node, that is, the pointer of the linked list. If the node is the tail of the linked list, the content of the pointer is not considered. By storing the information requested by each transaction of the same label in different nodes of the same linked list, since the nodes of the linked list are linked to each other through pointers, when monitoring the performance of the system chip, there is no need to compare the labels of each transaction request one by one. It is only necessary to find the linked list corresponding to the transaction request, and then search for information from each node of the linked list, which improves the monitoring efficiency. Further, information of multiple transaction requests with different tags can be stored in different linked lists.

In some embodiments, in order to facilitate searching for information from the linked list, the information requested by multiple transactions of the same tag may be stored in storage units corresponding to each node of the linked list in a specific order. The specific order may be a chronological order in which the plurality of transaction requests are detected. For example, for the same label, the detected information of the first transaction request is stored in the first node in the linked list, and the first node is represented as the header node; the detected information of the second transaction request is stored in the linked list and add the address of the second node in the header node, that is, the pointer of the header node points to the second node; and so on. Similarly, in order to facilitate extracting information from the linked list, the information of multiple transaction requests with the first tag is sequentially extracted according to the sequence of the multiple transaction requests in the first linked list. For example, first extract the information of the transaction request from the header node of the first linked list; find the next node according to the pointer of the header node, and set the next node as the new header node; extract the first label when needed When the information requested by the next transaction is obtained, the information requested by the transaction is extracted from the new header node, and so on.

In the case where only one tag's transaction request information is stored in each linked list, the depths of each linked list (ie, the number of nodes included in the linked list) in the embodiments of the present disclosure may be the same or different. In some embodiments, if a transaction request is detected, the information of the transaction request is stored in the linked list, and if a response to the transaction request is detected, the information of the transaction request is removed from the linked list Extracted from , therefore, the linked list can store information about currently unanswered transaction requests.

In some embodiments, each node in the linked list may be used to store information of one or more transaction requests, wherein, in the case where each node is used to store information of one transaction request, the first linked list currently includes The number of nodes may be equal to the number of currently unanswered transaction requests with the first label. For example, if there are currently 4 unanswered transaction requests with xID of 1, the depth of the linked list corresponding to the transaction request with xID of 1 is 4, that is, the linked list includes 4 nodes. For another example, if there are currently 5 unanswered transaction requests with xID of 2, the depth of the linked list corresponding to the transaction request with xID of 2 is 5.

In the chip system design, the communication bus can be allowed to support a maximum of 128 unanswered transaction requests, and these 128 transaction requests can be either transaction requests with the same xID, or 128 transaction requests with different xIDs, or less than 128 xID transaction requests. When using a linked list structure to store transaction requests, if 128 transaction requests are transaction requests with the same xID, each linked list is required to support a maximum of 128 nodes; in the case where 128 transaction requests are transaction requests with different xIDs , that is, a maximum of 128 linked lists are required. If a storage unit with a fixed depth of 128 nodes is designed for each xID transaction request, 128*128 storage units are required to satisfy the sequential request and response of the same xID transaction and the out-of-order request and response of different xID transactions. Require. The storage unit of one node may be a row of flip-flop storage arrays. In this case, the number of xIDs contained in unanswered transaction requests is between 1 and 128, and the depth of each link is between 128 and 1, and the number of trigger storage array rows is 128*128. Among them, the maximum number of trigger storage array rows used at the same time is 128, and the remaining (128-1)*128 trigger storage array rows are empty, but in the case of different transaction requests, this (128-1)* 128 flip-flop memory array row distribution is different. For example, the 128 trigger storage array rows may store the linked list corresponding to 128 transaction requests of the same xID, then the trigger storage array row of (128-1)*128 is the other 127 xID storage units. For another example, the 128 trigger storage array rows can store the linked list corresponding to 128 xID transaction requests, then the (128-1)*128 trigger storage array row is the 128 xIDs except the header node. storage unit.

In some embodiments, in order to further save storage units, the nodes of at least two linked lists may share a plurality of storage units, wherein each storage unit is used to store one node of the linked list. That is to say, the above-mentioned multiple storage units can be allocated to each node of the linked list with xID of 1, can also be allocated to each node of the linked list of xID of 2, or can be allocated to nodes in different linked lists respectively. The allocation is dynamic, and nodes are allocated/reclaimed from time to time based on each transaction request and response. Specifically, when the information of the first transaction request is stored in the first linked list, a storage unit may be allocated to the node corresponding to the first transaction request, so that the storage unit allocated to the first linked list The number of cells matches the number of nodes currently included in the first linked list. When a linked list includes several nodes, several storage units are allocated for the linked list. The total number of all allocated storage units is equal to the maximum number of unanswered transaction requests. That is, the number of the plurality of storage units is equal to the maximum number of unanswered transaction requests supported by the bus protocol.

In this case, the information stored by each node in the linked list must include the tag xID of the transaction request. Further, the stored information may also include other indication information, such as information indicating whether the storage unit is valid, information indicating whether it is a header, information indicating whether it is a footer, information indicating the location of the next node, and the like.

In the embodiment of the present disclosure, when a new node is created in a linked list, a storage unit may be allocated to the new node, and the information of the transaction request included in a certain node in the linked list is extracted. In this case, the storage unit allocated to the node can be reclaimed, for example, an information field indicating whether the storage unit is valid or not is set in the storage unit, and the information field includes indication information indicating whether the storage unit is valid or invalid, so as to facilitate If necessary, the storage unit indicating that the information is invalid can be allocated to other nodes.

The present disclosure adopts multiple linked lists, and the depth of the linked list allocated to the hardware is not fixed, but is dynamically allocated based on the xID transaction request, and the depth support of a linked list varies from 1 to 128. At the same time, the bus system supports a maximum of 128 unanswered transaction requests, which are allocated as a maximum of 128 xID linked lists. The nodes corresponding to transaction requests of different xIDs share storage space, and the size of the shared storage space is 128 storage units, such as trigger storage array rows. , through the linked list to complete the sequential request and response of the transaction and the out-of-order request and response of the transaction. In this way, not only enough storage units can be allocated for different linked lists, but also the number of storage units required by the system bus performance monitoring module can be reduced, thereby reducing the hardware cost of the chip. This way of sharing storage space by multiple linked lists is called a multi-linked list structure based on shared storage.

It should be noted that the present disclosure does not limit the hardware form for realizing the storage unit, which may be a flip-flop storage array row, a register storage array row, or other hardware circuits. For the sake of simplicity, the following is an example of a flip-flop storage array row.

In the case where the linked list structure is not used to store the transaction request information, if 128 trigger storage array rows (referred to as array rows) are used to store the transaction request information of all xIDs, when extracting the transaction request information, it is necessary to start from 128 triggers. The memory array row extracts valid rows, filters the xIDs corresponding to the transaction requests in each valid row, and finally selects the array row corresponding to the minimum timestamp from the filtered array rows. In this process, a large number of arithmetic operations and/or logical operations will be introduced, and each step (including extracting valid rows, selecting the array row corresponding to the minimum timestamp value, etc.) needs to consider 128 cases. The logic design is very complicated, and the amount of operations Also very large.

In some embodiments of the present disclosure, the nodes in the linked list can be dynamically adjusted, and when the first transaction request is detected, a new node can be created for the first transaction request; and the created node can be linked to the current tail node of the first linked list. That is to say, every time a transaction request is detected, a new node is created in the corresponding linked list for the transaction request, and the created new node is linked to the tail node of the corresponding linked list to become the new tail node of the linked list. In this way, the transaction requests corresponding to each node in the linked list are arranged in the order of the detected time. When extracting the information of the transaction request, the storage unit corresponding to the head node of the linked list can be directly extracted without going through complex arithmetic operations and Logical operations improve processing efficiency.

In some embodiments, when detecting a transaction response, the controller of the system bus performance monitoring module may determine a corresponding linked list of the transaction request for which the transaction response is directed based on the tag contained in the transaction response, and retrieve the corresponding linked list from the corresponding linked list. The header node extracts the information requested by the transaction. For example, the generation time of the transaction request labeled xIDn can be extracted from the storage unit corresponding to the head node of the linked list, and the time interval between the response time of the transaction response labeled xIDn and the generation time of the transaction request labeled xIDn can be calculated. , so as to count the delay between the transaction request with the tag xIDn and the transaction response with the tag xIDn. In practical applications, the delay between each transaction request and the transaction response can be counted, and the average delay between the transaction request of each tag and the transaction response of the corresponding tag generated within a period of time can also be counted. Those skilled in the art can understand that other parameters may also be counted according to the transaction request information included in the linked list, which will not be repeated here.

In some embodiments, one of the allocated storage units stores the tag of the transaction request, the information of the system bus transaction request, and the indication information. The indication information includes: first indication information for indicating whether the storage unit is a valid storage unit, second indication information for indicating whether the current node is the tail node of the linked list to which it belongs, and second indication information for indicating whether the current node is a The third indication information of the header node of the linked list is used to indicate the fourth indication information of the address of the storage unit storing the next node of the current node, wherein the current node is the node corresponding to the storage unit.

The above indication information may be carried in the nodes of the linked list. The linked list structure of some embodiments is shown in FIG. 2. In order to flexibly utilize 128 trigger storage array rows, that is, trigger storage array rows of a shared storage multi-linked list structure, a shared storage multi-linked list structure is used to store these information, The area in the box in the figure is the information space that needs to be stored in the transaction request, and the rest are the extension fields added to realize the shared storage.

A row in Fig. 2, such as the row marked as 0, indicates a row of the flip-flop memory array, which is composed of a plurality of flip-flops. The bit width of the flip-flop array row is determined by the specific information content.

The information space may include the label xID corresponding to the node and the information AXI INFO of the system bus transaction request. xID can be a 16-bit transaction request identifier, any xID value supported by the bus. The width of AXI INFO depends on the design needs, generally including the time stamp (TIMESLOT) when the transaction request is generated, the type of the bus, the granularity of the burst transmission (BURST SIZE), the type of the burst transmission (BURST TYPE), and the protection type (PROT) , cache type (CACHE), request address (ADDRESS), etc. Among them, the granularity of burst transmission is used to determine the size of the transaction request transmitted in a burst transmission process; the type of burst transmission is used to indicate the attribute of the transaction request transmitted in a burst transmission process; the protection type is used to indicate the transaction request in the system chip The security mode and level of access; the cache type is used to indicate the storage method of the transaction request, whether it is cached first and then stored in the storage unit from the cache, or directly stored in the storage unit; the request address is used to indicate the transaction request of the burst transmission. Start storage location.

The extension fields may include V fields, T fields, H fields and pointer (Next Pointer, NPTR) fields. The first indication information is included in the V domain of the node, the second indication information is included in the T domain of the node, the third indication information is included in the H domain of the node, and the fourth indication information is included in the pointer domain of the node.

In some embodiments, the V field may be represented by 1 bit, eg, "0" to indicate that the memory cell is invalid, and "1" to indicate that the memory cell is valid. In the case where the information stored in the storage unit is extracted, or when the storage unit is not allocated, such as during initialization, the storage unit is an invalid storage unit. If the stored information is not extracted, the storage unit is an effective storage unit. The T field can also be represented by 1 bit, for example, "0" is used to indicate that it is not a footer node, and "1" is used to indicate that it is a footer node. The H field can also be represented by 1 bit, for example, "0" is used to indicate that it is not a header node, and "1" is used to indicate that it is a header node. The width of the NPTR field is determined by the depth of the storage unit shared by each linked list. For example, when the total number of available storage spaces is 128, the length of the fourth indication information may be 7 bits, and when the total number of available storage spaces is 256, the length of the fourth indication information may be is 8 bits. If the node is the tail node of the linked list, the content of the NPTR field in the node is not concerned. After a new node is linked to the current tail node of the linked list, the NPTR field of the current tail node may be updated based on the address of the storage unit in which the new node is stored.

Through the above expansion, it provides a basis for storing transaction requests as a linked list. When a new transaction request needs to be stored, the first linked list to be stored for the first transaction request and the current tail node of the first linked list can be determined according to the information stored in the storage unit. If the insertion of the first transaction request is detected, a new node is created for the first transaction request, the storage unit corresponding to the created node is determined, and the created node is linked to the current tail node of the first linked list. When determining the footer node, the first indication information, the second indication information and the label information stored in each of the plurality of storage units may be queried in parallel to determine whether the first linked list is empty, and to determine whether the first linked list is empty. The first storage unit corresponding to the current footer node.

The information of the first transaction request included in the created node may be stored in an invalid storage unit in the plurality of storage units according to the first indication information stored in each of the plurality of storage units , the invalid storage unit is the storage unit corresponding to the created node. In some embodiments, the created node may be randomly stored in any invalid storage unit among the plurality of invalid storage units. In other embodiments, the created node may be stored in the lowest numbered invalid storage location. In still other embodiments, the created node may be stored in the highest numbered invalid storage unit. This disclosure does not limit this.

Optionally, the tag xID in each storage unit can be compared with the tag requested by the first transaction to obtain a comparison result. For example, if the two tags are the same, the comparison result may be 1, and if the two tags are different, the comparison result may be 0. According to the first indication information stored in each storage unit, the comparison result of each storage unit, and the second indication information of each storage unit, logical operations, such as logical AND operation, are respectively performed, thereby obtaining the footer node.

After the tail node is determined, when the first linked list is not empty, the created node may be linked to the current tail node of the first linked list in the following manner. For example, the fourth indication information of the first storage unit may be updated to the information of the created node, that is, the storage unit corresponding to the created node. In addition, the second indication information of the first storage unit may be updated to a first indication state, where the first indication state indicates that the corresponding node is not the tail node of the linked list to which it belongs. Assuming that the first linked list currently includes N nodes, and node N is the current tail node of the first linked list, after the created node is linked to the tail node of the first linked list, node N is no longer a member of the first linked list. The end node of the table is reached. Therefore, the second indication information corresponding to the node N can be updated to the first indication state. Further, the second indication information in the storage unit corresponding to the created node may be set to a second indication state, and the second indication state indicates that the corresponding node is the tail node of the linked list to which it belongs. Assuming that the first linked list currently includes N nodes, and node N is the current tail node of the first linked list, after the created node is linked to the tail node of the first linked list, the created node becomes the first linked list Therefore, the second indication information corresponding to the created node can be updated to the second indication state.

Through the above method, each transaction request can be stored in each node of the linked list in the order in which it is detected, so that when extracting the information of the transaction request, only the header node of the linked list can be found, and then the data can be extracted from the header node. Information about the transaction request.

The specific execution process of determining the table footer and linking the node to the table footer node is as follows.

(1) Based on the V field in each flip-flop storage array row, determine the location where the first transaction request tagged as xIDn needs to be stored by means of low (high) bit priority decoding.

(2) Based on the parallel polling method, find the tail node of the linked list corresponding to xIDn.

(3) The middle NPTR field of the table footer node of the update xIDn transaction request is a storage unit for storing the node corresponding to the first transaction request, and the T field of the current table footer node is set to 0 at the same time.

(4) Based on the information requested by the first transaction, update the content of the corresponding storage unit, set the V field of the node corresponding to the first transaction request to 1, set the T field to 1, and do not update the NPTR field.

In practical applications, the implementation method of the above step (1) has been described above, and will not be repeated here. And step (2) can be realized by the following way: compare the label stored in each storage unit and the first label of the first transaction request respectively, obtain the first comparison result, compare the first indication information of each storage unit, the first label of the first transaction request. The second indication information and the first comparison result are respectively logically ANDed to obtain the operation result, the position of "1" in the operation result is determined, and the end node of the table is determined according to the position of "1". Specifically, a one-dimensional array V can be generated from the first indication information corresponding to each node. The length of the one-dimensional array V is 128, and each element in the array is 1 or 0, which are respectively used to store the corresponding The storage unit is or is not a valid storage unit. Similarly, a one-dimensional array T can be generated from the second indication information corresponding to each node, the length of the one-dimensional array T is 128, and each element in the array is 1 or 0, which are used to indicate whether the corresponding node is or not. Footer node. A first comparison result is obtained by comparing the tag carried in each node with the tag of the transaction request, and the first comparison result is also represented by a one-dimensional first comparison array, and the length of the one-dimensional first comparison array is 128. An AND operation is performed on the one-dimensional first comparison array, the one-dimensional array V, and the one-dimensional array T, and the end node of the table can be determined according to the position of 1 in the operation result of the AND operation. If the linked list corresponding to the first transaction request exists, that is, if it is not empty, the operation result is a 128-bit one-hot code, and the position of "1" is the 127th bit at the maximum, and the minimum is The 0th bit; when the linked list corresponding to the transaction request does not exist, that is, when it is empty, the operation result is a value of all 0s, and the address of the tail node obtained in step (2) can be used as one 7-bit pointer to represent. The process of obtaining the 7-bit pointer through arithmetic operation is as follows:

When the first linked list is not empty, subtract 1 from the operation result of the AND operation to obtain the first operation result. Then, in the first operation result, the bit corresponding to "1" in the one-hot code and the value higher than the bit are all 0, and the bits lower than the one-hot code "1" are all 1. Each bit in the first operation result is summed to obtain the position of "1" in the one-hot code, and the final bit of "1" is the position of the storage unit where the tail node is located. For example, 28 is obtained after addition, which means that there are 28 "1"s in the first operation result, which further indicates that the position of "1" in the one-hot code is the 28th bit, which means that the 28th storage unit stores as The tail node of the first target linked list. In this way, the address of the first storage unit corresponding to xIDn is obtained, and the address can be represented by a 7-bit pointer.

If the operation result is not a one-hot code, but a 0 value, when the first linked list is empty. In this case, subtract 1 from the operation result, that is, the 128-bit value of all 0s, to obtain the first operation result, which is the 128-bit value of all "1", and add 128 "1"s 128 is obtained. For a 7-bit pointer, if the high bit overflows, each bit in the 7-bit pointer is 0, that is, the value of the 7-bit pointer is 0. Since the first operation result after subtracting 1 from the one-hot code [0 0 0... 0. Therefore, when the 7-bit pointer is 0, it will correspond to the above two situations, resulting in a conflict. In order to resolve the conflict, when filling the linked list with a 7-bit pointer with a value of 0, it is necessary to compare the operation result with 128-bit 0. If the two are different, it is determined that the node indicated by the 7-bit pointer is a one-hot code [0 0 0 ... 0 1] corresponds to the node. If the two are the same, it is determined that the operation result is a 0 value, thereby determining that the first linked list is empty. In this case, the above-mentioned step (3) may not be performed, and the above-mentioned step (4) may be directly performed. In addition, in step (4), it is also necessary to set the third indication information in the storage unit corresponding to the created node to a third indication state, wherein the third indication state is used to indicate that the corresponding node belongs to the linked list header node.

In some embodiments, the method provided by the present disclosure further includes: in the case of detecting the extraction of the first transaction request, obtaining a first tag of the first transaction request; based on the first tag of the first transaction request, Extracting the information of the first transaction request from the header node of the first linked list.

Similarly, when the transaction information of xIDn needs to be extracted, the first indication information, the third indication information and the label information stored in each of the multiple storage units can be queried in parallel to determine the current header of the first linked list The second storage unit corresponding to the node then extracts the transaction information of xIDn from the information requested by the system bus transaction in the second storage unit, and changes the indication information in the storage unit involved in the operation. The specific implementation process is as follows.

(1) Based on the parallel polling method, find the second storage unit where the header node of the linked list of the first transaction request with the label xIDn is located.

(2) Extract the information of the transaction request with the label xIDn from the second storage unit, and obtain the position of the next node through the NPTR field, and set the V field of the second storage unit of the extracted information to 0, and the H field Set to 0.

(3) Update the H field of the next node to 1, indicating that the next node is the head node of the linked list corresponding to xIDn.

In practical applications, step (1) can be implemented in the following manner: comparing the tags of each storage unit and the first tag of the first transaction request respectively, obtaining a second comparison result, and comparing the stored first indication information, The three indication information and the second comparison result are respectively ANDed to obtain an initial operation result, the position of "1" in the initial operation result is determined, and the header node is determined according to the position of "1". For example, 1 is subtracted from the initial operation result to obtain a second operation result; each bit in the second operation result is summed; and the second storage unit is determined according to the summation result. Specifically, the second storage unit corresponding to the header node may be determined by referring to the method of determining the first storage unit corresponding to the footer node, which will not be further described here.

The method provided by the present disclosure judges the earliest transaction request in the same xIDn (transaction tag with xID n) transaction request according to the header node of the linked list, and avoids obtaining the earliest transaction request by comparing the value of the real-time counter of the timestamps of each transaction request. Transaction requests, thus saving a lot of computational logic.

The process of inserting and extracting transaction requests is shown in Figure 3. Based on the design and implementation of a multi-linked list structure with shared storage, it is mainly composed of a storage unit 310 and two parallel polling modules, including one for inserting detected transaction requests into the linked list. The insert polling module 321, and a delete polling module 322 for extracting transaction request information from the linked list. The deletion polling module 322 is configured to execute the method for extracting transaction request information from the linked list in any of the foregoing embodiments, and the insertion polling module 321 is configured to execute the method for extracting transaction request information from any of the foregoing embodiments. The method of inserting the information into the linked list. The specific insertion and extraction methods are detailed in the foregoing embodiments, which will not be repeated here.

The storage space of the embodiment of the present disclosure may be implemented by using a flip-flop storage array, the depth of the storage space may be 128, and the width is defined according to the bus protocol and statistical requirements. By designing the peripheral circuits of the memory array, such as the circuits associated with the insert polling module 321 and the delete polling module 322, the V domain, H domain, xID domain and T domain of the flip-flop memory array are accessed in a parallel traversal polling manner Part or all of the state in the domain, so as to determine the current tail node or head node of the first linked list. For the transaction request to write the linked list corresponding to xID (or create a new linked list corresponding to xID), and to read the linked list whose response transaction is xID, the parallel polling method is adopted. The logic design is shown in Figure 4, and its input is 128 bits. V-domain one-dimensional array, namely V[0:127], 128-bit node xID, namely xID[0:127]; and 128-bit T-domain one-dimensional array or H-domain one-dimensional array, namely T[0: 127] or H[0:127]. It should be noted that although xID is represented as [0:127] for simplicity, since the xID of each node is represented by multiple bits, the xID of a node is a multi-dimensional array. The judgment process is as follows (i takes value from 0 to 127):

(S1) Determine whether the data of the i-th row of the storage array is valid through V[i].

(S2) Determine whether the data in the i-th row of the storage array belongs to the linked list corresponding to xIDn by comparing whether the tag xIDn of the transaction request is equal to the xID[i] of the node.

(S3) Determine whether the i-th row data of the storage array is the tail node of the linked list through T[i], or determine whether the i-th row data of the storage array is the head node of the linked list through H[i].

(S4) After the above three steps, a 128-bit one-hot code or an all-zero value is obtained, and each bit is recorded as Bit[0], Bit[1], . . . , Bit[127]. The position of 1 in the one-hot code, that is, the tail node of the linked list to be inserted or the head node of the linked list to be extracted.

(S5) Based on the 128-bit one-hot code or 0 value, a subtraction operation is performed, and the obtained 128-bit Bit[0]', Bit[1]', ..., Bit[127]' are accumulated, that is, 7 The head pointer or the tail pointer PTR[6:0] of the linked list of bits. The value of the pointer ranges from 0 to 127. The pointer indicates the address/location of the head node or the tail node.

It should be noted that, the execution sequence of the above steps (S1) to (S3) is only for illustration, which is not limited in the present disclosure.

Based on the design and implementation of this method, it can support the statistics of delay information of different xIDs, and support the statistics of different types of transaction requests. The hardware design requires less storage and less computing delay.

As shown in FIG. 5 , an embodiment of the present disclosure further provides a data processing method for system chip performance monitoring, and the method includes the following steps.

Step 501: In the case of detecting the first transaction request, create a first node in the first linked list for the first transaction request.

Step 502 : Store the information requested by the first transaction in a storage unit allocated for the first node, wherein at least two nodes of the linked list share a plurality of storage units.

In some embodiments, the number of the plurality of storage units is equal to the maximum number of unacknowledged transaction requests supported in the bus protocol included in the system chip.

In some embodiments, each storage unit is used to store one node of the linked list, and the number of storage units allocated to the first linked list matches the number of nodes currently included in the first linked list.

In some embodiments, the storage unit storage allocated for the first node includes the following indication information: first indication information for indicating whether the storage unit is a valid storage unit, for indicating whether the first node is a valid storage unit The second indication information of the tail node of the first linked list is used to indicate whether the first node is the head node of the first linked list. The third indication information is used to indicate that the first node is used to store the first The fourth indication information of the storage unit of the next node of the node.

In some embodiments, the storage unit allocated for the first node further stores the tag of the transaction request and the information of the system bus transaction request.

In some embodiments, the method further includes: querying the first indication information, the second indication information and the label information stored in each of the plurality of storage units in parallel to determine the current tail node of the first linked list and/or query the first indication information, the third indication information and the label information stored in each of the plurality of storage units in parallel to determine the current header node of the first linked list.

In some embodiments, the method further includes: allocating an invalid storage unit of the plurality of storage units to the first node based on the first indication information stored in the plurality of storage units.

In some embodiments, the method further includes: querying the first indication information stored in the plurality of storage units respectively, so as to determine the invalid storage unit from the plurality of storage units, the first indication information of the storage unit is to indicate whether the storage unit is a valid storage unit.

In some embodiments, each linked list includes at least one node for storing information about a transaction request with a tag. For example, the linked list 1 is used to store the information of the transaction request with the tag xID1, and the linked list 2 is used to store the information of the transaction request with the tag xID2.

In some embodiments, the information of the multiple transaction requests with the first tag is sequentially stored in each node of the first linked list according to the time when the multiple transaction requests are detected; and/or the information with the first tag is The information of multiple transaction requests of a tag is sequentially extracted according to the sequence of the multiple transaction requests in the first linked list.

In some embodiments, the number of nodes currently included in the first linked list is the number of currently unanswered transaction requests with the first label.

In some embodiments, the creating a first node for the first transaction request in the first linked list includes: creating a new node for the first transaction request; linking the created node to the first linked list The current footer node.

In some embodiments, the linking the created node to the current tail node of the first linked list includes: querying in parallel the first indication information, all the stored information stored in each of the plurality of storage units The second indication information and the label are used to determine whether the first linked list is empty and the first storage unit corresponding to the current tail node of the first linked list; when the first linked list is not empty , update the fourth indication information corresponding to the first storage unit to the storage unit of the created node; when the first linked list is not empty, update the second storage unit of the first first storage unit The indication information is updated to the first indication state, wherein the first indication state of the second indication information is used to indicate that the corresponding node is not the tail node of the linked list to which it belongs; the second indication information in the storage unit corresponding to the created node is It is set to the second indication state, and the second indication state of the second indication information is used to indicate that the corresponding node is the tail node of the linked list to which it belongs.

In some embodiments, the method further comprises: in the case of detecting the extraction of the first transaction request, obtaining a first tag of the first transaction request; based on the first tag of the first transaction request, The information of the first transaction request is extracted from the header node of the first linked list.

In some embodiments, extracting the information of the first transaction request from the header node of the first linked list includes: including: querying the first data stored in each of the plurality of storage units in parallel The indication information, the third indication information and the label are used to determine the second storage unit corresponding to the current header node of the first linked list; extracted from the information of the system bus transaction request in the second storage unit the information requested by the first transaction; the first indication information for updating the storage unit is a fourth indication state, wherein the fourth indication state is used to indicate that the second storage space is an invalid storage space; The third indication information of the second storage unit is updated to a fifth indication state, wherein the fifth indication state of the third indication information is used to indicate that the corresponding node is not the head node of the linked list to which it belongs; the fourth indication information, determine the storage unit corresponding to the next node of the current header node, and update the third indication information in the determined storage unit to the third indication state, the third indication information The third indication state is used to indicate that the corresponding node is the head node of the linked list to which it belongs.

For details of each step in this method embodiment, refer to the previous method embodiment, which is not repeated here.

Those skilled in the art can understand that in the above method of the specific implementation, the writing order of each step does not mean a strict execution order but constitutes any limitation on the implementation process, and the specific execution order of each step should be based on its function and possible Internal logic is determined.

As shown in FIG. 6 , the present disclosure further provides a data processing apparatus for system chip performance monitoring, the apparatus includes: a controller module 330 , an insertion polling module 321 and a linked list storage unit 310 . Wherein, the controller module 330 is respectively connected to the insert polling module 321 and the linked list storage unit 310 , and the linked list storage unit 310 is connected to the insert polling module 321 . The controller module 330 is configured to acquire information of the first transaction request when the first transaction request is detected, where the information includes the first tag of the first transaction request. The insertion polling module 321 is configured to store the information of the first transaction request in the first linked list corresponding to the first tag in the linked list storage unit 310 based on the first tag of the first transaction request, Wherein, the first linked list includes at least one node, and a storage unit corresponding to each node of the first linked list stores information of a transaction request with the first label.

In some embodiments, the information of the multiple transaction requests with the first tag is sequentially stored in each node of the first linked list according to the time when the multiple transaction requests are detected; and/or the information with the first tag is The information of multiple transaction requests of a tag is sequentially extracted according to the sequence of the multiple transaction requests in the first linked list.

In some embodiments, the number of nodes currently included in the first linked list is the number of currently unanswered transaction requests with the first label; and/or the information of transaction requests with different labels is stored in different in the linked list.

In some embodiments, the nodes of at least two linked lists share a plurality of storage units, wherein each storage unit is used to store one node of the linked list, and each storage unit includes a tag of a transaction request, information of a system bus transaction request, and the following Indication information: the first indication information used to indicate whether the storage unit is a valid storage unit, the second indication information used to indicate whether the current node is the tail node of the linked list to which it belongs, and the second indication information used to indicate whether the current node is a table of the linked list to which it belongs The third indication information of the head node is used to indicate the fourth indication information of the address of the storage unit that stores the next node of the current node, wherein the current node is the node corresponding to the storage unit.

In some embodiments, the apparatus further includes: an allocation module, the allocation module is connected to the controller module and the linked list storage unit, and the allocation module is configured to store the information requested by the first transaction when When reaching the first linked list, allocate storage units to the nodes corresponding to the first transaction request, so that the number of storage units allocated to the first linked list is equal to the number of nodes currently included in the first linked list. match.

In some embodiments, the allocation module is further configured to create a new node for the first transaction request, and determine a storage unit corresponding to the created node; the insertion polling module is further configured to modify the storage unit in the linked list The indication information of the corresponding storage unit, so as to link the created node to the current tail node of the first linked list.

In some embodiments, the insert polling module is further configured to: query the first indication information, the second indication information and the tag stored in each of the plurality of storage units in parallel, so as to Determine whether the first linked list is empty and the first storage unit corresponding to the current tail node of the first linked list; when the first linked list is not empty, store the first storage unit in the first storage unit 4. The indication information is updated to the storage unit corresponding to the created node; when the first linked list is not empty, the second indication information in the first storage unit is updated to the first indication state, wherein the The first indication state is used to indicate that the corresponding node is not the tail node of the linked list; the second indication information in the storage unit corresponding to the created node is set to the second indication state, and the second indication state is used to indicate that the corresponding The node is the tail node of the linked list to which it belongs.

In some embodiments, the insert polling module is further configured to compare the tags stored in the plurality of storage units with the first tags of the first transaction request, respectively, to obtain the first tags of the plurality of storage units. a comparison result; respectively perform logical operations on the first indication information, the second indication information and the first comparison result stored in the plurality of storage units to determine whether the first linked list is empty and the first storage unit.

In some embodiments, the insert polling module is further configured to perform a logical AND operation on the first indication information, the second indication information and the first comparison result stored in the plurality of storage units, respectively, Obtain an operation result; subtract 1 from the operation result to obtain a first operation result; sum each bit in the first operation result; determine whether the first linked list is at least according to the summation result empty and the first storage unit.

In some embodiments, the operation result is a one-hot code or an all-zero value.

In some embodiments, the insert polling module is further configured to, when the result of the summation is not 0, determine that the address of the first storage unit is equal to the result of the summation, and determine the first The linked list is not empty; when the result of the summation is equal to 0, the operation result is compared with 0, and if the operation result is different from 0, it is determined that the address of the first storage unit is equal to the summation As a result, it is determined that the first linked list is not empty.

In some embodiments, the insertion polling module is further configured to, if the operation result is the same as 0, determine that the first linked list is empty, and set the third indication information in the storage unit corresponding to the created node is a third indication state, wherein the third indication state is used to indicate that the corresponding node is the head node of the linked list to which it belongs.

In some embodiments, the allocating module is further configured to store, according to the first indication information stored in each of the plurality of storage units, the information of the first transaction request included in the created node to in an invalid storage unit of the plurality of storage units.

In some embodiments, the apparatus further includes a deletion polling module 322 , and the deletion polling module 322 is connected to the controller module 330 and the linked list storage unit 310 . The controller module 330 is further configured to obtain the first tag of the first transaction request in the case of detecting the extraction of the first transaction request; the deletion polling module 322 is configured to obtain the first tag of the first transaction request based on the The first tag extracts the information of the first transaction request from the header node of the first linked list in the linked list storage unit 310 .

In some embodiments, the deletion polling module is further configured to query the first indication information, the third indication information and the label stored in each of the plurality of storage units in parallel to determine the the second storage unit corresponding to the current header node of the first linked list; extract the information of the first transaction request from the information of the system bus transaction request in the second storage unit; update the second storage unit The first indication information in is a fourth indication state, wherein the fourth indication state is used to indicate that the second storage space is an invalid storage space; update the third indication information in the second storage unit to the first Five indication states, wherein the fifth indication state is used to indicate that the corresponding node is not the header node of the linked list; according to the fourth indication information in the second storage unit, determine the next one of the current header node The storage unit corresponding to the node, and the third indication information in the determined storage unit is updated to a third indication state, where the third indication state is used to indicate that the corresponding node is the head node of the linked list to which it belongs.

In some embodiments, the deletion polling module is further configured to compare the tags stored in the plurality of storage units with the first tags of the first transaction request, respectively, to obtain the first tags of the plurality of storage units. 2. Comparison results; respectively perform logical operations on the first indication information, the third indication information and the second comparison results stored in the plurality of storage units to determine the second storage unit.

In some embodiments, the deletion polling module is further configured to perform a logical AND operation on the first indication information, the third indication information and the second comparison result stored in the plurality of storage units, respectively, Obtain an initial operation result; subtract 1 from the initial operation result to obtain a second operation result; sum each bit in the second operation result; determine the second storage unit according to the summation result .

In some embodiments, the number of the plurality of storage units is equal to the maximum number of unacknowledged transaction requests supported by the bus protocol.

As shown in FIG. 7 , the present disclosure also provides a data processing apparatus for system chip performance monitoring, the apparatus includes: a creation module 701 for, when a first transaction request is detected, in the first linked list creating a first node for the first transaction request; a storage module 702, configured to store the information of the first transaction request in a storage unit allocated for the first node, wherein the nodes of at least two linked lists share the same multiple storage units.

In some embodiments, each storage unit is used to store one node of the linked list, and the number of storage units allocated to the first linked list matches the number of nodes currently included in the first linked list.

In some embodiments, the storage unit allocated to the first node stores the following indication information: first indication information used to indicate whether the storage unit is a valid storage unit, used to indicate whether the first node is a valid storage unit The second indication information of the tail node of the first linked list is used to indicate whether the first node is the head node of the first linked list. The third indication information is used to indicate that the first node is used to store the first The fourth indication information of the storage unit of the next node of the node.

In some embodiments, the apparatus further includes: a third query module, configured to query the first indication information, the second indication information and the label stored in each of the plurality of storage units in parallel, so as to determine the first indication information the current tail node of the linked list; and/or a fourth query module, configured to query the first indication information, the third indication information and the label stored in each storage unit in the plurality of storage units in parallel, so as to determine the current state of the first linked list the header node.

In some embodiments, the apparatus further includes: an allocation module configured to allocate an invalid storage unit in the plurality of storage units to the first node based on the first indication information stored in the plurality of storage units .

In some embodiments, the functions or modules included in the apparatuses provided in the embodiments of the present disclosure may be used to execute the methods described in the above method embodiments. For specific implementation, reference may be made to the descriptions of the above method embodiments. For brevity, here No longer.

Part or all of each module and unit of the above device can also be implemented by being embedded on a certain chip in the form of an integrated circuit. And they can be implemented individually or integrated together. That is, the above modules and units can be configured as one or more integrated circuits that implement the above methods, such as: one or more specific integrated circuits (Application Specific Integrated Circuit, ASIC), or one or more microprocessors (Digital Singnal Processor, DSP), or, one or more Field Programmable Gate Array (Field Programmable Gate Array, FPGA), etc.

The embodiments of the present specification further provide a computer device, which at least includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the foregoing embodiments when executing the program. method described.

FIG. 8 shows a more specific schematic diagram of the hardware structure of a computer device provided by an embodiment of this specification. The device may include: a processor 801 , a memory 802 , an input/output interface 803 , a communication interface 804 and a bus 805 . The processor 801 , the memory 802 , the input/output interface 803 and the communication interface 804 realize the communication connection among each other within the device through the bus 805 .

The processor 801 can be implemented by a general-purpose CPU (Central Processing Unit, central processing unit), a microprocessor, an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, etc. program to implement the technical solutions provided by the embodiments of this specification.

The memory 802 can be implemented in the form of a ROM (Read Only Memory, read-only memory), a RAM (Random Access Memory, random access memory), a static storage device, a dynamic storage device, and the like. The memory 802 may store an operating system and other application programs. When implementing the technical solutions provided by the embodiments of this specification through software or firmware, relevant program codes are stored in the memory 802 and invoked by the processor 801 for execution.

The input/output interface 803 is used for connecting input/output modules to realize information input and output. The input/output/module can be configured in the device as a component (not shown in the figure), or can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, and the like.

The communication interface 804 is used to connect a communication module (not shown in the figure), so as to realize the communication interaction between the device and other devices. The communication module may implement communication through wired means (eg, USB, network cable, etc.), or may implement communication through wireless means (eg, mobile network, WIFI, Bluetooth, etc.).

Bus 805 includes a path to transfer information between the various components of the device (eg, processor 801, memory 802, input/output interface 803, and communication interface 804).

It should be noted that although the above-mentioned device only shows the processor 801, the memory 802, the input/output interface 803, the communication interface 804 and the bus 805, in the specific implementation process, the device may also include necessary components for normal operation. other components. In addition, those skilled in the art can understand that, the above-mentioned device may only include the components necessary to realize the solutions of the embodiments of the present specification, and does not necessarily include all the components shown in the figures.

An embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, implements the method described in any of the foregoing embodiments.

Computer-readable media includes both persistent and non-permanent, removable and non-removable media, and storage of information may be implemented by any method or technology. Information may be computer readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read only memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), Flash Memory or other memory technology, Compact Disc Read Only Memory (CD-ROM), Digital Versatile Disc (DVD) or other optical storage, Magnetic tape cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media, such as modulated data signals and carrier waves.

From the description of the above embodiments, those skilled in the art can clearly understand that the embodiments of the present specification can be implemented by means of software plus a necessary general hardware platform. Based on such understanding, the technical solutions of the embodiments of this specification or the parts that make contributions to the prior art may be embodied in the form of software products, and the computer software products may be stored in storage media, such as ROM/RAM, A magnetic disk, an optical disk, etc., includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments in this specification.

The systems, devices, modules or units described in the above embodiments may be specifically implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer, which may be in the form of a personal computer, laptop computer, cellular phone, camera phone, smart phone, personal digital assistant, media player, navigation device, e-mail device, game control desktop, tablet, wearable device, or a combination of any of these devices.

Each embodiment in this specification is described in a progressive manner, and the same and similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the apparatus embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and reference may be made to the partial description of the method embodiment for related parts. The device embodiments described above are only illustrative, wherein the modules described as separate components may or may not be physically separated. When implementing the solutions of the embodiments of the present specification, the functions of each module may be integrated into the same module. or multiple software and/or hardware implementations. Some or all of the modules may also be selected according to actual needs to achieve the purpose of the solution in this embodiment. Those of ordinary skill in the art can understand and implement it without creative effort.

The above are only specific implementations of the embodiments of the present specification. It should be pointed out that for those skilled in the art, without departing from the principles of the embodiments of the present specification, several improvements and modifications can be made. These Improvements and modifications should also be regarded as the protection scope of the embodiments of the present specification.

Claims (25)

1. A data processing method for system chip performance monitoring, characterized in that the method comprises:

   In the case of detecting the first transaction request, obtain information of the first transaction request, the information including the first tag of the first transaction request;

   Based on the first tag of the first transaction request, the information of the first transaction request is stored in a first linked list corresponding to the first tag, wherein the first linked list includes at least one node, and the A storage unit corresponding to each node of the first linked list stores information of a transaction request with the first label.
2. The method of claim 1, wherein:

   The information of the multiple transaction requests with the first label is sequentially stored in the storage units corresponding to each node of the first linked list according to the time when the multiple transaction requests are detected; and/or

   The information of the multiple transaction requests with the first tag is sequentially extracted according to the sequence of the multiple transaction requests in the first linked list.
3. The method according to claim 1 or 2, characterized in that,

   The number of nodes currently included in the first linked list is the number of currently unanswered transaction requests with the first label; and/or

   Information for transaction requests with different labels is stored in different linked lists.
4. The method according to any one of claims 1 to 3, characterized in that:

   The nodes of at least two linked lists share a plurality of storage units, wherein each storage unit is used to store a node of the linked list, and each storage unit includes the label of the transaction request, the information of the system bus transaction request and the following indication information: used to indicate The first indication information for whether the storage unit is a valid storage unit, the second indication information for indicating whether the current node is the tail node of the linked list to which it belongs, and the third indication information for indicating whether the current node is the head node of the linked list to which it belongs information, which is used to indicate fourth indication information that stores the address of the storage unit of the next node of the current node, where the current node is the node corresponding to the storage unit.
5. The method according to claim 4, wherein the storing the information of the first transaction request in the first linked list based on the first tag of the first transaction request comprises:

   creating a new node for the first transaction request, and determining a storage unit corresponding to the created node;

   The created node is linked to the current tail node of the first linked list.
6. The method according to claim 5, wherein the linking the created node to the current tail node of the first linked list comprises:

   Querying the first indication information, the second indication information and the label stored in each of the plurality of storage units in parallel to determine whether the first linked list is empty and the current state of the first linked list The first storage unit corresponding to the footer node of ;

   When the first linked list is not empty, the fourth indication information in the first storage unit is updated to the storage unit corresponding to the created node;

   When the first linked list is not empty, the second indication information in the first storage unit is updated to a first indication state, where the first indication state is used to indicate that the corresponding node does not belong to the linked list footer node;

   The second indication information in the storage unit corresponding to the created node is set to a second indication state, where the second indication state is used to indicate that the corresponding node is the tail node of the linked list to which it belongs.
7. The method according to claim 6, wherein the determining whether the first linked list is empty and the first storage unit corresponding to the current tail node of the first linked list comprises:

   comparing the tags stored in the plurality of storage units with the first tags of the first transaction request, respectively, to obtain a first comparison result of the plurality of storage units;

   Perform logical operations on the first indication information, the second indication information, and the first comparison result stored in the plurality of storage units, respectively, to determine whether the first linked list is empty and whether the first storage unit is empty .
8. The method according to claim 7, wherein the determining whether the first linked list is empty and the first storage unit comprises:

   Perform a logical AND operation on the first indication information, the second indication information and the first comparison result stored in the plurality of storage units, respectively, to obtain an operation result;

   Subtract 1 from the operation result to obtain the first operation result;

   summing each bit in the first operation result;

   Whether the first linked list is empty and the first storage unit is determined at least according to the result of the summation.
9. The method according to claim 8, wherein the operation result is a one-hot code or an all-zero value.
10. The method according to claim 8, wherein the determining whether the first linked list is empty and the first storage unit comprises at least according to the result of the summation:

    When the result of the summation is not 0, determine that the address of the first storage unit is equal to the result of the summation, and determine that the first linked list is not empty;

    When the result of the summation is equal to 0, the result of the operation is compared with 0, and if the result of the operation is different from 0, it is determined that the address of the first storage unit is equal to the result of the summation, and it is determined that the The first linked list is not empty.
11. The method of claim 10, wherein the method further comprises:

    If the operation result is the same as 0, it is determined that the first linked list is empty, and the third indication information in the storage unit corresponding to the created node is set to a third indication state, wherein the third indication state uses Indicates that the corresponding node is the head node of the linked list to which it belongs.
12. The method according to claim 5, wherein the determining the storage unit corresponding to the created node comprises:

    According to the first indication information stored in each of the plurality of storage units, the information of the first transaction request included in the created node is stored in an invalid storage unit of the plurality of storage units .
13. The method according to claim 4, wherein the method further comprises:

    In the case of detecting the extraction of the first transaction request, acquiring the first tag of the first transaction request;

    Based on the first tag of the first transaction request, the information of the first transaction request is extracted from the header node of the first linked list.
14. The method according to claim 13, wherein the extracting the information of the first transaction request from the header node of the first linked list comprises:

    Querying the first indication information, the third indication information and the label stored in each of the plurality of storage units in parallel to determine the second storage corresponding to the current header node of the first linked list unit;

    Extract the information of the first transaction request from the information of the system bus transaction request in the second storage unit;

    updating the first indication information in the second storage unit to a fourth indication state, wherein the fourth indication state is used to indicate that the second storage space is an invalid storage space;

    updating the third indication information in the second storage unit to a fifth indication state, wherein the fifth indication state is used to indicate that the corresponding node is not the header node of the linked list to which it belongs;

    According to the fourth indication information in the second storage unit, determine the storage unit corresponding to the next node of the current header node, and update the third indication information in the determined storage unit to a third indication state , and the third indication state is used to indicate that the corresponding node is the head node of the linked list to which it belongs.
15. The method according to claim 14, wherein the determining the second storage unit corresponding to the current header node of the first linked list comprises:

    respectively comparing the tags stored in the plurality of storage units with the first tags requested by the first transaction to obtain second comparison results of the plurality of storage units;

    The second storage unit is determined by performing logical operations on the first indication information, the third indication information and the second comparison result stored in the plurality of storage units respectively.
16. The method according to claim 15, wherein the determining the second storage unit comprises:

    Perform a logical AND operation on the first indication information, the third indication information and the second comparison result stored in the plurality of storage units respectively to obtain an initial operation result;

    Subtract 1 from the initial operation result to obtain a second operation result;

    summing each bit in the second operation result;

    The second storage unit is determined according to the result of the summation.
17. The method according to claim 4, wherein the number of the plurality of storage units is equal to the maximum number of unanswered transaction requests supported in a bus protocol included in the system chip.
18. A data processing method for system chip performance monitoring, characterized in that the method comprises:

    In the case of detecting the first transaction request, creating a first node in the first linked list for the first transaction request;

    The information requested by the first transaction is stored in a storage unit allocated for the first node, wherein the nodes of at least two linked lists share a plurality of storage units.
19. The method according to claim 18, wherein each storage unit is used to store a node of the linked list, and the number of storage units allocated to the first linked list is the same as the number of nodes currently included in the first linked list match.
20. The method according to claim 18 or 19, wherein the storage unit allocated for the first node stores the following indication information:

    the first indication information for indicating whether the storage unit is a valid storage unit,

    second indication information for indicating whether the first node is the tail node of the first linked list,

    third indication information for indicating whether the first node is the header node of the first linked list,

    Fourth indication information for indicating a storage unit for storing the next node of the first node.
21. The method of claim 20, wherein the method further comprises:

    Query the first indication information, the second indication information and the label stored in each storage unit in the plurality of storage units in parallel to determine the current tail node of the first linked list; and/or

    The first indication information, the third indication information and the label stored in each of the plurality of storage units are queried in parallel to determine the current head node of the first linked list.
22. The method according to claim 20 or 21, wherein the method further comprises:

    Based on the first indication information stored in the plurality of storage units, an invalid storage unit in the plurality of storage units is allocated to the first node.
23. A data processing device for system chip performance monitoring, characterized in that the device comprises:

    a controller module, a plug-in polling module, and a linked list storage unit, wherein the controller module is respectively connected with the plug-in polling module and the linked list storage unit, and the linked list storage unit is connected with the plug-in polling module;

    the controller module, configured to acquire information of the first transaction request when the first transaction request is detected, the information including the first tag of the first transaction request;

    The insertion polling module is configured to, based on the first tag of the first transaction request, store the information of the first transaction request in the first linked list corresponding to the first tag in the linked list storage unit , wherein the first linked list includes at least one node, and a storage unit corresponding to each node of the first linked list stores information about a transaction request with the first label.
24. The device according to claim 23, wherein the device further comprises a deletion polling module, the deletion polling module is connected to the controller module and the linked list storage unit,

    The controller module is further configured to acquire the first tag of the first transaction request in the case of detecting the extraction of the first transaction request;

    The deletion polling module is configured to extract the information of the first transaction request from the header node of the first linked list in the linked list storage unit based on the first tag of the first transaction request.
25. A computer-readable storage medium on which a computer program is stored, characterized in that, when the program is executed by a processor, the method described in any one of claims 1 to 22 is implemented.

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