WO2022041768A1 - Split-gate flash memory device and preparation method therefor, and electronic device - Google Patents

Abstract

The present application relates to a split-gate flash memory device and a preparation method therefor, and an electronic device. The preparation method comprises: obtaining a substrate (102), on which a gate dielectric layer film (104) and a floating gate polycrystalline silicon film (106) are formed in sequence; forming a hard mask layer film (108) on the floating gate polycrystalline silicon film (106); etching the hard mask layer film (108) to form at least two openings (112) in a floating gate preset area (109), with part of the floating gate polycrystalline silicon film (106) being exposed via the openings (112); carrying out a thermal oxidation process to form a field oxide layer (204) in the floating gate polycrystalline silicon film (106) in the floating gate preset area (109), with the distance between the bottom of the field oxide layer (204) and the bottom of the floating gate polycrystalline silicon film (106) being not less than a preset distance; carrying out an etching process to remove the hard mask layer film (108) on the substrate (102), and the gate dielectric layer film (104) and the floating gate polycrystalline silicon film (106) outside the floating gate preset area (109), to obtain a floating gate structure (114) formed by the remaining gate dielectric layer film (104) and the remaining floating gate polycrystalline silicon film (106); and forming a tunnel oxide layer (116) on the substrate (102).

Description

Split-gate flash memory device, preparation method thereof, and electronic device

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of the Chinese patent application filed on August 31, 2020 with the application number of 2020108988221 and the invention titled "Split-gate flash memory device and its preparation method, and electronic equipment", the entire contents of which are by reference Incorporated in this application.

technical field

The present application relates to the field of semiconductor technology, in particular to a structure of a split-gate flash memory device and a preparation method thereof, and also to an electronic device.

Background technique

The statements herein merely provide background information related to the present application and do not necessarily constitute prior art.

Flash memory is a non-volatile memory whose operation principle is to control the switch of the gate channel by changing the threshold voltage of the transistor or memory cell to achieve the purpose of storing data, so that the data stored in the memory will not disappear due to power interruption. , and flash memory is a special structure of electrically erasable and programmable read-only memory.

Flash memory is a split gate structure, a stacked gate structure, or a combination of the two. Due to its special structure, the split-gate flash memory shows its unique performance advantages in programming and erasing compared with the stacked-gate flash memory. Therefore, the split-gate structure has high programming efficiency, and the structure of the word line can be avoided. Over-erasing” and other advantages are particularly widely used. The height and sharpness of the floating gate tip will affect the voltage coupled to the floating gate during programming and erasing, thereby affecting the performance of the flash memory during programming and erasing. Increasing the thickness of the field oxygen can make the floating gate tip sharper. However, the distance between the bottom of the center position of the floating gate and the bottom of the field oxygen is very small. Increasing the thickness of the field oxygen may cause the floating gate oxide to penetrate, and when the thickness of the floating gate is too small, it is not conducive to the writing of the split-gate flash memory device. During the storage of electrons, the performance of the device deteriorates.

SUMMARY OF THE INVENTION

According to various embodiments of the present application, a split-gate flash memory device and a method for fabricating the same are provided.

A preparation method of a split-gate flash memory device, comprising:

obtaining a substrate, on which a gate dielectric layer film and a floating gate polysilicon film are sequentially formed;

forming a hard mask layer film on the floating gate polysilicon film;

etching the hard mask layer film to form no less than two openings in the floating gate preset area, and the openings expose part of the floating gate polysilicon film;

performing a thermal oxidation process to form a field oxide layer in the floating gate polysilicon film in the floating gate preset area, and the distance between the bottom of the field oxide layer and the bottom of the floating gate polysilicon film is not less than a preset distance;

Perform an etching process to remove the hard mask layer film on the substrate, as well as the gate dielectric layer film and the floating gate polysilicon film outside the predetermined area of the floating gate, to obtain the remaining gate dielectric layer film and the remaining floating gate. A floating gate structure formed of a polysilicon film; and

A tunnel oxide film is formed on the substrate.

A split-gate flash memory device, comprising:

substrate;

a gate dielectric layer, located on the substrate;

a floating gate polysilicon layer on the gate dielectric layer;

a field oxide layer on the floating gate polysilicon layer, the field oxide layer is formed by a thermal oxidation process; and

a tunnel oxide layer, located on the field oxide layer and extending along the field oxide layer to the substrate on both sides of the floating gate polysilicon layer;

The distance between the bottom of the field oxide layer and the bottom of the floating gate polysilicon layer is not less than a preset distance; the longitudinal section of the contact surface between the field oxide layer and the floating gate polysilicon layer is a wavy shape with at least two troughs .

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features, objects and advantages of the present application will become apparent from the description, drawings and claims.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the traditional technology, the following briefly introduces the accompanying drawings that are used in the description of the embodiments or the traditional technology. Obviously, the drawings in the following description are only the For some embodiments of the application, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without any creative effort.

FIG. 1 is a flowchart of a method for fabricating a split-gate flash memory device provided in an embodiment;

FIG. 2 is a schematic cross-sectional view of the split-gate flash memory device after step S104 in an embodiment;

3 is a schematic cross-sectional view of the split-gate flash memory device after step S106 in an embodiment;

4 is a schematic cross-sectional view of the split-gate flash memory device after step S108 in an embodiment;

5 is a schematic cross-sectional view of a split-gate flash memory device after step S110 in an embodiment;

FIG. 6 is a schematic cross-sectional view of the split-gate flash memory device after step S112 in an embodiment.

detailed description

In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the related drawings. Embodiments of the present application are presented in the accompanying drawings. However, the application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application, such that variations in the shapes shown may be contemplated due, for example, to manufacturing techniques and/or tolerances. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation proceeds. Thus, the regions shown in the figures are schematic in nature and their shapes do not represent the actual shape of a region of a device and do not limit the scope of the present application.

The erasing mechanism of split-gate flash memory is to apply a high voltage on the select gate to tunnel electrons from the tip of the floating gate through the tunnel oxide layer to the select gate in a Fowler-Nordheim (FN) tunneling manner. , the larger the electric field, the smaller the potential barrier width, the easier the electrons can tunnel, and the better the erasing performance of the flash memory. The tip of the floating gate of the current structure is relatively blunt. Increasing the field oxygen can make the tip of the floating gate sharper, but the center of the floating gate is very thin. Continuing to increase the field oxygen may oxidize and penetrate the floating gate polysilicon. Too thin field oxygen is not conducive to separation. The storage of electrons when the gate flash memory is written will cause the performance of the split gate flash memory to deteriorate, and may lead to device failure in severe cases.

As shown in FIG. 1, in one embodiment, a method for preparing a split-gate flash memory device is provided, including:

S102 , obtaining a substrate, on which a gate dielectric layer film and a floating gate polysilicon film are sequentially formed.

As shown in FIG. 2 , a substrate 102 is obtained, and a gate dielectric layer film 104 and a floating gate polysilicon film 106 are sequentially formed on the substrate 102 .

The substrate 102 can be monocrystalline silicon, polycrystalline silicon or amorphous silicon; the substrate 102 can also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide; the substrate 102 can be a bulk material, It can also be a composite structure, such as silicon-on-insulator; the 102 can also be other semiconductor materials, which will not be exemplified here.

S104, forming a hard mask layer film on the floating gate polysilicon film.

A hard mask layer film 108 is formed on the floating gate polysilicon film 106 .

S106 , etching the hard mask layer thin film to form no less than two openings in the floating gate preset area.

As shown in FIG. 3 , the hard mask layer film 108 is etched to obtain a hard mask layer 202 composed of the remaining hard mask layer film 108 , and no less than two openings 112 are formed in the floating gate preset area 109 . The opening 112 exposes a portion of the floating gate polysilicon film 106 .

S108 , a thermal oxidation process is performed to form a field oxide layer in the floating gate polysilicon thin film in the floating gate preset area.

As shown in FIG. 4 , a thermal oxidation process is performed to form a field oxide layer 204 in the floating gate polysilicon film 106 in the floating gate pre-set region 109 , and the bottom of the field oxide layer 204 is connected to the bottom of the floating gate polysilicon film 106 . The distance between the bottoms is not less than the preset distance.

S110, obtaining a floating gate structure.

As shown in FIG. 5 , an etching process is performed to remove the hard mask layer film 108 on the substrate 102 , that is, the hard mask layer 202 on the substrate 102 and the floating gate preset region 109 are removed. The remaining gate dielectric layer 104 and the floating gate polysilicon film 106 are used to obtain a floating gate structure 114 composed of the remaining gate dielectric layer film 104 , namely the gate dielectric layer 206 , and the remaining floating gate polysilicon film 106 , namely the floating gate polysilicon layer 208 .

S112, forming a tunnel oxide layer on the substrate.

As shown in FIG. 6 , a tunnel oxide layer 116 is formed on the substrate 102 . The tunnel oxide layer 116 covers the surface of the field oxide layer 204 and extends down to the surface of the substrate 102 along the sidewall of the floating gate structure 114 .

As shown in FIG. 4 , the distance between the adjacent openings 112 needs to satisfy: after the field oxygen layer 204 is formed, the field oxygen layer 204 under the adjacent openings 112 is connected as a whole, and the dotted ellipse in FIG. Exemplary positions of the field oxide layer formed in the floating gate preset region 109, compared with the prior art, the present application forms no less than two openings 112 in the floating gate preset region 109 in the hard mask layer 202, Under the condition that the minimum distance between the bottom of the field oxide layer 204 and the bottom of the floating gate polysilicon film 106 remains unchanged, that is, the writing performance and reliability of the split-gate flash memory device are not changed, so that the floating gate polysilicon film 106 and the floating gate polysilicon film 106 are not changed. The tangent angle of the field oxide layer 204 in the edge region of the floating gate pre-set region 109 is smaller, and a sharper floating gate structure 114 is obtained later. When the device is erased, a larger electric field will be formed, and electrons are more conducive to Tunneling is performed to obtain a better erase performance.

In one embodiment, the gate dielectric layer film 104 includes an oxide layer film and a high-k gate dielectric layer film.

In one embodiment, the step of forming a shallow trench isolation structure is further included before forming the hard mask layer film 108 on the floating gate polysilicon film 106 .

In one embodiment, the hard mask layer film 108 includes at least one of a silicon nitride film, a silicon oxynitride film, a silicon oxycarbide film, a silicon carbonitride film, and a silicon oxycarbonitride film.

As shown in FIG. 2 and FIG. 3 , in one embodiment, the step of etching the hard mask layer film 108 to form no less than two openings 112 in the floating gate preset area 109 includes:

First, a first photoresist pattern 110 is formed on the hard mask layer film 108 , and the first photoresist pattern 110 exposes the hard mask layer film 108 in the predetermined opening area 111 in the floating gate predetermined area 109 .

Next, the hard mask layer film 108 in the predetermined opening area 111 is removed by etching, and the opening 112 is formed in the predetermined opening area 111 .

Thirdly, the first photoresist pattern 110 is removed. At this time, a schematic cross-sectional view of the split-gate flash memory device is shown in FIG. 3 .

In one embodiment, the openings 112 are evenly distributed in the floating gate predetermined region 109 .

In one embodiment, the openings 112 are symmetrically distributed in the floating gate predetermined region 109 with respect to the center line of the floating gate predetermined region 109 .

As shown in Figure 6, in one embodiment, the method further includes:

A select gate structure 118 is formed. The select gate structure 118 is located on the surface of the tunnel oxide layer 116 on one side of the floating gate structure 114 and extends along the tunnel oxide layer 116 to a part of the floating gate structure 114 .

The preparation method of the above-mentioned split-gate flash memory device, by forming no less than two openings exposing part of the floating gate polysilicon film in the floating gate preset area, and dividing the floating gate polysilicon film in the floating gate preset area into no less than 2 regions, and then a field oxide layer is formed in the floating gate polysilicon film in the floating gate preset region by a thermal oxidation process, and the distance between the bottom of the field oxide layer and the bottom of the floating gate polysilicon film is not less than the preset distance. The floating gate structure under the field oxide layer is obtained by an etching process. Compared with forming a field oxide layer in the floating gate polysilicon film in the floating gate preset area through a thermal oxidation process after forming an opening no less than a part of the floating gate polysilicon film in the floating gate preset area, the bottom of the field oxide layer and the floating gate Under the condition that the distance between the bottoms of the polysilicon films remains unchanged, the height and sharpness of the floating gate tip of the floating gate structure obtained in the present application are better, and when the erasing operation of the split-gate flash memory device is performed, a larger The electric field is more favorable for electrons to tunnel, thus obtaining a better erasing performance.

As shown in FIG. 6, in one embodiment, a split-gate flash memory device is provided, including:

substrate 102;

a gate dielectric layer 206, located on the substrate 102;

The floating gate polysilicon layer 208 is located on the gate dielectric layer 206;

a field oxide layer 204 on the floating gate polysilicon layer 208, the field oxide layer 204 is formed by a thermal oxidation process; and

The tunnel oxide layer 116 is located on the field oxide layer 204 and extends along the field oxide layer 204 to the substrate 102 on both sides of the floating gate polysilicon layer 208;

The distance between the bottom of the field oxide layer 204 and the bottom of the floating gate polysilicon layer 208 is not less than a preset distance; the longitudinal section of the contact surface between the field oxide layer 204 and the floating gate polysilicon layer 208 has at least two The wave shape of the trough, and the slope of the tangent line at the intersection of the wave shape and the tunnel oxide layer 116 is greater than a preset value; the preset value refers to the contact between the field oxide layer 204 and the floating gate polysilicon layer 208 When the longitudinal section of the surface is a parabola with a trough, the slope of the tangent at the intersection of the parabola and the tunnel oxide layer.

In one of the embodiments, the wave shape is symmetrical about the center line of the field oxygen layer 204 .

In one embodiment, the wave shape has two troughs, and the distances between the troughs and the bottom of the floating gate polysilicon layer 208 are equal.

In one embodiment, a selection gate structure 118 is further included, the selection gate structure 118 is located on the surface of the tunnel oxide layer 116 on one side of the floating gate polysilicon layer 208 and extends along the tunnel oxide layer 116 to a part of the on the floating gate polysilicon layer 208 .

In one of the embodiments, an electronic device is provided, and the electronic device includes the split-gate flash memory device described in any one of the above.

The above-mentioned split-gate flash memory device and electronic device include a substrate; a gate dielectric layer on the substrate; a floating gate polysilicon layer on the gate dielectric layer; and a field oxygen layer on the floating gate polysilicon layer , the field oxide layer is formed by a thermal oxidation process; a tunnel oxide layer is located on the field oxide layer and extends along the field oxide layer to the substrate on both sides of the floating gate polysilicon layer; wherein , the distance between the bottom of the field oxygen layer and the bottom of the floating gate polysilicon is not less than a preset distance; the longitudinal section of the contact surface between the field oxygen layer and the floating gate polysilicon layer is a wavy shape with at least two troughs , and the slope of the tangent line at the intersection of the wave shape and the tunnel oxide layer is greater than a preset value; the preset value means that the longitudinal section of the contact surface between the field oxide layer and the floating gate polysilicon layer has a When the trough is parabolic, the slope of the tangent at the intersection of the parabola and the tunnel oxide layer. In the present application, the longitudinal section of the contact surface between the field oxide layer and the floating gate polysilicon layer is a wave shape with at least two troughs, and the slope of the tangent at the intersection of the wave shape and the tunnel oxide layer is greater than the preset value, so that the gate dielectric layer and the The height and sharpness of the floating gate tip of the floating gate structure composed of the floating gate polysilicon layer are better. When the erase operation of the split-gate flash memory device is performed, a larger electric field will be formed, and the electrons are more conducive to tunneling, thereby obtaining A better erase performance.

It should be understood that although the various steps in the flowchart of FIG. 1 are shown in sequence according to the arrows, these steps are not necessarily executed in the sequence shown by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order, and these steps may be performed in other orders. Moreover, at least a part of the steps in FIG. 1 may include multiple steps or multiple stages, these steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution sequence of these steps or stages is also It does not have to be performed sequentially, but may be performed alternately or alternately with other steps or at least a portion of the steps or stages within the other steps.

Claims (15)

1. A preparation method of a split-gate flash memory device, comprising:

   obtaining a substrate, on which a gate dielectric layer film and a floating gate polysilicon film are sequentially formed;

   forming a hard mask layer film on the floating gate polysilicon film;

   etching the hard mask layer film to form no less than two openings in the floating gate preset area, and the openings expose part of the floating gate polysilicon film;

   performing a thermal oxidation process to form a field oxide layer in the floating gate polysilicon film in the floating gate preset area, and the distance between the bottom of the field oxide layer and the bottom of the floating gate polysilicon film is not less than a preset distance;

   Perform an etching process to remove the hard mask layer film on the substrate, as well as the gate dielectric layer film and the floating gate polysilicon film outside the predetermined area of the floating gate, to obtain the remaining gate dielectric layer film and the remaining floating gate. A floating gate structure formed of a polysilicon film; and

   A tunnel oxide layer is formed on the substrate.
2. The preparation method according to claim 1, wherein the openings are uniformly distributed in the predetermined area of the floating gate.
3. The manufacturing method according to claim 1, wherein the openings are symmetrically distributed in the predetermined floating gate area with respect to a center line of the predetermined floating gate area.
4. The preparation method according to claim 1, wherein the method further comprises:

   A select gate structure is formed, the select gate structure is located on the surface of the tunnel oxide layer on one side of the floating gate structure, and extends to a part of the floating gate structure along the tunnel oxide layer.
5. The preparation method according to claim 1, wherein the step of etching the hard mask layer film to form no less than 2 openings in the floating gate preset area comprises:

   forming a first photoresist pattern on the hard mask layer film, the first photoresist pattern exposing the hard mask layer film in the predetermined opening area in the floating gate predetermined area;

   Etching and removing the hard mask layer film in the predetermined opening area, and forming the opening in the predetermined opening area; and

   The first photoresist pattern is removed.
6. The preparation method according to claim 1, wherein the gate dielectric layer film comprises an oxide layer film and a high-k gate dielectric layer film.
7. The preparation method according to claim 4, wherein the step of forming a shallow trench isolation structure is further included before forming the hard mask layer film on the floating gate polysilicon film.
8. The preparation method according to claim 1, wherein the hard mask layer film comprises at least one of a silicon nitride film, a silicon oxynitride film, a silicon oxycarbide film, a silicon carbonitride film, and a silicon oxycarbonitride film .
9. The preparation method according to claim 1, wherein after forming the field oxide layer, the field oxide layers under the adjacent openings are connected as a whole.
10. A split-gate flash memory device, comprising:

    substrate;

    a gate dielectric layer, located on the substrate;

    a floating gate polysilicon layer on the gate dielectric layer;

    a field oxide layer on the floating gate polysilicon layer, the field oxide layer is formed by a thermal oxidation process; and

    a tunnel oxide layer, located on the field oxide layer and extending along the field oxide layer to the substrate on both sides of the floating gate polysilicon layer;

    The distance between the bottom of the field oxide layer and the bottom of the floating gate polysilicon layer is not less than a preset distance; the longitudinal section of the contact surface between the field oxide layer and the floating gate polysilicon layer is a wavy shape with at least two troughs .
11. The split-gate flash memory device according to claim 10, wherein the slope of the tangent line at the intersection of the wave shape and the tunnel oxide layer is greater than a predetermined value; When the longitudinal section of the contact surface of the floating gate polysilicon layer is a parabola with a wave valley, the slope of the tangent at the intersection of the parabola and the tunnel oxide layer.
12. The split-gate flash memory device of claim 10, wherein the wave shape is symmetrical about a center line of the field oxide layer.
13. The split-gate flash memory device of claim 10, wherein the wave shape has two valleys, and the distances between the valleys and the bottom of the floating gate polysilicon layer are equal.
14. The split-gate flash memory device according to claim 10, further comprising a select gate structure, the select gate structure is located on the surface of the tunnel oxide layer on one side of the floating gate polysilicon layer, and extends to a portion of the tunnel oxide layer along the tunnel oxide layer on the floating gate polysilicon layer.
15. An electronic device comprising the split-gate flash memory device of claim 10 .

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