WO2022037346A1 - 快速外设组件互联设备启动方法、装置以及存储介质 - Google Patents

快速外设组件互联设备启动方法、装置以及存储介质 Download PDF

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Publication number
WO2022037346A1
WO2022037346A1 PCT/CN2021/106710 CN2021106710W WO2022037346A1 WO 2022037346 A1 WO2022037346 A1 WO 2022037346A1 CN 2021106710 W CN2021106710 W CN 2021106710W WO 2022037346 A1 WO2022037346 A1 WO 2022037346A1
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Prior art keywords
bios
firmware
pcie device
image
code
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PCT/CN2021/106710
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English (en)
French (fr)
Inventor
李宇涛
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华为技术有限公司
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Priority to EP21857441.6A priority Critical patent/EP4191452A4/en
Publication of WO2022037346A1 publication Critical patent/WO2022037346A1/zh
Priority to US18/170,574 priority patent/US20230195473A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4403—Processor initialisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/64—Protecting data integrity, e.g. using checksums, certificates or signatures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
    • G06F21/575—Secure boot
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
    • G06F21/572—Secure firmware programming, e.g. of basic input output system [BIOS]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/82—Protecting input, output or interconnection devices
    • G06F21/85—Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44589—Program code verification, e.g. Java bytecode verification, proof-carrying code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • the present application relates to the field of computer technologies, and in particular, to a method, an apparatus, and a storage medium for starting a fast peripheral component interconnection device.
  • TPM trusted platform module
  • the process of starting the BIOS of the computer equipment is: during the system initialization process, the TPM chip reads the BIOS firmware (firmware), and reads the BIOS firmware. The integrity of the firmware is verified. If the read firmware passes the verification, the firmware has not been tampered with, and the computer device starts the BIOS. If the read firmware fails the verification, the firmware may be tampered with, and the computer device does not start the BIOS, so Avoid booting a tampered BIOS.
  • the TPM chip can only verify the integrity of some components such as the BIOS and baseboard management controller (BMC) in the computer equipment, but not the peripheral component interconnect express mounted on the computer equipment.
  • PCIE BIOS and baseboard management controller
  • PCIE device integrity verification then the PCIE device started by the computer device is not necessarily safe, for example, the PCIE device may have been implanted with malicious code, and the operating system in the subsequent computer device communicates with the PCIE device implanted with malicious code. , which may cause the operating system to be attacked by malicious code, thereby threatening the security of the computer device. Therefore, in order to avoid the PCIE device from threatening the security of the computer device, a method for safely booting the PCIE device is urgently needed.
  • Embodiments of the present application provide a method, apparatus, and storage medium for fast startup of peripheral component interconnection equipment, which can prevent PCIE equipment from threatening the security of computer equipment.
  • the technical solution is as follows:
  • a method for starting a fast peripheral component interconnection PCIE device includes:
  • the input and output system BIOS of the computer device acquires the firmware of the PCIE device; the BIOS verifies the firmware; if the firmware passes the verification, the BIOS starts the PCIE device.
  • the method verifies the firmware of the PCIE device through the BIOS to determine whether the firmware of the PCIE device has been tampered with, and the BIOS can only start the PCIE device where the verified firmware is located, so as to prevent the computer device from starting the PCIE device whose firmware has been tampered with and reduce the risk of Security risks posed by PCIE equipment to computer equipment.
  • the method further includes:
  • the BIOS does not start the PCIE device.
  • the BIOS not starting the PCIE device includes:
  • the BIOS controls the PCIE device to be in a reset state or a power-off state
  • the BIOS marks the PCIE device as a startup prohibited state, and the startup prohibited state is used to indicate that the PCIE device is not to be started.
  • the BIOS is used to control the PCIE device whose firmware has not passed the verification to be in the reset state or the power-off state, or mark the PCIE device where the unverified firmware is located in the prohibited state, so as to completely shield the unverified firmware of the PCIE device.
  • PCIE equipment
  • obtaining the firmware of the PCIE device by the input and output system BIOS of the computer device includes:
  • the BIOS reads the firmware image from the extended read-only memory ROM of the PCIE device.
  • the firmware includes signature data
  • the BIOS before the BIOS reads the firmware image from the extended read-only memory ROM of the PCIE device, the method further includes:
  • the BIOS reads the image type of the image and the certificate type of the signature data from the read-only ROM, where the image type is used to indicate the code type of the image, and the certificate type is used to indicate the calculation The encryption algorithm used when describing the signed data.
  • the firmware includes firmware code and signature data of the firmware code
  • the input and output system BIOS of the computer device obtains the firmware of the PCIE device including:
  • the BIOS obtains the signature data of the firmware code from the driver of the PCIE device; the BIOS reads the firmware code from the PCIE device.
  • the BIOS reading the firmware code from the PCIE device includes:
  • the BIOS reads the image of the firmware code from the expansion ROM of the PCIE device.
  • the method before the BIOS reads the image of the firmware code from the expansion ROM of the PCIE device, the method further includes:
  • the BIOS reads the image type of the image and the certificate type of the signature data from the extended ROM, where the image type is used to indicate the code type of the image, and the certificate type is used to indicate the calculation of the The encryption algorithm used when signing data.
  • the BIOS acquiring the signature data of the firmware code from the driver of the PCIE device includes:
  • the BIOS reads the image of the driver from the extended ROM of the PCIE device;
  • the BIOS obtains the signature data of the firmware code from the image of the driver.
  • the method further includes:
  • the BIOS verifies the driver; if the driver passes the verification, the BIOS executes the step of reading the firmware code from the PCIE device.
  • the BIOS stores a public key of the PCIE device, and the public key is used to verify the firmware.
  • the method further includes:
  • the BIOS modifies the stored public key of the PCIE device based on the public key modification instruction.
  • a PCIE device startup apparatus which is used for executing the above-mentioned PCIE device startup method.
  • the PCIE device startup apparatus includes a functional module for executing the PCIE device startup method provided by the first aspect or any optional manner of the first aspect.
  • a computer-readable storage medium where at least one piece of program code is stored in the storage medium, and the program code is loaded and executed by a processor to implement the operations performed by the above PCIE device startup method.
  • a computer program product or computer program includes computer instructions, the computer instructions are stored in a computer-readable storage medium, and the processor of the computer device reads from the computer-readable storage medium.
  • the computer instruction is fetched, and the processor executes the computer instruction, so that the computer device performs the method provided in the first aspect or various optional implementation manners of the first aspect.
  • a fifth aspect provides a computer device, the computer device includes a processor and a memory, the memory stores at least one piece of program code, the program code is loaded by the processor, so that the computer device realizes the above-mentioned first aspect or The method provided in any optional manner of the foregoing first aspect.
  • FIG. 1 is a schematic diagram of the structure of a computer device provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of the structure of a computer device provided by an embodiment of the present application.
  • FIG. 3 is a flowchart of a PCIE device startup method provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a space of an extended ROM provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a PCIE device startup provided by an embodiment of the present application.
  • FIG. 6 is a flowchart of another PCIE device startup method provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of another PCIE device startup provided by an embodiment of the present application.
  • FIG. 8 is a flowchart of a PCIE device startup method provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of an apparatus for starting a PCIE device according to an embodiment of the present application.
  • FIG. 1 is a schematic diagram of the structure of a computer device provided by an embodiment of the present application.
  • the computer device 100 includes a plurality of peripheral component interconnect express (PCIE) devices 101, and the PCIE device 101 includes a network card , redundant arrays of independent disks (RAID) cards, graphics cards, peripheral Component Interconnect (PCI) solid state drive (solid state drive, SSD) cards, accelerator cards, etc. No specific limitation is made.
  • PCIE peripheral component interconnect express
  • Each PCIE device 101 includes a driver 1011 and a firmware 1012, wherein the driver 1011 is a driver of the PCIE device and can be called by the BIOS running in the computer device 100 to realize data between the BIOS and the PCIE device. interact.
  • the driver 1011 is also used to configure the parameters of the PCIE device.
  • the driver 1011 is a unified extensible firmware interface (unified extensible firmware interface, UEFI) driver.
  • the firmware 1012 is used to implement the functions of the PCIE device 101 , for example, the target firmware of the network card is used to implement functions such as network connection, packet forwarding, and protocol offloading of the network card.
  • the firmware 1012 includes the firmware code and the signature data of the firmware code, wherein the firmware code is also the code used to realize the function of the PCIE device 101, and the signature data is the digital signature of the firmware code, used to determine the firmware code. Whether it has been tampered with, that is, the signature data is used to ensure the integrity of the firmware code.
  • the firmware 1012 does not include the signature data of the firmware code, and the signature data of the firmware code is stored in the driver 1011 .
  • the firmware code may be regarded as the firmware 1012 .
  • the computer device 100 runs a BIOS, and the BIOS is used to obtain the firmware 1012 of the PCIE device 101 and verify the obtained firmware 1012. If the firmware 1012 passes the verification, the BIOS will start the PCIE device 101 where the firmware 1012 is located. , otherwise the PCIE device 101 where the firmware 1012 is located will not be started.
  • the manners for the BIOS to obtain the firmware 1012 of the PCIE device 101 include manner 1 and manner 2, wherein the manner 1 is: the BIOS reads the firmware 1012 including signature data and firmware codes from the PCIE device 101 .
  • Mode 2 is: the BIOS reads the driver 1011 from the PCIE device 101, obtains the signature data of the firmware code from the read driver 1011, and reads the firmware code from the PCIE device.
  • the BIOS stores public keys of multiple PCIE devices 101 , each public key corresponds to a target identifier of a PCIE device, and one public key is used to verify the firmware of the PCIE device indicated by the corresponding target identifier.
  • a target identifier is used to indicate a PCIE device, and the target identifier is the device identifier of the PCIE device, or the slot identifier of the slot where the PCIE device is located.
  • the BIOS when the BIOS receives the public key modification instruction, the BIOS modifies the stored public key of the PCIE device based on the public key modification instruction.
  • the public key modification instruction includes at least one target public key and a target identifier corresponding to each target public key.
  • the BIOS will store the The public key corresponding to the any target identifier is modified to the any target public key.
  • the BIOS further stores BIOS firmware, where the BIOS firmware is a code for implementing BIOS functions.
  • the BIOS is UEFI BIOS.
  • the computer device 100 also includes a processor 102, and the BIOS can run on random access memory (RAM) or read-only memory (ROM) of the processor 102.
  • the processor 102 is connected to the PCIE device 101 through a target communication interface, so that the BIOS can perform signaling interaction with the PCIE device through the target communication interface.
  • the target communication interface is a PCIE interface.
  • the processor 102 includes a central processing unit (CPU), an image processor (graphics processing unit, GPU), an artificial intelligence (artificial intelligence, AI) processor, and so on. Make specific restrictions.
  • the driver and firmware in the PCIE device are separate, that is, the driver and firmware of the PCIE device are two separate parts, such as the PCIE device 101 shown in FIG. 1 .
  • the driver of the PCIE device is located in the firmware, that is, the firmware includes the driver, the firmware code, and the signature data of the firmware code.
  • FIG. 2 is a schematic diagram of the structure of a computer device provided by an embodiment of the present application.
  • the computer device 200 may vary greatly due to different configurations or performance, including one or more processors 201 and one or more memories. 202, the computer device 200 further includes one or more PCIE devices 203, wherein the memory 202 stores at least one piece of program code, and the at least one piece of program code is loaded and executed by the processor 201 to achieve the following:
  • the computer device 200 may also have components such as a wired or wireless network interface and an input/output interface for input and output, and the computer device 200 may also include other components for implementing device functions, which will not be repeated here.
  • a computer-readable storage medium such as a memory including program codes
  • the program codes can be executed by a processor in a computer device to implement the PCIE device startup method in the following embodiments.
  • the computer-readable storage medium may be ROM, RAM, compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, optical data storage device, and the like.
  • BIOS obtains the firmware of the PCIE device through Mode 1
  • verifies the obtained firmware and determines whether to start the PCIE device according to the verification result
  • FIG. 3 Method flow diagram. Applies to computer equipment including PCIE devices.
  • the PCIE device stores firmware and drivers of the PCIE device.
  • the PCIE device is any PCIE device, and the firmware includes firmware code and signature data.
  • the driver includes target driver code and target signature data, wherein the driver code is a code for implementing a driver function, and the target signature data is a digital signature of the driver code for ensuring the integrity of the driver code.
  • the PCIE device acquires firmware and drivers of the PCIE device, and stores the acquired firmware and drivers in an expansion ROM of the PCIE device as a ROM image (image) respectively.
  • the extended ROM includes any number of code images (that is, ROM images) required by different systems and processor architectures. For example, as shown in FIG. There are N+1 ROM images stored in the ROM, which are respectively image 0 to image N. Each ROM image corresponds to an extended ROM header (header) and a peripheral component interconnect (PCI) data structure, where N As an integer greater than 0, the extended ROM header and PCI data structures are used to store the information required by the corresponding ROM image.
  • PCI peripheral component interconnect
  • the extended ROM header is used to store ROM signatures and pointers to PCI data structures.
  • the PCI data structure includes a pointer field, a length field, an image type field, a certificate type field and other fields, wherein the pointer field is used to store a device list pointer to indicate the expansion ROM Supported devices; the length field is used to store the length of the PCI data structure and the length of the ROM image corresponding to the PCI data structure; the image type field is used to indicate the code type of the image, such as driver type, firmware type; certificate type field The type of encryption algorithm used to store the signature data used to calculate the signature.
  • the process for the PCIE device to obtain the firmware is: the PCIE device calculates the firmware code based on the first digest calculation algorithm, obtains the first digest data of the firmware code, and based on the private key of the PCIE device and the first digest data of the firmware code.
  • An encryption algorithm encrypts the first digest data to obtain signature data of the firmware code; the PCIE device combines the firmware code and the signature data into firmware.
  • the process for the PCIE device to obtain the driver is: the PCIE device calculates the driver code based on the second digest calculation algorithm, obtains the second digest data of the driver code, and based on the private key of the PCIE device and the first digest data of the driver code.
  • the second encryption algorithm is used to encrypt the second digest data to obtain the target signature data; the PCIE device combines the driver code and the target signature data to form the driver.
  • the first digest calculation algorithm is an algorithm negotiated between the PCIE device and the BIOS for calculating the first digest data
  • the second digest calculation algorithm is an algorithm negotiated by the PCIE device and the BIOS for calculating the second digest data
  • Two digest calculation algorithms include hash algorithm, message digest (MD) algorithm, secure hash algorithm (SHA), message authentication code (message authentication code, MAC) algorithm and other digest calculation algorithms. This embodiment of the present application does not specifically limit the first/second digest calculation algorithm.
  • the first encryption algorithm is an encryption algorithm negotiated by the PCIE device and the BIOS for encrypting the first digest data
  • the second encryption algorithm is an encryption algorithm negotiated by the PCIE device and the BIOS for encrypting the second digest data
  • the first/second encryption algorithm includes digital signature algorithm (DSA), elliptic curve digital signature algorithm (ECDSA) or by Ron Rivest (Ron Rivest), Adi Sa
  • DSA digital signature algorithm
  • EDSA elliptic curve digital signature algorithm
  • Adi Sa Adi Sa
  • the first/second encryption algorithm is not specifically limited in this embodiment of the present application.
  • the inverse algorithm of the first encryption algorithm is the first decryption algorithm, and the first decryption algorithm is used to decrypt the signature data of the firmware code, and the decrypted data can be recorded as the first decryption data;
  • the inverse algorithm of the second encryption algorithm is: The second decryption algorithm is used to decrypt the target signature data of the driving code, and the decrypted data obtained is recorded as the second decrypted data.
  • the process of combining the firmware code and the signature data into firmware by the PCIE device is as follows: the PCIE device stores the signature data in the first target location of the firmware code to obtain the firmware.
  • the process of combining the driver code and the target signature data into a driver by the PCIE device is as follows: the PCIE device stores the target signature data in a second target location of the driver code to obtain the driver.
  • the first target location is the location in the firmware code negotiated between the PCIE device and the BIOS for storing the signature data, optionally, the first target location is any location of the firmware code, for example, the firmware code Head, somewhere in the middle, or tail.
  • the second target location is a location in the driver code negotiated between the PCIE device and the BIOS for storing the target signature data, optionally, the second target location is any location of the driver code, such as the header of the driver code part, somewhere in the middle, or at the end. This embodiment of the present application does not specifically limit the first/second target position.
  • the PCIE device After acquiring the firmware, the PCIE device stores the firmware as a ROM image in the extended ROM, and configures an extended ROM header and a PCI data structure corresponding to the firmware image, where the extended ROM header is used to store the PCI data structure
  • the pointer of the PCI data structure includes a pointer field, a length field, a mirror type field and a certificate type field, etc., wherein the pointer field is used to indicate the device supported by the extended ROM; the length field is used to store the length of the PCI data structure and the length of the image; the image type field is used to store the image type of the image, and the image type is used to indicate the code type of the image; the certificate type field is used to store the certificate type of the data signature of the image, and the certificate type is used to indicate the calculation signature
  • the encryption algorithm used to encrypt the data is used to a pointer field, a length field, a mirror type field and a certificate type field, etc.
  • the mirror image N in FIG. 4 is the mirror image of the firmware
  • the PCIE device configures the pointer of the PCI data structure corresponding to the mirror image N in the extended ROM header corresponding to the mirror image N; for the PCI data structure corresponding to the mirror image N, the PCIE device
  • the length of the PCI data structure and the length of the firmware are stored in the length field
  • the code type of the firmware code is stored in the image type field
  • the type of the first encryption algorithm is stored in the certificate type field.
  • the PCIE device After acquiring the driver, the PCIE device stores the driver as another ROM image in the extended ROM, and configures the extended ROM header and the PCI data structure corresponding to the image of the driver.
  • the image 0 in FIG. 4 is the image of the driver
  • the PCIE device configures the pointer of the PCI data structure corresponding to the image 0 in the extended ROM header corresponding to the image 0; for the pointer to the PCI data structure corresponding to the image 0, the
  • the PCIE device length field stores the length of the PCI data structure and the length of the driver
  • the image type field stores the code type of the driver code
  • the certificate type field stores the type of the second encryption algorithm.
  • the image of the firmware stored in the extended ROM can be located after the image of the driver, for example, the image of the firmware is the last image of the image of the driver, or the image of the firmware is the last image stored in the extended ROM.
  • the PCIE device stores each image in the extended ROM, the PCIE device stores the start address of the extended ROM in the extended ROM base address field in the base address registers (BAR) space of the PCIE device , so that the BIOS of the subsequent computer device can read the starting address of the extended ROM in the base address field of the extended ROM.
  • BAR base address registers
  • the BIOS reads the driver of the PCIE device from the PCIE device.
  • the BIOS When the computer device is powered on or reset, the BIOS starts to run, the BIOS enumerates each PCIE device installed on the computer device, and after the BIOS enumerates the PCIE device, the BIOS reads the PCIE device from the PCIE device drive.
  • the BIOS can read the image of the driver in the extended read-only memory ROM of the PCIE device, thereby realizing reading the driver of the PCIE device from the PCIE device.
  • the BIOS accesses an extended ROM base address field in the BAR space of the PCIE device through a target communication interface, and the BIOS reads the extended ROM of the PCIE device from the extended ROM base address field start address, and access the extension ROM based on the start address of the extension ROM; for any image stored in the extension ROM, the BIOS can read the image type field of the PCI data structure corresponding to any image
  • the image type of any image if the read image type is the code type of the driver code, then the image is the image of the driver; when the image is the image of the driver, the BIOS can also download the image from the driver.
  • the certificate type of the target signature data is read from the certificate type field of the PCI data structure corresponding to an image, so that according to the second encryption algorithm indicated by the certificate type, it is determined that the inverse algorithm of the second encryption algorithm is the second decryption algorithm, And the BIOS can also read the image of the driver of the PCIE device from the extended ROM. If the read image type is not the code type of the driver code, the BIOS reads the image type of the next image of any image until the driver image is obtained. Still based on Figure 4, the BIOS reads image 0 (ie, the driver) from the expansion ROM.
  • the BIOS verifies the read driver.
  • the BIOS verifies the driver based on the stored public key of the PCIE device.
  • the BIOS obtains the target signature data of the driver code from the second target location of the driver code of the driver, and based on the public key of the PCIE device and the second decryption algorithm, the target The signature data is decrypted to obtain second decrypted data; the BIOS calculates the driver code based on the second digest calculation algorithm to obtain the second digest data of the driver code; if the obtained second digest data is the same as the second decrypted data, Then it means that the driver code in the driver has not been tampered with, and the driver code is complete, and the driver passes the verification; if the obtained second digest data is different from the first decrypted data, it means that the driver code has been tampered with, and the driver code Incomplete, the driver failed validation.
  • the BIOS reads the firmware of the PCIE device from the PCIE device.
  • the BIOS can read the image of the firmware from the extended read-only memory ROM of the PCIE device, so as to realize reading the firmware from the PCIE device.
  • the BIOS accesses the extended ROM based on the start address of the extended ROM through the target communication interface; for any image stored in the extended ROM, the BIOS can access the extended ROM from the corresponding image of the extended ROM. Read the image type of any image in the image type field of the PCI data structure.
  • the read image type is the code type of the firmware code
  • the image is the image of the firmware
  • the BIOS can also read the certificate type of the signature data of the firmware code from the certificate type field of the PCI data structure corresponding to any mirror image (that is, the BIOS reads the mirror image of the firmware from the expansion ROM).
  • the process of the image type and the certificate type of the signed data so that the BIOS can also determine the inverse algorithm of the first encryption algorithm as the first decryption algorithm according to the first encryption algorithm indicated by the certificate type, and the BIOS from Read the image of the firmware in the expansion ROM.
  • the BIOS If the read image type is not the code type of the firmware code, the BIOS reads the image type of the next image of any image until the firmware image is obtained. At this time, the image of the firmware read by the BIOS includes the firmware code and the signature data of the firmware code. Still based on FIG. 4, the BIOS reads the image N (ie, firmware) from the expansion ROM.
  • the image N ie, firmware
  • the driver may bring a security risk to the computer device, and the BIOS jumps to step 307, that is, the BIOS does not start the PCIE device.
  • the BIOS verifies the read firmware.
  • the BIOS verifies the firmware based on the stored public key of the PCIE device.
  • the BIOS obtains the signature data of the firmware code from the first target location of the firmware code in the firmware, and signs the signature based on the public key of the PCIE device and the first decryption algorithm The data is decrypted to obtain the first decrypted data; the BIOS calculates the firmware code based on the first digest calculation algorithm to obtain the first digest data of the firmware code; if the obtained first digest data is the same as the first decrypted data, then It means that the firmware code has not been tampered with and the firmware code is complete, and the firmware has passed the verification; if the obtained first digest data is different from the first decrypted data, it means that the firmware code has been tampered with and the firmware code is incomplete, then The firmware failed verification.
  • the BIOS starts the PCIE device.
  • the firmware passes the verification, the firmware does not bring security risks to the computer device, and the BIOS starts the PCIE device.
  • the process of starting the PCIE device by the BIOS is: the BIOS configures the PCIE device, for example, the BIOS allocates PCI resources to the PCIE device, so that the PCIE device can perform operations in the computer device.
  • the operating system (OS) is visible.
  • the PCI resource includes a bus device function (bus device function, BDF) and a memory space.
  • the PCIE device has been powered on before the BISO starts the PCIE device. Therefore, the PCIE device can interact with the BIOS. Therefore, starting the PCIE device in the embodiments of the present application does not mean powering on the PCIE device and/or The PCIE device interacts with the processing chip, but refers to the normal configuration of the PCIE device so that the normally configured PCIE device can work completely normally.
  • the firmware fails the verification, after the PCIE device is started, the firmware may bring security risks to the computer device, and the BIOS does not start the PCIE device.
  • the BIOS can shield the PCIE device so as not to start the PCIE device, thereby making the operating system in the computer device invisible to the PCIE device that is not started.
  • the process of shielding the PCIE device by the BIOS is as follows: the BIOS controls the PCIE device to be in a reset state or a power-off state; or, the BIOS marks the PCIE device as a boot-forbidden state, which prohibits booting The state is used to indicate that the PCIE device is not started, thereby completely shielding the PCIE device with potential security risks.
  • the BIOS controls a hardware circuit in the computer device to output a PCIE reset (reset) signal, so that the PCIE device is in a reset state.
  • the power supply circuit of the PCIE device is controlled by the target controller, then the BIOS sends a power-off instruction to power off the PCIE device to the target controller. After the controller receives the power-off command, the target controller controls the power supply circuit of the PCIE device to power off the PCIE device.
  • the BIOS may store the target identifier of the PCIE device in association with the state identifier of the boot-prohibited state, so as to mark the PCIE device as the boot-prohibited state.
  • the signature data of the firmware code is signature data 1
  • the target signature data of the driver code is signature data 2
  • the BIOS reads the driver including the driver code and signature data 2 from the PCIE device; BIOS is based on the stored PCIE
  • the public key of the device and the signature data 2 in the driver verify whether the driver code is complete; if the driver code is complete, the BIOS continues to read the firmware including the firmware code and signature data 1 from the PCIE device; BIOS is based on the stored PCIE device.
  • the public key of the firmware and the signature data 1 in the firmware are used to verify whether the firmware code is complete. If the firmware code is complete, the PCIE device will be started, otherwise the PCIE device will not be started.
  • the firmware of the PCIE device is verified through the BIOS to determine whether the firmware of the PCIE device has been tampered with, and the BIOS can only start the PCIE device where the verified firmware is located, thereby avoiding the computer device booting firmware from being tampered with PCIE devices to reduce the security risks caused by PCIE devices to computer equipment.
  • the BIOS also verifies the driver of the PCIE device. As long as either the firmware or the driver fails the verification, the BIOS will not start the PCIE device, thereby preventing the computer device from being tampered with the startup firmware or driver. PCIE devices to further reduce the security risks caused by PCIE devices to computer equipment.
  • BIOS controls the PCIE device where the unauthenticated firmware is located to be in the reset state or the power-off state, or marks the PCIE device where the unauthenticated firmware is located as a disabled state, thereby completely shielding the PCIE device with potential security risks.
  • BIOS obtains the firmware of the PCIE device through Mode 2
  • verifies the obtained firmware and determines whether to start the PCIE device according to the verification result
  • FIG. 6 Method flow diagram. Applies to computer equipment including PCIE devices.
  • the PCIE device stores firmware and drivers of the PCIE device.
  • the firmware is actually firmware code
  • the driver includes the driver code, target signature data of the driver code, and signature data of the firmware code.
  • the firmware in another schematic diagram of PCIE device startup provided by the embodiment of the present application shown in FIG. 7 is firmware code
  • the target signature data included in the driver is signature data 2
  • the signature data of the firmware code is signature data 1.
  • the PCIE device acquires firmware and drivers of the PCIE device, and stores the acquired firmware and drivers as a ROM image in the extended ROM of the PCIE device, respectively.
  • the process for the PCIE device to acquire the firmware of the PCIE device and the driver is: the PCIE device acquires the firmware code and the driver code, acquires the signature data of the firmware code and the target signature data of the driver code, and the PCIE device acquires the The signature data of the firmware code is stored in the third target position of the driver code, and the target signature data is stored in the second target position of the driver code to obtain the driver; wherein, the third target position is negotiated between the PCIE device and the BIOS
  • the position in the driver code for storing the signature data of the firmware code, optionally, the third target position is any position in the driver code except the second target position, and the embodiment of the present application does not apply to the third target position. Make specific restrictions.
  • step 301 the process of obtaining the signature data of the firmware code and the target signature data of the driver code by the PCIE device is described in step 301.
  • the process of the target signature data of the driver code will not be described in detail.
  • the process in which the PCIE device stores the acquired firmware and driver as a ROM image in the extended ROM of the PCIE device, respectively, is also described in step 301.
  • the process of storing in the extended ROM of the PCIE device as a ROM image will not be repeated.
  • the certificate type of the signature data of the firmware code at this time can be stored in the PCI data corresponding to the image of the firmware.
  • the BIOS reads a driver of the PCIE device from the PCIE device, where the driver includes the signature data.
  • This step 602 is the same as the process shown in step 302, and the process shown in this step 602 is not repeated in this embodiment of the present application.
  • the BIOS verifies the read driver.
  • This step 603 is the same as the process shown in step 303, and the process shown in this step 603 is not repeated in this embodiment of the present application.
  • the BIOS decrypts the signature data 2 based on the public key of the PCIE device and the second decryption algorithm to obtain the second decrypted data; the BIOS calculates the driver code based on the second digest calculation algorithm , to obtain the second digest data of the driver code; if the obtained second digest data is the same as the second decrypted data, the driver passes the verification; otherwise, the driver fails the verification.
  • the BIOS obtains the signature data from the read driver.
  • the BIOS can obtain the signature data of the firmware code from the image of the driver. In a possible implementation manner, the BIOS obtains the signature data from the third target location of the driver code in the image of the driver.
  • steps 602 and 604 are also processes in which the BIOS obtains the signature data of the firmware code from the driver of the PCIE device.
  • the BIOS reads the firmware code from the PCIE device.
  • the BIOS can read the image of the firmware code from the expansion ROM of the PCIE device, so as to realize reading the firmware code from the PCIE device.
  • the process of the BIOS reading the image of the firmware code from the extended ROM of the PCIE device is the same as the process of reading the image of the firmware of the PCIE device by the BIOS in step 304.
  • the process of reading the image of the firmware code in the extended ROM of the PCIE device will not be repeated.
  • the BIOS After the BIOS reads the firmware code, the BIOS determines the signature data and the firmware code as the firmware. It should be noted that the processes shown in the above steps 602 , 604 and 605 are also processes in which the input and output system BIOS of the computer device acquires the firmware of the PCIE device.
  • the BIOS verifies the firmware code based on the signature data.
  • the BIOS decrypts the signature data based on the public key of the PCIE device and the first decryption algorithm to obtain the first decrypted data; the BIOS calculates the firmware code based on the first digest calculation algorithm to obtain the first decryption data of the firmware code.
  • Digest data if the obtained first digest data is the same as the first decrypted data, it means that the firmware code has not been tampered with and the firmware code is complete, then the firmware has passed the verification; if the obtained first digest data is the same as the first If the decrypted data is different, it means that the firmware code has been tampered with, and if the firmware code is incomplete, the firmware has not passed the verification.
  • the BIOS decrypts the signature data 1 based on the public key of the PCIE device and the first decryption algorithm to obtain the first decrypted data; the BIOS calculates the firmware code based on the first digest calculation algorithm , to obtain the first digest data of the firmware code; if the obtained first digest data is the same as the first decrypted data, the firmware code passes the verification; otherwise, the firmware code fails the verification.
  • This step 607 is the same as the process shown in step 306, and the process shown in this step 607 is not repeated in this embodiment of the present application.
  • This step 608 is the same as the process shown in step 307, and the process shown in this step 608 is not repeated in this embodiment of the present application.
  • the firmware of the PCIE device is verified through the BIOS to determine whether the firmware of the PCIE device has been tampered with, and the BIOS can only start the PCIE device where the verified firmware is located, thereby avoiding the computer device booting firmware from being tampered with PCIE devices to reduce the security risks caused by PCIE devices to computer equipment.
  • the BIOS also verifies the driver of the PCIE device. As long as either the firmware or the driver fails the verification, the BIOS will not start the PCIE device, thereby preventing the computer device from being tampered with the startup firmware or driver. PCIE devices to further reduce the security risks caused by PCIE devices to computer equipment.
  • BIOS controls the PCIE device where the unauthenticated firmware is located to be in the reset state or the power-off state, or marks the PCIE device where the unauthenticated firmware is located as a disabled state, thereby completely shielding the PCIE device with potential security risks.
  • FIG. 8 refers to the flowchart of a PCIE device startup method provided by an embodiment of the present application shown in FIG. 8 .
  • the computer device is powered on or reset, the BIOS firmware of the computer device runs, the BIOS enumerates each PCIE device in the computer device, and every time any PCIE device is enumerated, the BIOS verifies the driver of the PCIE device, and the operation passes the verification.
  • the BIOS loads the firmware of the PCIE device; the BIOS verifies the loaded firmware, if the verification passes, the BIOS configures the PCIE device normally, so that the PCIE device is visible to the OS of the computer device, otherwise the BIOS shields the PCIE device; when the BIOS After loading all PCIE devices that pass the verification in the computer device, the BIOS loads the OS.
  • the "tampering" mentioned in this application includes malicious tampering, unintentional modification, incomplete firmware, firmware damage, increase/decrease in the code amount of the firmware code, or modification of the content of the firmware code.
  • the first digest data calculated by the BISO according to the obtained firmware code is different from the first decrypted data calculated by the BIOS according to the obtained signature data, it means that the firmware obtained by the BIOS has been tampered with.
  • the apparatus 900 includes a PCIE device 901, and the apparatus 900 includes:
  • an obtaining module 902 used for the input and output system BIOS to obtain the firmware of the PCIE device
  • a control module 904 configured to enable the BIOS to start the PCIE device if the firmware passes the verification.
  • control module 904 is further configured to:
  • the BIOS does not start the PCIE device.
  • control module 904 is further configured to:
  • the BIOS controls the PCIE device to be in a reset state or a power-off state
  • the BIOS marks the PCIE device as a startup prohibited state, and the startup prohibited state is used to indicate that the PCIE device is not to be started.
  • the obtaining module 902 is used for:
  • the BIOS reads the firmware image from the extended read-only memory ROM of the PCIE device.
  • the firmware includes signature data
  • the obtaining module is further configured to:
  • the BIOS reads the image type of the image and the certificate type of the signature data from the read-only ROM, where the image type is used to indicate the code type of the image, and the certificate type is used to indicate the computing The encryption algorithm used when describing the signed data.
  • the firmware includes firmware code and signature data of the firmware code;
  • the acquisition module includes:
  • an obtaining unit used for the BIOS to obtain the signature data of the firmware code from the driver of the PCIE device
  • a reading unit used for the BIOS to read the firmware code from the PCIE device.
  • the reading unit is used for:
  • the BIOS reads the image of the firmware code from the expansion ROM of the PCIE device.
  • the reading unit is also used for:
  • the BIOS reads the image type of the image and the certificate type of the signature data from the extended ROM, where the image type is used to indicate the code type of the image, and the certificate type is used to indicate the calculation of the The encryption algorithm used when signing data.
  • the obtaining unit is used for:
  • the BIOS reads the image of the driver from the extended ROM of the PCIE device;
  • the BIOS obtains the signature data of the firmware code from the image of the driver.
  • the verification module 903 is also used for:
  • the BIOS verifies the driver
  • the BIOS executes the step of reading the firmware code from the PCIE device.
  • the BIOS stores a public key of the PCIE device, and the public key is used to verify the firmware.
  • the apparatus 900 further includes:
  • the modification module is used for the BIOS to modify the stored public key of the PCIE device based on the public key modification instruction.
  • Embodiments of the present application also provide a computer program product or computer program, where the computer program product or computer program includes computer instructions, where the computer instructions are stored in a computer-readable storage medium, and the processor of the computer device is stored in the computer-readable storage medium.
  • the computer instruction is read, and the processor executes the computer instruction, so that the computer device executes the above PCIE device startup method.

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Abstract

一种快速外设组件互联设备启动方法、装置以及存储介质，属于计算机技术领域。本方法通过BIOS对PCIE设备的固件进行验证，以确定PCIE设备的固件是否被篡改，且BIOS仅能启动通过验证的固件所在的PCIE设备，从而避免计算机设备启动固件被篡改的PCIE设备，以降低PCIE设备对计算机设备造成的安全风险。

Description

快速外设组件互联设备启动方法、装置以及存储介质
本申请要求于2020年08月21日提交中国专利局、申请号为202010849505.0、发明名称为“快速外设组件互联设备启动方法、装置以及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，特别涉及一种快速外设组件互联设备启动方法、装置以及存储介质。
背景技术
随着网络技术的发展，计算机设备对网络安全的要求越来越严格，为了保证计算机设备的网络安全，一般在系统初始化的过程中，计算机设备中的可信平台模块(trusted platform module，TPM)芯片对计算机设备内的部分部件进行验证，计算机设备启动通过验证的部件。
以计算机设备启动基本输入输出系统(base input output system，BIOS)为例，目前，计算机设备启动BIOS的过程为：在系统初始化过程中，TPM芯片读取BIOS的固件(firmware)，对读取到的固件进行完整性验证，若读取到的固件通过验证，则固件没有被篡改，计算机设备启动BIOS，若读取到的固件未通过验证，则固件可能被篡改，计算机设备不启动BIOS，从而避免启动被篡改的BIOS。
但是TPM芯片仅能对计算机设备中的BIOS、基板管理控制器(baseboard management controller，BMC)等部分部件进行完整性验证，而未对计算机设备上挂载的快速外设组件互联(peripheral component interconnect express，PCIE)设备进行完整性验证，那么计算机设备启动的PCIE设备不一定安全，例如PCIE设备可能已经被植入恶意代码，后续计算机设备内的操作系统与被植入恶意代码的PCIE设备进行通信时，可能导致操作系统被恶意代码攻击，进而威胁计算机设备的安全，因此为了避免PCIE设备威胁计算机设备的安全，亟需一种能够安全启动PCIE设备的方法。
发明内容
本申请实施例提供了一种快速外设组件互联设备启动方法、装置以及存储介质，能够避免PCIE设备威胁计算机设备的安全。该技术方案如下：
第一方面，提供了一种快速外设组件互联PCIE设备启动方法，该方法包括：
所述计算机设备的输入输出系统BIOS获取所述PCIE设备的固件；所述BIOS对所述固件进行验证；若所述固件通过验证，所述BIOS启动所述PCIE设备。
该方法通过BIOS对PCIE设备的固件进行验证，以确定PCIE设备的固件是否被篡改，且BIOS仅能启动通过验证的固件所在的PCIE设备，从而避免计算机设备启动固件被篡改的PCIE设备，以降低PCIE设备对计算机设备造成的安全风险。
在一种可能实现方式中，所述方法还包括：
若所述固件未通过验证，所述BIOS不启动所述PCIE设备。
基于上述可能的实现方式，通过不启动固件未通过验证的PCIE设备，避免计算机设备启动固件被篡改的PCIE设备，以降低PCIE设备对计算机设备造成的安全风险。
在一种可能实现方式中，所述BIOS不启动所述PCIE设备包括：
所述BIOS控制所述PCIE设备处于复位状态或者下电状态；
或，所述BIOS将所述PCIE设备标记为禁止启动状态，所述禁止启动状态用于指示不启动所述PCIE设备。
基于上述可能的实现方式，通过BIOS控制固件未通过验证的PCIE设备处于复位状态或者下电状态，或将未通过验证的固件所在的PCIE设备标记为禁止启动状态，从而彻底屏蔽固件未通过验证的PCIE设备。
在一种可能实现方式中，所述计算机设备的输入输出系统BIOS获取所述PCIE设备的固件包括：
所述BIOS从所述PCIE设备的扩展只读存储器ROM中读取所述固件的镜像。
在一种可能实现方式中，所述固件包括签名数据，所述BIOS从所述PCIE设备的扩展只读存储器ROM中的读取所述固件的镜像之前，所述方法还包括：
所述BIOS从所述只读ROM中读取所述镜像的镜像类型以及所述签名数据的证书类型，所述镜像类型用于指示所述镜像的代码类型，所述证书类型用于指示计算所述签名数据时所使用的加密算法。
在一种可能实现方式中，所述固件包括固件代码以及所述固件代码的签名数据；
所述计算机设备的输入输出系统BIOS获取所述PCIE设备的固件包括：
所述BIOS从所述PCIE设备的驱动中，获取所述固件代码的签名数据；所述BIOS从所述PCIE设备读取所述固件代码。
在一种可能实现方式中，所述BIOS从所述PCIE设备读取所述固件代码包括：
所述BIOS从所述PCIE设备的扩展ROM中读取所述固件代码的镜像。
在一种可能实现方式中，所述BIOS从所述PCIE设备的扩展ROM中的读取所述固件代码的镜像之前，所述方法还包括：
所述BIOS从所述扩展ROM中读取所述镜像的镜像类型以及所述签名数据的证书类型，所述镜像类型用于指示所述镜像的代码类型，所述证书类型用于指示计算所述签名数据时所使用的加密算法。
在一种可能实现方式中，所述BIOS从所述PCIE设备的驱动中，获取所述固件代码的签名数据包括：
所述BIOS从所述PCIE设备的扩展ROM中读取所述驱动的镜像；
所所述BIOS从所述驱动的镜像中，获取所述固件代码的签名数据。
在一种可能实现方式中，所述BIOS对所述固件进行验证之前，所述方法还包括：
所述BIOS对所述驱动进行验证；若所述驱动通过验证，所述BIOS执行从所述PCIE设备读取所述固件代码的步骤。
在一种可能实现方式中，所述BIOS存储有所述PCIE设备的公钥，所述公钥用于对所述固件进行验证。
在一种可能实现方式中，所述方法还包括：
所述BIOS基于公钥修改指令，对存储的所述PCIE设备的公钥进行修改。
第二方面，提供了一种PCIE设备启动装置，用于执行上述PCIE设备启动方法。具体地，该PCIE设备启动装置包括用于执行上述第一方面或上述第一方面的任一种可选方式提供的PCIE设备启动方法的功能模块。
第三方面，提供一种计算机可读存储介质，该存储介质中存储有至少一条程序代码，该程序代码由处理器加载并执行以实现如上述PCIE设备启动方法所执行的操作。
第四方面，提供了一种计算机程序产品或计算机程序，该计算机程序产品或计算机程序包括计算机指令，该计算机指令存储在计算机可读存储介质中，计算机设备的处理器从计算机可读存储介质读取该计算机指令，处理器执行该计算机指令，使得该计算机设备执行上述第一方面或者第一方面的各种可选实现方式中提供的方法。
第五方面，提供一种计算机设备，该计算机设备包括处理器和存储器，该存储器中存储有至少一条程序代码，该程序代码由该处理器加载，以使得所述计算机设备实现上述第一方面或上述第一方面的任一种可选方式中提供的方法。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要启用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种计算机设备的结构的示意图；
图2是本申请实施例提供的一种计算机设备的结构的示意图；
图3是本申请实施例提供的一种PCIE设备启动方法流程图；
图4是本申请实施例提供的一种扩展ROM的空间示意图；
图5是本申请实施例提供的一种PCIE设备启动的示意图；
图6是本申请实施例提供的另一种PCIE设备启动方法流程图；
图7是本申请实施例提供的另一种PCIE设备启动的示意图；
图8是本申请实施例提供的一种PCIE设备启动方法的流程图；
图9是本申请实施例提供的一种PCIE设备启动装置的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
图1是本申请实施例提供的一种计算机设备的结构的示意图，参见图1，该计算机设备100包括多个快速外设组件互联(peripheral component interconnect express，PCIE)设备101，PCIE设备101包括网卡、磁盘阵列(redundant arrays of independent disks，RAID)卡、显卡、外设组件互联(peripheral Component Interconnect，PCI)固态驱动器(solid state drive，SSD)卡以及加速卡等，本申请实施例对PCIE设备101不做具体限定。
每个PCIE设备101包括驱动(driver)1011以及固件(firmware)1012，其中，驱动1011为PCIE设备的驱动程序，能够被计算机设备100内运行的BIOS调用，以实现BIOS与PCIE 设备之间的数据交互。在初始化阶段，驱动1011还用于配置PCIE设备的参数。可选地，该驱动1011为统一扩展固件接口(unified extensible firmware interface，UEFI)驱动。固件1012用于实现PCIE设备101的功能，例如，网卡的目标固件用于实现网卡的网络连接、报文转发以及协议卸载等功能。可选地，固件1012包括固件代码和该固件代码的签名数据，其中，固件代码也即是用于实现PCIE设备101的功能的代码，该签名数据为固件代码的数字签名，用于确定固件代码是否被篡改，也即是签名数据用于保证固件代码的完整性。在另一种可能的实现方式中，固件1012不包括该固件代码的签名数据，该固件代码的签名数据存储在驱动1011中，此时，固件代码可以视为固件1012。
该计算机设备100内运行有BIOS，该BIOS用于获取PCIE设备101的固件1012，并对获取到的固件1012进行验证，若固件1012通过验证，则由该BIOS启动该固件1012所在的PCIE设备101，否则不启动该固件1012所在的PCIE设备101。其中，该BIOS获取PCIE设备101的固件1012的方式包括方式1和方式2，其中，方式1为：该BIOS从PCIE设备101读取包括签名数据和固件代码的固件1012。方式2为：该BIOS从PCIE设备101读取驱动1011，从读取到的驱动1011中获取固件代码的签名数据，并从PCIE设备读取固件代码。
可选地，该BIOS存储有多个PCIE设备101的公钥，每个公钥分别对应一个PCIE设备的目标标识，一个公钥用于对对应的目标标识所指示的PCIE设备的固件进行验证。其中，一个目标标识用于指示一个PCIE设备，该目标标识为该PCIE设备的设备标识，或者该PCIE设备所在槽位的槽位标识。可选地，当该BIOS接收到公钥修改指令时，该BIOS基于该公钥修改指令，对存储的PCIE设备的公钥进行修改。其中，该公钥修改指令包括至少一个目标公钥以及每个目标公钥对应的目标标识，对于该至少一个目标公钥中任一目标公钥所对应的任一目标标识，该BIOS将存储的该任一目标标识所对应的公钥修改为该任一目标公钥。可选地，该BIOS还存储有BIOS固件，BIOS固件为用于实现BIOS功能的代码。可选地，该BIOS为UEFI BIOS。
该计算机设备100还包括处理器102，该BIOS能够运行在处理器102的随机存取存储器(random access memory，RAM)或只读存储器(read-only memory，ROM)上。该处理器102通过目标通信接口与PCIE设备101连接，以便BIOS能够通过该目标通信接口与PCIE设备进行信令交互。其中该目标通信接口为PCIE接口。该处理器102包括中央处理器(central processing unit，CPU)、图像处理器(graphics processing unit，GPU)以及人工智能(artificial intelligence，AI)处理器等，本申请实施例对该处理器102的不做具体限定。
需要说明的是，在一些实施例中，PCIE设备中的驱动和固件是分开的，也即是PCIE设备的驱动和固件是两个单独的部分，例如图1所示的PCIE设备101。而在另外一些实施例中，PCIE设备的驱动位于固件中，也即是固件包括驱动、固件代码以及该固件代码的签名数据。
图2是本申请实施例提供的一种计算机设备的结构的示意图，该计算机设备200可因配置或性能不同而产生比较大的差异，包括一个或一个以上处理器201和一个或一个以上的存储器202，该计算机设备200还包括一个或一个以上的PCIE设备203，其中，所述存储器202中存储有至少一条程序代码，所述至少一条程序代码由所述处理器201加载并执行以实现下述各个方法实施例提供的PCIE设备启动方法。当然，该计算机设备200还可以具有有线或无线网络接口以及输入输出接口等部件，以便进行输入输出，该计算机设备200还可以包括其他用于实现设备功能的部件，在此不做赘述。
在示例性实施例中，还提供了一种计算机可读存储介质，例如包括程序代码的存储器，上述程序代码可由计算机设备中的处理器执行以完成下述实施例中的PCIE设备启动方法。例如，该计算机可读存储介质可以是ROM、RAM、只读光盘(compact disc read-only memory，CD-ROM)、磁带、软盘和光数据存储设备等。
为了进一步说明BIOS通过方式1获取PCIE设备的固件，对获取到固件进行验证，并根据验证结果确定是否启动PCIE设备的过程，参见如图3所示的本申请实施例提供的一种PCIE设备启动方法流程图。应用于包括PCIE设备的计算机设备。
301、PCIE设备存储PCIE设备的固件和驱动。
该PCIE设备为任一PCIE设备，该固件包括固件代码和签名数据。该驱动包括目标驱动代码以及目标签名数据，其中，该驱动代码为实现驱动功能的代码，该目标签名数据为该驱动代码的数字签名，用于保证驱动代码的完整性。
在一种可能的实现方式中，该PCIE设备获取PCIE设备的固件以及驱动，并将获取到的固件和驱动分别作为一个ROM镜像(image)存储在该PCIE设备的扩展(expansion)ROM。其中，该扩展ROM包含不同系统和处理器架构所需的任意多的代码镜像(也即是ROM镜像)，例如图4所示的本申请实施例提供的一种扩展ROM的空间示意图，该扩展ROM中存储有N+1个ROM镜像，分别为镜像0至镜像N，每个ROM镜像对应一个扩展ROM头(header)以及一个外设组件互联(peripheral component interconnect，PCI)数据结构，其中，N为大于0的整数，扩展ROM头和PCI数据结构用于存储对应的ROM镜像所需的信息。扩展ROM头用于存储ROM签名以及指向PCI数据结构的指针。PCI数据结构包括指针(pointer)字段、长度字段、镜像类型字段、证书类型(certificate type)字段以及其他字段，其中，指针字段，用于存储设备列表指针(device list pointer)，以指示该扩展ROM支持的设备；长度字段用于存储该PCI数据结构的长度以及该PCI数据结构对应的ROM镜像的长度；镜像类型字段用于指示镜像的代码类型，例如驱动的类型、固件的类型；证书类型字段用于存储计算签名数据时所使用的加密算法的类型。
可选地，PCIE设备获取该固件的过程为：该PCIE设备基于第一摘要计算算法，对该固件代码进行计算，得到该固件代码的第一摘要数据，并基于该PCIE设备的私钥以及第一加密算法，对该第一摘要数据进行加密，得到该固件代码的签名数据；该PCIE设备将该固件代码和该签名数据组合成固件。可选地，PCIE设备获取该驱动的过程为：该PCIE设备基于第二摘要计算算法，对该驱动代码进行计算，得到该驱动代码的第二摘要数据，并基于该PCIE设备的私钥以及第二加密算法，对该第二摘要数据进行加密，得到该目标签名数据；该PCIE设备将该驱动代码和该目标签名数据组合成该驱动。
其中，第一摘要计算算法为PCIE设备与BIOS协商的用于计算第一摘要数据的算法，第二摘要计算算法为PCIE设备与BIOS协商的用于计算第二摘要数据的算法，第一/第二摘要计算算法包括哈希算法、消息摘要(message digest，MD)算法、安全散列算法(secure hash algorithm，SHA)、消息认证码(message authentication code，MAC)算法以及其他摘要计算算法。本申请实施例对该第一/第二摘要计算算法不做具体限定。该第一加密算法为PCIE设备与BIOS协商的用于对该第一摘要数据加密的加密算法，该第二加密算法为PCIE设备与BIOS协商的用于对该第二摘要数据加密的加密算法，该第一/第二加密算法包括数字签名算 法(digital signature algorithm，DSA)，椭圆曲线数字签名算法(elliptic curve digital signature algorithm，ECDSA)或由罗纳德·李维斯特(Ron Rivest)、阿迪·萨莫尔(Adi Shamir)和伦纳德·阿德曼(Leonard Adleman)三人提出的RSA加密算法，本申请实施例对该第一/第二加密算法不做具体限定。该第一加密算法的逆算法为第一解密算法，第一解密算法用于对该固件代码的签名数据进行解密，得到解密数据可记为第一解密数据；该第二加密算法的逆算法为第二解密算法，用于对驱动代码的目标签名数据进行解密，得到解密数据记为第二解密数据。
可选地，该PCIE设备将该固件代码和该签名数据组合成固件的过程为：该PCIE设备将该签名数据存储在该固件代码的第一目标位置，得到该固件。可选地，该PCIE设备将该驱动代码和该目标签名数据组合成驱动的过程为：该PCIE设备将该目标签名数据存储在该驱动代码的第二目标位置，得到该驱动。其中，该第一目标位置为该PCIE设备与BIOS协商的固件代码中用于存储该签名数据的位置，可选地，该第一目标位置为该固件代码的任一位置，例如该固件代码的头部、中间的某一位置或尾部。该第二目标位置为该PCIE设备与BIOS协商的驱动代码中用于存储该目标签名数据的位置，可选地，该第二目标位置为该驱动代码的任一位置，例如该驱动代码的头部、中间的某一位置或尾部。本申请实施例对该第一/第二目标位置不做具体限定。
当获取到该固件后，该PCIE设备将该固件作为一个ROM镜像存储在扩展ROM中，并配置该固件的镜像对应的扩展ROM头以及PCI数据结构，该扩展ROM头用于存储该PCI数据结构的指针，该PCI数据结构包括指针字段、长度字段、镜像类型字段以及证书类型字段等，其中，该指针字段用于指示该扩展ROM所支持设备；该长度字段用于存储该PCI数据结构的长度以及该镜像的长度；镜像类型字段用于存储该镜像的镜像类型，该镜像类型用于指示镜像的代码类型；证书类型字段用于存储镜像的数据签名的证书类型，证书类型用于指示计算签名数据时所使用的加密算法。例如图4中的镜像N为该固件的镜像，该PCIE设备在镜像N对应的扩展ROM头中配置镜像N所对应的PCI数据结构的指针；对于镜像N所对应的PCI数据结构，该PCIE设备在长度字段存储该PCI数据结构的长度以及该固件的长度，在镜像类型字段存储该固件代码的代码类型，并在证书类型字段存储第一加密算法的类型。
当获取到该驱动后，该PCIE设备将该驱动作为另一个ROM镜像存储在扩展ROM中，并配置该驱动的镜像对应的扩展ROM头以及PCI数据结构。例如图4中的镜像0为该驱动的镜像，该PCIE设备在镜像0对应的扩展ROM头中配置该镜像0对应的PCI数据结构的指针；对于该镜像0对应的PCI数据结构的指针，该PCIE设备长度字段存储该PCI数据结构的长度以及该驱动的长度，在镜像类型字段存储该驱动代码的代码类型，并在证书类型字段存储第二加密算法的类型。
需要说明的是，扩展ROM中存储的固件的镜像可以位于驱动的镜像之后，例如固件的镜像为该驱动的镜像的后一个镜像，或者固件的镜像为扩展ROM中存储的最后一个镜像。当该PCIE设备在该扩展ROM中存储完各个镜像后，该PCIE设备将该扩展ROM的起始地址存储在PCIE设备的基址寄存器(base address registers，BAR)空间内的扩展ROM基址字段中，以便后续计算机设备的BIOS能够在该扩展ROM基址字段中读取到该扩展ROM的起始地址。
302、该BIOS从该PCIE设备读取该PCIE设备的驱动。
当该计算机设备上电或复位后，该BIOS开始运行，该BIOS枚举该计算机设备上安装的各个PCIE设备，当BIOS枚举到该PCIE设备后，该BIOS从该PCIE设备读取该PCIE设备的驱动。
该BIOS可以在该PCIE设备的扩展只读存储器ROM中读取该驱动的镜像，从而实现从该PCIE设备读取该PCIE设备的驱动。在一种可能的实现方式中，该BIOS通过目标通信接口，访问该PCIE设备的BAR空间内的扩展ROM基址字段，该BIOS从该扩展ROM基址字段中读取该PCIE设备的扩展ROM的起始地址，并基于该扩展ROM的起始地址访问该扩展ROM；对于该扩展ROM中存储的任一镜像，该BIOS可以从该任一镜像对应的PCI数据结构的镜像类型字段中读取该任一镜像的镜像类型，若读取到的镜像类型为驱动代码的代码类型，则该任一镜像为驱动的镜像；当该任一镜像为该驱动的镜像时，该BIOS还可以从该任一镜像对应的PCI数据结构的证书类型字段中读取该目标签名数据的证书类型，从而根据该证书类型所指示的第二加密算法，确定该第二加密算法的逆算法为第二解密算法，且该BIOS还可以从该扩展ROM中读取该PCIE设备的驱动的镜像。若读取到的镜像类型不是驱动代码的代码类型，则该BIOS读取该任一镜像的下一个镜像的镜像类型，直至获取到驱动的镜像。仍以图4为基础，该BIOS从该扩展ROM中读取镜像0(也即是驱动)。
303、该BIOS对读取到的驱动进行验证。
该BIOS基于存储的该PCIE设备的公钥，对该驱动进行验证。
在一种可能的实现方式中，该BIOS从该驱动的驱动代码的第二目标位置，获取该驱动代码的目标签名数据，并基于该PCIE设备的公钥以及该第二解密算法，对该目标签名数据进行解密，得到第二解密数据；该BIOS基于第二摘要计算算法，对驱动代码进行计算，得到驱动代码的第二摘要数据；若得到的第二摘要数据和该第二解密数据相同，则说明该驱动中的驱动代码未被篡改，驱动代码是完整的，则该驱动通过验证；若得到的第二摘要数据和该第一解密数据不同，则该说明驱动代码已经被篡改，驱动代码不完整，则该驱动未通过验证。
304、若该驱动通过验证，BIOS从该PCIE设备读取该PCIE设备的固件。
该BIOS可以从该PCIE设备的扩展只读存储器ROM中读取该固件的镜像，从而实现从该PCIE设备读取该固件。在一种可能的实现方式中，该BIOS通过目标通信接口，基于该扩展ROM的起始地址访问该扩展ROM；对于该扩展ROM中存储的任一镜像，该BIOS可以从该任一镜像对应的PCI数据结构的镜像类型字段中读取该任一镜像的镜像类型，若读取到的镜像类型为固件代码的代码类型，则该任一镜像为固件的镜像；当该任一镜像为该固件的镜像时，该BIOS还可以从该任一镜像对应的PCI数据结构的证书类型字段中读取该固件代码的签名数据的证书类型(也即是该BIOS从该扩展ROM中读取固件的镜像的镜像类型以及该签名数据的证书类型的过程)，从而该BIOS还可以根据该证书类型所指示的第一加密算法，确定该第一加密算法的逆算法为第一解密算法，且该BIOS从该扩展ROM中读取该固件的镜像。若读取到的镜像类型不是固件代码的代码类型，则该BIOS读取该任一镜像的下一个镜像的镜像类型，直至获取到固件的镜像。此时BIOS读取到的固件的镜像中包括固件代码和固件代码的签名数据。仍以图4为基础，该BIOS从该扩展ROM中读取镜像N(也即是固件)。
在一种可能的实现方式中，若驱动未通过验证，则驱动可能为计算机设备带来安全风险， 则该BIOS跳转执行步骤307，也即是该BIOS不启动该PCIE设备。
305、该BIOS对读取到的固件进行验证。
该BIOS基于存储的该PCIE设备的公钥，对该固件进行验证。
在一种可能的实现方式中，该BIOS从该固件内的固件代码的第一目标位置，获取该固件代码的签名数据，并基于该PCIE设备的公钥以及该第一解密算法，对该签名数据进行解密，得到第一解密数据；该BIOS基于第一摘要计算算法，对固件代码进行计算，得到固件代码的第一摘要数据；若得到的第一摘要数据和该第一解密数据相同，则说明该固件代码未被篡改，固件代码是完整的，则该固件通过验证；若得到的第一摘要数据和该第一解密数据不同，则该说明固件代码已经被篡改，固件代码不完整，则该固件未通过验证。
306、若该固件通过验证，该BIOS启动该PCIE设备。
若该固件通过验证，则该固件不会为该计算机设备带来安全风险，则该BIOS启动该PCIE设备。
在一种可能的实现方式中，该BIOS启动该PCIE设备的过程为：该BIOS对该PCIE设备进行配置，例如该BIOS为该PCIE设备分配PCI资源，以便该PCIE设备对该计算机设备内的操作系统(operating system，OS)可见。其中，该PCI资源包括总线设备功能(bus device function，BDF)和内存空间。
需要说明的是，在BISO启动该PCIE设备之前该PCIE设备已经上电，因此，PCIE设备能够与BIOS进行交互，所以，本申请实施例中的启动PCIE设备不是指为PCIE设备上电和/或PCIE设备与处理芯片进行交互，而是指正常配置PCIE设备，以便正常配置后的PCIE设备能够完全正常工作。
307、若该固件未通过验证，该BIOS不启动该PCIE设备。
若该固件未通过验证，则该PCIE设备被启动后，该固件可能为该计算机设备带来安全风险，则该BIOS不启动该PCIE设备。
该BIOS可以通过屏蔽该PCIE设备，来实现不启动该PCIE设备，从而使得该计算机设备内的操作系统对未启动的PCIE设备不可见。在一种可能的实现方式中，该BIOS屏蔽该PCIE设备的过程为：该BIOS控制该PCIE设备处于复位状态或者下电状态；或，该BIOS将该PCIE设备标记为禁止启动状态，该禁止启动状态用于指示不启动该PCIE设备，从而彻底屏蔽有安全隐患的PCIE设备。可选地，该BIOS控制该计算机设备中的硬件电路输出PCIE复位(reset)信号，以使该PCIE设备处于复位状态。可选地，当该计算机设备支持PCIE设备热拔插时，该PCIE设备的供电电路由目标控制器控制，则该BIOS向目标控制器发送对该PCIE设备下电的下电指令，当该目标控制器接收到该下电指令后，则该目标控制器对该PCIE设备的供电电路进行控制，以给PCIE设备下电。可选地，该BIOS可以将该PCIE设备的目标标识与该禁止启动状态的状态标识进行关联存储，以实现将该PCIE设备标记为禁止启动状态。
为了进一步说明步骤302-307所示的过程，参见图5所示的本申请实施例提供的一种PCIE设备启动的示意图。在图5中，固件代码的签名数据为签名数据1，驱动代码的目标签名数据为签名数据2，BIOS从PCIE设备中读取到包括驱动代码和签名数据2的驱动；BIOS基于存储的该PCIE设备的公钥以及驱动中的签名数据2，验证驱动代码是否完整；若驱动代码完整，则BIOS继续从PCIE设备中读取到包括固件代码和签名数据1的固件；BIOS基于存储 的该PCIE设备的公钥以及固件中的签名数据1，验证固件代码是否完整，若固件代码完整则启动该PCIE设备，否则不启动该PCIE设备。
本申请实施例提供的方法，通过BIOS对PCIE设备的固件进行验证，以确定PCIE设备的固件是否被篡改，且BIOS仅能启动通过验证的固件所在的PCIE设备，从而避免计算机设备启动固件被篡改的PCIE设备，以降低PCIE设备对计算机设备造成的安全风险。并且，BIOS除了对PCIE设备进行验证以外，还对PCIE设备的驱动进行验证，只要固件和驱动中的任一个未通过验证，则BIOS不启动该PCIE设备，从而避免计算机设备启动固件或驱动被篡改的PCIE设备，以进一步降低PCIE设备对计算机设备造成的安全风险。并且，通过BIOS控制未通过验证的固件所在的PCIE设备处于复位状态或者下电状态，或将未通过验证的固件所在的PCIE设备标记为禁止启动状态，从而彻底屏蔽有安全隐患的PCIE设备。
为了进一步说明BIOS通过方式2获取PCIE设备的固件，对获取到固件进行验证，并根据验证结果确定是否启动PCIE设备的过程，参见如图6示的本申请实施例提供的另一种PCIE设备启动方法流程图。应用于包括PCIE设备的计算机设备。
601、PCIE设备存储PCIE设备的固件和驱动。
在图6所示的实施例中，该固件实际为固件代码，该驱动包括驱动代码、驱动代码的目标签名数据以及该固件代码的签名数据。例如，图7所示的本申请实施例提供的另一种PCIE设备启动的示意图中的固件为固件代码，驱动包括的目标签名数据为签名数据2，固件代码的签名数据为签名数据1。
在一种可能的实现方式中，该PCIE设备获取PCIE设备的固件以及驱动，并将获取到的固件和驱动分别作为一个ROM镜像存储在该PCIE设备的扩展ROM中。
可选地，该PCIE设备获取PCIE设备的固件以及驱动的过程为：该PCIE设备获取该固件代码以及驱动代码，获取该固件代码的签名数据以及该驱动代码的目标签名数据，该PCIE设备将该固件代码的签名数据存储该驱动代码的第三目标位置，将该目标签名数据存储在该驱动代码的第二目标位置，得到该驱动；其中，该第三目标位置为该PCIE设备与BIOS协商的驱动代码中用于存储固件代码的签名数据的位置，可选地，该第三目标位置为该驱动代码中除第二目标位置以外的任一位置，本申请实施例对该第三目标位置不做具体限定。
需要说明的是，PCIE设备获取该固件代码的签名数据以及该驱动代码的目标签名数据的过程在步骤301中有相关描述，在此，本申请实施例对PCIE设备获取该固件代码的签名数据以及该驱动代码的目标签名数据的过程不做赘述。PCIE设备将获取到的固件和驱动分别作为一个ROM镜像存储在该PCIE设备的扩展ROM的过程，在步骤301中也有相关描述，在此，本申请实施例对PCIE设备将获取到的固件和驱动分别作为一个ROM镜像存储在该PCIE设备的扩展ROM的过程不做赘述。
需要说明的是，由于此时该固件仅包括固件代码，而固件代码的签名数据存储在驱动中，则此时该固件代码的签名数据的证书类型可以存储在该固件的镜像所对应的PCI数据结构中的证书类型字段或该驱动的镜像所对应的PCI数据结构中的证书类型字段。
602、该BIOS从该PCIE设备读取PCIE设备的驱动，该驱动包括该签名数据。
本步骤602与步骤302所示的过程同理，在此，本申请实施例对本步骤602所示的过程不做赘述。
603、该BIOS对读取到的驱动进行验证。
本步骤603与步骤303所示的过程同理，在此，本申请实施例对本步骤603所示的过程不做赘述。
仍以图7为基础，BIOS基于该PCIE设备的公钥以及该第二解密算法，对该签名数据2进行解密，得到第二解密数据；该BIOS基于第二摘要计算算法，对驱动代码进行计算，得到驱动代码的第二摘要数据；若得到的第二摘要数据和该第二解密数据相同，则该驱动通过验证，否则，该驱动未通过验证。
604、若该驱动通过验证，该BIOS从读取到的该驱动中获取该签名数据。
该BIOS可以从驱动的镜像中，获取该固件代码的签名数据。在一种可能的实现方式中，该BIOS从该驱动的镜像中驱动代码的第三目标位置，获取该签名数据。
需要说明的是，步骤602和604所示的过程也即是BIOS从该PCIE设备的驱动中，获取该固件代码的签名数据的过程。
605、该BIOS从该PCIE设备读取该固件代码。
该BIOS可以从该PCIE设备的扩展ROM中读取该固件代码的镜像，以实现从该PCIE设备读取该固件代码。其中，BIOS从该PCIE设备的扩展ROM中读取该固件代码的镜像的过程与步骤304中BIOS读取该PCIE设备的固件的镜像的过程同理，在此，本申请实施例对BIOS从该PCIE设备的扩展ROM中读取该固件代码的镜像的过程不做赘述。
当该BIOS读取到该固件代码后，BIOS将该签名数据以及该固件代码确定为该固件。需要说明是，上述步骤602、604以及605所示的过程，也即是该计算机设备的输入输出系统BIOS获取所述PCIE设备的固件的过程。
606、该BIOS基于该签名数据，对固件代码进行验证。
该BIOS基于该PCIE设备的公钥以及该第一解密算法，对该签名数据进行解密，得到第一解密数据；该BIOS基于第一摘要计算算法，对固件代码进行计算，得到固件代码的第一摘要数据；若得到的第一摘要数据和该第一解密数据相同，则说明该固件代码未被篡改，固件代码是完整的，则该固件通过验证；若得到的第一摘要数据和该第一解密数据不同，则该说明固件代码已经被篡改，固件代码不完整，则该固件未通过验证。
仍以图7为基础，BIOS基于该PCIE设备的公钥以及该第一解密算法，对该签名数据1进行解密，得到第一解密数据；该BIOS基于第一摘要计算算法，对固件代码进行计算，得到固件代码的第一摘要数据；若得到的第一摘要数据和该第一解密数据相同，则该固件代码通过验证，否则，该固件代码未通过验证。
607、若该固件代码通过验证，该BIOS启动该PCIE设备。
本步骤607与步骤306所示的过程同理，在此，本申请实施例对本步骤607所示的过程不做赘述。
608、若该固件代码未通过验证，该BIOS不启动该PCIE设备。
本步骤608与步骤307所示的过程同理，在此，本申请实施例对本步骤608所示的过程不做赘述。
本申请实施例提供的方法，通过BIOS对PCIE设备的固件进行验证，以确定PCIE设备的固件是否被篡改，且BIOS仅能启动通过验证的固件所在的PCIE设备，从而避免计算机设备启动固件被篡改的PCIE设备，以降低PCIE设备对计算机设备造成的安全风险。并且，BIOS除了对PCIE设备进行验证以外，还对PCIE设备的驱动进行验证，只要固件和驱动中的任一 个未通过验证，则BIOS不启动该PCIE设备，从而避免计算机设备启动固件或驱动被篡改的PCIE设备，以进一步降低PCIE设备对计算机设备造成的安全风险。并且，通过BIOS控制未通过验证的固件所在的PCIE设备处于复位状态或者下电状态，或将未通过验证的固件所在的PCIE设备标记为禁止启动状态，从而彻底屏蔽有安全隐患的PCIE设备。
为了进一步综合说明图3以及图6所示的过程，参见图8所示的本申请实施例提供的一种PCIE设备启动方法的流程图。计算机设备上电或复位，计算机设备的BIOS的固件运行，BIOS枚举该计算机设备中的各个PCIE设备，每枚举到任一PCIE设备，BIOS对该PCIE设备的驱动进行验证，并运行通过验证的驱动；BIOS加载PCIE设备的固件；BIOS对加载的固件进行验证，若验证通过则BIOS正常配置该PCIE设备，以便该PCIE设备对计算机设备的OS可见，否则BIOS屏蔽该PCIE设备；当该BIOS加载完该计算机设备内的通过验证的所有PCIE设备，则该BIOS加载该OS。
需要说明的是，本申请中提及的“篡改”包括恶意篡改、无意修改、固件不完整、固件损坏、固件代码的代码量增加/减少、或者固件代码的内容的修改等多种情况。当BISO根据获取到的固件代码所计算出的第一摘要数据，与BIOS根据获取到的签名数据所计算出的第一解密数据不同时，说明BIOS获取到的固件已经被篡改。
图9是本申请实施例提供的一种PCIE设备启动装置的结构示意图，所述装置900包括PCIE设备901，所述装置900包括：
获取模块902，用于输入输出系统BIOS获取所述PCIE设备的固件；
验证模块903，用于所述BIOS对所述固件进行验证；
控制模块904，用于若所述固件通过验证，所述BIOS启动所述PCIE设备。
可选地，所述控制模块904还用于：
若所述固件未通过验证，所述BIOS不启动所述PCIE设备。
可选地，所述控制模块904还用于：
所述BIOS控制所述PCIE设备处于复位状态或者下电状态；
或，所述BIOS将所述PCIE设备标记为禁止启动状态，所述禁止启动状态用于指示不启动所述PCIE设备。
可选地，所述获取模块902用于：
所述BIOS从所述PCIE设备的扩展只读存储器ROM中读取所述固件的镜像。
可选地，所述固件包括签名数据，所述获取模块还用于：
所述BIOS从所述只读ROM中读取所述镜像的镜像类型以及所述签名数据的证书类型，所述镜像类型用于指示所述镜像的代码类型，所述证书类型用于指示计算所述签名数据时所使用的加密算法。
可选地，所述固件包括固件代码以及所述固件代码的签名数据；所述获取模块包括：
获取单元，用于所述BIOS从所述PCIE设备的驱动中，获取所述固件代码的签名数据；
读取单元，用于所述BIOS从所述PCIE设备读取所述固件代码。
可选地，所述读取单元用于：
所述BIOS从所述PCIE设备的扩展ROM中读取所述固件代码的镜像。
可选地，所述读取单元还用于：
所述BIOS从所述扩展ROM中读取所述镜像的镜像类型以及所述签名数据的证书类型， 所述镜像类型用于指示所述镜像的代码类型，所述证书类型用于指示计算所述签名数据时所使用的加密算法。
可选地，所述获取单元用于：
所述BIOS从所述PCIE设备的扩展ROM中读取所述驱动的镜像；
所述BIOS从所述驱动的镜像中，获取所述固件代码的签名数据。
可选地，所述验证模块903还用于：
所述BIOS对所述驱动进行验证；
若所述驱动通过验证，所述BIOS执行从所述PCIE设备读取所述固件代码的步骤。
可选地，所述BIOS存储有所述PCIE设备的公钥，所述公钥用于对所述固件进行验证。
可选地，所述装置900还包括：
修改模块，用于所述BIOS基于公钥修改指令，对存储的所述PCIE设备的公钥进行修改。
上述所有可选技术方案，可以采用任意结合形成本公开的可选实施例，在此不再一一赘述。
需要说明的是：上述实施例提供的PCIE设备启动装置在启动PCIE设备时，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。另外，上述实施例提供的PCIE设备启动方法实施例属于同一构思，其具体实现过程详见方法实施例，这里不再赘述。
本申请实施例还提供了一种计算机程序产品或计算机程序，该计算机程序产品或计算机程序包括计算机指令，该计算机指令存储在计算机可读存储介质中，计算机设备的处理器从计算机可读存储介质读取该计算机指令，处理器执行该计算机指令，使得该计算机设备执行上述PCIE设备启动方法。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (26)

  1. 一种快速外设组件互联PCIE设备启动方法，其特征在于，应用于包括PCIE设备的计算机设备，所述方法包括：
    所述计算机设备的输入输出系统BIOS获取所述PCIE设备的固件；
    所述BIOS对所述固件进行验证；
    若所述固件通过验证，所述BIOS启动所述PCIE设备。
  2. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    若所述固件未通过验证，所述BIOS不启动所述PCIE设备。
  3. 根据权利要求2所述的方法，其特征在于，所述BIOS不启动所述PCIE设备包括：
    所述BIOS控制所述PCIE设备处于复位状态或者下电状态；
    或，
    所述BIOS将所述PCIE设备标记为禁止启动状态，所述禁止启动状态用于指示不启动所述PCIE设备。
  4. 根据权利要求1-3任一项权利要求所述的方法，其特征在于，所述计算机设备的输入输出系统BIOS获取所述PCIE设备的固件包括：
    所述BIOS从所述PCIE设备的扩展只读存储器ROM中读取所述固件的镜像。
  5. 根据权利要求4所述的方法，其特征在于，所述固件包括签名数据，所述BIOS从所述PCIE设备的扩展只读存储器ROM中的读取所述固件的镜像之前，所述方法还包括：
    所述BIOS从所述只读ROM中读取所述镜像的镜像类型以及所述签名数据的证书类型，所述镜像类型用于指示所述镜像的代码类型，所述证书类型用于指示计算所述签名数据时所使用的加密算法。
  6. 根据权利要求1-3任一项权利要求所述的方法，其特征在于，所述固件包括固件代码以及所述固件代码的签名数据；
    所述计算机设备的输入输出系统BIOS获取所述PCIE设备的固件包括：
    所述BIOS从所述PCIE设备的驱动中，获取所述固件代码的签名数据；
    所述BIOS从所述PCIE设备读取所述固件代码。
  7. 根据权利要求6所述的方法，其特征在于，所述BIOS从所述PCIE设备读取所述固件代码包括：
    所述BIOS从所述PCIE设备的扩展ROM中读取所述固件代码的镜像。
  8. 根据权利要求7所述的方法，其特征在于，所述BIOS从所述PCIE设备的扩展ROM中的读取所述固件代码的镜像之前，所述方法还包括：
    所述BIOS从所述扩展ROM中读取所述镜像的镜像类型以及所述签名数据的证书类型，所述镜像类型用于指示所述镜像的代码类型，所述证书类型用于指示计算所述签名数据时所使用的加密算法。
  9. 根据权利要求6所述的方法，其特征在于，所述BIOS从所述PCIE设备的驱动中，获取所述固件代码的签名数据包括：
    所述BIOS从所述PCIE设备的扩展ROM中读取所述驱动的镜像；
    所述BIOS从所述驱动的镜像中，获取所述固件代码的签名数据。
  10. 根据权利要求6所述的方法，其特征在于，所述方法还包括：
    所述BIOS对所述驱动进行验证；
    若所述驱动通过验证，所述BIOS执行从所述PCIE设备读取所述固件代码的步骤。
  11. 根据权利要求1-10任一项权利要求所述的方法，其特征在于，所述BIOS存储有所述PCIE设备的公钥，所述公钥用于对所述固件进行验证。
  12. 根据权利要求11所述的方法，其特征在于，所述方法还包括：
    所述BIOS基于公钥修改指令，对存储的所述PCIE设备的公钥进行修改。
  13. 一种快速外设组件互联PCIE设备启动装置，其特征在于，所述装置包括PCIE设备，所述装置包括：
    获取模块，用于输入输出系统BIOS获取所述PCIE设备的固件；
    验证模块，用于所述BIOS对所述固件进行验证；
    控制模块，用于若所述固件通过验证，所述BIOS启动所述PCIE设备。
  14. 根据权利要求13所述的装置，其特征在于，所述控制模块还用于：
    若所述固件未通过验证，所述BIOS不启动所述PCIE设备。
  15. 根据权利要求14所述的装置，其特征在于，所述控制模块还用于：
    所述BIOS控制所述PCIE设备处于复位状态或者下电状态；
    或，
    所述BIOS将所述PCIE设备标记为禁止启动状态，所述禁止启动状态用于指示不启动所述PCIE设备。
  16. 根据权利要求13-15任一项权利要求所述的装置，其特征在于，所述获取模块用于：
    所述BIOS从所述PCIE设备的扩展只读存储器ROM中读取所述固件的镜像。
  17. 根据权利要求16任一项权利要求所述的装置，其特征在于，所述固件包括签名数据，所述获取模块还用于：
    所述BIOS从所述只读ROM中读取所述镜像的镜像类型以及所述签名数据的证书类型，所述镜像类型用于指示所述镜像的代码类型，所述证书类型用于指示计算所述签名数据时所使用的加密算法。
  18. 根据权利要求13-15任一项权利要求所述的装置，其特征在于，所述固件包括固件 代码以及所述固件代码的签名数据；所述获取模块包括：
    获取单元，用于所述BIOS从所述PCIE设备的驱动中，获取所述固件代码的签名数据；
    读取单元，用于所述BIOS从所述PCIE设备读取所述固件代码。
  19. 根据权利要求18所述的装置，其特征在于，所述读取单元用于：
    所述BIOS从所述PCIE设备的扩展ROM中读取所述固件代码的镜像。
  20. 根据权利要求19所述的装置，其特征在于，所述读取单元还用于：
    所述BIOS从所述扩展ROM中读取所述镜像的镜像类型以及所述签名数据的证书类型，所述镜像类型用于指示所述镜像的代码类型，所述证书类型用于指示计算所述签名数据时所使用的加密算法。
  21. 根据权利要求18所述的装置，其特征在于，所述获取单元用于：
    所述BIOS从所述PCIE设备的扩展ROM中读取所述驱动的镜像；
    所述BIOS从所述驱动的镜像中，获取所述固件代码的签名数据。
  22. 根据权利要求18所述的装置，其特征在于，所述验证模块还用于：
    所述BIOS对所述驱动进行验证；
    若所述驱动通过验证，所述BIOS执行从所述PCIE设备读取所述固件代码的步骤。
  23. 根据权利要求13-22任一项权利要求所述的装置，其特征在于，所述BIOS存储有所述PCIE设备的公钥，所述公钥用于对所述固件进行验证。
  24. 根据权利要求23所述的装置，其特征在于，所述装置还包括：
    修改模块，用于所述BIOS基于公钥修改指令，对存储的所述PCIE设备的公钥进行修改。
  25. 一种计算机可读存储介质，其特征在于，所述存储介质中存储有至少一条程序代码，所述程序代码由处理器加载并执行以实现如权利要求1至权利要求12任一项所述的快速外设组件互联PCIE设备启动方法所执行的操作。
  26. 一种计算机设备，其特征在于，所述计算机设备包括处理器和存储器，所述存储器中存储有至少一条程序代码，所述程序代码由所述处理器加载并执行以实现如权利要求1至权利要求12任一项所述的快速外设组件互联PCIE设备启动方法所执行的操作。
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