WO2022037178A1

WO2022037178A1 - Semiconductor device and method for forming same

Info

Publication number: WO2022037178A1
Application number: PCT/CN2021/097506
Authority: WO
Inventors: 赵亮
Original assignee: 长鑫存储技术有限公司
Priority date: 2020-08-21
Filing date: 2021-05-31
Publication date: 2022-02-24
Also published as: CN114078855A

Abstract

The present disclosure relates to the technical field of semiconductors, and provides a semiconductor device and a method for forming same. The semiconductor device of the present disclosure comprises a substrate, a capacitor array, and a support structure; a plurality of conductive contact plugs arranged at intervals are formed on the substrate; the capacitor array comprises a plurality of columnar capacitors arranged at intervals, the columnar capacitors are respectively formed on the conductive contact plugs, and a lower electrode of each columnar capacitor is in contact connection with the corresponding conductive contact plug; the support structure is formed on the substrate at the edge of the capacitor array, and surrounds the capacitor array; the distance between the inner wall and the outer wall of the support structure in any cross section parallel to the substrate is greater than the aperture of a capacitor hole of any columnar capacitor in the cross section. The semiconductor device of the present disclosure can perform lateral support on the outside of the capacitor array, thereby avoiding short circuit and increasing capacitance.

Description

Semiconductor device and method of forming the same

cross reference

This disclosure claims priority to the Chinese Patent Application No. 202010849895.1, entitled "Semiconductor Device and Method for Forming the Same," filed on August 21, 2020, the entire contents of which are incorporated herein by reference in their entirety.

technical field

The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for forming the same.

Background technique

With the continuous development of mobile devices, battery-powered mobile devices such as mobile phones, tablet computers, and wearable devices are more and more used in life. Small size and integration have put forward huge demands.

At present, Dynamic Random Access Memory (DRAM) is widely used in mobile devices due to its fast transmission speed. However, with the continuous shrinking of the volume, the size of the columnar storage capacitor in the dynamic random access memory is also shrinking, the density is also increasing, and the stability of the capacitor structure is also reduced.

It should be noted that the information disclosed in the above Background section is only for enhancement of understanding of the background of the present disclosure, and therefore may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.

public content

The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art, and to provide a semiconductor device and a method for forming the same, which can laterally support the outside of the capacitor array, avoid short circuits, and increase the capacitance.

According to one aspect of the present disclosure, there is provided a semiconductor device including:

a substrate, on which a plurality of conductive contact plugs arranged at intervals are formed;

A capacitor array, the capacitor array includes a plurality of column capacitors arranged at intervals, each of the column capacitors is formed on each of the conductive contact plugs, and the lower electrode layer of the column capacitor is in contact with the conductive contact plug ;

a support structure, the support structure is formed on the substrate at the edge of the capacitor array and surrounds the capacitor array, and the inner wall and the outer wall of the support structure are on any cross section parallel to the substrate The spacing is greater than the diameter of the capacitor hole on the cross section of any one of the column capacitors.

In an exemplary embodiment of the present disclosure, the conductive contact plug includes a first conductive contact plug and a second conductive contact plug, the first conductive contact plug is in contact with the lower electrode layer of the column capacitor, the A second conductive contact plug is in contact with the bottom of the support structure.

In an exemplary embodiment of the present disclosure, at least an insulating dielectric layer is formed on the substrate, and the capacitor array and the support structure are formed in the insulating dielectric layer.

In an exemplary embodiment of the present disclosure, an orthographic projection of the support structure on the second conductive contact plug coincides with a boundary of the second conductive contact plug.

In an exemplary embodiment of the present disclosure, the substrate includes a cell region and a peripheral region, the capacitor array is formed in the cell region, the conductive contact plug further includes a peripheral conductive contact plug, the peripheral conductive Contact plugs are formed in the peripheral region, and the semiconductor device further includes an interconnect structure connected to the peripheral conductive contact plug, the interconnect structure formed in the insulating dielectric layer.

In an exemplary embodiment of the present disclosure, the insulating dielectric layer includes a first insulating dielectric layer and a second insulating dielectric layer spaced along a direction perpendicular to the substrate, the capacitor array and the A support structure is formed in the first insulating dielectric layer and the second insulating dielectric layer.

According to one aspect of the present disclosure, there is provided a method of forming a semiconductor device, the forming method comprising:

provide a substrate;

forming a plurality of spaced-apart conductive contact plugs on the substrate;

A capacitor array is formed, the capacitor array includes a plurality of column capacitors arranged at intervals, each of the column capacitors is formed on each of the conductive contact plugs, and the lower electrode layer of the column capacitor is in contact with the conductive contact plug connect;

A support structure is formed, the support structure is formed on the substrate at the edge of the capacitor array, and surrounds the capacitor array, and the inner wall and the outer wall of the support structure are in any cross-section parallel to the substrate The distance between the capacitor holes is larger than the diameter of the capacitor holes on the cross section of any one of the column capacitors.

In an exemplary embodiment of the present disclosure, the substrate has a unit area, a plurality of conductive contact plugs arranged at intervals are formed on the unit area, and the conductive contact plugs are located at the edge of the unit area The width of the conductive contact plug is greater than the width of the non-edge conductive contact plug in the unit area, and the forming the capacitor array and the supporting structure includes:

A sacrificial layer and an insulating dielectric layer are sequentially formed on the substrate, the conductive contact plug is used as an etch stop layer, the sacrificial layer and the insulating dielectric layer in the unit area are etched, and multiple layers are formed in the unit area. Columnar void structures are arranged at intervals, and the etching window is controlled so that the cross-sectional spacing of the columnar void structures located at the periphery of the cell region in the direction parallel to the substrate is greater than that of the non-periphery columnar void structures in the cell region the cross-sectional spacing;

depositing a lower electrode material to form a lower electrode layer on the sidewall of the columnar void structure;

depositing a dielectric material, the dielectric material filling the columnar void structures at the periphery of the cell region to form the support structure, and the non-peripheral columnar void structures in the cell region being unfilled;

removing the sacrificial layer in the unit region, leaving the insulating dielectric layer;

A capacitor dielectric layer and an upper electrode layer are sequentially formed on the lower electrode layer of the non-peripheral columnar void structure in the unit area to form a capacitor array.

In an exemplary embodiment of the present disclosure, the substrate further has a peripheral region, and before etching the sacrificial layer and the insulating dielectric layer in the unit region, the forming method further includes:

An interconnect structure is formed in the peripheral region.

In an exemplary embodiment of the present disclosure, forming the interconnect structure includes:

forming the conductive contact plugs in the peripheral region while forming the conductive contact plugs on the cell region of the substrate;

forming a first sacrificial layer in the peripheral region;

Using the conductive contact plug in the peripheral region as an etch stop layer, etching the first sacrificial layer to form a first via hole;

A first interconnect structure is formed in the first via.

In an exemplary embodiment of the present disclosure, after forming the first interconnect structure, the forming method further includes:

The insulating dielectric layer and the second sacrificial layer are sequentially formed on the first sacrificial layer in the peripheral region, and the insulating dielectric layer and the second sacrificial layer are etched using the first interconnect structure as an etch stop layer. , to form a second via;

A second interconnect structure is formed in the second via.

In the semiconductor device and its forming method of the present disclosure, since the support structure surrounds the outside of the capacitor array, the outside of the capacitor array can be laterally supported, thereby increasing the lateral stability of the capacitor array, preventing lateral deformation of the capacitors in the capacitor array, and avoiding short circuits. At the same time, since the distance between the inner wall and the outer wall of the support structure on any cross section parallel to the substrate is larger than the aperture of any capacitor hole in the capacitor array on the cross section, the support strength of the support structure can be guaranteed. In addition, since the capacitor array includes multiple capacitors, the multiple capacitors can be charged and discharged at the same time during use, thereby increasing the capacitance.

It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description serve to explain the principles of the disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and for those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

FIG. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the disclosure.

FIG. 2 is a schematic structural diagram of a capacitor hole and an annular ring according to an embodiment of the present disclosure.

FIG. 3 is a schematic structural diagram of a lower electrode layer according to an embodiment of the disclosure.

FIG. 4 is a schematic structural diagram of a support structure according to an embodiment of the present disclosure.

FIG. 5 is a schematic structural diagram of a semiconductor layer according to an embodiment of the disclosure.

FIG. 6 is a schematic structural diagram of an insulating dielectric layer according to an embodiment of the disclosure.

FIG. 7 is a schematic structural diagram of a first via hole according to an embodiment of the present disclosure.

FIG. 8 is a schematic structural diagram of a connection layer according to an embodiment of the present disclosure.

9 is a flowchart of a method of forming a semiconductor device according to an embodiment of the disclosure.

FIG. 10 is a flow chart of forming a capacitor array and a support structure in an embodiment of the disclosure.

FIG. 11 is a schematic structural diagram of an insulating dielectric layer and a sacrificial layer according to an embodiment of the disclosure.

FIG. 12 is a schematic structural diagram of forming a photoresist on an insulating dielectric layer according to an embodiment of the present disclosure.

13 is a schematic structural diagram of a lower electrode layer covering a capacitor hole and its top surface in an embodiment of the disclosure.

FIG. 14 is a schematic structural diagram of a cover layer according to an embodiment of the disclosure.

FIG. 15 is a schematic diagram of a structure after forming a photoresist on the cover layer according to an embodiment of the present disclosure.

FIG. 16 is a schematic structural diagram of an opening formed in a cover layer according to an embodiment of the present disclosure.

FIG. 17 is a schematic structural diagram of an embodiment of the present disclosure after removing the top sacrificial layer.

FIG. 18 is a schematic structural diagram of a cover layer after planarization processing is performed according to an embodiment of the present disclosure.

FIG. 19 is a flowchart corresponding to step S160 in FIG. 9 .

In the figure: 1, substrate; 11, unit area; 12, peripheral area; 2, conductive contact plug; 21, first conductive contact plug; 22, second conductive contact plug; 23, peripheral conductive contact plug; 3, capacitor Array; 31, insulating layer; 32, insulating medium layer; 321, first sacrificial layer; 322, first insulating medium layer; 323, second sacrificial layer; 324, second insulating medium layer; 3341, photoresist layer; 33, lower electrode layer; 34, capacitor dielectric layer; 35, upper electrode layer; 37, capacitor hole; 4, support structure; 41, annular ring; 5, semiconductor layer; 6, first interconnect structure; 61, first 62, connection layer; 63, lead-out layer; 7, cover layer; 71, opening.

detailed description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments, however, can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, such as according to the direction of the example described. It will be appreciated that if the device of the icon is turned upside down, the components described as "on" will become the components on "bottom". When a certain structure is "on" other structures, it may mean that a certain structure is integrally formed on other structures, or that a certain structure is "directly" arranged on other structures, or that a certain structure is "indirectly" arranged on another structure through another structure. other structures.

The terms "a", "an", "the" and "said" are used to indicate the presence of one or more elements/components/etc; the terms "including" and "having" are used to indicate open-ended inclusive means and means that additional elements/components/etc may be present in addition to the listed elements/components/etc. The terms "first" and "second" are used only as labels and are not intended to limit the number of their objects.

Embodiments of the present disclosure provide a semiconductor device. As shown in FIG. 1 , the semiconductor device may include a substrate 1 , a capacitor array 3 and a support structure 4 , wherein:

A plurality of conductive contact plugs 2 arranged at intervals are formed on the substrate 1;

The capacitor array 3 includes a plurality of column capacitors arranged at intervals, each column capacitor is formed on each conductive contact plug 2, and the lower electrode layer 33 of the column capacitor is in contact with the conductive contact plug 2;

The support structure 4 is formed on the substrate 1 at the edge of the capacitor array 3 and surrounds the capacitor array 3, and the distance between the inner wall and the outer wall of the support structure 4 on any cross section parallel to the substrate 1 is greater than the capacitance of any column capacitor The diameter of the hole in the cross section.

In the semiconductor device of the present disclosure, since the support structure 4 surrounds the outside of the capacitor array 3, the outside of the capacitor array 3 can be laterally supported, thereby increasing the lateral stability of the capacitor array 3, preventing lateral deformation of the capacitors in the capacitor array 3, and avoiding At the same time, since the distance between the inner wall and the outer wall of the support structure 4 on any cross section parallel to the substrate 1 is greater than the aperture of any capacitor hole in the capacitor array 3 on the cross section, the support strength of the support structure 4 can be guaranteed. . In addition, since the capacitor array 3 includes a plurality of capacitors, in use, the plurality of capacitors can be charged and discharged at the same time, thereby increasing the capacitance.

Each part of the semiconductor device according to the embodiment of the present disclosure will be described in detail below:

As shown in FIG. 1 , the substrate 1 can have a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular, and its material can be silicon or other semiconductor materials. Materials are subject to special restrictions.

A plurality of conductive contact plugs 2 can be formed on the substrate 1 at intervals. For example, the conductive contact plugs 2 can be formed on the substrate 1 by vacuum evaporation, magnetron sputtering or chemical vapor deposition. Of course, the conductive contact plugs 2 can be formed on the substrate 1. , the conductive contact plugs 2 may also be formed in other ways, which will not be listed one by one here.

In one embodiment, the conductive contact plug 2 may include a first conductive contact plug 21 and a second conductive contact plug 22, and the second conductive contact plug 22 may be an annular structure, which may be a circular ring or a rectangular ring; The second conductive contact plug 22 may be made of conductor or semiconductor material, for example, the material may be tungsten, copper or polysilicon. There can be a plurality of first conductive contact plugs 21 , the plurality of first conductive contact plugs 21 can be located in the annular shape of the second conductive contact plugs 22 , and can be distributed in an array, and the material of the first conductive contact plugs 21 can be the same as that of the second conductive contact plugs 21 . The material of the conductive contact plugs 22 is the same.

As shown in FIG. 2, the substrate 1 may include a unit area 11 and a peripheral area 12 arranged side by side, a capacitor array 3 may be formed on the substrate 1 and may be located on the unit area 11, and the capacitor array 3 may include a plurality of spaced rows As for the cloth column capacitors, each column capacitor can be formed on each conductive contact plug 2 respectively, and specifically, each column capacitor can be formed on each first conductive contact plug 21 respectively. When in use, multiple capacitors can be charged and discharged at the same time, thereby increasing the capacitance.

In an embodiment of the present disclosure, the capacitor array 3 may include an insulating layer 31 , an insulating medium layer 32 , a lower electrode layer 33 , a capacitor medium layer 34 and an upper electrode layer 35 . The insulating layer 31 is distributed between the first conductive contact plugs 21 and can be used to separate the first conductive contact plugs 21 ; the lower electrode layer 33 can be in the shape of a strip, which can be formed on the first conductive contact plug 21 away from the substrate 1 . one side, and can be in contact with the first conductive contact plug 21, and can extend to the side of the first conductive contact plug 21 away from the substrate 1 along the direction perpendicular to the contact direction of the first conductive contact plug 21, so as to form a columnar capacitor . The capacitor dielectric layer 34 is located between the lower electrode layer 33 and the upper electrode layer 35 to form a double-sided capacitor, so as to improve the capacitance. The insulating medium layer 32 can cover the outer periphery of the lower electrode layer 33 , can support the lower electrode layer 33 laterally, increase the stability of the lower electrode layer 33 in the lateral direction, and prevent the lower electrode layer 33 from being deformed laterally.

For example, the insulating layer 31 can be formed on the substrate 1. The insulating layer 31 can be formed on the substrate 1 by vacuum evaporation, magnetron sputtering or chemical vapor deposition. Of course, the insulating layer 31 can also be formed by other methods. Layer 31 will not be listed one by one here. The shape of the insulating layer 31 may be the same as that of the substrate 1 , and the material thereof may be silicon nitride, silicon oxide, etc., and the material thereof is not limited herein.

The insulating layer 31 can be provided with an annular hole and a plurality of openings arranged in an array inside the annular hole. The annular hole and each opening can be a through hole, and the annular hole can be a circular ring or a rectangular ring. The shape of the annular hole and each opening is not particularly limited here.

The second conductive contact plugs 22 may be formed in the annular holes, and at the same time, the first conductive contact plugs 21 may be formed in each opening, and the second conductive contact plugs 22 and a plurality of first conductive contact plugs 21 may be formed simultaneously in one process, For example, the second conductive contact plugs 22 and the plurality of first conductive contact plugs 21 may be simultaneously formed through a chemical vapor deposition process. In one embodiment, the second conductive contact plugs 22 can be in contact with the substrate 1 through the annular hole, and at the same time, each of the first conductive contact plugs 21 can be in contact with the substrate 1 through each opening.

At least an insulating dielectric layer 32 is formed on the substrate 1 . For example, an insulating dielectric layer 32 can be formed on the side of the insulating layer 31 away from the substrate 1 , and the insulating dielectric layer 32 can cover both the cell region 11 and the peripheral region 12 . Both the capacitor array 3 and the supporting structure 4 can be formed in the insulating dielectric layer 32 opposite to the unit region 11 , that is, the insulating dielectric layer 32 can be used to support the capacitors.

As shown in FIG. 2 , the insulating dielectric layer 32 may have a plurality of through holes exposing the first conductive contact plugs 21 respectively. The through holes may be capacitor holes 37 , which may be used to form capacitors. Each capacitor hole 37 may be perpendicular to the insulating medium. The direction of the layer 32 runs through the insulating dielectric layer 32 , and the cross-sectional shape of the layer 32 may be a circle, a rectangle, etc., or an irregular shape, and the shape of the capacitor hole 37 is not particularly limited herein. The through hole can also include an annular ring 41, which can be used to form the support structure 4, which can be a circular ring or a rectangular ring, which is not limited herein.

For example, the insulating medium layer 32 may include a first insulating medium layer 322 and a second insulating medium layer 324 spaced along a direction perpendicular to the substrate 1, which may be deposited by vacuum evaporation, magnetron sputtering or chemical vapor deposition The first insulating dielectric layer 322 and the second insulating dielectric layer 324 can be formed in the same manner. Of course, the insulating dielectric layer 32 can also be formed by other processes, which are not limited herein.

Both the capacitor array 3 and the support structure 4 can be formed in the first insulating dielectric layer 322 and the second insulating dielectric layer 324 , and the capacitors inside the capacitor array 3 can be adjusted through the first insulating dielectric layer 322 and the second insulating dielectric layer 324 . At the same time, the edge of the capacitor array 3 can be supported by the support structure 4 .

As shown in FIG. 3 , a lower electrode layer 33 can be formed in the capacitor hole 37 to conform to the bottom and the sidewall surface of the capacitor hole 37 , and the lower electrode layer 33 can be in contact with the first conductive contact plug 21 through the capacitor hole 37 connected to input the electricity stored in the lower electrode layer 33 to the first conductive contact plug 21 to realize capacitance storage. For example, the chemical vapor deposition process can be used to form the lower electrode layer 33 in the capacitor hole 37 , and of course, the lower electrode layer 33 can also be formed by other processes, which is not limited herein. The material of the lower electrode layer 33 may be titanium nitride, and its thickness may be 4 nm to 10 nm, for example, it may be 4 nm, 6 nm, 8 nm or 10 nm. Of course, the lower electrode layer 33 may also be made of other materials or other thicknesses. I will not list them one by one here.

As shown in FIG. 1 , the capacitor dielectric layer 34 may be a thin film formed on the outer surface and the inner surface of the structure composed of the lower electrode layer 33 and the insulating dielectric layer 32, and may be formed by vacuum evaporation or magnetron sputtering. Of course, the capacitive dielectric layer 34 can also be formed by other processes, which will not be listed here. The capacitor dielectric layer 34 may be a single-layer film structure composed of the same material, or may be a mixed film layer structure composed of film layers of different materials. For example, it may include a material with a higher dielectric constant, for example, it may be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, or mixtures thereof, of course, It can also be other materials, which will not be listed one by one here.

The upper electrode layer 35 may be formed on the outer surface of the capacitor dielectric layer 34 by a chemical vapor deposition process. Of course, the upper electrode layer 35 may also be formed by other processes, which are not limited herein. The material of the upper electrode layer 35 can be titanium nitride, and its thickness can be 2nm-8nm, for example, it can be 2nm, 4nm, 6nm or 8nm, of course, the upper electrode layer 35 can also be other materials or other thicknesses, I will not list them one by one here.

The support structure 4 may be formed on the substrate 1, which may be located at the edge of the capacitor array 3, and may surround the periphery of the capacitor array 3. For example, as shown in FIG. 4, the support structure 4 may be formed on the second conductive contact The plug 22 faces away from the surface of the substrate 1 , the bottom of which can be in contact with the second conductive contact plug 22 . The support structure 4 may be formed on the surface of the second conductive contact plug 22 facing away from the substrate 1 by means of vacuum evaporation, magnetron sputtering or chemical vapor deposition. The support structure 4 may be of the same material as the insulating dielectric layer 32, for example, it may be silicon nitride.

The support structure 4 can be in contact with the capacitor array 3, for example, it can be in contact with the insulating dielectric layer 32 in the capacitor array 3, so as to support the capacitors located at the edge of the capacitor array 3 all around, increasing the capacitor array 3 The stability in the lateral direction prevents the lateral deformation of the capacitors located at the edge of the capacitor array 3 and avoids short circuits.

The spacing between the inner wall and the outer wall of the support structure 4 on any cross section parallel to the substrate 1 is greater than the aperture of the capacitor hole 37 of any column capacitor in the capacitor array 3 on the cross section, which can ensure that the support structure 4 is positioned opposite to the capacitor array. 3 The support strength of the capacitor at the edge part. For example, the distance between the inner wall and the outer wall of the support structure 4 on any cross section parallel to the substrate 1 may be at least twice the diameter of any capacitor hole 37 in the capacitor array 3 on the cross section. Of course, the minimum value of the distance between the inner wall and the outer wall of the support structure 4 may also be greater than the maximum value of the diameter of any capacitor hole 37 .

At the same time, in order to ensure the support strength for the top of the capacitor, the distance between the inner wall and the outer wall of the support structure 4 can be increased sequentially from the side close to the substrate 1 to the side away from the substrate 1 . In all cross sections, the distance between the inner wall and the outer wall can also be equal, and the size between the inner wall and the outer wall of the support structure 4 is not particularly limited here.

In one embodiment, the orthographic projection of the support structure 4 on the second conductive contact plug 22 can be coincident with the boundary of the second conductive contact plug 22, that is, the support structure 4 can be a continuous whole, which can be continuously wrapped around the second conductive contact plug 22. Outside the capacitor array 3, so as to continuously support the edge portion of the capacitor array 3. In another embodiment, the supporting structure 4 may be a discontinuous segment, which may include a plurality of supporting regions distributed at intervals and a one-to-one corresponding supporting column formed on each supporting region, and the thickness of each supporting column may be equal. , and can be encircled in a ring shape, and each support column can be respectively contacted and connected with the insulating medium layer 32 of the capacitor array 3 , so as to support the capacitor array 3 in sections.

The thickness of the support structure 4 in the direction perpendicular to the substrate 1 can be equal to the height of each capacitor in the capacitor array 3 in the direction perpendicular to the substrate 1, which can support the capacitor array 3 in the lateral direction, and can also The capacitor array 3 is supported in the longitudinal direction to improve the stability of the device. For example, the thickness of the support structure 4 in the direction perpendicular to the substrate 1 can be equal to the height of the lower electrode layer 33 in the direction perpendicular to the substrate 1, and the capacitors located at the edge of the capacitor array 3 can be adjusted by the support structure 4. The lower electrode layer 33 of the capacitor array 3 is supported laterally and vertically to prevent the lower electrode layer 33 of the capacitor located at the edge of the capacitor array 3 from deforming outward.

In one embodiment, as shown in FIG. 1 , FIG. 5 and FIG. 6 , the semiconductor device of the present disclosure may further include a semiconductor layer 5 , which may cover the surface of the capacitor array 3 and may be filled with capacitor holes 37 and capacitors. The gap between two adjacent capacitors in array 3,

The semiconductor layer 5 covering the capacitor array 3 can be formed on the surface of the upper electrode layer 35 by a vacuum evaporation process, so that the electric charges can be fully contacted with the second electrode, which helps to improve the charging efficiency of the capacitor. As shown in FIG. 5, the semiconductor layer 5 can cover the surface of the capacitor array 3, and can fill the capacitor hole 37 and the gap between two adjacent capacitors in the capacitor array 3, which can improve the electrical conductivity of the device and strengthen the capacitor array. The stability of each capacitor in 3. The semiconductor layer 5 may be composed of silicon material, metal material or metal compound, for example, it may be silicon, silicon germanium, tungsten, titanium silicide, titanium oxide or tungsten oxide, etc., which is not limited herein.

In one embodiment, the conductive contact plugs 2 may further include peripheral conductive contact plugs 23, which may be formed in the peripheral region 12 of the substrate 1, and the semiconductor device of the present disclosure may further include an interconnect structure that The interconnection structure can be formed in the insulating medium layer 32 corresponding to the peripheral region 12 , and can be in contact with the peripheral conductive contact plug 23 so as to electrically lead out the capacitor array 3 . The peripheral conductive contact plugs 23 can be made of the same material as the first conductive contact plugs 21 and the second conductive contact plugs 22 and have the same thickness, and the peripheral conductive contact plugs can be formed at the same time as the first conductive contact plugs 21 and the second conductive contact plugs 22 are formed twenty three.

As shown in FIGS. 7-8 , the first interconnect structure 6 can be formed in the first via hole 61 by a chemical vapor deposition process, and the first interconnect structure 6 can be communicated with the semiconductor layer 5 through the first via hole 61 , In order to lead out the capacitor array 3 electrically.

The first interconnection structure 6 may include a connection layer 62 and an extraction layer 63. The connection layer 62 may be attached to the hole wall and bottom surface of the first via hole 61, and may communicate with the top of the semiconductor layer 5. The extraction layer 63 may be connected to the top of the semiconductor layer 5. It is located on the connection layer 62 and can fill the first via hole 61 . Both the connection layer 62 and the extraction layer 63 can be made of conductive materials, for example, the connection layer 62 can be made of titanium nitride, and the extraction layer 63 can be made of tungsten.

Embodiments of the present disclosure also provide a method for forming a semiconductor device. As shown in FIG. 9 , the forming method may include:

Step S110, providing a substrate;

Step S120, forming a plurality of conductive contact plugs arranged at intervals on the substrate;

Step S130, forming a capacitor array, the capacitor array includes a plurality of column capacitors arranged at intervals, each of the column capacitors is formed on each of the conductive contact plugs, and the lower electrode layer of the column capacitor is connected to the conductive contact plug. contact plug contact connection;

Step S140, forming a support structure, the support structure is formed on the substrate at the edge of the capacitor array, and surrounds the capacitor array, and the inner wall and the outer wall of the support structure are in any position parallel to the substrate. The spacing on a cross section is larger than the diameter of the capacitor hole of any one of the column capacitors on the cross section.

In the method for forming a semiconductor device of the present disclosure, since the support structure 4 surrounds the outside of the capacitor array 3, the outside of the capacitor array 3 can be laterally supported, thereby increasing the lateral stability of the capacitor array 3 and preventing the capacitors in the capacitor array 3 from generating lateral deformation to avoid short circuit; at the same time, since the spacing between the inner wall and the outer wall of the support structure 4 on any cross-section parallel to the substrate 1 is greater than the aperture of any capacitor hole 37 in the capacitor array 3 on the cross-section, the support structure can be guaranteed. 4. Support strength. In addition, since the capacitor array 3 includes a plurality of capacitors, in use, the plurality of capacitors can be charged and discharged at the same time, thereby increasing the capacitance.

Each step of the method for forming the embodiment of the present disclosure will be described in detail below:

In step S110, a substrate is provided.

The substrate 1 may have a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular, and its material may be silicon or other semiconductor materials. The shape and material of the substrate 1 are not particularly limited herein.

In step S120, a plurality of spaced conductive contact plugs are formed on the substrate.

In one embodiment, the conductive contact plug 2 may include a first conductive contact plug 21 and a second conductive contact plug 22, and the second conductive contact plug 22 may be an annular structure, which may be a circular ring or a rectangular ring; The second conductive contact plug 22 may be made of conductor or semiconductor material, for example, the material may be tungsten, copper or polysilicon. There can be a plurality of first conductive contact plugs 21 , the plurality of first conductive contact plugs 21 can be located in the annular shape of the second conductive contact plugs 22 , and can be distributed in an array, and the material of the first conductive contact plugs 21 can be the same as that of the second conductive contact plugs 21 . The material of the conductive contact plugs 22 is the same. The substrate 1 may include a cell region 11 and a peripheral region 12 arranged side by side, and the first conductive contact plugs 21 and the second conductive contact plugs 22 are formed in the cell region 11 .

In step S130, a capacitor array is formed, the capacitor array includes a plurality of column capacitors arranged at intervals, each of the column capacitors is respectively formed on each of the conductive contact plugs, and the lower electrode layer of the column capacitor is connected to all the column capacitors. The conductive contact plugs make contact connections.

The capacitor array 3 can be formed on the substrate 1 and can be located on the unit area 11. The capacitor array 3 can include a plurality of column capacitors arranged at intervals, and each column capacitor can be formed on each conductive contact plug. Specifically, Each column capacitor may be formed on each first conductive contact plug 21 , respectively. When in use, multiple capacitors can be charged and discharged at the same time, thereby increasing the capacitance.

Both the capacitor array 3 and the support structure 4 can be formed in the first insulating dielectric layer 322 and the second insulating dielectric layer 324 , and the capacitors inside the capacitor array 3 can be processed through the first insulating dielectric layer 322 and the second insulating dielectric layer 324 . At the same time, the edge of the capacitor array 3 can be supported by the support structure 4 .

In step S140, a support structure is formed, the support structure is formed on the substrate at the edge of the capacitor array, and surrounds the capacitor array, and the inner wall and the outer wall of the support structure are parallel to the substrate The spacing on any cross-section is greater than the diameter of the capacitor hole of any of the column capacitors on the cross-section.

In one embodiment, forming the capacitor array 3 and the supporting structure 4 on the substrate 1 may include steps S210 to S250, as shown in FIG. 10 , wherein:

Step S210, forming a sacrificial layer and an insulating dielectric layer on the substrate in sequence, using the conductive contact plug as an etch stop layer, etching the sacrificial layer and the insulating dielectric layer in the unit area, and etching the sacrificial layer and the insulating dielectric layer in the unit area. The area forms a plurality of columnar void structures arranged at intervals, and the etching window is controlled so that the cross-sectional spacing of the columnar void structures located at the periphery of the unit area in the direction parallel to the substrate is greater than that of the non-periphery in the unit area. The cross-sectional spacing of the columnar void structures.

The insulating layer 31 can be formed on the substrate 1 by vacuum evaporation, magnetron sputtering or chemical vapor deposition, etc. Of course, the insulating layer 31 can also be formed by other methods, which will not be listed here. The shape of the insulating layer 31 may be the same as that of the substrate 1 , and the material thereof may be silicon nitride, silicon oxide, etc., and the material thereof is not limited herein.

The pattern in the mask can be transferred to the insulating layer 31 by a photolithography process. The mask can be grid-shaped, and the pattern on it can be the same as the pattern required for the annular hole and each opening, so that the insulating layer 31 can be formed. An annular hole and a plurality of openings arranged in an array are formed inside the annular hole, the annular hole and each opening can be a through hole, the annular hole can be a circular ring or a rectangular ring, and each opening can be circular, It can also be rectangular or irregular, and the shape of the annular hole and each opening is not limited here.

An overlapping sacrificial layer and an insulating dielectric layer 32 may be sequentially formed on the surface of the structure formed by each of the first conductive contact plugs 21 , the second conductive contact plugs 22 and the substrate 1 by chemical vapor deposition or physical vapor deposition. As shown in FIG. 11 , it may include a first sacrificial layer 321 , a first insulating dielectric layer 322 , a second sacrificial layer 323 and a second insulating dielectric layer 324 , which are stacked in sequence, which can be formed by vacuum evaporation or magnetron sputtering. The first sacrificial layer 321, the first insulating dielectric layer 322, the second sacrificial layer 323, and the second insulating dielectric layer 324 are formed in other ways. The dielectric layer 322 , the second sacrificial layer 323 and the second insulating dielectric layer 324 are not particularly limited herein.

The first sacrificial layer 321 can be formed on the surface of the structure formed by the first conductive contact plugs 21, the second conductive contact plugs 22 and the substrate 1, and its material can be SiO2; the first insulating dielectric layer 322 can be formed on the surface of the structure. A thin film on the side of the sacrificial layer 321 away from the substrate 1 can be made of silicon nitride or SiCN; the second sacrificial layer 323 can be formed on the side of the first insulating dielectric layer 322 away from the first sacrificial layer 321, and can be The material and thickness of the first sacrificial layer 321 are the same, and the top surfaces of the first sacrificial layer 321 and the second sacrificial layer 323 may be polished by a chemical polishing process, so that the first sacrificial layer 321 and the second sacrificial layer 323 The thickness of each part is uniform; the second insulating dielectric layer 324 can be formed on the side of the second sacrificial layer 323 away from the first insulating dielectric layer 322, and can be made of the same material as the first insulating dielectric layer 322. It should be noted that , the thickness of each insulating dielectric layer 32 may be the same or different, which is not particularly limited here.

A photoresist layer 3341 may be formed on the second insulating medium layer 324 by spin coating or other methods, and the material of the photoresist layer 3341 may be positive photoresist or negative photoresist, which is not limited herein. The shape of the surface of the photoresist layer 3341 away from the second insulating medium layer 324 may be the same as the shape of the surface of the second insulating medium layer 324 . The photoresist layer 3341 can be exposed using a mask, the pattern of which can be matched to the desired pattern of the annular ring 41 and each capacitor hole 37 . Subsequently, the exposed photoresist layer 3341 can be developed to form a developed area, as shown in FIG. 12 , the second insulating medium layer 324 can be exposed in the developed area, and the pattern of the developed area can be matched with the annular ring 41 and the respective The required pattern of the capacitor holes 37 is the same, and the size of the developing area can be the same as the required size of the annular ring 41 and each capacitor hole 37 .

The first sacrificial layer 321, the first insulating dielectric layer 322, the second sacrificial layer 323 and the second insulating dielectric layer 324 can be etched in the developing area by dry etching, and the conductive contact plug 2 is used as the etching stop layer, A plurality of columnar void structures arranged at intervals are formed in the unit region 11 , and the columnar void structures can expose the second conductive contact plug 22 and each of the first conductive contact plugs 21 . At the same time, the opening size of the columnar void structure can be controlled so that The cross-sectional spacing of the columnar void structures located at the periphery of the cell region 11 in the direction parallel to the substrate 1 is greater than the cross-sectional spacing of the non-peripheral columnar void structures in the cell region 11 . In order to facilitate the distinction, the columnar pore structure corresponding to the first conductive contact plug 21 may be used as the capacitor hole 37, and the columnar pore structure corresponding to the second conductive contact plug 22 may be used as the annular ring 41.

In order to increase the capacity of the capacitor, the size of each capacitor hole 37 can be sequentially increased from the side close to the substrate 1 to the side away from the substrate 1. Of course, each capacitor hole 37 can also be a straight hole. The size is specially limited. At the same time, in order to ensure the support strength for the top of the capacitor, the distance between the inner wall and the outer wall of the annular ring 41 can be increased sequentially from the side close to the substrate 1 to the side away from the substrate 1 . In all cross sections, the distance between the inner wall and the outer wall can also be equal, and the size between the inner wall and the outer wall of the annular ring 41 is not particularly limited here.

Step S220, depositing a lower electrode material, and forming a lower electrode layer on the sidewall of the columnar void structure.

The lower electrode layer 33 can be formed on the sidewall of the columnar void structure. Specifically, the lower electrode layer 33 can be formed in the capacitor hole 37 to conform to the bottom of the capacitor hole 37 and the surface of the sidewall, as shown in FIG. 13 . For the convenience of the process, the lower electrode layer 33 can be formed in the capacitor hole 37 and its top surface at the same time, and then the lower electrode layer 33 on the top surface of the capacitor hole 37 can be removed, and only the bottom electrode layer 33 on the bottom and sidewalls of the capacitor hole 37 can be left, and finally The formed lower electrode layer 33 is shown in FIG. 3 . In addition, the lower electrode layer 33 can be in contact with the first conductive contact plug 21 through the capacitor hole 37 to input the electricity stored in the lower electrode layer 33 to the storage dielectric contact plug, thereby realizing capacitance storage.

For example, the chemical vapor deposition process can be used to form the lower electrode layer 33 in the capacitor hole 37 , and of course, the lower electrode layer 33 can also be formed by other processes, which is not limited herein. The material of the lower electrode layer 33 may be titanium nitride, and its thickness may be 4 nm to 10 nm, for example, it may be 4 nm, 6 nm, 8 nm or 10 nm. Of course, the lower electrode layer 33 may also be made of other materials or other thicknesses. I will not list them one by one here. In addition, for the convenience of the process, the lower electrode layer 33 may also be formed in the annular ring 41 at the same time.

Step S230 , depositing a dielectric material, the dielectric material filling the columnar void structures at the periphery of the cell region to form the support structure, and the non-periphery columnar void structures in the cell region are not filled.

A chemical vapor deposition process can be used to deposit a dielectric material on the surface of the second insulating dielectric layer 324 facing away from the second sacrificial layer 323 and in the annular ring 41 to form a cover layer 7, as shown in FIG. 14, the cover layer 7 can fill the cell The columnar void structure at the periphery of the area 11 is filled with the annular ring 41 to form the support structure 4 . At this time, the columnar void structure at the non-periphery of the cell area 11 is not filled, that is, the capacitor hole 37 is not filled. At the same time, a mask material layer can be formed on the side of the insulating dielectric layer 32 farthest from the substrate 1 away from the substrate 1 by chemical vapor deposition or other methods, and the mask material layer can cover the capacitor hole 37 away from the first conductive contact. one side of the plug 21. The material of the mask material layer may be at least one of silicon oxide, oxynitride or carbon, and of course, may also be other materials, which will not be listed here. The mask material layer may be a single-layer structure or a multi-layer structure, which is not particularly limited here.

The photoresist layer 3341 may be formed on the mask material layer by spin coating or other methods, and the material of the photoresist layer 3341 may be positive photoresist or negative photoresist, which is not limited herein. As shown in FIG. 15 , the photoresist layer 3341 can be exposed using a mask, and the pattern of the mask can match the desired pattern of the opening on the insulating medium layer 32 farthest from the substrate 1 , as shown in FIG. 16 . As shown, the orthographic projection of the opening 71 on the substrate 1 may cover the area between two adjacent capacitor holes 37 . Subsequently, the exposed photoresist layer 3341 may be developed to form a development area, which may expose the mask material layer. As shown in FIG. 17 , the mask material layer and the insulating medium layer 32 farthest from the substrate 1 are etched in the developing area to form an opening 71 through which the sacrificial layer adjacent to the insulating medium layer 32 can be exposed. .

Step S240 , removing the sacrificial layer in the unit region and leaving the insulating dielectric layer.

After the lower electrode layer 33 is formed, the sacrificial layers in the unit region 11 can be removed, and the insulating dielectric layers 32 can be retained, which can not only increase the capacitance storage density, but also support the lower electrode layer 33 and prevent the lower electrode layer 33 from being deformed. , reduce the risk of short circuit.

In addition, as shown in FIG. 18 , the surface of the cover layer 7 can also be planarized to remove the cover layer 7 located at the top of the outer ring 41 , so that the surface of the cover layer 7 in the ring ring 41 is insulated from the second The surface of the dielectric layer 324 on the side facing away from the substrate 1 is flush to form the support structure 4 .

In step S250, a capacitor dielectric layer and an upper electrode layer are sequentially formed on the lower electrode layer of the non-peripheral columnar void structure in the unit region to form a capacitor array.

The capacitor dielectric layer 34 can be formed on the lower electrode layer 33 in the capacitor hole 37 of the unit region 11. For example, the capacitor dielectric layer 34 can be a thin film formed on the surface of the lower electrode layer 33, which can be formed by vacuum evaporation or magnetic The capacitive dielectric layer 34 may be formed by processes such as controlled sputtering. Of course, the capacitive dielectric layer 34 may also be formed by other processes, which will not be listed here. The capacitor dielectric layer 34 may be a single-layer film structure composed of the same material, or may be a mixed film layer structure composed of film layers of different materials. For example, it may include a material with a higher dielectric constant, for example, it may be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, or mixtures thereof, of course, It can also be other materials, which will not be listed one by one here.

In one embodiment, the forming method of the present disclosure may further include the steps: as shown in FIG. 9 , wherein:

Step S150, forming a semiconductor layer covering the surface of the capacitor array, the semiconductor layer filling the capacitor hole and the gap between two adjacent capacitors in the capacitor array.

The semiconductor layer 5 covering the capacitor array 3 can be formed on the surface of the upper electrode layer 35 by a vacuum evaporation process, so that the electric charges can be fully contacted with the second electrode, which helps to improve the charging efficiency of the capacitor. The semiconductor layer 5 can cover the surface of the capacitor array 3 and can fill the capacitor hole 37 and the gap between two adjacent capacitors in the capacitor array 3 , which can improve the electrical conductivity of the device and enhance the stability of each capacitor in the capacitor array 3 sex. The semiconductor layer 5 may be composed of silicon material, metal material or metal compound, for example, it may be silicon, silicon germanium, tungsten, titanium silicide, titanium oxide or tungsten oxide, etc., which is not limited herein.

In one embodiment, before etching the sacrificial layer and the insulating dielectric layer 32 of the cell region 11, the formation method of the present disclosure may further include:

Step S160, forming an interconnection structure in the peripheral region.

The interconnection structure can be formed in the insulating dielectric layer 32 corresponding to the peripheral region 12 , and can be in contact with the peripheral conductive contact plugs 23 , so as to electrically lead out the capacitor array 3 . The peripheral conductive contact plugs 23 can be made of the same material as the first conductive contact plugs 21 and the second conductive contact plugs 22 and have the same thickness, and the peripheral conductive contact plugs can be formed at the same time as the first conductive contact plugs 21 and the second conductive contact plugs 22 are formed twenty three.

In one embodiment, as shown in FIG. 19, forming the interconnect structure may include:

Step S1601, the conductive contact plugs are formed in the peripheral region while the conductive contact plugs are formed on the unit region of the substrate.

The first conductive contact plugs 21 , the second conductive contact plugs 22 and the peripheral conductive contact plugs 23 located in the peripheral area 12 of the cell region 11 may be simultaneously formed in one process. For example, the first conductive contact plugs 21 , the second conductive contact plugs 22 and the peripheral conductive contact plugs 23 can be formed simultaneously by a chemical vapor deposition process and a dry etching process. Of course, the first conductive contact plugs 21 can also be formed simultaneously by means of , the second conductive contact plug 22 and the peripheral conductive contact plug 23 , which will not be listed one by one here.

Step S1602, forming a first sacrificial layer in the peripheral region.

The first sacrificial layer 321 can be formed by vacuum evaporation, magnetron sputtering, atomic layer deposition, or the like.

Step S1603, using the conductive contact plug in the peripheral region as an etch stop layer, etching the first sacrificial layer to form a first via hole.

The first via hole 61 may be formed by a photolithography process, and the first via hole 61 may be formed in the first sacrificial layer 321 and may expose the peripheral conductive contact plugs 23 .

Step S1604, forming a first interconnect structure in the first via hole.

The first interconnect structure 6 can be formed in the first via hole 61 by a chemical vapor deposition process, and the first interconnect structure 6 can be communicated with the semiconductor layer 5 through the first via hole 61 so as to electrically lead out the capacitor array 3 .

As shown in FIG. 19, after forming the first interconnect structure 6, the forming method of the present disclosure may further include:

In step S1605, the insulating dielectric layer and the second sacrificial layer are sequentially formed on the first sacrificial layer in the peripheral region, and the first interconnection structure is used as an etch stop layer to etch the insulating dielectric layer and the second sacrificial layer. two sacrificial layers to form second vias.

The insulating dielectric layer 32 and the second sacrificial layer 323 can be sequentially formed on the first sacrificial layer 321 in the peripheral region 12 by vacuum evaporation, magnetron sputtering, atomic layer deposition, etc., and the second via hole can be formed by a photolithography process , the second via hole can be formed in the second sacrificial layer 323 and can be in contact with the first interconnect structure 6 .

Step S1606, forming a second interconnection structure in the second via hole.

The second interconnection structure can be formed in the second via hole by a chemical vapor deposition process, and the second interconnection structure can be communicated with the first interconnection structure 6 through the second via hole, so as to electrically lead out the capacitor array 3 .

The second interconnection structure may be the same in structure and material as the first interconnection structure 6 , the second interconnection structure may also include a connection layer and a lead-out layer, and the connection layer may be attached to the hole wall of the second via hole 91 according to the pattern and the bottom surface, and can communicate with the top of the first interconnection structure 6 , the lead-out layer can be located on the connection layer, and the second via hole 91 can be filled.

The semiconductor device of the present disclosure can be a memory chip, for example, it can be a DRAM (Dynamic Random Access Memory, dynamic random access memory), of course, can also be other semiconductor devices, which will not be listed one by one here.

Other embodiments of the present disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or techniques in the technical field not disclosed by the present disclosure . The specification and examples are to be regarded as exemplary only, with the true scope and spirit of the disclosure being indicated by the appended claims.

Claims

A semiconductor device, comprising:

a substrate, on which a plurality of conductive contact plugs arranged at intervals are formed;

A capacitor array, the capacitor array includes a plurality of column capacitors arranged at intervals, each of the column capacitors is formed on each of the conductive contact plugs, and the lower electrode layer of the column capacitor is in contact with the conductive contact plug ;

a support structure, the support structure is formed on the substrate at the edge of the capacitor array and surrounds the capacitor array, and the inner wall and the outer wall of the support structure are on any cross section parallel to the substrate The spacing is greater than the diameter of the capacitor hole on the cross section of any one of the column capacitors.
The semiconductor device of claim 1, wherein the conductive contact plug comprises a first conductive contact plug and a second conductive contact plug, the first conductive contact plug is in contact with a lower electrode layer of the column capacitor, the A second conductive contact plug is in contact with the bottom of the support structure.
The semiconductor device of claim 1, wherein at least an insulating dielectric layer is formed on the substrate, and the capacitor array and the support structure are formed in the insulating dielectric layer.
3. The semiconductor device of claim 2, wherein an orthographic projection of the support structure on the second conductive contact plug coincides with a boundary of the second conductive contact plug.
The semiconductor device of claim 3, wherein the substrate includes a cell region and a peripheral region, the capacitor array is formed in the cell region, the conductive contact plug further includes a peripheral conductive contact plug, the peripheral conductive Contact plugs are formed in the peripheral region, and the semiconductor device further includes an interconnect structure connected to the peripheral conductive contact plug, the interconnect structure formed in the insulating dielectric layer.
3. The semiconductor device of claim 3, wherein the insulating dielectric layer comprises a first insulating dielectric layer and a second insulating dielectric layer spaced along a direction perpendicular to the substrate, the capacitor array and the A support structure is formed in the first insulating dielectric layer and the second insulating dielectric layer.
A method of forming a semiconductor device, wherein the forming method comprises:

provide a substrate;

forming a plurality of spaced-apart conductive contact plugs on the substrate;

A capacitor array is formed, the capacitor array includes a plurality of column capacitors arranged at intervals, each of the column capacitors is formed on each of the conductive contact plugs, and the lower electrode layer of the column capacitor is in contact with the conductive contact plug connect;

A support structure is formed, the support structure is formed on the substrate at the edge of the capacitor array, and surrounds the capacitor array, and the inner wall and the outer wall of the support structure are in any cross-section parallel to the substrate The distance between the capacitor holes is larger than the diameter of the capacitor holes on the cross section of any one of the column capacitors.
The forming method according to claim 7, wherein the substrate has a unit area, a plurality of conductive contact plugs arranged at intervals are formed on the unit area, and the conductive contact plugs are located at the edge of the unit area The width of the conductive contact plug is greater than the width of the non-edge conductive contact plug in the unit area, and the forming the capacitor array and the supporting structure includes:

A sacrificial layer and an insulating dielectric layer are sequentially formed on the substrate, the conductive contact plug is used as an etch stop layer, the sacrificial layer and the insulating dielectric layer in the unit area are etched, and multiple layers are formed in the unit area. Columnar void structures are arranged at intervals, and the etching window is controlled so that the cross-sectional spacing of the columnar void structures located at the periphery of the cell region in the direction parallel to the substrate is greater than that of the non-periphery columnar void structures in the cell region the cross-sectional spacing;

depositing a lower electrode material to form a lower electrode layer on the sidewall of the columnar void structure;

depositing a dielectric material, the dielectric material filling the columnar void structures at the periphery of the cell region to form the support structure, and the non-peripheral columnar void structures in the cell region being unfilled;

removing the sacrificial layer in the unit region, leaving the insulating dielectric layer;

A capacitor dielectric layer and an upper electrode layer are sequentially formed on the lower electrode layer of the non-peripheral columnar void structure in the unit region to form a capacitor array.
The forming method according to claim 8, wherein the substrate further has a peripheral area, and before etching the sacrificial layer and the insulating dielectric layer of the unit area, the forming method further comprises:

An interconnect structure is formed in the peripheral region.
9. The forming method of claim 9, wherein forming the interconnect structure comprises:

forming the conductive contact plugs in the peripheral region while forming the conductive contact plugs on the cell region of the substrate;

forming a first sacrificial layer in the peripheral region;

Using the conductive contact plug in the peripheral region as an etch stop layer, etching the first sacrificial layer to form a first via hole;

A first interconnect structure is formed in the first via.
The forming method of claim 10, wherein after forming the first interconnect structure, the forming method further comprises:

The insulating dielectric layer and the second sacrificial layer are sequentially formed on the first sacrificial layer in the peripheral region, and the insulating dielectric layer and the second sacrificial layer are etched using the first interconnect structure as an etch stop layer. , to form a second via;

A second interconnect structure is formed in the second via.