WO2022037090A1

WO2022037090A1 - Interface, data processing method and apparatus, and network device

Info

Publication number: WO2022037090A1
Application number: PCT/CN2021/087110
Authority: WO
Inventors: 刘永志; 何向; 张琴
Original assignee: 华为技术有限公司
Priority date: 2020-08-17
Filing date: 2021-04-14
Publication date: 2022-02-24

Abstract

Disclosed are an interface, a data processing method and apparatus, and a network device. The interface can be shared by a plurality of PHY modules in a PHY chip and a plurality of MAC modules in a MAC chip. By using a relationship between a time slot and a PHY module and a relationship between a time slot and a MAC module, the transmission of data code streams at a plurality of different rates between the PHY chip and the MAC chip is realized by means of a physical channel corresponding to each direction, such that there is no need to occupy a large number of chip pins and the area of a circuit board, and the problems whereby an existing serialized MII cannot be compatible with a plurality of different rates and cannot be shared by a plurality of PHY modules and a plurality of MAC modules are solved, thereby achieving the effect of orderly transmitting data code streams at a plurality of different rates between a PHY chip and a MAC chip.

Description

An interface, data processing method, device and network equipment

This application claims the priority of the Chinese patent application with the application number 202010827823.7 and the application name "Interfaces, Computing Devices and Network Systems" filed with the State Intellectual Property Office of China on August 17, 2020, the entire contents of which are incorporated herein by reference In the application; and, this application also requires the priority of the Chinese patent application submitted to the State Intellectual Property Office of China on November 30, 2020, the application number is 202011375388.5, and the application name is "an interface, data processing method, device and network equipment". rights, the entire contents of which are incorporated herein by reference.

technical field

The present application relates to the field of communication technologies, and in particular, to an interface, a data processing method, an apparatus, and a network device.

Background technique

Since the media independent interface (English: media independent interface, referred to as: MII) is not affected by the signal transmission medium used by the PHY, in order to meet a media access control (English: Media Access Control, referred to as: MAC) chip adaptation To meet the needs of physical layer (English: physical layer, PHY) chips of different media types, MII is usually used to communicate between the MAC chip and the PHY chip, but the current MII implementation is not effective and cannot meet the actual needs.

SUMMARY OF THE INVENTION

Based on this, the embodiments of the present application provide an interface, a data processing method, an apparatus, and a network device to meet higher communication requirements between a MAC chip and a PHY chip.

The interface in this embodiment of the present application may be a pair of interface modules integrated in the transmitting-side device and the receiving-side device, or may also be an independent chip connected between the transmitting-side device and the receiving-side device.

In a first aspect, an embodiment of the present application provides an interface, where the interface may at least include: a coding unit, an allocation unit, and an overhead frame control unit. Wherein, the overhead frame control unit is configured to generate a first overhead frame based on the data streams received from the corresponding multiple MAC modules in the medium access control MAC chip; the encoding unit is configured to encode the data streams into corresponding a data code block; an allocation unit configured to allocate the data code block to a corresponding time slot according to the first overhead frame, and generate a first code block stream, where the first code block stream includes the first overhead frame and multiple blocks of data. In this way, when the first code block stream generated by the relationship between the time slot and the MAC module reaches the PHY chip through a physical channel corresponding to each direction, the interface corresponding to the PHY chip will follow the first code block stream in the first code block stream. The overhead frame determines the PHY module corresponding to the data code block in each time slot, so that each data code block in the code block stream is allocated to multiple PHY modules in the PHY chip, not only does it not need to occupy a lot of chip pins and circuit board area , and solves the problem that the existing serialized MII cannot be compatible with multiple different rates and cannot be shared by multiple PHY modules and multiple MAC modules, and realizes data streams of multiple different rates between the PHY chip and the MAC chip. The effect of orderly transmission.

In some implementation manners, the first overhead frame includes the rate of the MAC module and the identifier of the MAC module corresponding to each time slot in a time slot period. Then, the allocating unit is specifically configured to: according to the identifier of the MAC module corresponding to each time slot carried in the first overhead frame, fill the data code block corresponding to each MAC module to the time corresponding to the identifier of the MAC module and generating the first code block stream according to the multiple data code blocks that are filled and the first overhead frame. In this way, the code block stream to be sent is obtained by orderly filling according to the instructions in each time slot, which provides a data basis for orderly transmission of the code block stream and subsequent orderly reception and allocation.

In some implementations, when the first time slot corresponds to the first MAC module and the second MAC module, the first overhead frame further includes first indication information, where the first indication information is used to indicate that the first time slot is used by multiple MAC modules Module reuse.

As an example, the first overhead frame may further include an extended overhead block, where the extended overhead block includes the identifier of the first time slot, the rate of the first MAC module, the identifier of the first MAC module, the rate of the second MAC module, and the rate of the first MAC module. 2. Identification of the MAC module. In this way, it is ensured that time slots multiplexed by multiple MAC modules in different time slot periods can be inserted into corresponding data code blocks in an orderly and accurate manner, which provides a guarantee for the communication efficiency and communication quality of the interface.

As another example, the field corresponding to the first time slot in the first overhead frame carries the rate of the first MAC module and the identifier of the first MAC module in the first time slot period, and in the second time slot period Carry the rate of the second MAC module and the identifier of the second MAC module, carry the rate of the first MAC module and the identifier of the first MAC module in the third time slot period, and carry the data of the second MAC module in the fourth time slot period. The rate and the identification of the second MAC module, wherein the first time slot period is adjacent to the second time slot period, the second time slot period is adjacent to the third time slot period, and the third time slot period is adjacent to the fourth time slot period adjacent. In this way, by carrying different indication information in the overhead frames corresponding to multiple different timeslot periods, it is ensured that timeslots multiplexed by multiple MAC modules in different timeslot periods can be inserted into corresponding data code blocks in an orderly and accurate manner , which provides a guarantee for the communication efficiency and communication quality of the interface.

In a second aspect, an embodiment of the present application further provides an interface, where the interface may include an allocation unit, where the allocation unit is configured to, according to the first overhead frame in the first code block stream, allocate the first code block stream to the first code block stream. The data code block is allocated to the corresponding medium access control MAC module, and the first code block stream is received by the interface from the physical layer PHY chip. In this way, using the relationship between the time slot and the MAC module, the code block stream received from the PHY chip can be accurately allocated to the corresponding MAC module, and a variety of data code streams of different rates between the PHY chip and the MAC chip can be realized. The effect of orderly transmission.

Wherein, the filling frequency of the data code block corresponding to each MAC module in the first code block stream is determined according to the rate of the MAC module and the equivalent bandwidth corresponding to each time slot. For example, the rate of the data block filled in each time slot is 2.5 Gb/s, and the rate of the MAC module 1 is 1.25 Gb/s, then, the MAC module 1 is filled in one time slot of every two time slot periods.

In a third aspect, an embodiment of the present application further provides an interface, where the interface may include: an encoding unit, an allocation unit, and an overhead frame control unit. Wherein, the overhead frame control unit is used to generate a first overhead frame based on the data code streams received from the corresponding multiple PHY modules in the physical layer PHY chip; the encoding unit is used to encode the data code stream into corresponding data A code block; an allocation unit configured to allocate the data code block to a corresponding time slot according to the first overhead frame, and generate a first code block stream, where the first code block stream includes the first overhead frame and multiple data code blocks. In this way, when the first code block stream generated by using the relationship between the time slot and the PHY module reaches the MAC chip through a physical channel corresponding to each direction, the interface corresponding to the MAC chip will follow the first code block stream in the first code block stream. The overhead frame determines the MAC module corresponding to the data code block in each time slot, so that each data code block in the code block stream is allocated to multiple MAC modules in the MAC chip, not only does it not need to occupy a lot of chip pins and circuit board area , and solves the problem that the existing serialized MII cannot be compatible with multiple different rates and cannot be shared by multiple PHY modules and multiple MAC modules, and realizes data streams of multiple different rates between the PHY chip and the MAC chip. The effect of orderly transmission.

In some implementations, the first overhead frame may include the rate of the PHY module and the identifier of the PHY module corresponding to each time slot in one time slot period. Then, the allocation unit is specifically configured to: according to the identifier of the PHY module corresponding to each time slot carried in the first overhead frame, fill the data code block corresponding to each PHY module to the time slot corresponding to the identifier of the PHY module ; generating the first code block stream according to the filled-in multiple data code blocks and the first overhead frame. In this way, the code block stream to be sent is obtained by orderly filling according to the instructions in each time slot, which provides a data basis for orderly transmission of the code block stream and subsequent orderly reception and allocation.

The total bandwidth supported by the interface may be equal to the total bandwidth of the PHY chip.

In a fourth aspect, an embodiment of the present application further provides an interface, where the interface may include a distribution unit. The allocating unit is configured to allocate, according to the first overhead frame in the first code block stream, the data code blocks in the first code block stream to the PHY module corresponding to the first physical layer PHY chip, the first code block The block stream is received by the interface from the medium access control MAC chip. In this way, using the relationship between the time slot and the PHY module, the code block stream received from the MAC chip can be accurately allocated to the corresponding PHY module, and a variety of data code streams at different rates between the PHY chip and the MAC chip can be realized. The effect of orderly transmission.

In some implementations, if the first PHY chip further includes a first extended interface, the first extended interface is used to communicate with the second extended interface of the second PHY chip, and the second PHY chip includes a plurality of PHY modules . Then, the assigning unit is specifically configured to: according to the first overhead frame in the first code block stream, assign part of the data code blocks in the first code block stream to the PHY corresponding to the first PHY chip module; according to the first overhead frame in the first code block stream, allocate another part of the data code blocks in the first code block stream through the first extended interface and the second extended interface, and allocate to the PHY module corresponding to the second PHY chip. The total bandwidth supported by the interface may be equal to the sum of the total bandwidth of the first PHY chip and the total bandwidth of the second PHY chip.

For any implementation manner of the first aspect to the fourth aspect, the number of overhead blocks included in the first overhead frame may be determined according to the number of time slots included in one slot period of the first code block stream. The first overhead frame may further include any one or more of the following information: second indication information, where the second indication information is used to represent the first overhead frame; time slot status identifier Reset information, the Reset information The information is used to represent that the time slot state is the default state or the negotiation state; the link failure alarm RPF indication bit and LPF indication bit. The second indication information includes one or more of the following information: a synchronization header SH field, a 0x4B field, and a 0x5 field, where the value of the SH field is 10. In addition, the first overhead frame may further include one or more of the following information: CRC information, total bandwidth supported by the interface, and reserved fields.

In a fifth aspect, an embodiment of the present application further provides an interface, where the interface may include: an encoding unit, an allocation unit, and an overhead frame control unit. Wherein, an overhead frame control unit is used to generate a first overhead frame; an encoding unit is used to encode the data code stream into a corresponding data code block; an allocation unit is used to allocate the data code block according to the configuration information Go to the corresponding time slot, and generate a first code block stream, the configuration information is used to indicate the correspondence between the MAC module in the medium access control MAC chip and the time slot, and the first code block stream includes the first overhead frame. and a plurality of data code blocks, the first overhead frame is used to indicate the starting position of the first code block stream. In this way, the relationship between the time slot and the MAC module is stored in the interface in the form of configuration information. When reaching the PHY chip through a physical channel corresponding to each direction, the interface corresponding to the PHY chip will follow the first code block stream. The first overhead frame determines the starting position of the code block stream, and determines the PHY module corresponding to the data code block in each time slot based on the locally stored configuration information, so as to allocate each data code block in the code block stream to the transmitting side device. The multiple PHY modules in the PHY chip not only do not need to occupy a lot of chip pins and circuit board area, but also solve the problem that the existing serialized MII cannot be compatible with multiple different rates and cannot implement multiple PHY modules and multiple MACs. The problem of module sharing realizes the effect of orderly transmission of multiple data streams of different rates between the PHY chip and the MAC chip.

In a sixth aspect, an embodiment of the present application further provides an interface, characterized in that the interface includes an allocation unit, and the allocation unit is configured to determine, according to the first overhead frame, the size of the data code block in the first code block stream. location, and according to the configuration information, the data code blocks in the first code block stream are allocated to the MAC module corresponding to the medium access control MAC chip, where the configuration information is stored in the MAC chip, and the configuration information is used to indicate The correspondence between the MAC module in the MAC chip and the time slot, and the first code block stream is received by the interface from the physical layer PHY chip. In this way, the relationship between the time slot and the MAC module is stored in the interface in the form of configuration information. When reaching the MAC chip through a physical channel corresponding to each direction, the interface corresponding to the MAC chip will follow the first code block stream. The first overhead frame determines the starting position of the code block stream, and determines the MAC module corresponding to the data code block in each time slot based on the locally stored configuration information, so as to allocate each data code block in the code block stream to the transmitting side device. The multiple MAC modules in the PHY chip and the MAC chip realize the effect of orderly transmission of data streams of different rates between the PHY chip and the MAC chip.

In a seventh aspect, an embodiment of the present application further provides an interface, where the interface may include: an encoding unit, an allocation unit, and an overhead frame control unit. Wherein, an overhead frame control unit is used to generate a first overhead frame; an encoding unit is used to encode the data code stream into a corresponding data code block; an allocation unit is used to allocate the data code block according to the configuration information to the corresponding time slot, and generate a first code block stream, the configuration information is used to indicate the correspondence between the PHY module in the physical layer PHY chip and the time slot, and the first code block stream includes the first overhead frame and A plurality of data code blocks, the first overhead frame is used to indicate the starting position of the first code block stream. In this way, the relationship between the time slot and the PHY module is stored in the interface in the form of configuration information, and when reaching the MAC chip through a physical channel corresponding to each direction, the interface corresponding to the MAC chip is in accordance with the first code block stream. The first overhead frame determines the starting position of the code block stream, and determines the MAC module corresponding to the data code block in each time slot based on the locally stored configuration information, so as to allocate each data code block in the code block stream to the transmitting side device. The multiple MAC modules in the MAC chip not only need not occupy a lot of chip pins and circuit board area, but also solve the problem that the existing serialized MII cannot be compatible with multiple different rates and cannot implement multiple PHY modules and multiple MACs. The problem of module sharing realizes the effect of orderly transmission of multiple data streams of different rates between the PHY chip and the MAC chip.

In an eighth aspect, an embodiment of the present application further provides an interface, where the interface may include a distribution unit. The allocation unit is configured to determine the position of the data code block in the first code block stream according to the first overhead frame, and allocate the data code block in the first code block stream to the physical layer PHY chip according to the configuration information The corresponding PHY module, the configuration information is stored in the PHY chip, and the configuration information is used to indicate the corresponding relationship between the PHY module and the time slot in the PHY chip, and the first code block stream is the interface slave Media Access Control MAC chip received. In this way, the relationship between the time slot and the PHY module is stored in the interface in the form of configuration information. When reaching the PHY chip through a physical channel corresponding to each direction, the interface corresponding to the PHY chip will follow the first code block stream. The first overhead frame determines the starting position of the code block stream, and determines the PHY module corresponding to the data code block in each time slot based on the locally stored configuration information, so as to allocate each data code block in the code block stream to the transmitting side device. The multiple PHY modules in the PHY chip realize the effect of orderly transmission of data streams of various rates between the PHY chip and the MAC chip.

For any implementation manner of the fifth aspect to the eighth aspect, the MAC module in the MAC chip may correspond one-to-one with the PHY module in the PHY chip. The first overhead frame may include indication information for characterizing the frame as an overhead frame, and the indication information may be one or more of the following information: a synchronization header SH field, a 0x4B field, and a 0x5 field, where the value of the SH field is The value is 10.

For any implementation manner of the first aspect to the eighth aspect, the sum of the rates of all the MAC modules in the MAC chip is less than or equal to the total bandwidth supported by the interface. The number of MAC modules included in the MAC chip may be greater than or equal to the number of PHY modules included in the PHY chip, or may be smaller than the number of PHY modules included in the PHY chip.

For any implementation manner of the first aspect to the eighth aspect, the number of time slots included in one time slot cycle of the code block stream is a positive integer multiple of the number of PHY modules included in the physical layer PHY chip connected to the interface . The equivalent bandwidth corresponding to each time slot is the total bandwidth supported by the interface divided by the number of time slots included in one time slot cycle of the code block stream.

For any implementation manner of the above-mentioned first aspect to the eighth aspect, when the total bandwidth supported by the interface is less than 40 gigabits/second, the coding unit in the interface performs 64B according to the manner of Article 49 in IEEE 802.3 /66B encoding. When the total bandwidth supported by the interface is greater than or equal to 40 gigabits/second, the coding unit in the interface performs 64B/66B coding according to the manner of Clause 82 in IEEE802.3.

In a ninth aspect, an embodiment of the present application provides a data processing method, wherein an interface is connected to a medium access control MAC chip, where the MAC chip includes a first MAC module and a second MAC module, and the method may, for example, include: A first data stream from a MAC module and a second data stream from the second MAC module generate a first overhead frame, where the first overhead frame is used to indicate the first data stream and the second data stream. two time slots corresponding to the data code stream; encoding the first data code stream and the second data code stream respectively to obtain a first data code block and a second data code block; based on the first overhead frame, Inserting the first data code block into a first time slot, inserting the second data code block into a second time slot, and generating a first code block stream, the first code block stream includes a first overhead frame, the The first data code block inserted in the first time slot, and the second data code block inserted in the second time slot.

In some implementation manners, the method may further include: using a serializer SerDes to serialize the first code block stream to obtain a first processing result; sending the first processing result to a first Physical layer PHY chip.

As an example, the method may further include: receiving a second processing result from the first PHY chip; using the SerDes to deserialize the second processing result to obtain a second code block stream; The second overhead frame in the second code block stream is allocated, and the data code blocks in the second code block stream are allocated to a plurality of MAC modules corresponding to the MAC chip.

In other implementation manners, the method may further include: using a scrambling processing unit to scramble the first code block stream to obtain an updated first code block stream; using a serial deserializer SerDes to scramble the updated first code block stream The latter first code block stream is serialized to obtain a third processing result; and the third processing result is sent to the first physical layer PHY chip.

In some implementation manners, the MAC chip further includes a plurality of ports, and each port in the plurality of ports communicates with a corresponding MAC module through a corresponding adaptation sublayer RS. The method may further include: using the RS to connect the corresponding MAC The MAC frame stream sent by the module is processed into a data code stream; or, the RS is used to process the data code stream received by the interface into a MAC frame stream and sent to the corresponding MAC module.

It should be noted that the method provided by the ninth aspect corresponds to the interface provided by the first aspect, so the various possible implementation manners of the method provided by the ninth aspect and the technical effects achieved may refer to the interface provided by the aforementioned first aspect. 's introduction.

In a tenth aspect, the embodiments of the present application further provide another data processing method, which interfaces a first physical layer PHY module and a second PHY module, and the method may include: according to a first data code from the first PHY module stream and the second data stream from the second PHY module to generate a first overhead frame, where the first overhead frame is used to indicate time slots corresponding to the first data stream and the second data stream ; Encode the first data code stream and the second data code stream respectively to obtain a first data code block and a second data code block; Based on the first overhead frame, encode the first data code block inserting a first time slot, inserting the second data code block into a second time slot, and generating a first code block stream, the first code block stream including a first overhead frame, all the inserted data blocks in the first time slot the first data code block, and the second data code block inserted in the second time slot.

In some implementation manners, the method may further include: using a serializer SerDes to serialize the first code block stream to obtain a first processing result; sending the first processing result to a medium access Control the MAC chip.

As an example, the method further includes: receiving a second processing result from the MAC chip; using the SerDes to deserialize the second processing result to obtain a second code block stream, the second code block The stream includes a second overhead frame, a third data code block and a fourth data code block; according to the second overhead frame, the third data code block and the fourth data code block are respectively allocated to the first a PHY module and a second PHY module.

In some implementation manners, the method may further include: using a scrambling processing unit to scramble the first code block stream to obtain an updated first code block stream; using a serial deserializer SerDes to scramble the updated first code block stream The latter first code block stream is serialized to obtain a third processing result; and the third processing result is sent to the medium access control MAC chip.

In some implementations, the first PHY module and the second PHY module belong to a first PHY chip; or, the first PHY module belongs to a first PHY chip, the second PHY module belongs to a second PHY chip, and the first PHY module belongs to a second PHY chip. A PHY chip and the second PHY chip are connected through an extended interface.

It should be noted that the method provided by the tenth aspect corresponds to the interface provided by the third aspect. Therefore, various possible implementation manners of the method provided by the tenth aspect and the technical effects achieved may refer to the interface provided by the aforementioned third aspect. 's introduction.

In an eleventh aspect, an embodiment of the present application further provides a data processing method, wherein an interface is connected to a medium access control MAC chip, the MAC chip includes a first MAC module and a second MAC module, and the method includes: generating a first overhead frame , the first overhead frame is used to indicate the starting position of the code block stream; the first data code stream from the first MAC module and the second data code stream from the second MAC module are respectively encoded, obtaining a first data code block and a second data code block; based on the first overhead frame and configuration information, inserting the first data code block into the first time slot, and inserting the second data code block into the second time slot slot to generate a first code block stream, the first code block stream including a first overhead frame, the first data code block inserted in the first time slot, and the first data code block inserted in the second time slot In the second data code block, the configuration information is used to indicate the corresponding relationship between the MAC module and the time slot in the MAC chip.

It should be noted that the method provided in the eleventh aspect corresponds to the interface provided by the fifth aspect. Therefore, various possible implementations and technical effects of the method provided in the eleventh aspect can be provided with reference to the aforementioned fifth aspect. An introduction to the interface.

In a twelfth aspect, an embodiment of the present application provides a data processing method, wherein an interface is connected to a medium access control MAC chip, the MAC chip includes a first MAC module and a second MAC module, and the method includes: obtaining from a physical layer PHY chip a first code block stream, the first code block stream including a first overhead frame, a first data code block inserted in a first time slot, and a second data code block inserted in a second time slot; according to the first an overhead frame, determining the starting position of the data code block in the first code block stream; according to the configuration information, the first data code block and the second data code block in the first code block stream are The configuration information is respectively allocated to the first MAC module and the second MAC module, and the configuration information is used to indicate the corresponding relationship between the MAC module and the time slot in the MAC chip.

It should be noted that the method provided by the twelfth aspect corresponds to the interface provided by the sixth aspect. Therefore, various possible implementations and technical effects of the method provided by the twelfth aspect can be provided with reference to the aforementioned sixth aspect. An introduction to the interface.

In a thirteenth aspect, an embodiment of the present application further provides a data processing method, wherein an interface is connected to a physical layer PHY chip, the PHY chip includes a first PHY module and a second PHY module, and the method includes: generating a first overhead frame, The first overhead frame is used to indicate the starting position of the code block stream; the first data code stream from the first PHY module and the second data code stream from the second PHY module are respectively encoded to obtain a first data code block and a second data code block; based on the first overhead frame and configuration information, inserting the first data code block into a first time slot, and inserting the second data code block into a second time slot , generating a first code block stream, the first code block stream including a first overhead frame, the first data code block inserted in the first time slot, and the first data code block inserted in the second time slot Two data code blocks, the configuration information is used to indicate the corresponding relationship between the PHY module and the time slot in the PHY chip.

It should be noted that the method provided by the thirteenth aspect corresponds to the interface provided by the seventh aspect. Therefore, various possible implementations and technical effects of the method provided by the thirteenth aspect can be provided with reference to the aforementioned seventh aspect. An introduction to the interface.

In a fourteenth aspect, an embodiment of the present application further provides a data processing method, wherein an interface is connected to a physical layer PHY chip, the PHY chip includes a first PHY module and a second PHY module, and the method includes: accessing a control MAC from a medium The chip obtains a first code block stream, the first code block stream includes a first overhead frame, a first data code block inserted in the first time slot, and a second data code block inserted in the second time slot; according to the the first overhead frame, determining the starting position of the data code block in the first code block stream; according to the configuration information, combining the first data code block and the second data block in the first code block stream The code blocks are respectively allocated to the first PHY module and the second PHY module, and the configuration information is used to indicate the corresponding relationship between the PHY modules and the time slots in the PHY chip.

It should be noted that the method provided by the fourteenth aspect corresponds to the interface provided by the eighth aspect. Therefore, various possible implementations and technical effects of the method provided by the fourteenth aspect can be provided with reference to the aforementioned eighth aspect. An introduction to the interface.

For any one of the implementation manners of the eleventh aspect to the fourteenth aspect, in the MAC chip and the PHY chip connected through the interface, the MAC module and the PHY module may be in one-to-one correspondence. The first overhead frame includes indication information used to characterize the frame as an overhead frame, and the indication information may be one or more of the following information: a synchronization header SH field, a 0x4B field, and a 0x5 field, where the value of the SH field is is 10.

In a fifteenth aspect, an embodiment of the present application further provides a data processing device, the data processing device is located at an interface or communicates with a flexible interface, the interface is connected to a medium access control MAC chip, and the MAC chip includes a first MAC module and the second MAC module. The apparatus may include: a first generating unit, an encoding unit and a second generating unit. Wherein, a first generating unit is configured to generate a first overhead frame according to the first data code stream from the first MAC module and the second data code stream from the second MAC module, the first overhead frame It is used to indicate the time slot corresponding to the first data code stream and the second data code stream; the coding unit is used to encode the first data code stream and the second data code stream respectively to obtain the first data code stream. a data code block and a second data code block; a second generating unit, configured to insert the first data code block into the first time slot and insert the second data code block into the first time slot based on the first overhead frame Two time slots, generate a first code block stream, and the first code block stream includes a first overhead frame, the first data code block inserted in the first time slot, and the first data code block inserted in the second time slot. the second data code block.

In some implementations, the apparatus may further include a serializing unit and a transmitting unit. The serialization unit is used for serializing the first code block stream by using a serializer SerDes to obtain a first processing result; the sending unit is used for sending the first processing result to The first physical layer PHY chip.

As an example, the apparatus may further include: a receiving unit, a deserializing unit, and an allocating unit. The receiving unit is configured to receive the second processing result from the first PHY chip; the deserializing unit is configured to use the SerDes to deserialize the second processing result to obtain a second code block. a flow; an allocation unit configured to allocate data code blocks in the second code block flow to multiple MAC modules corresponding to the MAC chip according to the second overhead frame in the second code block flow.

In some implementations, the apparatus may further include a scrambling unit, a serializing unit, and a transmitting unit. Wherein, the scrambling unit is used for scrambling the first code block stream by using the scrambling code processing unit to obtain the updated first code block stream; the serialization unit is used for using the serializer SerDes to scramble the code block stream. The updated first code block stream is serialized to obtain a third processing result; the sending unit is configured to send the third processing result to the first physical layer PHY chip.

In some implementation manners, the MAC chip further includes a plurality of ports, and each port in the plurality of ports communicates with a corresponding MAC module through a corresponding adaptation sublayer RS, and the apparatus may further include a processing unit. The processing unit is configured to use the RS to process the MAC frame stream sent by the corresponding MAC module into a data stream; or, the processing unit is configured to use the RS to process the data stream received by the interface into a MAC frame stream and send it to Corresponding MAC module.

It should be noted that the device provided in the fifteenth aspect corresponds to the interface provided in the first aspect and the method provided in the ninth aspect, so the various possible implementations of the device provided in the fifteenth aspect and the technical effects achieved, Reference may be made to the relevant introductions of the foregoing first and ninth aspects.

In a sixteenth aspect, an embodiment of the present application further provides a data processing apparatus, the data processing apparatus is located at an interface or communicates with a flexible interface, the interface is connected to the first physical layer PHY module and the second PHY module, the apparatus It includes: a first generating unit, a coding unit and a second generating unit. Wherein, the first generating unit is configured to generate a first overhead frame according to the first data code stream from the first PHY module and the second data code stream from the second PHY module, the first overhead frame It is used to indicate the time slot corresponding to the first data code stream and the second data code stream; the coding unit is used to encode the first data code stream and the second data code stream respectively to obtain the first data code stream. a data code block and a second data code block; a second generating unit, configured to insert the first data code block into the first time slot and insert the second data code block into the first time slot based on the first overhead frame Two time slots, generate a first code block stream, and the first code block stream includes a first overhead frame, the first data code block inserted in the first time slot, and the first data code block inserted in the second time slot. the second data code block.

In some implementations, the apparatus may further include a serializing unit and a transmitting unit. The serialization unit is used for serializing the first code block stream by using a serializer SerDes to obtain a first processing result; the sending unit is used for sending the first processing result to Media Access Control MAC chip.

As an example, the apparatus may further include: a receiving unit, a deserializing unit, and an allocating unit. The receiving unit is configured to receive the second processing result from the MAC chip; the deserializing unit is configured to perform deserialization processing on the second processing result by using the SerDes, and the obtained second code block stream is The second code block stream includes a second overhead frame, a third data code block, and a fourth data code block; an allocation unit is configured to divide the third data code block and the first data code block according to the second overhead frame. Four data code blocks are allocated to the first PHY module and the second PHY module, respectively.

In some implementations, the apparatus may further include a scrambling unit, a serializing unit, and a transmitting unit. Wherein, the scrambling unit is used for scrambling the first code block stream by using the scrambling code processing unit to obtain the updated first code block stream; the serialization unit is used for using the serializer SerDes to scramble the code block stream. The updated first code block stream is serialized to obtain a third processing result; a sending unit is configured to send the third processing result to the medium access control MAC chip.

In some implementations, the first PHY module and the second PHY module may belong to the first PHY chip; or, the first PHY module belongs to the first PHY chip, the second PHY module belongs to the second PHY chip, and the first PHY chip and the first PHY chip belong to the first PHY chip. Two PHY chips are connected through an extended interface.

It should be noted that the device provided in the sixteenth aspect corresponds to the interface provided in the third aspect and the method provided in the tenth aspect, so the various possible implementations of the device provided in the sixteenth aspect and the technical effects achieved, Reference may be made to the above-mentioned related introductions of the third aspect and the tenth aspect.

In a seventeenth aspect, an embodiment of the present application further provides a data processing device, the data processing device is located at an interface or communicates with a flexible interface, the interface is connected to a medium access control MAC chip, and the MAC chip includes a first MAC module and a second MAC module, the apparatus includes: a first generating unit, an encoding unit and a second generating unit. The first generating unit is used to generate a first overhead frame, where the first overhead frame is used to indicate the starting position of the code block stream; the coding unit is used to encode the first data code from the first MAC module The stream and the second data code stream from the second MAC module are respectively encoded to obtain a first data code block and a second data code block; a second generating unit is configured to, based on the first overhead frame and the configuration information, Inserting the first data code block into a first time slot, inserting the second data code block into a second time slot, and generating a first code block stream, the first code block stream includes a first overhead frame, the the first data code block inserted in the first time slot and the second data code block inserted in the second time slot, the configuration information is used to indicate the MAC module and time slot in the MAC chip corresponding relationship.

It should be noted that the device provided in the seventeenth aspect corresponds to the interface provided in the fifth aspect and the method provided in the eleventh aspect, so various possible implementations of the device provided in the seventeenth aspect and the technical effects achieved , reference may be made to the above-mentioned related introductions of the fifth aspect and the eleventh aspect.

In an eighteenth aspect, an embodiment of the present application further provides a data processing apparatus, the data processing apparatus is located at an interface or communicates with a flexible interface, the interface is connected to a medium access control MAC chip, and the MAC chip includes a first MAC module and a second MAC module, the apparatus includes: an acquisition unit, a determination unit and an allocation unit. The obtaining unit is configured to obtain the first code block stream from the physical layer PHY chip, where the first code block stream includes the first overhead frame, the first data code block inserted in the first time slot, and the second time slot. the inserted second data code block; a determining unit, configured to determine the starting position of the data code block in the first code block stream according to the first overhead frame; an allocation unit, configured to assign the The first data code block and the second data code block in the first code block stream are respectively allocated to the first MAC module and the second MAC module, and the configuration information is used to indicate the MAC The correspondence between the MAC module in the chip and the time slot.

It should be noted that the device provided in the eighteenth aspect corresponds to the interface provided in the sixth aspect and the method provided in the twelfth aspect, so various possible implementations of the device provided in the eighteenth aspect and the technical effects achieved , you can refer to the related introductions of the sixth aspect and the twelfth aspect.

In a nineteenth aspect, an embodiment of the present application further provides a data processing device, the interface is connected to a physical layer PHY chip, the PHY chip includes a first PHY module and a second PHY module, and the device includes: a first generating unit, a coding unit and a second generating unit. Wherein, the first generating unit is used to generate a first overhead frame, the first overhead frame is used to indicate the starting position of the code block stream; the coding unit is used to generate the first data code from the first PHY module The stream and the second data code stream from the second PHY module are encoded respectively to obtain a first data code block and a second data code block; a second generating unit is configured to, based on the first overhead frame and the configuration information, Inserting the first data code block into a first time slot, inserting the second data code block into a second time slot, and generating a first code block stream, the first code block stream includes a first overhead frame, the The first data code block inserted in the first time slot and the second data code block inserted in the second time slot, the configuration information is used to indicate the PHY module and the time slot in the PHY chip corresponding relationship.

It should be noted that the device provided in the nineteenth aspect corresponds to the interface provided in the seventh aspect and the method provided in the thirteenth aspect, so various possible implementations of the device provided in the nineteenth aspect and the technical effects achieved , you can refer to the related introductions of the seventh aspect and the thirteenth aspect.

In a twentieth aspect, an embodiment of the present application further provides a data processing apparatus, the data processing apparatus is located at an interface or communicates with a flexible interface, the interface is connected to a physical layer PHY chip, and the PHY chip includes a first PHY module and a second PHY module, the apparatus includes: an acquisition unit, a determination unit and an allocation unit. Wherein, the obtaining unit is configured to obtain the first code block stream from the medium access control MAC chip, where the first code block stream includes the first overhead frame, the first data code block inserted in the first time slot, and the second time slot The second data code block inserted in the data code block; the determining unit is used to determine the starting position of the data code block in the first code block stream according to the first overhead frame; the allocation unit is used to determine the starting position of the data code block according to the configuration information The first data code block and the second data code block in the first code block stream are respectively allocated to the first PHY module and the second PHY module, and the configuration information is used to indicate the The correspondence between the PHY module and the time slot in the PHY chip.

It should be noted that the device provided in the twentieth aspect corresponds to the interface provided in the eighth aspect and the method provided in the fourteenth aspect, so various possible implementations of the device provided in the twentieth aspect and the technical effects achieved , reference may be made to the relevant introductions of the foregoing eighth aspect and fourteenth aspect.

For any implementation manner of the seventeenth aspect to the twentieth aspect, in the MAC chip and the PHY chip connected through the interface, the MAC module and the PHY module may be in one-to-one correspondence. The first overhead frame may include indication information for characterizing the frame as an overhead frame, and the indication information may be one or more of the following information: a synchronization header SH field, a 0x4B field, and a 0x5 field, where the value of the SH field is The value is 10.

In a twenty-first aspect, an embodiment of the present application further provides a network device, where the network device may include: a processor. Wherein, the processor communicates with a memory, and the memory includes computer-readable instructions, and the processor is configured to execute the computer-readable instructions, so that the network device performs any one of the ninth aspect to the twentieth aspect above A method provided by an aspect or any one possible implementation of any aspect.

In a twenty-second aspect, an embodiment of the present application further provides a computer-readable storage medium, including a program or an instruction, which, when executed by a processor, implements any one or any one of the above ninth to twentieth aspects A method provided by any one possible implementation of the aspect.

In a twenty-third aspect, an embodiment of the present application further provides a computer program product, characterized in that it includes a computer program, and when the computer program is executed by a processor, implements any one of the ninth aspect to the twentieth aspect above or the method provided by any possible implementation manner of any aspect.

Description of drawings

1 is a schematic structural diagram of an interface in an embodiment of the application;

FIG. 2a is a schematic diagram of the format of an overhead frame 1 in an embodiment of the present application;

FIG. 2b is a schematic diagram of the format of another overhead frame 1 in an embodiment of the present application;

3a is a schematic diagram of the format of a code block stream 1 in an embodiment of the present application;

FIG. 3b is a schematic diagram of the format of another code block stream 1 in an embodiment of the present application;

4 is a schematic diagram of a format of an overhead frame 2 in an embodiment of the present application;

FIG. 5 is a schematic diagram of the format of a code block stream 2 in an embodiment of the present application;

6a is a schematic diagram of a format of a code block stream in an embodiment of the present application;

FIG. 6b is a schematic diagram of the format of another code block stream in an embodiment of the present application;

FIG. 7 is a schematic flowchart of a data processing method 100 in an embodiment of the present application;

FIG. 8a is a schematic diagram of a format of a first overhead frame in an embodiment of the present application;

FIG. 8b is a schematic diagram of a format of another first overhead frame in an embodiment of the present application;

9 is a schematic diagram of a format of a first code block stream in an embodiment of the present application;

FIG. 10 is a schematic flowchart of a data processing method 200 in an embodiment of the present application;

FIG. 11 is a schematic flowchart of a data processing method 300 in an embodiment of the present application;

FIG. 12 is a schematic flowchart of a data processing method 400 in an embodiment of the present application;

13a is a schematic diagram of a format of a first overhead frame in an embodiment of the present application;

FIG. 13b is a schematic diagram of the format of another first overhead frame in an embodiment of the present application;

13c is a schematic diagram of a format of still another first overhead frame in an embodiment of the present application;

13d is a schematic diagram of a format of still another first overhead frame in an embodiment of the present application;

14a is a schematic diagram of a format of a first overhead frame in an embodiment of the present application;

14b is a schematic diagram of a format of still another first overhead frame in an embodiment of the present application;

FIG. 15 is a schematic structural diagram of a PHY chip cascade scenario in an embodiment of the present application;

FIG. 16 is a schematic structural diagram of a data processing apparatus 1600 in an embodiment of the present application;

FIG. 17 is a schematic structural diagram of a data processing apparatus 1700 according to an embodiment of the present application;

FIG. 18 is a schematic structural diagram of a data processing apparatus 1800 in an embodiment of the present application;

FIG. 19 is a schematic structural diagram of a data processing apparatus 1900 in an embodiment of the present application;

FIG. 20 is a schematic structural diagram of a data processing apparatus 2000 in an embodiment of the present application;

FIG. 21 is a schematic structural diagram of a data processing apparatus 2100 in an embodiment of the present application;

FIG. 22 is a schematic structural diagram of a network device 2200 in an embodiment of the present application;

FIG. 23 is a schematic structural diagram of a network device 2300 in an embodiment of the present application.

detailed description

The current medium independent interface MII is the interface between the medium access control MAC chip and the physical layer PHY chip defined by the Institute of Electrical and Electronic Engineers (English: Institute of Electrical and Electronic Engineers, referred to as: IEEE) 802.3 standard.

Generally, MII can parallelize the data transmitted between the MAC chip and the PHY chip to meet the communication requirements between the MAC chip and the PHY chip. Specifically, the parallelized processing can be realized by extending the signal transmission width between the two, for example: When the MII transmission rate is 100 Mbit/s (English: Mb/s), the data signal width of the MAC chip and the PHY chip needs to be 8 bits respectively; the MII transmission rate is 1 Gigabit/s (English: Gb/s) s), the data signal width of the MAC chip and PHY chip is 16 bits respectively; when the MII transmission rate is 10Gb/s, the data signal width of the MAC chip and PHY chip is 64 bits respectively. It can be seen that the method of increasing the communication rate through high parallelization will greatly increase the area of the circuit board occupied by the MII and occupy more pins of the MAC chip and more pins of the PHY chip as the demand for the communication rate continues to increase.

In addition, the high-speed communication between the MAC chip and the PHY chip is currently implemented through serialized MII, that is, the high-speed signal is transmitted through a physical channel corresponding to each direction, and there is no need to provide an associated clock, the MAC chip and The PHY chip can obtain the clock from the exchange of the data signal according to the clock and data recovery (English: clock and data recovery, CDR for short) technology, and transmit the data signal according to the 8B/10B format. Wherein, a physical channel can be realized by, for example, a pair of differential lines, or can be realized by a twin-axial cable (English: twin-axial cable). For example, the serialized MII may be a serial gigabit media independent interface (English: serial gigabit media independent interface, SGMII for short). In this way, the serialized MII solves the problem of occupying more pins of the MAC chip and the PHY chip in the parallel processing. No matter how high-speed communication is realized, only two pipes need to be provided for the MAC chip and the PHY chip respectively. feet. However, the current serialized MII only supports communication at one rate between one MAC module in the MAC chip and one PHY module in the PHY chip at a time, and cannot provide support for multiple MAC modules and multiple PHYs The modules communicate at different rates. Moreover, the total bandwidth that can be supported by the current serialized MII is limited, and the supported rates are all standard Ethernet interface rates, and cannot support communications at larger rates or non-standard Ethernet interface rates.

Based on this, the embodiments of the present application provide an interface (also referred to as a flexible interface (ie Flexible Interface) that can be shared by multiple PHY modules in a PHY chip and multiple MAC modules in a MAC chip, hereinafter referred to as the flexible interface description), using the relationship between the time slot and the PHY module and the relationship between the time slot and the MAC module, through a physical channel corresponding to each direction to achieve a variety of data streams between the PHY chip and the MAC chip at different rates Transmission, not only does not need to occupy a lot of chip pins and circuit board area, but also solves the problem that the existing serialized flexible interface cannot be compatible with multiple different rates and cannot be shared by multiple PHY modules and multiple MAC modules. The effect of orderly transmission of multiple data streams of different rates between the PHY chip and the MAC chip.

The flexible interface in this embodiment of the present application may be a pair of interface modules integrated in the transmitting-side device and the receiving-side device, or may be an independent chip connected between the transmitting-side device and the receiving-side device. For the convenience of description, the following description takes the flexible interface as a pair of interface modules integrated in the sending-side device and the receiving-side device as an example for description.

In the first implementation manner, on the sending side device, the first flexible interface in the MAC chip of the sending side device generates an overhead frame indicating the time slot occupied by the data code block corresponding to each MAC module, and according to the indication of the overhead frame, in the time slot Fill the code block stream corresponding to the time slot in the cycle with the corresponding data code block, and insert the overhead frame into the code block stream and send it to the PHY chip of the transmitting side device. In this way, the second flexible interface in the PHY chip of the transmitting side device That is, the PHY module corresponding to the data code block in each time slot can be determined according to the overhead frame in the code block stream, so that each data code block in the code block stream is allocated to multiple PHY modules in the PHY chip. On the receiving side device, the third flexible interface in the PHY chip of the receiving side device generates an overhead frame indicating the time slot occupied by the data code block corresponding to each PHY module, and the code corresponding to the time slot in the time slot cycle according to the indication of the overhead frame The block stream is filled with corresponding data code blocks, and the overhead frame is inserted into the code block stream and sent to the MAC chip of the receiving-side device. In this way, the fourth flexible interface in the MAC chip of the receiving-side device can follow the code block stream. The overhead frame determines the MAC module corresponding to the data code block in each time slot, so that each data code block in the code block stream is allocated to multiple MAC modules in the MAC chip. Wherein, the overhead frame in this implementation manner may also indicate the start position of the time slot period corresponding to the code block stream. For related concepts in this implementation manner, refer to the corresponding description in the following first example, and for the data processing method corresponding to this implementation manner, refer to the related descriptions of the following method 100 and method 200 .

In the second implementation manner, the configuration information may be pre-stored on the sending-side device or the receiving-side device, for example, the configuration information may be stored on the MAC chip and PHY chip of the sending-side device or the receiving-side device. In an embodiment, the sending-side device or the receiving-side device may also communicate with a device or module that has pre-stored configuration information, so as to acquire the pre-stored configuration information. The configuration information on the MAC chip is used to indicate the corresponding relationship between each MAC module and time slot in the MAC chip, and the configuration information on the PHY chip is used to indicate the corresponding relationship between each PHY module and time slot in the PHY chip. There is a one-to-one correspondence between modules and PHY modules. In this way, the first flexible interface in the MAC chip of the transmitting-side device can fill the corresponding data code block in the code block stream corresponding to the time slot in the time slot cycle according to the instruction of the configuration information, and use it to indicate the start of the code block stream. The overhead frame at the starting position is inserted into the code block stream and sent to the PHY chip of the sending side device. The second flexible interface in the PHY chip of the sending side device can determine the starting position of the code block stream according to the overhead frame in the code block stream. The PHY module corresponding to the data code block in each time slot is determined based on the locally stored configuration information, so that each data code block in the code block stream is allocated to multiple PHY modules in the PHY chip of the transmitting-side device. The third flexible interface in the PHY chip of the receiving-side device can fill the corresponding data code block in the code block stream corresponding to the time slot in the time slot cycle according to the instruction of the configuration information, and will be used to indicate the starting position of the code block stream The overhead frame is inserted into the code block stream and sent to the MAC chip of the receiving side device. The fourth flexible interface in the MAC chip of the receiving side device can determine the start position of the code block stream according to the overhead frame in the code block stream, and based on The locally stored configuration information determines the MAC module corresponding to the data code block in each time slot, so that each data code block in the code block stream is allocated to multiple MAC modules in the MAC chip of the receiving-side device. For related concepts in this implementation, refer to the description corresponding to the following second example, and for the data processing method corresponding to this implementation, refer to the related descriptions of the following methods 300 and 400 .

The total bandwidth that can be supported by the flexible interface provided by the embodiments of the present application may be equal to the total bandwidth of the PHY chip in one case, that is, equal to the sum of the bandwidths of all PHY modules in the PHY chip; in another case, it may also be equal to the total bandwidth of the PHY chip. The sum of the bandwidth of multiple PHY chips cascaded through an extended flexible interface. The embodiment of the present application is described by taking the first case as an example. For a scenario in which multiple PHY chips are cascaded, refer to the related description of the embodiment shown in FIG. 15 below.

It should be noted that, in the embodiment of the present application, the sum of the rates of all MAC modules in the MAC chip connected by the flexible interface is less than or equal to the total bandwidth supported by the flexible interface. For example, if the total bandwidth supported by the flexible interface is 10 Gb/s, then, The sum of the rates of all MAC modules in the MAC chip should be less than 10Gb/s.

FIG. 1 is a schematic structural diagram of a flexible interface provided by an embodiment of the present application. Referring to FIG. 1 , the MAC chip 10 includes a flexible interface 100 and a MAC module 1 to a MAC module N, and the PHY chip 20 includes a flexible interface 200 and a PHY module 1 to a PHY module M, where N and M are both positive integers, and N is equal to M Or N is greater than M or N is less than M, the number N of MAC modules may also be different or the same as the number L of RSs, for example, N is greater than or less than L. The following description takes M equals N and N equals L as an example. For the case where N is greater than M, it involves multiple MAC modules multiplexing a time slot. See Figures 13a to 13d and the corresponding descriptions of Figures 14a and 14b . The flexible interface 100 and the flexible interface 200 are connected through two physical channels 300 .

If the flexible interface 100 and the flexible interface 200 belong to network devices on the transmitting side, the flexible interface 100 includes an overhead frame control unit 110, an encoding unit 120 and an allocation unit 130, wherein the overhead frame control unit 120 is used to generate an overhead frame, and the encoding unit 120 is used to encode the data code stream to obtain the corresponding data code block, and the allocation unit 130 is used to allocate the data code block to the code block stream corresponding to the time slot in the time slot cycle according to the overhead frame or configuration information, and generate the code block stream . In addition, the flexible interface 100 may also include a serializer SerDes 140 for serializing the stream of code blocks. The flexible interface 100 may further include a SerDes 140 and a scrambling code processing unit 150. The scrambling code processing unit 150 is used to scramble the code block stream before serialization processing. The work of the scrambling code processing unit 150 can make the code block stream The data code blocks in the are more randomized, and the data balance is better. The flexible interface 100 can send the generated code block stream to the flexible interface 200. At this time, the allocation unit 230 in the flexible interface 200 can be used to determine the corresponding time slots according to the configuration information or according to the overhead frame in the received code block stream. The PHY module to which the data code block of 1 should be allocated, so that each data code block in the code block stream is allocated to the PHY module in the PHY chip 20 . The flexible interface 200 may also include an overhead frame control unit 210 and an encoding unit 220, and may also include a SerDes 240 and a scrambling code processing unit 250, wherein the SerDes 240 The code processing unit 250 may be used to descramble the received stream of code blocks.

If the flexible interface 100 and the flexible interface 200 belong to the network equipment on the receiving side, the flexible interface 200 includes an overhead frame control unit 210, an encoding unit 220 and an allocation unit 230, wherein the overhead frame control unit 220 is used to generate an overhead frame, and the encoding unit 220 is used to encode the data code stream to obtain the corresponding data code block, and the allocation unit 230 is used to allocate the data code block to the code block stream corresponding to the time slot in the time slot cycle according to the overhead frame or configuration information, and generate the code block stream . In addition, the flexible interface 200 may also include a serializer SerDes 240 for serializing the stream of code blocks. The flexible interface 200 may further include a SerDes 240 and a scrambling code processing unit 250. The scrambling code processing unit 250 is used to scramble the code block stream before the serialization process. The work of the scrambling code processing unit 250 can make the code block stream The data code blocks in the are more randomized, and the data balance is better. The flexible interface 200 can send the generated code block stream to the flexible interface 100. At this time, the allocation unit 130 in the flexible interface 100 can be used to determine the corresponding time slots according to the configuration information or according to the overhead frame in the received code block stream. The data code block should be allocated to the MAC module, so that each data code block in the code block stream is allocated to the MAC module in the MAC chip 10 . The flexible interface 100 may also include an overhead frame control unit 110 and an encoding unit 120, and may also include a SerDes 140 and a scrambling code processing unit 150, wherein the SerDes 140 may be used to deserialize the received processing result, and scramble the The code processing unit 150 may be configured to descramble the received stream of code blocks.

The code block stream transmitted between the MAC chip 10 and the PHY chip 20 may be divided according to the time slot period. The number of time slots included in a time slot cycle is equal to the positive integer multiple of the number of PHY modules included in the PHY chip; the rate of data code blocks that can be filled in each time slot (also called the equivalent bandwidth corresponding to a time slot) is a flexible interface The total supported bandwidth divided by the number of slots included in a slot cycle. For example, if the PHY chip 200 includes M=8 PHY modules, then, one time slot cycle may include 8i time slots (i=1, 2, . . . ), with i=1, the total bandwidth supported by the flexible interface is 20 Gb/s For example, the rate of data code blocks filled in each time slot is (20Gb/s÷8)=2.5Gb/s.

As a first example, the process of sending data from the MAC chip 10 to the PHY chip 20 is taken as an example to illustrate the working process of the flexible interface and related concepts involved in the first implementation provided by the embodiment of the present application:

First, MAC modules 1 to MAC modules N are respectively connected to adaptation sublayers (English: reconciliation sublayer, RS for short) 1 to N. When each MAC module receives the MAC frame stream, the RS corresponding to the MAC module reconciles the MAC frame stream. It is divided into data code streams, and the data code streams are sent to the flexible interface 100 through the corresponding ports. In some embodiments, the RS can process the MAC frame stream into a data stream based on the rate from the MAC module. For example, when the rate of the MAC module 1 is 10Gb/s, the RS 1 can process the MAC frame stream from the MAC module 1. 1 is processed as a 32-bit data stream; for another example, when the rate of the MAC module N is 1Gb/s, the RS N can process the MAC frame stream N from the MAC module N into an 8-bit data stream.

After the flexible interface 100 receives the data code stream, on the one hand, the encoding unit 120 is configured to encode each data code stream to obtain a corresponding data code block. If the total bandwidth supported by the flexible interface 100 is less than 40 Gb/s, the encoding unit 120 performs 66B/68B encoding according to the method in Clause 49 of IEEE 802.3; if the total bandwidth supported by the flexible interface 100 is greater than or equal to 40 Gb/s, the encoding unit 120 performs 66B/68B encoding is performed in the manner of Clause 82 in IEEE 802.3. On the other hand, the overhead frame control unit 110 generates the overhead frame 1 based on the data streams received from the plurality of MAC modules. The overhead frame 1 is used to indicate the data code blocks generated by the MAC module that should be filled in each time slot. The overhead frame 1 may include at least one overhead block, and the size of one overhead block is 68 bits. The number of overhead blocks included in the overhead frame 1 is related to the time slots included in a time slot cycle. Assuming that a time slot cycle includes 2 time slots, the overhead frame 1 may include only one overhead block 1 as shown in Figure 2a; Assuming that one time slot period includes 8 time slots, the overhead frame 1 may include an overhead block 1 and an overhead block 2 as shown in FIG. 2 b .

In FIG. 2a, overhead frame 1 (ie, overhead block 1) may include: an indication information field for characterizing the frame as an overhead frame, a time slot 1 field, and a time slot 2 field. The indication information field may include at least one of a synchronization header (English: synchronization header, SH for short) field, a 0x4B field and a 0x5 field, where the value of the SH field is 10, indicating that the overhead block 1 is the control of the overhead frame 1 Block; the position and value of the 0x4B field and the 0x5 field are used to identify the frame as an overhead frame that is different from the data frame. The value of the 0x4B field can be 0x4B, the value of the 0x5 field can be 0x5, and the value of the 0x4B field and the 0x5 field can also be Define the data frame as an overhead frame by other values. For example, the indication information fields in FIG. 2a include the SH field, the 0x4B field and the 0x5 field. The time slot 1 field includes the rate 1 (English: Client Rate 1) of the MAC module 1 (English: Client Rate 1) and the identification 1 (English: Client ID 1) of the MAC module 1 that need to be filled into the time slot 1. Similarly, the time slot 2 field includes the required The rate 2 (English: Client Rate 2) of the MAC module 2 and the identification 2 (English: Client ID 2) of the MAC module 2 are filled into the time slot 2. In addition, the overhead frame 1 may also include a time slot status identification bit Reset, a remote PHY fault (English: Remote PHY Fault, abbreviated: RPF) indication bit, a local PHY fault (English: Local PHY Fault, abbreviated: LPF) indication Bit, PHY chip rate indication field (English: PHY Rate) and cyclic redundancy check (English: cyclic redundancy check, abbreviated: CRC) field, where Reset is used to characterize the time slot state as the default state or negotiation state; RPF and LPF are used to indicate whether the PHY chip is faulty, PHY Rate is used to indicate the maximum rate supported by the PHY chip (that is, the total bandwidth supported by the flexible interface), and CRC is used to check the overhead frame 1. In addition, if the content included in the overhead frame 1 is less than the size requirement of one overhead block 1, the overhead frame 1 may further include a reserved (English: Reserved) field of several bits.

In Fig. 2b, since one slot field occupies 8 bits, for the case where one slot cycle includes 8 slots, one overhead block cannot carry all slot fields, so overhead frame 1 includes overhead block 1 and overhead block 2. Wherein, overhead block 1 may include: indication information field 1, timeslot 1 field, timeslot 2 field, and timeslot 3 field, and overhead block 2 may include indication information field 2, timeslot 4 field, timeslot 5 field, timeslot 6 field, slot 7 field and slot 8 field. The indication information field 1 may include the SH field=10, the 0x4B field, and the 0x5 field, and the overhead block 1 may also include fields such as R, RPF, LPF, PHY Rate, and Reserved. The indication information field 2 may include the SH field=01, which is used to represent that the overhead block 2 is the data block of the overhead frame 1, and the overhead block 2 may also include fields such as Reserved and CRC, and the value of the CRC may be, for example, an 8-bit CRC (abbreviation: CRC-8).

It should be noted that PHY Rate can indicate different bandwidths through different values. For example, if the length of the PHY Rate is 3 bits, then the corresponding relationship between the preset PHY Rate value and the bandwidth can be seen in Table 1 below:

Table 1 Correspondence between the value of PHY Rate and the bandwidth

PHY Rate的取值The value of PHY Rate	PHY芯片支持的总带宽Total bandwidth supported by the PHY chip
000000	ReservedReserved
001001	2.5Gb/s2.5Gb/s
010010	5Gb/s5Gb/s
011011	10Gb/s10Gb/s
100100	20Gb/s20Gb/s
101-111101-111	ReservedReserved

Wherein, assuming that the total bandwidth of the PHY chip 20 is 20 Gb/s, the value of the PHY Rate in the overhead frame 1 generated by the overhead frame control unit 110 may be 100. It should be noted that the total bandwidth supported by the flexible interface is no longer limited to the standard Ethernet interface rate. The flexible interface can support any bandwidth by defining the value of the reserved PHY Rate or expanding the bit length occupied by the PHY Rate. .

Client Rate can also indicate the rate of the MAC module through different values. For example, if the length of the Client Rate is 4 bits, then the corresponding relationship between the value of the preset Client Rate and the rate of the corresponding MAC module can be seen in Table 2 below.

Among them, assuming that the rate of the MAC module 1 is 1.25Gb/s, the time slot 1 in the overhead frame 1 generated by the overhead frame control unit 110 corresponds to the MAC module 1, then the Client Rate 1 included in the time slot 1 field = 0x4 . It should be noted that each time slot field in the overhead frame indicates the rate of the MAC module corresponding to the time slot, so that the flexible interface supports communication between multiple MAC modules and multiple PHY modules in the PHY chip at different rates.

Next, the allocating unit 130 can allocate the data code blocks to the code block stream corresponding to the time slot in the time slot cycle according to the overhead frame 1, and generate the code block stream 1, if the code block stream 1 is between the MAC chip 10 and the PHY chip 20 For the first data communication between, the code block stream 1 carries the overhead frame 1 and several timeslot periods filled with data code blocks. Wherein, the filling frequency of the data code block corresponding to each MAC module in the code block stream is determined according to the rate of the MAC module and the equivalent bandwidth corresponding to each time slot. For example, the rate of the data block filled in each time slot is 2.5 Gb/s, and the rate of the MAC module 1 is 1.25 Gb/s, then, the MAC module 1 is filled in one time slot of every two time slot periods. The specific time slot field in a time slot cycle that the data code block in the MAC module is filled into can be flexibly designed according to needs, which is not specifically limited in this embodiment of the present application. For example, in order to save resources, the overhead frame control unit 120 may determine the MAC module corresponding to each time slot according to the sequence of the data stream generated in the RS corresponding to the MAC module.

Table 2 The corresponding relationship between the value of Client Rate and the rate of the MAC module

Client Rate的取值The value of Client Rate	MAC模块的速率The rate of the MAC module
0x00x0	ReservedReserved
0x10x1	10Mb/s10Mb/s
0x20x2	100Mb/s100Mb/s
0x30x3	1Gb/s1Gb/s
0x40x4	1.25Gb/s1.25Gb/s
0x50x5	2.5Gb/s2.5Gb/s
0x60x6	5Gb/s5Gb/s
0x70x7	10Gb/s10Gb/s
0x80x8	20Gb/s20Gb/s
0x9～0xF0x9～0xF	ReservedReserved

For example, the bandwidth supported by the flexible interface is 20Gb/s, the PHY chip 20 includes 8 PHY modules, the MAC chip 10 includes MAC module 1 to MAC module 4, and the rates are 1.25Gb/s, 1Gb/s, and 2.5Gb/s respectively. and 5Gb/s. Referring to Fig. 3a, it is a schematic diagram of the format of a code block stream 1. One time slot cycle includes 8 time slots, and the equivalent bandwidth of each time slot is 2.5Gb/s. The MAC module is determined according to the sequence in which the RS generates data code blocks. 1 corresponds to time slot 7, MAC module 2 corresponds to time slot 2, MAC module 3 corresponds to time slot 5, and MAC module 4 corresponds to time slot 1 and time slot 3. Since the rate of the MAC module 1 is 1.25Gb/s, the data code block corresponding to the MAC module 1 is filled in one slot 7 in every two slot cycles, that is, every (2*8-1=15 ) timeslots fill the data code block corresponding to MAC module 1 once. Similarly, since the rate of the MAC module 2 is 1 Gb/s, the data code blocks corresponding to the MAC module 2 are filled in the timeslot 2 of two timeslot periods every five timeslot periods. Since the rate of the MAC module 3 is 2.5 Gb/s, the data code blocks corresponding to the MAC module 3 are filled in the time slot 5 of each time slot cycle. Since the rate of the MAC module 4 is 5Gb/s, the data code blocks corresponding to the MAC module 4 are filled in the time slot 1 and the time slot 3 of each time slot cycle. It should be noted that the correspondence between each time slot in a time slot cycle and the MAC module is fixed. Taking the above MAC module 1 as an example, in the time slot cycle in which the data code block does not need to be filled in time slot 7 , the time slot 7 can be filled with a special code block (for example: an idle control code block (English: idle control block) or an error control code block (English: error control block), represented by X in the figure). Referring to Fig. 3b, it is a schematic diagram of the format of another code block stream 1. One time slot cycle includes 16 time slots, and the equivalent bandwidth of each time slot is 1.25 Gb/s. The MAC is determined according to the sequence in which the RS generates data code blocks. Module 1 corresponds to slot 14, MAC module 2 corresponds to slot 5, MAC module 3 corresponds to slot 9 and slot 10, and MAC module 4 corresponds to slot 1, slot 2, slot 3, slot 7 and slot 8 . Since the rate of the MAC module 1 is 1.25 Gb/s, the data code block corresponding to the MAC module 1 is filled once in one time slot 14 in each time slot cycle. Similarly, since the rate of the MAC module 2 is 1 Gb/s, the data code blocks corresponding to the MAC module 2 are filled in the timeslot 5 of the four timeslot periods every five timeslot periods. Since the rate of the MAC module 3 is 2.5 Gb/s, the data code blocks corresponding to the MAC module 3 are filled in the time slot 9 and the time slot 10 of each time slot cycle. Since the rate of the MAC module 4 is 5Gb/s, the data code blocks corresponding to the MAC module 4 are filled in time slot 1, time slot 2, time slot 3, time slot 7 and time slot 8 of each time slot cycle. In the figure, the number filled in the time slot can be regarded as the identification of the MAC module. For example, the number 4 in the time slot 1 represents the identification of the MAC module 4, which is used to indicate that the data code corresponding to the MAC module 4 is filled in the time slot. Piece.

Optionally, the flexible interface 100 can also use the SerDes 140 to serialize the code block stream 1 to obtain the processing result 1, and send the processing result 1 to the PHY chip 20 through a physical channel in the corresponding direction in the physical channel 300. , and is specifically sent to the flexible interface 200 in the PHY chip 20 .

Optionally, in order to make the data sent to the PHY chip 20 more balanced, the flexible interface 100 can also use the scrambling processing unit 150 to perform scramble processing on the code block stream 1 before the serialization processing, so as to obtain the code block stream 1'. , and then use the SerDes 140 to serialize the code block stream 1' to obtain a processing result 1', and send the processing result 1' to the PHY chip 20 through a physical channel in the corresponding direction in the physical channel 300. For example, the scrambling processing unit 150 may be implemented using a scrambler defined by IEEE 802.3 Clause 49.2.6.

Optionally, the flexible interface 100 may further include a forward error correction FEC sublayer, where the FEC sublayer is used to perform FEC encoding on the code block stream. For example, in the flexible interface 100, the scrambling processing unit 150 scrambles the code block stream 1 to obtain the code block stream 1'; then, the FEC sublayer is used to perform FEC encoding on the code block stream 1' to obtain the code block stream 1 ”; then, the SerDes 140 serializes the code block stream 1” to obtain the processing result 1”, and sends the processing result 1” to the PHY chip 20 through a physical channel in the corresponding direction in the physical communication 300.

Finally, on the side of the PHY chip 20, when the flexible interface 200 receives data transmitted through a physical channel in the corresponding direction in the physical channel 300, the allocation unit 230 can allocate each data code block to the corresponding PHY module based on the overhead frame 1 superior. Optionally, if the data is the processing result 1 obtained by serializing the code block stream 1 by the SerDes 140, then, in the flexible interface 200, the SerDes 240 may firstly perform the deserializing processing on the processing result 1, The code block stream 1 is obtained, and then the allocation unit 230 allocates each data code block to the corresponding PHY module based on the overhead frame 1 in the code block stream 1. Optionally, if the data is the processing result 1' obtained by processing by the scrambling processing unit 150 and the SerDes 140, then, in the flexible interface 200, the SerDes 240 can also perform deserialization processing on the processing result 1' to obtain the code. Block stream 1', the code block stream 1' is descrambled by the scrambling processing unit 250 to obtain code block stream 1, and then the allocation unit 230 allocates each data code block to the block stream 1 based on the overhead frame 1 in the code block stream 1. on the corresponding PHY module. It should be noted that the execution sequence of the operations of deserializing and descrambling the received data in the flexible interface 200 is merely exemplary, and is not specifically limited in the embodiments of the present application. For example, the scrambling processing unit 250 may be implemented using a scrambler defined by IEEE 802.3 Clause 49.2.6.

In specific implementation, in one case, the flexible interface 200 may include the mapping relationship 1 between the MAC module and the PHY module, then the allocation unit 230 may determine which MAC module the data code blocks in each time slot come from based on the overhead frame 1, and then Considering the mapping relationship 1 and the indication of the overhead frame 1 comprehensively, the data code blocks in each time slot are accurately allocated to the corresponding PHY modules. In another case, the flexible interface 200 may also include the mapping relationship 2 between each time slot and the PHY module. Then, the allocation unit 230 can accurately assign the data code blocks in each time slot to the data code block based on the indication of the mapping relationship 2. assigned to the corresponding PHY module.

It can be seen that through the flexible interface provided by this example, the effect of data interaction between multiple MAC modules in the MAC chip 10 and multiple PHY modules in the PHY chip 20 at different rates can be realized, so that the multiple PHY modules and the multiple PHY modules can interact with each other at different rates. It is possible for MAC modules to share flexible interfaces.

As a second example, taking the process of sending data from the PHY chip 20 to the MAC chip 10 as an example, the working process of the flexible interface and related concepts involved in the second implementation manner provided by the embodiment of the present application are described:

In this example, there may be a one-to-one correspondence between the PHY modules and the MAC modules, each MAC module supports the same rate, each PHY module supports the same rate, and the MAC module and the PHY module have the same rate. Configuration information is pre-stored on the PHY chip 20 and the MAC chip 10, wherein the configuration information 1 on the PHY chip 20 is used to indicate the corresponding relationship between the PHY module and the time slot, and the configuration information 2 on the MAC chip 10 is used to indicate the MAC module and the time slot. gap correspondence. The number of times each PHY module or MAC module appears in the configuration information can be determined according to the rate supported by the PHY module or MAC module and the equivalent bandwidth corresponding to each time slot. For example, the equivalent bandwidth of each time slot is 2.5 Gb/s, the rate supported by each MAC module is also 2.5Gb/s, then in the configuration information 2, each MAC module corresponds to a time slot in a time slot period; for another example, the equivalent bandwidth of each time slot is 2.5 Gb/s, the rate supported by each MAC module is also 5Gb/s, then in the configuration information 2, each MAC module corresponds to two time slots in a time slot cycle, and the two time slots corresponding to the same MAC module can be time slots. The adjacent time slots in the slot period may also be non-adjacent time slots in the time slot period.

For example, if the PHY chip 20 includes 8 PHY modules, and one time slot cycle includes 8 time slots, the configuration information 1 on the PHY chip 20 may be as shown in Table 3 below:

Table 3 Configuration Information 1

For another example, if the PHY chip 20 includes 4 PHY modules, and one time slot cycle includes 8 time slots, the configuration information 1 on the PHY chip 20 may be as shown in Table 4 below:

Table 4 Configuration Information 1

For example, if the MAC chip 10 includes 8 MAC modules, and one time slot cycle includes 8 time slots, the configuration information 2 on the MAC chip 10 may be as shown in Table 5 below:

Table 5 Configuration Information 2

For another example, if the MAC chip 10 includes 2 MAC modules, and one time slot cycle includes 8 time slots, the configuration information 2 on the MAC chip 10 may be as shown in Table 6 below:

Table 6 Configuration Information 2

First, the PHY module 1 to the PHY module N send the data stream to the flexible interface 200 through the corresponding port.

Then, after the flexible interface 200 receives the data code stream, on the one hand, the encoding unit 220 is configured to encode each data code stream to obtain a corresponding data code block. The encoding mode of the encoding unit 220 is not specifically limited in the embodiment of the present application. For example, if the total bandwidth supported by the flexible interface 200 is less than 40Gb/s, the encoding unit 220 performs 66B/68B encoding according to the method of Article 49 in IEEE 802.3. The total bandwidth supported by the interface 200 is greater than or equal to 40 Gb/s, and the encoding unit 220 performs 66B/68B encoding according to the IEEE 802.3 clause 82; for another example, the encoding method is not distinguished by the total bandwidth supported by the flexible interface 200, the encoding unit 220 66B/68B encoding is performed according to Clause 49 in IEEE 802.3. On the other hand, the overhead frame control unit 110 generates the overhead frame 2 . The overhead frame 2 is used to indicate the starting position of the code block stream transmitted by the flexible interface 200. The overhead frame 2 may include at least one 68-bit overhead block, and the overhead frame 2 may include an indication information field for characterizing the frame as an overhead frame. The indication information field may include at least one of the SH field, the 0x4B field, and the 0x5 field, where the value of the SH field is 10, indicating that the overhead block is the control block of the overhead frame 2 . For example, the indication information field in FIG. 4 includes the SH field, the 0x4B field, and the 0x5 field. In addition, the overhead frame 2 may also include fields such as R, RPF, LPF, PHY Rate, and CRC. In addition, if the content included in the overhead frame 2 is less than 68 bits, the overhead frame 2 may further include a Reserved field of several bits.

Next, the allocation unit 230 can allocate the data code blocks to the corresponding time slots according to the configuration information 1, and generate a code block stream 2. If the code block stream 2 is the first data communication between the MAC chip 10 and the PHY chip 20, then, The start position in the code block stream 2 fills the overhead frame 2 to indicate the start position of the data code block in the code block stream 2 .

For example, if the PHY chip 20 includes 4 PHY modules, the rate supported by each PHY module is 2.5 Gb/s, and one time slot cycle includes 8 time slots, the configuration information 1 on the PHY chip 20 is shown in Table 4 above, Then, the generated code block stream 2 can be referred to as shown in FIG. 5 . Referring to FIG. 5 , the code block stream 2 may include overhead frame 2, time slot 1 corresponding to PHY module 1, time slot 2 corresponding to PHY module 2, time slot 3 corresponding to PHY module 3, and time slot 4 corresponding to PHY module 4 , Time slot 5 corresponding to PHY module 1, time slot 6 corresponding to PHY module 2, time slot 7 corresponding to PHY module 3, time slot 8 corresponding to PHY module 4, time slot 1 corresponding to PHY module 1, corresponding to PHY module 2 time slot 2, . . . In the figure, the number filled in the time slot can be regarded as the identity of the PHY module. For example, the number 1 in the time slot 1 represents the identity of the PHY module 1, which is used to indicate that the data code corresponding to the PHY module 1 is filled in the time slot. Piece.

Optionally, the flexible interface 200 can also use the SerDes 240 to serialize the code block stream 2 to obtain a processing result 2, and send the processing result 2 to the MAC chip 10 through a physical channel in the corresponding direction in the physical channel 300. , which is specifically sent to the flexible interface 100 in the MAC chip 10 .

Optionally, in order to make the data sent to the MAC chip 10 more balanced, the flexible interface 200 can also use the scrambling processing unit 250 to scramble the code block stream 2 before the serialization process to obtain the code block stream 2', wherein , the lengths of the code block stream 2 and the code block stream 2' are the same, and then use the SerDes 240 to serialize the code block stream 2' to obtain the processing result 2', and pass the processing result 2' through the corresponding direction in the physical channel 300. is sent to the MAC chip 10 on a physical channel.

Finally, on the side of the MAC chip 10, when the flexible interface 100 receives the data transmitted through a physical channel in the corresponding direction in the physical channel 300, the allocation unit 130 can determine the starting position of the code block stream 2 based on the overhead frame 2, so as to be based on Configuration information 2 allocates each data code block to the corresponding PHY module. For example, if the configuration information 1 on the PHY chip 20 is shown in Table 4, the configuration information 2 on the MAC chip 10 can be shown in Table 7 below:

Table 7 Configuration Information 2

时隙1 slot 1	时隙2 slot 2	时隙3 slot 3	时隙4 slot 4	时隙5slot 5	时隙6 slot 6	时隙7 slot 7	时隙8slot 8
MAC模MAC mode	MAC模MAC mode	MAC模MAC mode	MAC模MAC mode	MAC模MAC mode	MAC模MAC mode	MAC模MAC mode	MAC模MAC mode

block 1

block 2

block 3

block 4

block 1

block 2

block 3

block 4

Optionally, if the data is the processing result 2 obtained by serializing the code block stream 2 through the SerDes 240, then, in the flexible interface 100, the SerDes 140 may first perform deserialization processing on the processing result 2, The code block stream 2 is obtained, and then the allocation unit 130 allocates each data code block to the corresponding MAC module based on the configuration information 2 .

Optionally, if the data is the processing result 2' obtained through processing by the scrambling code processing unit 250 and the SerDes 240, then, in the flexible interface 100, the SerDes 140 can also perform deserialization processing on the processing result 2' to obtain the code. For block stream 2', the scrambling processing unit 150 descrambles the code block stream 2' to obtain code block stream 2, and then the allocation unit 130 allocates each data code block to the corresponding MAC module based on the configuration information 2. It should be noted that, the execution sequence of the operations of deserializing and descrambling the received data in the flexible interface 100 is only exemplary, and is not specifically limited in this embodiment of the present application.

It can be seen that, through the flexible interface provided by this example, the effect of data interaction between multiple MAC modules in the MAC chip 10 and multiple PHY modules in the PHY chip 20 can be achieved, so that multiple PHY modules and multiple MAC modules share Flexible interfaces are possible.

For the two possible implementation manners provided by the embodiments of the present application, the frequency of inserting overhead frames into the code block stream and the insertion timing can be flexibly set according to timing requirements. For example, overhead frames can be periodically inserted into the code block stream, and the period for inserting overhead frames can be a preset number (eg, 20,000) timeslot periods. Errors occur in the process of allocating code blocks to various modules, which ensures the orderly and accurate allocation to a certain extent. For another example, an overhead frame may also be inserted into the code block stream based on a trigger event, where the trigger event may be an event such as a time slot allocation modification or a link failure. In this case, the inserted overhead frame is generated based on the trigger event. A new overhead frame, in this way, ensures that after a trigger event occurs, the allocation can still be guaranteed to be accurate.

In some embodiments, if the overhead frame includes at least two overhead blocks, in one case, the at least two overhead blocks can be inserted into the code block stream at the same time, so that the flexible interface in the code block stream can be received. The overhead frame is quickly acquired from the code block stream, so that the data code blocks in each time slot can be directly allocated based on the overhead frame, which improves the processing efficiency of the flexible interface. In another case, in order to avoid more serious jitter caused by inserting more overhead blocks at a time, thus affecting data transmission, at least two overhead frames can also be inserted into the code block stream at different positions. However, the code block The position in the stream where the overhead block is inserted is usually the position between two slot periods, instead of choosing to insert the overhead block inside a slot period. For inserting at least two overhead blocks into different positions of the code block stream, the flexible interface that receives the code block stream needs to obtain all the overhead blocks of the overhead frame from different positions of the code block stream first, before obtaining the last overhead block. All the data code blocks of the time slot need to be buffered, and then the data code blocks in each time slot are allocated based on the overhead frame determined by all the overhead blocks. In this case, the impact of inserting overhead frames on the code block stream can be effectively reduced. In this case, the overhead blocks may be inserted periodically, and the number of code blocks included in the insertion period may be an integer multiple of the total number of time slots included in one slot cycle.

For example, an overhead frame includes two overhead blocks, and the overhead frame is inserted periodically, and the period for inserting the overhead frame is 2500 time slot periods. In one case, if two overhead blocks are inserted into the code block stream at the same time, then the code block The format of the stream can be seen in Figure 6a. The code block stream includes: overhead frame, 2500 timeslot periods, overhead frames, 2500 timeslot periods, ...; in another case, if two

overhead blocks

1 and 2 are inserted into the code block stream respectively, and are separated by 2 timeslot periods, then the format of the code block stream can be seen in Figure 6b. The code block stream sequentially includes:

overhead block

1, 2 timeslot periods, overhead Block 2, 2498 slot periods,

overhead block

1, 2 slot periods, overhead block 2, 2498 slot periods, . . .

For the process of sending overhead frames, for example, before sending data code blocks, the overhead blocks are continuously sent until all the overhead blocks included in the overhead frame are received and identified, and then, from the next non-overhead frame (the next non-overhead frame) The overhead frame is the data code block adjacent to the last overhead block, for example, can be identified by the overhead block identification field) as the starting point of sending the data code block, and starts to send the code block stream including the data code block to the opposite end. For another example, overhead blocks can also be sent periodically, that is, a fixed number of data code blocks are spaced between two adjacent overhead blocks, for example, 10 data code blocks are spaced between two adjacent overhead blocks. When the opposite end determines that all the overhead blocks included in the overhead frame are received and recognized, it may feed back an acknowledgement signal through the overhead frame to trigger the sending end to no longer send the overhead blocks. It should be noted that, in the above two examples, if there is an operation of losing the lock during operation or the configuration needs to be modified, the entire process of sending the overhead frame needs to be restarted.

The above-mentioned first example is an example of the first possible implementation manner provided by the embodiment of the present application. For the corresponding data processing method in this implementation manner, reference may be made to the related descriptions in the following method 100 and method 200; similarly, The above second example is an example of the second possible implementation manner provided by the embodiment of the present application. For the corresponding data processing method in this implementation manner, reference may be made to the related descriptions in the following method 300 and method 400 .

The specific implementation of a data processing method in the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

In a data processing method provided by an embodiment of the present application, data is processed by a flexible interface in a MAC chip and a PHY chip, so as to achieve the effect of orderly transmission of multiple data streams of different rates between the MAC chip and the PHY chip. For example, the method can be implemented in the scenario shown in FIG. 1 , where the MAC chip is the MAC chip 10 in FIG. 1 , the PHY chip is the PHY chip 20 , and the flexible interface corresponds to the flexible interface 100 in the MAC chip 10 and the interface in the PHY chip 20 . Flexible interface 200.

The following method 100 and method 200 correspond to the first possible implementation manner, wherein the method 100 takes the process of sending data from the MAC chip 10 to the PHY chip 20 as an example to introduce the data processing process performed by the flexible interface; The process of sending data to the MAC chip 10 is taken as an example to introduce the data processing process performed by the MII. The following methods 300 and 400 correspond to the second possible implementation manner, wherein the method 300 takes the process of sending data from the MAC chip 10 to the PHY chip 20 as an example to introduce the data processing process performed by the flexible interface; The process of sending data to the MAC chip 10 is taken as an example to introduce the data processing process performed by the flexible interface.

In the following methods 100 to 400, the total bandwidth supported by the flexible interface is considered in the process that the encoding unit encodes the data code stream to obtain the data code block. If the total bandwidth supported by the flexible interface 100 is less than 40 Gb/s, the encoding unit 120 performs 66B/68B encoding according to the method in Clause 49 of IEEE 802.3; if the total bandwidth supported by the flexible interface 100 is greater than or equal to 40 Gb/s, the encoding unit 120 performs 66B/68B encoding is performed in the manner of Clause 82 in IEEE 802.3.

FIG. 7 is a schematic flowchart of a data processing method 100 in an embodiment of the present application. S101 to S105 in the method 100 are performed by the flexible interface 100 in the MAC chip 10 , and S106 to S107 are performed by the flexible interface 200 in the PHY chip 20 . Referring to FIG. 7, the method 100 may include, for example:

S101, the overhead frame control unit 110 in the MII 100 generates a first overhead frame according to the data stream from each MAC module, where the first overhead frame is used to indicate the time slot corresponding to each data stream.

It should be noted that, before the flexible interface 100 receives the data code stream corresponding to each MAC module, each MAC module will process the MAC frame stream to be sent to the PHY chip 20 by connecting the corresponding RS to each MAC module to obtain the data code. stream, and send the data stream to the flexible interface 100 through the corresponding port. It should be noted that, the processing of the MAC frame stream by the RS may be, for example, by dividing the MAC frame stream based on the rate supported by the MAC module from which the MAC frame stream comes to obtain a data stream. If the rate of the MAC module 1 is 10Gb/s, the same The RS 1 connected to the MAC module 1 can divide the MAC frame stream 1 from the MAC module 1 into 32-bit data streams; if the rate of the MAC module N is 1Gb/s, the RS N connected to the MAC module N can The MAC frame stream N from the MAC module N is divided into 8-bit data streams.

After receiving the data stream, the flexible interface 100 may generate a first overhead frame based on the data stream. For a description of the first overhead frame, please refer to the description of the overhead frame 1 in the first example above, and the specific format may refer to FIG. 2a and 2b and related descriptions.

S102, the encoding unit 120 in the flexible interface 100 encodes the data code stream from each MAC module to obtain a data code block corresponding to each MAC module.

The total bandwidth supported by the flexible interface 100 depends on the total bandwidth of the PHY chip 20 , and the total bandwidth of the PHY chip 20 may be the sum of the rates supported by each PHY module in the PHY chip 20 .

It should be noted that the execution of S101 and S102 is not limited in order. S101 may be executed first and then S102 may be executed, or S102 may be executed first and then S101, or S101 and S102 may be executed simultaneously, which is not specifically limited in this embodiment.

S103, the allocation unit 130 in the flexible interface 100 inserts each data code block into the corresponding time slot based on the first overhead frame, and generates a first code block stream, where the first code block stream includes the first overhead frame and the inserted data code block slot.

Wherein, inserting each data code block into the corresponding time slot may refer to inserting each data code block into the corresponding position of the time slot corresponding to the time slot period in the code block stream to obtain the first code block stream to be sent.

For example, if the total bandwidth supported by the flexible interface 100 is 20Gb/s, and one slot cycle includes 8 slots, the lower 4 bits of each slot field in the first overhead frame indicate the Client Rate, and the upper 4 bits indicate the Client ID. The rate supported by MAC module 1 is 1.25GB/s, the rate supported by MAC module 2 is 1Gb/s, the rate supported by MAC module 3 is 2.5Gb/s, and the rate supported by MAC module 4 is 5Gb/s. The first overhead frame is shown in Figure 8a. In the field of time slot 1, Client Rate=0x06, and the Client ID indicates MAC module 4; in the field of time slot 2, Client Rate=0x3, and the Client ID indicates MAC module 2; in the field of time slot 3, the Client Rate=0x6, Client ID indicates MAC module 4; slot 4 field is empty; Client Rate=0x5 in slot 5 field, Client ID indicates MAC module 3; slot 6 field is empty; in slot 7 field Client Rate= 0x4, Client ID indicates MAC module 1, slot 8 is empty. In this scenario, after S103, the format of the generated first code block stream can be referred to, for example, FIG. 3a.

For another example, if the total bandwidth supported by the flexible interface 100 is 10 Gb/s, and one slot cycle includes 10 slots, the lower 4 bits of each slot field in the first overhead frame indicate the Client Rate, and the upper 4 bits indicate the Client ID. . The rate supported by the MAC module 1 is 100MB/s, the rate supported by the MAC module 2 is 1Gb/s, the rate supported by the MAC module 3 is 5Gb/s, and the rate supported by the MAC module 4 is 1Gb/s. The first overhead frame is shown in Figure 8b. In the fields of time slot 1 to time slot 5, Client Rate=0x6, and Client ID indicates MAC module 3; in the time slot 6 field, Client Rate=0x3, and Client ID indicates MAC module 2; Client Rate=0x3 in slot 7 field, Client ID indicates MAC module 4; Client Rate=0x2 in slot 8 field, Client ID indicates MAC module 1; slot 9 field and slot 10 field are empty. In this scenario, after S103, the format of the generated first code block stream can be seen, for example, as shown in FIG. 9. In each time slot cycle, the data code block corresponding to the MAC module 3 occupies time slot 1 to time slot 5, and the MAC The data code blocks corresponding to the module 2 and the MAC module 4 occupy time slot 6 and time slot 7 respectively, and the data code block corresponding to the MAC module 1 is inserted in every 10 time slot cycles, and the data code block corresponding to the MAC module 1 occupies In the time slot 8, in the time slot period in which the data code block corresponding to the MAC module 1 is not inserted, a special code block (such as an idle control code block or an error control code block) is used to occupy the time slot 8.

It should be noted that the above example only shows the case of inserting the first overhead frame at the beginning of the first code block stream, and does not consider the case of inserting the overhead frame into the first code block stream multiple times, inserting the overhead multiple times. The frame situation and related explanations can be referred to the above-mentioned Fig. 6a and Fig. 6b and the corresponding description.

S104, the SerDes 140 in the flexible interface 100 performs serialization processing on the first code block stream to obtain a first processing result.

It should be noted that, S104 is an optional step.

Serializing the first code block stream can ensure orderly transmission of the first code block stream through the physical channel 300 .

As an example, the flexible interface 100 may further include a scrambling code processing unit 150 for scrambling the first code block stream obtained by the allocation unit 130 to obtain an updated first code block stream; then, the The SerDes 140 performs serialization processing on the updated first code block stream to obtain a first processing result. In this way, by scrambling the first code block stream, the data sent to the PHY chip 20 can be more balanced.

S105, the flexible interface 100 sends the first processing result to the MII 200 through the physical channel 300.

With the flexible interfaces and data processing methods provided by the embodiments of the present application, effective communication between multiple MAC modules and multiple PHY modules can be completed only through a pair of physical channels between the MAC chip 10 and the PHY chip 20 .

S106, the SerDes 240 in the flexible interface 200 deserializes the first processing result to obtain a first code block stream.

It should be noted that, S106 is an optional step.

If the first processing result is the result of serializing the first code block stream by the SerDes 140 in the flexible interface 100, then the flexible interface 200 also needs to perform deserializing processing on the received first processing result through the SerDes 240 , to get the first code block stream. The serialization process performed by the SerDes 140 and the deserialization process performed by the SerDes 240 are inverse processes, that is, B is obtained by serializing A, and A is obtained by deserializing B.

As an example, if the first code block stream is also scrambled in the flexible interface 100, the flexible interface 200 also includes a scrambling code processing unit 250, configured to descramble the deserialized code block stream , get the first code block stream. It should be noted that the execution sequence of the operations of deserializing and descrambling the received data in the above flexible interface 200 is only exemplary, and the first processing result received may also be descrambled first. Then, deserialize the result of descrambling to obtain the first code block stream.

S107 , the allocation unit 230 in the flexible interface 200 allocates each data code block in the first code block stream to each PHY module in the PHY chip 20 based on the first overhead frame in the first code block stream.

As an example, the flexible interface 200 may include a mapping relationship 1 between the MAC module and the PHY module. Then, the allocation unit 230 may determine the MAC module from which the data code blocks in each time slot come from based on the first overhead frame, and then comprehensively consider the mapping According to the relationship 1 and the indication of the first overhead frame, the data code blocks in each time slot are accurately allocated to the corresponding PHY modules.

As another example, the flexible interface 200 may also include the mapping relationship 2 between each time slot and the PHY module, then the allocation unit 230 can accurately allocate the data code blocks in each time slot based on the indication of the mapping relationship 2 to the corresponding PHY module.

It should be noted that after the PHY module receives the corresponding data code block, it can perform standard processing on the data code block. Access (English: physical medium attachment, referred to as: PMA) processing or forward error correction (English: forward error correction, referred to as: FEC) processing and so on.

It can be seen that, through the method 100 provided in the embodiment of the present application, the flexible interface in the MAC chip generates an overhead frame, and the overhead frame can indicate the time slot occupied by the data code block corresponding to each MAC module. In this way, the flexible interface can follow the overhead frame. Instructs to accurately fill the corresponding data code block in the time slot of the code block stream, and insert the overhead frame into the code block stream and send it to the PHY chip. The flexible interface in the PHY chip can also be determined according to the overhead frame in the code block stream. The PHY module corresponding to the data code block in each time slot, so that each data code block in the code block stream is allocated to multiple PHY modules in the PHY chip, so as to realize various data codes of different rates between the PHY chip and the MAC chip The effect of orderly transmission of streams satisfies the demand for better communication between the PHY chip and the MAC chip.

FIG. 10 is a schematic flowchart of a data processing method 200 in an embodiment of the present application. S201 - S205 in the method 200 are performed by the flexible interface 200 in the PHY chip 20 , and S206 - S207 are performed by the flexible interface 100 in the MAC chip 10 . Referring to FIG. 10, the method 200 may include, for example:

S201 , the overhead frame control unit 210 in the flexible interface 200 generates a second overhead frame according to the data stream from each PHY module, where the second overhead frame is used to indicate the time slot corresponding to each data stream.

After receiving the data code stream, the flexible interface 200 may generate a second overhead frame based on the data code stream. For the relevant description of the second overhead frame, please refer to the relevant description of the overhead frame 1 in the first example above, and the specific format may refer to FIG. 2a and FIG. 2b and related descriptions, the difference is that the time slot field in the second overhead frame includes the rate supported by the PHY module corresponding to the time slot and the identifier of the PHY module.

S202, the encoding unit 220 in the flexible interface 200 encodes the data code stream from each PHY module to obtain a data code block corresponding to each PHY module.

It should be noted that the execution of S201 and S202 is not limited in sequence. S201 may be executed first and then S202 may be executed, or S202 may be executed first and then S201 may be executed, or S201 and S202 may be executed simultaneously, which is not specifically limited in this embodiment.

S203, the allocation unit 230 in the flexible interface 200 inserts each data code block into the corresponding time slot based on the second overhead frame, and generates a second code block stream, where the second code block stream includes the second overhead frame and the inserted data code block time slot.

Wherein, inserting each data code block into the corresponding time slot may refer to inserting each data code block into the corresponding position of the time slot corresponding to the time slot period in the code block stream to obtain the second code block stream to be sent.

S204, the SerDes 240 in the flexible interface 200 performs serialization processing on the second code block stream to obtain a second processing result.

It should be noted that S204 is an optional step.

As an example, the flexible interface 200 may further include a scrambling code processing unit 250, configured to scramble the second code block stream obtained by the allocation unit 230 to obtain an updated second code block stream; then, the SerDes 240 serializes the updated second code block stream to obtain a second processing result. In this way, the data sent to the MAC chip 10 can be more balanced by scrambling the second code block stream.

S205 , the flexible interface 200 sends the second processing result to the flexible interface 100 through the physical channel 300 .

S206, the SerDes 140 in the flexible interface 100 deserializes the second processing result to obtain a second code block stream.

It should be noted that S206 is an optional step.

If the second processing result is the result of serializing the second code block stream by the SerDes 240 in the flexible interface 200, the flexible interface 100 also needs to perform deserializing processing on the received second processing result through the SerDes 140 , to obtain the second code block stream.

As an example, if the second code block stream is also scrambled in the flexible interface 200, the flexible interface 100 also includes a scrambling code processing unit 150, configured to descramble the deserialized code block stream , to obtain the second code block stream.

S207 , the allocation unit 130 in the flexible interface 100 allocates each data code block in the second code block stream to each MAC module in the MAC chip 10 based on the second overhead frame in the second code block stream.

As an example, the flexible interface 100 may include a mapping relationship 1 between the MAC module and the PHY module. Then, the allocation unit 130 may determine, based on the second overhead frame, the PHY module from which the data code blocks in each time slot come from, and then comprehensively consider the mapping According to the indication of relation 1 and the second overhead frame, the data code blocks in each time slot are accurately allocated to the corresponding MAC module.

As another example, the flexible interface 100 may also include the mapping relationship 3 between each time slot and the MAC module, then the allocation unit 130 can accurately allocate the data code blocks in each time slot based on the indication of the mapping relationship 3 to the corresponding PHY module.

It should be noted that, S207 may specifically refer to: the flexible interface 100 sends the data code blocks to the RS corresponding to each MAC module through a plurality of ports, and the RS performs corresponding processing and sends the data block to the MAC module.

It can be seen that, through the method 200 provided by the embodiment of the present application, the flexible interface in the PHY chip generates an overhead frame, and the overhead frame can indicate the time slot occupied by the data code block corresponding to each PHY module. In this way, the flexible interface can follow the overhead frame. Instructs to accurately fill the corresponding data code block in the time slot of the code block stream, and insert the overhead frame into the code block stream and send it to the MAC chip. The flexible interface in the MAC chip can also be determined according to the overhead frame in the code block stream. The MAC module corresponding to the data code block in each time slot, so that each data code block in the code block stream is allocated to multiple MAC modules in the MAC chip, so as to realize various data codes of different rates between the PHY chip and the MAC chip The effect of orderly transmission of streams satisfies the demand for better communication between the PHY chip and the MAC chip.

It should be noted that, in the following methods 300 and 400, configuration information needs to be stored in both the MAC chip 10 and the PHY chip 20. For security and reliability, the configuration information may be hardened on the chip by hardware and cannot be Modified content. In addition, the registers of the MAC chip 10 and the PHY chip 20 both store the operation mode, and the operation mode corresponds to the configuration information. After the flexible interface reads the operation mode, it can automatically process data according to the configuration information corresponding to the operation mode.

In some embodiments, in the method 300 and the method 400, there may be a one-to-one correspondence between the PHY module and the MAC module, the rates supported by each MAC module are the same or different, and the rates supported by each PHY module are the same or different, The rates of the MAC block and the PHY block are the same or different. The first configuration information on the PHY chip 20 is used to indicate the corresponding relationship between the PHY module and the time slot, and the second configuration information on the MAC chip 10 is used to indicate the corresponding relationship between the MAC module and the time slot. The number of times each PHY module or MAC module appears in the configuration information can be determined according to the rate supported by the PHY module or MAC module and the equivalent bandwidth corresponding to each time slot. For example, the equivalent bandwidth of each time slot is 2.5 Gb/s, the rate supported by each MAC module is also 2.5Gb/s, then in the second configuration information, each MAC module corresponds to a time slot in a time slot period; for another example, the equivalent bandwidth of each time slot is 2.5Gb/s, and the rate supported by each MAC module is also 5Gb/s. In the second configuration information, each MAC module corresponds to two time slots in one time slot period, and the two time slots corresponding to the same MAC module can be It is an adjacent time slot in the time slot period, or it can be a non-adjacent time slot in the time slot period. For the specific content of the configuration information, see Table 3 to Table 7 and related descriptions above.

FIG. 11 is a schematic flowchart of a data processing method 300 in an embodiment of the present application. S301 to S305 in the method 300 are performed by the flexible interface 100 in the MAC chip 10 , and S306 to S307 are performed by the flexible interface 200 in the PHY chip 20 . Referring to FIG. 11 , the method 300 may include, for example:

S301 , the overhead frame control unit 110 in the flexible interface 100 generates a third overhead frame, where the third overhead frame is used to indicate the starting position of the stream of code blocks to be transmitted.

After receiving the data code stream, the flexible interface 100 may generate a third overhead frame based on the data code stream. For the relevant description of the third overhead frame, please refer to the relevant description of the overhead frame 2 in the second example above, and the specific format may refer to FIG. 4 and related instructions.

S302, the encoding unit 120 in the flexible interface 100 encodes the data code stream from each MAC module to obtain a data code block corresponding to each MAC module.

It should be noted that the execution of S301 and S302 is not limited in order. S301 may be executed first and then S302 may be executed, or S302 may be executed first and then S301 may be executed, or S301 and S302 may be executed simultaneously, which is not specifically limited in this embodiment.

S303, the allocation unit 130 in the flexible interface 100 inserts each data code block into the corresponding time slot according to the second configuration information, and generates a third code block stream, where the third code block stream includes a third overhead frame and an inserted data code block time slot.

Wherein, inserting each data code block into the corresponding time slot may refer to inserting each data code block into the corresponding position of the time slot corresponding to the time slot period in the code block stream to obtain the third code block stream to be sent.

For example, if the second configuration information is shown in Table 6 above, the generated third code block stream may include: the third overhead frame, the time slot 1 corresponding to the MAC module 1, the time slot 2 corresponding to the MAC module 2, and the MAC module Time slot 1 corresponding to 3, time slot 2 corresponding to MAC module 4, time slot 1 corresponding to MAC module 5, time slot 2 corresponding to MAC module 6, time slot 1 corresponding to MAC module 7, time slot corresponding to MAC module 8 2. Time slot 1 corresponding to MAC module 1, time slot 2 corresponding to MAC module 2, . . .

For another example, if the second configuration information is shown in Table 5 above, the generated third code block stream may include: the third overhead frame, the time slot 1 corresponding to the MAC module 1, the time slot 2 corresponding to the MAC module 2, and the MAC Time slot 3 corresponding to module 3, time slot 4 corresponding to MAC module 4, time slot 5 corresponding to MAC module 5, time slot 6 corresponding to MAC module 6, time slot 7 corresponding to MAC module 7, time slot corresponding to MAC module 8 Slot 8, time slot 1 corresponding to MAC module 1, time slot 2 corresponding to MAC module 2, . . .

It should be noted that the above example only shows the case where the third overhead frame is inserted at the beginning of the third code block stream, and does not consider the case where the overhead frame is inserted into the third code block stream multiple times, and the overhead is inserted multiple times. The frame situation and related explanations can refer to the above-mentioned Fig. 6a and Fig. 6b and the corresponding description.

S304, the SerDes 140 in the flexible interface 100 performs serialization processing on the third code block stream to obtain a third processing result.

It should be noted that S304 is an optional step.

As an example, the flexible interface 100 may further include a scrambling code processing unit 150, configured to scramble the third code block stream obtained by the allocation unit 130 to obtain an updated third code block stream; then, in the flexible interface 100 The SerDes 140 serializes the updated third code block stream to obtain a third processing result. In this way, the data sent to the PHY chip 20 can be more balanced by scrambling the third code block stream.

S305 , the flexible interface 100 sends the third processing result to the flexible interface 200 through the physical channel 300 .

S306, the SerDes 240 in the flexible interface 200 deserializes the third processing result to obtain a third code block stream.

It should be noted that S306 is an optional step.

If the third processing result is the result of serializing the third code block stream by the SerDes 140 in the flexible interface 100, then the flexible interface 200 also needs to use the SerDes 240 to deserialize the received third processing result. , to obtain the third code block stream.

As an example, if the third code block stream is also scrambled in the flexible interface 100, the flexible interface 200 also includes a scrambling code processing unit 250, configured to descramble the deserialized code block stream , get the third code block stream.

S307 , the allocation unit 230 in the flexible interface 200 allocates each data code block in the third code block stream to each PHY module in the PHY chip 20 based on the first configuration information and the third overhead frame.

For example, if the second configuration information on the MAC chip 10 is as shown in Table 5 above, then the first configuration information stored on the PHY chip 20 may be as shown in Table 3 above.

It should be noted that, after the PHY module receives the corresponding data code block, it can perform standard processing on the data code block, for example, through PCS processing, PMA processing, or FEC processing.

It can be seen that, through the method 300 provided in this embodiment of the present application, the flexible interface in the MAC chip generates an overhead frame, and the overhead frame can indicate the starting position of the stream of code blocks to be transmitted, and the MAC chip includes an overhead frame for indicating the difference between the MAC module and the time slot. In this way, the flexible interface can accurately fill the corresponding data block in the time slot of the code block stream according to the instructions of the configuration information, and insert the overhead frame into the code block stream and send it to the PHY chip. The flexible interface in the PHY chip can also determine the starting position of the code block stream according to the overhead frame in the code block stream, and determine each time based on the configuration information stored in the PHY chip to indicate the correspondence between the PHY module and the time slot. The PHY module corresponding to the data code block in the slot, so that each data code block in the code block stream is allocated to multiple PHY modules in the PHY chip, and the effect of orderly transmission of the data code stream between the PHY chip and the MAC chip is realized. It meets the demand for better communication between the PHY chip and the MAC chip.

FIG. 12 is a schematic flowchart of a data processing method 400 in an embodiment of the present application. S401 to S405 in the method 400 are performed by the flexible interface 200 in the PHY chip 20 , and S406 to S407 are performed by the flexible interface 100 in the MAC chip 10 . Referring to Figure 12, the method 400 may include, for example:

S401 , the overhead frame control unit 210 in the flexible interface 200 generates a fourth overhead frame, where the fourth overhead frame is used to indicate the starting position of the stream of code blocks to be transmitted.

After receiving the data code stream, the flexible interface 200 may generate a fourth overhead frame based on the data code stream. For the relevant description of the fourth overhead frame, please refer to the relevant description of the overhead frame 2 in the second example above, and the specific format can be referred to in FIG. 4 and related instructions.

S402, the encoding unit 220 in the flexible interface 200 encodes the data code stream from each PHY module to obtain a data code block corresponding to each MAC module.

It should be noted that the execution of S401 and S402 is not limited in sequence. S401 may be executed first and then S402 may be executed, or S402 may be executed first and then S401 may be executed, or S401 and S402 may be executed simultaneously, which is not specifically limited in this embodiment.

S403, the allocation unit 230 in the flexible interface 200 inserts each data code block into the corresponding time slot based on the first configuration information, and generates a fourth code block stream, where the fourth code block stream includes a fourth overhead frame and an inserted data code block time slot.

Inserting each data code block into the corresponding time slot may refer to inserting each data code block into the corresponding position of the time slot corresponding to the time slot period in the code block stream to obtain the fourth code block stream to be sent.

S404, the SerDes 240 in the flexible interface 200 serializes the fourth code block stream to obtain a fourth processing result.

It should be noted that S404 is an optional step.

As an example, the flexible interface 200 may further include a scrambling code processing unit 250, configured to scramble the fourth code block stream obtained by the allocation unit 230 to obtain an updated fourth code block stream; then, in the flexible interface 200 SerDes 240 serializes the updated fourth code block stream to obtain a fourth processing result. In this way, by performing scrambling processing on the fourth code block stream, the data sent to the MAC chip 10 can be more balanced.

S405 , the flexible interface 200 sends the fourth processing result to the flexible interface 100 through the physical channel 300 .

S406, the SerDes 140 in the flexible interface 100 deserializes the fourth processing result to obtain a fourth code block stream.

It should be noted that S406 is an optional step.

If the fourth processing result is the result of serializing the fourth code block stream by the SerDes 240 in the flexible interface 200, then the flexible interface 100 also needs to perform deserializing processing on the received fourth processing result through the SerDes 140 , to obtain the fourth code block stream.

As an example, if the fourth code block stream is also scrambled in the flexible interface 200, then the flexible interface 100 also includes a scrambling code processing unit 150, configured to descramble the deserialized code block stream code to obtain the fourth code block stream.

S407 , the allocation unit 130 in the flexible interface 100 allocates each data code block in the fourth code block stream to each MAC module in the MAC chip 10 based on the second configuration information and the fourth overhead frame.

For example, if the first configuration information stored on the PHY chip 20 is as shown in Table 3 above, then the second configuration information on the MAC chip 10 may be as shown in Table 5 above.

It should be noted that S407 may specifically refer to: the flexible interface 100 sends the data code blocks to the RS corresponding to each MAC module respectively through multiple ports, and the RS performs corresponding processing and sends the data block to the MAC module.

It can be seen that, through the method 400 provided in this embodiment of the present application, the flexible interface in the PHY chip generates an overhead frame, where the overhead frame can indicate the starting position of the stream of code blocks to be transmitted, and the PHY chip includes an overhead frame for indicating the difference between the PHY module and the time slot. In this way, the flexible interface can accurately fill the corresponding data code block in the time slot of the code block stream according to the instructions of the configuration information, and insert the overhead frame into the code block stream and send it to the MAC chip. The flexible interface in the MAC chip can also determine the starting position of the code block stream according to the overhead frame in the code block stream, and determine each time based on the configuration information stored in the MAC chip to indicate the correspondence between the MAC module and the time slot. The MAC module corresponding to the data code block in the slot, so that each data code block in the code block stream is allocated to multiple MAC modules in the MAC chip, and the effect of orderly transmission of the data code stream between the PHY chip and the MAC chip is realized. It meets the demand for better communication between the PHY chip and the MAC chip.

It should be noted that, in the above method 100 and method 200, each time slot corresponds to only one MAC module. However, the rates supported by each MAC module may be different, and the MAC module with a smaller rate and the MAC module with a larger rate occupy the same time slot bandwidth. In this way, the MAC module supporting the smaller rate will waste the bandwidth on the time slot. resource. For example, the equivalent bandwidth of each time slot is 2.5Gb/s, but the rate supported by a certain MAC module is 100Mb/s, then the MAC module occupies the time slot in each time slot cycle, and the time slot waste of bandwidth resources. Based on this, the embodiments of the present application also provide a mechanism to support multiplexing of a time slot by at least two MAC modules, that is, data code blocks corresponding to multiple MAC modules occupy the same time slot in different time slot periods respectively. gaps to improve resource utilization.

Taking the first overhead frame in method 100 as an example, the first overhead frame may further include multiplexing indication information, which is used to indicate that a certain time slot is multiplexed by multiple MAC modules.

As an example, the multiplexing indication information may be carried by the time slot field corresponding to the multiplexed time slot, and the value of the time slot field corresponding to the multiplexed time slot is a specific value (for example, each of the time slot fields The value of each bit is 1, for example, the value of each bit in the time slot field is 0), which is used to identify that the time slot corresponding to the time slot field is multiplexed by multiple MAC modules.

In one case, the first overhead frame can use the extended overhead block to indicate at least two MAC module identifiers (English: Client ID) and the rate supported by the MAC module (English: Client ID) corresponding to the multiplexed time slot. : Client Rate). In this way, the first overhead frame only needs to be inserted before the first slot cycle of the first code block stream, and the first overhead frame does not need to be inserted before each slot cycle in the future, and the first overhead frame can also be ordered according to the first overhead frame. The accurate insertion of the data code blocks corresponding to each MAC module is completed to generate the first code block stream.

For example, assuming that the time slot 1 is multiplexed by the MAC module 1 and the MAC module 2, the first overhead frame may add an extended overhead block 3 based on the overhead frame 1 shown in FIG. 2b, as shown in FIG. 13a. The value of the time slot 1 field in the overhead block 1 is 8'hFF (that is, all 8 bits are 1), and the extended overhead block 3 may include: SH field=01, the identifier of the multiplexed time slot 0 , time slot 0 subfield 1 and time slot 0 subfield 2, wherein, time slot 0 subfield 1 is used to carry the identification of MAC module 1 (English: Client ID 1) and the rate supported by MAC module 1 (English: Client Rate1 ), the subfield 2 of the slot 0 is used to carry the identification of the MAC module 2 (English: Client ID 2) and the rate supported by the MAC module 2 (English: Client Rate 2). In addition, the extended overhead block 3 may also include fields such as Reserved and CRC.

For another example, it is assumed that time slot 1 is multiplexed by MAC module 1 and MAC module 2 , and time slot 3 is multiplexed by MAC module 4 , MAC module 5 and MAC module 6 . In one way, the first overhead frame may add an extended overhead block 4 on the basis of the overhead frame 1 shown in FIG. 13a, as shown in FIG. 13b. Among them, the value of the time slot 1 field and the time slot 3 field in the overhead block 1 are both 8'hFF. As shown in Figure 13a in the extended overhead block 3, the extended overhead block 4 may include: SH field=01, which is The identifier of the multiplexed time slot 3, the time slot 3 subfield, the time slot 3 subfield 2 and the time slot 3 subfield 3, wherein, the time slot 3 subfield 1 is used to carry the identification of the MAC module 4 (English: Client ID 4 ) and the rate supported by the MAC module 4 (English: Client Rate 4), the time slot 3 subfield 2 is used to carry the identification of the MAC module 5 (English: Client ID5) and the rate supported by the MAC module 5 (English: Client Rate 5) , the subfield 3 of the time slot 3 is used to carry the identification of the MAC module 6 (English: Client ID 6) and the rate supported by the MAC module 6 (English: Client Rate 6). In addition, the extended overhead block 4 may also include fields such as Reserved and CRC. In another way, the first overhead frame may add information about multiplexing of timeslot 3 in the extended overhead block 3 of the overhead frame 1 shown in FIG. 13a, as shown in FIG. 13c. The value of the time slot 1 field and the time slot 3 field in the overhead block 1 are both 8'hFF, and the extended overhead block 3 may include: SH field=01, the identifier of the multiplexed time slot 0, and the time slot 0 Subfield 1, subfield 2 of slot 0, identification of multiplexed slot 3, subfield 1 of slot 3, subfield 2 of slot 3, and subfield 3 of slot 3. In addition, the extended overhead block 3 may also include fields such as Reserved and CRC.

In another case, the first overhead frame may indicate, through the Reserved field, the identifiers (English: Client ID) of at least two MAC modules corresponding to the multiplexed time slot and the rate (English: Client Rate) supported by the MAC modules. In this way, without increasing the length of the first overhead block, the guidance for inserting the data code block into the time slot in the time slot multiplexing scenario can be completed.

For example, still taking the multiplexing of time slot 1 by MAC module 1 and MAC module 2 as an example, the first overhead frame can be based on the overhead frame 1 shown in FIG. 2b, in the Reserved field after the time slot 8 field, carrying The identifier of the multiplexed time slot 0, the time slot 0 subfield 1 and the time slot 0 subfield 2 are shown in FIG. 13d for details.

It should be noted that in this case, if there are fewer multiplexed time slots and the number of MAC modules multiplexing the time slot is small, the multiplexed time slot and the relevant information of the MAC module corresponding to the time slot can be carried in the In the Reserved field, there is no need to insert the first overhead frame including the relevant information of the MAC module corresponding to the multiplexed timeslot under the timeslot period before each timeslot period. If the multiplexed time slot and the relevant information of the MAC module corresponding to the time slot cannot all be carried in the Reserved field, a first overhead frame can be inserted before each time slot period, and the Reserved field of the first overhead frame can be inserted It includes the relevant information of the MAC module corresponding to the multiplexed timeslot under the timeslot period.

As another example, the multiplexing indication information may also be borne by several bits of the time slots included in a time slot period in the Reserved field (also referred to as the multiplexing enable identification field). For example, the multiplexing enable Each bit in the identification field corresponds to a time slot. When the value of this bit is 1, it means that the time slot corresponding to this bit is multiplexed. When the value of this bit is 0, it means that the corresponding time slot of this bit is Slots are not multiplexed. In this example, once a multiplexed time slot is indicated in the multiplexing enable flag field, a first overhead frame needs to be inserted before each time slot period, and the multiplexed time slot in the first overhead frame corresponds to In the slot field of , it carries the identifier and rate of the MAC module occupying the slot in the current slot cycle.

For example, still taking the multiplexing of time slot 1 by MAC module 1 and MAC module 2 as an example, then, the first overhead frame can be based on the overhead frame 1 shown in FIG. The multiplexing enable flag field, as shown in Figure 14a, in the first overhead frame generated and inserted before the first time slot period, the 0th bit of the multiplexing enable flag field is 1, and the time slot The 1 field carries the identification of MAC module 1 (English: Client ID 1) and the rate supported by MAC module 1 (English: Client Rate 1); as shown in Figure 14b, before the second slot cycle, the first generated and inserted In the overhead frame, the 0th bit of the multiplexing enable identification field is 1, and the time slot 1 field is used to carry the identification of the MAC module 2 (English: Client ID 2) and the rate supported by the MAC module 2 (English: Client Rate 2); Before the third time slot cycle, the first overhead frame generated and inserted is shown in Figure 14a; before the fourth time slot cycle, the first overhead frame generated and inserted is shown in Figure 14b; like this Reciprocating, realizing the indication of the correspondence between the multiplexed time slot and the MAC module.

It should be noted that in this example, the corresponding relationship between the multiplexed time slot and the MAC module can be carried in the first overhead frame by adding an extended overhead block, so that there is no need to insert the corresponding relationship before each time slot period. Therefore, the resources of the first code block stream occupied by the first overhead frame are reduced, and the impact of inserting the first overhead frame on data transmission between the MAC chip 10 and the PHY chip 20 can also be reduced.

In order to increase the total number of ports supported by the flexible interface and make full use of the total bandwidth supported by the flexible interface to meet higher communication requirements, the embodiment of the present application also provides an extended flexible interface, which is used for cascading PHYs chip. As shown in FIG. 15 , taking the PHY chip 20 and the PHY chip 30 for cascading through an extended flexible interface as an example, the scenario of PHY chip cascading is introduced. Referring to FIG. 15, in this scenario, the PHY chip 20 includes: a flexible interface 200, a PHY module 1, a PHY module 2, . . . , a PHY module M, and an extended flexible interface 210, and the PHY chip 30 may include: an extended flexible interface 310. PHY module (M+1), PHY module (M+2), . . . , PHY module (M+K), wherein K is an integer greater than 1. The extended flexible interface 210 and the extended flexible interface 310 may also be connected through a pair of physical channels 400 .

Assuming that the bandwidth of the PHY chip 20 is 10Gb/s and the bandwidth of the PHY chip 30 is 20Gb/s, then the total bandwidth supported by the flexible interface between the PHY chip 20 and the MAC chip 10 is (10Gb/s+20Gb/s)= 30Gb/s. In this scenario, the number of MAC modules in the MAC chip 10 is greater than or equal to the total number (M+K) of PHY modules included in the two PHY chips.

In the scenario of cascading PHY chips, for the first possible implementation manner provided by the embodiment of the present application, the related operations performed by the flexible interface 100 remain unchanged. Corresponding to the method 100, the flexible interface 200 can allocate the received data code blocks in the first code block stream to the PHY module 1, PHY module 2, . . . , and PHY module M according to the first overhead frame. The interface 210 and the extended flexible interface 310 are assigned to PHY module (M+1), PHY module (M+2), . . . , PHY module (M+K). Corresponding to the method 200, the flexible interface 200 can be allocated to the PHY module (M+1), the PHY module (M+2), . code streams, and, receiving data code streams from PHY module 1, PHY module 2, ..., PHY module M, thereby generating a second overhead frame based on all received data code streams, and generating a second code block stream based on the second overhead blocks , and send the second code block stream to the MAC chip 10 .

For the second possible implementation manner provided by the embodiment of the present application, the configuration information on the MAC chip 10 and the PHY chip 20 may remain unchanged, and the PHY chip 20 can process the sent and received data based on the configuration information, and the extended The flexible interface 210 and the extended flexible interface 310 are only regarded as transmission media, and do not process data. Alternatively, in the configuration information on the PHY chip 20 , the part corresponding to the PHY module in the PHY chip 30 may be identified as the extended flexible interface 210 , and other configuration information may be stored on the PHY chip 30 , indicating that the PHY chip 30 The corresponding time slot of each PHY module, in this way, the effective transmission of data can also be realized.

FIG. 16 is a schematic structural diagram of a data processing apparatus 1600 according to an embodiment of the application. The data processing apparatus 1600 is located at or communicates with a flexible interface. The apparatus 1600 includes a first generating unit 1601, an encoding unit 1602, and a first generating unit 1601. Second generation unit 1603. In the device 1600, the interface is connected to a medium access control MAC chip, and the MAC chip includes a first MAC module and a second MAC module. The first generating unit 1601 is configured to generate a first overhead frame according to the first data code stream from the first MAC module and the second data code stream from the second MAC module, the first overhead frame The frame is used to indicate the time slot corresponding to the first data code stream and the second data code stream; the encoding unit 1602 is used to encode the first data code stream and the second data code stream respectively, obtaining the first data code block and the second data code block; the second generating unit 1603 is configured to insert the first data code block into the first time slot based on the first overhead frame, and generate the second data code block block into a second time slot to generate a first code block stream, the first code block stream including a first overhead frame, the first data code block inserted in the first time slot, the second time slot the second data code block inserted in .

In some implementations, the apparatus 1600 may further include a serializing unit and a transmitting unit. The serialization unit is used for serializing the first code block stream by using a serializer SerDes to obtain a first processing result; the sending unit is used for sending the first processing result to The first physical layer PHY chip.

As an example, the apparatus 1600 may further include: a receiving unit, a deserializing unit, and an allocating unit. The receiving unit is configured to receive the second processing result from the first PHY chip; the deserializing unit is configured to use the SerDes to deserialize the second processing result to obtain a second code block. a flow; an allocation unit configured to allocate data code blocks in the second code block flow to multiple MAC modules corresponding to the MAC chip according to the second overhead frame in the second code block flow.

In some implementations, the apparatus 1600 may further include a scrambling unit, a serializing unit, and a transmitting unit. Wherein, the scrambling unit is used for scrambling the first code block stream by using the scrambling code processing unit to obtain the updated first code block stream; the serialization unit is used for using the serializer SerDes to scramble the code block stream. The updated first code block stream is serialized to obtain a third processing result; the sending unit is configured to send the third processing result to the first physical layer PHY chip.

It can be understood that, for various specific embodiments of the apparatus 1600 shown in FIG. 16 , reference may be made to the introduction of each embodiment in the method 100 shown in FIG. 7 , and details are not repeated in this embodiment.

FIG. 17 is a schematic structural diagram of a data processing apparatus 1700 provided by an embodiment of the present application. The data processing apparatus 1700 is located at or communicates with a flexible interface. The apparatus 1700 includes: a first generating unit 1701, an encoding unit 1702 and The second generation unit 1703 . In the apparatus 1700, the interface connects the first physical layer PHY module and the second PHY module. The first generating unit 1701 is configured to generate a first overhead frame according to the first data code stream from the first PHY module and the second data code stream from the second PHY module, the first overhead frame The frame is used to indicate the time slot corresponding to the first data code stream and the second data code stream; the encoding unit 1702 is used to encode the first data code stream and the second data code stream respectively, obtaining the first data code block and the second data code block; the second generating unit 1703 is configured to insert the first data code block into the first time slot based on the first overhead frame, and generate the second data code block block into a second time slot to generate a first code block stream, the first code block stream including a first overhead frame, the first data code block inserted in the first time slot, the second time slot the second data code block inserted in .

In some implementations, the apparatus 1700 may further include a serializing unit and a transmitting unit. The serialization unit is used for serializing the first code block stream by using a serializer SerDes to obtain a first processing result; the sending unit is used for sending the first processing result to Media Access Control MAC chip.

As an example, the apparatus 1700 may further include: a receiving unit, a deserializing unit, and an allocating unit. The receiving unit is configured to receive the second processing result from the MAC chip; the deserializing unit is configured to perform deserialization processing on the second processing result by using the SerDes, and the obtained second code block stream is The second code block stream includes a second overhead frame, a third data code block, and a fourth data code block; an allocation unit is configured to divide the third data code block and the first data code block according to the second overhead frame. Four data code blocks are allocated to the first PHY module and the second PHY module, respectively.

In some implementations, the apparatus 1700 may further include a scrambling unit, a serializing unit, and a transmitting unit. Wherein, the scrambling unit is used for scrambling the first code block stream by using the scrambling code processing unit to obtain the updated first code block stream; the serialization unit is used for using the serializer SerDes to scramble the code block stream. The updated first code block stream is serialized to obtain a third processing result; a sending unit is configured to send the third processing result to the medium access control MAC chip.

It can be understood that, for various specific embodiments of the apparatus 1700 shown in FIG. 17 , reference may be made to the introduction of each embodiment in the method 200 shown in FIG. 10 , and details are not repeated in this embodiment.

FIG. 18 is a schematic structural diagram of a data processing apparatus 1800 provided by an embodiment of the present application. The data processing apparatus 1800 is located at or communicates with a flexible interface. The apparatus 1800 includes: a first generating unit 1801, an encoding unit 1802 and The second generation unit 1803 . In the device 1800, the interface is connected to a medium access control MAC chip, and the MAC chip includes a first MAC module and a second MAC module. Wherein, the first generating unit 1801 is used to generate a first overhead frame, the first overhead frame is used to indicate the starting position of the code block stream; the encoding unit 1802 is used to generate the first overhead frame from the first MAC module. The data code stream and the second data code stream from the second MAC module are encoded respectively to obtain a first data code block and a second data code block; the second generation unit 1803 is configured to be based on the first overhead frame and the second data code block. configuration information, insert the first data code block into the first time slot, insert the second data code block into the second time slot, and generate a first code block stream, where the first code block stream includes a first overhead frame , the first data code block inserted in the first time slot and the second data code block inserted in the second time slot, the configuration information is used to indicate the MAC module in the MAC chip corresponding to the time slot.

It can be understood that, for various specific implementation manners of the apparatus 1800 shown in FIG. 18 , reference may be made to the introduction of various implementation manners corresponding to S301 to S303 in the method 300 shown in FIG. 11 , and details are not repeated in this embodiment.

FIG. 19 is a schematic structural diagram of a data processing apparatus 1900 provided by an embodiment of the application. The data processing apparatus 1900 is located at or communicates with a flexible interface. The apparatus 1900 includes: an acquisition unit 1901, a determination unit 1902, and an allocation unit 1903. In the device 1900, an interface is connected to a medium access control MAC chip, and the MAC chip includes a first MAC module and a second MAC module. The obtaining unit 1901 is configured to obtain a first code block stream from a physical layer PHY chip, where the first code block stream includes a first overhead frame, a first data code block inserted in a first time slot, and a second time slot The determining unit 1902 is used to determine the starting position of the data code block in the first code block stream according to the first overhead frame; the allocation unit 1903 is used to determine the starting position of the data code block according to the configuration information , assigning the first data code block and the second data code block in the first code block stream to the first MAC module and the second MAC module respectively, and the configuration information is used to indicate Correspondence between MAC modules in the MAC chip and time slots.

It can be understood that, for various specific implementation manners of the apparatus 1900 shown in FIG. 19 , reference may be made to the introduction of various implementation manners corresponding to S407 in the method 400 shown in FIG. 12 , and details are not repeated in this embodiment.

FIG. 20 is a schematic structural diagram of a data processing apparatus 2000 according to an embodiment of the present application. The data processing apparatus 2000 is located at or communicates with a flexible interface. The apparatus 2000 includes: a first generating unit 2001 and an encoding unit 2002 and the second generation unit 2003. In the apparatus 2000, the interface is connected to a physical layer PHY chip, and the PHY chip includes a first PHY module and a second PHY module. The first generating unit 2001 is configured to generate a first overhead frame, where the first overhead frame is used to indicate the starting position of the code block stream; the encoding unit 2002 is configured to generate a first overhead frame from the first PHY module. The data code stream and the second data code stream from the second PHY module are encoded respectively to obtain a first data code block and a second data code block; the second generation unit 2003 is configured to be based on the first overhead frame and configuration information, insert the first data code block into the first time slot, insert the second data code block into the second time slot, and generate a first code block stream, where the first code block stream includes a first overhead frame , the first data code block inserted in the first time slot and the second data code block inserted in the second time slot, the configuration information is used to indicate the PHY module in the PHY chip corresponding to the time slot.

It can be understood that, for various specific implementation manners of the apparatus 2000 shown in FIG. 20 , reference may be made to the introduction of various implementation manners corresponding to S401 to S403 in the method 400 shown in FIG. 12 , and details are not repeated in this embodiment.

FIG. 21 is a schematic structural diagram of a data processing apparatus 2100 provided by an embodiment of the application. The data processing apparatus 2100 is located at or communicates with a flexible interface. The apparatus 2100 includes: an acquisition unit 2101, a determination unit 2102, and an allocation unit Unit 2103. In the device 2100, the interface is connected to a physical layer PHY chip, and the PHY chip includes a first PHY module and a second PHY module. The obtaining unit 2101 is configured to obtain a first code block stream from a medium access control MAC chip, where the first code block stream includes a first overhead frame, a first data code block inserted in a first time slot, and a second time code block. the second data code block inserted in the slot; the determining unit 2102 is used to determine the starting position of the data code block in the first code block stream according to the first overhead frame; the allocation unit 2103 is used to determine the starting position of the data code block according to the configuration information, respectively assigning the first data code block and the second data code block in the first code block stream to the first PHY module and the second PHY module, and the configuration information is used for Indicates the correspondence between the PHY module and the time slot in the PHY chip.

It can be understood that, for various specific implementation manners of the apparatus 2100 shown in FIG. 21 , reference may be made to the introduction of the various implementation manners corresponding to S307 in the method 300 shown in FIG. 11 , and details are not repeated in this embodiment.

In any implementation manner of the foregoing apparatus 1800 , apparatus 1900 , apparatus 2000 and apparatus 2100 , in the MAC chip and the PHY chip connected through the interface, the MAC module and the PHY module may be in one-to-one correspondence. The first overhead frame may include indication information for characterizing the frame as an overhead frame, and the indication information may be one or more of the following information: a synchronization header SH field, a 0x4B field, and a 0x5 field, where the value of the SH field is The value is 10.

In addition, an embodiment of the present application further provides a network device 2200, as shown in FIG. 22 . The network device 2200 includes a first communication interface 2201 , a second communication interface 2202 and a processor 2203 . Wherein, the first communication interface 2201 is used for performing the receiving operation performed by the network device in the foregoing embodiments; the second communication interface 2201 is used for performing the sending operation performed by the network device in the foregoing embodiments; the processor 2203 is used for performing the foregoing various Other operations other than the receiving operation and the sending operation performed by the network device in the embodiment.

In addition, an embodiment of the present application further provides a network device 2300, as shown in FIG. 23 . The network device 2300 includes a processor 2302 in communication with memory 2301 . The memory 2301 includes computer-readable instructions; the processor 2302 is configured to execute the computer-readable instructions, so that the network device 2300 executes the method in the embodiment shown in FIG. 7 , FIG. 10 , FIG. 11 or FIG. 12 .

In the above embodiment, the processor may be a central processing unit (English: central processing unit, abbreviation: CPU), a network processor (English: network processor, abbreviation: NP), or a combination of CPU and NP. The processor may also be an application-specific integrated circuit (English: application-specific integrated circuit, abbreviation: ASIC), a programmable logic device (English: programmable logic device, abbreviation: PLD) or a combination thereof. The above-mentioned PLD can be a complex programmable logic device (English: complex programmable logic device, abbreviation: CPLD), field programmable logic gate array (English: field-programmable gate array, abbreviation: FPGA), general array logic (English: generic array logic, abbreviation: GAL) or any combination thereof. The processor may refer to one processor, or may include multiple processors. The memory may include volatile memory (English: volatile memory), such as random-access memory (English: random-access memory, abbreviation: RAM); the memory may also include non-volatile memory (English: non-volatile memory), For example, read-only memory (English: read-only memory, abbreviation: ROM), flash memory (English: flash memory), hard disk (English: hard disk drive, abbreviation: HDD) or solid-state hard disk (English: solid-state drive, Abbreviation: SSD); the memory may also comprise a combination of the above-mentioned kinds of memory. The memory may refer to one memory, or may include multiple memories. In a specific embodiment, a computer program or instruction is stored in the memory, and the computer program or instruction includes a plurality of software modules, such as a sending module, a processing module and a receiving module. After executing each software module, the processor can perform corresponding operations according to the instructions of each software module. In this embodiment, the operation performed by a software module actually refers to the operation performed by the processor according to the instruction of the software module. After the processor executes the computer program or instructions in the memory, it can execute all operations in the data processing method according to the instructions of the computer program or instructions.

In addition, an embodiment of the present application also provides a computer-readable storage medium, where a computer program or instruction is stored in the computer-readable storage medium, and when it is run on a computer, the computer is made to execute the above FIG. 7 and FIG. 10 . , the method in the embodiment shown in FIG. 11 or FIG. 12 .

In addition, the embodiments of the present application also provide a computer program product, including a computer program or computer-readable instructions, when the computer program or the computer-readable instructions are run on a computer, the computer is caused to execute the aforementioned FIG. 7 , FIG. 10 , The method in the embodiment shown in FIG. 11 or FIG. 12 .

The "first" in the names such as the "first PHY chip" and the "first MAC module" mentioned in the application examples is only used for name identification, and does not represent the first in order. The same rule applies to "second" etc.

From the description of the above embodiments, those skilled in the art can clearly understand that all or part of the steps in the methods of the above embodiments can be implemented by means of software plus a general hardware platform. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product, and the computer software product can be stored in a storage medium, such as read-only memory (English: read-only memory, ROM)/RAM, magnetic disk, An optical disc, etc., includes several instructions for causing a computer device (which may be a personal computer, a server, or a network communication device such as a router) to execute the methods described in various embodiments or some parts of the embodiments of the present application.

Each embodiment in this specification is described in a progressive manner, and the same and similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiments and device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and reference may be made to some descriptions of the method embodiments for related parts. The device and system embodiments described above are only illustrative, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in One place, or it can be distributed over multiple network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution in this embodiment. Those of ordinary skill in the art can understand and implement it without creative effort.

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the protection scope of the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the present application, several improvements and modifications can also be made, and these improvements and modifications should also be regarded as the protection scope of the present application.

Claims

An interface, characterized in that it comprises a coding unit, an allocation unit and an overhead frame control unit, wherein:

the overhead frame control unit, configured to generate a first overhead frame based on data streams received from multiple MAC modules corresponding to the medium access control MAC chip;

the encoding unit, configured to encode the data code stream into a corresponding data code block;

The assigning unit is configured to assign the data code blocks to corresponding time slots according to the first overhead frame, and generate a first code block stream, where the first code block stream includes the first overhead frame and Multiple data code blocks.
The interface according to claim 1, wherein the first overhead frame includes the rate of the MAC module and the identifier of the MAC module corresponding to each time slot in a time slot period.
The interface according to claim 2, wherein the distribution unit is specifically used for:

According to the identifier of the MAC module corresponding to each time slot carried in the first overhead frame, the data code block corresponding to each MAC module is filled into the time slot corresponding to the identifier of the MAC module;

The first code block stream is generated according to the padded multiple data code blocks and the first overhead frame.
The interface according to any one of claims 1-3, wherein when the first time slot corresponds to the first MAC module and the second MAC module, the first overhead frame further includes first indication information, and the The first indication information is used to indicate that the first time slot is multiplexed by multiple MAC modules.
The interface according to claim 4, wherein the first overhead frame further includes an extension overhead block, wherein the extension overhead block includes an identifier of the first time slot, a rate of the first MAC module, The identity of the first MAC module, the rate of the second MAC module, and the identity of the second MAC module.
The interface according to claim 4, wherein the field corresponding to the first time slot in the first overhead frame carries the rate of the first MAC module and the first time slot period in the first time slot period. An identifier of a MAC module, carrying the rate of the second MAC module and the identifier of the second MAC module in the second time slot period, and carrying the rate and all the data of the first MAC module in the third time slot period The identifier of the first MAC module carries the rate of the second MAC module and the identifier of the second MAC module in the fourth timeslot period, and the first timeslot period is the same as the second timeslot period. Neighboringly, the second time slot period is adjacent to the third time slot period, and the third time slot period is adjacent to the fourth time slot period.
An interface, characterized by comprising a distribution unit, wherein:

The assigning unit is configured to assign, according to the first overhead frame in the first code block stream, a data code block in the first code block stream to a corresponding medium access control MAC module, the first code block stream received from the physical layer PHY chip for the interface.
The interface according to claim 7, wherein the filling frequency of the data code block corresponding to each MAC module in the first code block stream is based on the rate of the MAC module and the equivalent bandwidth corresponding to each time slot Sure.
An interface, characterized in that it comprises a coding unit, an allocation unit and an overhead frame control unit, wherein:

the overhead frame control unit, configured to generate a first overhead frame based on data code streams received from multiple PHY modules corresponding to the physical layer PHY chip;

the encoding unit, configured to encode the data code stream into a corresponding data code block;

The assigning unit is configured to assign the data code blocks to corresponding time slots according to the first overhead frame, and generate a first code block stream, where the first code block stream includes the first overhead frame and Multiple data code blocks.
The interface according to claim 9, wherein the first overhead frame includes a rate of a PHY module and an identifier of the PHY module corresponding to each time slot in a time slot period.
The interface according to claim 10, wherein the distribution unit is specifically used for:

According to the identifier of the PHY module corresponding to each time slot carried in the first overhead frame, the data code block corresponding to each PHY module is filled into the time slot corresponding to the identifier of the PHY module;

The first code block stream is generated according to the padded multiple data code blocks and the first overhead frame.
The interface according to any one of claims 9-11, wherein the total bandwidth supported by the interface is equal to the total bandwidth of the PHY chip.
An interface, characterized by comprising a distribution unit, wherein:

The assigning unit is configured to assign, according to the first overhead frame in the first code block stream, the data code blocks in the first code block stream to the PHY module corresponding to the first physical layer PHY chip, the first code block stream The code block stream is received by the interface from the medium access control MAC chip.
The interface according to claim 13, wherein the first PHY chip further comprises a first extended interface, and the first extended interface is used to communicate with a second extended interface of the second PHY chip, The second PHY chip includes a plurality of PHY modules.
The interface according to claim 14, wherein the distribution unit is specifically used for:

Allocate some data code blocks in the first code block stream to the PHY module corresponding to the first PHY chip according to the first overhead frame in the first code block stream;

According to the first overhead frame in the first code block stream, another part of the data code blocks in the first code block stream is allocated to the The PHY module corresponding to the second PHY chip.
The interface according to claim 14 or 15, wherein the total bandwidth supported by the interface is equal to the sum of the total bandwidth of the first PHY chip and the total bandwidth of the second PHY chip.
The interface according to any one of claims 1-16, wherein the number of overhead blocks included in the first overhead frame is determined according to the number of time slots included in one slot period of the first code block stream.
The interface according to any one of claims 1-17, wherein the first overhead frame further includes any one or more of the following information:

second indication information, where the second indication information is used to represent the first overhead frame;

Time slot state identification Reset information, and the Reset information is used to represent that the time slot state is a default state or a negotiated state;

far-end PHY failure alarm RPF indicator bit; and

Local PHY failure LPF indication bit.
The interface according to claim 18, wherein the second indication information includes one or more of the following information: a synchronization header SH field, a 0x4B field, and a 0x5 field,

The value of the SH field is 10.
The interface according to claim 18 or 19, wherein the first overhead frame further includes one or more of the following information: cyclic redundancy check (CRC) information, total bandwidth supported by the interface, and reserved text.
An interface, characterized in that it comprises a coding unit, an allocation unit and an overhead frame control unit, wherein:

the overhead frame control unit, configured to generate a first overhead frame;

the encoding unit, configured to encode the data code stream into a corresponding data code block;

The allocating unit is configured to allocate the data code block to the corresponding time slot according to the configuration information to generate a first code block stream, the configuration information is used to indicate the MAC module and the time slot in the medium access control MAC chip The first code block stream includes the first overhead frame and a plurality of data code blocks, and the first overhead frame is used to indicate the starting position of the first code block stream.
An interface, characterized by comprising a distribution unit, wherein:

The allocation unit is configured to determine the position of the data code block in the first code block stream according to the first overhead frame, and allocate the data code block in the first code block stream to the medium access control according to the configuration information The MAC module corresponding to the MAC chip, the configuration information is stored in the MAC chip, and the configuration information is used to indicate the corresponding relationship between the MAC module and the time slot in the MAC chip, and the first code block stream is the The interface is received from the physical layer PHY chip.
An interface, characterized in that it comprises a coding unit, an allocation unit and an overhead frame control unit, wherein:

the overhead frame control unit, configured to generate a first overhead frame;

the encoding unit, configured to encode the data code stream into a corresponding data code block;

The allocation unit is configured to allocate the data code block to the corresponding time slot according to the configuration information, and the configuration information is used to indicate the PHY module and the time slot in the physical layer PHY chip. Correspondingly, the first code block stream includes the first overhead frame and a plurality of data code blocks, and the first overhead frame is used to indicate a starting position of the first code block stream.
An interface, characterized by comprising a distribution unit, wherein:

The allocation unit is configured to determine the position of the data code block in the first code block stream according to the first overhead frame, and allocate the data code block in the first code block stream to the physical layer PHY according to the configuration information The PHY module corresponding to the chip, the configuration information is stored in the PHY chip, and the configuration information is used to indicate the corresponding relationship between the PHY module and the time slot in the PHY chip, and the first code block stream is the interface Received from the medium access control MAC chip.
The interface according to any one of claims 21-24, wherein the MAC modules in the MAC chip correspond to the PHY modules in the PHY chip one-to-one.
The interface according to any one of claims 21-25, wherein the first overhead frame includes indication information for characterizing the frame as an overhead frame, and the indication information is one or more of the following information A: Sync header SH field, 0x4B field and 0x5 field,

The value of the SH field is 10.
The interface according to any one of claims 1-26, wherein the sum of the rates of all MAC modules in the MAC chip is less than or equal to the total bandwidth supported by the interface.
The interface according to claim 27, wherein the number of MAC modules included in the MAC chip is greater than or equal to the number of PHY modules included in the PHY chip.
The interface according to any one of claims 1-28, wherein the number of time slots included in one time slot cycle of the code block stream is equal to the number of PHY modules included in a physical layer PHY chip connected to the interface positive integer multiples.
The interface according to any one of claims 1-29, wherein the equivalent bandwidth corresponding to each time slot is the total bandwidth supported by the interface divided by the number of time slots included in one time slot cycle of the code block stream number.
The interface according to any one of claims 1-30, characterized in that, when the total bandwidth supported by the interface is less than 40 gigabits/second, the coding unit in the interface is in accordance with Article 49 in IEEE 802.3. 64B/66B encoding.
The interface according to any one of claims 1-30, wherein when the total bandwidth supported by the interface is greater than or equal to 40 gigabits/second, the coding unit in the interface is in accordance with the IEEE 802.3 No. 82 64B/66B encoding in strips.
A data processing method, characterized in that an interface is connected to a medium access control MAC chip, the MAC chip includes a first MAC module and a second MAC module, and the method includes:

A first overhead frame is generated according to the first data code stream from the first MAC module and the second data code stream from the second MAC module, where the first overhead frame is used to indicate the first data code the time slot corresponding to the stream and the second data stream;

Encoding the first data code stream and the second data code stream respectively to obtain a first data code block and a second data code block;

Based on the first overhead frame, the first data code block is inserted into a first time slot, the second data code block is inserted into a second time slot, and a first code block stream is generated, the first code block stream It includes a first overhead frame, the first data code block inserted in the first time slot, and the second data code block inserted in the second time slot.
The method of claim 33, further comprising:

Use a serializer SerDes to serialize the first code block stream to obtain a first processing result;

Send the first processing result to the first physical layer PHY chip.
The method of claim 34, further comprising:

receiving a second processing result from the first PHY chip;

Using the SerDes to perform deserialization processing on the second processing result to obtain a second code block stream;

According to the second overhead frame in the second code block stream, the data code blocks in the second code block stream are allocated to a plurality of MAC modules corresponding to the MAC chip.
The method of claim 33, further comprising:

The first code block stream is scrambled by a scrambling processing unit to obtain an updated first code block stream;

Using a serializer SerDes to serialize the updated first code block stream to obtain a third processing result;

Send the third processing result to the first physical layer PHY chip.
The method according to any one of claims 33-36, wherein the MAC chip further comprises a plurality of ports, and each port in the plurality of ports passes through a corresponding adaptation sublayer RS and a corresponding MAC module to communicate, and the method further includes:

Use RS to process the MAC frame stream sent by the corresponding MAC module into a data stream;

Alternatively, the RS is used to process the data stream received by the interface into a MAC frame stream and send it to the corresponding MAC module.
A data processing method, characterized in that an interface connects a first physical layer PHY module and a second PHY module, the method comprising:

A first overhead frame is generated according to the first data code stream from the first PHY module and the second data code stream from the second PHY module, where the first overhead frame is used to indicate the first data code the time slot corresponding to the stream and the second data stream;

Encoding the first data code stream and the second data code stream respectively to obtain a first data code block and a second data code block;

Based on the first overhead frame, the first data code block is inserted into a first time slot, the second data code block is inserted into a second time slot, and a first code block stream is generated, the first code block stream It includes a first overhead frame, the first data code block inserted in the first time slot, and the second data code block inserted in the second time slot.
The method of claim 38, further comprising:

Use a serializer SerDes to serialize the first code block stream to obtain a first processing result;

The first processing result is sent to the medium access control MAC chip.
The method of claim 39, further comprising:

receiving a second processing result from the MAC chip;

Deserialize the second processing result by using the SerDes, and obtain a second code block stream, where the second code block stream includes a second overhead frame, a third data code block, and a fourth data code block;

According to the second overhead frame, the third data code block and the fourth data code block are allocated to the first PHY module and the second PHY module, respectively.
The method of claim 38, further comprising:

The first code block stream is scrambled by a scrambling processing unit to obtain an updated first code block stream;

Using a serializer SerDes to serialize the updated first code block stream to obtain a third processing result;

The third processing result is sent to the medium access control MAC chip.
The method according to any one of claims 38-41, wherein,

the first PHY module and the second PHY module belong to a first PHY chip;

Alternatively, the first PHY module belongs to a first PHY chip, the second PHY module belongs to a second PHY chip, and the first PHY chip and the second PHY chip are connected through an extended interface.
A data processing method, characterized in that an interface is connected to a medium access control MAC chip, the MAC chip includes a first MAC module and a second MAC module, and the method includes:

generating a first overhead frame, where the first overhead frame is used to indicate the starting position of the code block stream;

Encoding the first data code stream from the first MAC module and the second data code stream from the second MAC module, respectively, to obtain a first data code block and a second data code block;

Based on the first overhead frame and configuration information, the first data code block is inserted into a first time slot, the second data code block is inserted into a second time slot, and a first code block stream is generated, the first code block The code block stream includes a first overhead frame, the first data code block inserted in the first time slot, and the second data code block inserted in the second time slot, and the configuration information is used to indicate Correspondence between MAC modules in the MAC chip and time slots.
A data processing method, characterized in that an interface is connected to a medium access control MAC chip, the MAC chip includes a first MAC module and a second MAC module, and the method includes:

A first code block stream is obtained from the physical layer PHY chip, the first code block stream includes a first overhead frame, a first data code block inserted in a first time slot, and a second data code block inserted in a second time slot ;

determining, according to the first overhead frame, a starting position of a data code block in the first code block stream;

According to the configuration information, the first data code block and the second data code block in the first code block stream are respectively allocated to the first MAC module and the second MAC module, and the configuration information It is used to indicate the corresponding relationship between the MAC module and the time slot in the MAC chip.
A data processing method, characterized in that an interface is connected to a physical layer PHY chip, the PHY chip includes a first PHY module and a second PHY module, and the method includes:

generating a first overhead frame, where the first overhead frame is used to indicate the starting position of the code block stream;

encoding the first data code stream from the first PHY module and the second data code stream from the second PHY module, respectively, to obtain a first data code block and a second data code block;

Based on the first overhead frame and configuration information, the first data code block is inserted into a first time slot, the second data code block is inserted into a second time slot, and a first code block stream is generated, the first code block The code block stream includes a first overhead frame, the first data code block inserted in the first time slot, and the second data code block inserted in the second time slot, and the configuration information is used to indicate The corresponding relationship between the PHY module in the PHY chip and the time slot.
A data processing method, characterized in that an interface is connected to a physical layer PHY chip, the PHY chip includes a first PHY module and a second PHY module, and the method includes:

A first code block stream is obtained from a medium access control MAC chip, the first code block stream includes a first overhead frame, a first data code block inserted in a first time slot, and a second data code inserted in a second time slot Piece;

determining, according to the first overhead frame, a starting position of a data code block in the first code block stream;

According to configuration information, the first data code block and the second data code block in the first code block stream are respectively allocated to the first PHY module and the second PHY module, the configuration information It is used to indicate the corresponding relationship between the PHY module and the time slot in the PHY chip.
The method according to any one of claims 43-46, wherein, in the MAC chip and the PHY chip connected through the interface, the MAC module and the PHY module are in one-to-one correspondence.
The method according to any one of claims 43-47, wherein the first overhead frame includes indication information for characterizing the frame as an overhead frame, and the indication information is one or more of the following information A: Sync header SH field, 0x4B field and 0x5 field,

The value of the SH field is 10.
A data processing device, characterized in that an interface is connected to a medium access control MAC chip, the MAC chip includes a first MAC module and a second MAC module, and the device includes:

a first generating unit, configured to generate a first overhead frame according to the first data code stream from the first MAC module and the second data code stream from the second MAC module, where the first overhead frame is used for Indicate time slots corresponding to the first data stream and the second data stream;

an encoding unit, configured to encode the first data code stream and the second data code stream respectively to obtain a first data code block and a second data code block;

a second generating unit, configured to, based on the first overhead frame, insert the first data code block into a first time slot, insert the second data code block into a second time slot, and generate a first code block stream, The first code block stream includes a first overhead frame, the first data code block inserted in the first time slot, and the second data code block inserted in the second time slot.
A data processing device, characterized in that an interface connects a first physical layer PHY module and a second PHY module, the device comprising:

a first generating unit, configured to generate a first overhead frame according to the first data code stream from the first PHY module and the second data code stream from the second PHY module, where the first overhead frame is used for Indicate time slots corresponding to the first data stream and the second data stream;

an encoding unit, configured to encode the first data code stream and the second data code stream respectively to obtain a first data code block and a second data code block;

a second generating unit, configured to, based on the first overhead frame, insert the first data code block into a first time slot, insert the second data code block into a second time slot, and generate a first code block stream, The first code block stream includes a first overhead frame, the first data code block inserted in the first time slot, and the second data code block inserted in the second time slot.
A data processing device, characterized in that an interface is connected to a medium access control MAC chip, the MAC chip includes a first MAC module and a second MAC module, and the device includes:

a first generating unit, configured to generate a first overhead frame, where the first overhead frame is used to indicate the starting position of the code block stream;

an encoding unit, configured to encode the first data code stream from the first MAC module and the second data code stream from the second MAC module, respectively, to obtain a first data code block and a second data code block;

a second generating unit, configured to insert the first data code block into a first time slot, insert the second data code block into a second time slot, and generate a first code based on the first overhead frame and the configuration information a block stream, the first code block stream comprising a first overhead frame, the first data code block inserted in the first time slot, and the second data code block inserted in the second time slot, The configuration information is used to indicate the correspondence between the MAC module and the time slot in the MAC chip.
A data processing device, characterized in that an interface is connected to a medium access control MAC chip, the MAC chip includes a first MAC module and a second MAC module, and the device includes:

an obtaining unit, configured to obtain a first code block stream from a physical layer PHY chip, where the first code block stream includes a first overhead frame, a first data code block inserted in the first time slot, and a first code block inserted in the second time slot the second data code block;

a determining unit, configured to determine the starting position of the data code block in the first code block stream according to the first overhead frame;

an allocation unit, configured to allocate the first data code block and the second data code block in the first code block stream to the first MAC module and the second MAC module respectively according to configuration information , the configuration information is used to indicate the corresponding relationship between the MAC module and the time slot in the MAC chip.
A data processing device, characterized in that an interface is connected to a physical layer PHY chip, the PHY chip includes a first PHY module and a second PHY module, and the device includes:

a first generating unit, configured to generate a first overhead frame, where the first overhead frame is used to indicate the starting position of the code block stream;

an encoding unit, configured to encode the first data code stream from the first PHY module and the second data code stream from the second PHY module respectively to obtain a first data code block and a second data code block;

a second generating unit, configured to insert the first data code block into a first time slot, insert the second data code block into a second time slot, and generate a first code based on the first overhead frame and the configuration information a block stream, the first code block stream comprising a first overhead frame, the first data code block inserted in the first time slot, and the second data code block inserted in the second time slot, The configuration information is used to indicate the corresponding relationship between the PHY module and the time slot in the PHY chip.
A data processing device, characterized in that an interface is connected to a physical layer PHY chip, the PHY chip includes a first PHY module and a second PHY module, and the device includes:

an obtaining unit, configured to obtain a first code block stream from a medium access control MAC chip, where the first code block stream includes a first overhead frame, a first data code block inserted in the first time slot, and a first data code block inserted in the second time slot the second data code block;

a determining unit, configured to determine the starting position of the data code block in the first code block stream according to the first overhead frame;

an allocation unit, configured to allocate the first data code block and the second data code block in the first code block stream to the first PHY module and the second PHY module respectively according to configuration information , the configuration information is used to indicate the corresponding relationship between the PHY module and the time slot in the PHY chip.
A network device, characterized in that it includes:

A processor in communication with a memory for executing computer readable instructions included in the memory to cause the network device to perform the method of any of claims 33-48.
A computer-readable storage medium, characterized by comprising programs or instructions which, when executed by a processor, implement the method of any one of claims 33-48.
A computer program product, characterized in that it includes a computer program, which implements the method of any one of claims 33-48 when the computer program is executed by a processor.