WO2022036434A2 - Appareil et procédé de numérisation échelonnable - Google Patents

Appareil et procédé de numérisation échelonnable Download PDF

Info

Publication number
WO2022036434A2
WO2022036434A2 PCT/CA2021/000028 CA2021000028W WO2022036434A2 WO 2022036434 A2 WO2022036434 A2 WO 2022036434A2 CA 2021000028 W CA2021000028 W CA 2021000028W WO 2022036434 A2 WO2022036434 A2 WO 2022036434A2
Authority
WO
WIPO (PCT)
Prior art keywords
signal
converters
clock frequency
analogue
conversion apparatus
Prior art date
Application number
PCT/CA2021/000028
Other languages
English (en)
Other versions
WO2022036434A3 (fr
Inventor
Brent Carlson
Original Assignee
National Research Council Of Canada
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Research Council Of Canada filed Critical National Research Council Of Canada
Publication of WO2022036434A2 publication Critical patent/WO2022036434A2/fr
Publication of WO2022036434A3 publication Critical patent/WO2022036434A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H03M1/126—Multi-rate systems, i.e. adaptive to different fixed sampling rates
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel

Definitions

  • the disclosure relates to an apparatus and method for data conversion between the continuous time domain and the discrete time domain.
  • the method and apparatus relate to scalable digitization of an analogue input as it relates to electrical signals.
  • the present invention attempts to solve the problem associated with existing technologies in terms of providing high performance conversion between analogue and digital signals using digitizer systems or architectures that employ Analogue-to-Digital converters (ADCs) which may also be referred to as converters or digitizers.
  • ADCs Analogue-to-Digital converters
  • Analogue- to-digital converters are key devices transforming signal processing from the continuous time domain to the discrete time domain.
  • ADCs Analogue-to-Digital Converters
  • Flash converters produce the best results in terms of speed or efficiency but consume the most power. Flash converters can perform an entire conversion in a single clock cycle. Thus, an 8-bit conversion for an 8 bit (B) resolution can be completed in one clock cycle.
  • a Flash converter requires a huge number of comparators compared to other Analog-to-Digital converters, especially as the precision or resolution increases.
  • Some Flash converters require 2 n - 1 comparators for an n-bit conversion. The size, power consumption, and cost of all those comparators makes flash converters generally impractical for precisions much greater than 8 bits (255 comparators). Thus, Flash converters are limited by their high-power consumption and size with each increasing number of bits (B) of resolution.
  • SAR d digitizers are different from flash converters as they perform only one conversion per clock cycle as compared to flash converters that perform the conversion in one clock cycle. Thus, an 8-bit conversion will take at least 8-clock cycles to complete. Thus, with every increase in number of bits (B) to improve performance, the SAR digitizer will be slower to complete the conversion as compared to a Flash converter requiring at least another additional clock cycle to complete.
  • SAR Successive Approximation Register
  • an individual Analogue-to-Digital Converter (ADC) or digitizer of a particular architecture for example a Flash Converter or a Successive Approximation Register (SAR) Converter (as described in prior art literature), with a resolution of B bits can encode an analogue input to 2 b different levels of amplitude fidelity.
  • ADC Analogue-to-Digital Converter
  • SAR Successive Approximation Register
  • each additional B bit requires 2 b more high-speed time-synchronized circuit elements in order to meet the precise timing synchronization requirements, where each circuit element requires copies of the analogue signal (that is to be digitized) having sufficiently high fidelity delivered to it.
  • the analogue signal is ideally converted to 2 B levels of amplitude fidelity on each clock cycle.
  • ADC Analog-to-Digital Converter
  • clock jitter affects the effective number of bits (ENOBs) of the ADC, where ENOB ⁇ B, and therefore only 2 EN0B levels can actually be obtained. This is because clock jitter has the equivalent effect of distorting the analogue signal.
  • clock jitter must be ⁇ 100 fsec (femtoseconds, i.e. 10' 15 seconds) or less.
  • clock jitter For B > 8 and even higher speeds, clock jitter must be sub-50 fsec and ultimately at a level of precision that cannot be achieved. Additionally, if the clock jitter is non-random in nature, the output digitized signal will contain low-level “ghost” spectral copies of the input analogue signal, causing spectral confusion and further limiting amplitude fidelity. Regarding prior art analogue signal fidelity fed into each ADC circuit element, any differential distortion has the effect of distorting the analogue signal and therefore limiting the ADC’s ENOBs. As well, for time- interleaved ADC architectures such as SAR, this has the same effect as non-random clock jitter, i.e.
  • the output digitized signal will contain low-level “ghost” spectral copies of the input analogue signal, causing spectral confusion and further limiting amplitude fidelity.
  • present state-of-the-art systems and technology approaches for digitizing electrical signals are limited to increasing number of bits in the digitizers used by the digitizer system whereby they are additionally limited by the circuity that is required to implement digitizer architecture to support increasing number of bits. This limitation of present technology thus limits the number of bits (B) that can be implemented which ultimately leads to a “performance wall” that limits digitizer speed and dynamic range in digitizing electrical signals, and limits the number of circuit elements that can be used.
  • any high-performance ADC solution is normally limited to a single integrated circuit (“chip”).
  • chips integrated circuit
  • a performance limit is reached in terms of speed and number of bits (B) for a given technology node because of the extremely precise timing and signal integrity requirements of the input stages of an ADC and the fact that for every 1 -bit increase in ENOB, these requirements get stricter by a factor of 2 or more.
  • the inventors of the present invention have invented a novel apparatus and method for providing scalable digitization that solves the problems associated with prior art digitizer systems for digitizing electrical signals, that comprise one or more analogue- to-digital converters, requiring high time-synchronization and analogue signal integrity to each digitizer circuit element.
  • the solutions proposed by the present invention have been disclosed with reference to analog to digital converters using digitizers for digitizing electrical signals.
  • the present invention provides a solution to the problem of providing high performance conversion between an analog signal and a digital signal.
  • the inventors of the present invention have invented a novel apparatus and method that provides scalable digitization of electrical signals where the scaling is independent of the one or more Analog-to-Digital converters (ADCs) or digitizers that are being implemented and/or the specific architecture of these Analog-to-Digital converters (ADCs) in a given digitization system for digitizing electrical signals.
  • ADCs Analog-to-Digital converters
  • ADCs Analog-to-Digital converters
  • the scaling does not need to rely on increasing the B bits of resolution of one or more highly time-synchronized analogue-to- digital converter to improve performance.
  • the solution to scalable digitization as proposed by the present invention is to provide a scaling system for a digitizer that is independent of a given digitizer architecture in terms of the specific A-D converters or ADCs that it utilizes. Additionally, the solution proposed by the present inventors obviates the need for high speed timed synchronization of A-D converters or one or more components thereof in digitizers that implement multi data converter arrays. As such, the digitizer solution that is proposed attempts to relax and/or eliminate clock jitter requirements for high speed digitizers. The present invention attempts to eliminate the need for precise synchronisation of individual clocks for respective digitizers or converters in a data converter array or a digitizer system.
  • proposed embodiments of the present invention provide an apparatus and method for scalable incoherent digitization of electrical signals and provide a scalable architecture for digitizers that allows one or more ADCs in the digitizer to use independent clocks for digitizing electrical signals that need not be synchronized in time.
  • such embodiments of the present invention need not rely on increasing number of bits (B) to improve performance in terms of digitized signal amplitude fidelity, i.e. ENOBs and therefore number of levels 2 EN0B .
  • B bits
  • some embodiments of the present invention may not increase the speed of any individual independent ADC, the speed of the collection of independent ADCs is improved by requiring that each independent ADC in the collection have fewer B bits, and therefore 2 B independent, highly time-synchronized digitizer circuit elements.
  • the ADC clock jitter requirements for each independent ADC of the collection need only be sufficient for the purposes of obtaining the required ENOBs of each independent ADC even though more ENOBs is produced by the collection using the present invention.
  • Carlson points out that each antenna/receiver’s digitizer can operate with its own independent local oscillator (LO), if its frequency can be measured sufficiently accurately, to be able to digitally re-sample the data to a common frequency before correlation and/or beamforming, and additionally provides some notions on how to measure each antenna’s LO over a digital fiber-optic connection.
  • Carlson additionally points out that the benefits as documented in prior art publication noted below by Carlson B.et al. [URSI/GASS paper] can be obtained with this method as provided. Specifically, publication by Carlson B. et al. is provided as “Carlson B., Gunaratne T., Signal processing aspects of the sample clock frequency offset scheme for the SKA1 mid telescope array, 32 nd URSI GASS, Montreal, 19-26 August 2017”.
  • Carlson B. et al. additionally investigate the conclusions of the following publication: “Carlson B., Sample Clock Frequency Offset (SCFO) Resolution Team 3 (RT-3) investigation, SKA-CSP Memo-0021 (arXiv:1812.06972)” in more detail, in particular de-correlation of low-level spectral ghosts.
  • Carlson B. et al. provide additional information relating to investigation of quantization noise and spurs from digitization adding, to some extent, incoherently, whereas the signal of interest adds coherently. Additional information can be found in the following publication “Carlson B., Gunaratne T., Signal processing aspects of the sample clock frequency offset scheme for the SKA 1 mid telescope array, 32 nd URSI GASS, Montreal, 19-26 August 2017”.
  • proposed embodiments of the present invention provide an apparatus and method for scalable incoherent digitization of electrical signals and provide a scalable architecture for digitizers that allows one or more ADCs in the digitizer to use independent clocks for digitizing electrical signals.
  • proposed embodiments of the present invention provide a new approach to scaling digitization by providing an apparatus and method for scalable incoherent digitization (SID), wherein the intractable problem of extreme timing synchronization across many closely integrated analogue elements is transformed into a virtually infinitely scalable, parallelized digital signal processing problem, combined with simpler distributed analogue elements, decoupled from each other.
  • SID scalable incoherent digitization
  • Such digital processing may be integrated onto a chip, a board, or across a system since each parallel path is independently timed, with final timing convergence of all paths occurring at one point, all in the digital domain. This opens up a new decision space when determining where, or even if, heterodyne down-conversion/mixing and filtering is required before digitization for virtually any system.
  • a data conversion apparatus for transforming a signal between an analogue signal and a digital representation of the signal.
  • a data conversion apparatus or digitizer architecture for converting an electrical signal from an analogue signal to a digital signal (or in other words for converting an analogue electrical signal to a digital electrical signal), the data conversion apparatus or digitizer architecture comprising: a data converter array comprising one or more converters each for receiving (a copy of) an analogue input signal; each of said one or more converters being clocked at a different respective clock frequency; and a re-sampler for re-sampling an output of each of said one or more converters clocked to a common clock frequency to produce a re-sampled output; each of said re-sampled outputs being correlated or compared with a reference digitized signal to provide the information required to align the re-sampled outputs in time; and where
  • each of said one or more converters that are clocked at the different respective clock frequency each have an independent clock that operates at the respective different clock frequency.
  • each of said one or more converters are clocked at the different respective clock frequency by an independent clock that operates at the respective different clock frequency.
  • Each of these independent clocks may derive from a common clock reference frequency, or may be completely independent, for example sourcing from independent clock sources such as crystal oscillators.
  • each of said one or more re-sampled outputs are clocked to the common clock frequency by an independent clock that operates at the common clock frequency.
  • each of said one or more re-sampled outputs are clocked to the common clock frequency by a clock that operates the respective clock frequency of one of the one or more converters.
  • the common clock frequency to which the output of each of said one or more converters is re-sampled to is the respective clock frequency of one of the one or more converters.
  • this common clock frequency may be the clock frequency of one of the converters, or may be an independent clock frequency not used by any of the converters.
  • the digital signal of interest adds coherently from the summation of the re-sampled outputs whereas a quantization noise from the converters and re-sampled outputs adds incoherently.
  • a source of the analogue signal may include, audio, video, communication, radar, or any other continuous-time signal that is to be digitized.
  • a data conversion apparatus for converting an electrical signal between an analogue signal and a digital signal, the data conversion apparatus comprising: a data converter array comprising one or more converters each for receiving a copy of an electrical input signal; each of said one or more converters being clocked at a different respective clock frequency; a re-sampler for re-sampling an output of each of said one or more converters to a common clock frequency; and each of said re-sampled outputs being added to produce a digital signal of interest.
  • the electrical signal is an analogue electrical signal and the data conversion apparatus comprises a digitizer for digitizing the electrical signal; and the one or more converters of the data converter array comprise an analog ue-to- digital converter; wherein the signal of interest is an analogue signal of interest that is converted into a digital signal of interest.
  • FIG. 1 is an illustration of a simplified block diagram of a digitizer architecture using scalable incoherent digitization for digitizing an electrical signal, in accordance with an embodiment of the present invention
  • Fig. 2A is a graphical illustration showing quantization noise vs. quantization level for various few-bit (B) ideal ADCs operating in Nyquist zone-1 for an apparatus implementing scalable incoherent digitization of a white noise analogue electrical signal, in accordance with an embodiment of the present invention
  • Fig. 2B is a graphical illustration showing quantization noise vs. quantization level for various few-bit (B) ideal ADCs operating in Nyquist zone-2 for an apparatus implementing scalable incoherent digitization of a white noise analogue electrical signal, in accordance with an embodiment of the present invention
  • FIG. 4 is an illustration of a digitizer architecture using scalable incoherent digitization for digitizing an electrical signal, in accordance with an alternate embodiment of the present invention.
  • a method and apparatus are disclosed for providing scalable digitization.
  • the data conversion apparatus 1000 converts the electrical signal from an analogue signal to a digital signal and comprises a data converter array 500 comprising one or more converters 200.
  • the data conversion apparatus comprises a digitizer for digitizing an electrical signal, where the one or more converters 200 of the data converter array 500 are comprised of an analogue-to-digital converter (ADC) or a digitizer 220.
  • ADC analogue-to-digital converter
  • the data conversion apparatus 1000 comprises a digitizer architecture or system 1010 that utilizes scalable incoherent digitization where the one or more converters 200 comprise analogue-to-digital converters or digitizers 220.
  • the analogue signal to be digitized is fed, through an arbitrary path maintaining sufficient signal fidelity, into each analogue input of N independent analogue-to-digital converters or digitizers 220.
  • a copy of an electrical analogue input signal is received by one or more converters 220 of the data converter array 500, where that copy of the analogue signal is of sufficient quality.
  • Each of said one or more converters 220 are clocked at a different respective clock frequency.
  • each of the one or more converters 220 that are clocked at the different respective clock frequency each have an independent clock 420 that operates at the respective different clock frequency.
  • each of said one or more converters 220 are clocked at the different respective clock frequency by an independent clock 420 that operates at the respective different clock frequency.
  • the output of each independent N digitizer 220 is provided in terms of the effective number of bits (ENOBs),
  • ENOBs effective number of bits
  • the digitizer system 1010 in accordance with embodiments of the present invention also comprises a ReSampler system or array 300.
  • the output of each of the digitizers 220 noted above (which may be N independent digitizers 220) is then digitally re-sampled by a ReSampler system 300 to a common clock frequency.
  • Each output of these N independent digitizers is then directed to an individual ReSampler 320 of the ReSampler system 300 where it is resampled to a common clock frequency prior to summation to produce a digitized output signal.
  • each of the ReSamplers 320 re-sample a respective output of each of said one or more converters 220 to a common clock frequency where each of these re-sampled outputs is then added together to produce the output digital signal of interest.
  • the ReSampler re-samples these outputs to a common clock frequency which are summed to produce an output of B + b(N) ENOBs to produce the digitized output.
  • the outputs of the individual ReSamplers 320 of the ReSampler array 300 are synchronized to each other using a common clock 400 that operates at the common clock frequency.
  • the ReSampler 320 re-samples an output of each of said one or more converters 220 that is clocked to the common clock frequency 400 to produce a re- sampled output.
  • Each of these re-sampled outputs is correlated with a reference ADC output to align the re-sampled outputs in time; and each of said re-sampled outputs being added to produce the final output digital signal of interest.
  • each of said one or more re-sampled outputs are clocked to the common clock frequency by a ReSampler clock 520 that operates the respective clock frequency of one of the one or more converters 220, such as clock ADC-1 520.
  • the common clock frequency to which the output of each of said one or more converters 220 is re-sampled to is the respective clock frequency of one of the one or more converters 220.
  • the ReSampler clock 520 having the common clock frequency could be independent of all ADC clocks before summation to produce an output of B + b(N) ENOBs.
  • each of the one or more re-sampled outputs are clocked to the common clock frequency by a re-sample clock 520 that is an independent clock that operates at the common clock frequency.
  • each digitizer output (sequence) is re-sampled to a common clock frequency (which is the incoherent clocking method)
  • the digitized sequences are sampled at the same common clock frequency but are not lined up in time so cannot yet be added to form a coherent sum.
  • the re-sampled output (or sequences) of each of the digitizers 220 is correlated with a reference sequence, which in one example, may be any one of the digitizer’s re-sampled sequences.
  • the correlation yields delay and phase residuals that are applied to the re-sampled sequences (using the already implemented re-sampler circuitry, or independent circuitry) to align them in time, phase, and if desired, amplitude.
  • the digitized sequences are simply added together to form a coherent sum.
  • the signal of interest in the digitized signal i.e. the analogue input signal
  • the digitization noise (quantization noise) in the digitized signal adds incoherently, thereby yielding an improvement in signal-to-noise ratio of the signal of interest.
  • the signal of interest component of the digitized signal adds coherently in the summation of the resampled outputs whereas the quantization noise component of the digitized signal adds incoherently.
  • embodiments of the present invention recognize the key hypothesis of a scalable incoherent digitizer (SID) (now proven with modelling, i.e. Fig. 2 and Fig. 3) and that is that even for an identical signal (having arbitrary narrowband and/or broadband components) into each digitizer, each digitizer clocked at a sufficiently different SID (SID) (now proven with modelling, i.e. Fig. 2 and Fig. 3) and that is that even for an identical signal (having arbitrary narrowband and/or broadband components) into each digitizer, each digitizer clocked at a sufficiently different
  • Correlation is an essential component of SID as feedback into the resampler to ensure coherent summation of the signal of interest and, as well, allowing the analogue signal path into each digitizer to be arbitrarily
  • the correlation operation yields the total delay and phase residuals (as well as fixed and/or temporal amplitude vs0 frequency variations) between the digitized re-sampled outputs and the reference sequence, it means that the input analogue signal copy split and/or amplified and fed to each digitizer may undergo an a priori indeterminate temporal and frequency dependent transfer function on its way to each digitizer’s input, provided that such transfer functions don’t unduly degrade the signal.
  • each digitizer 220 operates with its own independent clock 420.
  • each digitizer operates independently, which completely eliminates the need for high-precision time synchronization of the independent ADCs with each other as well as digitizer clocks and analogue signals into them, which is a key limiting factor increasing ENOBs and speed in current digitizers.
  • digitizers 220 there may be virtually no limitation in the number of digitizers 220 that may be employed to improve the net digitized signal fidelity, making it virtually infinitely scalable.
  • a scalable incoherent digitization (SID) architecture 1010 is illustrated in Fig. 1 and Fig. 4, that results in the highest digitization performance possible for a given technology node, by operating any number of independent ADCs, at fewer effective number of bits (ENOBs) each than ultimately required, to increase the ENOBs of the collection. Since fewer-bit digitizers have fewer circuit elements with analogue cross-coupling effects and timing that must be coordinated, they run the fastest for any technology node.
  • “Fewer” is a free parameter, thus SID may be applied to digitization problems across the spectrum of bandwidth and ENOBs using custom or commercial off-the-shelf (COTS) devices operating as fast as technology and techniques allow. Such processing may be integrated on a single chip, across a circuit board, or across a system of virtually any size with no loss of performance. And, with the availability of high-performance 4-level pulse amplitude modulation (PAM4) serializer/de-serializer (SERDES) transceivers in field programmable gate arrays (FPGAs), it opens up the possibility that ADC performance, for all but the most demanding applications, could track FPGA PAM4 performance, thus enabling access to ultra-wideband digitization to any FPGA user.
  • PAM4 4-level pulse amplitude modulation
  • SERDES serializer/de-serializer
  • scalable incoherent digitization using a scalable incoherent digitization (SID) architecture 1010, as outlined in Fig. 1 and Fig. 4, the fundamental enabling factor is that quantization noise and spurs from digitization add, to some extent, incoherently, whereas the signal of interest adds coherently.
  • incoherent clocking in digitizer architectures such as digitizer architecture 1010 as outlined herein above, can be employed to use independent ADC clocks across any sized system, without the need for central timing distribution.
  • scalable incoherent digitization (SID) may be truly scalable to virtually any extent.
  • Fig. 2A and Fig. 2B a graphical illustration showing quantization noise vs. quantization level for various few-bit B (i.e. few levels) resolutions is shown for an apparatus using a digitizer architecture 1010 implementing scalable incoherent digitization (SID) of an electrical signal, in accordance with embodiment of the present invention in a Nyquist zone 600.
  • Fig. 2A and Fig. 2B show scalable incoherent digitization (SID) modelling results for N ideal ADCs with very few levels for Nyquist zone-1 620 and Nyquist zone-2 640 respectively, with a white noise input, as shown.
  • SID scalable incoherent digitization
  • added quantization noise is the key metric, but such can be converted to ENOBs if required by those skilled in the art of analogue-to-digital conversion signal processing.
  • Figs. 2A and 2B illustrate a model of SID digitization and signal processing in MatLab, to include the use of any number of digitizers 220 of a range of ENOBs of interest, each operating at any arbitrary frequency over an arbitrary span of frequencies, in each of Nyquist zone-1 620 and zone-2 640, with analogue inputs of varying characteristics.
  • Fig. 2A and Fig. 2B show the SID b(N) investigation via modelling and show that: resulting added quantization noise (and therefore sensitivity loss) for zone-1 620 and zone-2 respectively for ideal ADCs 220 with very few levels, of interest for the highest- speed operation where the signal of interest is typically broad-band (i.e. approximately white noise) in nature.
  • digitizer 220 frequencies are at quasi-randomly fixed values over a range of -0.025% of the digitizer frequency and zone-1 620 results are not as good as zone-2 640 results.
  • zone-2 all digitizer 220 quantization noise is clearly dependent on the digitizer 220 frequency and thus the above equation for b(N) very nearly applies.
  • zone-2-like results can be obtained in zone-1 620 if the ReSampler 300 consists of a coarse filter bank followed by per-coarse-channel resampling, in which case each coarse channel’s down-sampled rate is dependent on the digitizer clock, as in “Gunaratne T., Carlson B., Comoreto G., Novel RFI Mitigation Methods in the Square Kilometre Array 1 Mid Correlator Beamformer, Journal of Astronomical Instrumentation, Vol. 08, No. 01, 1940011 (2019).”.
  • Fig. 3 is a graphical illustration 700 showing spurious free dynamic range vs. quantization level for a given resolution, for an apparatus implementing scalable incoherent digitization for digitizing an electrical signal, in accordance with an embodiment of the present invention.
  • the ReSampler has 64-taps, with 512 steps of interpolation delay across 1 sample.
  • the number of ADCs, N which may be applied to achieve higher collective ENOBs and SFDR is scalable, using digitizer architecture 1010 in line with embodiments of the present invention, although in some such embodiments, at some point more than one board and even one rack may be required to achieve performance goals.
  • incoherent clocking methods discussed with refence to radio signals in: “Carlson B.R., Incoherent clocking in coherent radio interferometers, Electronics Letters, 12 th July 2018, Vol. 54, No. 14, pp. 909-911” may be applied with one final measurement and summation step producing the collective output. This may provide more options for defining the digitization point in any analogue-to-digital signal chain for a given application.
  • any digitizer output content that is digitizer clock frequency and/or phase dependent doesn’t add coherently.
  • any appropriate ADC device may be used (for each of N ADCs) and may have its own calibration issues that must be dealt with largely independently of SID noting that individual ADC output artefacts that are a function of its clock frequency, don’t add coherently in SID. For example, for both Nyquist zones, low-level spectral “ghost” copies due to time-interleaving and/or non-random clock jitter don’t add coherently and are therefore suppressed in the SID output. This fact could ease ADC core self-calibration methods used to suppress these.
  • correlation may require input of some broadband signal component into each ADC to determine corrective delay and phase residuals.
  • Such content may be intrinsic in the signal to be digitized; if not, then an additional broadband signal injection at the analogue signal input, functionally as shown, is required, noting that the broadband signal level can be small as long as enough cross-correlation signal-to-noise is obtained to ensure sufficient coherence as discussed previously.
  • this broadband signal source could be completely independently generated (as shown in the figure), or it could be digitally generated in the common clock domain, converted to analogue with a D-to-A converter (DAC), and then injected into the input.
  • DAC D-to-A converter
  • the injected broadband signal could be removed from the “collective SID output” so as not to degrade the result.
  • some embodiments of the present invention as outlined herein above, provide a potentially revolutionary method of scaling digitization by providing scalable incoherent digitization (SID), where the wall of performance for any ADC technology node can be overcome by employing any number of independent ADCs to increase the ENOBs of the whole.
  • SID scalable incoherent digitization
  • FPGA PAM4 SERDES receivers may be used as 2-bit ADCs, thus allowing FPGA users access to very high performance ADCs, rather than through expensive and hard to obtain custom solutions.
  • a data conversion apparatus or digitizer architecture for transforming an electrical signal between an analogue signal and a digital signal
  • the data conversion apparatus or digitizer architecture comprising: a data converter array comprising one or more converters each for receiving a copy of an analogue input signal; each of said one or more converters being clocked at a different respective clock frequency; and a resampler for re-sampling an output of each of said one or more converters to a common clock frequency; wherein each of said re-sampled outputs are added or summed to produce the digital signal of interest.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

L'invention concerne un appareil et un procédé pour un appareil de conversion de données pour convertir un signal électrique entre un signal analogique et un signal numérique d'intérêt. L'appareil de conversion de données comprend un réseau de convertisseurs de données comprenant un ou plusieurs convertisseurs destinés chacun à recevoir une copie d'un signal d'entrée électrique analogique. Chacun du ou des convertisseurs est synchronisé à une fréquence d'horloge respective différente. L'appareil de conversion de données comprend en outre un rééchantillonneur pour rééchantillonner la sortie de chacun desdits un ou plusieurs convertisseurs à une fréquence d'horloge commune pour produire une sortie rééchantillonnée. Chacune des sorties rééchantillonnées est corrélée ou comparée à une séquence de référence pour fournir les informations pour aligner les sorties rééchantillonnées dans le temps dans le rééchantillonneur; et chacune des sorties rééchantillonnées est ajoutée pour produire le signal numérique d'intérêt.
PCT/CA2021/000028 2020-04-06 2021-04-06 Appareil et procédé de numérisation échelonnable WO2022036434A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202063005623P 2020-04-06 2020-04-06
US63/005,623 2020-04-06

Publications (2)

Publication Number Publication Date
WO2022036434A2 true WO2022036434A2 (fr) 2022-02-24
WO2022036434A3 WO2022036434A3 (fr) 2022-06-02

Family

ID=80322314

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA2021/000028 WO2022036434A2 (fr) 2020-04-06 2021-04-06 Appareil et procédé de numérisation échelonnable

Country Status (1)

Country Link
WO (1) WO2022036434A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024121776A1 (fr) * 2022-12-07 2024-06-13 National Research Council Of Canada Découpeur en canaux de rééchantillonnage combiné à large bande

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010055354A1 (en) * 2000-03-03 2001-12-27 Danny Fung Method & apparatus for data rate synchronization
DE60115246T2 (de) * 2001-09-28 2006-06-01 Freescale Semiconductor, Inc., Austin Analog-Digital-Wandler mit vershiedenen Übertragungsraten
KR101253185B1 (ko) * 2007-03-26 2013-04-10 엘지전자 주식회사 디지털 방송 시스템 및 데이터 처리 방법
JP5619883B2 (ja) * 2009-06-26 2014-11-05 シントロピーシステムズSyntropy Systems サンプリング／量子化変換器
US9793910B1 (en) * 2016-09-12 2017-10-17 Analog Devices, Inc. Time-interleaved ADCs with programmable phases
WO2020150670A1 (fr) * 2019-01-18 2020-07-23 Precision Receivers Incorporated Réduction de parasites pour convertisseurs analogique-numérique

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024121776A1 (fr) * 2022-12-07 2024-06-13 National Research Council Of Canada Découpeur en canaux de rééchantillonnage combiné à large bande

Also Published As

Publication number Publication date
WO2022036434A3 (fr) 2022-06-02

Similar Documents

Publication Publication Date Title
Razavi Problem of timing mismatch in interleaved ADCs
Ragheb et al. Expression of Concern: Implementation models for analog-to-information conversion via random sampling
Camarero et al. Mixed-signal clock-skew calibration technique for time-interleaved ADCs
US10312927B1 (en) Calibration for time-interleaved analog-to-digital converters and signal generators therefor
US9685970B1 (en) Analog-to-digital converting system and converting method
WO2011038189A1 (fr) Système et procédé pour la conversion analogique-numérique basée sur la technique de filtrage imbriqué à longueur d'onde sélective (swift)
Pereira et al. An FFT-based method to evaluate and compensate gain and offset errors of interleaved ADC systems
Haftbaradaran et al. A background sample-time error calibration technique using random data for wide-band high-resolution time-interleaved ADCs
CN107223311B (zh) 用于增加矢量信号分析仪中瞬时带宽的频谱拼接方法
Niu et al. An efficient spur-aliasing-free spectral calibration technique in time-interleaved ADCs
Gao et al. An adaptive calibration technique of timing skew mismatch in time-interleaved analog-to-digital converters
Guangshan et al. Research progress of time-interleaved analog-to-digital converters
WO2022036434A2 (fr) Appareil et procédé de numérisation échelonnable
Tzou et al. Low-cost wideband periodic signal reconstruction using incoherent undersampling and back-end cost optimization
Guo et al. A single SAR ADC converting multi-channel sparse signals
Jiang et al. Mismatch error correction for time interleaved analog-to-digital converter over a wide frequency range
Tzou et al. Low cost sparse multiband signal characterization using asynchronous multi-rate sampling: Algorithms and hardware
Huang et al. General analysis of resolution enhancement on time-synchronized sampling and its multi-resolution solution in 20GSPS acquisition system
Harpe et al. Analog calibration of channel mismatches in time‐interleaved ADCs
Haftbaradaran et al. A sample-time error compensation technique for time-interleaved ADC systems
Zhao et al. An arbitrary waveform synthesis structure with high sampling rate and low spurious
Bhatta et al. Time domain characterization and test of high speed signals using incoherent sub-sampling
KR102123270B1 (ko) 디지털 후면 교정을 가지는 시간 인터리브 파이프라인 아날로그 디지털 변환 장치 및 그 방법
Gande et al. Blind background calibration of harmonic distortion based on selective sampling
Villa-Angulo et al. Bit-resolution improvement of an optically sampled time-interleaved analog-to-digital converter based on data averaging

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21857069

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21857069

Country of ref document: EP

Kind code of ref document: A2