WO2022027619A1

WO2022027619A1 - Multi-level power convertor and method for multi-level power convertor

Info

Publication number: WO2022027619A1
Application number: PCT/CN2020/107893
Authority: WO
Inventors: Fu Yang; Yaming Shi; Jing Zhang
Original assignee: Abb Schweiz Ag
Priority date: 2020-08-07
Filing date: 2020-08-07
Publication date: 2022-02-10

Abstract

A multi-level power convertor (100) and a method for a multi-level power convertor (100) are disclosed. The multi-level power convertor (100) comprises: a DC port; an AC port; four power converting units (5, 6, 7, 8) each coupled to the DC port and each comprising an AC terminal (51, 61, 71, 81) adapted to provide a predefined number of voltage levels; first, second and third coupling inductors (1, 2, 3) each comprising first and second windings (11, 21, 31; 12, 22, 32) with the same number of turns, the first, second and third coupling inductors (1, 2, 3) each comprising a first end (111, 211, 311), a second end (112, 212, 312), a third end (121, 221, 321) and a fourth end (122, 222, 322); and an inductive filtering unit (4) arranged between the AC port and the second and fourth ends (312, 322) of the third coupling inductor (3).

Description

[Title established by the ISA under Rule 37.2] MULTI-LEVEL POWER CONVERTOR AND METHOD FOR MULTI-LEVEL POWER CONVERTOR

FIELD

Embodiments of present disclosure generally relate to the field of power convertors, and more particularly, to a multi-level power convertor and a method for a multi-level power convertor.

BACKGROUND

Currently, multi-level power converters are widely used in various fields, which can effectively decrease the switching frequency and improve the output waveform quality.

Fig. 1 illustrates a schematic circuit diagram of a conventional multi-level power convertor 100. As shown in Fig. 1, the multi-level power convertor 100 includes a DC port and an AC port. The DC port includes DC terminals DC+ and DC-. Capacitors C1 and C2 are connected in series between the DC terminals DC+ and DC-. Switching semiconductor devices S1, S2, S3, and S4 are connected in series between the DC terminals DC+ and DC-. The switching semiconductor devices S1, S2, S3, and S4 are line frequency switches. A node N1 between the capacitors C1 and C2 is connected to a node N2 between the switching semiconductor devices S2 and S3. A first branch includes switching semiconductor devices S13, S14, S15, and S16 connected in series between a node N3 and an inductor L. A second branch includes switching semiconductor devices S17, S18, S19, and S20 connected in series between a node N4 and the inductor L. The switching semiconductor devices S13, S14, S15, S16, S17, S18, S19, and S20 are high frequency switches. Capacitors C4, C5, and C6 are connected between the first and second branches respectively. The switching semiconductor devices S1, S2, S3, S4, S13, S14, S15, S16, S17, S18, S19, and S20 may be switched on and off under control of respective driving signals. With the above arrangement, the multi-level power convertor 100 may output nine voltage levels at the AC port.

When the multi-level power convertor 100 operates, the capacitors C4, C5, and C6 may be connected in series via respective ones of the switching semiconductor devices S13, S14, S15, S16, S17, S18, S19, and S20. In a steady state of the multi-level power convertor 100, the voltages across the capacitors C4, C5, and C6 are stable. However, in a dynamic state of the multi-level power convertor 100, the voltages across the capacitors C4, C5, and C6 may be out of control. For example, the voltage of the capacitor C4, C5, or C6 may become relatively high. In this event, the corresponding switching semiconductor devices S13, S14, S15, S16, S17, S18, S19, or S20 may be susceptible to be damaged. Hence, the performance and reliability of the multi-level power convertor 100 would be adversely affected.

Thus, there is need for a solution for improving the performance and reliability of the multi-level power convertor.

SUMMARY

In view of the foregoing problems, various example embodiments of the present disclosure provide a multi-level power convertor and a method for a multi-level power convertor so as to improve the performance and reliability of the multi-level power convertor.

In a first aspect of the present disclosure, example embodiments of the present disclosure provide a multi-level power convertor. The multi-level power convertor comprises a DC port; an AC port; first, second, third and fourth power converting units each coupled to the DC port and each comprising an AC terminal adapted to provide a predefined number of voltage levels; first, second and third coupling inductors each comprising first and second windings with the same number of turns, each of the first windings comprising a first end and a second end, and each of the second windings comprising a third end and a fourth end, wherein the first end of the first coupling inductor is coupled to the AC terminal of the first power converting unit, the third end of the first coupling inductor is coupled to the AC terminal of the second power converting unit, the first end of the second coupling inductor is coupled to the AC terminal of the third power converting unit, and the third end of the second coupling inductor is coupled to the AC terminal of the fourth power converting unit, wherein the second and fourth ends of the first coupling inductor are coupled to a first common node, and the second and fourth ends of the second coupling inductor are coupled to a second common node, and wherein the first end of the third coupling inductor is coupled to the first common node, and the third end of the third coupling inductor is coupled to the second common node; and an inductive filtering unit arranged between the AC port and the second and fourth ends of the third coupling inductor.

In some embodiments, the second and fourth ends of the third coupling inductor are coupled to a third common node, and the inductive filtering unit comprises an inductor arranged between the third common node and the AC port.

In some embodiments, the inductive filtering unit comprises: a first inductor arranged between the second end of the third coupling inductor and the AC port; and a second inductor arranged between the fourth end of the third coupling inductor and the AC port.

In some embodiments, the inductive filtering unit comprises an additional coupling inductor comprising third and fourth windings, wherein the third winding is arranged between the second end of the third coupling inductor and the AC port, and wherein the fourth winding is arranged between the fourth end of the third coupling inductor and the AC port.

In some embodiments, each of the AC terminals provides three voltage levels, each of the first and second common nodes provides five voltage levels, and the AC port provides nine voltage levels.

In some embodiments, each of the AC terminals provides five voltage levels, each of the first and second common nodes provides nine voltage levels, and the AC port provides seventeen voltage levels.

In some embodiments, the DC port comprises first and second DC terminals, and each of the first, second, third and fourth power converting units comprises: first and second capacitors coupled in series between the first and second DC terminals; first, second, third, and fourth switching semiconductor devices coupled in series between the first and second DC terminals, wherein a first node between the first and second capacitors is coupled to a second node between the second and third switching semiconductor devices; a fifth switching semiconductor device coupled between a third node and the respective AC terminal, the third node being between the first and second switching semiconductor devices; and a sixth switching semiconductor device coupled between a fourth node and the respective AC terminal, the fourth node being between the third and fourth switching semiconductor devices.

In some embodiments, the first and second capacitors and the first, second, third, and fourth switching semiconductor devices are shared by the first, second, third and fourth power converting units.

In some embodiments, the first and second capacitors and the first, second, third, and fourth switching semiconductor devices are provided individually for each of the first, second, third and fourth power converting units.

In some embodiments, each of the first, second, third and fourth power converting units further comprises: a seventh switching semiconductor device coupled between the fifth switching semiconductor device and the respective AC terminal; an eighth switching semiconductor device coupled between the sixth switching semiconductor device and the respective AC terminal; and a third capacitor arranged between a fifth node and a sixth node, the fifth node being between the fifth switching semiconductor device and the seventh switching semiconductor device, and the sixth node being between the sixth switching semiconductor device and the eighth switching semiconductor device.

In some embodiments, the voltage levels provided by the second power converting unit are phase-shifted by 90 degree with respect to the voltage levels provided by the first power converting unit, the voltage levels provided by the fourth power converting unit are phase-shifted by 90 degree with respect to the voltage levels provided by the third power converting unit, and the voltage levels provided by the third power converting unit are phase-shifted by 180 degree with respect to the voltage levels provided by the first power converting unit.

In some embodiments, the voltage levels provided by the second power converting unit are phase-shifted by 180 degree with respect to the voltage levels provided by the first power converting unit, the voltage levels provided by the fourth power converting unit are phase-shifted by 180 degree with respect to the voltage levels provided by the third power converting unit, and the voltage levels provided by the third power converting unit are phase-shifted by 90 degree with respect to the voltage levels provided by the first power converting unit.

In some embodiments, the DC port comprises first and second DC terminals, and each of the first, second, third and fourth power converting units comprises: first and second capacitors coupled in series between the first and second DC terminals; ninth and tenth switching semiconductor devices coupled in series between a first node and the respective AC terminal, the first node being between the first and second capacitors; and eleventh and twelfth switching semiconductor devices coupled in series between the first and second DC terminals, wherein a seventh node between the eleventh and twelfth switching semiconductor devices is coupled to the respective AC terminal.

In some embodiments, the multi-level power convertor operates as an inverter when the DC port is used as an input and the AC port is used as an output, and the multi-level power convertor operates as a rectifier when the AC port is used as an input and the DC port is used as an output.

In a second aspect of the present disclosure, example embodiments of the present disclosure provide a method for the multi-level power convertor according to the first aspect of the present application. The method comprises providing a predefined number of voltage levels to the first end of the first coupling inductor, the third end of the first coupling inductor, the first end of the second coupling inductor, and the third end of the second coupling inductor, from the first, second, third and fourth power converting units, respectively; generating a first plurality of voltage levels at the first common node with the first coupling inductor; generating a second plurality of voltage levels at the second common node with the second coupling inductor; and outputting a third plurality of voltage levels at the AC port with the third coupling inductor, wherein the number of the third plurality of voltage levels equals to the sum of the number of the first plurality of voltage levels and the number of the second plurality of voltage levels minus one.

According to various embodiments of the present disclosure, the voltage levels provided by the first and second power converting units may be combined by the first coupling inductor into a first plurality of voltage levels, the voltage levels provided by the third and fourth power converting units may be combined by the second coupling inductor into a second plurality of voltage levels, and the first plurality of voltage levels and the second plurality of voltage levels may be combined by the third coupling inductor into a third plurality of voltage levels. In this way, the multi-level power convertor in accordance with embodiments of the present disclosure may use less capacitor to generate the same number of voltage levels as the conventional multi-level power convertor, reducing the risk of voltage imbalance among the capacitors in the multi-level power convertor and thereby avoiding the damage of the switching semiconductor devices in the multi-level power convertor. Hence, the performance and reliability of the multi-level power convertor may be improved.

DESCRIPTION OF DRAWINGS

Through the following detailed descriptions with reference to the accompanying drawings, the above and other objectives, features and advantages of the example embodiments disclosed herein will become more comprehensible. In the drawings, several example embodiments disclosed herein will be illustrated in an example and in a non-limiting manner, wherein:

Fig. 1 illustrates a schematic circuit diagram of a conventional multi-level power convertor;

Fig. 2 illustrates a block diagram of a multi-level power convertor in accordance with an embodiment of the present disclosure;

Fig. 3 illustrates an example arrangement of a coupling inductor and an inductive filtering unit in accordance with an embodiment of the present disclosure;

Fig. 4 illustrates an example arrangement of the coupling inductor and the inductive filtering unit in accordance with another embodiment of the present disclosure;

Fig. 5 illustrates an example arrangement of the coupling inductor and the inductive filtering unit in accordance with yet another embodiment of the present disclosure;

Fig. 6 illustrates a schematic circuit diagram of a multi-level power convertor in accordance with an embodiment of the present disclosure;

Fig. 7 illustrates a schematic circuit diagram of a multi-level power convertor in accordance with another embodiment of the present disclosure;

Fig. 8 illustrates a schematic circuit diagram of a three-phase power converting circuit in accordance with an embodiment of the present disclosure;

Fig. 9 illustrates a schematic circuit diagram of a multi-level power convertor in accordance with another embodiment of the present disclosure;

Fig. 10 illustrates a schematic circuit diagram of a multi-level power convertor in accordance with yet another embodiment of the present disclosure; and

Fig. 11 illustrates a schematic circuit diagram of a three-phase power converting circuit in accordance with another embodiment of the present disclosure.

Throughout the drawings, the same or similar reference symbols are used to indicate the same or similar elements.

DETAILED DESCRIPTION OF EMBODIEMTNS

Principles of the present disclosure will now be described with reference to several example embodiments shown in the drawings. Though example embodiments of the present disclosure are illustrated in the drawings, it is to be understood that the embodiments are described only to facilitate those skilled in the art in better understanding and thereby achieving the present disclosure, rather than to limit the scope of the disclosure in any manner.

The term “comprises” or “includes” and its variants are to be read as open terms that mean “includes, but is not limited to. ” The term “or” is to be read as “and/or” unless the context clearly indicates otherwise. The term “based on” is to be read as “based at least in part on. ” The term “being operable to” is to mean a function, an action, a motion or a state can be achieved by an operation induced by a user or an external mechanism. The term “one embodiment” and “an embodiment” are to be read as “at least one embodiment. ” The term “another embodiment” is to be read as “at least one other embodiment. ” The terms “first, ” “second, ” and the like may refer to different or same objects. Other definitions, explicit and implicit, may be included below. A definition of a term is consistent throughout the description unless the context clearly indicates otherwise.

Unless specified or limited otherwise, the terms “mounted, ” “connected, ” “supported, ” and “coupled” and variations thereof are used broadly and encompass direct and indirect mountings, connections, supports, and couplings. Furthermore, “connected” and “coupled” are not restricted to physical or mechanical connections or couplings. In the description below, like reference numerals and labels are used to describe the same, similar or corresponding parts in the figures. Other definitions, explicit and implicit, may be included below.

As discussed above, the performance and reliability of the conventional multi-level power convertor may be adversely affected due to the use of multiple capacitors. According to embodiments of the present disclosure, to improve the performance and reliability of the multi-level power convertor, the voltage levels provided by the first, second, third and fourth power converting units may be combined into more voltage levels by the first, second and third coupling inductors, such that the multi-level power convertor in accordance with embodiments of the present disclosure may generate the same number of voltage levels as the conventional multi-level power convertor through using less capacitor. The above idea may be implemented in various manners, as will be described in detail in the following paragraphs.

Hereinafter, the principles of the present disclosure will be described in detail with reference to Figs. 2-11. Referring to Fig. 2 first, Fig. 2 illustrates a block diagram of a multi-level power convertor 100 in accordance with an embodiment of the present disclosure. As shown in Fig. 2, the multi-level power convertor 100 generally includes a DC port, an AC port, a first power converting unit 5, a second power converting unit 6, a third power converting unit 7, a fourth power converting unit 8, a first coupling inductor 1, a second coupling inductor 2, a third coupling inductor 3, and an inductive filtering unit 4. The multi-level power convertor 100 may be a bidirectional power convertor. The multi-level power convertor 100 may operate as an inverter when the DC port is used as an input and the AC port is used as an output. Instead, the multi-level power convertor 100 may operate as a rectifier when the AC port is used as an input and the DC port is used as an output.

The DC port includes first and second DC terminals DC+, DC-. The first, second, third, and fourth

power converting units

5, 6, 7, 8 are coupled to the DC port respectively. Each of the first, second, third, and fourth

power converting units

5, 6, 7, 8 includes an

AC terminal

51, 61, 71, 81 for providing a predefined number of voltage levels. In other words, the first, second, third, and fourth

power converting units

5, 6, 7, 8 may provide the same number voltage levels via the

respective AC terminal

51, 61, 71, 81. The first, second, third, and fourth

power converting units

5, 6, 7, 8 have the same switching cycle.

The first coupling inductor 1 includes first and

second windings

11, 12 with the same number of turns. The first winding 11 includes a first end 111 coupled to the AC terminal 51 of the first power converting unit 5 and a second end 112. The second winding 12 includes a third end 121 coupled to the AC terminal 61 of the second power converting unit 6 and a fourth end 122. The second and fourth ends 112, 122 of the first coupling inductor 1 are coupled to a first common node N01. The second end 112 of the first winding 11 and the third end 121 of the second winding 12 are namesake ends of the first and

second windings

11, 12. With such an arrangement, the first and second winding 11, 12 of the first coupling inductor 1 may induce voltages of the same magnitude and opposite directions. With the first coupling inductor 1, the voltage levels provided by the first and second

power converting units

5, 6 may be combined into a first plurality of voltage levels at the first common node N01.

The second coupling inductor 2 includes first and

second windings

21, 22 with the same number of turns. The first winding 21 includes a first end 211 coupled to the AC terminal 71 of the third power converting unit 7 and a second end 212. The second winding 22 includes a third end 221 coupled to the AC terminal 81 of the fourth power converting unit 8 and a fourth end 222. The second and fourth ends 212, 222 of the second coupling inductor 2 are coupled to a second common node N02. The second end 212 of the first winding 21 and the third end 221 of the second winding 22 are namesake ends of the first and

second windings

21, 22. With such an arrangement, the first and second winding 21, 22 of the second coupling inductor 2 may induce voltages of the same magnitude and opposite directions. With the second coupling inductor 2, the voltage levels provided by the third and fourth

power converting units

7, 8 may be combined into a second plurality of voltage levels at the second common node N02.

The third coupling inductor 3 includes first and

second windings

31, 32 with the same number of turns. The first winding 31 includes a first end 311 coupled to the first common node N01 and a second end 312. The second winding 32 includes a third end 321 coupled to the second common node N02 and a fourth end 322. The second end 312 of the first winding 31 and the third end 321 of the second winding 32 are namesake ends of the first and

second windings

31, 32. With such an arrangement, the first and second winding 31, 32 of the third coupling inductor 3 may induce voltages of the same magnitude and opposite directions. With the third coupling inductor 3, the first plurality of voltage levels provided by the first coupling inductor 1 and the second plurality of voltage levels provided by the second coupling inductor 2 may be combined into a second plurality of voltage levels.

In some embodiments, the number of the first plurality of voltage levels equals to the sum of the number of the voltage levels provided by the first power converting unit 5 and the number of the voltage levels provided by the second power converting unit 6 minus one, the number of the second plurality of voltage levels equals to the sum of the number of the voltage levels provided by the third power converting unit 7 and the number of the voltage levels provided by the fourth power converting unit 8 minus one, and the number of the third plurality of voltage levels equals to the sum of the number of the first plurality of voltage levels and the number of the second plurality of voltage levels minus one.

In an embodiment, if the number of the voltage levels provided by each of the first, second, third and fourth

power converting units

5, 6, 7, 8 is three, the number of both the first plurality of voltage levels and the second plurality of voltage levels would be five, and thus the number of the third plurality of voltage levels would be nine. In another embodiment, if the number of the voltage levels provided by each of the first, second, third and fourth

power converting units

5, 6, 7, 8 is five, the number of both the first plurality of voltage levels and the second plurality of voltage levels would be nine, and thus the number of the third plurality of voltage levels would be seventeen. In other embodiments, the voltage levels provided by each of the first, second, third and fourth

power converting units

5, 6, 7, 8 may be of other numbers. Accordingly, the first, second and

third coupling inductors

1, 2, 3 may provide voltage levels of other numbers.

The inductive filtering unit 4 is arranged between the AC port and the third coupling inductor 3 so as to filter the third plurality of voltage levels provided by the third coupling inductor 3. The third coupling inductor 3 and the inductive filtering unit 4 may have various arrangements, which will be described in detail hereinafter with reference to Figs. 3-5.

In an embodiment, as shown in Fig. 3, the second and fourth ends 312, 322 of the third coupling inductor 3 are coupled to a third common node N03. The inductive filtering unit 4 includes an inductor L0 arranged between the third common node N03 and the AC port.

In another embodiment, as shown in Fig. 4, the inductive filtering unit 4 includes a first inductor L1 and a second inductor L2. The first inductor L1 is arranged between the second end 312 of the third coupling inductor 3 and the AC port. The second inductor L2 is arranged between the fourth end 322 of the third coupling inductor 3 and the AC port.

In yet another embodiment, as shown in Fig. 5, the inductive filtering unit 4 includes an additional coupling inductor consisting of third and

fourth windings

41, 42. The third winding 41 is arranged between the second end 312 of the third coupling inductor 3 and the AC port. The fourth winding 42 is arranged between the fourth end 322 of the third coupling inductor 3 and the AC port. Namesake ends of the third and

fourth windings

41, 42 are connected to the AC port.

Fig. 6 illustrates a schematic circuit diagram of a multi-level power convertor 100 in accordance with an embodiment of the present disclosure. As shown in Fig. 6, the third coupling inductor 3 and the inductive filtering unit 4 have the same construction and arrangement as those described with reference to Figs. 2 and 3. It is to be understood that the third coupling inductor 3 and the inductive filtering unit 4 may have other constructions and arrangements, for example those as described above with reference to Figs. 4 and 5. The scope of the present disclosure is not intended to be limited in this respect.

In an embodiment, as shown in Fig. 6, each of the first, second, third and fourth

power converting units

5, 6, 7, 8 includes capacitors C1 and C2 and switching semiconductor devices S1, S2, S3, S4, S5, and S6. The capacitors C1 and C2 and the switching semiconductor devices S1, S2, S3 and S4 are shared by the first, second, third and fourth

power converting units

5, 6, 7, 8.

As shown in Fig. 6, the capacitors C1 and C2 are connected in series between the first and second DC terminals DC+, DC-. The switching semiconductor devices S1, S2, S3, and S4 are line frequency switches having the same switching cycle. The switching semiconductor devices S1, S2, S3, and S4 are connected in series between the first and second DC terminals DC+, DC-. In a positive half cycle of the AC port, the switching semiconductor devices S1 and S3 are turned on and the switching semiconductor devices S2 and S4 are turned off. In a negative half cycle of the AC port, the switching semiconductor devices S1 and S3 are turned off and the switching semiconductor devices S2 and S4 are turned on.

A first node N1 between the capacitors C1 and C2 is connected to a second node N2 between the switching semiconductor devices S2 and S3. The first node N1 may be used as a reference voltage point of the AC port. The switching semiconductor devices S5 and S6 are high frequency switches having the same switching cycle. The switching semiconductor device S5 is connected between a third node N3 and the

respective AC terminal

51, 61, 71, 81. The third node N3 is between the switching semiconductor devices S1 and S2. The sixth switching semiconductor device S6 is connected between a fourth node N4 and the

respective AC terminal

51, 61, 71, 81. The fourth node N4 is between the switching semiconductor devices S3 and S4.

In an embodiment, one way of controlling the switching semiconductor devices S5 and S6 is phase shift PWM control. Under such control, in each of the first, second, third and fourth

power converting units

5, 6, 7, 8, the switching semiconductor devices S5 and S6 are complementary switches. That is, when the switching semiconductor device S5 is switched on, the switching semiconductor device S6 is switched off, and vice versa. The driving signal of the switching semiconductor device S5 in the second power converting unit 6 may lag a quarter of the switching cycle than that of the switching semiconductor device S5 in the first power converting unit 5. The driving signal of the switching semiconductor device S5 in the fourth power converting unit 8 may lag a quarter of the switching cycle than that of the switching semiconductor device S5 in the third power converting unit 7. The driving signal of the switching semiconductor device S5 in the third power converting unit 7 may lag a half of the switching cycle than that of the switching semiconductor device S5 in the first power converting unit 5.

Under the above phase shift PWM control, the voltage levels provided by the second power converting unit 6 are phase-shifted by 90 degree, i.e., a quarter of the switching cycle of the first, second, third and fourth

power converting units

5, 6, 7, 8, with respect to the voltage levels provided by the first power converting unit 5. Similarly, the voltage levels provided by the fourth power converting unit 8 are phase-shifted by 90 degree with respect to the voltage levels provided by the third power converting unit 7. Moreover, the voltage levels provided by the third power converting unit 7 are phase-shifted by 180 degree, i.e., a half of the switching cycle of the first, second, third and fourth

power converting units

5, 6, 7, 8, with respect to the voltage levels provided by the first power converting unit 5. Accordingly, there is a phase shift of a half of the switching cycle between the first plurality of voltage levels provided by the first coupling inductor 1 and the second plurality of voltage levels provided by the second coupling inductor 2.

With the above arrangement and control method, each of the first, second, third and fourth

power converting units

5, 6, 7, 8 may provide three voltage levels at the

respective AC terminals

51, 61, 71, 81. Accordingly, each of the first and

second coupling inductors

1, 2 may provide five voltage levels, and the third coupling inductor 3 may provide nine voltage levels. In comparison with the conventional multi-level power convertor 100 as shown in Fig. 1, in each of the first, second, third and fourth

power converting units

5, 6, 7, 8 as shown in Fig. 6, less capacitors are used, thus reducing the risk of voltage imbalance among the capacitors in the multi-level power convertor 100 and thereby avoiding the damage of the switching semiconductor devices in the multi-level power convertor 100.

In another embodiment, the switching semiconductor devices S5 and S6 in each of the first, second, third and fourth

power converting units

5, 6, 7, 8 may be controlled such that the voltage levels provided by the second power converting unit 6 are phase-shifted by 180 degree with respect to the voltage levels provided by the first power converting unit 5, the voltage levels provided by the fourth power converting unit 8 are phase-shifted by 180 degree with respect to the voltage levels provided by the third power converting unit 7, and the voltage levels provided by the third power converting unit 7 are phase-shifted by 90 degree with respect to the voltage levels provided by the first power converting unit 5. Accordingly, each of the first, second, third and fourth

power converting units

5, 6, 7, 8 may provide three voltage levels at the

respective AC terminals

51, 61, 71, 81, each of the first and

second coupling inductors

1, 2 may provide five voltage levels, and the third coupling inductor 3 may provide nine voltage levels.

In other embodiments, the voltage levels provided by the first, second, third and fourth

power converting units

5, 6, 7, 8 may have other phase relationships. The scope of the present disclosure is not intended to be limited in this respect.

Fig. 7 illustrates a schematic circuit diagram of a multi-level power convertor 100 in accordance with another embodiment of the present disclosure. The construction of the multi-level power convertor 100 as shown in Fig. 7 is similar to that of the multi-level power convertor 100 as shown in Fig. 6. The difference between the multi-level power convertors 100 as shown in Figs. 6 and 7 lies in the specific arrangement of the capacitors C1 and C2 and the switching semiconductor devices S1, S2, S3 and S4. As shown in Fig. 7, the capacitors C1 and C2 and the switching semiconductor devices S1, S2, S3 and S4 are provided individually for each of the first, second, third and fourth

power converting units

5, 6, 7, 8. In other words, each of the first, second, third and fourth

power converting units

5, 6, 7, 8 includes the capacitors C1 and C2 and the switching semiconductor devices S1, S2, S3 and S4 as described above with reference to Fig. 6.

With the above arrangements, the operation of the multi-level power convertor 100 as shown in Fig. 7 is similar to that of the multi-level power convertor 100 as shown in Fig. 6.

It is noted that each of the multi-level power convertors 100 as described with reference to Figs. 2-7 is a single-phase circuit. However, in embodiments of the present disclosure, each of the multi-level power convertors 100 may be used to form a three-phase circuit. Fig. 8 illustrates a schematic circuit diagram of a three-phase power converting circuit 200 in accordance with an embodiment of the present disclosure. As shown in Fig. 8, the three-phase power converting circuit 200 includes three phases L11, L22, and L33. Each of the phases L11, L22, and L33 includes the multi-level power convertor 100 as described above with reference to Fig. 6. With such an arrangement, each of the phases L11, L22, and L33 may provide nine voltage levels. It is to be understood that in some embodiments, each of the phases L11, L22, and L33 may include the multi-level power convertor 100 according to other embodiments of the present disclosure.

Fig. 9 illustrates a schematic circuit diagram of a multi-level power convertor 100 in accordance with another embodiment of the present disclosure. The construction of the multi-level power convertor 100 as shown in Fig. 9 is similar to that of the multi-level power convertor 100 as shown in Fig. 6. The difference between the multi-level power convertors 100 as shown in Figs. 9 and 6 lies in the construction of the first, second, third and fourth

power converting units

5, 6, 7, 8. As shown in Fig. 9, each of the first, second, third and fourth

power converting units

5, 6, 7, 8 further includes switching semiconductor devices S7 and S8 and a capacitor C3. The switching semiconductor device S7 is coupled between the switching semiconductor device S5 and the

respective AC terminals

51, 61, 71, 81. The switching semiconductor device S8 is coupled between the switching semiconductor device S6 and the

respective AC terminals

51, 61, 71, 81. The third capacitor C3 is arranged between a fifth node N5 and a sixth node N6. The fifth node N5 is between the switching semiconductor devices S5 and S7. The sixth node N6 is between the switching semiconductor devices S6 and S8.

With the above arrangement, each of the first, second, third and fourth

power converting units

5, 6, 7, 8 as shown in Fig. 9 may provide five voltage levels at the

respective AC terminals

51, 61, 71, 81. Accordingly, each of the first and

second coupling inductors

1, 2 may provide nine voltage levels, and the third coupling inductor 3 may provide seventeen voltage levels.

Fig. 10 illustrates a schematic circuit diagram of a multi-level power convertor 100 in accordance with yet another embodiment of the present disclosure. The construction of the multi-level power convertor 100 as shown in Fig. 10 is similar to that of the multi-level power convertor 100 as shown in Fig. 7. The difference between the multi-level power convertors 100 as shown in Figs. 10 and 7 lies in the construction of the first, second, third and fourth

power converting units

5, 6, 7, 8. As shown in Fig. 10, each of the first, second, third and fourth

power converting units

respective AC terminals

With the above arrangement, each of the first, second, third and fourth

power converting units

5, 6, 7, 8 as shown in Fig. 10 may provide five voltage levels at the

respective AC terminals

51, 61, 71, 81. Accordingly, each of the first and

second coupling inductors

It is to be understood that in embodiments of the present disclosure, the switching semiconductor devices in the first, second, third and fourth

power converting units

5, 6, 7, 8 may be of various types, for example MOSFET, IGBT and the like. The scope of the present disclosure is not intended to be limited in this respect.

Fig. 11 illustrates a schematic circuit diagram of a three-phase power converting circuit 200 in accordance with another embodiment of the present disclosure. As shown in Fig. 11, the three-phase power converting circuit 200 includes three phases L11, L22, and L33. Each of the phases L11, L22, and L33 includes the multi-level power convertor 100 as described above with reference to Fig. 2.

As shown in Fig. 11, each of the first, second, third and fourth

power converting units

5, 6, 7, 8 includes capacitors C1 and C2 and switching semiconductor devices S9, S10, S11, and S12. The capacitors C1 and C2 are connected in series between the first and second DC terminals DC+, DC-. The switching semiconductor devices S9 and S10 are coupled in series between a first node N1 and the

respective AC terminals

51, 61, 71, 81. The first node N1 is between the capacitors C1 and C2. The switching semiconductor devices S11 and S12 are coupled in series between the first and second DC terminals DC+, DC-. A seventh node N7 between the switching semiconductor devices S11 and S12 is coupled to the

respective AC terminals

51, 61, 71, 81.

In some embodiments, as shown in Fig. 11, each of the switching semiconductor devices S9 and S10 includes MOSFET, and each of the switching semiconductor devices S11 and S12 includes a diode. The driving signal of the switching semiconductor device S10 in the second power converting unit 6 may lag a half of the switching cycle than that of the switching semiconductor device S10 in the first power converting unit 5. The driving signal of the switching semiconductor device S10 in the fourth power converting unit 8 may lag a half of the switching cycle than that of the switching semiconductor device S10 in the third power converting unit 7. The driving signal of the switching semiconductor device S10 in the third power converting unit 7 may lag a quarter of the switching cycle than that of the switching semiconductor device S10 in the first power converting unit 5.

Taking the first node N1 as the reference voltage point of each of the phases L11, L22, and L33, each of the first, second, third and fourth

power converting units

5, 6, 7, 8 may provide three voltage levels at the

respective AC terminals

51, 61, 71, 81. Accordingly, each of the first and

second coupling inductors

It is to be understood that in other embodiments, each of the switching semiconductor devices S9, S10, S11 and S12 may be of other types. For example, each of the switching semiconductor devices S9 and S10 may include IGBT, and each of switching semiconductor devices S11 and S12 may include MOSFET, IGBT and the like.

In some embodiments, a method for the multi-level power convertor 100 as described above is provided. The method includes the method comprising: providing a predefined number of voltage levels to the first end 111 of the first coupling inductor 1, the third end 121 of the first coupling inductor 1, the first end 211 of the second coupling inductor 2, and the third end 221 of the second coupling inductor 2, from the first, second, third and fourth power converting units 5, 6, 7, 8, respectively; generating a first plurality of voltage levels at the first common node N01 with the first coupling inductor 1, wherein the number of the first plurality of voltage levels equals to the sum of the number of the voltage levels provided by the first power converting unit 5 and the number of the voltage levels provided by the second power converting unit 6 minus one; generating a second plurality of voltage levels at the second common node N02 with the second coupling inductor 2, wherein the number of the second plurality of voltage levels equals to the sum of the number of the voltage levels provided by the third power converting unit 7 and the number of the voltage levels provided by the fourth power converting unit 8 minus one; and outputting a third plurality of voltage levels at the AC port with the third coupling inductor 3, wherein the number of the third plurality of voltage levels equals to the sum of the number of the first plurality of voltage levels and the number of the second plurality of voltage levels minus one.

According to various embodiments of the present disclosure, the voltage levels provided by the first and second

power converting units

5, 6 may be combined by the first coupling inductor 1 into a first plurality of voltage levels, the voltage levels provided by the third and fourth

power converting units

7, 8 may be combined by the second coupling inductor 2 into a second plurality of voltage levels, and the first plurality of voltage levels and the second plurality of voltage levels may be combined by the third coupling inductor 3 into a third plurality of voltage levels. In this way, the multi-level power convertor 100 in accordance with embodiments of the present disclosure may use less capacitor to generate the same number of voltage levels as the conventional multi-level power convertor, reducing the risk of voltage imbalance among the capacitors in the multi-level power convertor 100 and thereby avoiding the damage of the switching semiconductor devices in the multi-level power convertor 100. Hence, the performance and reliability of the multi-level power convertor 100 may be improved.

While several inventive embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the function and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the inventive embodiments described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and/or configurations will depend upon the specific application or applications for which the inventive teachings is/are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific inventive embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and/or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and/or methods, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure.

Claims

A multi-level power convertor (100) comprising:

a DC port;

an AC port;

first, second, third and fourth power converting units (5, 6, 7, 8) each coupled to the DC port and each comprising an AC terminal (51, 61, 71, 81) adapted to provide a predefined number of voltage levels;

first, second and third coupling inductors (1, 2, 3) each comprising first and second windings (11, 21, 31; 12, 22, 32) with the same number of turns, each of the first windings (11, 21, 31) comprising a first end (111, 211, 311) and a second end (112, 212, 312) , and each of the second windings (12, 22, 32) comprising a third end (121, 221, 321) and a fourth end (122, 222, 322) ,

wherein the first end (111) of the first coupling inductor (1) is coupled to the AC terminal (51) of the first power converting unit (5) , the third end (121) of the first coupling inductor (1) is coupled to the AC terminal (61) of the second power converting unit (6) , the first end (211) of the second coupling inductor (2) is coupled to the AC terminal (71) of the third power converting unit (7) , and the third end (221) of the second coupling inductor (2) is coupled to the AC terminal (81) of the fourth power converting unit (8) ,

wherein the second and fourth ends (112, 122) of the first coupling inductor (1) are coupled to a first common node (N01) , and the second and fourth ends (212, 222) of the second coupling inductor (2) are coupled to a second common node (N02) , and

wherein the first end (311) of the third coupling inductor (3) is coupled to the first common node (N01) , and the third end (321) of the third coupling inductor (3) is coupled to the second common node (N02) ; and

an inductive filtering unit (4) arranged between the AC port and the second and fourth ends (312, 322) of the third coupling inductor (3) .
The multi-level power convertor (100) according to claim 1, wherein the second and fourth ends (312, 322) of the third coupling inductor (3) are coupled to a third common node (N03) , and the inductive filtering unit (4) comprises an inductor (L0) arranged between the third common node (N03) and the AC port.
The multi-level power convertor (100) according to claim 1, wherein the inductive filtering unit (4) comprises:

a first inductor (L1) arranged between the second end (312) of the third coupling inductor (3) and the AC port; and

a second inductor (L2) arranged between the fourth end (322) of the third coupling inductor (3) and the AC port.
The multi-level power convertor (100) according to claim 1, wherein the inductive filtering unit (4) comprises an additional coupling inductor comprising third and fourth windings (41, 42) ,

wherein the third winding (41) is arranged between the second end (312) of the third coupling inductor (3) and the AC port, and

wherein the fourth winding (42) is arranged between the fourth end (322) of the third coupling inductor (3) and the AC port.
The multi-level power convertor (100) according to claim 1, wherein each of the AC terminals (51, 61, 71, 81) provides three voltage levels, each of the first and second common nodes (N01, N02) provides five voltage levels, and the AC port provides nine voltage levels.
The multi-level power convertor (100) according to claim 1, wherein each of the AC terminals (51, 61, 71, 81) provides five voltage levels, each of the first and second common nodes (N01, N02) provides nine voltage levels, and the AC port provides seventeen voltage levels.
The multi-level power convertor (100) according to claim 1, wherein the DC port comprises first and second DC terminals (DC+, DC-) , and wherein each of the first, second, third and fourth power converting units (5, 6, 7, 8) comprises:

first and second capacitors (C1, C2) coupled in series between the first and second DC terminals (DC+, DC-) ;

first, second, third, and fourth switching semiconductor devices (S1, S2, S3, S4) coupled in series between the first and second DC terminals (DC+, DC-) , wherein a first node (N1) between the first and second capacitors (C1, C2) is coupled to a second node (N2) between the second and third switching semiconductor devices (S2, S3) ;

a fifth switching semiconductor device (S5) coupled between a third node (N3) and the respective AC terminal (51, 61, 71, 81) , the third node (N3) being between the first and second switching semiconductor devices (S1, S2) ; and

a sixth switching semiconductor device (S6) coupled between a fourth node (N4) and the respective AC terminal (51, 61, 71, 81) , the fourth node (N4) being between the third and fourth switching semiconductor devices (S3, S4) .
The multi-level power convertor (100) according to claim 7, wherein the first and second capacitors (C1, C2) and the first, second, third, and fourth switching semiconductor devices (S1, S2, S3, S4) are shared by the first, second, third and fourth power converting units (5, 6, 7, 8) .
The multi-level power convertor (100) according to claim 7, wherein the first and second capacitors (C1, C2) and the first, second, third, and fourth switching semiconductor devices (S1, S2, S3, S4) are provided individually for each of the first, second, third and fourth power converting units (5, 6, 7, 8) .
The multi-level power convertor (100) according to claim 7, wherein each of the first, second, third and fourth power converting units (5, 6, 7, 8) further comprises:

a seventh switching semiconductor device (S7) coupled between the fifth switching semiconductor device (S5) and the respective AC terminal (51, 61, 71, 81) ;

an eighth switching semiconductor device (S8) coupled between the sixth switching semiconductor device (S6) and the respective AC terminal (51, 61, 71, 81) ; and

a third capacitor (C3) arranged between a fifth node (N5) and a sixth node (N6) , the fifth node (N5) being between the fifth switching semiconductor device (S5) and the seventh switching semiconductor device (S7) , and the sixth node (N6) being between the sixth switching semiconductor device (S6) and the eighth switching semiconductor device (S8) .
The multi-level power convertor (100) according to claim 1,

wherein the voltage levels provided by the second power converting unit (6) are phase-shifted by 90 degree with respect to the voltage levels provided by the first power converting unit (5) ,

wherein the voltage levels provided by the fourth power converting unit (8) are phase-shifted by 90 degree with respect to the voltage levels provided by the third power converting unit (7) , and

wherein the voltage levels provided by the third power converting unit (7) are phase-shifted by 180 degree with respect to the voltage levels provided by the first power converting unit (5) .
The multi-level power convertor (100) according to claim 1,

wherein the voltage levels provided by the second power converting unit (6) are phase-shifted by 180 degree with respect to the voltage levels provided by the first power converting unit (5) ,

wherein the voltage levels provided by the fourth power converting unit (8) are phase-shifted by 180 degree with respect to the voltage levels provided by the third power converting unit (7) , and

wherein the voltage levels provided by the third power converting unit (7) are phase-shifted by 90 degree with respect to the voltage levels provided by the first power converting unit (5) .
The multi-level power convertor (100) according to claim 1, wherein the DC port comprises first and second DC terminals (DC+, DC-) , and wherein each of the first, second, third and fourth power converting units (5, 6, 7, 8) comprises:

first and second capacitors (C1, C2) coupled in series between the first and second DC terminals (DC+, DC-) ;

ninth and tenth switching semiconductor devices (S9, S10) coupled in series between a first node (N1) and the respective AC terminal (51, 61, 71, 81) , the first node (N1) being between the first and second capacitors (C1, C2) ; and

eleventh and twelfth switching semiconductor devices (S11, S12) coupled in series between the first and second DC terminals (DC+, DC-) , wherein a seventh node (N7) between the eleventh and twelfth switching semiconductor devices (S11, S12) is coupled to the respective AC terminal (51, 61, 71, 81) .
The multi-level power convertor (100) according to claim 1, wherein the multi-level power convertor (100) operates as an inverter when the DC port is used as an input and the AC port is used as an output, and

wherein the multi-level power convertor (100) operates as a rectifier when the AC port is used as an input and the DC port is used as an output.
A method for a multi-level power convertor (100) , the multi-level power convertor (100) comprising a DC port; an AC port; first, second, third and fourth power converting units (5, 6, 7, 8) each coupled to the DC port and each comprising an AC terminal (51, 61, 71, 81) adapted to provide a predefined number of voltage levels; first, second and third coupling inductors (1, 2, 3) each comprising first and second windings (11, 21, 31; 12, 22, 32) with the same number of turns, each of the first windings (11, 21, 31) comprising a first end (111, 211, 311) and a second end (112, 212, 312) , and each of the second windings (12, 22, 32) comprising a third end (121, 221, 321) and a fourth end (122, 222, 322) , wherein the first end (111) of the first coupling inductor (1) is coupled to the AC terminal (51) of the first power converting unit (5) , the third end (121) of the first coupling inductor (1) is coupled to the AC terminal (61) of the second power converting unit (6) , the first end (211) of the second coupling inductor (2) is coupled to the AC terminal (71) of the third power converting unit (7) , and the third end (221) of the second coupling inductor (2) is coupled to the AC terminal (81) of the fourth power converting unit (8) , wherein the second and fourth ends (112, 122) of the first coupling inductor (1) are coupled to a first common node (N01) , and the second and fourth ends (212, 222) of the second coupling inductor (2) are coupled to a second common node (N02) , and wherein the first end (311) of the third coupling inductor (3) is coupled to the first common node (N01) , and the third end (321) of the third coupling inductor (3) is coupled to the second common node (N02) ; and an inductive filtering unit (4) arranged between the AC port and the second and fourth ends (312, 322) of the third coupling inductor (3) ,

the method comprising:

providing a predefined number of voltage levels to the first end (111) of the first coupling inductor (1) , the third end (121) of the first coupling inductor (1) , the first end (211) of the second coupling inductor (2) , and the third end (221) of the second coupling inductor (2) , from the first, second, third and fourth power converting units (5, 6, 7, 8) , respectively;

generating a first plurality of voltage levels at the first common node (N01) with the first coupling inductor (1) ;

generating a second plurality of voltage levels at the second common node (N02) with the second coupling inductor (2) ; and

outputting a third plurality of voltage levels at the AC port with the third coupling inductor (3) , wherein the number of the third plurality of voltage levels equals to the sum of the number of the first plurality of voltage levels and the number of the second plurality of voltage levels minus one.