WO2022021896A1 - 一种进程间通信的方法及装置 - Google Patents

一种进程间通信的方法及装置 Download PDF

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Publication number
WO2022021896A1
WO2022021896A1 PCT/CN2021/081410 CN2021081410W WO2022021896A1 WO 2022021896 A1 WO2022021896 A1 WO 2022021896A1 CN 2021081410 W CN2021081410 W CN 2021081410W WO 2022021896 A1 WO2022021896 A1 WO 2022021896A1
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execution entity
data
execution
entity
memory
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PCT/CN2021/081410
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English (en)
French (fr)
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王楠
齐义飞
余青松
付明
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华为技术有限公司
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Priority to EP21849255.1A priority Critical patent/EP4187386A4/en
Publication of WO2022021896A1 publication Critical patent/WO2022021896A1/zh
Priority to US18/160,671 priority patent/US20230168953A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/54—Indexing scheme relating to G06F9/54
    • G06F2209/543—Local

Definitions

  • the present application relates to the field of computer technologies, and in particular, to a method and apparatus for inter-process communication.
  • the sending (send)-receiving (recv) semantic model based on communication channel is usually used to realize the sending and receiving of inter-process messages.
  • the kernel provides interprocess communication (IPC) services through communication channels, which are created by the receiving process and granted to the sending process.
  • IPC interprocess communication
  • the sending process prepares the data to be sent in user mode according to the requirements, and then the sending process and the receiving process use memory blocks (buffers) to send and receive data respectively.
  • buffers memory blocks
  • the sending process needs to serialize the data. Deserialization of data results in additional performance overhead during inter-process communication.
  • the present application provides an interprocess communication method for reducing the performance overhead of interprocess communication (IPC).
  • the present application also provides corresponding apparatuses, computer-readable storage media, computer program products, and the like.
  • a first aspect of the present application provides a method for inter-process communication.
  • the method is applied to a computer system.
  • the method includes: according to a calling convention, writing communication information into a register group of a first execution entity of a sending process, and writing target data into a register group.
  • the first data is written into the stack memory of the first execution entity
  • the communication information includes a first value
  • the first value is used to indicate the data amount of the first data
  • the target data is the data to be sent by the sending process to the first receiving process
  • the calling convention is used to indicate the writing order of the communication information in the register group and the writing order of the first data in the stack memory; copy the information in the register group of the first execution entity into the context of the first execution entity,
  • the information in the register group includes communication information and the address of the stack memory, and the context of the first execution entity is the information in the register group of the first execution entity stored in the kernel; according to the first value in the context of the first execution entity and the stack
  • the address of the memory the first data is copied from the stack memory of the first execution entity to the stack memory of the second execution entity of the first receiving process, and the second execution entity is used for the communication between the first receiving process and the sending process.
  • the calling convention is a stipulation related to data writing and data reading applied under the architectures such as x86 and arm.
  • Data includes the values in various types of registers, as well as the data to be passed by inter-process communication.
  • the calling convention specifies the order of writing data in the registers and stack memory corresponding to the execution entity of the sending process, and the order of reading data from the registers and stack memory corresponding to the execution entity of the receiving process.
  • the register group includes general-purpose registers, and the general-purpose registers may also be used to store all or part of the target data to be transmitted by the sending process and the first receiving process.
  • the general-purpose register can complete the transfer.
  • the first value used to describe the first data stored in the stack memory can be equal to 0.
  • the communication information (ipcinfo) will be written into the register group, and the register group may also include a stack frame register, and the stack frame register will write the address of the stack memory.
  • the execution entity (activation) is a part of the thread control block (thread control block, TCB), and the TCB also includes the scheduling entity.
  • a TCB is a data structure that stores information related to the corresponding thread.
  • a process may include multiple threads and also include one or more TCBs, the first execution entity is located in a TCB of the sending process, and the second execution entity is the execution entity of the first receiving process.
  • Interprocess communication needs to fall into the kernel from user mode and complete data transfer in the kernel. Therefore, after the above trigger sending process falls into the kernel from the user mode, the first data is copied from the stack memory of the first execution entity to the second execution entity in the kernel according to the first value in the context of the first execution entity and the address of the stack memory. In the stack memory of the entity, the data transfer can be completed.
  • the inter-process communication data is transmitted through the stack memory. Since the stack memory address always exists in the register group at the sending end, it is not necessary to write the address of the stack memory for inter-process communication. The communication overhead is reduced, and the data of inter-process communication can be directly read from the stack memory for processing at the receiving end, without the need to first read the data of inter-process communication from the memory block and then write it into the stack memory, and then Then process it, which further reduces the performance overhead of inter-process communication.
  • the target data further includes second data
  • the method further includes: according to The calling convention is to write the second data into the register group of the first execution entity, and the calling convention is also used to indicate the writing sequence of the second data in the register group; the above steps: write the information in the register group of the first execution entity
  • the copying into the context of the first execution entity includes: copying the second data, communication information and the address of the stack memory in the register group into the context of the first execution entity.
  • the method further includes: copying the context of the first execution entity into the context of the second execution entity; and writing the context of the second execution entity into the register group of the second execution entity.
  • the target data to be sent by the sending process to the first receiving process includes two parts, the first data and the second data, the first data is sent through the stack memory, and the second data is sent through the register group.
  • the transmission speed of the second data can be improved, and the performance of inter-process communication can be improved.
  • the target data to be sent by the sending process to the first receiving process may be all sent through the stack memory, or all sent through the register group.
  • the target data further includes third data
  • the communication information further includes a second value, where the second value is used to indicate the third data stored in the first memory block of the first execution entity
  • the method further includes: writing the address of the first memory block into the register group of the first execution entity, and writing the third data into the first memory block of the first execution entity; according to the second value, and The address of the first memory block, the third data is copied from the memory block of the first execution entity to the memory block of the second execution entity.
  • a part of the data such as the third data, may be transmitted through the first memory block.
  • the data amount (that is, the second value) of the third data can be carried in the communication information to notify the first receiving process, which is also beneficial to the transmission of large data while ensuring the performance overhead.
  • the first execution entity further includes first page table information
  • the second execution entity further includes second page table information, first page table information and second page table information For the first data to be copied from the stack memory of the first execution entity to the stack memory of the second execution entity, or the third data to be copied from the first memory block of the first execution entity to the memory block of the second execution entity.
  • the above-mentioned replication process of implementing data based on the first page table information and the second page table information may include the following two types:
  • the first copy method copy the first data from the stack memory of the user mode to the memory of the kernel based on the information of the first page table, and then copy the first data from the memory of the kernel to the memory of the second execution entity based on the information of the second page table. stack memory.
  • the principle of copying from the first memory block of the first execution entity to the memory block of the second execution entity is also the same.
  • the second copying method map the stack memory of the first execution entity to the first memory of the kernel based on the first page table information, and map the stack memory of the second execution entity to the first memory of the kernel based on the page table information of the second execution entity.
  • Second memory copy the first data from the first memory to the second memory.
  • the principle of copying from the first memory block of the first execution entity to the memory block of the second execution entity is also the same.
  • the method further includes: superimposing a second execution entity on the first execution entity, and writing the context of the second execution entity into a register group of the second execution entity, wherein, the context of the second execution entity includes data in the context of the first execution entity.
  • the method further includes: superimposing a second execution entity on the first execution entity, and writing the context of the second execution entity into a register group of the second execution entity, wherein, the context of the second execution entity includes data in the context of the first execution entity.
  • the calling convention is also used to indicate the The read sequence of the register set and stack memory of the second execution entity.
  • the second execution entity can be superimposed on the first execution entity by means of a linked list. After the second execution entity is superimposed, the first execution entity will enter an inactive state, and the second execution entity will take over. For the work of the first execution entity, the second execution entity superimposed on the first execution entity will be switched to the user mode of the second execution entity. As the second execution entity switches from the kernel to the user mode, the second execution entity will be switched to The context of the entity is written into the register group of the second execution entity, so that the second execution entity can read and process the target data in the user mode, thereby obtaining the processing result.
  • the first execution entity is located in a thread of the sending process, or in a TCB, and the TCB also includes a scheduling entity. After the second execution entity is superimposed on the first execution entity, the TCB is The second execution entity and the scheduling entity are included, so that the present application realizes that a thread of the sending process borrows the second execution entity of the first receiving process to process the target data and obtain the processing result. It can be seen that this possible implementation provides a different form of inter-process communication.
  • the communication information further includes an identifier of a function used to process the target data; the above steps: processing all or part of the target data to obtain a processing result, including: executing according to the second The identification of the function in the register group of the entity, the function is called, and all or part of the target data is processed to obtain the processing result.
  • the identifier of the function is transmitted in the communication information, so that it can be ensured that the sending process can accurately call the function used for target data processing after borrowing the resources of the first receiving process, which improves the accuracy of data processing. Spend.
  • the first execution entity further includes an identifier of the sending process
  • the method further includes: writing the identifier of the sending process into the context of the second execution entity, and the identifier of the sending process is used Verifying the identity of the sending process at the second execution entity.
  • the identifier of the sending process is written into the context of the second execution entity, and in the process of switching the second execution entity to the user state, the identifier of the sending process is also written into the second execution entity's In the register group, in this way, the receiving end can read the identity of the sending process from the register group, and then perform authentication.
  • the authentication process can be understood with reference to the principle of whitelisting, and safe processes will be registered in advance to the whitelist.
  • the receiving end can find out whether the identifier is in the whitelist according to the identifier of the sending process. If it is in the whitelist, it can confirm that the sending process is a safe process.
  • the execution When the entity executes the inter-process communication, the identifier of the sending process is transmitted by the second execution entity, so as to authenticate the sending process and improve the security of the inter-process communication.
  • the method further includes: determining a first value according to a data volume of the target data and a calling convention; and using the first value to generate communication information.
  • the first data to be written into the stack memory may be determined according to the data amount of the target data.
  • the target data is large, you need to use the memory block to transfer the data, you can then determine the amount of data to be written into the third data in the memory block, that is, the second value, and then Both the first value and the second value are placed in the communication.
  • the first receiving process can be notified of the data amount of the target data in the stack memory and the memory block through the communication information, and then the first receiving process can read the corresponding first data from the stack memory, and read the corresponding first data from the memory block.
  • the corresponding third data is read for data processing.
  • the method further includes: allocating the second execution entity from the resource pool of the execution entity; if the number of available execution entities after subtracting the second execution entity from the resource pool is lower than the lower line , a new execution entity is created in the resource pool, and the lower line is used to indicate the lower limit of the number of available execution entities in the resource pool.
  • the first receiving process has an execution entity that can provide the service, and the number of available execution entities is controllable, which avoids the blocking of the sending process. Reliability issues.
  • the method further includes: after obtaining the processing result, releasing the second execution entity; if the number of available execution entities after the second execution entity is added to the resource pool is higher than that of the water supply line, then at least one execution entity is deleted from the resource pool, and the upper water line is used to indicate the upper limit of the number of available execution entities in the resource pool.
  • the first receiving process is located in a multi-level IPC sequence
  • the multi-level IPC sequence further includes a second receiving process
  • the second receiving process is located in the first receiving process.
  • the method further includes: passing the address of the second memory block of the first executing entity, the first page table information of the first executing entity, and the third value to the first executing entity through the second executing entity of the first receiving process.
  • the third execution entity of the receiving process is used to indicate the data amount of the fourth data sent by the sending process to the second receiving process; according to the address of the second memory block of the first execution entity, the first execution entity A page table information, and the third value, copy the fourth data from the second memory block of the first execution entity to the memory block of the third execution entity.
  • receiving processes may also be included between the first receiving process and the second receiving process, no matter if one or more intermediate processes are included between the sending process and the second receiving process, in this application, the sending process to the first receiving process
  • the second receiving process only needs to transmit the address of the second memory block, the data amount of the fourth data and the first page table information, and the second receiving process only needs to perform a cross-process copy of the fourth data, which greatly improves the performance of data transmission .
  • the method further includes: passing the identifier of the sending process to the third executing entity of the second receiving process through the second executing entity of the first receiving process, where the identifier of the sending process is used for The third execution entity verifies the identity of the sending process after returning to the user state.
  • the second receiving process can directly read the identifier of the sending process transmitted by the kernel, and then perform identity verification, thereby improving the security of inter-process communication.
  • a second aspect of the present application provides an apparatus for inter-process communication, where the apparatus for inter-process communication has the function of implementing the method of the first aspect or any possible implementation manner of the first aspect.
  • This function can be implemented by hardware or by executing corresponding software by hardware.
  • the hardware or software includes one or more modules corresponding to the above functions, such as a processing unit.
  • a third aspect of the present application provides a computer device comprising at least one processor, a memory, an input/output (I/O) interface, and a computer executable stored in the memory and executable on the processor Instructions, when the computer-executed instructions are executed by the processor, the processor executes the method as described above in the first aspect or any possible implementation manner of the first aspect.
  • a fourth aspect of the present application provides a computer-readable storage medium that stores one or more computer-executable instructions.
  • the processor executes the first aspect or any one of the possible operations of the first aspect. method of implementation.
  • a fifth aspect of the present application provides a computer program product that stores one or more computer-executable instructions.
  • the processor executes the first aspect or any possible implementation manner of the first aspect. Methods.
  • a sixth aspect of the present application provides a chip system, the chip system includes at least one processor, and the at least one processor is configured to support inter-process communication.
  • the device implements the first aspect or any of the possible implementation manners of the first aspect. functions involved.
  • the chip system may further include a memory, which is used for storing necessary program instructions and data of the device for inter-process communication.
  • the chip system may be composed of chips, or may include chips and other discrete devices.
  • the inter-process communication data is transmitted through the stack memory. Since the stack memory address always exists in the register group at the sending end, the address of the stack memory does not need to be specially written for the inter-process communication, which can reduce the communication rate. In addition, at the receiving end, the data of inter-process communication can be directly read from the stack memory for processing, and there is no need to read the data of inter-process communication from the memory block first and then write it into the stack memory, and then perform processing, which further reduces the performance overhead of inter-process communication.
  • the present application does not need to transmit data in multiple stages through the intermediate process, and only needs one cross-process copy to complete the data transmission of the multi-level IPC sequence, which greatly reduces the communication overhead and improves the process. performance of intercommunication.
  • FIG. 1 is a schematic diagram of an embodiment of a computer system provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of an embodiment of a method for inter-process communication provided by an embodiment of the present application
  • 3A is a schematic diagram of another embodiment of a method for inter-process communication provided by an embodiment of the present application.
  • FIG. 3B is a schematic diagram of another embodiment of the method for inter-process communication provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of another embodiment of the method for inter-process communication provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of another embodiment of the method for inter-process communication provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of another embodiment of the method for inter-process communication provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of another embodiment of the method for inter-process communication provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of an embodiment of an apparatus for inter-process communication provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of an embodiment of a computer device provided by an embodiment of the present application.
  • the embodiments of the present application provide an inter-process communication method, which is used to reduce the performance overhead of inter-process communication (interprocess communication, IPC).
  • IPC inter-process communication
  • the present application also provides corresponding apparatuses, computer-readable storage media, computer program products, and the like. Each of them will be described in detail below.
  • the method for inter-process communication is applied to a computer system, and the computer system may be a server, a terminal device, or a virtual machine (virtual machine, VM).
  • the computer system may be a server, a terminal device, or a virtual machine (virtual machine, VM).
  • VM virtual machine
  • the architecture of the computer system can be understood with reference to FIG. 1 .
  • Terminal equipment also known as user equipment (UE) is a device with wireless transceiver functions that can be deployed on land, including indoor or outdoor, handheld or vehicle-mounted; it can also be deployed on water (such as ships). etc.); can also be deployed in the air (eg on airplanes, balloons, satellites, etc.).
  • the terminal may be a mobile phone (mobile phone), a tablet computer (pad), a computer with a wireless transceiver function, a virtual reality (virtual reality, VR) terminal, an augmented reality (augmented reality, AR) terminal, an industrial control (industrial control) wireless terminals in self-driving, wireless terminals in remote medical, wireless terminals in smart grid, wireless terminals in transportation safety, Wireless terminals in smart cities, wireless terminals in smart homes, etc.
  • VR virtual reality
  • AR augmented reality
  • industrial control industrial control
  • FIG. 1 is a schematic structural diagram of a computer system.
  • the architecture of the computer system 10 includes a user layer 101 , a kernel 102 , a compiler 103 and a hardware layer 104 .
  • the user layer 101 includes multiple applications, each application corresponds to a process, and a process can also be understood as an abstraction or entity of an application.
  • a process may be called a sending process when executing a sending task of a corresponding application, and may be called a receiving process when executing a receiving task of a corresponding application.
  • the process of inter-process communication can be initiated by the user by triggering the application. For example, the user opens a web page in the browser, and when browsing a message in the web page, a plug-in is required to assist in completing the full-text loading of the message.
  • the web page is Sending process
  • the plug-in is the receiving process
  • the process of the web page needs to send the corresponding loading instruction of the message to the process of the plug-in
  • the process of the plug-in will execute the full-text loading of the message.
  • inter-process communication The main purpose of inter-process communication is to realize data sharing and information exchange between cooperating processes within the same computer system. Two or more parties involved in the communication realize the transfer of data between processes by sending or receiving messages, thereby completing data communication. Two or more processes that communicate with each other, the process that sends data can be called the sending process, and the process that receives data can be called the receiving process. A process running in the user layer 101 is called a process running in the user mode. Inter-process communication is usually triggered in user mode, but the process of inter-process communication requires the kernel 102 to be implemented.
  • the kernel 102 is an operating system (operating system, OS) responsible for managing key resources, providing system call entry for user-mode processes and providing services in the kernel, such as inter-process communication, page table management, and interrupt control.
  • OS operating system
  • the sending process can apply for the service of sending data through system calls
  • the receiving process can apply for the service of receiving data through system calls.
  • the compiler 103 may provide compilation services in the process of inter-process communication.
  • the compiler may write the communication information into the register group, and may write the data to be transmitted in the inter-process communication into the register group, and so on.
  • the hardware layer 104 includes hardware resources on which the kernel 102 operates, such as processors, memory, memory management unit (MMU), and input/output (I/O) devices.
  • the processor may include a register group, and the register group may include various types of registers, such as stack frame registers, general-purpose registers, and non-volatile (callee-saved) registers.
  • the stack frame register is used to store the address of the stack memory
  • the general-purpose register can be used to store the target data to be transmitted in inter-process communication, and can also be used to store other information, such as: general information (ipcinfo), etc.
  • non-volatile registers can be used It is used to store some parameters other than the target data, for example: the non-volatile register can also save the communication information.
  • the MMU is a type of computer hardware responsible for processing memory access requests from the central processing unit (CPU). Its functions include translation of virtual addresses to physical addresses, memory protection, and control of CPU caches.
  • processes include threads.
  • the process is the running entity of the program and the basic unit for the system to allocate and call resources.
  • a thread is the smallest unit of program scheduling. There may be multiple threads in the same process. They have their own scheduling attributes and share the resources of the process.
  • a process control block PCB
  • TCB thread control block
  • the PCB is a data structure set in the OS to manage the process, and the PCB will record the relevant information of the process running.
  • a TCB can be a subset of a PCB, or it can be understood that a PCB includes multiple TCBs, and each TCB corresponds to a thread.
  • Different threads in a sending process can communicate with different threads in the same receiving process, or with threads in different receiving processes.
  • a thread in a receiving process can also communicate with threads in multiple different sending processes. Therefore, inter-process communication can also be understood as communication between threads in different processes.
  • the sending process needs a TCB to support this communication, and the TCB may include an activation entity (activation) and a scheduling entity.
  • the execution entity is a part of the thread, and contains the information of the registers required for the thread to run, the information of the stack memory, the information of the memory block, etc.
  • the scheduling entity is also a part of the thread, and contains scheduling-related information such as the priority required for the thread to run.
  • the receiving process needs to provide an execution entity to support this communication.
  • the method for inter-process communication includes two situations.
  • the first is: communication between two processes, that is, one sending process and one receiving process.
  • the second case including multi-level inter-process communication, that is, one sending process and multiple receiving processes, this case can also be called inter-process communication of multi-level IPC sequence.
  • a plurality of includes “two”.
  • “Plurality” can also be described as "at least two”. The two cases are introduced separately below.
  • the method for inter-process communication can be implemented by a device having a computer system, such as a terminal device. Specifically, it can be It is a process in which one or more processors in a computer system implement the above-mentioned inter-process communication.
  • the first communication between two processes, that is, a sending process and a receiving process.
  • an embodiment of the method for inter-process communication provided by the embodiment of the present application includes:
  • This step 201 may be performed in the user mode.
  • the first data is included in the target data to be sent by the sending process to the first receiving process.
  • the calling convention is a regulation related to data writing and data reading, where "data” in “data writing” and “data reading” includes the values in various types of registers, as well as the requirements for inter-process communication. passed data.
  • the calling convention specifies the order of writing data in the registers and stack memory corresponding to the execution entity of the sending process, and the order of reading data from the registers and stack memory corresponding to the execution entity of the receiving process.
  • the first execution entity is used for the sending process to communicate with the first receiving process.
  • the register group can include multiple types of registers, such as stack frame registers, general-purpose registers, and non-volatile registers.
  • the stack frame register is used to store the address of the stack memory.
  • General purpose registers can be used to store some or all of the target data.
  • Stack memory can be used to store some or all of the target data.
  • the first memory block may also store some or all of the target data.
  • Communication information is a concept newly proposed in this embodiment of the present application, and the communication information may include a first value, where the first value is used to indicate the data amount of the first data.
  • a part of the target data may also be stored in the general-purpose register, and this part of data may be referred to as second data.
  • second data When there is second data, according to the calling convention, the second data is written into the register group of the first execution entity, and the information in the register group of the first execution entity further includes the second data.
  • the communication information may further include a second value, where the second value is used to indicate the data amount of the third data.
  • the target data does not include the second data. If the memory block does not include the third data, the target data is the first data. If the second data is written in the register group, but the third data is not included in the memory block, the target data is the first data plus the second data. If the second data is written in the register group and the third data is also included in the memory block, the target data is the first data plus the second data and the third data.
  • the communication information may also include an identifier of a function for processing the target data, and the function may be a receiving function.
  • the first value and the second value in the general information may be determined by the compiler in the computer system of FIG. 1.
  • the compiler may use the size of the target data and the calling convention in the register group and the The first value is determined according to the requirement for the amount of data written in the stack memory. If the data is large, the data other than the register group and the stack memory can be placed in the first memory block, which should be stored in the second memory block.
  • the amount of data in the memory block can be represented by a second value.
  • the second value should also be included in the communication information, that is, it is generated according to the first value, the second value, and the identifier of the function used to process the target data. the communication information.
  • This step can be implemented by triggering the sending process to trap into the kernel through a system call.
  • the information in the register group includes communication information and the address of the stack memory, and may also include second data, the address of the first memory block, etc.
  • the context of the first execution entity is the information in the register group of the first execution entity stored in the kernel .
  • the register set also includes other information or values, and these information or values will be copied into the context of the first execution entity when the sending process falls into the kernel.
  • the second execution entity may be an execution entity allocated from the resource pool of the execution entity of the first receiving process.
  • the resource pool usually includes multiple execution entities. When the sending process applies for communication with the first receiving process, it can obtain the An execution entity is allocated to the sending process in the resource pool.
  • the address of the stack memory indicates the starting position where the first data is stored in the stack memory, and the first value indicates the data length of the first data. Therefore, according to the address of the stack memory and the first value, it can be stored in the first execution entity.
  • the first data is found in the stack memory, and the first data is copied to the stack memory of the second execution entity in the kernel.
  • the method further includes: writing the second data into the register group of the first execution entity according to the calling convention, and the calling convention is further used to indicate that the second data is in the register group. write order.
  • the above step 202 may include: copying the second data, the communication information and the address of the stack memory in the register group into the context of the first execution entity.
  • the method may further include: copying the context of the first execution entity into the context of the second execution entity; and writing the context of the second execution entity into the register group of the second execution entity.
  • the context of the second execution entity is the information in the register group of the second execution entity stored in the kernel.
  • the third data may also be copied from the first memory block of the first execution entity to the memory block of the second execution entity according to the second value and the address of the first memory block.
  • the first execution entity further includes first page table information
  • the second execution entity further includes second page table information
  • the first page table information and the second page table information are used for the first data to be executed from the first page.
  • the stack memory of the entity is copied to the stack memory of the second execution entity, or the third data is copied from the first memory block of the first execution entity to the memory block of the second execution entity.
  • the first page table information is used to represent the mapping relationship between the virtual address and the physical address of the memory space of the first execution entity.
  • the memory space of the first execution entity includes the stack memory and the first memory block of the first execution entity
  • the second page The table information is used to indicate the mapping relationship between the virtual address and the physical address of the memory space of the second execution entity, where the memory space of the second execution entity includes the stack memory and the memory block of the second execution entity.
  • the process of copying the first data or the third data based on the first page table information and the second page table information may be implemented in the following two ways.
  • the first copy method copy the first data from the stack memory of the user mode to the memory of the kernel based on the information of the first page table, and then copy the first data from the memory of the kernel to the memory of the second execution entity based on the information of the second page table. stack memory.
  • the principle of copying from the first memory block of the first execution entity to the memory block of the second execution entity is also the same, except that the stack memory of the first execution entity is modified to the first memory block of the first execution entity , the stack memory of the second execution entity is modified to the memory block of the second execution entity.
  • the process referring to Figure 3A may include:
  • the address (virtual address) of the stack memory of the first execution entity According to the address (virtual address) of the stack memory of the first execution entity and the mapping relationship between the virtual address and the physical address contained in the first page table information, determine the first physical address corresponding to the address of the stack memory, and then determine the first physical address. a physical memory.
  • the kernel determines the second physical address corresponding to the stack memory of the second execution entity based on the address of the stack memory of the second execution entity and the second page table information, and then according to the length of the first data indicated by the first value , and determine the required second physical memory of the second execution entity.
  • the second copying method map the stack memory of the first execution entity to the first memory of the kernel based on the first page table information, and map the stack memory of the second execution entity to the first memory of the kernel based on the page table information of the second execution entity.
  • Second memory copy the first data from the first memory to the second memory.
  • the principle of copying from the first memory block of the first execution entity to the memory block of the second execution entity is also the same, except that the stack memory of the first execution entity is modified to the first memory block of the first execution entity , the stack memory of the second execution entity is modified to the memory block of the second execution entity.
  • the process referring to Figure 3B may include:
  • the stack memory of the first execution entity is mapped to the first physical memory of the first execution entity
  • the second memory is mapped to the second execution entity.
  • the stack memory of the second execution entity is mapped with the second physical memory of the second execution entity. Therefore, in the virtual form, the first data is copied from the first memory to the second execution entity.
  • Second memory, in physical form, the first data is copied from the first physical memory to the second physical memory.
  • the embodiment of the present application transmits the inter-process communication data through the stack memory. Since the stack memory address always exists in the register group at the sending end, the address of the stack memory does not need to be specially written for the inter-process communication, which can reduce the communication overhead. , and at the receiving end, the data of inter-process communication can be directly read from the stack memory for processing, and there is no need to first read the data of inter-process communication from the memory block and then write it into the stack memory, and then process it. , which further reduces the performance overhead of inter-process communication.
  • the general-purpose register can complete the transfer.
  • the data is used to describe the first data stored in the stack memory.
  • the first value of can be equal to 0.
  • the stack memory, memory block, the first memory and the second memory of the kernel are all logical memory spaces
  • the first physical memory and the second physical memory are hardware storage devices
  • the above description involves the description that the first data is copied from the stack memory of the first execution entity to the stack memory of the second execution entity
  • the third data is copied from the first memory block of the first execution entity to the second execution entity.
  • the description of the memory block, the first data and the third data here can be understood as logical data.
  • the above also involves the description that the first data and the third data are copied from the first physical memory to the second physical memory, where the first data and the third data can be understood as physical data.
  • the application refers to the same piece of data, and the physical data is also replicated synchronously in the process of replicating logical data.
  • the second execution entity plus the scheduling entity of the sending process may also process data by superimposing execution entities, and then return the processing result.
  • the solutions provided by the embodiments of the present application can also perform identity verification on the sending process. The method for inter-process communication provided by the embodiment of the present application is further described below with reference to FIG. 4 .
  • the first execution entity of the sending process includes a linked list node (list node), first configuration information (Curr_Conf), second configuration information (Xact_Conf), and context (UCTX).
  • the second execution entity also includes a linked list node, the first configuration information, the second configuration information and the context.
  • Each execution entity will include the above four parts, but the content included in each part may be different.
  • the linked list node of the first execution entity and the linked list node of the second execution entity are associated by arrows, indicating that the second execution entity is superimposed on the first execution entity. After the second execution entity is superimposed, the first execution entity will enter an inactive state, and the second execution entity will take over the work of the first execution entity.
  • the first execution entity is located in a thread of the sending process, or in a TCB, and the TCB also includes a scheduling entity. After the second execution entity is superimposed on the first execution entity, the TCB includes the second execution entity and the scheduling entity, so that The present application implements a process in which one thread of the sending process runs the content of the second execution entity to perform data processing.
  • the first configuration information will include the identity of the process and the page table information of the process
  • the second configuration information will include the identity of the communication initiating process and the page table information of the communication initiating process.
  • the first configuration information of the first execution entity may include the identifier of the sending process and the first page table information.
  • the location of the second configuration information of the first execution entity may not be used, that is, the second configuration information does not include specific content, or the content in the second configuration information may be the same as the content in the first configuration information.
  • the first configuration information of the second execution entity includes the identifier of the first receiving process and the second page table information.
  • the second configuration information includes the identifier of the sending process and the first page table information.
  • the second configuration information includes the identifier of the process that initiated the multi-level IPC sequence, that is, the identifier of the first process on the entire IPC sequence.
  • the context of the first execution entity includes information in the register group of the first execution entity.
  • the context of the second execution entity includes information in the register set of the second execution entity.
  • the first execution entity may be an execution entity in the thread control block 1, and the thread control block 1 further includes a scheduling entity, and the scheduling entity includes the scheduling priority of the sending task of the sending process this time, and the sending The state the process is in.
  • the thread control block 1 may be one of multiple thread control blocks of the sending process, and the sending process may also include multiple thread control blocks such as thread control block 2 to thread control block X, where X is an integer greater than 2.
  • the second execution entity may be an execution entity in a resource pool of execution entities of the first receiving process, and the resource pool further includes other execution entities, such as execution entity M to execution entity N.
  • the process from the sending process running in the user mode to when the first data is copied to the stack memory of the second execution entity in the kernel can refer to the aforementioned FIG. 2 , FIG. 3A and FIG.
  • the corresponding content of the embodiment section corresponding to 3B should be understood.
  • the follow-up content is introduced below.
  • the process of performing entity superposition can be implemented by means of a linked list.
  • the second execution entity switches to the user mode.
  • the thread control block of the sending process includes the second execution entity and the original scheduling entity, and the second execution entity will switch to the user mode. Entering the user mode from the kernel, the content in the context of the second execution entity will be written into the register group of the second execution entity in the user mode. From the description of the first page table information and the second page table information, it can be known that the first data can be copied to the stack memory of the second execution entity through the first copy method or the second copy method. The third data is included, and the third data is also copied to the memory block of the second execution entity through the first copying method or the second copying method.
  • the communication information will be copied from the register set of the first execution entity to the context of the first execution entity with the system call. After entering the kernel, the communication information will be copied to the context of the second execution entity along with the context of the first execution entity. The context is then copied to the register file of the second execution entity as the second execution entity switches to user mode.
  • the identifier of the function used to process the target data will also be copied to the register group of the second execution entity.
  • the identification of the function in the register group of the call the function, and process all or part of the target data to obtain the processing result.
  • registers, stack memory, and memory blocks transfer data at different speeds, when processing target data, you can wait for all target data to arrive at the second execution entity before processing, or process some data that first arrives at the second execution entity.
  • the second configuration information includes the identifier of the sending process.
  • the identifier of the sending process is written into the context of the second execution entity.
  • the identifier of the sending process will also be written into the register group of the second execution entity, so that the receiving end can read the identifier of the sending process from the register group, and then perform authentication.
  • the principle of the list is understood.
  • the safe process will be registered in the white list in advance. The receiving end can find out whether the identifier is in the white list according to the identifier of the sending process. If it is in the white list, it can confirm that the sending process is safe.
  • the second execution entity is used to transmit the identifier of the sending process, so as to authenticate the sending process and improve the security of inter-process communication sex.
  • the second execution entity can be released, the original first execution entity continues to perform the work of the sending process, receives the processing result returned by the second execution entity after processing the target data, and completes an IPC communication.
  • a thread of the sending process borrows the second execution entity of the first receiving process to process the target data to obtain a processing result. It can be seen that this possible implementation provides a different form of inter-process communication.
  • the first execution entity of the sending process includes a register group, and the register group includes R0 -R3 four general-purpose registers, according to the calling convention, the first execution entity R0-R3 four general-purpose registers can be used to transmit communication information and target data, this register group can also include other registers, such as stack frame registers, Figure 5 not all shown.
  • the register group of the second execution entity includes four general-purpose registers R0-R3, R4 may be a non-volatile register, and the register group may also include other registers, such as stack frame registers, which are not all shown in FIG. 5 .
  • the communication information can be encoded using a 64-bit unsigned integer in the user mode of the sending process and stored in the R0 and R1 registers.
  • the 64 bits here are just examples, and the number of bits of the communication information is not limited in this application.
  • the bits of the communication information from low to high are: 14 bits: the data amount (second value) of the data sent by the sending process through the memory block.
  • a multi-level IPC sequence, or a sequence with only one sending process and one receiving process is referred to as a transaction.
  • a transaction opened for the first time refers to a new transaction. If the subsequent IPC is performed on the basis of the existing transaction, then the IPC in this case indicates that the current transaction is forwarded.
  • 11 bits the identifier of the function that the user processes the target data; 5 bits: the amount of data sent by the sending process through the stack memory (the amount of data here represents the 4 identified by the value formed by the 5-bit binary (that is, the maximum 32). A multiple of the size in bytes), the amount of data can also be described as the size of the data.
  • 33 bits reserved for extended use.
  • the address of the stack memory can be passed through the stack frame register in the register bank, which is not shown in this FIG. 5 .
  • pass-through register R3 vacant in the general-purpose register, and the pass-through register R3 can be used to transmit a part of the target data, that is, the second data described above.
  • the second data may be the first data in the target data.
  • the sending process and the first receiving process can respectively use the memory of up to 128 bytes represented by the above 5 bits to send and receive data passed through the stack memory.
  • the 128 bytes is also an example, and the amount of data to be transferred by using the stack memory can be set according to requirements.
  • the sending process is trapped into the kernel from user mode through a system call.
  • each process corresponds to a structure CNode for recording authorization information.
  • Each CNode has a unique identifier cnode_idx represented by a 32-bit unsigned integer.
  • cnode_idx is used to represent the identifier of the process. Can be used to authenticate the identity of the sending process.
  • the first configuration information (Curr_Conf) of the first execution entity records the cnode_idx of the first execution entity and the address space information of the first execution entity, and the address space information is used to indicate the memory of the first execution entity in the kernel.
  • the address space can be understood by referring to the table information on the first page.
  • the second configuration information (Xact_Conf) of the first execution entity records the identity and address space information of the process where the transaction initiator is located. Because in this scenario, only one sending process and one receiving process are involved, the second configuration information here The content of is empty, which can also be the same as the content of the first configuration information.
  • the second execution entity uses a 64-bit unsigned integer to encode the cnode_idx of the process where the previous execution entity is located, and stores it in the R0 register and the R1 register. Because in this scenario, only one sending process and one receiving process are involved, so, R0 and R1 The representation of the process in the register can be the same.
  • the R2 register in the second execution entity is reserved (the reserved register can be used to transmit user-mode identification information pre-set for the sending process by the first receiving process, and the user-mode identification information can be used to speed up data processing).
  • the reception of the second data starts through the general register R3 in the second execution entity.
  • the first data is received through the stack memory in the second execution entity.
  • the third data is received through the memory block in the second execution entity.
  • the communication information can be stored in the register R4. If the communication information uses the upper 32 reserved bits, R4 and R5 are required to store the communication information.
  • the second execution entity comes from the resource pool of the execution entity of the first receiving process.
  • flexibility management of adding or deleting execution entities in the resource pool is also performed. This process can be understood with reference to FIG. 6 .
  • a listening thread can be set in the resource pool of the execution entity, and the listening thread is used to monitor the allocation or release of execution entities in the resource pool, or to monitor the number of remaining execution entities in the resource pool.
  • the remaining execution entity can also be understood as the execution entity that can be used.
  • a waterline and a waterline are set in the resource pool.
  • the lower line is used to indicate the lower limit of the number of available execution entities in the resource pool.
  • the upper waterline is used to indicate the upper limit of the number of available execution entities in the resource pool.
  • the listening thread detects that an execution entity is allocated, for example, in the above-mentioned IPC process, the second execution entity is allocated from the resource pool of the execution entity. If the number of available execution entities in the resource pool after subtracting the second execution entity is lower than the lower line, a new execution entity is created in the resource pool. For example, if the number of available execution entities remaining in the resource pool is less than M+1, one or more execution entities will be created to supplement the number of execution entities in the resource pool. In this way, by properly setting the waterline, when the sending process applies for the IPC service, the first receiving process has execution entities that can provide services, and the number of available execution entities is controllable, avoiding the problem of reliability degradation caused by blocking.
  • the listening thread detects that an execution entity is released, for example, after obtaining the processing result, the second execution entity is released; if the number of available execution entities after adding the second execution entity to the resource pool is higher than the waterline, then Delete at least one execution entity from the resource pool. For example, after releasing the second execution entity, and the number of execution entities in the resource pool exceeds N, one or more execution entities may be deleted. In this way, by setting the waterline reasonably, you can control the excessive memory overhead caused by too many available execution entities.
  • the second case the communication between multiple processes, that is, one sending process and multiple receiving processes, this situation can also be called the inter-process communication of multi-level IPC sequence.
  • the above-mentioned first receiving process is located in a multi-level IPC sequence, and the multi-level IPC sequence further includes a second receiving process.
  • the second receiving process is located after the first receiving process.
  • the two-level receiving process of the first receiving process and the second receiving process is used as an example for illustration.
  • a multi-level IPC sequence can include multiple receiving processes. No matter how many receiving processes there are, every two The principles of IPC between two consecutive receiving processes are the same, and the IPC process of each two consecutive receiving processes can be understood by referring to the processes of the foregoing sending process and the first receiving process.
  • the difference between the multi-level IPC sequence and the aforementioned two-level IPC process is that each intermediate process will pass the identifier of the first process, and the page table information of the first process is used to identify the identifier passed to the last process through the second memory block.
  • the second receiving process includes a third execution entity
  • the third execution entity includes not only the identifier of the previous second receiving process and the third page table information, but also the identifier of the sending process and the first page table. information.
  • the sending process and the first receiving process transmit the first data, the second data and the third data to the first receiving process through the general-purpose register, the stack memory and the first memory block, respectively, in the manner described in the foregoing embodiments.
  • the sending process transmits the fourth value, the address of the second memory block, the identifier of the sending process and the first page table information through the second execution entity of the first receiving process.
  • the third execution entity performs identity verification according to the identity of the sending process, and according to the address of the second memory block of the first execution entity, the first page table information of the first execution entity, and the third value, from the first execution entity
  • the fourth data is copied from the second memory block to the memory block of the third execution entity.
  • receiving processes may also be included between the first receiving process and the second receiving process, no matter if one or more intermediate processes are included between the sending process and the second receiving process, in this application, the sending process to the first receiving process
  • the second receiving process only needs to transmit the address of the second memory block, the data amount of the fourth data and the first page table information, and the second receiving process only needs to copy the fourth data once, which greatly improves the performance of data transmission.
  • the apparatus may be a computer device.
  • an embodiment of the apparatus 40 for inter-process communication provided by the embodiment of the present application includes:
  • the first processing unit 401 is configured to write the communication information into the register group of the first execution entity of the sending process according to the calling convention, and write the first data of the target data into the stack memory of the first execution entity, and the communication information includes: The first value, the first value is used to indicate the data amount of the first data, the target data is the data to be sent by the sending process to the first receiving process, the calling convention is used to indicate the writing order of the communication information in the register group, and the first value The order in which data is written in stack memory.
  • the second processing unit 402 is configured to copy the information in the register group of the first execution entity into the context of the first execution entity, where the information in the register group includes the communication information and the address of the stack memory.
  • the third processing unit 403 is configured to copy the first data from the stack memory of the first execution entity to the stack of the second execution entity of the first receiving process according to the first value in the context of the first execution entity and the address of the stack memory in memory.
  • the inter-process communication data is transmitted through the stack memory. Since the stack memory address always exists in the register group at the sending end, the address of the stack memory does not need to be specially written for the inter-process communication, which can reduce the Communication overhead, and at the receiving end, the data of inter-process communication can be directly read from the stack memory for processing, and there is no need to read the data of inter-process communication from the memory block first, write it into the stack memory, and then processing, which further reduces the performance overhead of inter-process communication.
  • the target data further includes second data
  • the first processing unit 401 is further configured to, before copying the information in the register group of the first execution entity into the context of the first execution entity, according to the calling convention, to The second data is written into the register group of the first execution entity, and the calling convention is further used to indicate the writing sequence of the second data in the register group.
  • the second processing unit 402 is configured to copy the second data, the communication information and the address of the stack memory in the register group to the context of the first execution entity.
  • the third processing unit 403 is further configured to copy the context of the first execution entity into the context of the second execution entity; and write the context of the second execution entity into the register group of the second execution entity.
  • the target data further includes third data
  • the communication information further includes a second value
  • the second value is used to indicate the data amount of the third data stored in the first memory block of the first execution entity.
  • the third processing unit 403 is further configured to copy the third data from the memory block of the first execution entity to the memory block of the second execution entity according to the second value and the address of the first memory block.
  • the first execution entity further includes first page table information
  • the second execution entity further includes second page table information
  • the first page table information and the second page table information are used for the first data to be executed from the first page.
  • the stack memory of the entity is copied to the stack memory of the second execution entity, or the third data is copied from the first memory block of the first execution entity to the memory block of the second execution entity.
  • the third processing unit 403 is further configured to superimpose the second execution entity on the first execution entity, and write the context of the second execution entity into the register group of the second execution entity, wherein the second execution entity
  • the context of the entity includes the data in the context of the first execution entity; according to the calling convention, all or part of the target data is read from the register set of the second execution entity and the stack memory of the second execution entity, and all or part of the target data is processed. processing to obtain the processing result, and the calling convention is also used to indicate the reading sequence of the register group and the stack memory of the second execution entity.
  • the third processing unit 403 is configured to call the function according to the identifier of the function in the register group of the second execution entity, and process all or part of the target data to obtain a processing result.
  • the first execution entity further includes the identifier of the sending process
  • the third processing unit 403 is further configured to write the identifier of the sending process into the context of the second execution entity before switching the second execution entity to the user state.
  • the identity of the sending process is used to verify the identity of the sending process after the second execution entity switches to the user mode.
  • the first processing unit 401 is further configured to determine the first value according to the data volume of the target data and the calling convention; and use the first value to generate communication information.
  • the second processing unit 402 is further configured to allocate the second execution entity from the resource pool of the execution entity; if the number of available execution entities after subtracting the second execution entity from the resource pool Create a new execution entity in , and the lower line is used to indicate the lower limit of the number of available execution entities in the resource pool.
  • the second processing unit 402 is further configured to release the second execution entity after obtaining the processing result; if the number of available execution entities after adding the second execution entity to the resource pool is higher than the upper At least one execution entity is deleted from the pool, and the upper waterline is used to indicate the upper limit of the number of available execution entities in the resource pool.
  • the first receiving process is located in a multi-level IPC sequence, and the multi-level IPC sequence further includes a second receiving process, and in the communication sequence with the sending process, the second receiving process is located after the first receiving process; the third processing unit 403, which is further configured to pass the address of the second memory block of the first execution entity, the first page table information of the first execution entity, and the third value to the first execution entity of the second receiving process through the second execution entity of the first receiving process.
  • the third value is used to indicate the data amount of the fourth data sent by the sending process to the second receiving process; according to the address of the second memory block of the first execution entity, the first page table information of the first execution entity, and a third value, copying the fourth data from the second memory block of the first execution entity to the memory block of the third execution entity.
  • the third processing unit 403 is further configured to transmit the identifier of the sending process to the third executing entity of the second receiving process through the second executing entity of the first receiving process, where the identifier of the sending process is used by the third executing entity to verify the identity of the sending process .
  • the apparatus 40 for inter-process communication described above can be understood by referring to the corresponding description in the foregoing method embodiment section, which will not be repeated here.
  • FIG. 9 is a schematic diagram of a possible logical structure of a computer device 50 provided in an embodiment of the present application.
  • Computer device 50 includes: processor 501 , communication interface 502 , memory 503 , and bus 504 .
  • the processor 501 , the communication interface 502 and the memory 503 are connected to each other through a bus 504 .
  • the processor 501 is configured to control and manage the actions of the computer device 50.
  • the processor 501 is configured to execute steps 201 to 205 in the method embodiments of FIG. 2 to FIG. 7, and the communication interface 502 Used to support computer equipment 50 to communicate.
  • the memory 503 is used for storing program codes and data of the computer device 50 .
  • the processor 501 may be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array, or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It may implement or execute the various exemplary logical blocks, modules and circuits described in connection with this disclosure.
  • the processor 501 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, and the like.
  • the bus 504 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (Extended Industry Standard Architecture, EISA) bus or the like.
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture
  • a computer-readable storage medium is also provided, where computer-executable instructions are stored in the computer-readable storage medium.
  • the processor of the device executes the computer-executable instructions
  • the device executes the above-mentioned FIG. 2 to The method of inter-process communication in FIG. 7 .
  • a computer program product includes computer-executable instructions, and the computer-executable instructions are stored in a computer-readable storage medium; when a processor of a device executes the computer-executable instructions , the device executes the above-mentioned methods for inter-process communication in FIG. 2 to FIG. 7 .
  • a chip system is further provided, the chip system includes a processor, and the processor is used for the apparatus for supporting inter-process communication to implement the above-mentioned methods for inter-process communication in FIG. 2 to FIG. 7 .
  • the chip system may further include a memory, which is used for storing necessary program instructions and data of the device for inter-process communication.
  • the chip system may be composed of chips, or may include chips and other discrete devices.
  • Units described as separate components may or may not be physically separated, and components shown as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the embodiments of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the functions, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer-readable storage medium.
  • the technical solutions of the embodiments of the present application can be embodied in the form of software products in essence, or the parts that make contributions to the prior art or the parts of the technical solutions, and the computer software products are stored in a storage medium , including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in the embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program codes .

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Abstract

一种进程间通信的方法，该方法应用于计算机系统，包括：根据调用约定，将发送进程与接收进程之间要传递的数据写入到发送进程的第一执行实体的寄存器组和栈内存中，并在寄存器组中写入该栈内存的地址和表示该栈内存中数据的数据量的第一值，然后通过接收进程的第二执行实体根据该栈内存的地址和相应的第一值将该要传递的数据从第一执行实体的栈内存复制到第二执行实体的栈内存。所述方法通过寄存器组和栈内存传递数据，提高了IPC的通信性能，另外，还提供了多级IPC序列的进程间通信的方案，多级IPC序列的中间进程只需要转发内存块的地址和数据长度，就可以实现跨进程拷贝，提高了多级IPC的通信性能。

Description

一种进程间通信的方法及装置
本申请要求于2020年7月30日提交中国专利局、申请号为202010753141.6、发明名称为“一种进程间通信的方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，具体涉及一种进程间通信的方法及装置。
背景技术
随着计算机技术的发展，多个进程之间，以及多个进程与同一个进程之间的通信需求增大。当前通常采用基于通信信道的发送(send)-接收(recv)语义模型实现进程间消息的发送与接收。
内核通过通信信道提供进程间通信(interprocess communication，IPC)服务，通信信道由接收进程创建并授权给发送进程。发送进程在用户态根据需求准备好需要发送的数据，然后发送进程和接收进程分别使用内存块(buffer)发送和接收数据，在发送过程中，需要发送进程对数据进行序列化，在接收过程需要对数据进行反序列化，导致进程间通信过程中存在额外的性能开销。
发明内容
本申请提供一种进程间通信的方法，用于降低进程间通信(interprocess communication，IPC)的性能开销。本申请还提供了相应的装置、计算机可读存储介质、计算机程序产品等。
本申请第一方面提供一种进程间通信的方法，该方法应用于计算机系统，该方法包括：根据调用约定，将通信信息写入发送进程的第一执行实体的寄存器组中，将目标数据的第一数据写入第一执行实体的栈内存中，该通信信息包括第一值，第一值用于指示第一数据的数据量，目标数据为发送进程要发送给第一接收进程的数据，调用约定用于指示通信信息在寄存器组中的写入顺序，以及第一数据在栈内存中的写入顺序；将第一执行实体的寄存器组中的信息复制到第一执行实体的上下文中，寄存器组中的信息包括通信信息和栈内存的地址，第一执行实体的上下文为内核中存储的第一执行实体的寄存器组中的信息；根据第一执行实体的上下文中的第一值和栈内存的地址，从第一执行实体的栈内存复制第一数据到第一接收进程的第二执行实体的栈内存中，第二执行实体用于第一接收进程与发送进程通信。
该第一方面中，调用约定(calling convension)是应用在x86、arm等架构下的与数据写入和数据读取相关的规定，该处“数据写入”和“数据读取”中的“数据”包括各类型寄存器中的数值，以及进程间通信要传递的数据。该调用约定明确了数据在发送进程的执行实体对应的寄存器和栈内存中的写入顺序，以及从接收进程的执行实体对应的寄存器和栈内存中读取数据的顺序。
需要说明的是，寄存器组包括通用寄存器，该通用寄存器也可以用于存储发送进程与第一接收进程要传递的目标数据中的全部或部分数据。若要传递的目标数据的数据量很小的情况下，通用寄存器就可以完成传递，这种情况下，用于描述栈内存中存储的第一数据 的第一值可以等于0。通信信息(ipcinfo)会写入到寄存器组中，寄存器组中还可以包括栈帧寄存器，该栈帧寄存器中会写入栈内存的地址。
执行实体(activation)是线程控制块(thread control block，TCB)中的一部分，TCB中还包括调度实体。TCB是一种数据结构，用于存储与相应线程相关的信息。一个进程可以包括多个线程，也会包括一个或多个TCB，第一执行实体位于发送进程的一个TCB中，第二执行实体是第一接收进程的执行实体。进程间通信需要从用户态陷入内核，在内核中完成数据传递。所以，上述触发发送进程从用户态陷入内核后，在内核中根据第一执行实体的上下文中的第一值和栈内存的地址，从第一执行实体的栈内存复制第一数据到第二执行实体的栈内存中，就可以完成数据的传递。
由该第一方面可知，基于调用约定，通过栈内存传递进程间通信数据，在发送端因为栈内存地址一直在寄存器组中存在，不需要为进程间通信特别写入该栈内存的地址，可以降低通信开销，而且在接收端可以直接从栈内存中读取进程间通信的数据进行处理，不需要先将进程间通信的数据从内存块中先读取出来再写入到栈内存中，然后再进行处理，这样进一步降低了进程间通信的性能开销。
在第一方面的一种可能的实现方式中，目标数据还包括第二数据，在将第一执行实体的寄存器组中的信息复制到第一执行实体的上下文中之前，该方法还包括：根据调用约定，将第二数据写入第一执行实体的寄存器组中，调用约定还用于指示第二数据在寄存器组中的写入顺序；上述步骤：将第一执行实体的寄存器组中的信息复制到第一执行实体的上下文中包括：将寄存器组中的第二数据、通信信息和栈内存的地址复制到第一执行实体的上下文中。该方法还包括：将第一执行实体的上下文复制到第二执行实体的上下文中；将第二执行实体的上下文写入第二执行实体的寄存器组中。
该种可能的实现方式中，发送进程要发送给第一接收进程的目标数据包括第一数据和第二数据两部分，第一数据通过栈内存发送，第二数据通过寄存器组发送。通过寄存器组发送第二数据，可以提高第二数据的传输速度，提高了进程间通信的性能。
应理解的是，在其他实现方式中，发送进程要发送给第一接收进程的目标数据可以全部通过栈内存发送，或全部通过寄存器组发送。
在第一方面的一种可能的实现方式中，目标数据还包括第三数据，通信信息还包括第二值，第二值用于指示存储在第一执行实体的第一内存块中第三数据的数据量，该方法还包括：将第一内存块的地址写入第一执行实体的寄存器组中，将第三数据写入第一执行实体的第一内存块中；根据第二值，以及第一内存块的地址，从第一执行实体的内存块复制第三数据到第二执行实体的内存块中。
该种可能的实现方式中，目标数据较大的情况下，为了避免过多占用栈内存，可以通过第一内存块再传输一部分数据，如：第三数据。可以将第三数据的数据量(也就是第二值)携带在通信信息中通知给第一接收进程，这样在保证性能开销的情况下，也有利于大数据的传输。
在第一方面的一种可能的实现方式中，第一执行实体中还包括第一页表信息，第二执行实体中还包括第二页表信息，第一页表信息和第二页表信息用于第一数据从第一执行实 体的栈内存复制到第二执行实体的栈内存，或第三数据从第一执行实体的第一内存块复制到第二执行实体的内存块。
上述基于第一页表信息和第二页表信息实现数据的复制过程可以包括如下两种：
第一种复制方式：基于第一页表信息将第一数据从用户态的栈内存复制到内核的内存，再基于第二页表信息将第一数据从内核的内存复制到第二执行实体的栈内存。对于第三数据，从第一执行实体的第一内存块复制到第二执行实体的内存块的原理也是相同的。
第二种复制方式：基于第一页表信息将第一执行实体的栈内存映射到内核的第一内存，基于第二执行实体的页表信息将第二执行实体的栈内存映射到内核的第二内存，将第一数据从第一内存复制到第二内存。对于第三数据，从第一执行实体的第一内存块复制到第二执行实体的内存块的原理也是相同的。
在第一方面的一种可能的实现方式中，该方法还包括：在第一执行实体上叠加第二执行实体，并将第二执行实体的上下文写入到第二执行实体的寄存器组中，其中，第二执行实体的上下文包括第一执行实体的上下文中的数据。根据调用约定从第二执行实体的寄存器组和第二执行实体的栈内存中读取全部或部分目标数据，并对全部或部分目标数据进行处理，以得到处理结果，调用约定还用于指示对第二执行实体的寄存器组和栈内存的读取顺序。
该种可能的实现方式中，可以通过链表的方式在第一执行实体上叠加第二执行实体，叠加第二执行实体后，该第一执行实体会进入非活跃状态，由第二执行实体来接替第一执行实体的工作，叠加在第一执行实体上的第二执行实体会被切换到第二执行实体的用户态，随着第二执行实体从内核到用户态的切换，会将第二执行实体的上下文写入到第二执行实体的寄存器组中，这样第二执行实体就可以在用户态读取目标数据并进行处理，从而得到处理结果。另外，因为寄存器、栈内存和内存块传递数据的速度不同，在处理目标数据时可以等待全部目标数据都到达第二执行实体后再处理，也可以针对先到达第二执行实体的部分数据先进行处理。需要说明的是，本申请的方案中，第一执行实体位于发送进程的一个线程，或者一个TCB中，该TCB还包括调度实体，在第二执行实体叠加到第一执行实体后，该TCB就包括第二执行实体和该调度实体，这样本申请实现了发送进程的一个线程借用第一接收进程的第二执行实体进行目标数据处理，得到处理结果。可见，该种可能的实现方式提供了一种不同的进程间通信的形式。
在第一方面的一种可能的实现方式中，通信信息还包括用于处理目标数据的函数的标识；上述步骤：对全部或部分目标数据进行处理，以得到处理结果，包括：根据第二执行实体的寄存器组中的函数的标识，调用函数，对全部或部分目标数据进行处理，以得到处理结果。
该种可能的实现方式中，在通信信息中传递函数的标识，这样，可以确保发送进程借用第一接收进程的资源后也可以准确调用到用于目标数据处理的函数，提高了数据处理的准确度。
在第一方面的一种可能的实现方式中，第一执行实体中还包括发送进程的标识，该方法还包括：将发送进程的标识写入第二执行实体的上下文中，发送进程的标识用于第二执 行实体验证发送进程的身份。
该种可能的实现方式中，将发送进程的标识写入第二执行实体的上下文中，在第二执行实体切换到用户态的过程中，该发送进程的标识也会写入第二执行实体的寄存器组中，这样，在接收端就可以从寄存器组中读取发送进程的标识，进而进行身份验证，该身份验证的过程可以参考白名单的原理进行理解，安全的进程都会提前注册到白名单中，接收端可以根据该发送进程的标识查找该标识是否在白名单中，若在白名单中，则可以确认该发送进程是安全的进程，这样，该种可能的实现方式中，在采用执行实体执行进程间通信的过程中借用第二执行实体传递了发送进程的标识，从而对发送进程进行身份验证，提高了进程间通信的安全性。
在第一方面的一种可能的实现方式中，该方法还包括：根据目标数据的数据量，以及调用约定，确定第一值；使用第一值，生成通信信息。
该种可能的实现方式中，在使用调用约定，将通信信息写入发送进程的第一执行实体的寄存器组中之前，可以根据目标数据的数据量，先确定要写入栈内存中第一数据的数据量，也就是第一值，当然，如果目标数据较大，还需要使用内存块传递数据，可以再确定出要写入内存块中第三数据的数据量，也就是第二值，然后将该第一值和第二值都放入该通信信息中。这样，就可以通过通信信息向第一接收进程通知该目标数据在栈内存和内存块中的数据量，进而在第一接收进程端从栈内存中读取相应的第一数据，从内存块中读取相应的第三数据进行数据处理。
在第一方面的一种可能的实现方式中，该方法还包括：从执行实体的资源池分配第二执行实体；若资源池中减掉第二执行实体后可用执行实体的数量低于下水线，则在资源池中创建新的执行实体，下水线用于表示资源池中可用执行实体的数量下限。
该种可能的实现方式中，通过合理设置下水线，可以使得发送进程申请IPC服务时，第一接收进程有执行实体可以提供服务，且可用执行实体数量可控，避免了因发送进程阻塞导致的可靠性下降问题。
在第一方面的一种可能的实现方式中，该方法还包括：在得到处理结果后，释放第二执行实体；若资源池中加上第二执行实体后可用执行实体的数量高于上水线，则从资源池中删除至少一个执行实体，上水线用于表示资源池中可用执行实体的数量上限。
该种可能的实现方式中，通过合理设置上水线，可以控制生成过多的执行实体，可以避免因执行实体过多而导致过大的内存开销。
在第一方面的一种可能的实现方式中，第一接收进程位于多级IPC序列中，多级IPC序列还包括第二接收进程，在与发送进程的通信顺序上，第二接收进程位于第一接收进程之后；该方法还包括：通过第一接收进程的第二执行实体传递第一执行实体的第二内存块的地址，第一执行实体的第一页表信息，以及第三值到第二接收进程的第三执行实体，第三值用于指示发送进程发送给第二接收进程的第四数据的数据量；根据第一执行实体的第二内存块的地址，第一执行实体的第一页表信息，以及第三值，从第一执行实体的第二内存块中复制第四数据到第三执行实体的内存块中。
该种可能的实现方式中，在多级IPC序列中，当较大数据需要多级传递时，该种可能的 实现方式中只需要各级中间进程(如：第一接收进程)的执行实体中记录发送进程的第一页表信息、第一执行实体的第二内存块的地址和第四数据的数据量。这样，从发送进程到第二接收进程的第四数据的传递只需基于发送进程和第二接收进程页表信息做跨进程拷贝。需要说明的是，第一接收进程和第二接收进程之间还可以包括其他接收进程，无论从发送进程到第二接收进程之间包括一个或多个中间进程，本申请中从发送进程到第二接收进程只需要传递第二内存块的地址、第四数据的数据量以及第一页表信息，第二接收进程只需要进行一次对第四数据的跨进程拷贝，大大提高了数据传输的性能。
在第一方面的一种可能的实现方式中，该方法还包括：通过第一接收进程的第二执行实体传递发送进程的标识到第二接收进程的第三执行实体，发送进程的标识用于第三执行实体回到用户态后验证发送进程的身份。
该种可能的实现方式中，在进程间通信时，第二接收进程能够直接读取内核传递的发送进程的标识，进而进行身份验证，提高了进程间通信的安全性。
本申请第二方面提供一种进程间通信的装置，该进程间通信的装置具有实现上述第一方面或第一方面任意一种可能实现方式的方法的功能。该功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的模块，例如：处理单元。
本申请第三方面提供一种计算机设备，该计算机设备包括至少一个处理器、存储器、输入/输出(input/output，I/O)接口以及存储在存储器中并可在处理器上运行的计算机执行指令，当计算机执行指令被处理器执行时，处理器执行如上述第一方面或第一方面任意一种可能的实现方式的方法。
本申请第四方面提供一种存储一个或多个计算机执行指令的计算机可读存储介质，当计算机执行指令被处理器执行时，处理器执行如上述第一方面或第一方面任意一种可能的实现方式的方法。
本申请第五方面提供一种存储一个或多个计算机执行指令的计算机程序产品，当计算机执行指令被处理器执行时，处理器执行如上述第一方面或第一方面任意一种可能的实现方式的方法。
本申请第六方面提供了一种芯片系统，该芯片系统包括至少一个处理器，至少一个处理器用于支持进程间通信的装置实现上述第一方面或第一方面任意一种可能的实现方式中所涉及的功能。在一种可能的设计中，芯片系统还可以包括存储器，存储器，用于保存进程间通信的装置必要的程序指令和数据。该芯片系统，可以由芯片构成，也可以包含芯片和其他分立器件。
本申请实施例，基于调用约定，通过栈内存传递进程间通信数据，在发送端因为栈内存地址一直在寄存器组中存在，不需要为进程间通信特别写入该栈内存的地址，可以降低通信开销，而且在接收端可以直接从栈内存中读取进程间通信的数据进行处理，不需要先将进程间通信的数据从内存块中先读取出来再写入到栈内存中，然后再进行处理，这样进一步降低了进程间通信的性能开销。而且，本申请在多级IPC序列的通信过程中，不需要通过中间进程多级传递数据，只需一次跨进程复制就可以完成多级IPC序列的数据传输， 大大降低了通信开销，提高了进程间通信的性能。
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图3B是本申请实施例提供的进程间通信的方法的另一实施例示意图；
图4是本申请实施例提供的进程间通信的方法的另一实施例示意图；
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图6是本申请实施例提供的进程间通信的方法的另一实施例示意图；
图7是本申请实施例提供的进程间通信的方法的另一实施例示意图；
图8是本申请实施例提供的进程间通信的装置的一实施例示意图；
图9是本申请实施例提供的计算机设备的一实施例示意图。
具体实施方式
下面结合附图，对本申请的实施例进行描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。本领域普通技术人员可知，随着技术的发展和新场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
本申请实施例提供本申请实施例提供一种进程间通信的方法，用于降低进程间通信(interprocess communication，IPC)的性能开销。本申请还提供了相应的装置、计算机可读存储介质、计算机程序产品等。以下分别进行详细说明。
本申请实施例提供的进程间通信的方法应用于计算机系统，该计算机系统可以为服务器、终端设备或虚拟机(virtual machine，VM)。该计算机系统的架构可以参阅图1进行理解。
终端设备(也可以称为用户设备(user equipment，UE))是一种具有无线收发功能的设备，可以部署在陆地上，包括室内或室外、手持或车载；也可以部署在水面上(如轮船等)；还可以部署在空中(例如飞机、气球和卫星上等)。所述终端可以是手机(mobile phone)、平板电脑(pad)、带无线收发功能的电脑、虚拟现实(virtual reality，VR)终端、增强现实(augmented reality，AR)终端、工业控制(industrial control)中的无线终端、无人驾驶(self driving)中的无线终端、远程医疗(remote medical)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端、智慧家庭(smart home)中的无线终端等。
图1为计算机系统的一架构示意图。
如图1所示，该计算机系统10的架构包括用户层101、内核102、编译器103和硬件层104。
该用户层101包括多个应用，每个应用都会对应一个进程，也可以将进程理解为是应用的抽象或实体。进程在执行对应应用的发送任务时可以称为发送进程，在执行对应应用的接收任务时可以称为接收进程。进程间通信的过程可以是用户通过触发应用启动的，例如：用户打开浏览器中的一个网页，在浏览该网页中的一个消息时需要插件辅助完成该消息的全文加载，该场景中，网页为发送进程，插件为接收进程，需要网页的进程向插件的进程发送该消息的相应加载指示，插件的进程才会执行该消息的全文加载。
进程间通信的主要目的是实现同一计算机系统内部相互协作的进程之间的数据共享与信息交换。参与通信的双方或多方通过消息发送或接收实现数据在进程之间的传递，从而完成数据通信。相互通信的两个进程或多个进程，发送数据的进程可以称为发送进程，接收数据的进程可以称为接收进程。在用户层101运行的进程称为运行在用户态的进程。进程间通信通常是在用户态被触发的，但进程间通信的过程需要内核102才能实现。
内核102是操作系统(operating system，OS)负责管理关键资源，并为用户态的进程提供系统调用入口进而在内核提供服务，如：进程间通信，页表管理以及中断控制等服务。以进程间通信为例，从用户态到内核，发送进程可以通过系统调用来申请发送数据的服务，接收进程可以通过系统调用来申请接收数据的服务。
编译器103在进程间通信过程中，可以提供编译服务。本申请中，编译器可以将通信信息写入到寄存器组中，可以将进程间通信要传输的数据写入到寄存器组中等。
硬件层104包括内核102运行所依赖的硬件资源，如：处理器、内存、内存管理单元(memory management unit，MMU)，以及输入/输出(input/output,I/O)设备等。处理器中可以包括寄存器组，该寄存器组可以包括多种类型的寄存器，如：栈帧寄存器、通用寄存器，以及非易失性(callee-saved)寄存器等。栈帧寄存器用于存储栈内存的地址，通用寄存器可以用于存储进程间通信要传输的目标数据，也可以用于存储其他信息，如：通用信息(ipcinfo)等，非易失性寄存器可以用于存储除目标数据之外的一些参数，例如：该非易失性寄存器也可以保存通信信息。
MMU是一种负责处理中央处理器(central processing unit，CPU)的内存访问请求的计算机硬件。它的功能包括虚拟地址到物理地址的转换、内存保护、CPU高速缓存的控制等。
在计算机系统中，进程包括线程。进程是程序的运行实体，是系统进行资源分配和调用的基本单位。线程是程序调度的最小单位，同一进程可能有多个线程，它们拥有各自的调度属性，共享进程的资源。操作系统中，对进程采用进程控制块(processing control block，PCB)来管理进程，采用线程控制块(thread control block，TCB)来管理线程。PCB是OS中为了管理进程设置的一个数据结构，PCB中会记录进程运行的相关信息。TCB可以PCB的一个子集，也可以理解为一个PCB包括多个TCB，每个TCB对应一个线程。一个发送进程中的不同线程可以与同一接收进程中的不同线程通信，也可以与不同接收进程中的线程通信。同理，一个接收进程中的线程也可以与多个不同发送进程中的线程通信，因此，进 程间的通信也可以理解为是不同进程中的线程间的通信。
在一次通信过程中，发送进程需要一个TCB来支持本次通信，该TCB中可以包括执行实体(activation)和调度实体。执行实体是线程的一部分，包含线程运行所需的寄存器的信息，栈内存的信息、内存块的信息等。调度实体也是线程的一部分，包含线程运行所需的优先级等调度相关信息。本申请实施例中，接收进程需要提供一个执行实体来支持本次通信。
本申请实施例提供的进程间通信的方法包括两种情况，第一种为：两个进程之间的通信，即一个发送进程，一个接收进程。第二种情况：包括多级进程间的通信，即一个发送进程，多个接收进程，该种情况也可以称为多级IPC序列的进程间通信。需要说明的是，本申请中，“多个”包括“两个”。“多个”也可以描述为“至少两个”。下面对这两种情况分别进行介绍。
无论是两个进程间的通信，还是多级IPC序列的进程间通信，本申请实施例提供的进程间通信的方法都可以通过具有计算机系统的设备，如：终端设备来实现，具体的，可以是计算机系统中的一个或多个处理器来实现上述进程间通信的过程。
第一种：两个进程之间的通信，即一个发送进程，一个接收进程。
如图2所示，本申请实施例提供的进程间通信的方法的一实施例包括：
201、根据调用约定，将通信信息写入发送进程的第一执行实体的寄存器组中，将第一数据写入第一执行实体的栈内存中。
该步骤201可以在用户态执行。
第一数据包含在发送进程要发送给第一接收进程的目标数据中。
调用约定(calling convension)是与数据写入和数据读取相关的规定，该处“数据写入”和“数据读取”中的“数据”包括各类型寄存器中的数值，以及进程间通信要传递的数据。该调用约定明确了数据在发送进程的执行实体对应的寄存器和栈内存中的写入顺序，以及从接收进程的执行实体对应的寄存器和栈内存中读取数据的顺序。
第一执行实体用于发送进程与第一接收进程通信。寄存器组中可以包括多个类型的寄存器，如：栈帧寄存器、通用寄存器，以及非非易失性寄存器等。该栈帧寄存器用于存储栈内存的地址。通用寄存器可以用于存储目标数据中的部分或全部。栈内存可以用于存储目标数据中的部分或全部。第一内存块也可以存储目标数据中的部分或全部。
通信信息(ipcinfo)是本申请实施例中新提出的概念，该通信信息中可以包括第一值，该第一值用于指示第一数据的数据量。
通用寄存器中也可以存储有目标数据中的一部分数据，这部分数据可以称为第二数据。当有第二数据时，根据调用约定，将第二数据写入第一执行实体的寄存器组中，第一执行实体的寄存器组中的信息还包括第二数据。
若该内存块中也存储有目标数据中的部分数据，则将这部分数据称为第三数据。这时该通信信息中还可以包括第二值，该第二值用于指示第三数据的数据量。
若寄存器组中没有写入目标数据中的一部分数据，则该目标数据不包括第二数据。若内存块中不包括第三数据，则该目标数据就为第一数据。若寄存器组中有写入第二数据， 但内存块中不包括第三数据，则该目标数据就为第一数据加上第二数据。若寄存器组中有写入第二数据，内存块中也包括第三数据，则该目标数据就为第一数据加上第二数据，再加上第三数据。
该通信信息中还可以包括用于处理该目标数据的函数的标识，该函数可以是接收函数。
该通用信息中的第一值，也可以还包括的第二值可以是上述图1的计算机系统中的编译器确定的，该编译器可以根据目标数据的大小，再结合调用约定在寄存器组和栈内存中对写入数据量的要求，确定出第一值，若数据较大，可以将除掉存储在寄存器组和栈内存之外的数据放在第一内存块中，该存储在第二内存块中的数据量可以用第二值表示，这时，该通信信息中也应包含该第二值，即根据第一值、第二值，以及用于处理该目标数据的函数的标识生成该通信信息。
202、通过系统调用,将第一执行实体的寄存器组中的信息复制到第一执行实体的上下文中。
该步骤可以通过系统调用触发发送进程陷入内核来实现。
寄存器组中的信息包括通信信息和栈内存的地址，也可以包括第二数据，第一内存块的地址等，第一执行实体的上下文为内核中存储的第一执行实体的寄存器组中的信息。当然，寄存器组中还会包括其他的信息或数值，这些信息或数值都会随着发送进程陷入内核而被复制到第一执行实体的上下文中。
203、根据第一执行实体的上下文中的第一值和栈内存的地址，从第一执行实体的栈内存复制第一数据到第二执行实体的栈内存中。
第二执行实体可以是从第一接收进程的执行实体的资源池中分配的一个执行实体，该资源池中通常包括多个执行实体，当发送进程申请与第一接收进程通信时，就可以从该资源池中为该发送进程分配一个执行实体。
栈内存的地址指示了第一数据在栈内存中存储的起始位置，第一值指示了第一数据的数据长度，因此，根据栈内存的地址和第一值就可以在第一执行实体的栈内存中找到该第一数据，并将该第一数据复制到第二执行实体在内核中的栈内存中。
若目标数据还包括第二数据，在步骤202之前，还包括：根据调用约定，将第二数据写入第一执行实体的寄存器组中，调用约定还用于指示第二数据在寄存器组中的写入顺序。
然后，上述步骤202可以包括：将寄存器组中的第二数据、通信信息和栈内存的地址复制到第一执行实体的上下文中。
在执行步骤202之后，还可以包括：将第一执行实体的上下文复制到第二执行实体的上下文中；将第二执行实体的上下文写入第二执行实体的寄存器组中。
第二执行实体的上下文为内核中存储的第二执行实体的寄存器组中的信息。
若目标数据还包括第三数据，则还可以根据第二值，以及第一内存块的地址，从第一执行实体的第一内存块复制第三数据到第二执行实体的内存块中。
可选地，第一执行实体中还包括第一页表信息，第二执行实体中还包括第二页表信息，第一页表信息和第二页表信息用于第一数据从第一执行实体的栈内存复制到第二执行实体的栈内存，或第三数据从第一执行实体的第一内存块复制到第二执行实体的内存块。
第一页表信息用于表示第一执行实体的内存空间的虚拟地址与物理地址的映射关系，该第一执行实体的内存空间包括第一执行实体的栈内存和第一内存块，第二页表信息用于表示第二执行实体的内存空间的虚拟地址与物理地址的映射关系，该第二执行实体的内存空间包括第二执行实体的栈内存和内存块。
本申请实施例中，基于第一页表信息和第二页表信息复制第一数据或第三数据的过程可以通过如下两种方式实现。
第一种复制方式：基于第一页表信息将第一数据从用户态的栈内存复制到内核的内存，再基于第二页表信息将第一数据从内核的内存复制到第二执行实体的栈内存。对于第三数据，从第一执行实体的第一内存块复制到第二执行实体的内存块的原理也是相同的，只是将第一执行实体的栈内存修改为第一执行实体的第一内存块，第二执行实体的栈内存修改为第二执行实体的内存块。
该过程参阅图3A可以包括：
2031、根据第一执行实体的栈内存的地址(虚拟地址)以及第一页表信息所包含的虚拟地址与物理地址的映射关系，确定该栈内存的地址对应的第一物理地址，进而确定第一物理内存。
2032、根据该第一物理地址以及第一值从第一执行实体的第一物理内存中读出该第一数据，并将该第一数据放入内核的一块物理内存中。
2033、在内核基于第二执行实体的栈内存的地址和第二页表信息确定该第二执行实体的栈内存对应的第二物理地址，再根据该第一值所指示的第一数据的长度，确定需要的第二执行实体的第二物理内存。
2034、从内核的内存中将该第一数据复制到该第二执行实体的第二物理内存中。
第二种复制方式：基于第一页表信息将第一执行实体的栈内存映射到内核的第一内存，基于第二执行实体的页表信息将第二执行实体的栈内存映射到内核的第二内存，将第一数据从第一内存复制到第二内存。对于第三数据，从第一执行实体的第一内存块复制到第二执行实体的内存块的原理也是相同的，只是将第一执行实体的栈内存修改为第一执行实体的第一内存块，第二执行实体的栈内存修改为第二执行实体的内存块。
该过程参阅图3B可以包括：
2035、基于第一页表信息所表示的第一执行实体的用户态的内存空间与内核的内存空间的映射关系，根据第一执行实体的栈内存的地址确定在内核中对应的第一内存。
2036、基于第二页表信息所表示的第二执行实体的用户态的内存空间与内核的内存空间的映射关系，根据第二执行实体的栈内存的地址确定在内核中对应的第二内存。
2037、将第一数据从第一内存复制到第二内存。
因为第一内存与第一执行实体的栈内存映射，通过上述图3A对应的过程可知，第一执行实体的栈内存与第一执行实体的第一物理内存映射，第二内存与第二执行实体的栈内存映射，通过上述图3A对应的过程可知，第二执行实体的栈内存与第二执行实体的第二物理内存映射，所以，虚拟形态上，将第一数据从第一内存复制到第二内存，物理形态上，该第一数据就好从第一物理内存被复制到第二物理内存。
本申请实施例基于调用约定，通过栈内存传递进程间通信数据，在发送端因为栈内存地址一直在寄存器组中存在，不需要为进程间通信特别写入该栈内存的地址，可以降低通信开销，而且在接收端可以直接从栈内存中读取进程间通信的数据进行处理，不需要先将进程间通信的数据从内存块中先读取出来再写入到栈内存中，然后再进行处理，这样进一步降低了进程间通信的性能开销。
另外，本申请实施例中，若发送进程与第一接收进程要传递的目标数据的数据量很小，通用寄存器就可以完成传递，这种情况下，用于描述栈内存中存储的第一数据的第一值可以等于0。
从上述图2、图3A和图3B可知，栈内存、内存块、内核的第一内存和第二内存都是逻辑上的内存空间，第一物理内存和第二物理内存才是硬件的存储器件，上述描述中涉及了第一数据从第一执行实体的栈内存复制到第二执行实体的栈内存的描述，以及第三数据从第一执行实体的第一内存块复制到第二执行实体的内存块的描述，这里的第一数据和第三数据可以理解为是逻辑上的数据。上述也涉及到了第一数据和第三数据从第一物理被复制到第二物理内存的描述，这里的第一数据和第三数据可以理解为是物理上的数据。无论是逻辑的还是物理的，本申请中指代的都是同一份数据，逻辑数据被复制的过程物理数据也会同步被复制。
可选地，本申请实施例提供的进程间通信的方法，还可以通过叠加执行实体的方式来实现由第二执行实体加上发送进程的调度实体来处理数据，然后返回处理结果。而且，为了保证进程间通信的安全性，本申请实施例提供的方案还可以对发送进程进行身份验证。下面结合图4进一步介绍本申请实施例提供的进程间通信的方法。
如图4所示，在内核中，发送进程的第一执行实体中包括链表节点(list node)、第一配置信息(Curr_Conf)、第二配置信息(Xact_Conf)和上下文(UCTX)。第二执行实体也包括链表节点、第一配置信息、第二配置信息和上下文。每个执行实体中都会包括上述四个部分，只是各部分中所包括的内容可能不相同。
第一执行实体的链表节点和第二执行实体的链表节点通过箭头关联表示第二执行实体叠加到第一执行实体上。叠加第二执行实体后，该第一执行实体会进入非活跃状态(inactive)，由第二执行实体来接替第一执行实体的工作。第一执行实体位于发送进程的一个线程，或者一个TCB中，该TCB还包括调度实体，在第二执行实体叠加到第一执行实体后，该TCB就包括第二执行实体和该调度实体，这样本申请实现发送进程的一个线程运行第二执行实体的内容来执行数据处理的过程。
第一配置信息中会包括本进程的标识和本进程的页表信息，第二配置信息会包括通信发起进程的标识和该通信发起进程的页表信息。这样，第一执行实体的第一配置信息中可以包括发送进程的标识，以及第一页表信息。第一执行实体的第二配置信息的位置可以不使用，也就是第二配置信息中不包括具体内容，也可以是该第二配置信息中的内容与第一配置信息中的内容相同。第二执行实体的第一配置信息包括第一接收进程的标识和第二页表信息。第二配置信息中包括的是发送进程的标识和第一页表信息。若是多级IPC序列的场景，第二配置信息中包括的是发起该多级IPC序列的进程的标识，也就是整个IPC序列上的 第一个进程的标识。
第一执行实体的上下文中包括第一执行实体的寄存器组中的信息。第二执行实体的上下文中包括第二执行实体的寄存器组中的信息。
该第一执行实体可以是线程控制块1中的执行实体，该线程控制块1中还包括调度实体，该调度实体中包括该发送进程本次发送任务的调度优先级(priority),以及该发送进程所处的状态(state)。该线程控制块1可以是该发送进程多个线程控制块中的一个，该发送进程还可以包括线程控制块2到线程控制块X等多个线程控制块，X为大于2的整数。
该第二执行实体可以是第一接收进程的执行实体的资源池中的一个执行实体，该资源池中还包括其他执行实体，如执行实体M到执行实体N。
在发送进程与第一接收进程通信的过程中，从发送进程在用户态开始运行到第一数据在内核中被复制到第二执行实体的栈内存的过程可以参阅前述图2、图3A和图3B所对应的实施例部分的相应内容进行理解。下面对后续内容进行介绍。
204、在第一执行实体上叠加第二执行实体。
执行实体叠加的过程可以是通过链表的方式实现的。
205、第二执行实体切换到用户态。
发送进程的线程控制块中包括第二执行实体和原本的调度实体，并且该第二执行实体会切换到用户态。从内核进入用户态，第二执行实体的上下文中的内容会写入到第二执行实体在用户态的寄存器组中。由前述第一页表信息和第二页表信息部分的描述可知，第一数据可以通过第一种复制方式或第二种复制方式被复制到第二执行实体的栈内存中，若目标数据中包括第三数据，该第三数据也会通过第一种复制方式或第二种复制方式被复制到第二执行实体的内存块中。
206、读取全部或部分目标数据并对全部或部分目标数据进行处理，以得到处理结果。
通信信息会随着系统调用从第一执行实体的寄存器组被复制到第一执行实体的上下文，在进入内核后，该通信信息又会随第一执行实体的上下文被复制到第二执行实体的上下文，然后随着第二执行实体切换到用户态被复制到第二执行实体的寄存器组。
因为通信信息中包括用于处理目标数据的函数的标识，所以，该用于处理目标数据的函数的标识也会被复制到第二执行实体的寄存器组中，这样，就可以根据第二执行实体的寄存器组中的函数的标识，调用函数，对全部或部分目标数据进行处理，以得到处理结果。
因为寄存器、栈内存和内存块传递数据的速度不同，在处理目标数据时可以等待全部目标数据都到达第二执行实体后再处理，也可以针对先到达第二执行实体的部分数据先进行处理。
第二配置信息中包括发送进程的标识，在将第二执行实体切换到用户态之前，将发送进程的标识写入第二执行实体的上下文中，在第二执行实体切换到用户态的过程中，该发送进程的标识也会写入第二执行实体的寄存器组中，这样，在接收端就可以从寄存器组中读取发送进程的标识，进而进行身份验证，该身份验证的过程可以参考白名单的原理进行理解，安全的进程都会提前注册到白名单中，接收端可以根据该发送进程的标识查找该标识是否在白名单中，若在白名单中，则可以确认该发送进程是安全的进程，这样，该种可 能的实现方式中，在采用执行实体执行进程间通信的过程中借用第二执行实体传递了发送进程的标识，从而对发送进程进行身份验证，提高了进程间通信的安全性。
在得到处理结果后，可以释放第二执行实体，由原来的第一执行实体继续执行发送进程的工作，接收第二执行实体处理目标数据后返回的处理结果，完成一次IPC通信。
本申请实施例，发送进程的一个线程借用第一接收进程的第二执行实体进行目标数据处理，得到处理结果。可见，该种可能的实现方式提供了一种不同的进程间通信的形式。
为了便于理解，将上述进程间通信的过程结合到基于ARM-V7架构的微内核系统中，在如图5所示的结构中，发送进程的第一执行实体包括寄存器组，该寄存器组包括R0-R3四个通用寄存器，根据调用约定规定，第一执行实体的R0-R3四个通用寄存器可用于传递通信信息和目标数据，该寄存器组中还可以包括其他寄存器，如栈帧寄存器，图5中未全部示出。第二执行实体的寄存器组包括R0-R3四个通用寄存器，R4可以是一个非易失性寄存器，该寄存器组还可以包括其他寄存器，如栈帧寄存器，图5中未全部示出。
需要说明的是，本申请提出的方法也可以适用于其它类型的内核架构。
根据调用约定，在发送进程的用户态可以使用64位无符号整数编码通信信息(ipcinfo)，存储在R0和R1寄存器中。当然，这里的64位只是举例，本申请中不限定该通信信息的位数。以64位为例，该通信信息由低到高位数分别为：14位：发送进程通过内存块发送的数据的数据量(第二值)。1位：0表示开启一个新的事务(transaction),1表示转发当前事务。本申请实施例中将多级IPC序列，或者只有一个发送进程和一个接收进程的序列称为一个事务。首次开启的事务指的是一个新的事务。如果是在已有事务的基础上进行后续IPC，那么该种情况的IPC表示的是转发当前事务。11位：用户处理目标数据的函数的标识；5位：发送进程通过栈内存发送的数据量(该处的数据量表示的是通过5位二进制(也就是最大32)构成的数值所标识的4字节大小的倍数)，该数据量也可以描述为数据的大小。33位：保留，待扩展使用。
使用R2传递第一内存块的地址。栈内存的地址可以通过寄存器组中的栈帧寄存器传递，在该图5中未示出该栈帧寄存器。
通用寄存器中还空余出一个通过寄存器R3，该通过寄存器R3可以用于传递目标数据中的一部分，也就是前述所描述的第二数据。该第二数据可以是目标数据中的第一个数据。
根据调用约定，发送进程和第一接收进程可以分别使用上述5位表示的最多128字节内存发送和接收通过栈内存传递的数据。当然，该128字节也是举例说明，具体使用栈内存传递的数据的数据量可以根据需求设置。
该发送进程通过系统调用从用户态陷入内核。
在内核中，每个进程对应一个用于记录授权信息的结构体CNode，每个CNode具有一个由32位无符号整数表示的唯一标识cnode_idx，本申请中用cnode_idx表示进程的标识，该进程的标识可以用于验证发送进程的身份。
第一执行实体的第一配置信息(Curr_Conf)中记录第一执行实体的cnode_idx和第一执行实体的地址空间信息，该地址空间信息用于表示内核中的与该第一执行实体对应的内存的地址空间，可以参阅第一页表信息进行理解。
第一执行实体的第二配置信息(Xact_Conf)中记录事务发起者所在进程的标识和地址空间信息，因为该场景中，只涉及到一个发送进程和一个接收进程，所以该处第二配置信息中的内容为空，也可以与第一配置信息的内容相同。
第二执行实体使用64位无符号整数编码前一级执行实体所在进程的cnode_idx，存储在R0寄存器和R1寄存器，因为该场景中，只涉及到一个发送进程和一个接收进程，所以，R0和R1寄存器中的进程的表示可以是相同的。
第二执行实体中R2寄存器用作保留(该保留的寄存器可用于传递第一接收进程预先为发送进程设置的用户态标识信息，该用户态标识信息可以用于加速数据处理)。
通过第二执行实体中的通用寄存器R3开始接收第二数据。
通过第二执行实体中的栈内存接收第一数据。
通过第二执行实体中的内存块接收第三数据。
通信信息可以存储在寄存器R4中，若通信信息使用高32位保留位，则需要R4以及R5来存储该通信信息。
本申请实施例中第二执行实体来自于第一接收进程的执行实体的资源池。本申请实施例中还会对该资源池中的执行实体进行增加或删除的弹性管理。该过程可以参阅图6进行理解。
如图6所示，该执行实体的资源池中可以设置侦听线程，该侦听线程用于侦听该资源池中执行实体的分配或释放，或者用于监控资源池中剩余执行实体的数量，剩余执行实体也可以理解为可被使用的执行实体。
该资源池中设置有下水线和上水线。下水线用于表示资源池中可用执行实体的数量下限。上水线用于表示资源池中可用执行实体的数量上限。
从图6中可见，该下水线为M+1个执行实体，上水线为N个执行实体。
当侦听线程侦听到有执行实体被分配，如：上述IPC过程中，从执行实体的资源池分配第二执行实体。若资源池中减掉第二执行实体后可用执行实体的数量低于下水线，则在资源池中创建新的执行实体。如：若资源池中剩余的可用执行实体数量小于M+1，则会创建一个或多个执行实体，以补充资源池中执行实体的数量。这样通过合理设置下水线，可以使得发送进程申请IPC服务时，第一接收进程有执行实体可以提供服务，且可用执行实体数量可控，避免了因阻塞导致的可靠性下降问题。
当侦听线程侦听到有执行实体被释放，如：在得到处理结果后，释放第二执行实体；若资源池中加上第二执行实体后可用执行实体的数量高于上水线，则从资源池中删除至少一个执行实体，如：释放第二执行实体后，该资源池中的执行实体数量超过N，则可以删除一个或多个执行实体。这样通过合理设置上水线，可以控制过多的可用执行实体导致过大的内存开销。
无论是弹性增加还是弹性删除，都尽量使资源池中执行实体的数量保持在上水线和下水线之间。既可以避免执行实体数量太少而导致的进程堵塞，也可以避免因执行实体数量太多而导致过大的内存开销。
第二种情况：多个进程间的通信，即一个发送进程，多个接收进程，该种情况也可以 称为多级IPC序列的进程间通信。
上述第一接收进程位于多级IPC序列中，多级IPC序列还包括第二接收进程，在与发送进程的通信顺序上，第二接收进程位于第一接收进程之后。需要说明的是，这里只是以第一接收进程和第二接收进程这两级接收进程为例来进行说明，实际上多级IPC序列中可以包括多个接收进程，无论有多少接收进程，每两个连续的接收进程之间的IPC原理都是相同的，每两个连续的接收进程的IPC过程都可以参阅前述发送进程和第一接收进程的过程进行理解。
在多级IPC序列中与前述两级IPC的过程不同的是，每个中间进程都会传递第一个进程的标识，第一个进程的页表信息，用于标识通过第二内存块传递给最后一个进程的第四数据的数据量的第三值，以及第二内存块的地址。
将该过程结合到上述过程中，可以参阅图7进行理解。如图7所示，第二接收进程包括第三执行实体，该第三执行实体中不仅包括上一个第二接收进程的标识和第三页表信息，还包括发送进程的标识和第一页表信息。
发送进程和第一接收进程通过前述实施例所描述的方式，将第一数据、第二数据和第三数据分别通过通用寄存器、栈内存和第一内存块传递给第一接收进程。
发送进程通过第一接收进程的第二执行实体传递第四值、第二内存块的地址，发送进程的标识和第一页表信息。第三执行实体根据该发送进程的标识进行身份验证，根据第一执行实体的第二内存块的地址，第一执行实体的第一页表信息，以及第三值，从第一执行实体的第二内存块中复制第四数据到第三执行实体的内存块中。
本申请实施例中，在多级IPC序列中，当较大数据需要多级传递时，该种可能的实现方式中只需要各级中间进程(如：第一接收进程)的执行实体中记录发送进程的第一页表信息、第一执行实体的第二内存块的地址和第四数据的数据量。这样，从发送进程到第二接收进程的第四数据的传递只需基于发送进程和第二接收进程页表信息做跨进程拷贝。需要说明的是，第一接收进程和第二接收进程之间还可以包括其他接收进程，无论从发送进程到第二接收进程之间包括一个或多个中间进程，本申请中从发送进程到第二接收进程只需要传递第二内存块的地址、第四数据的数据量以及第一页表信息，第二接收进程只需要复制一次第四数据，大大提高了数据传输的性能。
以上介绍了计算机系统和进程间通信的方法，下面结合附图介绍本申请实施例提供的进程间通信的装置，该装置可以是一个计算机设备。
如图8所示，本申请实施例提供的进程间通信的装置40的一实施例包括：
第一处理单元401，用于根据调用约定，将通信信息写入发送进程的第一执行实体的寄存器组中，将目标数据的第一数据写入第一执行实体的栈内存中，通信信息包括第一值，第一值用于指示第一数据的数据量，目标数据为发送进程要发送给第一接收进程的数据，调用约定用于指示通信信息在寄存器组中的写入顺序，以及第一数据在栈内存中的写入顺序。
第二处理单元402，用于将第一执行实体的寄存器组中的信息复制到第一执行实体的上下文中，寄存器组中的信息包括通信信息和栈内存的地址。
第三处理单元403，用于根据第一执行实体的上下文中的第一值和栈内存的地址，从第一执行实体的栈内存复制第一数据到第一接收进程的第二执行实体的栈内存中。
本申请实施例中，基于调用约定，通过栈内存传递进程间通信数据，在发送端因为栈内存地址一直在寄存器组中存在，不需要为进程间通信特别写入该栈内存的地址，可以降低通信开销，而且在接收端可以直接从栈内存中读取进程间通信的数据进行处理，不需要先将进程间通信的数据从内存块中先读取出来再写入到栈内存中，然后再进行处理，这样进一步降低了进程间通信的性能开销。
可选地，目标数据还包括第二数据，第一处理单元401，还用于在将第一执行实体的寄存器组中的信息复制到第一执行实体的上下文中之前，根据调用约定，将第二数据写入第一执行实体的寄存器组中，调用约定还用于指示第二数据在寄存器组中的写入顺序。
第二处理单元402，用于将寄存器组中的第二数据、通信信息和栈内存的地址复制到第一执行实体的上下文中。
第三处理单元403，还用于将第一执行实体的上下文复制到第二执行实体的上下文中；将第二执行实体的上下文写入第二执行实体的寄存器组中。
可选地，目标数据还包括第三数据，通信信息还包括第二值，第二值用于指示存储在第一执行实体的第一内存块中第三数据的数据量，第一处理单元401，将第一内存块的地址写入第一执行实体的寄存器组中，将第三数据写入第一执行实体的第一内存块中。
第三处理单元403，还用于根据第二值，以及第一内存块的地址，从第一执行实体的内存块复制第三数据到第二执行实体的内存块中。
可选地，第一执行实体中还包括第一页表信息，第二执行实体中还包括第二页表信息，第一页表信息和第二页表信息用于第一数据从第一执行实体的栈内存复制到第二执行实体的栈内存，或第三数据从第一执行实体的第一内存块复制到第二执行实体的内存块。
可选地，第三处理单元403，还用于在第一执行实体上叠加第二执行实体，并将第二执行实体的上下文写入到第二执行实体的寄存器组中，其中，第二执行实体的上下文包括第一执行实体的上下文中的数据；根据调用约定从第二执行实体的寄存器组和第二执行实体的栈内存中读取全部或部分目标数据，并对全部或部分目标数据进行处理，以得到处理结果，调用约定还用于指示对第二执行实体的寄存器组和栈内存的读取顺序。
可选地，第三处理单元403，用于根据第二执行实体的寄存器组中的函数的标识，调用函数，对全部或部分目标数据进行处理，以得到处理结果。
可选地，第一执行实体中还包括发送进程的标识，第三处理单元403，还用于在将第二执行实体切换到用户态之前，将发送进程的标识写入第二执行实体的上下文中，发送进程的标识用于在第二执行实体切换到到用户态后验证发送进程的身份。
可选地，第一处理单元401，还用于根据目标数据的数据量，以及调用约定，确定第一值；使用第一值，生成通信信息。
可选地，第二处理单元402，还用于从执行实体的资源池分配第二执行实体；若资源池中减掉第二执行实体后可用执行实体的数量低于下水线，则在资源池中创建新的执行实体，下水线用于表示资源池中可用执行实体的数量下限。
可选地，第二处理单元402，还用于在得到处理结果后，释放第二执行实体；若资源池中加上第二执行实体后可用执行实体的数量高于上水线，则从资源池中删除至少一个执行实体，上水线用于表示资源池中可用执行实体的数量上限。
可选地，第一接收进程位于多级IPC序列中，多级IPC序列还包括第二接收进程，在与发送进程的通信顺序上，第二接收进程位于第一接收进程之后；第三处理单元403，还用于通过第一接收进程的第二执行实体传递第一执行实体的第二内存块的地址，第一执行实体的第一页表信息，以及第三值到第二接收进程的第三执行实体，第三值用于指示发送进程发送给第二接收进程的第四数据的数据量；根据第一执行实体的第二内存块的地址，第一执行实体的第一页表信息，以及第三值，从第一执行实体的第二内存块中复制第四数据到第三执行实体的内存块中。
第三处理单元403，还用于通过第一接收进程的第二执行实体传递发送进程的标识到第二接收进程的第三执行实体，发送进程的标识用于第三执行实体验证发送进程的身份。
以上所描述的进程间通信的装置40可以参阅前述方法实施例部分的相应描述进行理解，此处不做重复赘述。
图9所示，为本申请的实施例提供的计算机设备50的一种可能的逻辑结构示意图。计算机设备50包括：处理器501、通信接口502、存储器503以及总线504。处理器501、通信接口502以及存储器503通过总线504相互连接。在本申请的实施例中，处理器501用于对计算机设备50的动作进行控制管理，例如，处理器501用于执行图2至图7的方法实施例中201至205的步骤，通信接口502用于支持计算机设备50进行通信。存储器503，用于存储计算机设备50的程序代码和数据。
其中，处理器501可以是中央处理器单元，通用处理器，数字信号处理器，专用集成电路，现场可编程门阵列或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。其可以实现或执行结合本申请公开内容所描述的各种示例性的逻辑方框，模块和电路。处理器501也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，数字信号处理器和微处理器的组合等等。总线504可以是外设部件互连标准(Peripheral Component Interconnect，PCI)总线或扩展工业标准结构(Extended Industry Standard Architecture，EISA)总线等。总线可以分为地址总线、数据总线、控制总线等。为便于表示，图8中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
在本申请的另一实施例中，还提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机执行指令，当设备的处理器执行该计算机执行指令时，设备执行上述图2至图7中进程间通信的方法。
在本申请的另一实施例中，还提供一种计算机程序产品，该计算机程序产品包括计算机执行指令，该计算机执行指令存储在计算机可读存储介质中；当设备的处理器执行该计算机执行指令时，设备执行上述图2至图7中进程间通信的方法。
在本申请的另一实施例中，还提供一种芯片系统，该芯片系统包括处理器，该处理器用于支持进程间通信的装置实现上述图2至图7中进程间通信的方法。在一种可能的设计中，芯片系统还可以包括存储器，存储器，用于保存进程间通信的装置必要的程序指令和数据。 该芯片系统，可以由芯片构成，也可以包含芯片和其他分立器件。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请实施例的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请实施例所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请实施例各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请实施例各个实施例方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。

Claims (15)

  1. 一种进程间通信的方法，其特征在于，所述方法应用于计算机系统，所述方法包括：
    根据调用约定，将通信信息写入发送进程的第一执行实体的寄存器组中，将目标数据的第一数据写入所述第一执行实体的栈内存中，所述通信信息包括第一值，所述第一值用于指示所述第一数据的数据量，所述目标数据为所述发送进程要发送给第一接收进程的数据，所述调用约定用于指示所述通信信息在所述寄存器组中的写入顺序，以及所述第一数据在所述栈内存中的写入顺序；
    将所述第一执行实体的所述寄存器组中的信息复制到所述第一执行实体的上下文中，所述寄存器组中的所述信息包括所述通信信息和所述栈内存的地址；
    根据所述第一执行实体的所述上下文中的所述第一值和所述栈内存的地址，从所述第一执行实体的所述栈内存复制所述第一数据到所述第一接收进程的第二执行实体的栈内存中。
  2. 根据权利要求1所述的方法，其特征在于，所述目标数据还包括第二数据，在所述将所述第一执行实体的所述寄存器组中的信息复制到所述第一执行实体的上下文中之前，所述方法还包括：
    根据所述调用约定，将所述第二数据写入所述第一执行实体的所述寄存器组中，所述调用约定还用于指示所述第二数据在所述寄存器组中的写入顺序；
    所述将所述第一执行实体的所述寄存器组中的信息复制到所述第一执行实体的上下文中包括：
    将所述寄存器组中的第二数据、所述通信信息和所述栈内存的地址复制到所述第一执行实体的上下文中；
    所述方法还包括：
    将所述第一执行实体的上下文复制到所述第二执行实体的上下文中；
    将所述第二执行实体的上下文写入所述第二执行实体的寄存器组中。
  3. 根据权利要求1或2所述的方法，其特征在于，所述目标数据还包括第三数据，所述通信信息还包括第二值，所述第二值用于指示存储在所述第一执行实体的第一内存块中所述第三数据的数据量，所述方法还包括：
    将所述第一内存块的地址写入所述第一执行实体的所述寄存器组中，将所述第三数据写入所述第一执行实体的所述第一内存块中；
    根据所述第二值，以及所述第一内存块的地址，从所述第一执行实体的所述第一内存块复制所述第三数据到所述第二执行实体的内存块中。
  4. 根据权利要求3所述的方法，其特征在于，所述第一执行实体中还包括第一页表信息，所述第二执行实体中还包括第二页表信息，所述第一页表信息和所述第二页表信息用于所述第一数据从所述第一执行实体的栈内存复制到所述第二执行实体的栈内存，或所述第三数据从所述第一执行实体的第一内存块复制到所述第二执行实体的内存块。
  5. 根据权利要求1-4任一项所述的方法，其特征在于，所述方法还包括：
    在所述第一执行实体上叠加所述第二执行实体，并将所述第二执行实体的上下文写入 到所述第二执行实体的寄存器组中，其中，所述第二执行实体的上下文包括所述第一执行实体的上下文中的数据；
    根据所述调用约定从所述第二执行实体的寄存器组和所述第二执行实体的所述栈内存中读取全部或部分所述目标数据，并对所述全部或部分所述目标数据进行处理，以得到处理结果，所述调用约定还用于指示对所述第二执行实体的所述寄存器组和所述栈内存的读取顺序。
  6. 根据权利要求5所述的方法，其特征在于，所述通信信息还包括用于处理所述目标数据的函数的标识；
    所述对所述全部或部分目标数据进行处理，以得到处理结果，包括：
    根据所述第二执行实体的寄存器组中的所述函数的标识，调用所述函数，对所述全部或部分目标数据进行处理，以得到所述处理结果。
  7. 根据权利要求5或6所述的方法，其特征在于，所述第一执行实体中还包括所述发送进程的标识，所述方法还包括：
    将所述发送进程的标识写入所述第二执行实体的上下文中，所述发送进程的标识用于所述第二执行实体验证所述发送进程的身份。
  8. 根据权利要求1-7任一项所述的方法，其特征在于，所述方法还包括：
    从执行实体的资源池分配所述第二执行实体；
    若所述资源池中减掉所述第二执行实体后可用执行实体的数量低于下水线，则在所述资源池中创建新的执行实体，所述下水线用于表示所述资源池中可用执行实体的数量下限。
  9. 根据权利要求5-7任一项所述的方法，其特征在于，所述方法还包括：
    在得到所述处理结果后，释放所述第二执行实体；
    若所述资源池中加上所述第二执行实体后可用执行实体的数量高于上水线，则从所述资源池中删除至少一个执行实体，所述上水线用于表示所述资源池中可用执行实体的数量上限。
  10. 根据权利要求1-9任一项所述的方法，其特征在于，所述第一接收进程位于多级IPC序列中，所述多级IPC序列还包括第二接收进程，在与所述发送进程的通信顺序上，所述第二接收进程位于所述第一接收进程之后；所述方法还包括：
    通过所述第一接收进程的第二执行实体传递所述第一执行实体的第二内存块的地址，所述第一执行实体的第一页表信息，以及第三值到所述第二接收进程的所述第三执行实体，所述第三值用于指示所述发送进程发送给所述第二接收进程的第四数据的数据量；
    根据所述第一执行实体的第二内存块的地址，所述第一执行实体的第一页表信息，以及所述第三值，从所述第一执行实体的第二内存块复制所述第四数据到所述第三执行实体的内存块中。
  11. 根据权利要求10所述的方法，其特征在于，所述方法还包括：
    通过所述第一接收进程的第二执行实体传递所述发送进程的标识到所述第二接收进程的所述第三执行实体，所述发送进程的标识用于所述第三执行实体验证所述发送进程的身份。
  12. 一种计算机可读存储介质，其上存储有计算机程序，其特征在于，所述计算机程序被处理器执行时实现如权利要求1-11任一项所述的方法。
  13. 一种计算设备，其特征在于，包括处理器和存储有计算机程序的计算机可读存储介质；
    所述处理器与所述计算机可读存储介质耦合，所述计算机程序被所述处理器执行时实现如权利要求1-11任一项所述的方法。
  14. 一种芯片系统，其特征在于，包括处理器，所述处理器被调用用于执行如权利要求1-11任一项所述的方法。
  15. 一种计算机程序产品，其特征在于，包括计算机程序，所述计算机程序当被一个或多个处理器执行时用于实现如权利要求1-11任一项所述的方法。
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