WO2022021337A1

WO2022021337A1 - Flash memory control method and device

Info

Publication number: WO2022021337A1
Application number: PCT/CN2020/106229
Authority: WO
Inventors: 苏杰; 林财成; 朱胜
Original assignee: 华为技术有限公司
Priority date: 2020-07-31
Filing date: 2020-07-31
Publication date: 2022-02-03
Also published as: CN115668153A

Abstract

The present application provides a flash memory control method and device, the device comprising: a random access memory for storing a flash translation layer (FTL) secondary table; and a controller for receiving a data access instruction sent by a host machine, the data access instruction comprising a target logical block address (LBA) of target data. Physical page numbers (PPN) corresponding to an LBA segment indicated by a first entry of the FTL secondary table are continuous. If the first entry corresponds to a valid data space, the target data is accessed according to the target LBA and a beginning PPN in the first entry, the beginning PPN being a PPN corresponding to the first LBA in the LBA segment indicated by the first entry. The flash memory control device can directly access the target data using information in the FTL secondary table, does not require an FTL primary table to be loaded and replaced, and improves data access efficiency.

Description

Flash memory control method and device

technical field

The present application relates to the field of storage technologies, and in particular, to a flash memory control method and device.

Background technique

In universal flash storage (UFS), embedded multi-media card (eMMC), or consumer solid state disk (SSD), NAND flash memory has special physical properties, such as requiring Erasing is done at block granularity, and each block has a limit on the number of erasures. Therefore, it is necessary to maintain the mapping relationship between the logical block address (LBA) and the physical page number (PPN) through the flash translation layer (FTL) table entry, so as to achieve the purpose of wear leveling .

UFS, eMMC and consumer SSDs cannot accommodate complete FTL entries due to the small capacity of the on-chip static random access memory (SRAM) of the controller. Therefore, FTL adopts a multi-level mapping method and can only cache part of the SRAM. FTL first-level entry. When the cached FTL first-level table entry misses, the appropriate FTL first-level table needs to be loaded and replaced from the NAND.

The loading and replacement of FTL first-level entries increases read and write latency, reduces system performance, and affects user experience.

SUMMARY OF THE INVENTION

The present application provides a method and device for controlling a flash memory, which can directly access target data through the information of the second-level table of the flash translation layer (FTL) without loading and replacing the first-level table of the FTL, thereby improving the efficiency of data access.

In a first aspect, a flash memory control device is provided, comprising: a random access memory for storing an FTL secondary table; a controller for receiving a data access instruction sent by a host, where the data access instruction includes a target logical block address ( logical block address, LBA); when the physical page number (physical page number, PPN) corresponding to the LBA address segment indicated by the first entry of the FTL secondary table is continuous, and the first entry corresponds to the valid data space , the target data is accessed according to the target LBA and the starting PPN in the first entry, where the starting PPN is the PPN corresponding to the first LBA in the LBA address segment indicated by the first entry.

When the PPNs corresponding to the LBA address segment indicated by the first entry are consecutive, the first entry includes the starting PPN, and the controller may, according to the target LBA of the target data and the information of the starting PPN in the first entry, perform an update on the target data. For access control, there is no need to load and replace FTL first-level tables, which avoids the access delay caused by the loading and replacement of FTL first-level tables, improves the efficiency of data access, and improves system performance.

In a possible implementation manner, when the physical page numbers PPN corresponding to the LBA address segment indicated by the first entry of the FTL secondary table are consecutive, and the first entry corresponds to the invalid data space, the controller further uses : Send indication information to the host, where the indication information is used to indicate that the data access is invalid.

When the first entry corresponds to an invalid data space, the controller can directly return invalid data access information to the host without loading the FTL first-level table corresponding to the first entry for judgment, which improves the efficiency of data access.

In another possible implementation manner, the controller is specifically configured to: obtain the offset of the target LBA, where the offset of the target LBA is the difference between the target LBA and the first LBA in the LBA address segment indicated by the first entry; The target data is accessed based on the offset and the starting PPN.

In another possible implementation manner, the controller is specifically configured to: determine the target PPN corresponding to the target LBA of the target data according to the offset and the starting PPN, where the target PPN is the sum of the starting PPN and the offset; The target PPN accesses target data.

In the above technical solution, according to the starting PPN and the target LBA in the first item, the target PPN corresponding to the target LBA can be obtained through simple calculation, so as to access the target data, which improves the efficiency of data access.

In another possible implementation manner, the controller is further configured to: receive a data write instruction sent by the host, where the data write instruction includes the data to be written; assign a write address to the data to be written; Data write control.

In another possible implementation manner, the controller is specifically configured to: determine that the PPNs corresponding to the LBA address segment indicated by the first entry where the write address is located are continuous; and record the starting PPN in the first entry.

When performing data access control, for the first consecutive entry of the PPN, the starting PPN may be recorded in the first entry to facilitate subsequent data access.

In another possible implementation manner, the first entry includes a space reduction flag, and the space reduction flag is used to indicate that the first entry corresponds to valid data space, or the space reduction flag is used to indicate that the first entry corresponds to invalid data space .

The controller may determine that the first entry corresponds to the valid data space or the first entry corresponds to the invalid data space according to the space reduction flag in the first entry, so as to perform appropriate data access control according to the instruction of the host.

In a second aspect, a flash memory control method is provided, comprising: receiving a data access command sent by a host, where the data access command includes a target logical block address LBA of target data; the LBA address segment indicated by the first entry of the FTL secondary table When the corresponding physical page number PPN is continuous, and the first entry corresponds to the valid data space, the target data is accessed according to the target LBA and the starting PPN in the first entry, and the starting PPN is indicated by the first entry. The PPN corresponding to the first LBA in the LBA address segment.

In a possible implementation manner, when the physical page numbers PPN corresponding to the LBA address segment indicated by the first entry of the FTL secondary table are consecutive, and the first entry corresponds to the invalid data space, the method further includes: Sending indication information to the host, where the indication information is used to indicate that the data access is invalid.

When the first entry corresponds to an invalid data space, the flash controller can directly return the information that the data access is invalid to the host, without loading the FTL first-level table corresponding to the first entry for judgment, which improves the efficiency of data access.

In another possible implementation manner, accessing the target data according to the target LBA and the starting PPN in the first entry includes: obtaining an offset of the target LBA, where the offset of the target LBA is indicated by the target LBA and the first entry The difference of the first LBA in the LBA address segment; according to the offset and the starting PPN, the target data is accessed.

In another possible implementation manner, accessing the target data according to the offset and the starting PPN includes: determining a target PPN corresponding to the target LBA of the target data according to the offset and the starting PPN, where the target PPN is the starting PPN and the offset and ; access target data according to the target PPN.

In the above technical solution, according to the starting PPN and the target LBA in the first item, the target PPN corresponding to the target LBA can be obtained through simple calculation, thereby accessing the target data, which improves the efficiency of data access.

In another possible implementation manner, the method further includes: receiving a data write instruction sent by the host, where the data write instruction includes data to be written; assigning a write address to the data to be written; Write control.

In another possible implementation manner, performing data write control on the data to be written includes: determining that the PPN corresponding to the LBA address segment indicated by the first entry where the write address is located is continuous; recording the first entry Start PPN.

In a third aspect, a method for processing an FTL table entry is provided, comprising: a storage device determining that the physical page numbers corresponding to the logical block addresses in the FTL level-1 table of the first segment are consecutive; updating or establishing the FTL level-2 table of the first segment entry, the FTL secondary table entry for this first segment includes the space reduction flag.

For a segment of PPN continuous data, the storage device may not store the FTL level-1 table of the segment, but directly mark it in the entry of the FTL level-2 table of the segment, which reduces the storage space occupied by the FTL level-1 entry. Moreover, in this case, the FTL second-level table entry with the space reduction flag implies the information of the FTL first-level table of the segment, which improves the hit rate of the FTL table entry of the storage device to a certain extent.

In a possible implementation manner, the first segment corresponds to all continuous data, or the first segment corresponds to all invalid data.

In another possible implementation manner, the first segment corresponds to fully continuous data, and the FTL secondary table entry of the first segment includes: a start PPN of the first segment, where the start PPN is the first segment of the first segment The PPN corresponding to each LBA.

For fully continuous data, the starting PPN of the segment is stored in the entry of the FTL secondary table of the corresponding segment. When performing the data read operation, the target data can be obtained directly according to the LBA offset and the starting PPN, which improves the The hit rate of FTL entries improves the efficiency of data access.

In another possible implementation manner, the space reduction flag includes a first flag, the first flag includes a bit, the value of the first flag indicates that the first segment corresponds to fully continuous data, and the FTL entry of the first segment is reduced .

In another possible implementation manner, the space reduction flag includes a second flag, the second flag includes multiple bits, and the first undefined state among the multiple states indicated by the second flag is used to indicate that the first segment corresponds to full continuity data, and the FTL entry of the first segment is reduced.

In the above solution, the newly defined flag bit can be used as the space reduction flag, or the undefined state of the existing flag bit can be used as the space reduction flag, and the space reduction flag can be flexibly selected according to the actual situation.

In another possible implementation manner, the space reduction flag includes a second flag, the second flag includes multiple bits, and the second undefined state among the multiple states indicated by the second flag is used to indicate that the first segment corresponds to all invalid data, and the FTL entry of the first segment is reduced.

In another possible implementation manner, the space reduction flag includes a third flag, the third flag includes a bit, the value of the third flag indicates that the first segment corresponds to all invalid data, and the FTL entry of the first segment is reduced .

In another possible implementation manner, the space reduction flag includes a first mode, the first mode indicates that the first segment corresponds to all invalid data, and the FTL entry of the first segment is reduced.

In the above scheme, a newly defined flag bit or a new mode can be used as the space reduction flag, or the undefined state of the existing flag bit can be used as the space reduction flag, and the space reduction flag can be flexibly selected according to the actual situation.

In another possible implementation manner, the FTL entry processing method is executed when the storage device performs an input/output IO operation.

In another possible implementation manner, the FTL entry processing method is executed during an idle period of the storage device.

The processing of the FTL table entry can be performed during the IO operation or during the idle period of the storage device, which improves the work efficiency of the storage device.

In a fourth aspect, a method for reading data is provided, comprising: determining that the flash memory translation layer FTL secondary table entry of the segment where the target logical block address LBA of the target data is located includes a space reduction flag, and the space reduction flag indicates the corresponding first segment. The physical page number PPN is continuous; the target data is read according to the FTL secondary table entry of the first segment where the target LBA is located.

When reading data, you can first check the entry of the FTL secondary table of the target segment. When the secondary table entry of the segment includes the space reduction flag, the target data can be obtained directly from the secondary table entry of the segment without loading. The FTL first-level table of this segment improves the hit rate of the FTL table entry and improves the efficiency of data reading.

In a possible implementation manner, the space reduction flag includes a first flag, the first flag includes one bit, the value of the first flag indicates that the first segment corresponds to fully continuous data, and the FTL entry of the first segment is reduced.

In another possible implementation manner, the FTL secondary table entry of the first segment includes: the starting PPN of the first segment, and the starting PPN is the PPN corresponding to the first LBA of the first segment.

In another possible implementation manner, reading the target data according to the FTL secondary table entry of the first segment where the target LBA is located includes: acquiring the offset of the target LBA; The starting PPN is used, and the target data is read.

In the above solution, it can be determined that the target data corresponds to fully continuous data according to the space reduction flag of the FTL secondary table entry of the first segment where the target LBA is located. In this case, the starting PPN of the segment and the corresponding partial It is not necessary to obtain the FTL first-level table of the segment by moving to obtain the target data, which improves the efficiency of data reading.

In another possible implementation manner, reading the target data according to the FTL secondary table entry of the first segment where the target LBA is located includes: returning invalid data to the host.

When reading data, according to the space reduction flag of the FTL secondary table entry of the first segment where the target LBA is located, it can be directly determined that this segment corresponds to all invalid data, so all invalid data can be directly returned to the host without needing to The FTL first-level table obtains the PPN of the target LBA, which improves the efficiency of data reading.

A fifth aspect provides a data writing method, comprising: determining that the data to be written is fully contiguous data, and the physical data in the first segment of the flash memory translation layer FTL first-level table where the logical block address LBA of the fully contiguous data is located. The page number PPN is continuous; the FTL secondary table entry of the first segment is updated or established, and the FTL secondary table entry of the first segment includes a space reduction flag; and the fully continuous data is written.

When writing data, when it is determined that the data to be written is fully continuous data, the entry of the FTL secondary table of the segment can be directly updated, and the space reduction flag is included in the FTL secondary table entry of the segment, without the need for The FTL first-level table is then established or updated, which reduces the storage space occupied by the FTL table entry and facilitates the reading of data.

In another possible implementation manner, the FTL secondary table entry of the first segment includes: the starting PPN of the first segment, where the starting PPN is the PPN corresponding to the first LBA of the first segment.

In a sixth aspect, a storage device is provided, comprising: a determination module for determining that the physical page number PPN corresponding to the logical block address LBA in the first-stage flash memory translation layer FTL level table is continuous; an update module for updating Or create an FTL secondary table entry for the first segment, where the FTL secondary table entry for the first segment includes a space reduction flag.

In a possible implementation manner, the determining module is specifically configured to determine that the first segment corresponds to all continuous data, or to determine that the first segment corresponds to all invalid data.

In another possible implementation manner, the determining module determines that the first segment corresponds to fully continuous data; the FTL secondary table entry of the first segment includes: the starting PPN of the first segment, where the starting PPN is the first segment The first LBA corresponds to the PPN.

In another possible implementation manner, the determining module determines that the first segment corresponds to all invalid data; the space reduction flag includes a second flag, the second flag includes a plurality of bits, and the second non-valid data among the multiple states indicated by the second flag The definition state is used to indicate that the first segment corresponds to all invalid data, and the FTL entry of the first segment is reduced.

In another possible implementation manner, the determining module determines that the first segment corresponds to all invalid data; the space reduction flag includes a third flag, the third flag includes one bit, and the value of the third flag indicates that the first segment corresponds to all invalid data, And the FTL entry of the first paragraph is reduced.

In another possible implementation manner, the determining module determines that the first segment corresponds to all invalid data; the space reduction flag includes a first mode, the first mode indicates that the first segment corresponds to all invalid data, and the first segment corresponds to all invalid data. FTL entries have been reduced.

In the above solution, a newly defined flag bit or a new mode can be used as a space reduction flag, or an undefined state of an existing flag bit can be used as a space reduction flag, and the space reduction flag can be flexibly selected according to the actual situation.

In a seventh aspect, a data reading device is provided, the data reading device is applied to a storage device, and the device includes: a determining module for determining the flash memory conversion of the first segment where the target logical block address LBA of the target data is located The layer FTL secondary table entry includes a space reduction flag indicating that the physical page number PPN corresponding to the first segment is continuous; the reading module is configured to read target data according to the FTL secondary table entry of the first segment.

In another possible implementation manner, the apparatus further includes: an obtaining module, configured to obtain the offset of the target LBA; and the reading module is specifically configured to read the target data according to the offset and the starting PPN.

In another possible implementation manner, the read module is specifically configured to return invalid data to the host.

In an eighth aspect, a data writing device is provided, the data writing device is applied to a storage device, and the device includes: a determining module for determining that the data to be written is fully continuous data, the logical block address of the fully continuous data The physical page numbers PPN in the FTL first-level table of the flash conversion layer of the first segment where the LBA is located are consecutive; the update module is used to update or establish the FTL second-level table entry of the first segment, and the FTL second-level table entry of the first segment includes Space reduction flag; write module for writing fully contiguous data.

In a ninth aspect, a computer-readable medium is provided, where the computer-readable medium stores program codes for device execution, the program codes including flash memory control for executing the second aspect or any implementation manner of the second aspect method.

In a tenth aspect, a computer-readable medium is provided, where the computer-readable medium stores program codes for device execution, the program codes including an FTL table for executing the third aspect or any implementation manner of the third aspect item processing method.

In an eleventh aspect, a computer-readable medium is provided, and the computer-readable medium stores program code for execution by a device, the program code including data for executing the fourth aspect or any implementation manner of the fourth aspect read method.

In a twelfth aspect, a computer-readable medium is provided, where the computer-readable medium stores program code for execution by a device, the program code including data for executing the fifth aspect or any implementation manner of the fifth aspect write method.

A thirteenth aspect provides a computer program product, the computer program product comprising: computer program code, when the computer program code runs on the flash memory control device, the flash memory control device executes the second aspect or the second aspect. Flash memory control method in any implementation manner.

A fourteenth aspect provides a computer program product, the computer program product comprising: computer program code, which when the computer program code is executed on a storage device, causes the storage device to execute the third aspect or any one of the third aspects An FTL table entry processing method in an implementation manner.

A fifteenth aspect provides a computer program product, the computer program product comprising: computer program code, when the computer program code is run on a storage device, the storage device executes the fourth aspect or any one of the fourth aspect The data reading method in this implementation.

A sixteenth aspect provides a computer program product, the computer program product comprising: computer program code, when the computer program code is run on a storage device, the storage device executes the fifth aspect or any one of the fifth aspects The data writing method in this implementation.

A seventeenth aspect provides a chip, the chip includes a processor and a data interface, the processor reads an instruction stored in a memory through the data interface, and executes the second aspect or any implementation manner of the second aspect Flash control method in .

Optionally, as an implementation manner, the chip may further include a memory, the memory stores instructions, the processor is used to execute the instructions stored in the memory, and when the instructions are executed, the processor is used to execute the second aspect or the second aspect. The flash memory control method in any one of the implementations.

In an eighteenth aspect, a chip is provided, the chip includes a processor and a data interface, the processor reads instructions stored in a memory through the data interface, and executes the third aspect or any one of the implementation manners of the third aspect. FTL entry processing method in .

Optionally, as an implementation manner, the chip may further include a memory, the memory stores instructions, the processor is used to execute the instructions stored in the memory, and when the instructions are executed, the processor is used to execute the third aspect or the third aspect. The FTL entry processing method in any one of the implementations.

A nineteenth aspect provides a chip, the chip includes a processor and a data interface, the processor reads an instruction stored in a memory through the data interface, and executes any one of the fourth aspect or the fourth aspect. The data read method in .

Optionally, as an implementation manner, the chip may further include a memory, the memory stores instructions, the processor is used to execute the instructions stored in the memory, and when the instructions are executed, the processor is used to execute the fourth aspect or the fourth aspect. The data reading method in any one of the implementations.

A twentieth aspect provides a chip, the chip includes a processor and a data interface, the processor reads an instruction stored in a memory through the data interface, and executes any implementation manner of the fifth aspect or the fifth aspect The data write method in .

Optionally, as an implementation manner, the chip may further include a memory, the memory stores instructions, the processor is used to execute the instructions stored in the memory, and when the instructions are executed, the processor is used to execute the fifth aspect or the fifth aspect. The data writing method in any one of the implementations.

In a twenty-first aspect, an apparatus is provided, comprising: a processor and a memory, where the memory is used to store the computer program code, when the computer program code is executed on the processor, the apparatus causes the apparatus to execute a third The FTL entry processing method in any one of the implementation manners of the aspect or the third aspect.

In a twenty-second aspect, there is provided an apparatus, comprising: a processor and a memory, the memory is used for storing the computer program code, when the computer program code is executed on the processor, the apparatus causes the apparatus to execute the fourth The data reading method in the aspect or any one of the implementation manners of the fourth aspect.

In a twenty-third aspect, an apparatus is provided, comprising: a processor and a memory, the memory is used to store the computer program code, when the computer program code is executed on the processor, the apparatus causes the apparatus to execute the fifth A data writing method in any one of the implementation manners of the aspect or the fifth aspect.

Description of drawings

FIG. 1 is a schematic diagram of a multi-level flash memory translation layer FTL table entry;

2 is a schematic flowchart of a method for processing an FTL entry according to an embodiment of the present application;

3 is a schematic diagram of an FTL table entry according to an embodiment of the present application;

4 is a schematic diagram of an FTL secondary table entry of full continuous data according to an embodiment of the present application;

5 is a schematic diagram of an FTL secondary table entry of all invalid data according to an embodiment of the present application;

6 is a schematic flowchart of data access control according to an embodiment of the present application;

7 is a schematic flowchart of data write control according to an embodiment of the present application;

8 is a schematic diagram of a storage device according to an embodiment of the present application;

9 is a schematic diagram of another storage device according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a flash memory control device according to an embodiment of the present application;

11 is a schematic diagram of a data reading device according to an embodiment of the present application;

FIG. 12 is a schematic diagram of a data writing device according to an embodiment of the present application.

detailed description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. It is to be understood that the described embodiments are some, but not all, of the embodiments of the present application.

The technical solutions of the embodiments of the present application can be applied to various non-volatile memory (NVM) products, such as universal flash storage (UFS), embedded multi-media card (embedded multi-media card, eMMC), solid state disk (solid state disk, SSD), etc.

NAND is a non-volatile storage medium. NAND flash memory needs to be erased on a block-by-block basis, and new data can be written to the erased blocks, and each block has a limit on the number of times of erasure. In a storage device using NAND flash memory, due to the physical characteristics of NAND, it is necessary to maintain the logical block address (LBA) and physical page number (physical page number) through the flash translation layer (FTL) table entry. , PPN) mapping relationship to achieve the purpose of balancing NAND wear. Under normal circumstances, each entry (entry) of the FTL table uses 4 bytes (byte, B) to store a PPN, and a PPN corresponds to a 4KB address space, which means that the FTL table entry consumes an unprecedented amount of storage device capacity. 1/1000. Because the on-chip static random access memory (SRAM) of the storage device controller is small and cannot accommodate the complete FTL table entry, the FTL table generally adopts a multi-level mapping method.

Figure 1 is a schematic diagram of a multi-level FTL table. The multi-level FTL table uses a segmentation mechanism to equally divide the complete address space into multiple segments. Illustratively, the size of each segment may be 128, 256, 512, and so on. The FTL level 1 table directly corresponds to the conversion relationship between LBA and PPN. In the FTL first-level table, each entry (entry) indicates the PPN corresponding to a certain LBA. The FTL first-level table of each segment can be independently stored in NAND. Each segment of the FTL level-1 table corresponds to an entry of the FTL level-2 (level 2) table, and each entry in the level-2 table stores the position of the segment's FTL level-1 table in NAND.

For example, as shown in FIG. 1 , the size of a segment is 256 as an example (that is, the FTL level-1 table of each segment includes 256 mapping relationships between LBAs and PPNs). Exemplarily, for LBA 0-255, in the FTL first-level table of the segment pair, each entry indicates the PPN corresponding to the LBA, for example, the first entry indicates the physical page number corresponding to the logical block address LAB 0. is PPN 0. This segment corresponds to the first entry in the FTL second-level table, which stores the location where the FTL first-level table of LAB 0-255 is stored in NAND.

Multi-level FTL mapping can cache some FTL first-level entries in SRAM. When an entry misses, it needs to be loaded and replaced. According to the location of the segment's FTL first-level table stored in the FTL second-level table in NAND , read the required FTL first-level table, and swap in the segment that needs to be accessed currently in the SRAM. Loading and replacing table items will increase the read and write latency, reduce performance, and affect user experience.

To improve the hit rate of FTL entries, there are two main solutions. One is to increase the SRAM space inside the storage device controller to increase the number of FTL first-level tables that can be stored in the controller, thereby increasing the hit rate. However, expanding the SRAM increases the cost of the controller, and its benefits are limited. For example, for a storage device with a capacity of 256G, increasing the controller SRAM from 1MB to 2MB doubles the entries that can be stored in the SRAM, but the range of NAND that can be covered by an entry is only increased from 1GB to 2GB. And because expanding the SRAM will lead to increased cost, as well as increased power consumption of the storage device.

Another solution is to open up a space in the host memory (host memory), such as using a host performance booster (HPB), as the FTL table entry cache of the storage device. When data needs to be read and written, the PPN address information on the HPB cache is directly sent to the storage device. And, when the table entry is updated, the host obtains the latest table entry from the storage device.

With this approach, the host and storage device have frequent synchronization overhead. In addition, in some terminal devices, such as mobile phones, the host memory is also a bottleneck, and using the host memory to store the FTL mapping table is also a great challenge to the host memory capacity.

The embodiment of the present application provides a flash memory control method, which can directly perform data access control according to the information of the FTL second-level table, without frequently loading and replacing the FTL first-level table, improving the hit rate of FTL table entries, and improving the performance of the system. Illustratively, a two-level FTL table is used as an example to introduce the FTL table entry processing method in this embodiment of the present application. It should be understood that the descriptions such as the “FTL first-level table” and the “FTL second-level table” in the embodiments of the present application are only for distinguishing FTL table items of different levels. May be referred to as the "FTL Level 2 Table"; the "FTL Level 2 Table" for this application may also be referred to as the "FTL Level 1 Table".

The flash memory control method according to the embodiment of the present application mainly includes the processing of FTL entries and the reading and writing of data (data access or data writing).

FIG. 2 is a schematic flowchart of a method 200 for processing an FTL entry according to an embodiment of the present application. As shown in FIG. 2 , the method for processing an FTL entry in this embodiment of the present application includes steps S210 to S230. In the following, with reference to FIG. 2 , the method for processing an FTL entry in this embodiment of the present application will be described in detail.

S210, identifying feature data, and determining whether the data conforms to the space reduction feature.

Specifically, in some embodiments, the storage device determines that the PPN of the LBA address segment corresponding to a certain entry (for example, the "first entry" hereinafter) of the FTL secondary table is continuous. In this case, the corresponding space With the feature of reduction, the FTL first-level table can be reduced. This FTL first-level table may not occupy storage space, and is only marked in the entry corresponding to this section in the FTL second-level table.

Illustratively, each segment is 256 in size. For example, as shown in (a) of Figure 3, in the address segment of LBA0-255, the PPN 0 corresponding to LBA 0 points to page 1 in the NAND space, and the PPN 1 corresponding to LBA 1 points to the NAND space The page 2... The PPN 255 corresponding to LBA 255 points to page 256 in the NAND space, that is to say, the pages in the NAND space pointed to by the PPN corresponding to each LBA are continuous, that is, a logical block address LBA The corresponding physical page number PPN is continuous. In this case, the FTL first-level table of the segment of LBA 0-255 does not occupy storage space, and is only identified in the entry corresponding to the FTL second-level table LBA 0-255.

As shown in (b) of Figure 3, in the LBA0-255 address segment, the PPN corresponding to LBA 0 points to page 1 in the NAND space, the PPN corresponding to LBA 1 points to page 2 in the NAND space, and the corresponding PPN of LBA 2 points to page 2 in the NAND space. PPN points to page 3 in the NAND space; however, the pages in the NAND space pointed to by the PPN corresponding to LBA 3-255 are discontinuous, that is, in the first segment, the physical address corresponding to each logical block address is not Continuously, in this case, the FTL level-1 table cannot be reduced, and the complete FTL level-1 table of the first segment needs to be stored in the SRAM or NAND of the storage device.

In some embodiments, when the PPNs corresponding to a segment of data are continuous, and the segment of data is valid data, the segment of data may be called fully continuous data. In this case, the first entry corresponds to the valid data space.

In other embodiments, when the PPNs corresponding to a segment of data are continuous, and the segment of data is invalid data, the segment of data may be referred to as completely invalid data, and in this case, the first entry corresponds to an invalid data space.

S220, the data does not conform to the characteristics of space reduction, and an FTL first-level table is generated.

When the data does not conform to the space reduction feature, the existing multi-level FTL table entry technology is used to generate or update the FTL first-level table and the FTL second-level table, which will not be described in detail here for brevity.

S230, the data conforms to the space reduction feature, and is identified in the FTL secondary table. Wherein, the space reduction flag is included in the first entry of the FTL secondary table. The method for identifying the FTL secondary table according to the embodiment of the present application will be described in detail below with reference to FIG. 4 to FIG. 5 .

Exemplarily, in some embodiments, taking (a) in FIG. 3 as an example, the PPNs corresponding to LBA0-255 are continuous, which conforms to the space reduction feature in the above step S210. The FTL first-level table of LBA0-255 is stored, and is identified in the entry of the second-level table. FIG. 4 is an FTL secondary table entry identification method for full continuous data.

As shown in Fig. 4, the FTL secondary entry of the full continuous data includes the status flag and the start PPN of the segment. The starting PPN of the segment points to the PPN corresponding to the first LBA of the segment. For example, taking (a) in FIG. 3 as an example, in the secondary table entry of the segment, the starting PPN of the segment is PPN 0 corresponding to LBA 0, and PPN 0 points to page 1 of the NAND space.

In some embodiments, a first flag of 1 bit (bit) may be used to indicate that the segment corresponds to fully contiguous data. Exemplarily, when the value of the first flag is 1, it indicates that the current segment is full continuous data. Or, when the value of the first flag is 0, it indicates that the current segment is full continuous data.

It should be understood that the above-mentioned 1-bit first flag may be located at any position of the entry except the starting PPN, which is not limited in this embodiment of the present application.

In other embodiments, the first undefined state in the second flag can be used as the state flag of the fully continuous data, where the second flag includes multiple bits. For example, in the original secondary table entry, a 2-bit second flag is used to represent different states. These two bits can represent 4 different states. Exemplarily, when the value of these two bits is 11, it is the first undefined state. In this case, 11 can be used to indicate that the current segment is full continuous data.

Exemplarily, in other embodiments, taking (a) in FIG. 3 as an example, the data of the first segment is invalid data, and conforms to the space reduction feature in the above step S210, that is, the data of this segment is completely invalid. data. At this time, there is no need to store the FTL first-level table in the SRAM or NAND of the storage device. And, it is identified in the entry of the secondary table corresponding to this segment. FIG. 5 is an FTL secondary table entry identification method for all invalid data.

As shown in (a) of FIG. 5 , in some embodiments, the entry of the secondary table may use a 1-bit third flag to indicate that the data of the current segment is all invalid data. For example, when the value of the third flag is 1, it indicates that the data of the current segment is all invalid data; or, when the value of the third flag is 0, it indicates that the data of the current segment is all invalid data.

It should be understood that the above-mentioned 1-bit third flag may be located at any position of the entry except the first flag, which is not limited in this embodiment of the present application.

As shown in (b) of FIG. 5 , in other embodiments, the second undefined state in the second flag may be used as the state flag of all invalid data, where the second flag includes multiple bits. Exemplarily, the second flag of 2 bits is the original state identification bit, 2 bits can represent 4 different states, and the second undefined state among the four states can be used to represent that the data of the current segment is all invalid data. For example, 11 can be used to indicate that the data of the current segment is all continuous data, and 10 can be used to indicate that the data of the current segment is all invalid data.

As shown in (c) of FIG. 5 , in other embodiments, the entry of the secondary table may also use a first pattern (pattern) to indicate that the data of the current segment is all invalid data. For example, when the entry of the secondary table is "0xFFFFFFF", it means that the data of the current segment is all invalid data.

It should be understood that when the first mode is used to indicate that the data of the current segment is completely invalid data, the entry of the secondary table may also be identified by other modes, which is not limited in this embodiment of the present application.

By identifying the characteristic data and reducing the FTL entries that meet the space reduction feature, the storage space of the storage device can be saved, and the FTL first-level table does not need to be frequently replaced in the controller SRAM, which improves the hit rate of the FTL entry as a whole.

It should be understood that the method for processing FTL entries in this embodiment of the present application, in addition to reducing the FTL entries for the above-mentioned all continuous data or all invalid data, can also be applied to perform FTL entry processing on continuous data with other characteristics. reduction, which is not limited in this embodiment of the present application. For example, the FTL first-level table may be reduced for a segment of continuous PPN data with all 0s; for another example, the data of a specific pattern that is continuous for a segment of PPN may be reduced. It is not repeated here.

The FTL table entry processing method according to the embodiment of the present application is described in detail above with reference to FIG. 2 to FIG. 5 . The reduction method of the above FTL table entry can be performed at different stages of the data input and output (IO) process.

In some embodiments, the above-described method 200 may be performed when the storage device is idle. For example, the storage device may search for FTL entries in an idle period to determine whether the corresponding data conforms to the space reduction feature in the above method 200 .

For example, the NAND space pointed to by the PPN corresponding to the LBA address segment indicated by the first entry of the FTL secondary table is continuous, and the data is valid data, then the FTL primary table of this segment can no longer be stored, and the FTL of this segment is The entry (first entry) of the secondary table stores the starting PPN of the address segment, and is identified in the entry of the secondary table of this segment in the manner shown in FIG. 4 .

For example, if the NAND space pointed to by the PPN corresponding to the LBA address segment indicated by the first entry of the FTL secondary table is continuous, and the data is invalid data, then the FTL primary table of the address segment can no longer be stored, and in the segment's In the entry (first entry) of the FTL secondary table, identification is made in the entry of the FTL secondary table of the segment in the manner as shown in FIG. 5 .

By arranging the storage space in the idle period, and reducing the FTL entries that conform to the space reduction feature, the performance of the storage device when performing IO operations can be improved.

In other embodiments, the above-described method 200 may be performed when the storage device performs an IO operation.

For example, the storage device may perform the above method 200 during the process of performing the data writing operation. Exemplarily, in the process of data writing, the storage device recognizes that the NAND space pointed to by the PPN corresponding to a certain segment of the LBA address of the data to be written is continuous, then the FTL level-1 table of the segment can no longer be stored or updated, and The starting PPN of the address segment is stored in the entry (eg, the first entry) of the FTL secondary table of the segment, and is performed in the first entry of the secondary table of the segment in the manner shown in FIG. 4 . logo. The above method can be applied to scenarios where a large amount of sequential cold data is written, such as application (application, APP) installation, video, picture storage, and the like. The writing of a large amount of continuous data can meet the characteristics of the above-mentioned fully continuous data, and in these application scenarios, FTL entries can be greatly reduced.

For example, the storage device may perform the above-mentioned method 200 during the process of performing the data deletion operation. The deleted data is equivalent to the invalid data described above. Exemplarily, in the process of data deletion, the storage device recognizes that the address of the data to be deleted corresponds to a segment of the FTL entry, then the FTL level-1 table of the segment can no longer be stored or updated, and the FTL level-2 of the segment can be stored or updated. The table entry is identified, and the identification method is shown in Figure 5.

The above method can be applied to scenarios where a large number of continuous spaces are deleted, such as APP uninstallation, video, picture deletion, and the like. When deleting data, it can be directly marked in the entry of the corresponding segment of the FTL secondary table, and there is no need to update the FTL primary table.

Executing the above-mentioned FTL reduction method 200 while performing the IO operation can reduce the number of times the storage device scans the NAND space and improve the efficiency of data reading and writing.

FIG. 6 is a data access method according to an embodiment of the present application. The data access process of the flash memory control method according to the embodiment of the present application is described below with reference to FIG. 6 .

S410, the host (host) issues a read IO command (data access command). The storage device receives the read IO command from the host and starts to perform the data read operation.

S420, the storage device queries an entry (entry) corresponding to the FTL secondary table corresponding to the target LBA.

S430, determine whether the entry has a space reduction flag. If there is a space reduction flag, step S440 is performed, and if there is no space reduction flag, step S470 is performed.

Illustratively, the reduction flag includes a first flag, and the value of the first flag is a value for indicating fully contiguous data.

Illustratively, the reduction flag includes a third status flag bit, and the value of the third flag is a value for indicating all invalid data.

Illustratively, the reduction flag includes a second flag, and the value of the second flag is a value for indicating full-consecutive data or full-consecutive data.

Illustratively, the reduced flag includes a first pattern indicating all invalid data.

S440, according to the reduction flag of the entry, determine whether it is full continuous data.

Exemplarily, the entry includes a first flag, and the value of the first flag is 1, which determines that the segment corresponds to fully continuous data.

Exemplarily, the entry includes a first flag, and the value of the first flag is 0, which determines that the segment corresponds to fully continuous data.

Exemplarily, the entry includes a second flag, and the value of the second flag is 11, which determines that the segment corresponds to full continuous data.

When it is determined that the segment corresponds to fully continuous data, step S450 is performed; if it is determined that the segment corresponds to not fully continuous data, step S460 is performed.

S450, obtain the starting PPN from the FTL secondary table, calculate the corresponding offset, and read data from the NAND.

When it is determined that it is fully continuous data according to the reduction flag of the entry in the FTL secondary table, the starting PPN of the segment is obtained from the entry, and the corresponding offset is calculated.

Exemplarily, the target logical block address of the target data is LBA 30, which is located in a section of the FTL table LBA 0-255. It is determined by the space reduction flag in the entry of LBA 0-255 of the secondary table that the segment corresponds to fully continuous data, and the starting PPN of the segment obtained from the entry is PPN 0. The PPN 0 points to page n of the NAND space. The target logical block address is LBA 30, and the offset relative to the starting logical block address LBA 0 of the segment can be calculated as 30. Therefore, the target data can be read from page(n+30) of the NAND space.

S460, returning invalid data to the host.

In the embodiment of the present application, there are two types of reduction flags for the entry of the FTL secondary table, which are respectively used to identify all continuous data and all invalid data. When it is determined in step S440 that the data is not all continuous data according to the reduction flag, it can be determined that the segment corresponds to all invalid data.

In other embodiments, whether it is all invalid data may be further determined according to the reduction flag.

Exemplarily, the entry includes a third flag, and the value of the third flag is 1, which determines that the segment corresponds to all invalid data.

Exemplarily, the entry includes a third flag, and the value of the third flag is 0, which determines that the segment corresponds to all invalid data.

Exemplarily, the entry includes a second flag, and the value of the second flag is 10, which determines that the segment corresponds to all invalid data.

Exemplarily, the entry includes a first pattern that determines that the segment corresponds to all invalid data.

When it is determined that the data is all invalid, the storage device can directly return invalid data to the host.

S470: Read the FTL first-level table of the corresponding segment through the FTL second-level table.

When it is determined in step S430 that there is no reduction flag in the entry of the secondary table of the address segment where the target LBA is located, the data is read according to the existing multi-level FTL table entry data reading method, according to the entry in the FTL secondary table. The location where the stored FTL first-level table is located to obtain the FTL first-level table.

S480, read data through the PPN record corresponding to the target LBA in the FTL first-level table.

Through the flash memory control method of the embodiment of the present application, when reading data, for all continuous data or all invalid data, there is no need to load or replace the FTL first-level table in the SRAM, which improves the hit rate of the FTL table entry as a whole and improves the Efficiency of data access.

FIG. 7 is a data writing method according to an embodiment of the present application. The following describes the data writing process of the flash memory control method according to the embodiment of the present application with reference to FIG. 7 .

S310, the host (host) issues a write IO command (data write command). The storage device receives the write IO command from the host and starts to perform the data writing operation.

S320: Determine whether the data to be written is fully continuous data. The controller of the storage device will allocate a write address for the data to be written. In step S320, the storage device may determine whether the data to be written is fully continuous data according to the above method 200 according to the write address allocated by the controller. When it is determined that the data to be written is fully continuous data, step S330 is performed; when it is determined that the data to be written is not fully continuous data, step S340 is performed.

For example, the storage device determines that the PPN corresponding to the LBA address segment indicated by the first entry of the FTL secondary table where the LBA where the data to be written is located is continuous, and can determine that the current data to be written is fully continuous data.

For example, the storage device determines that the PPN corresponding to the LBA address segment indicated by the first entry of the FTL secondary table where the LBA where the data to be written is located is discontinuous, and can determine that the current data to be written is not fully continuous data.

S330, establish or update the FTL secondary table.

When it is determined that the data to be written is fully continuous data, the FTL first-level table of the currently written data may not be updated or saved, and the first entry of the corresponding FTL second-level table may be marked. In this case, the corresponding FTL secondary entry includes the space reduction flag and the starting PPN. The identification method of the FTL secondary table entry is shown in FIG. 4 , which will not be repeated here.

S340, establish or update the FTL primary table, and establish or update the FTL secondary table.

When it is determined that the data to be written is not completely continuous data, the method for updating or establishing the FTL entry is the same as that in the prior art. In this case, both the FTL first-level table and the FTL second-level table need to be updated, which will not be repeated here.

S350, write data. The storage device writes the data to be written into the storage unit of the storage device to complete the data writing process.

In some embodiments, log structured file systems (log structured file systems, LFS) can also be combined with the above-mentioned FTL entry processing method to further exert the effect of the above-mentioned FTL entry processing method.

The data update feature of LFS is out-of-place update (OPU). LFS will create a log header, and each update of data will be recorded in the header of the current log. Therefore, in LFS, a write operation can Multiple updates are written to the storage device consecutively.

LFS converts random IO writes into sequential writes, which makes it easier for data to meet the space reduction feature of the above-mentioned FTL entry processing method, which is conducive to better reduction of FTL entries and improves the hit rate of FTL entries.

The apparatus of the embodiment of the present application will be described below with reference to FIG. 8 to FIG. 11 .

FIG. 8 is a schematic diagram of a storage device according to an embodiment of the present application. As shown in FIG. 8 , the storage device in this embodiment of the present application includes a determination module 810 and an update module 820 .

The determining module 810 is configured to determine the module, configured to determine that the physical page numbers PPN corresponding to the logical block address LBA in the FTL level-1 table of the flash memory translation layer of the first segment are continuous.

The updating module 820 is configured to update the FTL level 2 table entry that will establish the first segment, where the FTL level 2 table entry of the first segment includes a space reduction flag.

In some embodiments, the storage device 800 can be used to execute the above-mentioned FTL entry processing method 200, wherein the determination module 810 can implement the function of step S210 in the above-mentioned method; the updating module 820 can implement the above-mentioned method from steps S220 to S220 Features of the S230. For the specific functions and beneficial effects of the determining module 810 and the updating module 820, reference may be made to the descriptions in the above methods, which are not repeated here for brevity.

FIG. 9 is a schematic diagram of another storage device according to an embodiment of the present application. As shown in FIG. 9 , the storage device of the embodiment of the present application includes a flash memory controller 910 and a NAND flash memory 920 .

The flash controller 910 is used to control the operation of the storage device. Wherein, the flash memory controller 910 may further include: an interface (interface) 911, a central processing unit (central processing unit, CPU) 912, a static random access device (static random access memory, SRAM) 913 and a NAND controller 914.

Among them, the interface 911 is specifically used to connect to the host and perform data transmission with the host. Exemplarily, the data transmission can be performed by a UFS method, an embedded multimedia card (embedded multimedia card, EMMC) method, or a high-speed serial computer expansion bus (peripheral component interconnect express, PCIE) method equal to the host computer.

The CPU 912 is specifically used to control the data interaction between the various modules or components of the storage device 900.

The SRAM 913 is a random access (random access memory, RAM) space inside the flash memory controller 910, and can be specifically used to store FTL entries and data.

The NAND controller 914 is specifically used to control and manage the NANA flash memory 920 of the storage device 900 .

It should be understood that the above-mentioned storage device 900 is only an example of the storage device of the embodiment of the present application. In other embodiments, the storage device of the storage device may be other storage devices besides the above-mentioned NAND flash memory 920, and when the above-mentioned NAND flash memory 920 is For other storage devices, the NAND controller 914 may also be the controller of the corresponding storage device. It should also be understood that the storage device may further include other modules, or other units, or other components, which are not limited in this embodiment of the present application.

FIG. 10 is a schematic structural diagram of a flash memory control device 1000 according to an embodiment of the present application. As shown in FIG. 10 , the flash memory control apparatus according to the embodiment of the present application includes a random access memory 1010 and a controller 1020 .

The random access memory 1010 is used to store the FTL secondary table.

The controller 1020 is used for data access control and data write control.

Specifically, the controller 1020 is configured to receive a data access command sent by the host, where the data access command includes the target LBA of the target data, and the PPN corresponding to the LBA address segment indicated by the first entry of the FTL secondary table is continuous and the first When the entry corresponds to the valid data space, the target data is accessed according to the target LBA and the starting PPN in the first entry. In this case, the controller 1020 may implement the functions of the various steps in the method 400 shown in FIG. 6 .

Specifically, the controller 1020 can also be configured to receive a data write instruction sent by the host, where the data write instruction includes data to be written; assign a write address to the data to be written, and perform data write control on the data to be written . In this case, the controller 1020 may implement the functions of each step in the method 300 shown in FIG. 7 .

In other embodiments, the controller 1020 may also process the FTL entries in the random access memory 1010 during the idle period. In this case, the controller 1020 may implement the various steps in the method 200 shown in FIG. 2 . function.

It should be understood that the flash memory control apparatus 1000 in this embodiment of the present application is equivalent to the flash memory controller 910 in the storage device shown in FIG. 9 , and it should also be understood that the flash memory controller 910 shown in FIG. 9 is only the flash memory control device shown in FIG. 10 . A possible implementation manner of the device, which is not limited in this embodiment of the present application.

FIG. 11 is a schematic diagram of a data reading apparatus 1100 according to an embodiment of the present application. As shown in FIG. 11 , the data reading device 1100 includes a determination module 1110 and a reading module 1120 .

The determining module 1110 is configured to determine that the FTL secondary table entry of the first segment where the target LBA of the target data is located includes a space reduction flag, where the space reduction flag indicates that the PPN corresponding to the first segment is continuous.

The reading module 1120 is configured to read the target data according to the FTL secondary table entry of the first segment.

The data reading apparatus 1000 in this embodiment of the present application can be used to implement the above method 400. Specifically, the determination module 1110 can implement steps S420, S430 and S440 of the above method; the reading module 1120 can implement steps S450 and S460 of the above method , S470 and S480. For the specific functions and beneficial effects of the determining module 1110 and the reading module 1120, reference may be made to the descriptions in the above methods, which are not repeated here for brevity.

The data reading apparatus 1000 can be applied to a storage device. Exemplarily, when the data reading apparatus 1000 is applied to the storage device shown in FIG. 9 , the functions of the determination module 1110 and the reading module 1120 may be implemented by the flash memory controller 910 or the flash memory control apparatus 1000 .

FIG. 12 is a schematic diagram of a data writing apparatus 1200 according to an embodiment of the present application. As shown in FIG. 12 , the data reading device 1200 includes a determining module 1210 , an updating module 1220 and a writing module 1230 .

The determining module 1210 is configured to determine that the data to be written is fully continuous data, and the PPNs of the FTL first-level table corresponding to the first segment where the LBA of the fully continuous data is located are continuous.

The updating module 1220 is configured to update or establish the FTL secondary table entry of the first segment, where the secondary table entry includes a space reduction flag.

The writing module 1230 is used for writing full continuous data.

The data reading apparatus 1200 in this embodiment of the present application can be used to implement the above method 300. Specifically, the determination module 1210 can implement step S320 of the above method; the update module 1220 can implement steps S330 and S340 of the above method; the writing module 1230 It can be used to implement step S350 of the above method. For the specific functions and beneficial effects of the determining module 1210, the updating module 1220, and the writing module 1230, reference may be made to the descriptions of the above methods, which are not repeated here for brevity.

The data reading apparatus 1200 can be applied to a storage device. Exemplarily, when the data reading apparatus 1200 is applied to the storage device shown in FIG. 9 , the functions of the determining module 1210 , the updating module 1220 and the writing module 1230 may be implemented by the flash memory controller 910 or the flash memory control apparatus 1000 .

Embodiments of the present application further provide a computer-readable medium, where the computer-readable medium stores a computer program (also referred to as code, or instruction), when it runs on the flash memory control device, so that the flash memory control device executes the above implementation Example of flash control method.

Embodiments of the present application further provide a computer-readable medium, where the computer-readable medium stores a computer program (also referred to as code, or instruction) when it runs on a storage device, causing the storage device to execute the above-mentioned embodiments. The FTL entry processing method.

Embodiments of the present application further provide a computer-readable medium, where the computer-readable medium stores a computer program (also referred to as code, or instruction) when it runs on a storage device, causing the storage device to execute the above-mentioned embodiments. data read method.

Embodiments of the present application also provide a computer-readable medium, where the computer-readable medium stores a computer program (also referred to as code, or instruction), when it runs on a storage device, to cause a computer to execute the above-mentioned embodiments. Data write method.

An embodiment of the present application also provides a chip system, including a memory and a processor, where the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the flash memory control device installed with the chip system The flash memory control method in the above embodiment is executed.

Wherein, the chip system may include an input circuit or interface for sending information or data, and an output circuit or interface for receiving information or data.

An embodiment of the present application further provides a chip system, including a memory and a processor, where the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that a storage device installed with the chip system executes the The FTL table entry processing method in the above embodiment.

An embodiment of the present application further provides a chip system, including a memory and a processor, where the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that a storage device installed with the chip system executes the The data reading and/or data writing methods in the above embodiments.

The term "and/or", which describes the association relationship of the associated objects, indicates that there can be three kinds of relationships, for example, A and/or B, which can mean: the existence of A alone, the existence of A and B at the same time, the case of the existence of B alone, where A , B can be singular or plural. The character "/" generally indicates that the associated objects are an "or" relationship.

It is to be understood that reference throughout the specification to "some embodiments" or "an embodiment" means that a particular feature, structure or characteristic associated with the embodiments is included in at least one embodiment of the present application. Thus, appearances of "in some embodiments" or "in an embodiment" in various places throughout this specification are not necessarily necessarily referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present application, the size of the sequence numbers of the above-mentioned processes does not mean the sequence of execution, and the execution sequence of each process should be determined by its functions and internal logic, and should not be dealt with in the embodiments of the present application. implementation constitutes any limitation.

Those of ordinary skill in the art can realize that, in combination with the method steps described in the embodiments disclosed herein, they can be implemented in electronic hardware, computer software, or a combination of the two, in order to clearly illustrate the interchangeability of hardware and software In the foregoing specification, steps of various embodiments have been described generally in terms of functionality. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Persons of ordinary skill in the art may use different methods of implementing the described functionality for each particular application, but such implementations should not be considered beyond the scope of this application.

Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in connection with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware accomplish. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each particular application, but such implementations should not be considered beyond the scope of this application.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and module described above can refer to the corresponding process in the foregoing method embodiments, which is not repeated here.

In the several embodiments provided in this application, it can be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are only illustrative. For example, the division of the modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or modules, and may be in electrical, mechanical or other forms.

The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional module in each embodiment of the present application may be integrated in one processing unit, or each module may exist physically alone, or two or more modules may be integrated in one unit.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited to this. should be covered within the scope of protection of this application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

A flash memory control device, characterized in that it includes:

Random access memory, used to store the flash translation layer FTL secondary table;

Controller for:

receiving a data access instruction sent by the host, where the data access instruction includes the target logical block address LBA of the target data;

In the case that the physical page numbers PPN corresponding to the LBA address segment indicated by the first entry of the FTL secondary table are consecutive, and the first entry corresponds to the valid data space, according to the target LBA and the first The starting PPN in the entry accesses the target data, and the starting PPN is the PPN corresponding to the first LBA in the LBA address segment indicated by the first entry.
The device according to claim 1, wherein the physical page numbers PPN corresponding to the LBA address segment indicated by the first entry of the FTL secondary table are consecutive, and the first entry corresponds to the invalid data space case, the controller is also used to:

Sending indication information to the host, where the indication information is used to indicate that the data access is invalid.
The device according to claim 1 or 2, wherein the controller is specifically used for:

Obtain the offset of the target LBA, where the offset of the target LBA is the difference between the target LBA and the first LBA in the LBA address segment indicated by the first entry;

The target data is accessed based on the offset and the starting PPN.
The device according to claim 3, wherein the controller is specifically configured to:

According to the offset and the starting PPN, determine a target PPN corresponding to the target LBA of the target data, where the target PPN is the sum of the starting PPN and the offset;

The target data is accessed according to the target PPN.
The device according to any one of claims 1-4, wherein the controller is further configured to:

receiving a data write instruction sent by the host, where the data write instruction includes data to be written;

Allocate a write address for the data to be written;

Data write control is performed on the data to be written.
The device according to claim 5, wherein the controller is specifically configured to:

Determine that the PPNs corresponding to the LBA address segment indicated by the first entry where the write address is located are continuous;

The starting PPN is recorded in the first entry.
The apparatus according to any one of claims 1-6, wherein the first entry includes a space reduction flag, and the space reduction flag is used to indicate that the first entry corresponds to a valid data space, Or the space reduction flag is used to indicate that the first entry corresponds to invalid data space.
A flash memory control method, characterized in that the method comprises:

receiving a data access instruction sent by the host, where the data access instruction includes the target logical block address LBA of the target data;

In the case that the physical page numbers PPN corresponding to the LBA address segment indicated by the first entry of the flash translation layer FTL secondary table are consecutive, and the first entry corresponds to the valid data space, according to the target LBA and the third The starting PPN in an entry accesses the target data, and the starting PPN is the PPN corresponding to the first LBA in the LBA address segment indicated by the first entry.
The method according to claim 8, wherein the method further comprises:

In the case that the physical page number PPN corresponding to the LBA address segment indicated by the first entry of the FTL secondary table is continuous, and the first entry corresponds to the invalid data space, send indication information to the host, the indication information Used to indicate that the data access is invalid.
The method according to claim 8 or 9, wherein the accessing the target data according to the target LBA and the starting PPN in the first entry comprises:

Obtain the offset of the target LBA, where the offset of the target LBA is the difference between the target LBA and the first LBA in the LBA address segment indicated by the first entry;

The target data is accessed based on the offset and the starting PPN.
The method according to claim 10, wherein the accessing the target data according to the offset and the starting PPN comprises:

According to the offset and the starting PPN, determine a target PPN corresponding to the target LBA of the target data, where the target PPN is the sum of the starting PPN and the offset;

The target data is accessed according to the target PPN.
The method according to any one of claims 8-11, wherein the method further comprises:

receiving a data write instruction sent by the host, where the data write instruction includes data to be written;

Allocate a write address for the data to be written;

Data write control is performed on the data to be written.
The method according to claim 12, wherein the performing data write control on the to-be-written data comprises:

Determine that the PPNs corresponding to the LBA address segment indicated by the first entry where the write address is located are continuous;

The starting PPN is recorded in the first entry.
The method according to any one of claims 8-13, wherein: the first entry includes a space reduction flag, and the space reduction flag is used to indicate that the first entry corresponds to a valid data space, Or the space reduction flag is used to indicate that the first entry corresponds to invalid data space.
A chip, the chip includes a processor, a memory and a data interface, the processor reads the instructions stored on the memory through the data interface, and executes the flash memory according to any one of claims 8-14 Control Method.