WO2022012312A1 - 一种监控内存带宽的方法及装置 - Google Patents

一种监控内存带宽的方法及装置 Download PDF

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Publication number
WO2022012312A1
WO2022012312A1 PCT/CN2021/102689 CN2021102689W WO2022012312A1 WO 2022012312 A1 WO2022012312 A1 WO 2022012312A1 CN 2021102689 W CN2021102689 W CN 2021102689W WO 2022012312 A1 WO2022012312 A1 WO 2022012312A1
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Prior art keywords
volatile memory
process group
memory bandwidth
memory
processor core
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PCT/CN2021/102689
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English (en)
French (fr)
Inventor
陈晓
马剑涛
黄凯耀
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华为技术有限公司
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Publication of WO2022012312A1 publication Critical patent/WO2022012312A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory

Definitions

  • the embodiments of the present application relate to the field of computers, and in particular, to a method and apparatus for monitoring memory bandwidth.
  • a server can run multiple processes of different tenants, and multiple processes share various resources of the server (such as computing resources, storage resources and memory resources, etc.) to improve the resource utilization of the server Rate.
  • resource sharing may introduce unfair performance issues. For example, processes of the same priority get different resources.
  • a process with a low priority occupies a large amount of resources, and a process with a high priority cannot obtain sufficient resources, which affects the tenant's business and reduces the user experience.
  • a resource control group (control group, cgroup) technology is used to divide multiple processes into different process groups, and different process groups use different resources (such as computing resources, storage resources, and memory resources).
  • resource director technology is used to identify the process that occupies a large amount of memory bandwidth of volatile memory and limit the memory bandwidth of the process occupying volatile memory to ensure that other processes obtain sufficient memory resources.
  • non-volatile memory Because the memory bandwidth of non-volatile memory (NVM) is much lower than that of volatile memory. In a multi-tenant cloud environment, the competition for memory bandwidth of non-volatile memory is more intense than that of volatile memory, which is likely to cause service degradation or even interruption. However, since the non-volatile memory does not provide the memory bandwidth limitation function, the resource provisioning technology cannot realize the monitoring and limitation of the memory bandwidth of the non-volatile memory. Therefore, how to monitor the memory bandwidth of non-volatile memory is an urgent problem to be solved.
  • the embodiments of the present application provide a method and device for monitoring memory bandwidth, which implements monitoring the memory bandwidth of non-volatile memory with a process group as the granularity, and further uses the memory bandwidth size of non-volatile memory as the limit of non-volatile memory. Memory based on memory bandwidth.
  • a method for monitoring memory bandwidth is provided, which is used for monitoring the memory bandwidth of a non-volatile memory.
  • the method includes: the processor core obtains the memory bandwidth size used by the process group to access the volatile memory in a preset period, and counts the memory operations performed by the process group in the preset period, and then according to the memory bandwidth size and the statistical data
  • the memory operation calculates the size of the first memory bandwidth used by the process group to access non-volatile memory.
  • the memory operations here include non-volatile memory operations and volatile memory operations.
  • the processor core estimates the memory bandwidth used by the process group to access the volatile memory based on the non-volatile memory operations, volatile memory operations and the memory bandwidth used by the process group to access the volatile memory within the preset cycle.
  • the memory bandwidth of non-volatile memory is monitored at the granularity of process group, and then the memory bandwidth of non-volatile memory is used as the basis for limiting the memory bandwidth of non-volatile memory.
  • a process group includes at least one process.
  • a process group may be a container or a virtual machine. All processes contained in a process group can be run by a container or a virtual machine.
  • the processes included in one process group may be run by multiple containers or multiple virtual machines. That is, a process group contains processes that are processes in multiple containers. Alternatively, a process group contains processes that are in multiple virtual machines.
  • calculating the first memory bandwidth size used by the process group to access the non-volatile memory according to the memory bandwidth size and statistical memory operations including: determining the process by the processor core according to the memory address accessed by the memory operation The ratio of the access amount of the group accessing the non-volatile memory and the access amount of the process group accessing the volatile memory; the first memory bandwidth size used by the process group accessing the non-volatile memory is calculated according to the memory bandwidth size and ratio. Because the memory address accessed by the memory operation includes the memory address accessed by the non-volatile memory operation and the memory address accessed by the volatile memory operation. The memory type and memory size of the memory accessed by the memory operation can be determined according to the memory address accessed by the memory operation.
  • Memory types include non-volatile memory and volatile memory.
  • the memory size includes the memory size of the process group accessing volatile memory and the memory size of the process group accessing non-volatile memory.
  • the processor core determines the ratio of the access amount of the process group accessing the non-volatile memory to the access amount of the process group accessing the volatile memory according to the memory size and memory type of the memory operation. Understandably, the access amount of the process group accessing the non-volatile memory is the memory size of the process group accessing the non-volatile memory.
  • the access amount of the process group accessing the volatile memory is the memory size of the process group accessing the volatile memory.
  • the memory operations performed within the preset period are all or part of the memory operations within the preset period.
  • the method further includes: if the size of the first memory bandwidth of the non-volatile memory is greater than or equal to the size of the non-volatile memory Volatile memory bandwidth threshold, which sets the memory bandwidth limit of the process group.
  • the non-volatile memory bandwidth threshold is the maximum memory bandwidth that the process group is allowed to use when accessing non-volatile memory. Therefore, the memory bandwidth used by the process group to access the volatile memory is controlled by restricting measures, and the memory bandwidth used by the process group to access the non-volatile memory is indirectly limited. Avoid excessive use of non-volatile memory bandwidth by process groups, containers or virtual machines, affecting other process groups, containers or virtual machines from being unable to access non-volatile memory, and solve business performance degradation caused by adjacent interference fault propagation. Interruption problem.
  • Setting the memory bandwidth limit of the process group includes one or more of the following: adjusting the first volatile memory bandwidth threshold of the process group to a second volatile memory bandwidth threshold, where the first volatile memory bandwidth threshold is greater than the second volatile memory bandwidth threshold.
  • the volatile memory bandwidth threshold, the first volatile memory bandwidth threshold and the second volatile memory bandwidth threshold all refer to the maximum value of the memory bandwidth that is allowed to be used by the process group accessing the volatile memory. Since the maximum memory bandwidth of the volatile memory that is allowed to be used by the process group to access the volatile memory is reduced, the total memory bandwidth of the volatile memory and the non-volatile memory used by the process group is also reduced. The memory bandwidth of the non-volatile memory used by the local process group is also reduced, and the implementation limits the memory bandwidth of the non-volatile memory to an arbitrary value.
  • the processes included in the process group are migrated from the first processor core running the process group to the second processor core. Since the number of processes included in the process group running by the processor core is reduced, the memory operations of the process group on volatile memory and non-volatile memory are reduced, and the process group uses volatile memory and non-volatile memory. The total memory bandwidth of the memory is also reduced, and the memory bandwidth of the non-volatile memory indirectly used by the process group is also reduced, so that the memory bandwidth of the non-volatile memory is limited to an arbitrary value.
  • the first time slice of the process group is adjusted to the second time slice, the first time slice is greater than the second time slice, and both the first time slice and the second time slice are the length of time that the process group occupies the first processor core. Since the time that the process group occupies the processor core is shortened, the memory operations of the process group on the volatile memory and the non-volatile memory are reduced, and the process group uses the total memory of the volatile memory and the non-volatile memory. The size of the bandwidth is also reduced, and the memory bandwidth of the non-volatile memory used indirectly by the process group is also reduced, so that the memory bandwidth of the non-volatile memory is limited to an arbitrary value.
  • the volatile memory bandwidth threshold of the process group is adjusted to the second volatile memory bandwidth threshold, when the second memory bandwidth of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth
  • the volatile memory bandwidth threshold is used to migrate the processes included in the process group from the first processor core running the process group to the second processor core.
  • the first processor core and the second processor core belong to one or more NUMA nodes in a non-uniform memory access (non-uniform memory access, NUMA) system.
  • the processes included in the process group are migrated from the first processor core running the process group to the second processor core, when the third memory bandwidth size of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth Volatile memory bandwidth threshold, adjust the first time slice of the process group to the second time slice.
  • the dynamic adjustment method can precisely control the memory bandwidth of the non-volatile memory to a specific value, avoid service performance degradation or even interruption, and reduce resource deployment costs.
  • the memory bandwidth of the non-volatile memory is limited, if the memory bandwidth of the non-volatile memory monitored by the processor core is less than the non-volatile memory bandwidth threshold, the restriction on the process group's access to the volatile memory can be lifted. Indirectly increases the memory bandwidth used by the process group to access non-volatile memory, so that the process group has sufficient available resources.
  • the method further includes: when the fourth memory bandwidth size of the non-volatile memory is smaller than the non-volatile memory bandwidth threshold, changing the The second time slice of the process group is adjusted to the first time slice.
  • the time that the process group occupies the processor core increases, the memory operations of the process group on volatile memory and non-volatile memory increase accordingly, and the process group uses the total memory of volatile memory and non-volatile memory.
  • the bandwidth is also increased, and the memory bandwidth of the non-volatile memory indirectly used by the process group is also increased, so that the process group has sufficient available resources.
  • the method further includes: when the fifth memory bandwidth size of the non-volatile memory is smaller than the non-volatile memory bandwidth threshold, setting the The processes contained in the process group are migrated from the second processor core to the first processor core.
  • the memory operations of the process group on volatile memory and non-volatile memory increase accordingly, and the process group uses volatile memory and non-volatile memory.
  • the total memory bandwidth size of the memory also increases, and the memory bandwidth of the non-volatile memory indirectly used by the process group also increases, so that the process group has sufficient available resources.
  • the method further includes: when the sixth memory bandwidth size of the non-volatile memory is smaller than the non-volatile memory bandwidth Memory bandwidth threshold, adjust the second volatile memory bandwidth threshold of the process group to the first volatile memory bandwidth threshold. Since the maximum memory bandwidth of the volatile memory used by the process group is increased, the total memory bandwidth of the volatile memory and non-volatile memory used by the process group also increases, and indirectly the non-volatile memory used by the process group is increased. The memory bandwidth of volatile memory is also increased, so that the process group has sufficient resources available.
  • non-volatile memory bandwidth threshold is set through the first file system interface.
  • the first volatile memory bandwidth threshold and the second volatile memory bandwidth threshold are set through the second file system interface.
  • a method for limiting memory bandwidth including: if the size of the first memory bandwidth used by a process group to access non-volatile memory within a preset period is greater than or equal to a non-volatile memory bandwidth threshold, The first volatile memory bandwidth threshold of the group is adjusted to the second volatile memory bandwidth threshold, and the non-volatile memory bandwidth threshold is the maximum memory bandwidth allowed by the process group to access non-volatile memory.
  • the volatile memory bandwidth threshold is greater than the second volatile memory bandwidth threshold.
  • the first volatile memory bandwidth threshold and the second volatile memory bandwidth threshold both refer to the maximum memory bandwidth that the process group is allowed to use when accessing volatile memory.
  • the group includes at least one process; when the second memory bandwidth size of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold, the process included in the process group is migrated from the first processor core running the process group to the second process device core.
  • the dynamic adjustment method is used to control the volatile memory bandwidth used by the process group to access the volatile memory, and indirectly limit the memory bandwidth of the non-volatile memory to an arbitrary value to avoid excessive use of the process group, container or virtual machine.
  • the non-volatile memory bandwidth can affect other process groups, containers or virtual machines from being unable to access the non-volatile memory, which solves the problem of business performance degradation or even interruption caused by the proliferation of adjacent interference faults.
  • the method further includes: when the third memory bandwidth size of the non-volatile memory is large If it is greater than or equal to the non-volatile memory bandwidth threshold, adjust the first time slice of the process group to the second time slice.
  • the first time slice is greater than the second time slice, and both the first time slice and the second time slice are occupied by the process group. The duration of the first processor core.
  • the method further includes: when the fourth memory bandwidth size of the non-volatile memory is smaller than the non-volatile memory bandwidth threshold, changing the The second time slice of the process group is adjusted to the first time slice.
  • the method further includes: when the fifth memory bandwidth size of the non-volatile memory is smaller than the non-volatile memory bandwidth threshold, setting the The processes contained in the process group are migrated from the second processor core to the first processor core.
  • the method further includes: when the sixth memory bandwidth size of the non-volatile memory is smaller than the non-volatile memory bandwidth Memory bandwidth threshold, adjust the second volatile memory bandwidth threshold of the process group to the first volatile memory bandwidth threshold.
  • an apparatus for monitoring memory bandwidth has the function of implementing the behavior in the method example of the first aspect.
  • the functions can be implemented by hardware, or can be implemented by hardware executing corresponding software.
  • the hardware or software includes one or more modules corresponding to the above functions.
  • the device for monitoring memory bandwidth includes: an acquisition unit, a monitoring unit, and a limiting unit.
  • the acquisition unit is used to acquire the memory bandwidth used by the process group to access the volatile memory in the preset period, and to count the memory operations performed by the process group in the preset period, and the memory operations include non-volatile memory operations and
  • the process group includes at least one process.
  • the monitoring unit is configured to calculate the size of the first memory bandwidth used by the process group to access the non-volatile memory according to the size of the memory bandwidth and the statistical memory operations.
  • the limiting unit is configured to set the memory bandwidth limit of the process group if the size of the first memory bandwidth is greater than or equal to the non-volatile memory bandwidth threshold, and the non-volatile memory bandwidth threshold is the non-volatile memory that the process group is allowed to use when accessing the non-volatile memory.
  • the maximum value of the memory bandwidth may perform the corresponding functions in the method examples of the first aspect. For details, refer to the detailed descriptions in the method examples, which will not be repeated here.
  • an apparatus for limiting memory bandwidth has the function of implementing the behavior in the method example of the second aspect.
  • the functions can be implemented by hardware, or can be implemented by hardware executing corresponding software.
  • the hardware or software includes one or more modules corresponding to the above functions.
  • the device for limiting memory bandwidth includes an acquisition unit and a limiting unit. The obtaining unit is configured to obtain the memory bandwidth size used by the process group to access the non-volatile memory in a preset period.
  • the limiting unit is configured to restrict the first volatile memory of the process group to the value of the
  • the bandwidth threshold is adjusted to the second volatile memory bandwidth threshold
  • the non-volatile memory bandwidth threshold is the maximum memory bandwidth that is allowed to be used by a process group accessing non-volatile memory
  • the first volatile memory bandwidth threshold is greater than the second volatile memory bandwidth threshold.
  • the volatile memory bandwidth threshold, the first volatile memory bandwidth threshold and the second volatile memory bandwidth threshold all refer to the maximum memory bandwidth allowed to be used by a process group accessing volatile memory, and the process group includes at least one process.
  • the limiting unit is further configured to migrate the processes included in the process group from the first processor core running the process group to the second processor core when the second memory bandwidth size of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold.
  • Two processor cores The limiting unit is further configured to adjust the first time slice of the process group to the second time slice, when the third memory bandwidth size of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold. greater than the second time slice, the first time slice and the second time slice are both the duration of the process group occupying the first processor core.
  • a processor in a fifth aspect, includes a plurality of processor cores, and the processor cores are configured to execute the method for monitoring memory bandwidth in the first aspect or any possible design of the first aspect.
  • the processor core may execute the operation steps of the method executed by the first processor core in the method example of the first aspect. For details, refer to the detailed description in the method example, which will not be repeated here.
  • a processor in a sixth aspect, includes a plurality of processor cores, and the processor cores are configured to execute the method for limiting memory bandwidth in the second aspect or any possible design of the second aspect.
  • the processor core may execute the operation steps of the method executed by the second processor core in the method example of the second aspect. For details, refer to the detailed description in the method example, which will not be repeated here.
  • a server in a seventh aspect, includes at least one processor according to the fifth aspect and a main memory, the processor includes a plurality of processor cores, each processor core is configured to execute the above-mentioned first Operation steps of the method for monitoring memory bandwidth in the aspect or any possible implementation manner of the first aspect.
  • a server in an eighth aspect, includes at least one processor according to the sixth aspect and a main memory, the processor includes a plurality of processor cores, each processor core is configured to execute the above-mentioned second Operation steps of the method for limiting memory bandwidth in any possible implementation manner of the aspect or the second aspect.
  • a computer-readable storage medium comprising: computer software instructions; when the computer software instructions are executed in the server, the server executes the first aspect or any possible implementation manner of the first aspect. steps of the method.
  • a computer-readable storage medium comprising: computer software instructions; when the computer software instructions are executed in the server, the server is made to execute as described in the second aspect or any possible implementation manner of the second aspect steps of the method.
  • An eleventh aspect provides a computer program product that, when the computer program product runs on a computer, causes the computer to execute the operation steps of the method described in the first aspect or any possible implementation manner of the first aspect.
  • a twelfth aspect provides a computer program product that, when the computer program product runs on a computer, causes the computer to execute the operation steps of the method described in the second aspect or any possible implementation manner of the second aspect.
  • the present application may further combine to provide more implementation manners.
  • FIG. 1 is a simplified schematic diagram of a cloud environment provided by an embodiment of the present application
  • FIG. 2 is a flowchart of a method for monitoring memory bandwidth provided by an embodiment of the present application
  • FIG. 3 is a flowchart of a method for monitoring memory bandwidth provided by an embodiment of the present application.
  • FIG. 4 is a flowchart of a method for monitoring memory bandwidth provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a process migration provided by an embodiment of the present application.
  • FIG. 6 is a flowchart of a method for limiting memory bandwidth provided by an embodiment of the present application.
  • FIG. 7 is a flowchart of a method for limiting memory bandwidth provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a process for dynamically limiting memory bandwidth provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of the composition of an apparatus for monitoring memory bandwidth provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of the composition of a device for limiting memory bandwidth provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of the composition of a server according to an embodiment of the present application.
  • Cloud environment is an entity that utilizes basic resources to provide cloud services to users under the cloud computing model.
  • the cloud environment 100 includes a cloud data center 110 and a cloud service platform 120 .
  • the cloud data center 110 includes a large number of basic resources (including computing resources 111 , storage resources 112 and memory resources 113 ) owned by the cloud service provider.
  • Computing resources 111 may be a number of computing devices (eg, servers).
  • the computing device includes multiple processors, such as processor 1111 and processor 1112 shown in FIG. 1 .
  • the processor 1111 is the control center of the computing device.
  • the processor 1111 is a central processing unit (central processing unit, CPU), including one processor core or multiple processor cores, such as processor core 0 and processor core 1 shown in FIG. 1 .
  • the processor 1111 may also be a specific integrated circuit (application specific integrated circuit, ASIC), or be configured as one or more integrated circuits, for example: one or more digital signal processors (DSP), or , one or more field programmable gate arrays (field programmable gate array, FPGA).
  • DSP digital signal processors
  • FPGA field programmable gate array
  • Processor core 0 and processor core 1 may refer to physical processor cores or logical processor cores in processor 1111 .
  • the processor 1111 may perform various functions of the computing device by running or executing software programs stored in the storage resource 112 and calling data stored in the storage resource 112 and the memory resource 113 .
  • the processor 1112 may have the same physical form as the processor 1111 , or may have a different physical form from the processor 1111 .
  • the processor 1112 is a processing chip with computing capability, and is used to share the running process of the processor 1111 to reduce the computational burden of the processor 1111 .
  • the memory resource 113 includes a non-volatile memory 1131 and a volatile memory 1132 .
  • Volatile memory includes random access memory (RAM).
  • RAM random access memory
  • Non-volatile memory has non-volatile, byte-by-byte access, high storage density, low energy consumption, and read and write performance close to dynamic random access memory (DRAM), but the read and write speed is asymmetric, and the read and write Faster than write, limited lifespan. When the current is turned off, the data stored in the non-volatile memory does not disappear.
  • Common non-volatile memories include phase change memory (PCM), magnetoresistive RAM (MRAM), resistive/resistive RAM (RRAM), ferroelectric RAM, FeRAM), racetrack memory, and graphene memory.
  • the storage resource 112 may be read-only memory (ROM) or other types of static storage devices that can store static information and instructions, random access memory (RAM), or other types of static storage devices that can store static information and instructions.
  • ROM read-only memory
  • RAM random access memory
  • Other types of dynamic storage devices for information and instructions which may also be electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or Other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage medium or other magnetic storage device, or capable of being used to carry or store desired in the form of instructions or data structures Program code and any other medium that can be accessed by a computer, but is not limited thereto.
  • EEPROM electrically erasable programmable read-only memory
  • CD-ROM compact disc read-only memory
  • Other optical disc storage optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.),
  • the storage resource 112 may exist independently, or may be connected to the computing resource 111 through a communication bus.
  • the storage resource 112 may also be integrated with the computing resource 111, which is not limited.
  • the communication bus may be an industry standard architecture (ISA) bus, a peripheral component (PCI) bus, or an extended industry standard architecture (EISA) bus, or the like.
  • ISA industry standard architecture
  • PCI peripheral component
  • EISA extended industry standard architecture
  • the bus can be divided into address bus, data bus, control bus and so on.
  • the storage resource 112 is also used to store the software program for executing the solution of the present application, and the execution is controlled by the computing resource 111.
  • the user can access various services (eg, financial services, game services, etc.) provided by the cloud service platform 120 through the terminal device 130 .
  • various services eg, financial services, game services, etc.
  • the computing device runs processes 114 of multiple services of different users, the processes of multiple services share basic resources (eg, computing resources 111 , storage resources 112 , and memory resources 113 , etc.).
  • the resource control group (cgroup) technology is used to divide multiple processes into different process groups, and different process groups use different resources (such as computing resources). , storage resources, and memory resources).
  • a process group includes at least one process.
  • a resource control group is a resource control mechanism that divides all processes in the operating system into groups, and all process groups are organized in a hierarchical structure.
  • Each process group specifies a set of access resources (eg, computing resources, storage resources, and memory resources). Different process groups access different resources. For example, processes in different process groups access memory with different memory sizes and memory with different memory bandwidths.
  • the system administrator can configure the processes included in each process group through the first file system interface.
  • the first file system interface is used to configure the processes included in the process group.
  • a user's application process can be divided into the same process group, or can be divided into different process groups.
  • a process group can contain processes of the same application or processes of different applications.
  • the processor cores have access to both volatile and non-volatile memory when running the processes contained in the process group.
  • resource director technology is used to identify a process that occupies a large amount of memory bandwidth of volatile memory and limit the memory bandwidth of the process occupied by volatile memory, so as to ensure that other processes obtain sufficient memory resources. Because the non-volatile memory does not provide the memory bandwidth limit function, the resource provisioning technology cannot realize the monitoring and limitation of the memory bandwidth of the non-volatile memory.
  • This embodiment provides a method for monitoring memory bandwidth, which estimates the memory bandwidth used by a process group to access non-volatile memory according to the memory bandwidth used by a process group to access volatile memory and memory operations within a preset period, In this way, the memory bandwidth of the non-volatile memory is monitored at the granularity of the process group, and the memory bandwidth of the non-volatile memory is used as the basis for limiting the memory bandwidth.
  • the first processor core acquires the memory bandwidth used by the process group to access the volatile memory in the preset period, and counts the memory operations performed by the process group in the preset period.
  • the kernel is the core of an operating system, responsible for managing the system's processes, memory, device drivers, files and network systems, and determines the performance and stability of the system.
  • the memory bandwidth monitor (MBM) technology can be used to view the memory management information in the kernel to obtain the memory used by the process group to access volatile memory within a preset period Bandwidth size.
  • the preset period may be 1 second.
  • Memory operations include non-volatile memory operations and volatile memory operations.
  • the memory operation performed by the process group within the preset period may be understood as the memory address accessed by the memory operation performed by the process group within the preset period.
  • the first processor core monitors the read and write interfaces of the file system, collects memory operations on the memory in the system through the read and write interfaces of the file system within a preset period, and obtains memory addresses accessed by the memory operations. Since the system includes non-volatile memory and volatile memory, the memory addresses accessed by memory operations include the memory address of the non-volatile memory and the memory address of the volatile memory.
  • the first processor core uses a precise event based sampling (PEBS) technology to collect other memory operations accessing the memory.
  • PEBS precise event based sampling
  • Other memory operations for accessing memory include but are not limited to: memory operations for mapping a file or other objects into memory, memory operations for accessing shared memory, memory operations for accessing file descriptors, and memory operations for accessing pipeline files.
  • the memory operations performed within the preset period are all or part of the memory operations within the preset period.
  • the memory operations counted by the first processor core may be memory operations of a certain duration within a preset cycle.
  • the memory operations include memory read and write operations of volatile memory and memory read and write operations of non-volatile memory.
  • the first processor core calculates the memory bandwidth size used by the process group to access the non-volatile memory according to the memory bandwidth size and the statistical memory operations.
  • the method flow shown in FIG. 3 is an elaboration of the specific operation process included in S202 in FIG. 2 , as shown in the figure: S2021 , the first processor core determines the process group access non-existent according to the memory address accessed by the memory operation. The ratio of volatile memory accesses to process group accesses to volatile memory. S2022. The first processor core calculates the memory bandwidth size used by the process group to access the non-volatile memory according to the memory bandwidth size and ratio.
  • the memory address accessed by the memory operation includes the memory address accessed by the non-volatile memory operation performed by the process group and the memory address accessed by the volatile memory operation performed by the process group.
  • the memory types of the memory accessed by the memory operation can be determined according to the memory address accessed by the memory operation, including non-volatile memory and volatile memory.
  • the access amount of the non-volatile memory can be determined according to the memory address accessed by the process group performing the memory operation of the non-volatile memory.
  • the amount of access to non-volatile memory can be understood as the memory size of the process group accessing non-volatile memory.
  • the access amount of the volatile memory can be determined according to the memory address accessed by the process group performing the memory operation of the volatile memory.
  • the amount of volatile memory access can be understood as the memory size of the process group accessing volatile memory.
  • the first processor core determines the access amount of the process group accessing the non-volatile memory and the memory size of the process group accessing the volatile memory according to the memory size of the process group accessing the non-volatile memory and the memory size of the process group accessing the volatile memory. percentage of visits.
  • the memory bandwidth used by the process group to access non-volatile memory satisfies formula (1).
  • B2 represents the memory bandwidth used by the process group to access the non-volatile memory in the preset period
  • B1 represents the memory bandwidth used by the process group to access the volatile memory in the preset period
  • d1 represents the process in the preset period.
  • d2 represents the access amount of process group access to non-volatile memory in a preset period
  • d2/d1 represents the ratio of the amount of access by the process group to the non-volatile memory and the amount of access by the process group to the volatile memory.
  • the first processor core can use the MBM technology to view the memory management information in the kernel to obtain the memory bandwidth size B1 used by the process group to access the volatile memory within the preset period.
  • d1 and d2 are acquired by the first processor core by collecting the memory operations on the memory in the system and other memory operations accessing the memory through the read-write interface of the file system.
  • the system administrator may assign a unique identifier to the user's service process, and the first processor core uses the identifier to monitor the memory bandwidth used by the process group to access the volatile memory in a preset period, and to sample the process group.
  • the first processor core detects that the memory bandwidth monitoring value at the start time T1 of the preset cycle is Bo, and the memory bandwidth monitoring value at the end time T2 of the preset cycle is Bn, the absolute value of the difference between Bn and Bo The amount of memory bandwidth used to access volatile memory for a process group within a preset period.
  • the first processor core samples the memory addresses accessed by 60,000 memory operations in the preset cycle, of which 20,000 The address is the address of the non-volatile memory, and the 40000 addresses are the addresses of the volatile memory.
  • the processor core estimates the memory bandwidth used by the process group to access the volatile memory based on the non-volatile memory operations, volatile memory operations and the memory bandwidth used by the process group to access the volatile memory within the preset cycle.
  • the memory bandwidth of non-volatile memory is monitored at the granularity of process group, and then the memory bandwidth of non-volatile memory is used as the basis for limiting the memory bandwidth of non-volatile memory.
  • the memory bandwidth of the non-volatile memory can be used as the limit of the non-volatile memory. Based on the memory bandwidth of the free memory, the method for limiting the memory bandwidth provided in this embodiment will be described in detail with reference to FIG. 4 .
  • the first processor core determines whether the memory bandwidth size of the non-volatile memory is greater than or equal to a non-volatile memory bandwidth threshold.
  • the non-volatile memory bandwidth threshold is the maximum amount of memory bandwidth that is allowed to access non-volatile memory.
  • the system administrator can set the non-volatile memory bandwidth threshold for different process groups to access the non-volatile memory through the second file system interface. For example, it is possible to limit the amount of non-volatile memory bandwidth that different groups of processes are allowed to use in each preset cycle.
  • the first processor core sets the memory bandwidth limit of the process group.
  • execute S201 and S202 that is, continue to monitor the memory bandwidth size used by the process group to access the non-volatile memory, and determine whether the memory bandwidth size of the non-volatile memory is greater than or equal to Equal to the non-volatile memory bandwidth threshold.
  • the first processor core releases the memory bandwidth limitation of the process group.
  • the method for releasing the memory bandwidth limit of the process group by the first processor core may be a reverse operation of setting the memory bandwidth limit of the process group.
  • execute S201 and S202 that is, continue to monitor the memory bandwidth size used by the process group to access the non-volatile memory, and determine whether the memory bandwidth size of the non-volatile memory is greater than or equal to Equal to the non-volatile memory bandwidth threshold.
  • the first processor core adjusts the first volatile memory bandwidth threshold of the process group to the second volatile memory bandwidth threshold.
  • the first volatile memory bandwidth threshold is greater than the second volatile memory bandwidth threshold, and both the first volatile memory bandwidth threshold and the second volatile memory bandwidth threshold refer to the memory that the process group is allowed to use when accessing the volatile memory Maximum bandwidth.
  • the first processor core may call the third file system interface to adjust the maximum value of the memory bandwidth allowed to be used by the process group accessing the volatile memory.
  • the first processor core may adjust the first volatile memory bandwidth threshold with an adjustment step size of 0.2G/s. For example, if the memory bandwidth of the non-volatile memory in the i-th preset cycle is greater than or equal to the non-volatile memory bandwidth threshold, the first processor core reduces the first volatile memory bandwidth threshold by 0.2G/s , to obtain a third volatile memory bandwidth threshold, where the third volatile memory bandwidth threshold is greater than the second volatile memory bandwidth threshold.
  • the first processor core obtains the memory bandwidth size of the non-volatile memory in the i+1th preset cycle, if the memory bandwidth size of the nonvolatile memory in the i+1th preset cycle is greater than or equal to the non-volatile memory The volatile memory bandwidth threshold, the first processor core continues to reduce the third volatile memory bandwidth threshold by 0.2G/s to obtain a fourth volatile memory bandwidth threshold, and the fourth volatile memory bandwidth threshold is greater than the second volatile memory bandwidth threshold Volatile memory bandwidth threshold. If the memory bandwidth size of the non-volatile memory in the i+1 preset cycle is smaller than the non-volatile memory bandwidth threshold, it is not necessary to set the memory bandwidth limit of the process group. i is an integer. The system administrator can set the adjustment step according to business needs and other factors.
  • the first processor core adjusts the first volatile memory bandwidth threshold at a granularity of 0.2G/s, until the first volatile memory bandwidth threshold decreases to the second volatile memory bandwidth threshold, but the non-volatile memory The size of the memory bandwidth is still greater than or equal to the non-volatile memory bandwidth threshold, the first processor executes the second possible implementation manner, that is, the first processor core removes the processes included in the process group from the first processor running the process group The core is migrated to the second processor core.
  • the second volatile memory bandwidth threshold is the maximum limit that limits the memory bandwidth used by the process group to access the volatile memory.
  • the system administrator can set the first volatile memory bandwidth threshold through the third file system interface.
  • the system administrator can be the person who deploys the business.
  • the system administrator uses the memory bandwidth allocation (MBA) technology of volatile memory to set the first volatile memory bandwidth threshold for the process group through the third file system interface.
  • MCA memory bandwidth allocation
  • the memory bandwidth of the volatile memory used by the process group is also reduced, so the process group uses the volatile memory.
  • the total memory bandwidth size of non-volatile memory and non-volatile memory is also reduced, and the memory bandwidth of non-volatile memory indirectly used by process groups is also reduced, so as to limit the memory bandwidth of non-volatile memory to any value.
  • the first processor core migrates the processes included in the process group from the first processor core running the process group to the second processor core, and the second processor core runs the migration process in the process group out process.
  • the second processor core may be the first processor core that runs fewer processes.
  • the number of processes migrated from the first processor core to the second processor core may be set by the system administrator or determined by the system itself.
  • the first processor core can migrate one process at a time, or can migrate two processes, which is not limited.
  • the first processor core migrates half of the processes included in the process group to the second processor core, and the memory bandwidth of the non-volatile memory is still greater than or equal to the non-volatile memory bandwidth threshold, the first processor executes the third A possible implementation manner is that the first processor core adjusts the first time slice of the process group to the second time slice, and the first time slice is larger than the second time slice.
  • the memory operations of the process group on the volatile memory and non-volatile memory are reduced accordingly, and the process group uses volatile memory and non-volatile memory.
  • the total memory bandwidth of the volatile memory is also reduced, and the memory bandwidth of the non-volatile memory indirectly used by the process group is also reduced, so as to limit the memory bandwidth of the non-volatile memory to an arbitrary value.
  • the first processor core and the second processor core belong to one or more NUMA nodes in a NUMA system. It is understandable that the first processor core and the second processor core belong to the same NUMA node in the NUMA system, or the first processor core and the second processor core belong to different NUMA nodes in the NUMA system.
  • a NUMA system typically includes multiple nodes, and each node includes multiple processor cores.
  • a processor contains multiple physical processor cores. Each physical processor core can also be divided into two logical processor cores.
  • a logical processor core in a physical processor may be divided into multiple NUMA nodes (abbreviated as nodes).
  • the first processor core may be a physical processor core or a logical processor core. If the first processor core is a physical processor core, the first processor core includes a plurality of logical processor cores. The first processor core and the second processor core may be cores in the same processor, or may be cores in different processors.
  • the processor includes 8 processor cores, and the 8 processor cores may be physical processor cores or logical processor cores.
  • the 8 processor cores are divided into 2 nodes. Assuming that processor core 1 runs a process group, processor core 1 can migrate a process in the process group from processor core 1 to processor core 2. Alternatively, processor core 1 may migrate the processes in the process group from processor core 1 to processor core 5 .
  • the first processor core adjusts the first time slice of the process group to the second time slice, the first time slice is larger than the second time slice, and both the first time slice and the second time slice are The duration of occupying the first processor core for the process group.
  • the first processor core may call the interface of the file system to adjust the duration that the process group occupies the first processor core.
  • the time period for the first processor core allocated to the process group to run the processes in the process group is reduced, the time period for the first processor core to run the processes in the process group is shortened.
  • the memory operations of the volatile memory are reduced accordingly, the total memory bandwidth of the volatile memory and non-volatile memory used by the process group is also reduced, and the memory bandwidth of the non-volatile memory indirectly used by the process group is also reduced. is reduced to limit the memory bandwidth of non-volatile memory to an arbitrary value.
  • the first processor core strengthens or relaxes the restriction on the process group according to the non-volatile memory bandwidth size and the non-volatile memory bandwidth threshold used by the process group in the i-th preset cycle, thereby allowing the process group to use the process group in the i-th preset cycle. Uses less or more non-volatile memory bandwidth resources for i+1 preset cycles.
  • the memory bandwidth used by the process group to access the volatile memory is controlled by restricting measures, and the memory bandwidth used by the process group to access the non-volatile memory is indirectly limited. Avoid excessive use of non-volatile memory bandwidth by process groups, containers or virtual machines, affecting other process groups, containers or virtual machines from being unable to access non-volatile memory, and solve business performance degradation caused by adjacent interference fault propagation. Interruption problem.
  • the first processor core selects one of three possible implementation manners to limit the memory bandwidth of the non-volatile memory used by the process group. However, after limiting the memory bandwidth of the non-volatile memory used by the process group, the memory bandwidth size of the non-volatile memory may still be greater than or equal to the non-volatile memory bandwidth threshold. At this time, the first processor core may also dynamically limit the memory bandwidth of the non-volatile memory. As shown in FIG. 6 , this embodiment further provides a method for dynamically limiting the memory bandwidth.
  • the first processor core acquires the size of the first memory bandwidth used by the process group to access the non-volatile memory in a preset period.
  • the first processor core determines whether the first memory bandwidth size of the non-volatile memory is greater than or equal to a non-volatile memory bandwidth threshold.
  • the size of the first memory bandwidth used by the process group to access the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold, perform S603. If the size of the first memory bandwidth used by the process group to access the non-volatile memory is smaller than the non-volatile memory bandwidth threshold, perform S604.
  • the first processor core adjusts the first volatile memory bandwidth threshold of the process group to the second volatile memory bandwidth threshold. Execute S604.
  • the first processor core acquires the second memory bandwidth size used by the process group to access the non-volatile memory in a preset period.
  • the first processor core determines whether the second memory bandwidth size of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold.
  • the first processor core may further adjust the second volatile memory bandwidth threshold of the process group to the first volatile memory bandwidth threshold according to the adjustment step size. For example, when the service demand increases, the first processor core may further adjust the second volatile memory bandwidth threshold of the process group to the first volatile memory bandwidth threshold according to the adjustment step size.
  • the first processor core migrates the processes included in the process group from the first processor core running the process group to the second processor core. Execute S607.
  • the first processor core acquires the third memory bandwidth size used by the process group to access the non-volatile memory in a preset period.
  • the first processor core determines whether the third memory bandwidth size of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold.
  • the first processor core migrates the processes included in the process group from the first processor core running the process group to the second processor core, the third memory bandwidth used by the process group to access the non-volatile memory If the size is smaller than the non-volatile memory bandwidth threshold, the first processor core may further migrate the processes included in the process group from the second processor core to the first processor core.
  • the first processor core adjusts the first time slice of the process group to the second time slice. Execute S610.
  • the specific method for the first processor core to obtain the memory bandwidth size (including the size of the first memory bandwidth, the size of the second memory bandwidth, and the size of the third memory bandwidth) used by the process group to access the non-volatile memory can refer to the details of S201 and S202 Explanation will not be repeated.
  • S603 reference may be made to the above description in the first possible implementation manner.
  • S606 reference may be made to the above description in the second possible implementation manner.
  • S609 reference may be made to the above description in the third possible implementation manner.
  • the first processor core periodically monitors the non-volatile memory used by the process group after limiting the memory bandwidth of the non-volatile memory used by the process group in one of the three possible implementation manners.
  • the memory bandwidth size of the memory may acquire the memory bandwidth size of the non-volatile memory in adjacent preset cycles, or may acquire the memory bandwidth size of the non-volatile memory in non-adjacent preset cycles.
  • the first processor core acquires the first memory bandwidth used by the process group to access the non-volatile memory in the i-th preset cycle, and the first processor core can acquire the process group in the i+1-th preset cycle
  • the size of the second memory bandwidth used for accessing the non-volatile memory the first processor core may also acquire the size of the second memory bandwidth used by the process group for accessing the non-volatile memory within the i+2th preset cycle.
  • i is an integer.
  • the number of cycles at which the first processor acquires the memory bandwidth size of the non-volatile memory is not limited.
  • the first processor core limits the memory bandwidth of the non-volatile memory in a dynamic manner. After the memory bandwidth of the non-volatile memory is limited, if the memory bandwidth of the non-volatile memory is less than the non-volatile memory bandwidth threshold, the memory bandwidth of the process group can also be increased, that is, the memory bandwidth of the non-volatile memory is released. Limit so that the process group has sufficient available resources. As shown in FIG. 7 , this embodiment further provides a method for dynamically limiting memory bandwidth.
  • the first processor core acquires the fourth memory bandwidth size used by the process group to access the non-volatile memory in a preset period.
  • the first processor core determines that the fourth memory bandwidth size of the non-volatile memory is smaller than the non-volatile memory bandwidth threshold. Execute S612.
  • the first processor core adjusts the second time slice of the process group to the first time slice. Execute S613.
  • the first processor core adjusts the second time slice of the process group to the first time slice, that is, increases the length of time that the process group occupies the processor core, so that the memory operation of the volatile memory and the non-volatile memory by the process group is easy. With the increase, the total memory bandwidth of volatile memory and non-volatile memory used by the process group also increases, and indirectly the memory bandwidth of the non-volatile memory used by the process group also increases, making the process group There are sufficient resources available.
  • the specific adjustment method is to adjust the first time slice of the process group to the reverse process of the second time slice. For details, please refer to the specific description of the above-mentioned third possible implementation manner.
  • the first processor core obtains the size of the fifth memory bandwidth used by the process group to access the non-volatile memory within a preset period.
  • the first processor core determines that the fifth memory bandwidth size of the non-volatile memory is smaller than the non-volatile memory bandwidth threshold. Execute S615.
  • the first processor core migrates the processes included in the process group from the second processor core to the first processor core. Execute S616.
  • the process migrated from the second processor core to the first processor core is a process included in the process group of the first processor core migrated from the first processor core to the second processor core.
  • the process group uses volatile memory and non-volatile memory.
  • the total memory bandwidth size of the memory also increases, and the memory bandwidth of the non-volatile memory indirectly used by the process group also increases, so that the process group has sufficient available resources.
  • the first processor core acquires the size of the sixth memory bandwidth used by the process group to access the non-volatile memory within a preset period.
  • the first processor core determines that the sixth memory bandwidth size of the non-volatile memory is smaller than the non-volatile memory bandwidth threshold. Execute S618.
  • the first processor core adjusts the second volatile memory bandwidth threshold of the process group to the first volatile memory bandwidth threshold.
  • the first processor core continues to monitor the memory bandwidth used by the process group to access the non-volatile memory within a preset period. Since the maximum memory bandwidth of the volatile memory used by the process group is increased, the total memory bandwidth of the volatile memory and non-volatile memory used by the process group also increases, and indirectly the non-volatile memory used by the process group is increased. The memory bandwidth of volatile memory is also increased, so that the process group has sufficient resources available.
  • the first processor core may increase the volatile memory bandwidth threshold to the first volatile memory bandwidth threshold according to the adjustment step size.
  • the method of increasing the volatile memory bandwidth threshold according to the adjustment step is the reverse process of reducing the volatile memory bandwidth threshold.
  • the specific method for the first processor core to obtain the memory bandwidth size (including the fourth memory bandwidth size, the fifth memory bandwidth size, and the sixth memory bandwidth size) used by the process group to access the non-volatile memory can refer to the details of S201 and S202 Explanation will not be repeated.
  • the system administrator configures the process group, sets the non-volatile memory bandwidth threshold and sets the volatile memory bandwidth threshold through different interfaces in the file system. For example, a system administrator configures a process group through the first file system interface. The system administrator sets the non-volatile memory bandwidth threshold through the second file system interface. The system administrator sets the first volatile memory bandwidth threshold through the third file system interface.
  • the first processor core uses the MBM technology to view the memory management information in the kernel, obtains the memory bandwidth used by the process group to access the volatile memory in the preset period, and collects the memory operations on the memory in the system through the read and write interfaces of the file system. and other memory operations that access memory.
  • the monitoring module in the first processor core calculates the size of the memory bandwidth used by the process group to access the non-volatile memory according to the size of the memory bandwidth and the statistical memory operations.
  • the restriction module in the first processor core adopts the above-mentioned first processing of adjusting the volatile memory bandwidth threshold, migrating processes and adjusting the occupation of the process group Either of the time slices of the core sets the memory bandwidth limit of the process group.
  • the first processor core adjusts the volatile memory bandwidth threshold B1', that is, adjusts the first volatile memory bandwidth threshold of the process group to the second volatile memory bandwidth threshold.
  • the non-volatile memory bandwidth used by the process group is 12GB/s.
  • the non-volatile memory bandwidth used by the process group is 6GB/s.
  • the first processor core adjusts the process group to occupy the first
  • the duration of the processor core that is, adjusting the first time slice of the process group to the second time slice.
  • the first time slice is the duration of a preset period.
  • the second time slice is 83% of the duration of the preset period.
  • the non-volatile memory bandwidth used by the process group is 1 GB/s.
  • the first processor core adjusts the length of time that the process group occupies the first processor core, that is, adjusts the second time slice of the process group to the first time slice.
  • the non-volatile memory bandwidth used by the process group is 2 GB/s.
  • the first processor core migrates the processes of the process group, that is, the processes included in the process group are migrated from the second processor core running the process group to the first processor core.
  • the non-volatile memory bandwidth used by the process group is 3GB/s.
  • the first processor core adjusts the volatile memory bandwidth threshold, that is, adjusts the second volatile memory bandwidth threshold of the process group to the first volatile memory bandwidth threshold.
  • the server includes corresponding hardware structures and/or software modules for executing each function.
  • the units and method steps of each example described in conjunction with the embodiments disclosed in the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is performed by hardware or computer software-driven hardware depends on the specific application scenarios and design constraints of the technical solution.
  • the method for monitoring memory bandwidth and the method for limiting memory bandwidth provided according to this embodiment are described in detail above with reference to FIGS. 1 to 8 .
  • the following describes the method for monitoring memory bandwidth provided according to this embodiment with reference to FIGS. 9 to 11 .
  • FIG. 9 is a schematic structural diagram of a possible apparatus for monitoring memory bandwidth provided in this embodiment.
  • These apparatuses for monitoring memory bandwidth can be used to implement the functions of the processor core in the above method embodiments, so the beneficial effects of the above method embodiments can also be achieved.
  • the device for monitoring memory bandwidth may be the processor core 0 shown in FIG. 1 , or may be a module (eg, a chip) applied to a server.
  • the apparatus 900 for monitoring memory bandwidth includes an acquiring unit 910 , a monitoring unit 920 and a limiting unit 930 .
  • the apparatus 900 for monitoring memory bandwidth is configured to implement the function of the first processor core in the method embodiment shown in FIG. 2 , FIG. 3 or FIG. 4 .
  • the apparatus 900 for monitoring memory bandwidth is used to implement the function of the first processor core in the method embodiment shown in FIG. 2: the obtaining unit 910 is used to implement the function performed by the first processor core in S201; the monitoring unit 920 uses to realize the function executed by the first processor core in S202.
  • the obtaining unit 910 is used to implement the function performed by the first processor core in S201; the monitoring unit 920 uses for realizing the functions executed by the first processor core in S2021 and S2022.
  • the apparatus 900 for monitoring memory bandwidth is used to implement the function of the first processor core in the method embodiment shown in FIG. 4: the obtaining unit 910 is used to implement the function performed by the first processor core in S201; the monitoring unit 920 uses is used to implement the function executed by the first processor core in S202; the limiting unit 930 is used to implement the function executed by the first processor core in S401, S402 and S403.
  • FIG. 10 is a schematic structural diagram of a possible device for limiting memory bandwidth provided in this embodiment.
  • These devices for limiting memory bandwidth can be used to implement the functions of the processor core in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments.
  • the device for limiting memory bandwidth may be the processor core 0 shown in FIG. 1 , or may be a module (eg, a chip) applied to a server.
  • the apparatus 1000 for limiting memory bandwidth includes an obtaining unit 1010 and a limiting unit 1020 .
  • the apparatus 1000 for limiting memory bandwidth is configured to implement the function of the first processor core in the method embodiment shown in FIG. 6 or FIG. 7 .
  • the apparatus 1000 for limiting memory bandwidth is used to implement the function of the first processor core in the method embodiment shown in FIG. 6 : the obtaining unit 1010 is used to implement the functions executed by the first processor core in S601 , S604 , S607 and S610 Function; the limiting unit 1020 is configured to implement the functions executed by the first processor core in S602, S603, S605, S606, S608 and S609.
  • the apparatus 1000 for limiting memory bandwidth is used to implement the function of the first processor core in the method embodiment shown in FIG. 7 : the obtaining unit 1010 is used to implement the function performed by the first processor core in S610, S613 and S616;
  • the limiting unit 1020 is configured to implement the functions performed by the first processor core in S611, S612, S614, S615, S617 and S618.
  • the processor in this embodiment may be a central processing unit (Central Processing Unit, CPU), and may also be other general-purpose processors, digital signal processors (Digital Signal Processors, DSP), application-specific integrated circuits (Application Specific Integrated Circuit, ASIC), field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof.
  • CPU Central Processing Unit
  • DSP Digital Signal Processors
  • ASIC Application Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • a general-purpose processor may be a microprocessor or any conventional processor.
  • the processor may also be a graphics processing unit (GPU), a neural network processing unit (NPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or A plurality of integrated circuits used to control the execution of the programs of the present application.
  • GPU graphics processing unit
  • NPU neural network processing unit
  • ASIC application-specific integrated circuit
  • FIG. 11 is a schematic structural diagram of a server 1100 according to this embodiment.
  • the server 1100 includes a processor 1110 , a bus 1120 , a communication interface 1150 , a main memory 1130 and a memory 1140 .
  • the processor 1110 may be a central processing unit (central processing unit, CPU), and the processor 1110 may also be other general-purpose processors, digital signal processors (digital signal processing, DSP), special-purpose processors Integrated circuit (application-specific integrated circuit, ASIC), field-programmable gate array (field-programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general purpose processor may be a microprocessor or any conventional processor or the like.
  • the communication interface 1150 is used to implement the communication between the server 1100 and external devices or devices.
  • the bus 1120 may include a path for transferring information between the aforementioned components (eg, the processor 1110, main memory 1130, and memory 1140).
  • the bus 1120 may also include a power bus, a control bus, a status signal bus, and the like.
  • the various buses are labeled as bus 1120 in the figure.
  • server 1100 may include multiple processors.
  • the processor may be a multi-core (multi-CPU) processor.
  • a processor herein may refer to one or more devices, circuits, and/or computational units for processing data (eg, computer program instructions).
  • the processor 1110 can monitor the memory bandwidth used by the running process group to access the volatile memory within the preset period, and count the memory operations performed by the process group within the preset period, and calculate the memory bandwidth according to the size of the memory bandwidth and the statistics of the memory operations. The amount of memory bandwidth used by the process group to access non-volatile memory. If the memory bandwidth size of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold, set the memory bandwidth limit of the process group.
  • the specific process of monitoring the memory bandwidth size of the non-volatile memory and setting the memory bandwidth limit of the process group can be obtained directly by referring to the relevant descriptions in the foregoing method embodiments, which will not be repeated here.
  • the server 1100 including one processor 1110 and one main memory 1130 is used as an example.
  • the processor 1110 and the main memory 1130 are respectively used to indicate a type of device or device. Specific embodiments , the number of each type of device or device can be determined based on business needs.
  • the memory 1140 may be used to store relevant information in a cloud environment, eg, a magnetic disk such as a mechanical hard disk or a solid state disk.
  • the above server 1100 may be a general-purpose device or a dedicated device.
  • the server 1100 may be an X86 or ARM-based server, or may be other dedicated servers, such as a policy control and charging (policy control and charging, PCC) server and the like.
  • policy control and charging policy control and charging, PCC
  • This embodiment of the present application does not limit the type of the server 1100 .
  • the server 1100 may correspond to the apparatus 900 for monitoring memory bandwidth and the apparatus 1000 for limiting memory bandwidth in this embodiment, and may correspond to the implementation of the apparatus according to FIGS. 2 to 4 , and FIGS. 6 and 7 .
  • the above-mentioned and other operations and/or functions of the respective modules in any one of the methods, and the above-mentioned and other operations and/or functions of the devices are respectively in order to realize the corresponding processes of the respective methods in FIGS. 2 to 4, and FIGS. 6 and 7, for brevity, It is not repeated here.
  • This embodiment further provides a processor, the structure of which is shown in FIG. 11 , and includes multiple processor cores, which are used to implement the operation steps of the methods described in FIGS. 2 to 4 , and FIGS. 6 and 7 . , in order to avoid repetition, it is not repeated here.
  • the method steps in this embodiment may be implemented in a hardware manner, or may be implemented in a manner in which a processor executes software instructions.
  • Software instructions can be composed of corresponding software modules, and software modules can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (programmable ROM) , PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically erasable programmable read-only memory (electrically EPROM, EEPROM), registers, hard disks, removable hard disks, CD-ROMs or known in the art in any other form of storage medium.
  • An exemplary storage medium is coupled to the processor, such that the processor can read information from, and write information to, the storage medium.
  • the storage medium can also be an integral part of the processor.
  • the processor and storage medium may reside in an ASIC.
  • the ASIC may be located in a network device or in an end device.
  • the processor and the storage medium may also exist in the network device or the terminal device as discrete components.
  • the above-mentioned embodiments it may be implemented in whole or in part by software, hardware, firmware or any combination thereof.
  • software it can be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer programs or instructions.
  • the processes or functions described in the embodiments of the present application are executed in whole or in part.
  • the computer may be a general purpose computer, a special purpose computer, a computer network, network equipment, user equipment, or other programmable apparatus.
  • the computer program or instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer program or instructions may be downloaded from a website, computer, A server or data center transmits by wire or wireless to another website site, computer, server or data center.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server, data center, or the like that integrates one or more available media.
  • the usable medium can be a magnetic medium, such as a floppy disk, a hard disk, and a magnetic tape; it can also be an optical medium, such as a digital video disc (DVD); it can also be a semiconductor medium, such as a solid state drive (solid state drive). , SSD).
  • a magnetic medium such as a floppy disk, a hard disk, and a magnetic tape
  • an optical medium such as a digital video disc (DVD)
  • DVD digital video disc
  • it can also be a semiconductor medium, such as a solid state drive (solid state drive). , SSD).

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Abstract

一种监控内存带宽的方法及装置，涉及计算机领域。方法包括：处理器核获取到预设周期内进程组访问易失性内存所使用的内存带宽大小，以及统计进程组在预设周期内执行的内存操作后，根据内存带宽大小和统计的内存操作计算进程组访问非易失性内存所使用的内存带宽大小。实现了以进程组为粒度监控非易失性内存的内存带宽，进而将易失性内存的内存带宽大小作为限制非易失性内存的内存带宽的依据。

Description

一种监控内存带宽的方法及装置
本申请要求于2020年07月17日提交国家知识产权局、申请号为202010691597.4、申请名称为“一种内存带宽的监控方法和装置”的中国专利申请的优先权，以及于2020年8月26日提交中国专利局、申请号为202010873243.1、申请名称为“一种监控内存带宽的方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及计算机领域，尤其涉及一种监控内存带宽的方法及装置。
背景技术
随着云技术的发展和繁荣，一台服务器可以运行不同租户的多个进程，多个进程共享服务器的各种资源(如：计算资源、存储资源和内存资源等)，以提高服务器的资源利用率。但是，资源共享可能带来性能上不公平的问题。例如，相同优先级的进程获得不同的资源。又如，优先级低的进程占用了大量的资源，优先级高的进程无法获取充足的资源，导致租户的业务受到影响，降低了用户体验。传统技术中，采用资源控制组(control group，cgroup)技术将多个进程划分为不同的进程组，不同的进程组使用不同的资源(如：计算资源、存储资源和内存资源)。另外，采用资源调配技术(resource director technology)识别占用大量易失性内存的内存带宽的进程并限制该进程占用易失性内存的内存带宽，以确保其他进程获取充足的内存资源。
由于非易失性内存(non-volatile memory，NVM)的内存带宽远低于易失性内存的内存带宽。在多租户云环境中，非易失性内存的内存带宽竞争比易失性内存的内存带宽的竞争更为激烈，易造成业务劣化甚至中断。但是，由于非易失性内存未提供内存带宽限制功能，资源调配技术无法实现对非易失性内存的内存带宽的监控和限制。因此，如何监控非易失性内存的内存带宽是一个亟待解决的问题。
发明内容
本申请实施例提供了一种监控内存带宽的方法及装置，实现了以进程组为粒度监控非易失性内存的内存带宽，进而将非易失性内存的内存带宽大小作为限制非易失性内存的内存带宽的依据。
第一方面，提供一种监控内存带宽的方法，用于监控非易失性内存的内存带宽。该方法包括：处理器核获取预设周期内进程组访问易失性内存所使用的内存带宽大小，以及统计进程组在预设周期内执行的内存操作，进而根据所述内存带宽大小和统计的内存操作计算进程组访问非易失性内存所使用的第一内存带宽大小。这里的内存操作包括非易失性内存操作和易失性内存操作。如此，处理器核基于预设周期内的非易失性内存操作、易失性内存操作和进程组访问易失性内存所使用的内存带宽大小估计进程组访问易失性内存所使用的内存带宽大小，通过软件方法实现了以进程组为粒度监控非易失性内存的内存带宽，进而将非易失性内存的内存带宽大小作为限制非易失性内存的内存带宽的依据。
值得说明的是，进程组在预设周期内执行的内存操作可理解为进程组在预设周期内执行的内存操作所访问的内存地址。内存操作为内存读写操作。进程组包括至少一个进程。在一些实施例中，一个进程组可以是一个容器或一个虚拟机。一个进程组包含的所有进程可以由 一个容器运行或一个虚拟机运行。在另一些实施例中，一个进程组包含的进程可以由多个容器运行或多个虚拟机运行。也就是说，一个进程组包含的进程是多个容器中的进程。或者，一个进程组包含的进程是多个虚拟机中的进程。
在一种可能的设计中，根据内存带宽大小和统计的内存操作计算进程组访问非易失性内存所使用的第一内存带宽大小，包括：处理器核根据内存操作所访问的内存地址确定进程组访问非易失性内存的访问量和进程组访问易失性内存的访问量的比例；根据内存带宽大小和比例计算进程组访问非易失性内存所使用的第一内存带宽大小。由于内存操作所访问的内存地址包括非易失性内存操作所访问的内存地址和易失性内存操作所访问的内存地址。依据内存操作所访问的内存地址可以确定内存操作所访问的内存的内存类型和内存大小。内存类型包括非易失性内存和易失性内存。内存大小包括进程组访问易失性内存的内存大小和进程组访问非易失性内存的内存大小。进而，处理器核根据内存操作的内存大小和内存类型确定进程组访问非易失性内存的访问量和进程组访问易失性内存的访问量的比例。可理解的，进程组访问非易失性内存的访问量为进程组访问非易失性内存的内存大小。进程组访问易失性内存的访问量为进程组访问易失性内存的内存大小。
可选的，预设周期内执行的内存操作是预设周期内全部内存操作或部分内存操作。
进一步，在根据内存带宽大小和统计的内存操作计算进程组访问非易失性内存所使用的第一内存带宽大小之后，方法还包括：若非易失性内存的第一内存带宽大小大于或等于非易失性内存带宽阈值，设置进程组的内存带宽限制，非易失性内存带宽阈值为进程组访问非易失性内存允许使用的内存带宽的最大值。从而，通过限制措施控制进程组访问易失性内存所使用的内存带宽大小，间接限制进程组访问非易失性内存所使用的内存带宽大小。避免由于进程组、容器或者虚拟机使用过多的非易失性内存带宽，影响其他进程组、容器或者虚拟机无法访问非易失性内存，解决了邻位干扰故障扩散导致的业务性能劣化甚至中断的问题。
设置进程组的内存带宽限制包括以下一种或多种：将进程组的第一易失性内存带宽阈值调整为第二易失性内存带宽阈值，第一易失性内存带宽阈值大于第二易失性内存带宽阈值，第一易失性内存带宽阈值和第二易失性内存带宽阈值均指进程组访问易失性内存允许使用的内存带宽的最大值。由于降低了进程组访问易失性内存允许使用的易失性内存的内存带宽的最大值，从而进程组使用易失性内存和非易失性内存的总的内存带宽大小也随之降低，间接地进程组使用的非易失性内存的内存带宽也随之降低，实现限制非易失性内存的内存带宽到任意值。
将进程组包含的进程从运行进程组的第一处理器核迁移到第二处理器核。由于减少了处理器核运行的进程组包含的进程的个数，进程组对易失性内存和非易失性内存的内存操作便随之减少，进程组使用易失性内存和非易失性内存的总的内存带宽大小也随之降低，间接地进程组使用的非易失性内存的内存带宽也随之降低，实现限制非易失性内存的内存带宽到任意值。
将进程组的第一时间片调整为第二时间片，第一时间片大于第二时间片，第一时间片和第二时间片均为进程组占用第一处理器核的时长。由于缩短了进程组占用处理器核的时长，进程组对易失性内存和非易失性内存的内存操作便随之减少，进程组使用易失性内存和非易失性内存的总的内存带宽大小也随之降低，间接地进程组使用的非易失性内存的内存带宽也随之降低，实现限制非易失性内存的内存带宽到任意值。
在一种可能的设计中，如果将进程组的第一易失性内存带宽阈值调整为第二易失性内存 带宽阈值后，当非易失性内存的第二内存带宽大小大于或等于非易失性内存带宽阈值，将进程组包含的进程从运行进程组的第一处理器核迁移到第二处理器核。可选的，第一处理器核和第二处理器核属于非一致性内存访问(non-uniform memory access，NUMA)系统中一个或多个NUMA节点。
在一种可能的设计中，如果将进程组包含的进程从运行进程组的第一处理器核迁移到第二处理器核后，当非易失性内存的第三内存带宽大小大于或等于非易失性内存带宽阈值，将进程组的第一时间片调整为第二时间片。
如此，采用动态调节的方法能够精确控制非易失性内存的内存带宽到特定值，避免业务性能劣化甚至中断，同时降低资源部署成本。
在限制非易失性内存的内存带宽后，若处理器核监控到的非易失性内存的内存带宽小于非易失性内存带宽阈值时，可以解除对进程组访问易失性内存的限制，间接提升了进程组访问非易失性内存所使用的内存带宽，使得进程组有充足的可用资源。
在一种可能的设计中，将进程组的第一时间片调整为第二时间片之后，方法还包括：当非易失性内存的第四内存带宽大小小于非易失性内存带宽阈值，将进程组的第二时间片调整为第一时间片。由于增加了进程组占用处理器核的时长，进程组对易失性内存和非易失性内存的内存操作便随之增加，进程组使用易失性内存和非易失性内存的总的内存带宽大小也随之提升，间接地进程组使用的非易失性内存的内存带宽也随之提升，使得进程组有充足的可用资源。
在一种可能的设计中，将进程组的第二时间片调整为第一时间片之后，方法还包括：当非易失性内存的第五内存带宽大小小于非易失性内存带宽阈值，将进程组包含的进程从第二处理器核迁移到第一处理器核。由于增加了处理器核运行的进程组包含的进程的个数，进程组对易失性内存和非易失性内存的内存操作便随之增加，进程组使用易失性内存和非易失性内存的总的内存带宽大小也随之增加，间接地进程组使用的非易失性内存的内存带宽也随之提升，使得进程组有充足的可用资源。
在一种可能的设计中，将进程组包含的进程从第二处理器核迁移到第一处理器核之后，方法还包括：当非易失性内存的第六内存带宽大小小于非易失性内存带宽阈值，将进程组的第二易失性内存带宽阈值调整为第一易失性内存带宽阈值。由于增加了进程组使用的易失性内存的内存带宽的最大值，从而进程组使用易失性内存和非易失性内存的总的内存带宽大小也随之增加，间接地进程组使用的非易失性内存的内存带宽也随之提升，使得进程组有充足的可用资源。
需要说明的是，非易失性内存带宽阈值是通过第一文件系统接口设置的。第一易失性内存带宽阈值和第二易失性内存带宽阈值是通过第二文件系统接口设置的。
第二方面，提供一种限制内存带宽的方法，包括：若进程组在预设周期内访问非易失性内存所使用的第一内存带宽大小大于或等于非易失性内存带宽阈值，将进程组的第一易失性内存带宽阈值调整为第二易失性内存带宽阈值，非易失性内存带宽阈值为进程组访问非易失性内存允许使用的内存带宽的最大值，第一易失性内存带宽阈值大于第二易失性内存带宽阈值，第一易失性内存带宽阈值和第二易失性内存带宽阈值均指进程组访问易失性内存允许使用的内存带宽的最大值，进程组包括至少一个进程；当非易失性内存的第二内存带宽大小大于或等于非易失性内存带宽阈值，将进程组包含的进程从运行进程组的第一处理器核迁移到第二处理器核。如此，采用动态调节的方法控制进程组访问易失性内存所使用的易失性内存 带宽，间接限制非易失性内存的内存带宽到任意值，避免由于进程组、容器或者虚拟机使用过多的非易失性内存带宽，影响其他进程组、容器或者虚拟机无法访问非易失性内存，解决了邻位干扰故障扩散导致的业务性能劣化甚至中断的问题。
在一种可能的设计中，在将进程组包含的进程从运行进程组的第一处理器核迁移到第二处理器核之后，方法还包括：当非易失性内存的第三内存带宽大小大于或等于非易失性内存带宽阈值，将进程组的第一时间片调整为第二时间片，第一时间片大于第二时间片，第一时间片和第二时间片均为进程组占用第一处理器核的时长。
在一种可能的设计中，将进程组的第一时间片调整为第二时间片之后，方法还包括：当非易失性内存的第四内存带宽大小小于非易失性内存带宽阈值，将进程组的第二时间片调整为第一时间片。
在一种可能的设计中，将进程组的第二时间片调整为第一时间片之后，方法还包括：当非易失性内存的第五内存带宽大小小于非易失性内存带宽阈值，将进程组包含的进程从第二处理器核迁移到第一处理器核。
在一种可能的设计中，将进程组包含的进程从第二处理器核迁移到第一处理器核之后，方法还包括：当非易失性内存的第六内存带宽大小小于非易失性内存带宽阈值，将进程组的第二易失性内存带宽阈值调整为第一易失性内存带宽阈值。
第三方面，提供了一种监控内存带宽的装置，有益效果可以参见第一方面的描述此处不再赘述。所述监控内存带宽的装置具有实现上述第一方面的方法实例中行为的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。在一个可能的设计中，所述监控内存带宽的装置包括：获取单元、监控单元和限制单元。所述获取单元，用于获取预设周期内进程组访问易失性内存所使用的内存带宽大小，以及统计进程组在预设周期内执行的内存操作，内存操作包括非易失性内存操作和易失性内存操作，进程组包括至少一个进程。所述监控单元，用于根据内存带宽大小和统计的内存操作计算进程组访问非易失性内存所使用的第一内存带宽大小。所述限制单元，用于若第一内存带宽大小大于或等于非易失性内存带宽阈值，设置进程组的内存带宽限制，非易失性内存带宽阈值为进程组访问非易失性内存允许使用的内存带宽的最大值。这些单元可以执行上述第一方面方法示例中的相应功能，具体参见方法示例中的详细描述，此处不做赘述。
第四方面，提供了一种限制内存带宽的装置，有益效果可以参见第二方面的描述此处不再赘述。所述限制内存带宽的装置具有实现上述第二方面的方法实例中行为的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。在一个可能的设计中，该限制内存带宽的装置包括：获取单元和限制单元。所述获取单元，用于获取预设周期内进程组访问非易失性内存所使用的内存带宽大小。所述限制单元，用于若进程组在预设周期内访问非易失性内存所使用的第一内存带宽大小大于或等于非易失性内存带宽阈值，将进程组的第一易失性内存带宽阈值调整为第二易失性内存带宽阈值，非易失性内存带宽阈值为进程组访问非易失性内存允许使用的内存带宽的最大值，第一易失性内存带宽阈值大于第二易失性内存带宽阈值，第一易失性内存带宽阈值和第二易失性内存带宽阈值均指进程组访问易失性内存允许使用的内存带宽的最大值，进程组包括至少一个进程。所述限制单元，还用于当非易失性内存的第二内存带宽大小大于或等于非易失性内存带宽阈值，将进程组包含的进程从运行进程组的第一处理器核迁移到第 二处理器核。所述限制单元，还用于当非易失性内存的第三内存带宽大小大于或等于非易失性内存带宽阈值，将进程组的第一时间片调整为第二时间片，第一时间片大于第二时间片，第一时间片和第二时间片均为进程组占用第一处理器核的时长。这些模块可以执行上述第二方面方法示例中的相应功能，具体参见方法示例中的详细描述，此处不做赘述。
第五方面，提供了一种处理器，处理器包括多个处理器核，该处理器核用于执行第一方面或第一方面任一种可能设计中的监控内存带宽的方法。处理器核可以执行上述第一方面方法示例中的第一处理器核所执行方法的操作步骤，具体参见方法示例中的详细描述，此处不做赘述。
第六方面，提供了一种处理器，处理器包括多个处理器核，该处理器核用于执行第二方面或第二方面任一种可能设计中的限制内存带宽的方法。处理器核可以执行上述第二方面方法示例中的第二处理器核所执行方法的操作步骤，具体参见方法示例中的详细描述，此处不做赘述。
第七方面，提供了一种服务器，该服务器包括至少一个如第五方面所述的处理器和主存，所述处理器包括多个处理器核，每个处理器核用于执行上述第一方面或第一方面任意一种可能的实现方式中监控内存带宽的方法的操作步骤。
第八方面，提供了一种服务器，该服务器包括至少一个如第六方面所述的处理器和主存，所述处理器包括多个处理器核，每个处理器核用于执行上述第二方面或第二方面任意一种可能的实现方式中限制内存带宽的方法的操作步骤。
第九方面，提供一种计算机可读存储介质，包括：计算机软件指令；当计算机软件指令在服务器中运行时，使得服务器执行如第一方面或第一方面任意一种可能的实现方式中所述方法的操作步骤。
第十方面，提供一种计算机可读存储介质，包括：计算机软件指令；当计算机软件指令在服务器中运行时，使得服务器执行如第二方面或第二方面任意一种可能的实现方式中所述方法的操作步骤。
第十一方面，提供一种计算机程序产品，当计算机程序产品在计算机上运行时，使得计算机执行如第一方面或第一方面任意一种可能的实现方式中所述方法的操作步骤。
第十二方面，提供一种计算机程序产品，当计算机程序产品在计算机上运行时，使得计算机执行如第二方面或第二方面任意一种可能的实现方式中所述方法的操作步骤。
本申请在上述各方面提供的实现方式的基础上，还可以进行进一步组合以提供更多实现方式。
附图说明
图1为本申请实施例提供的一种云环境的简化示意图；
图2为本申请实施例提供的一种监控内存带宽的方法的流程图；
图3为本申请实施例提供的一种监控内存带宽的方法的流程图；
图4为本申请实施例提供的一种监控内存带宽的方法的流程图；
图5为本申请实施例提供的一种进程迁移示意图；
图6为本申请实施例提供的一种限制内存带宽的方法的流程图；
图7为本申请实施例提供的一种限制内存带宽的方法的流程图；
图8为本申请实施例提供的一种动态限制内存带宽的过程的示意图；
图9为本申请实施例提供的一种监控内存带宽的装置的组成示意图；
图10为本申请实施例提供的一种限制内存带宽的装置的组成示意图；
图11为本申请实施例提供的一种服务器的组成示意图。
具体实施方式
下面将结合附图对本申请实施例的实施方式进行详细描述。
云环境是云计算模式下利用基础资源向用户提供云服务的实体。如图1所示，云环境100包括云数据中心110和云服务平台120。所述云数据中心110包括云服务提供商拥有的大量基础资源(包括计算资源111、存储资源112和内存资源113)。
计算资源111可以是大量的计算设备(例如服务器)。计算设备包括多个处理器，例如图1中所示的处理器1111和处理器1112。处理器1111是计算设备的控制中心。通常情况下，处理器1111是一个中央处理器(central processing unit，CPU)，包括一个处理器核或多个处理器核，例如图1中所示的处理器核0和处理器核1。此外，处理器1111也可以是特定集成电路(application specific integrated circuit，ASIC)，或者是被配置成一个或多个集成电路，例如：一个或多个微处理器(digital signal processor，DSP)，或，一个或者多个现场可编程门阵列(field programmable gate array，FPGA)。处理器核0和处理器核1可以是指处理器1111中的物理处理器核或逻辑处理器核。处理器1111可以通过运行或执行存储在存储资源112内的软件程序，以及调用存储在存储资源112和内存资源113内的数据，执行计算设备的各种功能。处理器1112可以和处理器1111具有相同物理形态的处理器，也可以和处理器1111具有不同物理形态的处理器。但处理器1112是具备计算能力的处理芯片，用于分担处理器1111的运行的进程，以减轻处理器1111的计算负担。
内存资源113包含非易失性内存1131和易失性内存1132。易失性内存包括随机存取存储器(random access memory，RAM)。非易失性内存具有非易失、按字节存取、存储密度高、低能耗、读写性能接近动态随机存取存储器(dynamic random access memory，DRAM)，但读写速度不对称，读远快于写，寿命有限。当电流关掉后，非易失性内存存储的数据不会消失。常见的非易失性内存包含相变存储器(phase change memory，PCM)、磁阻式存储器(magnetoresistive RAM，MRAM)、电阻式/阻变存储器(resistive RAM，RRAM)、铁电存储器(ferroelectric RAM，FeRAM)、赛道存储器(racetrack memory)和石墨烯存储器(graphene memory)。
在物理形态上，存储资源112可以是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(random access memory，RAM)或者可存储信息和指令的其他类型的动态存储设备，也可以是电可擦可编程只读存储器(electrically erasable programmable read-only memory，EEPROM)、只读光盘(compact disc read-only memory，CD-ROM)或其他光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。存储资源112可以是独立存在，还可以是通过通信总线与计算资源111相连接。存储资源112也可以和计算资源111集成在一起，不予限定。通信总线可以是工业标准体系结构(industry standard architecture，ISA)总线、外部设备互连(peripheral component，PCI)总线或扩展工业标准体系结构(extended industry standard architecture，EISA)总线等。该总线可以分为地址总线、数据总线、控制总线等。
另外，存储资源112还用于存储执行本申请方案的软件程序，并由计算资源111来控制 执行。
用户可以通过终端设备130访问云服务平台120提供的各种服务(如：金融服务、游戏服务等)。在计算设备运行不同用户的多个服务的进程114时，多个服务的进程共享基础资源(如：计算资源111、存储资源112和内存资源113等)。
为了避免多个进程共享基础资源带来不公平的问题，采用资源控制组(control group，cgroup)技术将多个进程划分为不同的进程组，不同的进程组使用不同的资源(如：计算资源、存储资源和内存资源)。一个进程组包括至少一个进程。
资源控制组是一种资源控制机制，即将操作系统中的所有进程以组为单位划分，所有进程组以层级结构进行组织。每个进程组指定一组访问资源(如：计算资源、存储资源和内存资源)。不同的进程组访问不同的资源。例如，不同的进程组中的进程访问的内存的内存大小不同和内存的内存带宽不同。系统管理员可以通过第一文件系统接口配置每个进程组所包含的进程。第一文件系统接口用于配置进程组所包含的进程。一个用户的应用进程可以划分到同一个进程组，也可以划分到不同的进程组。进程组可以包含同一个应用的进程，也可以包含不同应用的进程。
处理器核在运行进程组包含的进程时既可访问易失性内存又访问非易失性内存。传统技术中，采用资源调配技术(resource director technology)识别占用大量易失性内存的内存带宽的进程并限制该进程占用易失性内存的内存带宽，以确保其他进程获取充足的内存资源。由于非易失性内存未提供内存带宽限制功能，资源调配技术无法实现对非易失性内存的内存带宽的监控和限制。本实施例提供一种监控内存带宽的方法，依据预设周期内进程组访问易失性内存所使用的内存带宽大小和内存操作预估进程组访问非易失性内存所使用的内存带宽大小，从而实现了以进程组为粒度监控非易失性内存的内存带宽，进而将非易失性内存的内存带宽大小作为限制内存带宽的依据。
接下来，结合图2，对本实施例提供的监控内存带宽的方法进行详细说明。
S201、第一处理器核获取预设周期内进程组访问易失性内存所使用的内存带宽大小，以及统计进程组在预设周期内执行的内存操作。
内核是一个操作系统的核心，负责管理系统的进程、内存、设备驱动程序、文件和网络系统，决定着系统的性能和稳定性。第一处理器核运行一个进程组中的进程时，可以采用内存带宽监控(memory bandwidth monitor，MBM)技术查看内核中内存管理的信息获取预设周期内进程组访问易失性内存所使用的内存带宽大小。预设周期可以是1秒。
内存操作包括非易失性内存操作和易失性内存操作。进程组在预设周期内执行的内存操作可理解为进程组在预设周期内执行的内存操作所访问的内存地址。
在一些实施例中，第一处理器核监控文件系统的读写接口，采集在预设周期内通过文件系统的读写接口对系统中内存的内存操作，获取内存操作所访问的内存地址。由于系统中包含非易失性内存和易失性内存，内存操作所访问的内存地址包括非易失性内存的内存地址和易失性内存的内存地址。
在另一些实施例中，第一处理器核利用基于精准事件采样(precise event based sampling，PEBS)技术采集其他访问内存的内存操作。其他访问内存的内存操作包括但不限于：将一个文件或者其它对象映射进内存的内存操作，访问共享内存的内存操作，访问文件描述符的内存操作，访问管道文件的内存操作。
可选的，预设周期内执行的内存操作是预设周期内全部内存操作或部分内存操作。例如， 第一处理器核统计的内存操作可以是预设周期内一部分时长的内存操作。比如，一半预设周期的时长的内存操作。所述内存操作包括易失性内存的内存读写操作和非易失性内存的内存读写操作。
S202、第一处理器核根据内存带宽大小和统计的内存操作计算进程组访问非易失性内存所使用的内存带宽大小。
具体的，图3所述的方法流程是对图2中S202所包括的具体操作过程的阐述，如图所示：S2021、第一处理器核根据内存操作所访问的内存地址确定进程组访问非易失性内存的访问量和进程组访问易失性内存的访问量的比例。S2022、第一处理器核根据内存带宽大小和比例计算进程组访问非易失性内存所使用的内存带宽大小。
由于内存操作所访问的内存地址包括进程组执行的非易失性内存操作所访问的内存地址和进程组执行的易失性内存操作所访问的内存地址。依据内存操作所访问的内存地址可以确定内存操作所访问的内存的内存类型包括非易失性内存和易失性内存。
依据进程组执行非易失性内存的内存操作所访问的内存地址可以确定非易失性内存的访问量。非易失性内存的访问量可理解为进程组访问非易失性内存的内存大小。
依据进程组执行易失性内存的内存操作所访问的内存地址可以确定易失性内存的访问量。易失性内存的访问量可理解为进程组访问易失性内存的内存大小。
进而，第一处理器核根据进程组访问非易失性内存的内存大小和进程组访问易失性内存的内存大小确定进程组访问非易失性内存的访问量和进程组访问易失性内存的访问量的比例。
进程组访问非易失性内存所使用的内存带宽大小满足公式(1)。
B2＝B1*(d2/d1)    (1)
其中，B2表示预设周期内进程组访问非易失性内存所使用的内存带宽大小，B1表示预设周期内进程组访问易失性内存所使用的内存带宽大小，d1表示预设周期内进程组访问易失性内存的访问量，d2表示预设周期内进程组访问非易失性内存的访问量。d2/d1表示进程组访问非易失性内存的访问量和进程组访问易失性内存的访问量的比例。
可理解的，第一处理器核可以采用MBM技术查看内核中内存管理的信息获取预设周期内进程组访问易失性内存所使用的内存带宽大小B1。d1和d2是第一处理器核采集通过文件系统的读写接口对系统中内存的内存操作和其他访问内存的内存操作获取的。
示例的，系统管理员可以为用户的服务进程分配唯一的标识符，第一处理器核利用该标识符监控预设周期内进程组访问易失性内存所使用的内存带宽大小，以及采样进程组执行的内存操作所访问的内存地址。具体的，第一处理器核监测到预设周期的起始时刻T1的内存带宽监控值为Bo，以及预设周期的结束时刻T2的内存带宽监控值为Bn，Bn与Bo的差的绝对值为预设周期内进程组访问易失性内存所使用的内存带宽大小。假设预设周期内进程组访问易失性内存所使用的内存带宽大小B1为10G/s，第一处理器核在预设周期内采样到60000个内存操作所访问的内存地址，其中，20000个地址为非易失性内存的地址，40000个地址为易失性内存的地址。进程组访问非易失性内存的访问量和进程组访问易失性内存的访问量的比例为20000/40000＝0.5。进程组访问非易失性内存所使用的内存带宽大小为20000/40000*10G/s＝5G/s。
如此，处理器核基于预设周期内的非易失性内存操作、易失性内存操作和进程组访问易失性内存所使用的内存带宽大小估计进程组访问易失性内存所使用的内存带宽大小，通过软 件方法实现了以进程组为粒度监控非易失性内存的内存带宽，进而将非易失性内存的内存带宽大小作为限制非易失性内存的内存带宽的依据。
进一步的，监控到进程组访问非易失性内存所使用的内存带宽大小(简称：非易失性内存的内存带宽大小)后，可以将非易失性内存的内存带宽大小作为限制非易失性内存的内存带宽的依据，结合图4，对本实施例提供的限制内存带宽的方法进行详细说明。
S401、第一处理器核判断非易失性内存的内存带宽大小是否大于或等于非易失性内存带宽阈值。
若非易失性内存的内存带宽大小大于或等于非易失性内存带宽阈值，执行S402；若非易失性内存的内存带宽大小小于非易失性内存带宽阈值，此时，如果第一处理器核未设置过进程组的内存带宽限制，继续执行S201和S202。可选的，如果第一处理器核设置进程组的内存带宽限制，执行S403。非易失性内存带宽阈值为访问非易失性内存允许使用的内存带宽的最大值。系统管理员可以通过第二文件系统接口设置不同进程组访问非易失性内存的非易失性内存带宽阈值。例如，可以限制不同的进程组在每个预设周期内所允许使用的非易失性内存带宽。
S402、第一处理器核设置进程组的内存带宽限制。
第一处理器核设置进程组的内存带宽限制后，执行S201和S202，即继续监控进程组访问非易失性内存所使用的内存带宽大小，判断非易失性内存的内存带宽大小是否大于或等于非易失性内存带宽阈值。
S403、第一处理器核解除进程组的内存带宽限制。
第一处理器核解除进程组的内存带宽限制的方法可以是设置进程组的内存带宽限制的反向操作。第一处理器核解除进程组的内存带宽限制后，执行S201和S202，即继续监控进程组访问非易失性内存所使用的内存带宽大小，判断非易失性内存的内存带宽大小是否大于或等于非易失性内存带宽阈值。
下面对第一处理器核设置进程组的内存带宽限制的具体实现方式进行详细说明。
在第一种可能的实现方式中，第一处理器核将进程组的第一易失性内存带宽阈值调整为第二易失性内存带宽阈值。其中，第一易失性内存带宽阈值大于第二易失性内存带宽阈值，第一易失性内存带宽阈值和第二易失性内存带宽阈值均指进程组访问易失性内存允许使用的内存带宽的最大值。第一处理器核可以调用第三文件系统接口调整进程组访问易失性内存允许使用的内存带宽的最大值。
在一些实施例中，第一处理器核可以以调节步长为0.2G/s的粒度调节第一易失性内存带宽阈值。例如，若第i预设周期内的非易失性内存的内存带宽大小大于或等于非易失性内存带宽阈值，第一处理器核将第一易失性内存带宽阈值减小0.2G/s，得到第三易失性内存带宽阈值，第三易失性内存带宽阈值大于第二易失性内存带宽阈值。进而，第一处理器核获取第i+1预设周期内的非易失性内存的内存带宽大小，若第i+1预设周期内的非易失性内存的内存带宽大小大于或等于非易失性内存带宽阈值，第一处理器核将第三易失性内存带宽阈值继续减小0.2G/s，得到第四易失性内存带宽阈值，第四易失性内存带宽阈值大于第二易失性内存带宽阈值。若第i+1预设周期内的非易失性内存的内存带宽大小小于非易失性内存带宽阈值，无需再设置进程组的内存带宽限制。i为整数。系统管理员可以根据业务需要等因素设置调节步长。
如果第一处理器核以0.2G/s的粒度调节第一易失性内存带宽阈值，直到第一易失性内 存带宽阈值减小到了第二易失性内存带宽阈值，但是非易失性内存的内存带宽大小仍然大于或等于非易失性内存带宽阈值，第一处理器执行第二种可能的实现方式，即第一处理器核将进程组包含的进程从运行进程组的第一处理器核迁移到第二处理器核。
可理解的，第二易失性内存带宽阈值就是限制进程组访问易失性内存所使用的内存带宽的最大限制。系统管理员可以通过第三文件系统接口设置第一易失性内存带宽阈值。系统管理员可以是业务部署的人员。例如，系统管理员采用易失性内存的内存带宽分配(memory bandwidth allocation，MBA)技术通过第三文件系统接口为进程组设置第一易失性内存带宽阈值。
由于降低了进程组使用的易失性内存的内存带宽的最大值，也就是限制进程组访问易失性内存，进程组使用的易失性内存的内存带宽随之降低，从而进程组使用易失性内存和非易失性内存的总的内存带宽大小也随之降低，间接地进程组使用的非易失性内存的内存带宽也随之降低，实现限制非易失性内存的内存带宽到任意值。
在第二种可能的实现方式中，第一处理器核将进程组包含的进程从运行进程组的第一处理器核迁移到第二处理器核，第二处理器核运行该进程组中迁移出的进程。第二处理器核可以是运行进程较少的第一处理器核。从第一处理器核迁移到第二处理器核的进程的个数可以由系统管理员设置或系统自行确定。第一处理器核每次可以迁移一个进程，也可以迁移两个进程，不予限定。如果第一处理器核将进程组包含的一半的进程迁移到第二处理器核，非易失性内存的内存带宽大小仍然大于或等于非易失性内存带宽阈值，第一处理器执行第三种可能的实现方式，即第一处理器核将进程组的第一时间片调整为第二时间片，第一时间片大于第二时间片。
由于减少了第一处理器核运行的进程组包含的进程的个数，进程组对易失性内存和非易失性内存的内存操作便随之减少，进程组使用易失性内存和非易失性内存的总的内存带宽大小也随之降低，间接地进程组使用的非易失性内存的内存带宽也随之降低，达到限制非易失性内存的内存带宽到任意值。
在一些实施例中，第一处理器核和第二处理器核属于NUMA系统中一个或多个NUMA节点。可理解的，第一处理器核和第二处理器核属于NUMA系统中同一个NUMA节点，或者第一处理器核和第二处理器核属于NUMA系统中不同的NUMA节点。
通常，NUMA系统包括多个节点，每个节点包括多个处理器核。一个处理器包含多个物理处理器核。每个物理处理器核还可以分为两个逻辑处理器核。一个物理处理器中的逻辑处理器核可以划分为多个NUMA节点(简称：节点)。
值得说明的是，第一处理器核可以物理处理器核也可以是逻辑处理器核。若第一处理器核是一个物理处理器核，该第一处理器核包含多个逻辑处理器核。第一处理器核和第二处理器核可以是同一个处理器中的核，也可以是不同处理器中的核。
示例的，如图5所示，处理器包含8个处理器核，8个处理器核可以是物理处理器核也可以是逻辑处理器核。8个处理器核被划分为了2个节点。假设处理器核1运行进程组，处理器核1可以将进程组中的一个进程从处理器核1迁移到处理器核2。或者，处理器核1可以将进程组中的进程从处理器核1迁移到处理器核5。
在第三种可能的实现方式中，第一处理器核将进程组的第一时间片调整为第二时间片，第一时间片大于第二时间片，第一时间片和第二时间片均为进程组占用第一处理器核的时长。第一处理器核可以调用文件系统的接口调整进程组占用第一处理器核的时长。
由于降低了分配给进程组的第一处理器核运行进程组中的进程的时长，从而缩短了第一处理器核运行进程组中的进程的时长，进程组对易失性内存和非易失性内存的内存操作便随之减少，进程组使用易失性内存和非易失性内存的总的内存带宽大小也随之降低，间接地进程组使用的非易失性内存的内存带宽也随之降低，达到限制非易失性内存的内存带宽到任意值。
第一处理器核根据进程组在第i预设周期内使用的非易失性内存带宽大小和非易失性内存带宽阈值来加强或放松对该进程组的限制，从而允许该进程组在第i+1预设周期内使用更少或更多的非易失性内存带宽资源。
从而，通过限制措施控制进程组访问易失性内存所使用的内存带宽大小，间接限制进程组访问非易失性内存所使用的内存带宽大小。避免由于进程组、容器或者虚拟机使用过多的非易失性内存带宽，影响其他进程组、容器或者虚拟机无法访问非易失性内存，解决了邻位干扰故障扩散导致的业务性能劣化甚至中断的问题。
上述实施例中，第一处理器核从三种可能的实现方式中任选一种限制进程组所使用的非易失性内存的内存带宽。但是，限制进程组所使用的非易失性内存的内存带宽后，非易失性内存的内存带宽大小可能仍然大于或等于非易失性内存带宽阈值。此时，第一处理器核还可以动态限制非易失性内存的内存带宽，如图6所示，本实施例还提供一种动态限制内存带宽的方法。
S601、第一处理器核获取预设周期内进程组访问非易失性内存所使用的第一内存带宽大小。
S602、第一处理器核判断非易失性内存的第一内存带宽大小是否大于或等于非易失性内存带宽阈值。
若进程组访问非易失性内存所使用的第一内存带宽大小大于或等于非易失性内存带宽阈值，执行S603。若进程组访问非易失性内存所使用的第一内存带宽大小小于非易失性内存带宽阈值，执行S604。
S603、第一处理器核将进程组的第一易失性内存带宽阈值调整为第二易失性内存带宽阈值。执行S604。
S604、第一处理器核获取预设周期内进程组访问非易失性内存所使用的第二内存带宽大小。
S605、第一处理器核判断非易失性内存的第二内存带宽大小是否大于或等于非易失性内存带宽阈值。
若进程组访问非易失性内存所使用的第二内存带宽大小大于或等于非易失性内存带宽阈值，执行S606。若进程组访问非易失性内存所使用的第二内存带宽大小小于非易失性内存带宽阈值，执行S607。
可选的，如果第一处理器核将进程组的第一易失性内存带宽阈值调整为第二易失性内存带宽阈值后，进程组访问非易失性内存所使用的第二内存带宽大小小于非易失性内存带宽阈值，第一处理器核还可以根据调节步长将进程组的第二易失性内存带宽阈值调整为第一易失性内存带宽阈值。例如，业务需求增加时，第一处理器核还可以根据调节步长调节进程组的第二易失性内存带宽阈值至第一易失性内存带宽阈值。
S606、第一处理器核将进程组包含的进程从运行进程组的第一处理器核迁移到第二处理器核。执行S607。
S607、第一处理器核获取预设周期内进程组访问非易失性内存所使用的第三内存带宽大小。
S608、第一处理器核判断非易失性内存的第三内存带宽大小是否大于或等于非易失性内存带宽阈值。
若进程组访问非易失性内存所使用的第三内存带宽大小大于或等于非易失性内存带宽阈值，执行S609。若进程组访问非易失性内存所使用的第三内存带宽大小小于非易失性内存带宽阈值，执行S610。
可选的，如果第一处理器核将进程组包含的进程从运行进程组的第一处理器核迁移到第二处理器核后，进程组访问非易失性内存所使用的第三内存带宽大小小于非易失性内存带宽阈值，第一处理器核还可以将进程组包含的进程从第二处理器核迁移到第一处理器核。
S609、第一处理器核将进程组的第一时间片调整为第二时间片。执行S610。
第一处理器核获取进程组访问非易失性内存所使用的内存带宽大小(包括第一内存带宽大小、第二内存带宽大小和第三内存带宽大小)的具体方法可以参考S201和S202的详细阐述，不予赘述。S603的详细解释可以参考上述在第一种可能的实现方式的阐述。S606的详细解释可以参考上述在第二种可能的实现方式的阐述。S609的详细解释可以参考上述在第三种可能的实现方式的阐述。
需要说明的是，第一处理器核利用三种可能的实现方式中一种方式限制进程组所使用的非易失性内存的内存带宽后，周期性地监测进程组所使用的非易失性内存的内存带宽大小。第一处理器核可以在相邻的预设周期内获取非易失性内存的内存带宽大小，也可以在非相邻的预设周期内获取非易失性内存的内存带宽大小。例如，第一处理器核在第i预设周期内获取进程组访问非易失性内存所使用的第一内存带宽大小，第一处理器核可以在第i+1预设周期内获取进程组访问非易失性内存所使用的第二内存带宽大小，第一处理器核也可以在第i+2预设周期内获取进程组访问非易失性内存所使用的第二内存带宽大小。i为整数。第一处理器获取非易失性内存的内存带宽大小间隔的周期个数不予限定。
上述实施例中，第一处理器核采用动态方式限制非易失性内存的内存带宽。在限制非易失性内存的内存带宽后，若非易失性内存的内存带宽小于非易失性内存带宽阈值，还可以增加进程组的内存带宽，即解除对非易失性内存的内存带宽的限制，使得进程组有充足的可用资源。如图7所示，本实施例还提供一种动态限制内存带宽的方法。
S610、第一处理器核获取预设周期内进程组访问非易失性内存所使用的第四内存带宽大小。
S611、第一处理器核确定非易失性内存的第四内存带宽大小小于非易失性内存带宽阈值。执行S612。
S612、第一处理器核将进程组的第二时间片调整为第一时间片。执行S613。
第一处理器核将进程组的第二时间片调整为第一时间片，即增加了进程组占用处理器核的时长，从而进程组对易失性内存和非易失性内存的内存操作便随之增加，进程组使用易失性内存和非易失性内存的总的内存带宽大小也随之提升，间接地进程组使用的非易失性内存的内存带宽也随之提升，使得进程组有充足的可用资源。具体的调节方法是将进程组的第一时间片调整为第二时间片的反向过程，具体的可以参考上述第三种可能的实现方式的具体阐述。
S613、第一处理器核获取预设周期内进程组访问非易失性内存所使用的第五内存带宽大 小。
S614、第一处理器核确定非易失性内存的第五内存带宽大小小于非易失性内存带宽阈值。执行S615。
S615、第一处理器核将进程组包含的进程从第二处理器核迁移到第一处理器核。执行S616。
可理解的，从第二处理器核迁移到第一处理器核的进程是第一处理器核从第一处理器核迁移到第二处理器核的进程组包含的进程。具体的迁移方式可以参考上述第二种可能的实现方式的具体阐述。由于增加了处理器核运行的进程组包含的进程的个数，进程组对易失性内存和非易失性内存的内存操作便随之增加，进程组使用易失性内存和非易失性内存的总的内存带宽大小也随之增加，间接地进程组使用的非易失性内存的内存带宽也随之提升，使得进程组有充足的可用资源。
S616、第一处理器核获取预设周期内进程组访问非易失性内存所使用的第六内存带宽大小。
S617、第一处理器核确定非易失性内存的第六内存带宽大小小于非易失性内存带宽阈值。执行S618。
S618、第一处理器核将进程组的第二易失性内存带宽阈值调整为第一易失性内存带宽阈值。第一处理器核继续监测预设周期内进程组访问非易失性内存所使用的内存带宽大小。由于增加了进程组使用的易失性内存的内存带宽的最大值，从而进程组使用易失性内存和非易失性内存的总的内存带宽大小也随之增加，间接地进程组使用的非易失性内存的内存带宽也随之提升，使得进程组有充足的可用资源。第一处理器核可以根据调节步长增加易失性内存带宽阈值至第一易失性内存带宽阈值。根据调节步长增加易失性内存带宽阈值的方法是降低易失性内存带宽阈值的反向过程，具体的调节易失性内存带宽阈值方式可以参考上述第一种可能的实现方式的具体阐述。
第一处理器核获取进程组访问非易失性内存所使用的内存带宽大小(包括第四内存带宽大小、第五内存带宽大小和第六内存带宽大小)的具体方法可以参考S201和S202的详细阐述，不予赘述。
示例的，如图8中的(a)所示，在用户态，系统管理员通过文件系统中不同的接口配置进程组、设置非易失性内存带宽阈值和设置易失性内存带宽阈值。例如，系统管理员通过第一文件系统接口配置进程组。系统管理员通过第二文件系统接口设置非易失性内存带宽阈值。系统管理员通过第三文件系统接口设置第一易失性内存带宽阈值。
第一处理器核采用MBM技术查看内核中内存管理的信息获取预设周期内进程组访问易失性内存所使用的内存带宽大小，以及采集通过文件系统的读写接口对系统中内存的内存操作和其他访问内存的内存操作。第一处理器核中的监控模块根据内存带宽大小和统计的内存操作计算进程组访问非易失性内存所使用的内存带宽大小。若非易失性内存的内存带宽大小大于或等于非易失性内存带宽阈值，第一处理器核中的限制模块采用上述调整易失性内存带宽阈值、迁移进程和调整进程组的占用第一处理器核的时间片中任一种设置进程组的内存带宽限制。
假设非易失性内存带宽阈值B2’为5GB/s。若进程组使用的非易失性内存带宽B2为3GB/s，此时，进程组使用的非易失性内存带宽3GB/s低于非易失性内存带宽阈值5GB/s，即B2＝3GB/s<B2’＝5GB/s，不限制进程组使用的非易失性内存带宽。
若进程组使用的非易失性内存带宽为15GB/s，此时，进程组使用的非易失性内存带宽15GB/s大于非易失性内存带宽阈值5GB/s，即B2＝15GB/s>B2’＝5GB/s。如图8中的(b)所示，第一处理器核调节易失性内存带宽阈值B1’，即将进程组的第一易失性内存带宽阈值调整为第二易失性内存带宽阈值。
调节易失性内存带宽阈值(最大限制)后，进程组使用的非易失性内存带宽为12GB/s。进程组使用的非易失性内存带宽12GB/s大于非易失性内存带宽阈值5GB/s，即B2＝12GB/s>B2’＝5GB/s，第一处理器核迁移进程组的进程，即将进程组包含的进程从运行进程组的第一处理器核迁移到第二处理器核。
迁移进程后，进程组使用的非易失性内存带宽为6GB/s。进程组使用的非易失性内存带宽6GB/s大于非易失性内存带宽阈值5GB/s，即B2＝6GB/s>B2’＝5GB/s，第一处理器核调节进程组占用第一处理器核的时长，即将进程组的第一时间片调整为第二时间片。例如，第一时间片为预设周期的时长。第二时间片为预设周期的时长的83％。
调节进程组占用第一处理器核的时长(最大限制)后，进程组使用的非易失性内存带宽为1GB/s。进程组使用的非易失性内存带宽1GB/s小于非易失性内存带宽阈值5GB/s，即B2＝1GB/s<B2’＝5GB/s。第一处理器核调节进程组占用第一处理器核的时长，即将进程组的第二时间片调整为第一时间片。
调节进程组占用第一处理器核的时长后，进程组使用的非易失性内存带宽为2GB/s。进程组使用的非易失性内存带宽2GB/s小于非易失性内存带宽阈值5GB/s，即B2＝2GB/s<B2’＝5GB/s。第一处理器核迁移进程组的进程，即将进程组包含的进程从运行进程组的第二处理器核迁移到第一处理器核。
迁移进程后，进程组使用的非易失性内存带宽为3GB/s。进程组使用的非易失性内存带宽3GB/s小于非易失性内存带宽阈值5GB/s，即B2＝3GB/s<B2’＝5GB/s。第一处理器核调节易失性内存带宽阈值，即将进程组的第二易失性内存带宽阈值调整为第一易失性内存带宽阈值。
可以理解的是，为了实现上述实施例中功能，服务器包括了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本申请中所公开的实施例描述的各示例的单元及方法步骤，本申请能够以硬件或硬件和计算机软件相结合的形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用场景和设计约束条件。
上文中结合图1至图8，详细描述了根据本实施例所提供的监控内存带宽的方法和限制内存带宽的方法，下面将结合图9至图11描述根据本实施例所提供的监控内存带宽的装置、限制内存带宽的装置和服务器。
图9为本实施例提供的可能的监控内存带宽的装置的结构示意图。这些监控内存带宽的装置可以用于实现上述方法实施例中处理器核的功能，因此也能实现上述方法实施例所具备的有益效果。在本实施例中，该监控内存带宽的装置可以是如图1所示的处理器核0，还可以是应用于服务器的模块(如芯片)。
如图9所示，监控内存带宽的装置900包括获取单元910、监控单元920和限制单元930。监控内存带宽的装置900用于实现上述图2、图3或图4中所示的方法实施例中第一处理器核的功能。
当监控内存带宽的装置900用于实现图2所示的方法实施例中第一处理器核的功能时： 获取单元910用于实现S201中第一处理器核所执行的功能；监控单元920用于实现S202中第一处理器核所执行的功能。
当监控内存带宽的装置900用于实现图3所示的方法实施例中第一处理器核的功能时：获取单元910用于实现S201中第一处理器核所执行的功能；监控单元920用于实现S2021和S2022中第一处理器核所执行的功能。
当监控内存带宽的装置900用于实现图4所示的方法实施例中第一处理器核的功能时：获取单元910用于实现S201中第一处理器核所执行的功能；监控单元920用于实现S202中第一处理器核所执行的功能；限制单元930用于实现S401、S402和S403中第一处理器核所执行的功能。
有关上述获取单元910、监控单元920和限制单元930更详细的描述可以直接参考图2、图3或图4所示的方法实施例中相关描述直接得到，这里不加赘述。
图10为本实施例提供的可能的限制内存带宽的装置的结构示意图。这些限制内存带宽的装置可以用于实现上述方法实施例中处理器核的功能，因此也能实现上述方法实施例所具备的有益效果。在本实施例中，该限制内存带宽的装置可以是如图1所示的处理器核0，还可以是应用于服务器的模块(如芯片)。
如图10所示，限制内存带宽的装置1000包括获取单元1010和限制单元1020。限制内存带宽的装置1000用于实现上述图6或图7中所示的方法实施例中第一处理器核的功能。
当限制内存带宽的装置1000用于实现图6所示的方法实施例中第一处理器核的功能时：获取单元1010用于实现S601、S604、S607和S610中第一处理器核所执行的功能；限制单元1020用于实现S602、S603、S605、S606、S608和S609中第一处理器核所执行的功能。
当限制内存带宽的装置1000用于实现图7所示的方法实施例中第一处理器核的功能时：获取单元1010用于实现S610、S613和S616中第一处理器核所执行的功能；限制单元1020用于实现S611、S612、S614、S615、S617和S618中第一处理器核所执行的功能。
有关上述获取单元1010和限制单元1020更详细的描述可以直接参考图6或图7所示的方法实施例中相关描述直接得到，这里不加赘述。
可以理解的是，本实施例中的处理器可以是中央处理单元(Central Processing Unit，CPU)，还可以是其它通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现场可编程门阵列(Field Programmable Gate Array，FPGA)或者其它可编程逻辑器件、晶体管逻辑器件，硬件部件或者其任意组合。通用处理器可以是微处理器，也可以是任何常规的处理器。
处理器还可以是图形处理器(graphics processing unit，GPU)、神经网络处理器(neural network processing unit，NPU)、微处理器、特定应用集成电路(application-specific integrated circuit，ASIC)、或一个或多个用于控制本申请方案程序执行的集成电路。
图11为本实施例提供的一种服务器1100的结构示意图。如图所示，服务器1100包括处理器1110、总线1120、通信接口1150、主存1130和存储器1140。
应理解，在本实施例中，处理器1110可以是中央处理器(central processing unit，CPU)，该处理器1110还可以是其他通用处理器、数字信号处理器(digital signal processing，DSP)、专用集成电路(application-specific integrated circuit，ASIC)、现场可编程门阵列(field-programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者是任何常规 的处理器等。
通信接口1150用于实现服务器1100与外部设备或器件的通信。
总线1120可以包括一通路，用于在上述组件(如处理器1110、主存1130和存储器1140)之间传送信息。总线1120除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图中将各种总线都标为总线1120。
作为一个示例，服务器1100可以包括多个处理器。处理器可以是一个多核(multi-CPU)处理器。这里的处理器可以指一个或多个设备、电路、和/或用于处理数据(例如计算机程序指令)的计算单元。处理器1110可以监控运行的进程组在预设周期内访问易失性内存所使用的内存带宽大小，以及统计进程组在预设周期内执行的内存操作，根据内存带宽大小和统计的内存操作计算进程组访问非易失性内存所使用的内存带宽大小。若非易失性内存的内存带宽大小大于或等于非易失性内存带宽阈值，设置进程组的内存带宽限制。监控非易失性内存的内存带宽大小和设置进程组的内存带宽限制的具体的过程可以参考上述方法实施例中相关描述直接得到，这里不加赘述。
值得说明的是，图11中仅以服务器1100包括1个处理器1110和1个主存1130为例，此处，处理器1110和主存1130分别用于指示一类器件或设备，具体实施例中，可以根据业务需求确定每种类型的器件或设备的数量。
存储器1140可以用于存储云环境中的相关信息，例如，磁盘，如机械硬盘或固态硬盘。
上述服务器1100可以是一个通用设备或者是一个专用设备。例如，服务器1100可以是基于X86、ARM的服务器，也可以为其他的专用服务器，如策略控制和计费(policy control and charging，PCC)服务器等。本申请实施例不限定服务器1100的类型。
应理解，根据本实施例的服务器1100可对应于本实施例中的监控内存带宽的装置900和限制内存带宽的装置1000，并可以对应于执行根据图2至图4、以及图6和图7中任一方法中的相应主体，并且装置中的各个模块的上述和其它操作和/或功能分别为了实现图2至图4、以及图6和图7中的各个方法的相应流程，为了简洁，在此不再赘述。
本实施例还提供一种处理器，该处理器的结构如图11所示，包括多个处理器核，用于实现如图2至图4、以及图6和图7所述方法的操作步骤，为了避免重复，在此不再赘述。
本实施例中的方法步骤可以通过硬件的方式来实现，也可以由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于随机存取存储器(random access memory，RAM)、闪存、只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)、寄存器、硬盘、移动硬盘、CD-ROM或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。另外，该ASIC可以位于网络设备或终端设备中。当然，处理器和存储介质也可以作为分立组件存在于网络设备或终端设备中。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机程序或指令。在计算机上加载和执行所述计算机程序或指令时，全部或部分地执行本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、 计算机网络、网络设备、用户设备或者其它可编程装置。所述计算机程序或指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机程序或指令可以从一个网站站点、计算机、服务器或数据中心通过有线或无线方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是集成一个或多个可用介质的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，例如，软盘、硬盘、磁带；也可以是光介质，例如，数字视频光盘(digital video disc，DVD)；还可以是半导体介质，例如，固态硬盘(solid state drive，SSD)。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (31)

  1. 一种监控内存带宽的方法，其特征在于，包括：
    获取预设周期内进程组访问易失性内存所使用的内存带宽大小，以及统计所述进程组在所述预设周期内执行的内存操作，所述内存操作包括非易失性内存操作和易失性内存操作，所述进程组包括至少一个进程；
    根据所述内存带宽大小和统计的所述内存操作计算所述进程组访问非易失性内存所使用的第一内存带宽大小。
  2. 根据权利要求1所述的方法，其特征在于，所述进程组在所述预设周期内执行的内存操作，包括：
    所述进程组在所述预设周期内执行的内存操作所访问的内存地址。
  3. 根据权利要求1或2所述的方法，其特征在于，根据所述内存带宽大小和统计的所述内存操作计算所述进程组访问非易失性内存所使用的第一内存带宽大小，包括：
    根据所述内存操作所访问的内存地址确定所述进程组访问所述非易失性内存的访问量和所述进程组访问所述易失性内存的访问量的比例；
    根据所述内存带宽大小和所述比例计算所述进程组访问所述非易失性内存所使用的第一内存带宽大小。
  4. 根据权利要求3所述的方法，其特征在于，根据所述内存操作所访问的内存地址确定所述进程组访问所述非易失性内存的访问量和所述进程组访问所述易失性内存的访问量的比例，包括：
    根据所述内存操作所访问的内存地址确定所述内存操作的内存大小和内存类型，所述内存类型包括所述易失性内存和所述非易失性内存，所述内存大小包括所述进程组访问所述易失性内存的内存大小和所述进程组访问所述非易失性内存的内存大小；
    根据所述内存操作的内存大小和所述内存类型确定所述进程组访问所述非易失性内存的访问量和所述进程组访问所述易失性内存的访问量的比例。
  5. 根据权利要求1-4中任一项所述的方法，其特征在于，所述预设周期内执行的内存操作是全部内存操作或部分内存操作。
  6. 根据权利要求1-5中任一项所述的方法，其特征在于，所述内存操作为内存读写操作。
  7. 根据权利要求1-6中任一项所述的方法，其特征在于，在根据所述内存带宽大小和统计的所述内存操作计算所述进程组访问非易失性内存所使用的第一内存带宽大小之后，所述方法还包括：
    若所述第一内存带宽大小大于或等于非易失性内存带宽阈值，设置所述进程组的内存带宽限制，所述非易失性内存带宽阈值为所述进程组访问所述非易失性内存允许使用的内存带宽的最大值。
  8. 根据权利要求7所述的方法，其特征在于，设置所述进程组的内存带宽限制包括以下一种或多种：
    将所述进程组的第一易失性内存带宽阈值调整为第二易失性内存带宽阈值，所述第一易失性内存带宽阈值大于所述第二易失性内存带宽阈值，所述第一易失性内存带宽阈值和所述第二易失性内存带宽阈值均指所述进程组访问所述易失性内存允许使用的内存带宽的最大 值；
    将所述进程组包含的进程从运行所述进程组的第一处理器核迁移到第二处理器核；
    将所述进程组的第一时间片调整为第二时间片，所述第一时间片大于所述第二时间片，所述第一时间片和所述第二时间片均为所述进程组占用所述第一处理器核的时长。
  9. 根据权利要求8所述的方法，其特征在于，将所述进程组包含的进程从运行所述进程组的第一处理器核迁移到第二处理器核，包括：
    将所述进程组的第一易失性内存带宽阈值调整为第二易失性内存带宽阈值后，当所述非易失性内存的第二内存带宽大小大于或等于所述非易失性内存带宽阈值，将所述进程组包含的进程从运行所述进程组的第一处理器核迁移到所述第二处理器核。
  10. 根据权利要求9所述的方法，其特征在于，将所述进程组的第一时间片调整为第二时间片，包括：
    将所述进程组包含的进程从运行所述进程组的第一处理器核迁移到所述第二处理器核后，当所述非易失性内存的第三内存带宽大小大于或等于所述非易失性内存带宽阈值，将所述进程组的第一时间片调整为所述第二时间片。
  11. 根据权利要求10所述的方法，其特征在于，将所述进程组的第一时间片调整为所述第二时间片之后，所述方法还包括：
    当所述非易失性内存的第四内存带宽大小小于所述非易失性内存带宽阈值，将所述进程组的第二时间片调整为所述第一时间片。
  12. 根据权利要求11所述的方法，其特征在于，将所述进程组的第二时间片调整为所述第一时间片之后，所述方法还包括：
    当所述非易失性内存的第五内存带宽大小小于所述非易失性内存带宽阈值，将所述进程组包含的进程从所述第二处理器核迁移到所述第一处理器核。
  13. 根据权利要求12所述的方法，其特征在于，将所述进程组包含的进程从所述第二处理器核迁移到所述第一处理器核之后，所述方法还包括：
    当所述非易失性内存的第六内存带宽大小小于所述非易失性内存带宽阈值，将所述进程组的第二易失性内存带宽阈值调整为所述第一易失性内存带宽阈值。
  14. 根据权利要求7-13中任一项所述的方法，其特征在于，所述非易失性内存带宽阈值是通过第一文件系统接口设置的。
  15. 根据权利要求8-14中任一项所述的方法，其特征在于，第一易失性内存带宽阈值和第二易失性内存带宽阈值是通过第二文件系统接口设置的。
  16. 根据权利要求8-15中任一项所述的方法，其特征在于，第一处理器核和第二处理器核属于非一致性内存访问NUMA系统中一个或多个NUMA节点。
  17. 一种限制内存带宽的方法，其特征在于，包括：
    若进程组在预设周期内访问非易失性内存所使用的第一内存带宽大小大于或等于非易失性内存带宽阈值，将所述进程组的第一易失性内存带宽阈值调整为第二易失性内存带宽阈值，所述非易失性内存带宽阈值为所述进程组访问所述非易失性内存允许使用的内存带宽的最大值，所述第一易失性内存带宽阈值大于所述第二易失性内存带宽阈值，所述第一易失性内存带宽阈值和所述第二易失性内存带宽阈值均指所述进程组访问易失性内存允许使用的内存带宽的最大值，所述进程组包括至少一个进程；
    当所述非易失性内存的第二内存带宽大小大于或等于所述非易失性内存带宽阈值，将所 述进程组包含的进程从运行所述进程组的第一处理器核迁移到第二处理器核。
  18. 根据权利要求17所述的方法，其特征在于，在将所述进程组包含的进程从运行所述进程组的第一处理器核迁移到所述第二处理器核之后，所述方法还包括：
    当所述非易失性内存的第三内存带宽大小大于或等于所述非易失性内存带宽阈值，将所述进程组的第一时间片调整为第二时间片，所述第一时间片大于所述第二时间片，所述第一时间片和所述第二时间片均为所述进程组占用所述第一处理器核的时长。
  19. 根据权利要求18所述的方法，其特征在于，将所述进程组的第一时间片调整为所述第二时间片之后，所述方法还包括：
    当所述非易失性内存的第四内存带宽大小小于所述非易失性内存带宽阈值，将所述进程组的第二时间片调整为所述第一时间片。
  20. 根据权利要求19所述的方法，其特征在于，将所述进程组的第二时间片调整为所述第一时间片之后，所述方法还包括：
    当所述非易失性内存的第五内存带宽大小小于所述非易失性内存带宽阈值，将所述进程组包含的进程从所述第二处理器核迁移到所述第一处理器核。
  21. 根据权利要求20所述的方法，其特征在于，将所述进程组包含的进程从所述第二处理器核迁移到所述第一处理器核之后，所述方法还包括：
    当所述非易失性内存的第六内存带宽大小小于所述非易失性内存带宽阈值，将所述进程组的第二易失性内存带宽阈值调整为所述第一易失性内存带宽阈值。
  22. 根据权利要求17-21中任一项所述的方法，其特征在于，所述非易失性内存带宽阈值是通过第一文件系统接口设置的，所述第一易失性内存带宽阈值和所述第二易失性内存带宽阈值是通过第二文件系统接口设置的。
  23. 根据权利要求17-22中任一项所述的方法，其特征在于，所述第一处理器核和所述第二处理器核属于非一致性内存访问NUMA系统中一个或多个NUMA节点。
  24. 一种监控内存带宽的装置，其特征在于，包括：
    获取单元，用于获取预设周期内进程组访问易失性内存所使用的内存带宽大小，以及统计所述进程组在所述预设周期内执行的内存操作，所述内存操作包括非易失性内存操作和易失性内存操作，所述进程组包括至少一个进程；
    监控单元，用于根据所述内存带宽大小和统计的所述内存操作计算所述进程组访问非易失性内存所使用的第一内存带宽大小。
  25. 根据权利要求24所述的装置，其特征在于，在所述监控单元根据所述内存带宽大小和统计的所述内存操作计算所述进程组访问非易失性内存所使用的第一内存带宽大小时，所述监控单元具体用于：
    根据所述内存操作所访问的内存地址确定所述进程组访问所述非易失性内存的访问量和所述进程组访问所述易失性内存的访问量的比例；
    根据所述内存带宽大小和所述比例计算所述进程组访问所述非易失性内存所使用的第一内存带宽大小。
  26. 根据权利要求24或25所述的装置，其特征在于，所述装置还包括限制单元，
    所述限制单元，用于若所述第一内存带宽大小大于或等于非易失性内存带宽阈值，设置所述进程组的内存带宽限制，所述非易失性内存带宽阈值为所述进程组访问所述非易失性内存允许使用的内存带宽的最大值。
  27. 根据权利要求26所述的装置，其特征在于，所述限制单元，具体用于设置所述进程组的内存带宽限制包括以下一种或多种，
    将所述进程组的第一易失性内存带宽阈值调整为第二易失性内存带宽阈值，所述第一易失性内存带宽阈值大于所述第二易失性内存带宽阈值，所述第一易失性内存带宽阈值和所述第二易失性内存带宽阈值均指所述进程组访问所述易失性内存允许使用的内存带宽的最大值；
    将所述进程组包含的进程从运行所述进程组的第一处理器核迁移到第二处理器核；
    将所述进程组的第一时间片调整为第二时间片，所述第一时间片大于所述第二时间片，所述第一时间片和所述第二时间片均为所述进程组占用所述第一处理器核的时长。
  28. 一种限制内存带宽的装置，其特征在于，包括：
    限制单元，用于若进程组在预设周期内访问非易失性内存所使用的第一内存带宽大小大于或等于非易失性内存带宽阈值，将所述进程组的第一易失性内存带宽阈值调整为第二易失性内存带宽阈值，所述非易失性内存带宽阈值为所述进程组访问所述非易失性内存允许使用的内存带宽的最大值，所述第一易失性内存带宽阈值大于所述第二易失性内存带宽阈值，所述第一易失性内存带宽阈值和所述第二易失性内存带宽阈值均指所述进程组访问易失性内存允许使用的内存带宽的最大值，所述进程组包括至少一个进程；
    所述限制单元，还用于当所述非易失性内存的第二内存带宽大小大于或等于所述非易失性内存带宽阈值，将所述进程组包含的进程从运行所述进程组的第一处理器核迁移到第二处理器核。
  29. 根据权利要求28所述的装置，其特征在于，在所述限制单元将所述进程组包含的进程从运行所述进程组的第一处理器核迁移到所述第二处理器核后，所述限制单元，还用于：
    当所述非易失性内存的第三内存带宽大小大于或等于所述非易失性内存带宽阈值，将所述进程组的第一时间片调整为第二时间片，所述第一时间片大于所述第二时间片，所述第一时间片和所述第二时间片均为所述进程组占用所述第一处理器核的时长。
  30. 一种服务器，其特征在于，所述服务器包括存储器和处理器，所述处理器包括多个处理器核，所述存储器用于存储一组计算机指令；当所述处理器核执行所述一组计算机指令时，实现上述权利要求1至16中任一项所述的方法。
  31. 一种服务器，其特征在于，所述服务器包括存储器和处理器，所述存储器用于存储一组计算机指令；当所述处理器核执行所述一组计算机指令时，实现上述权利要求17至23中任一项所述的方法。
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