WO2022011679A1 - Junctionless nanowire field effect transistor and method for manufacturing same - Google Patents

Abstract

A junctionless nanowire field effect transistor, comprising a junctionless nanowire (100), the junctionless nanowire (100) comprising a source region (101), a channel region (103) and a drain region (102) which are sequentially defined along the axis direction of the junctionless nanowire, wherein the channel region (103) is undoped or lightly doped; the source region (101), the drain region (102) and the channel region (103) are of the same doping type; and the doping concentration of the source region (101) and the drain region (102) is greater than the doping concentration of the channel region (103). Further disclosed is a method for manufacturing a junctionless nanowire field effect transistor, the method comprising: forming a junctionless nanowire (100); lightly doping or not doping a channel region (103); and performing doping of the same doping type as the channel region (103) on a source region (101) and a drain region (102) by means of a doping process, wherein the doping concentration is greater than the doping concentration of the channel region (103), such that when a source metal layer (301) and a drain metal layer (302) are in contact with semiconductor bulk silicon, the contact resistance caused by a Schottky barrier is reduced, the on-state current and transconductance of a device are increased, and the fluctuations caused by random doping are suppressed.

Description

Junctionless nanowire field effect transistor and method of making the same technical field

The invention relates to the field of semiconductor integrated circuit application devices, in particular to a junctionless nanowire field effect transistor and a manufacturing method thereof.

Background technique

MOS devices follow "Moore's Law", and the feature size continues to shrink proportionally. The drawbacks of MOS field effect transistor devices based on PN junctions are becoming more and more obvious: the source-drain distance is continuously shortened, resulting in short channel effects, poor gate control capability, and device performance. And reliability is seriously degraded; in order to prevent source-drain punch-through, ultra-steep doping concentration gradient is used, which severely limits the thermal budget of the device process. In addition, due to the statistical distribution of dopant atoms and the natural properties of dopant atoms that are easy to diffuse at a certain temperature, it is extremely difficult to fabricate ultra-steep PN junctions in the nanoscale range, resulting in a decrease in transistor threshold voltage and serious leakage. However, Metal-Semiconductor Field Effect Transistor (MESFET) or High Electron Mobility Transistor (HEMT) have poor thermal stability, large Schottky junction gate electrode leakage current, and logic swing. The amplitude is small, and the anti-noise ability is weak. The existence of these problems seriously restricts the further and in-depth development of the semiconductor manufacturing industry in the future.

In order to overcome the insurmountable obstacles faced by junction field effect transistor devices in the nanoscale range, junctionless nanowire field effect transistors are proposed, but the device performance of current junctionless nanowire field effect transistors is sensitive to process fluctuations. From the device level, process fluctuations will cause great fluctuations in the electrical parameters of the device, resulting in poor electrical performance stability of the device, especially the large fluctuations in parameters such as threshold voltage and drive current; in circuit applications, it will affect specific The functional realization of circuits (such as symmetrical circuits: differential amplifiers, SRAMs, etc.) can even cause errors in circuit outputs, thus limiting the application of junctionless nanowire field effect transistors in circuits.

SUMMARY OF THE INVENTION

The present invention mainly provides a junctionless nanowire field effect transistor and a manufacturing method thereof, which have good process stability and improved electrical properties.

According to a first aspect, an embodiment provides a junctionless nanowire field effect transistor, comprising: a junctionless nanowire, wherein the junctionless nanowire includes a source region, a channel region and a drain defined in sequence along its axis direction Area;

An outer surface of the source region is covered with a source electrode layer, wherein an active dielectric layer is between the source electrode layer and a part of the surface of the source region;

The outer surface of the drain region is covered with a drain electrode layer, wherein a leakage dielectric layer is arranged between the drain electrode layer and a partial surface of the drain region;

The outer peripheral surface surrounding the channel region is covered with a gate dielectric layer, and the outer peripheral surface surrounding the gate dielectric layer is covered with a gate electrode layer;

The channel region is not doped or lightly doped, the source region and the drain region have doped regions of the same doping type as the channel region, and the doping concentration of the doped region is greater than that of the channel region Doping concentration in the channel region.

Optionally, the source region, the channel region and the drain region are axially symmetric; an isolation layer is provided between the source electrode and the gate electrode; and an isolation layer is provided between the drain electrode and the gate electrode.

Optionally, the doping materials of the source region, the drain region and the channel region are the same, and the doping concentration in the source region and the drain region is 1×10 ¹⁹ cm ⁻³ to 1×10 ²¹ cm ^-3 heavy doping, the channel region is lightly doped less than or equal to 1×10 ¹⁹ cm ^{-3 .}

Optionally, part or all of the source region and the drain region are doped regions.

Optionally, the shape of the channel region is a cylinder or a prism, and the shape of the source region and the drain region is a cylinder, a prism or a truncated cone, wherein, at the connection between the source region and the channel region, the source The cross-sectional shape of the region is the same as the cross-sectional shape of the channel region; at the connection between the drain region and the channel region, the cross-sectional shape of the drain region is the same as the cross-sectional shape of the channel region.

Optionally, the source dielectric layer is located between the source electrode layer and the peripheral surface of the source region;

The drain dielectric layer is located between the drain electrode layer and the outer peripheral surface of the drain region.

Optionally, the doping type is P-type doping or N-type doping;

When the doping type is N-type doping, the work function of the source electrode layer and the drain electrode layer is smaller than the work function of the junctionless nanowire;

When the doping type is P-type doping, the work function of the source electrode layer and the drain electrode layer is greater than the work function of the junctionless nanowire.

According to a second aspect, an embodiment provides a method for fabricating a junctionless nanowire field effect transistor, the method comprising:

forming a junctionless nanowire, and defining an active region, a channel region and a drain region in sequence along the axis direction of the junctionless nanowire;

Lightly doped or undoped channel region;

Doping the source region and the drain region with the same doping type as the channel region using a doping process, and the doping concentration is greater than the doping concentration of the channel region;

forming a dielectric layer including a gate dielectric layer, a source dielectric layer, and a drain dielectric layer, wherein the gate dielectric layer covers a peripheral surface surrounding the channel region, the source dielectric layer is formed in the source region part of the outer surface of the drain region, the drain dielectric layer is formed on a part of the outer surface of the drain region;

forming a gate electrode layer, a source electrode layer and a drain electrode layer, the gate electrode layer being formed on the peripheral surface surrounding the gate dielectric layer, the source electrode layer being formed on the surface of the source dielectric layer and the source not covering the source dielectric layer On the outer surface of the region, the drain electrode layer is formed on the surface of the drain dielectric layer and the outer surface of the drain region not covered with the drain dielectric layer.

Optionally, before the formation of the junctionless nanowires, the method further includes:

A silicon substrate is provided, and a preliminary doping process and an annealing process are performed on the silicon substrate, and the preliminary doping concentration is light doping ^{less than or equal to 1×10 19} cm ^{-3 ;}

Etching the silicon substrate of a certain thickness to form junctionless nanowires, the shape of the channel region of the junctionless nanowires is a cylinder or a prism, and the shape of the source region and the drain region is a cylinder, a prism or a truncated cone, Wherein, at the connection between the source region and the channel region, the cross-sectional shape of the source region is the same as the cross-sectional shape of the channel region; at the connection between the drain region and the channel region, the drain region The cross-sectional shape is the same as the cross-sectional shape of the channel region.

Optionally, before doping the source region and the drain region using a doping process, the method further includes: forming isolation layers on both sides of the gate dielectric layer.

Optionally, the gate dielectric layer is formed by a dry oxygen oxidation method.

Optionally, the doping the source region and the drain region with the same doping type as the channel region using a doping process includes: ion implantation on the source region and the drain region. Doping is performed, and the source and drain regions are heavily doped with ^{a doping concentration of 1×10 19} cm ⁻³ to 1×10 ²¹ cm ^{−3 .}

Optionally, the doping the source region and the drain region using a doping process includes: doping part and all regions of the source region and the drain region.

Optionally, the source dielectric layer and the drain dielectric layer are made of hafnium dioxide.

Optionally, the doping type is P-type doping or N-type doping;

When the doping type is N-type doping, the work function of the source electrode layer and the drain electrode layer is smaller than the work function of the junctionless nanowire;

When the doping type is P-type doping, the work function of the source electrode layer and the drain electrode layer is greater than the work function of the junctionless nanowire.

According to the junctionless nanowire field effect transistor and its manufacturing method provided in the above-mentioned embodiments, the junctionless nanowire includes a source region, a channel region and a drain region sequentially defined along its axis direction, the source region, the drain region and the channel region are not doped, or the source region, the drain region and the channel region are all doped and of the same doping type, and the doping concentration of the source region and the drain region is greater than that of the channel region The doping concentration of the channel region; since the source and drain regions of the device and the channel region are doped with the same type of ions, and the doping concentrations of the source and drain regions and the channel region are different, the source and drain metal electrode layers and the semiconductor bulk silicon body are formed. When contacting, the contact resistance caused by the Schottky barrier is reduced, thereby increasing the on-state current and transconductance of the device; in addition, the fluctuation caused by random doping can be better suppressed, and the electrical performance of the device can be improved.

Description of drawings

1A is a schematic structural diagram of a junctionless nanowire field effect transistor;

1B is a schematic structural diagram of a junctionless nanowire field effect transistor;

FIG. 2 is a schematic structural diagram of a junctionless nanowire field effect transistor according to an embodiment of the present application;

3 is a flowchart of a method for manufacturing a junctionless nanowire field effect transistor provided by an embodiment of the present application;

4 to 7 are schematic diagrams of a method for manufacturing a junctionless nanowire field effect transistor according to an embodiment of the present application;

8 is a comparison diagram of the influence of the junctionless nanowire field effect transistor provided by the application and the traditional Charge-plasma junctionless nanowire field effect transistor on the driving current;

9 is a comparison diagram of the carrier concentration distribution in the channel of the junctionless nanowire field effect transistor provided by the application and the traditional Charge-plasma junctionless nanowire field effect transistor;

FIG. 10 is a comparison diagram of the electrical characteristics of a junctionless nanowire field effect transistor and a traditional Charge-plasma junctionless nanowire field effect transistor when the channel doping concentration changes provided by the application;

FIG. 11 is a statistical diagram of the effect of changing the doping width of the source and drain regions on the driving current of the transistor in the junctionless nanowire field effect transistor provided by the present application.

detailed description

The present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments have used associated similar element numbers. In the following embodiments, many details are described so that the present application can be better understood. However, those skilled in the art will readily recognize that some of the features may be omitted under different circumstances, or may be replaced by other elements, materials, and methods. In some cases, some operations related to the present application are not shown or described in the specification, in order to avoid the core part of the present application being overwhelmed by excessive descriptions, and for those skilled in the art, these are described in detail. The relevant operations are not necessary, and they can fully understand the relevant operations according to the descriptions in the specification and general technical knowledge in the field.

Additionally, the features, acts, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can also be exchanged or adjusted in order in a manner obvious to those skilled in the art. Therefore, the various sequences in the specification and drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a necessary order unless otherwise stated, a certain order must be followed.

The serial numbers themselves, such as "first", "second", etc., for the components herein are only used to distinguish the described objects, and do not have any order or technical meaning. The "connection" and "connection" mentioned in this application, unless otherwise specified, include both direct and indirect connections (connections).

It can be known from the background art that the traditional junctionless nanowire field effect transistor is sensitive to process fluctuations, which leads to poor stability of the electrical performance of the device, and also limits its application in circuits.

Discovered by creative work, please refer to FIG. 1A. FIG. 1A is a schematic structural diagram of a traditional junctionless nanodevice. The structure of the traditional junctionless nanodevice includes: It is divided into a source region, a drain region and a channel region, wherein the source region and the drain region may be referred to as source and drain regions. The source-drain region and the channel region of the traditional junctionless nanodevice are made of the same material, the doping type and concentration of the source region, the drain region and the channel region are the same, and the doping concentration is all heavily doped (10 ¹⁹ order of magnitude). ), a source metal layer 2 is deposited on a part of the surface of the source region, and a drain metal layer 3 is deposited on a part of the surface of the drain region (the metal layers of the source and drain regions shown this time are respectively on the end faces of the junctionless nanowires); Outside the channel region of the junctionless nanowire 1 is a gate dielectric layer 4 and a gate metal layer 5 covering the gate dielectric layer 4 in sequence. The analysis shows that the traditional junctionless nanodevice works as follows (taking n-type semiconductor as an example): when the device is turned off, the metal with a larger work function is used to deplete the channel region, so as to realize the turn-off of the device. At this time, the corresponding gate When the electrode voltage is zero, the device works in the depletion region; when the device is turned on, by adding a positive gate voltage, the originally depleted channel accumulates to generate carriers. The larger the drive current is, the channel can be regarded as a variable gate-controlled resistor equivalently. At this time, the corresponding gate voltage is positive, and the device works in the accumulation region. Since the working principle of traditional junctionless nanodevices is closely related to the doping concentration, the doping concentration must also be heavily doped (on the order of 10 ¹⁹ ), so it is very susceptible to process fluctuations, resulting in inconsistent doping concentration, which affects the The stability of the electrical properties of the device limits the application of junctionless nanowire field effect transistors in circuits.

Subsequently, a junctionless nanowire field effect transistor with a double-gate Charge-plasma structure is proposed. Referring to FIG. 1B , FIG. 1B is a schematic structural diagram of a junctionless nanowire field effect transistor with a double-gate Charge-plasma structure. The junctionless nanowire field effect transistor with plasma structure includes junctionless nanowires 10. The junctionless nanowires are preferably axis-symmetrical, and can be divided into a source region, a drain region and a channel region. The source region and the drain region can be referred to as source and drain for short. a source metal layer 32 is covered on the outer surface of the source region, wherein a source dielectric layer 22 is provided between the outer surface of the sidewall of the source region and the source metal layer 32; The outer surface of the drain region is covered with a drain metal layer 33, wherein a drain dielectric layer 23 is arranged between the outer surface of the sidewall of the drain region and the drain metal layer 33; surrounding the sidewall of the channel region The outer surface has a gate dielectric layer 21 and a gate metal layer 31 in sequence, wherein an isolation layer 40 is provided between the gate metal layer 31 , the source metal layer 32 and the drain metal layer 33 . The device adjusts the type of transistor by controlling the work function between the source metal layer 32, the drain metal layer 33 and the gate metal layer 31, for example, by controlling the source metal layer 32, the drain metal layer 33 and the gate The work function relationship between the metal layers 31 makes the device an N-type semiconductor. At this time, the metal layers (that is, the source metal layer 32 and the drain metal layer 33 ) can induce a large number of electrons inside the source and drain regions, responsible for The metal layer that induces electrons and the bulk silicon (ie, the junctionless nanowire 10 ) are separated by a layer of dielectric (ie, the source dielectric layer 22 and the drain dielectric layer 23 ). The source and drain of the device with this structure Neither the region nor the channel region is doped, so the device not only gets rid of the influence of the doping process, but also achieves the desired function. Therefore, this kind of device solves to a certain extent the problem that the traditional junctionless device is affected by the fluctuation of the doping process. However, in the study, it was found that the driving current of the above-mentioned dual-gate Charge-plasma junctionless nanowire field effect transistor is relatively low, and at the interface where the source and drain regions are in direct contact with the metal electrode, the Fermi pinning effect will produce a relatively low driving current. The large Schottky barrier, resulting in large contact resistance, limits the electrical performance of the device.

After research, the present application proposes a junctionless nanowire field effect transistor and a manufacturing method thereof, which are improved on the basis of a junctionless nanowire field effect transistor with a double gate charge-plasma structure. Extremely heavy doping reduces the contact resistance at the interface where the source and drain regions are in direct contact with the metal electrode, overcomes the Schottky barrier problem caused by the Fermi pinning effect, and increases the on-state current and transconductance of the device. In addition, the transistor proposed in the present application also has a good inhibitory effect on the random doping fluctuation effect in the process.

In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application will be further described in detail below with reference to specific embodiments and accompanying drawings.

Example 1

FIG. 2 is a schematic structural diagram of a junctionless nanowire field effect transistor provided in this embodiment. Referring to FIG. 2 , the junctionless nanowire field effect transistor includes: A source region 101 , a channel region 103 and a drain region 102 are sequentially defined in the axial direction. The channel region 103 is not doped or lightly doped, the source region 101 and the drain region 102 have the same doping type as the channel region 103, and the doping concentration of the doped regions greater than the doping concentration of the channel region.

In this embodiment, the junctionless nanowire 100 can be understood as the body of a simplified semiconductor device, and the body can be a horizontal monocrystalline silicon pillar, and the two ends of the pillar are the source region 101 and the drain region 102 respectively , the middle is the channel region 103; the junctionless nanowire 100 can also be understood as a strip-shaped single crystal silicon rod body of a transistor on the SOI substrate, the single crystal silicon rod body can include the channel region 103, the source region 101 and drain region 102. The single crystal silicon rod is undoped or lightly doped. If it is lightly doped, the doping types of the channel region 103 , the source region 101 and the drain region 102 are the same.

For example, the doping types of the channel region 103 , the source region 101 and the drain region 102 are all P-type doping or all N-type doping. When the doping type of the channel region 103 , the source region 101 and the drain region 102 is P-type doping, the doping material can be boron or indium; when the channel region 103 , the source region 101 and the drain region 102 When the doping type is N-type doping, the doping material can be phosphorus, arsenic or antimony.

Part or all of the source region 101 and the drain region 102 are doped regions. For example, referring to FIG. 2 , part or all of the source region 101 is the doped region A. Part or all of the drain region 102 is the doped region B. As shown in FIG.

In this embodiment, along the axis of the junctionless nanowire 100, the range of the doped region A is the range after the total length of the source region 101 minus the length of the isolation region 400; the range of the doped region B is the range of the drain region The total length of region 102 minus the length of isolation region 400.

For example, when the total length of the junctionless nanowire field effect transistor in this embodiment is 50 nm, along the axis direction of the junctionless nanowire 100, if the range length of the doped region exceeds 10 nm, it may cause The reduction of the channel length in actual operation increases the leakage current of the device, which in turn leads to a decrease in the performance of the device. Therefore, controlling the widths of the doped region A and the doped region B within 10 nanometers can ensure stable electrical performance of the device.

The doping concentration of the doping region A of the source region 101 and the doping region B of the drain region 102 is greater than that of the channel region 103 .

In this embodiment, the doped regions in the source region 101 and the drain region 102 are ^{heavily doped with a doping concentration of 1×10 19} cm ⁻³ to 1×10 ²¹ cm ⁻³ , and the channel region 103 It is lightly doped less than or equal to 1×10 ¹⁹ cm ^-3 cm ^{-3 .}

The source region 101 , the channel region 103 and the drain region 102 are axially symmetric. For example, in other embodiments, in the shape of the junctionless nanowire 100 , the shape of the channel region 103 may be a cylinder or Prism, the shape of the source region 101 and the drain region 102 is a cylinder, a prism or a truncated cone, wherein, at the connection between the source region 101 and the channel region 103, the cross-sectional shape of the source region 101 and the channel The cross-sectional shape of the region 103 is the same; at the connection between the drain region 102 and the channel region 103 , the cross-sectional shape of the drain region 102 and the cross-sectional shape of the channel region 103 are the same.

Please continue to refer to FIG. 2 , an outer surface of the source region 101 is covered with a source electrode layer 301 , wherein a source dielectric layer 201 is provided between the source electrode layer 301 and a part of the surface of the source region 101 . The outer surface of the drain region 102 is covered with a drain electrode layer 302 , wherein there is a drain dielectric layer 202 between the drain electrode layer 302 and a part of the surface of the drain region 102 . According to the principle of the double-gate Charge-plasma junctionless nanowire field effect transistor, the source dielectric layer 201 and the drain dielectric layer 202 do not cover the entire outer surface of the source and drain regions, that is, at least a part of the outer surface of the source region and the source region The electrode layer 301 is in contact, and at least a part of the outer surface of the drain region is in contact with the drain electrode layer 302 . Typically, the source dielectric layer 201 is located between the source electrode layer 301 and the peripheral surface of the source region 101 , and the drain dielectric layer 202 is located between the drain electrode layer 302 and the peripheral surface of the drain region 102 .

The outer surface of the channel region 103 is covered with a gate dielectric layer 203 , and the surface of the gate dielectric layer 203 is covered with a gate electrode layer 303 .

An isolation layer 400 is provided between the source electrode 301 and the gate electrode 303 ; and an isolation layer 400 is provided between the drain electrode 302 and the gate electrode 303 .

It should be noted that when the doping type is N-type doping, the work function of the material of the source electrode layer 301 and the material of the drain electrode layer 302 is smaller than that of the junctionless nanowire material.

When the doping type is P-type doping, the work function of the material of the source electrode layer 301 and the material of the drain electrode layer 302 is greater than that of the junctionless nanowire material.

The type of device can be controlled by adjusting the work function relationship between the source-drain electrodes and the junctionless nanowire body.

In the junctionless nanowire field effect transistor provided in this embodiment, since the source and drain regions of the device are doped with the same type of ions as the channel region, and the source and drain regions are larger than the doping concentration of the channel region, the source and drain metal electrode layers are When in contact with the semiconductor bulk silicon body, the contact resistance caused by the Schottky barrier decreases, and the carrier concentration increases, thereby increasing the on-state current and transconductance of the device.

The present application also provides a method for manufacturing a junctionless nanowire field effect transistor. Please refer to FIG. 3 . FIG. 3 is a flowchart of the manufacturing method for a junctionless nanowire field effect transistor provided in this embodiment. The method includes:

In step S1, a junctionless nanowire 100 is formed, and a source region 101, a drain region 102 and a channel region 103 of the junctionless nanowire 100 are sequentially defined along the axis of the junctionless nanowire 100. The source region 101, The channel region 103 and the drain region 102 are axially symmetrical.

In this embodiment, the method for forming the junctionless nanowire 100 includes:

Referring to FIG. 4 , a silicon substrate 11 is provided, and a preliminary doping process and an annealing process are performed on the silicon substrate. The concentration of the preliminary doping determines the doping concentration of the channel region 103 of the device. When the preliminary doping is performed, the preliminary doping concentration may be light doping ^{less than or equal to 1×10 19} cm ^{−3 .} After the preliminary doping process, the resistivity of the whole device is reduced, and the electrical performance of the device is improved.

In other embodiments, the silicon substrate 11 may not be doped, so that the channel region 103 is not doped.

Referring to FIG. 5 , the silicon substrate 11 is etched to a certain thickness.

In this embodiment, the junctionless nanowire 100 may be a strip-shaped single crystal silicon rod body, and the single crystal silicon rod body may include a channel region 103 , a source region 101 and a drain region 102 .

In other embodiments, the shape of the channel region 103 may be a cylinder or a prism, and the shape of the source region 101 and the drain region 102 may be a cylinder, a prism or a truncated truncated cone. At the connection of the region 103, the cross-sectional shape of the source region 101 and the cross-sectional shape of the channel region 103 are the same; at the connection of the drain region 102 and the channel region 103, the cross-sectional shape of the drain region 102 and The cross-sectional shapes of the channel regions 103 are the same.

Step S2, the source region 101 and the drain region 102 are doped with the same doping type as the channel region 103 using a doping process, and the source region 101 and the drain region 102 are doped with the same doping concentration greater than the doping concentration of the channel region 103 .

During the doping process, it is necessary to control the implantation dose and energy so as to form appropriate doping regions in the source and drain regions.

It should be noted that the doping type is P-type doping or N-type doping.

For example, the doping types of the channel region 103, the source region 101 and the drain region 102 are P-type doping or N-type doping. When the doping type of the channel region 103 , the source region 101 and the drain region 102 is P-type doping, the doping material can be boron or indium; when the channel region 103 , the source region 101 and the drain region 102 When the doping type is N-type doping, the doping material can be phosphorus, arsenic or antimony.

In this embodiment, the source region 101 and the drain region 102 are doped by means of ion implantation, and the source region 101 and the drain region 102 have a doping concentration of 1×10 ¹⁹ cm ⁻³ to 1× 10 ²¹ cm ^-3 of heavy doping.

In other embodiments, the doping concentration of the source region 101 and the drain region 102 may be lower than 1×10 ¹⁹ cm ⁻³ .

In this embodiment, part and all regions of the source region 101 and the drain region 102 are doped.

For example, in FIG. 7 , the partial region A in the source region 101 is doped, and the partial region B in the drain region 102 is doped. It should be noted that, through the creative work of the inventor, it is found that when the widths of the doped region A and the doped region B are less than or equal to 10 nanometers, that is to say, along the axis of the junctionless nanowire 100, the When the range length of the doped region is less than or equal to 10 nanometers, the actual working channel length is reduced, the leakage current of the device is increased, and the performance of the device is degraded. Therefore, the width range of the doped region A and the doped region B is controlled within 10 nanometers to ensure stable electrical performance of the device.

It should be noted that, before doping the source region 101 and the drain region 102 using a doping process, the method further includes: forming an isolation layer 400 , where the isolation layer 400 is used for insulation isolation between electrodes.

S3, the gate dielectric layer 203, the source dielectric layer 201 and the drain dielectric layer 202 are formed.

FIG. 6 is a schematic cross-sectional view of the junctionless nanowire 100 in the direction of the tangent line CC1 in FIG. 5 . Referring to FIG. 6 , the gate dielectric layer 203 covers the outer peripheral surface of the channel region 103 , and the source The dielectric layer 201 is formed on a part of the outer surface of the source region 101 , and the drain dielectric layer 202 is formed on a part of the outer surface of the drain region 102 .

It should be noted that, in this embodiment, the thickness of the gate dielectric layer 203 is greater than the thicknesses of the source dielectric layer 201 and the drain dielectric layer 202 .

In this embodiment, the gate dielectric layer 203 may be made of silicon dioxide, and the source dielectric layer 201 and the drain dielectric layer 202 may be made of hafnium dioxide.

The gate dielectric layer 203 in this embodiment can be formed by a dry oxygen oxidation method.

It should be noted that the dielectric constants of the materials of the source dielectric layer 201 and the drain dielectric layer 202 are selected as high oxide materials as possible, and the thinner the thickness, the better.

S4, the gate electrode layer 303, the source electrode layer 301 and the drain electrode layer 302 are formed.

Referring to FIG. 7 , the gate electrode layer 303 is formed on the outer peripheral surface of the gate dielectric layer 203 , the source electrode layer 301 is formed on the surface of the source dielectric layer 201 and the outer surface of the source region 101 not covering the source dielectric layer 201 Above, the drain electrode layer 302 is formed on the surface of the drain dielectric layer 202 and the outer surface of the drain region 102 not covering the drain dielectric layer 202 .

In this embodiment, the gate electrode layer 303 , the source electrode layer 301 and the drain electrode layer 302 are formed by a deposition method.

It should be noted that, when the doping type is N-type doping, the work function of the source electrode layer 301 and the drain electrode layer 302 is smaller than the work function of the junctionless nanowire material;

When the doping type is P-type doping, the work function of the material of the source electrode layer 301 and the material of the drain electrode layer 302 is greater than that of the junctionless nanowire material.

The type of device can be controlled by adjusting the work function relationship between the source-drain electrodes and the junctionless nanowire body.

After adopting the junctionless nanowire field effect transistor with the above structure, the inventor found that the driving current of the junctionless nanowire field effect transistor was greatly improved after testing. Based on the above-mentioned junctionless nanowire field effect transistor and its manufacturing method, a comparison chart of the electrical properties of the junctionless nanowire field effect transistor of the present application and the Charge-plasma junctionless nanowire field effect transistor in the prior art is also provided. In this embodiment, the junctionless nanowire field effect transistor of the present application can be called an accumulation-type double-gate Charge-plasma nanowire field effect transistor, and the fixed parameters of the device include: the junctionless nanowire 100 is made of silicon material (which can be called as is a silicon body), wherein the doping types of the source region 101 , the drain region 102 and the channel region 103 are all N-type, and the doping concentration of the channel region 103 is 1×10 ¹⁶ cm ⁻³ . The device width is 10 nm in diameter, and the source dielectric layer 201 and the drain dielectric layer 202 are hafnium dioxide with a thickness of 0.4 nm. The work function of the gate electrode layer 303 is 4.72 eV, and the work function of the source electrode layer 301 and the drain electrode layer 302 is 3.9 eV.

FIG. 8 is a comparison diagram of driving current between the junctionless nanowire field effect transistor provided by the present application and the conventional Charge-plasma junctionless nanowire field effect transistor.

Wherein, the width of the doping region of the accumulation-type dual-gate Charge-plasma nanowire field effect transistor of the present application is 3 nanometers, and the doping concentration of the source and drain regions is 1×10 ¹⁹ cm ⁻³ . The abscissa represents the gate voltage, the ordinate is divided into two parts, the left ordinate is the log graph of the change of the driving current with the gate voltage (the data is processed by the log function), and the right ordinate is the change of the driving current with the gate voltage. Linear graph (untreated), two coordinates can better observe the change of current.

It can be seen from FIG. 8 that, compared with the traditional double-gate Charge-plasma nanowire field effect transistor, the junctionless nanowire field effect transistor of the present application can increase the driving current to more than 40 times, while the leakage current and subthreshold slope are almost remain unchanged, so the junctionless nanowire field effect transistor provided by the present application has a higher current switching ratio and transconductance without sacrificing the switching speed of the device.

FIG. 9 is a comparison diagram of the carrier concentration distribution in the channel of the accumulation-type double-gate Charge-plasma nanowire field effect transistor provided by the present application and the conventional Charge-plasma junctionless nanowire field effect transistor. The abscissa represents the coordinate along the channel direction, and the ordinate represents the carrier concentration inside the semiconductor.

It can be seen from FIG. 9 that when the device is in the on state, the electron concentration of the accumulation-type double-gate Charge-plasma nanowire field effect transistor provided by the present application is higher than that of the conventional double-gate Charge-plasma nanowire field effect transistor, which is Because compared with the traditional double-gate charge-plasma structure, in the structure of the junctionless nanowire field effect transistor provided by the application, due to the heavy doping of the source region and the drain region, the contact between the metal and the semiconductor is formed when the contact is made. The thicker Schottky barrier becomes thinner, so that electrons are transported into the semiconductor by means of tunneling, which also enables the channel of the junctionless nanowire field effect transistor provided by the present application to have a higher driving current.

FIG. 10 is a comparison diagram of the electrical characteristics of a conventional dual-gate Charge-plasma nanowire field effect transistor and an accumulation-type dual-gate Charge-plasma nanowire field effect transistor when the channel doping concentration is changed. The abscissa is the change of the channel doping concentration, the left ordinate represents the change of the on-state current (driving current) with the channel doping concentration, and the right ordinate is the leakage current (V _g = 0V) with the channel doping concentration The change.

As shown in Figure 10, the on-state current of the conventional dual-gate Charge-plasma nanowire field effect transistor is seriously affected by the channel doping fluctuation, while the on-state current of the accumulating dual-gate Charge-plasma structure hardly varies with the channel doping. It is less sensitive to the change of the overall doping concentration of the channel, so the accumulating dual-gate Charge-plasma structure has a good inhibitory effect on random doping fluctuations in the process.

FIG. 11 is a statistical diagram of the effect of changing the doping width of the source and drain regions on the driving current of the transistor in the junctionless nanowire field effect transistor provided by the present application. The abscissa is the variation of the width of the heavily doped regions at both ends of the source and drain, the left ordinate is the variation of the on-state current with the width of the heavily doped source and drain regions corresponding to different source-drain heavily doped concentrations, and the right ordinate is the corresponding The variation of the current switching ratio with the width of the source-drain heavily doped region at different source-drain heavily doped concentrations.

It can be seen from Figure 11 that when the width of the heavily doped source-drain region covers both the source-drain region and the isolation region, the leakage current will increase due to the reduction of the channel length during actual operation, resulting in a decrease in device performance. When the source-drain doped region is kept smaller than the width of the source-drain region, the junctionless nanowire field effect transistor provided by the present application can maintain a high-performance and stable working state, and is easier to implement in process. Therefore, in practical applications, the width of the heavily doped source and drain regions should be kept less than or equal to the length of the source and drain regions.

It can be seen from the above that the junctionless nanowire field effect transistor proposed by the present invention can improve the driving current, transconductance and current switching ratio of the transistor, and at the same time can better suppress the influence of random doping fluctuations and maintain a good sub-threshold swing. The characteristics such as amplitude and leakage current can improve the performance deterioration of the device in the process of size reduction, so that the device has more application value.

Descriptions are made herein with reference to various exemplary embodiments. However, those skilled in the art will recognize that changes and modifications may be made to the exemplary embodiments without departing from the scope of this document. For example, various operational steps, and components for performing operational steps, may be implemented in different ways depending on the particular application or considering any number of cost functions associated with the operation of the system (eg, one or more steps may be deleted, modified or incorporated into other steps).

Although the principles herein have been shown in various embodiments, many modifications may be made in structure, arrangement, proportions, elements, materials and components as are particularly suited to particular environmental and operating requirements without departing from the principles and scope of the present disclosure use. The above modifications and other changes or corrections are intended to be included within the scope of this document.

The foregoing Detailed Description has been described with reference to various embodiments. However, those skilled in the art will recognize that various modifications and changes can be made without departing from the scope of the present disclosure. Accordingly, this disclosure is to be considered in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within its scope. Likewise, the advantages, other advantages, and solutions to problems of the various embodiments have been described above. However, the benefits, advantages, solutions to the problems, and any elements that give rise to these, or make them more explicit, should not be construed as critical, necessary, or essential. As used herein, the term "comprising" and any other variations thereof are non-exclusive inclusion, such that a process, method, article or device that includes a list of elements includes not only those elements, but also not expressly listed or part of the process , method, system, article or other elements of the device. Furthermore, as used herein, the term "coupled" and any other variations thereof refer to physical connections, electrical connections, magnetic connections, optical connections, communication connections, functional connections, and/or any other connection.

Those skilled in the art will recognize that many changes may be made to the details of the above-described embodiments without departing from the underlying principles of the invention. Accordingly, the scope of the invention should be determined in accordance with the following claims.

Claims (15)

1. A junctionless nanowire field effect transistor, comprising: a junctionless nanowire, wherein the junctionless nanowire includes a source region, a channel region and a drain region defined in sequence along its axis direction;

   An outer surface of the source region is covered with a source electrode layer, wherein an active dielectric layer is between the source electrode layer and a part of the surface of the source region;

   The outer surface of the drain region is covered with a drain electrode layer, wherein a leakage dielectric layer is arranged between the drain electrode layer and a partial surface of the drain region;

   The outer peripheral surface surrounding the channel region is covered with a gate dielectric layer, and the outer peripheral surface surrounding the gate dielectric layer is covered with a gate electrode layer;

   The channel region is not doped or lightly doped, the source region and the drain region have doped regions of the same doping type as the channel region, and the doping concentration of the doped region is greater than that of the channel region Doping concentration in the channel region.
2. The junctionless nanowire field effect transistor according to claim 1, wherein the source region, the channel region and the drain region are axially symmetric; an isolation layer is provided between the source electrode and the gate electrode; An isolation layer is provided between the drain electrode and the gate electrode.
3. The junctionless nanowire field effect transistor according to claim 1, wherein the source region, the drain region and the channel region have the same doping material, and the doped regions in the source region and the drain region are doped The concentration is 1×10 ¹⁹ cm ⁻³ to 1×10 ²¹ cm ⁻³ of heavy doping, and the channel region is lightly doped with ^{less than or equal to 1×10 19} cm ^{−3 .}
4. The junctionless nanowire field effect transistor according to claim 1, wherein part or all of the source region and the drain region are doped regions.
5. The junctionless nanowire field effect transistor according to claim 1, wherein the shape of the channel region is a cylinder or a prism, and the shape of the source region and the drain region is a cylinder, a prism or a truncated cone, wherein, in the At the connection between the source region and the channel region, the cross-sectional shape of the source region is the same as the cross-sectional shape of the channel region; at the connection between the drain region and the channel region, the cross-sectional shape of the drain region It is the same as the cross-sectional shape of the channel region.
6. The junctionless nanowire field effect transistor according to claim 1 or 5, wherein the source dielectric layer is located between the source electrode layer and the peripheral surface of the source region;

   The drain dielectric layer is located between the drain electrode layer and the outer peripheral surface of the drain region.
7. The junctionless nanowire field effect transistor according to claim 1, wherein the doping type is P-type doping or N-type doping;

   When the doping type is N-type doping, the work function of the source electrode layer and the drain electrode layer is smaller than the work function of the junctionless nanowire;

   When the doping type is P-type doping, the work function of the source electrode layer and the drain electrode layer is greater than the work function of the junctionless nanowire.
8. A method for manufacturing a junctionless nanowire field effect transistor, characterized in that the method comprises:

   forming a junctionless nanowire, and defining an active region, a channel region and a drain region in sequence along the axis direction of the junctionless nanowire;

   Lightly doped or undoped channel region;

   Doping the source region and the drain region with the same doping type as the channel region using a doping process, and the doping concentration is greater than the doping concentration of the channel region;

   forming a dielectric layer including a gate dielectric layer, a source dielectric layer, and a drain dielectric layer, wherein the gate dielectric layer covers a peripheral surface surrounding the channel region, the source dielectric layer is formed in the source region part of the outer surface of the drain region, the drain dielectric layer is formed on a part of the outer surface of the drain region;

   forming a gate electrode layer, a source electrode layer and a drain electrode layer, the gate electrode layer being formed on the peripheral surface surrounding the gate dielectric layer, the source electrode layer being formed on the surface of the source dielectric layer and the source not covering the source dielectric layer On the outer surface of the region, the drain electrode layer is formed on the surface of the drain dielectric layer and the outer surface of the drain region not covered with the drain dielectric layer.
9. The manufacturing method according to claim 8, wherein before forming the junctionless nanowires, further comprising:

   A silicon substrate is provided, and a preliminary doping process and an annealing process are performed on the silicon substrate, and the preliminary doping concentration is light doping ^{less than or equal to 1×10 19} cm ^{-3 ;}

   Etching the silicon substrate of a certain thickness to form junctionless nanowires, the shape of the channel region of the junctionless nanowires is a cylinder or a prism, and the shape of the source region and the drain region is a cylinder, a prism or a truncated cone, Wherein, at the connection between the source region and the channel region, the cross-sectional shape of the source region is the same as the cross-sectional shape of the channel region; at the connection between the drain region and the channel region, the drain region The cross-sectional shape is the same as the cross-sectional shape of the channel region.
10. The manufacturing method according to claim 8, wherein before the doping the source region and the drain region using a doping process, the method further comprises:

    Isolation layers are formed on both sides of the gate dielectric layer.
11. 9. The manufacturing method of claim 8, wherein the gate dielectric layer is formed by a dry oxygen oxidation method.
12. The manufacturing method according to claim 8, wherein the doping of the source region and the drain region with the same doping type as that of the channel region using a doping process comprises: a method of ion implantation The source region and the drain region are doped, and the source region and the drain region are heavily doped with ^{a doping concentration of 1×10 19} cm ⁻³ to 1×10 ²¹ cm ^{−3 .}
13. The manufacturing method according to claim 8, wherein the doping the source region and the drain region using a doping process comprises: doping part and all regions of the source region and the drain region. doping.
14. The manufacturing method of claim 8, wherein the source dielectric layer and the drain dielectric layer are made of hafnium dioxide.
15. The manufacturing method according to claim 8, wherein the doping type is P-type doping or N-type doping;

    When the doping type is N-type doping, the work function of the source electrode layer and the drain electrode layer is smaller than the work function of the junctionless nanowire;

    When the doping type is P-type doping, the work function of the source electrode layer and the drain electrode layer is greater than the work function of the junctionless nanowire.

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