WO2022001885A1 - 复重构密钥的序列加密方法 - Google Patents

复重构密钥的序列加密方法 Download PDF

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WO2022001885A1
WO2022001885A1 PCT/CN2021/102451 CN2021102451W WO2022001885A1 WO 2022001885 A1 WO2022001885 A1 WO 2022001885A1 CN 2021102451 W CN2021102451 W CN 2021102451W WO 2022001885 A1 WO2022001885 A1 WO 2022001885A1
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bit
pseudo
segment
length
logic
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PCT/CN2021/102451
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English (en)
French (fr)
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徐智能
徐叶帆
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徐智能
徐叶帆
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Priority to CA3184576A priority Critical patent/CA3184576A1/en
Priority to AU2021298570A priority patent/AU2021298570B2/en
Priority to EP21830909.4A priority patent/EP4160979A4/en
Priority to JP2022581664A priority patent/JP2023532945A/ja
Priority to US17/505,509 priority patent/US20220038256A1/en
Publication of WO2022001885A1 publication Critical patent/WO2022001885A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H04L9/0625—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
    • H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords

Definitions

  • the invention relates to the field of information security cryptography, and relates to a sequence encryption method for complex and reconstructed keys.
  • Cipheral Patent Application No.: 201710249427.9 discloses a sequence encryption method based on a random binary sequence with an adjustable concomitant random reconstruction key.
  • the main features of the method are: (1) Dynamically construct a seed using an existing random sequence random sequence. (2) Use the seed random sequence to pseudo-randomly construct a random key with a fixed-length or variable-length bit segment. (3) The pseudo-random construction process of the random key accompanies the encryption process. (4) Using the transitivity of the XOR operation to realize the frequency conversion nonlinear XOR of the plaintext of the key pair. (5) The adjustment of the key structure is realized by the adjustment of the feature quantity and other manipulation quantities and the pseudo-random construction function, and then the encryption density is adjusted without increasing the time complexity.
  • the invention discloses a method for implementing a chaotic computing structure by using a key and a structural configuration quantity to configure a structural manipulation quantity, and then implementing the chaotic bit-segment stream sequence encryption with its scheduling matching compound logic.
  • the purpose of the present invention is achieved through the following concept: constructing a chaotic computing structure based on composite logic, and encrypting plaintext by round-by-round (or segment-by-segment) bits of indefinite length determined by pseudo-random.
  • the key bit segment construction source (or construction source) and the key bit segment manipulation source (or manipulation source) are pseudo-randomly reconstructed segment by segment according to the configuration of the computing structure, and the control source is pseudo-randomly manipulated using the control source.
  • the key bit segment of the regenerated key is reconstructed bit by bit round by round. Further, the regenerated key bit segment sequence generated segment by segment is integrated to implement an infinite non-circulating bit segment stream sequence encryption.
  • the key to achieving the goal of the concept is: scheduling bit fetching logic, bit metabolism logic, bit reconstruction logic (including pseudo-random bit bit rearrangement logic and pseudo-random bit bit conversion logic, see the description of several points) complex reconstruction 'pseudo-random Extract the unmetabolized structural source bit by dislocation or extract the regenerated key bit segment sequence of the metabolized structural source bit' by repositioning, and then: (1) Use the chaotic computing structure to resolve the regeneration key bit generated from the finite set The periodic rate of the segment sequence, (2) the staggered superposition of more than one regenerated key bit segment sequence to realize the intertwining between the regenerated key bit segment sequences and the embedded pseudo-random bit bit entanglement.
  • Technical solutions include:
  • the chaotic computing structure is constructed by the key through the structure configuration, which supports the bit-by-bit segment sequence encryption that pseudo-randomly determines the computing parameters of each segment.
  • the initial value of the dynamic driving vector, the maximum/minimum value of the length of the bit segment, and the selection pool (or the selection pool) of the key bit segment are determined pseudo-randomly according to the structure configuration quantity and the key secretly agreed by the encryption/decryption parties.
  • the pseudo-random update round by round selects the construction and manipulation sources in the pool, the length of the encrypted bit segment, etc., to construct the chaotic regeneration key Bit segment sequence, and further amplify the chaotic effect through the power-level superposition of the logical structure of the wrong segment, and integrate the infinite non-cyclic bit-segment stream encryption based on the bit-segment sequence of the regeneration key (bit-segment stream encryption).
  • the beneficial effects of the present invention are: in order to adapt to the breakthrough improvement of computing power, a secure encryption method with high efficiency, high density and broad application space is provided.
  • the present invention uses a concept called chaotic computing structure in this specification: using pseudo-randomly varied computing parameters in the encryption process to cause chaos in the encrypted computing trajectory, forcing the attacker to face the chaotic computing form.
  • the uncertainty of the chaotic computing structure driven by the key provides a broad space for logical integration for bit-segment stream sequence encryption.
  • the pseudo-random change of the chaotic trajectory of encryption/decryption based on logical integration is controllable by both encryption and decryption, but the attacker faces the chaotic trajectory shape.
  • the chaotic computing form generated by this chaotic computing structure of the present invention includes the following aspects: pseudo-random variation of structural manipulation quantities generated by using different keys, pseudo-random variation of computational parameters regenerated segment by segment from the structural manipulation quantities in the encryption process, and Encryption logic unit integration form (input/output of bit fetching logic, bit metabolizing logic and bit reconstruction logic and their matching effects) in the encryption process driven by calculation parameters, and the construction form (length and structure rule) of the regenerated key bit segment ), the pseudo-random change of the integrated form of the regenerated key bit segment (staggered segment stacking and embedded pseudo-random bit bit winding).
  • the invention uses the selection pool as the carrier of the construction source and the manipulation source, and the content of the selection pool is replaced segment by segment with the encryption process.
  • this specification calls it the key bit segment work pool (or work pool).
  • the working pool expands segment by segment with the reconstruction of the regenerated key bit segment until the selection pool is filled.
  • This specification calls this phase the growth phase of the working pool. After the growth period, the working pool reaches the mature period, and the working pool is still replaced with the reconstruction of the regenerated key bit segment during the mature period.
  • the growth in the growth phase of the working pool and the replacement in the mature stage are collectively referred to as the metabolism (or metabolism) of the working pool (or the selection pool).
  • the present invention adds a pseudo-plaintext random string (or called pseudo-plaintext) unrelated to the content of the plaintext before the plaintext.
  • Pseudo-plaintext has the following characteristics: (1) Since the random string is not identifiable, it is impossible to distinguish whether the attack on the pseudo-plaintext is successful or not. During the growth stage of the working pool, the pseudo-plaintext is embedded into the working pool piece by piece, and after the working pool reaches the mature stage, the pseudo-plaintext has the equivalent effect of the key. (2) The pseudo-plaintext is not a key, but a random string independently constructed by the encryption party to expand the working pool during the growth period, and is regarded as a fee code after decryption.
  • Pseudo-plaintext has the function of further chaotic computing process in the encryption process. Different pseudo-plaintexts lead to differences in the construction source and manipulation source when encrypting the formal plaintext, which in turn leads to differences in the bit sequence of the regeneration key.
  • 'dislocation extraction' refers to the bits with different extraction positions in different times
  • 'relocation extraction' is Refers to the bit with the same position extracted from different times.
  • Bit fetching logic and bit metabolizing logic are important logical units to realize 'pseudo-random dislocation to extract unmetabolized structural source bits or repositioning to extract metabolized structural source bits'. Their integrated effect is integral to the infinite non-circulating system of the present invention.
  • the composite logic structure of the present invention needs to contain more than one kind of bit fetching logic and bit metabolism logic. Different bit-taking logics and bit-metabolizing logics can be integrated into calculation models of different combinations, and the mis-segment stacking logic structure formed by using different bit-taking logics and bit-metabolizing logics in conjunction can improve the security of the present invention exponentially.
  • the bit fetching logic presented in this specification includes the key bit segment progressive bit fetching logic (or called progressive bit fetching logic), the key bit segment progressive chain bit fetching logic (or called progressive chain bit fetching logic), The key bit segment bit-jump bit-taking logic (or bit-jump bit-taking logic), and the key bit-segment sequential extraction bit-extracting logic (or called the sequential bit-extracting logic), the bit metabolism logic shown in this specification includes the key bit The segment selection pool has a deferred metabolization logic (or referred to as deferred metabolization logic) and the key bit segment selection pool is extracted bit metabolite logic (or referred to as extracted bit metabolite logic).
  • the composite logic structure of the present invention can also accommodate other bit fetching logic and bit metabolism logic.
  • the present invention allows pseudo-random bit rearrangement to generate regeneration key bits after the bits string is extracted. segment, which is called pseudo-random bit rearrangement in this specification
  • the present invention also needs to perform (1) pseudo-random bit resetting on the original metabolizing source pseudo-random string (that is, the output pseudo-random string output by the bit-taking logic before generating the regeneration key bit segment, the same below) before the metabolism of the working pool. row, at the same time (2) invert the bit value bit by bit (0 to 1 or 1 to 0, or interchangeable), (3) add sugar.
  • This specification will rearrange the pseudo-random bits of the original metabolic source pseudo-random string, Swap and sugar are collectively called pseudo-random bit conversion (See the relationship between bit fetching logic and bit metabolism logic for details).
  • the present invention uses a dynamic drive vector throughout the entire computational process.
  • the dynamic driving vector alternates round by round (or metabolism).
  • the initial value of the dynamic driving vector used in this specification is pseudo-randomly generated by the key, and it is still feasible to change this initial value to the initial value secretly agreed upon by the encryption/decryption parties instead of the key generated. This does not involve the structure of the encryption operation, and is not further explained in this specification.
  • this specification divides the description of the sequence encryption method for complex and reconstructed keys into three logic components for description: (1) a single complex and reconstructed logical structure, (2) ) Integration of bit fetching logic and bit metabolism logic, (3) staggered and superimposed logic structure.
  • the core of the present invention (A) Constructing a chaotic computing structure, metabolizing the working pool segment by segment in the encryption process, and then extracting the control source and construction source carried by the working pool segment by segment to control the bit in the control source. The bits in the source are constructed, and the key bit segment is regenerated by pseudo-random complex reconstruction. (B) Based on the chaotic computing structure, integrate the bit fetching logic and the bit metabolism logic to construct a regeneration key bit of 'pseudo-random dislocation to extract unmetabolized structural source bits or repositioning to extract metabolized structural source bits' The segment is infinite without looping the build logic. (C) Based on the chaotic calculation structure, the staggered-segment stacking encryption is realized for more than one different regeneration key bit sequence.
  • the chaotic computing structure extends the effect of 'pseudo-random dislocation to extract unmetabolized tectonic source bits or relocation to extract metabolized tectonic source bits'.
  • the expansion effect of chaotic computing structure can be clearly seen only on the basis of the basic operating principle of bit extraction that has been metabolized to construct the source bit. Therefore, this specification inserts a description of the expansion effect of the chaotic computing structure after explaining the integration of the bit fetching logic and the bit metabolism logic.
  • this specification selects a non-superimposed & single metabolic model configured by progressive bit logic/delayed metabolite logic as Example 1, progressive chain bit logic/delayed metabolite logic and bit hopping logic
  • the double-superposition & double-metabolism-staggered superposition model of the bit logic/extracted bit metabolism logic configuration is taken as Example 2.
  • Other combination models are not excluded.
  • Some logic units (or logic steps) in the present invention can be omitted or not omitted, and the omission or non-omission is selected according to different logic combinations (for example, pseudo-random bit rearrangement) It can be selected according to different situations), and the illustrations in this specification will not be omitted except for specific situations. Because this logical unit is still part of the logical structure, showing it is helpful to see the logical association.
  • pos_chain(j,k) 0,1,2, ... L max -L min
  • (2) is used for the set composed of each position chain
  • (3) is used for the position element set.
  • pos_chain(j) specifically refers to a certain position chain demarcated by j
  • pos_chain(j, k) refers specifically to a certain position element demarcated by j and k.
  • L max -L min chain number of positions but rather refers to the position of chain concentration ls i -L min locations chain pos_chain(ls i -L min ) is the position chain pos_chain(ls i -L min ) of the r-th metabolized in 2s-1 times of repeated metabolization (see notes to 4.5.3.2 and 4.5.4.4 in the staggered stacking logic structure ).
  • each embodiment adopts a new catalogue label according to the subject, wherein, except for the catalogue label indicating the theme prefix (such as: 'the encryption/decryption calculation formula and calculation unit 7 of the embodiment 1'), the descriptions of other embodiments in the text.
  • the directory labels of all refer to the directory labels of the current theme (eg, 'repeat steps 11 to 19...' in decryption 20 in the encryption/decryption process control of embodiment 2 refers to decryption 11 to 19 of embodiment 2).
  • FIG. 1 is a schematic diagram of the principle of a single complex reconstruction logic structure.
  • Fig. 2 is a schematic diagram of the supporting working principle of the progressive bit-lifting logic and the deferred bit-lifting metabolism logic.
  • FIG. 3 is a schematic diagram of the matching working principle of the progressive chain bit-taking logic and the extracted bit-metabolizing logic.
  • FIG. 4 is a schematic diagram of the matching working principle of the bit-hopping bit-fetching logic and the extracted bit-metabolizing logic.
  • FIG. 5 is a schematic diagram of the metabolic effect of delayed elevation.
  • Figure 6 is a schematic diagram of the metabolic effect of the extracted site.
  • FIG. 7 is a schematic diagram showing the principle of a simple staggered and superimposed logic structure.
  • FIG. 8 is a schematic diagram of the logical structure of the staggered-segment stacking with embedded pseudo-random bit entanglement.
  • Fig. 8' is a schematic diagram of the calculation process of the staggered-segment stacking logic embedded in pseudo-random bit wrapping.
  • FIG. 9 is a schematic diagram of a logical structure of a staggered segment stacking with embedded pseudo-random bit entanglement in a different embedding position from that in FIG. 8 .
  • the composite logic structure in the present invention is the basis for realizing the reconstructed regenerated key bit segment sequence and its integration.
  • this specification divides the composite logic structure into three logical components (single complex reconstruction logic structure, integration of bit fetching logic and bit metabolism logic, and staggered and superimposed logic structure) for description. . Since the efficiency of the chaotic computing structure to eliminate the periodic rate of the regenerated key bit sequence is based on the integration of the bit fetching logic and the bit metabolism logic, the chaotic computing structure is inserted after the integration of the bit fetching logic and the bit metabolism logic is explained. The expansion of the effect of random dislocation extraction of unmetabolized structural source bits or re-extraction of metabolized structural source bits.
  • the staggered superposition logic structure is the compound effect of the chaotic computing structure of the present invention, and achieves the goal of the present invention.
  • a single complex reconstruction logic structure realizes the process of reconstructing and regenerating the key bit segment sequence by pseudo-random scheduling of the key: in the preprocessing at the beginning of encryption/decryption, the present invention uses the combination of the structure configuration amount secretly agreed by the encryption/decryption parties
  • the key configures the structure control amount, supports the pseudo-random reconstruction of the calculation parameters segment by segment from the structure control amount in the encryption/decryption process, and implements the control of each logic unit.
  • the chaotic computing structure realized based on this manipulation cooperates with the bit fetching logic and the bit metabolism logic to jointly support the pseudo-random dislocation to extract the unmetabolized key bit segment to construct the source bit or re-extract the existing bit.
  • the metabolized key bit segment constructs the source bit' operation.
  • Figure 1 shows the encryption process. Since the decryption process only has non-structural differences from the encryption process in (1) preprocessing and post-processing, and (2) there are non-structural differences in the metabolic sources during the growth phase of the working pool, the decryption process will not be described in detail, but only in the Explain when necessary.
  • Figure 1 Represents a computing unit identified by Pnnn, rvnnn represents the output of a Pnnn, It specifically indicates bit fetch logic or bit metabolism logic, s001 indicates encrypted object, Indicates the structural manipulation amount (such as rV002) and manipulation source (such as key) of the referred computing unit, represents the connection relationship between computing units, Specifically, a pseudo-random bit rearrangement, Specifically refers to a pseudo-random bit conversion, Refers to pseudo-random bit conversion from the original metabolic source pseudo-random string
  • 1.3 Pseudo-randomly configure the structure control amount by encrypting/decrypting the structure configuration amount and key secretly agreed by both parties.
  • the maximum length of bit segment (or L max ) marked as rV001 and the minimum length of bit segment (Min length of bit segment, or L min ) P002 marked as rV002
  • the length of the selection pool (Source pool, or Spool) and the initial length of the work pool (Source work pool, or Spool work ) P003 marked as the initial value of the dynamic drive vector (vector 0 ) P004 of rV003, marked as The End-Of-Plaintext (or EOP) P005 of rV004, and the initial position chain set pos_chain, etc.
  • a pseudo-plaintext P006 (pseudo plaintext, or pM) marked as rV005 is generated proportionally.
  • the bit logic m001 determines the initial position of the construction source and the manipulation source in the working pool, determines the initial metabolism target area in the selection pool according to the selected bit metabolism logic m002, and reconstructs other calculation parameters.
  • a pseudo-plaintext bit segment pM i with a length equal to ls i is sequentially appended to the tail of the working pool or inserted into the working pool bit by bit pseudo-randomly until the working pool reaches the maturity stage.
  • the decrypted pseudo-plaintext bit segment pM i with length equal to ls i is appended to the tail of the working pool or inserted into the working pool bit by bit pseudo-randomly until the working pool reaches the maturity stage.
  • 1.5.5.2.1 Perform pseudo-random bit conversion on the original metabolic source pseudo-random string (the output of m001 in Figure 1) with an equal-length position chain pos_chain (ls i -L min ) (The pseudo-random rearrangement must be different from 1.5.3. For example: metabolize the position chain pos_chain(ls i -L min ) before the pseudo-random bit rearrangement) to generate a pseudo-random string of metabolites.
  • 1.5.5.2.2 Use the pseudo-random string of the metabolic source obtained in 1.5.5.2.1 and the bit metabolism logic m002 to metabolize the work pool Spool work .
  • bit fetching logic and bit metabolism logic includes the correlation control between bit fetching logic and bit metabolism logic, and the bit reconstruction logic supporting this correlation control (including pseudo-random bit rearrangement logic and pseudo-random bit conversion). logic), the metabolism and initialization of the position chain pos_chain, the metabolism of the dynamic driving vector vector i .
  • Figure 2 In order to express the correlation between the bit fetching logic and the bit metabolism logic, Figure 2, Figure 3, and Figure 4 all show the two alternately.
  • the bit fetching logic and bit metabolism logic are regulated by the chaotic computing structure.
  • the chaotic computing structure, bit fetching logic and bit metabolism logic jointly support the infinite non-cyclic operation of "pseudo-random dislocation to extract unmetabolized structural source bits or repositioning to extract metabolized structural source bits".
  • FIG. 2 shows the progressive bit logic of the i-th regenerated key bit segment (the first row) and the i+1-th regenerated key bit segment (the third row).
  • the starting byte C of the construction source of the i+1-th regenerated key bit segment is extended by one byte from the starting byte C of the construction source of the i-th regenerated key bit segment (extended to the end of the working pool and then continued from the beginning) .
  • the difference between the progressive chain bit logic and the progressive bit logic is that the order of the sequentially arranged byte segments in the construction source is changed to the order arranged according to the position elements in the position chain.
  • FIG. 2 shows the progressive chain bit logic of the i-th regenerated key bit segment (the first row) and the i+1-th regenerated key bit segment (the third row).
  • the chain fetch logic interleaves the extracted bits of the metabolite logic for round i (second row) and round i+1 (fourth row) of implementation.
  • the starting byte C of the construction source of the i+1-th regenerated key bit segment is extended by one byte from the starting byte C of the construction source of the i-th regenerated key bit segment (extended to the end of the working pool and then continued from the beginning) .
  • FIG. 4 shows the bit-hopping logic diagram of the i-th regenerated key bit segment (the first row) and the i+1-th regenerated key bit segment (the second row).
  • the bit-fetch logic interleaves the i-th round (first row) and the i+1-th round (second row) of the extracted bit metabolism logic of the implementation.
  • the construction source pickarea i consists of the bit string from the construction source start bit pickstart i,0 to the tail of the selection pool and the bit string from the selection pool head to the construction source start bit pickstart i, The bits strings before 0 are spliced together.
  • the construction source start bit pickstart i,0 of each round is determined pseudo-randomly by the dynamic driving vector vector i (for example, the value expressed by the dynamic driving vector vector i is modulo the length of the work pool (Spool work )).
  • the feature of the deferred bit extraction logic is that there are no unextracted bits in the rotation period of the construction source (that is, the repetition period when the construction source progresses by byte round by round in the working pool). Therefore, the key bit segment is regenerated. Sequences have higher usage of the worker pool.
  • the construction source pickarea i in each round consists of ls i bytes that extend from the construction source start byte pickstart i (the extension reaches the end of the working pool and continues from the beginning).
  • Bit metabolism logic is one of the keys to realize the present invention. This manual introduces two kinds of bit metabolism logic: deferred bit metabolism logic and extracted bit metabolism logic. Around the composite logic structure of the present invention, there are several other metabolic logics related to the bit metabolism logic that need to be explained: the working pool bit metabolism in the growth phase, the dynamic driving vector vector i metabolism, and the position chain pos_chain metabolism.
  • the feature of the metabolization logic of deferred promotion is that there is no unmetabolized bit in the rotation period of the metabolic target area (that is, the repetition period when the metabolic target area progresses by bytes in the working pool round by round). higher coverage.
  • the byte overlapping with the starting position E of the manipulation source (other bytes are not excluded) is selected as the starting byte metabolstart i of the metabolization target area of the deferred metabolization.
  • the metabolism of the dynamic driving vector vector i is one of the keys to ensure the randomness of the key bit segment of the complex reconstruction.
  • bit fetching logic The correlation between bit fetching logic and bit metabolism logic
  • bit fetching logic and bit metabolizing logic are to realize the infinite non-recycling regeneration key bit sequence of 'pseudo-random dislocation to extract unmetabolized structural source bits or double-bit extraction of metabolized structural source bits'. one of the keys.
  • Different matching of the two can construct different regenerated key bit segment sequences, and achieve different coverage ratios of the regenerated key bit segment sequences to the set of natural numbers. Its effect is particularly obvious in the wrong-segment stacking encryption of multiple regenerated key bit-segment sequences.
  • Figures 2, 3, and 4 each show one set, which basically summarizes the features of various sets.
  • Figure 2 shows the matching working form of the progressive bit logic and the deferred bit metabolism logic.
  • Figure 3 shows the matching working form of the progressive chain bit logic and the extracted bit metabolism logic.
  • Figure 4 shows the working state of the bit-hopping logic matching with the extracted bit metabolism logic.
  • bit fetching logic directly acts on the current round of encryption, and the bit metabolism logic affects subsequent rounds of encryption.
  • the randomness of the regeneration key bit segment of the subsequent round is higher when the starting position of the metabolic target area is selected as the starting position of the manipulation source.
  • the deferred metabolization logic of deferred promotion matches the logic of non-deferred promotion, although there will be bits that are not metabolized in the work pool of the current round, but because the construction source does not exist in the rotation cycle of the work pool For bits that have not been metabolized, the deferred metabolization logic has a higher overall metabolic rate for the working pool during the round-by-round deferred encryption process, which makes the working pool have a higher coverage rate for the set of natural numbers.
  • Figure 6 shows the difference between the non-progressive chain taking logic/extracted bit metabolism logic matching and the progressive chain taking logic/extracted bit metabolism logic matching.
  • the extraction bits in the former correspond to the order of metabolites. In the latter, since the extraction bits are arranged in the order specified by the position chain, the extraction bits are pseudo-randomly displaced from the metabolites.
  • the logic of deferred bit extraction and bit extraction may form a security loophole, so it is not suitable for use in a single complex and reconstructed encryption model.
  • the logic of deferred bit extraction and bit extraction may form a security loophole, so it is not suitable for use in a single complex and reconstructed encryption model.
  • due to its higher utilization rate of the working pool it is better to mix the delayed bit extraction logic and the non-sequential extraction bit extraction logic in the staggered overlay encryption of multiple regenerated key bit segment sequences.
  • bit metabolism logic matched with the deferred extraction bit logic must be the deferred extraction metabolism logic.
  • the purpose of the pseudo-random bit rearrangement is to update the '0'/'1' arrangement based on the original '0'/'1' ratio in the working pool.
  • bit-by-bit while pseudo-random bit rearrangement The purpose of the swap is to eliminate the proportional imbalance of the '0' and '1' bit values that may appear in the working pool, and to block the diffusion of this imbalance during the construction of the regenerated key bit segment sequence.
  • Sugaring refers to: using the pseudo-random variation characteristics of the calculation parameters in the chaotic computing structure, according to the state of the intermittent appearance of the calculation parameters (for example: (a), when the position element of a specific position in the position chain is equal to 0 or ls i ; or (b) ), when the value of a certain byte of the dynamic driving vector vector i is equal to 0 or ls i ; (c), the above (a) or (b) are not contradictory combination is established.
  • the exchange has a probability to cause the absolute uniformity of the distribution of '0' and '1' in the working pool, which will weaken the randomness of the regenerated key bit segment sequence, and the addition of sugar will destroy the absolute uniformity of this distribution. Due to the randomness of the distribution of metabolic targets and the intermittent nature of triggering conditions, the sugar treatment can still ensure the randomness of the distribution of '0' and '1' in the working pool.
  • the pseudo-random bit rearrangement in must be the same as the pseudo-random bit-bit rearrangement Different from each other, which ensures the independence between the pseudo-random change trajectory of the regenerated key bit sequence and the pseudo-random change trajectory of the working pool replacement.
  • the realization of 'pseudo-random dislocation extraction of unmetabolized construction source bits or double extraction of metabolized construction source bits' does not prove that the regenerated key bit segment sequence achieves an infinite loop.
  • the invention adopts two measures to realize the infinite non-circular encryption of the regenerated key bit segment sequence: chaotic calculation structure and staggered segment superposition logic structure.
  • chaotic calculation structure There is a probability that repeated sub-bit strings appear periodically in the chaotic computing structure elimination complex reconstruction key bit sequence, but this elimination cannot be proved to be complete.
  • the staggered superposition logic structure of the regenerated key bit segment sequence performs the entanglement between different regenerated key bit segment sequences and the chaotic entanglement of the regenerated key bit segment sequence space in the transition pseudo-random string space in the encryption process. Completely block the periodicity of the change of the regenerated key bit segment sequence.
  • the staggered superposition logical structure refers to the staggered superposition encryption structure of the plaintext bit segment by more than one different regeneration key bit segment sequence when the plaintext is encrypted based on the chaotic computing structure.
  • the staggered-segment overlay encryption is essentially different from the repeated encryption of multiple regenerated key bit-segment sequences. It is a specific logic winding encryption implemented by two or more regenerated key bit segment sequences using chaotic computing structure. Since the single regenerated key bit sequence itself has a chaotic computing structure, the chaotic entanglement effect of the regenerated key bit sequence generated by their staggered superposition can achieve the power-level expansion of the chaotic effect of the single regeneration key bit sequence.
  • the regenerated key bit-segment sequences participating in the mis-segment stacking are all based on the same chaotic computing structure, using the dislocation between different regenerated key bit-segment sequences and the same-scale cutting of regenerated key bit-segments, plaintext bit-segments, and ciphertext bit-segments. It realizes the intertwining of different regenerated key bit segment sequences in the encryption process.
  • Such a logical structure can be further embedded in the pseudo-random bit entanglement of the transition pseudo-random string (see 4.5) in the encryption process.
  • Figure 7 shows a simple staggered stacking logic structure.
  • Figure 8 shows the staggered stacking logic structure with embedded pseudo-random bit wrapping.
  • Figure 7 shows a simple mis-segment stacking logical structure of two regenerated key bit-segment sequences.
  • the logic structure of more heavy and simple staggered superposition is the same.
  • two regenerated key bit segment sequences (k1f i
  • k1li i , i 0,1,...; k2f i
  • k2li i , i 0,1,...; where '
  • the reproduction key bit segment bsk1 i, bsk2 i are respectively cut into two half-sections, k1f i and k1l i, k2f i and k2l i.
  • the first half of one regenerated key bit sequence is superimposed and encrypted with the second half of another regenerated key bit sequence (k1f i /k2l i-1 , k1l i /k2f i ).
  • the length l1f i of the first half-bit segment of bsk1 i (i 0,1,2,).
  • the simplest way of wrapping is to directly use the two half-segments of the two regenerated key bit segment sequences to alternately XOR the two half-segment error segments of the plaintext, which makes the plaintext always be replaced by different regenerated key bit segment sequences. Mis-segment overlay encryption. For more complicated wrapping, see the following staggered stacking logic structure with embedded pseudo-random bit wrapping.
  • bit metabolism logic uses the delayed extraction bit metabolism logic, and other bit extraction logic uses the extracted bit metabolism logic.
  • bit metabolism logic adopts the compound form alternately used by the extraction bit metabolism logic and the deferred bit extraction logic (bit bit extraction logic also adopts the compound form alternately used by the non-deferred bit extraction bit logic and the deferred bit extraction bit logic) .
  • FIG. 8 shows two sets of staggered-segment stacking logic structures each containing two regenerated key bit-segment sequences embedded with three pseudo-random bit-wounds. The same is true for the logical structure of more multiple error segments superimposed with more times of pseudo-random bit entanglement.
  • the pseudo-random bit wrapping is moved backward by half a key bit segment (that is, the pseudo-random bit wrapping is embedded in the sub-regenerating key bit segment sequence, see Figure 9).
  • Figure 8 omits the processing of regenerated key bit segment construction, working pool metabolism, and stack scheduling in the process of stacking of staggered segments, and focuses on the integration of bit segment segmentation, synchronization processing, and embedded pseudo-random bit wrapping. See Figure 8' for the complete multi-staggered superposition calculation process of multiple embedded pseudo-random bit wrapping (to clearly show the operation sequence, the intermediate calculation step in Figure 8' only replaces the old computing element, the new computing element, calculations, and their results).
  • the transition pseudo-random string refers to the generation of the previous regenerated key bit segment sequence between each re-encryption in the same round, or the pseudo-random bit bit entangled for the subsequent pseudo-random bit entangled or regenerated key bit sequence calculation. pseudo-random string.
  • Pseudo-random bit winding refers to pseudo-randomly rearranging the order of each bit in a transition pseudo-random string. This processing leads to further bits between different rounds of transition pseudo-random strings under the staggered superposition logic structure. twine. Pseudo-random bit bit rearrangement with bit fetch logic Pseudo-random bit conversion with bit metabolism logic The difference between the pseudo-random bit rearrangement in : (1) the object of pseudo-random bit winding is a transitional pseudo-random string; (2) the winding needs to be easy to be reversible.
  • the purpose of (1) is to realize rewinding in the vertical direction of the winding between different regenerated key bit segment sequences; the purpose of (2) is to ensure that it can be decrypted without increasing the amount of decryption calculation.
  • This specification uses the position elements paired in sequence in the position chain pos_chain (ls i -L min ) with the same length of the bit segment to perform bit value swap on the bit pair in the specified transition pseudo-random string.
  • the plaintext bit segment, the regenerated key bit segment, and the ciphertext bit segment are divided into the same scale; the sd in 4.2.2 is used to determine the bit segment segmentation scale: sd, ls i -sd.
  • Each regenerated key bit segment in each group of regenerated key bit segment sequences follows the scale segmentation in 4.5.1: k1f i,q (length is sd), k1l i,q (length is ls i - sd), k2f i, q (length ls i -sd), k2l i, q ( length SD); plaintext bit segments also scale with segmentation Mf i (length sd), Ml i (length ls i- sd).
  • the pseudorandom bit wrapping shown in FIG. 8 is implemented for the full bit segment of the first regenerated key bit segment. Due to the staggered segment effect, this pseudo-random bit wrapping acts on the transition pseudo-random string encrypted by the first regenerated key bit segment and the second half of the previous regenerated key bit segment and the first half of the current round.
  • a transitional pseudo-random string encrypted by the regenerated key bit segment of the segment recombination which realizes another staggered winding between the preceding and following bit segments on the basis of the staggered winding between the two sets of mutually different regeneration key bit segment sequences.
  • bit metabolism logic uses the extracted bit metabolism logic
  • the deferred bit fetching logic uses the deferred bit fetching logic
  • other bits fetch bits The logic uses the extracted bits of metabolic logic.
  • bit metabolism logic should preferably adopt a mixed form of alternately used bit extraction logic and deferred bit extraction logic (bit extraction logic also adopts non-deferred bit extraction logic and deferred bit extraction logic. A composite form of alternate use of bit-fetching logic).
  • 5.1.2 Determine the size of the key, select the size of the pool, and the size of the initial working pool according to the configuration logic, and load the initial working pool with the key according to the size of the initial working pool.
  • Example 1 the non-superposition & single metabolism model matched with progressive bit logic/deferred displacement logic is selected as Example 1, and progressive chain displacement logic/deferred displacement logic and bit-hopping bit logic/extracted bit are selected.
  • Example 2 The double-stacking & double-metabolism staggered stacking model with embedded pseudo-random bit-wound embedded in the metabolic logic is used as Example 2.
  • the purpose is to: (1) explain the basic form of the composite logic structure and the correlation form of the chaotic computing structure with the bit fetching logic and bit metabolism logic through embodiment 1; (2) explain the more complex association form of the composite logic structure through embodiment 2 :
  • Example 1 Non-superimposed & single metabolic model of the progressive-assignment logic/delayed-ascension metabolic logic configuration
  • Embodiment 1 As the secret agreement of encryption/decryption, define the dynamic drive vector vector i of Embodiment 1 as the substring in the selection pool Spool:
  • vectstart 0 is the byte position determined by the first three bytes of the key
  • vectstart 0 ((Spool work [0]+Spool work [1]+Spool work [2])%640)/8,
  • length(Spool work ) is the length of the work pool, and its initial value is the key length
  • vectstart i is the first byte of the i-th dynamic drive vector in the work pool (continue from the beginning after reaching the end of the work pool),
  • vector i is the dynamic driving vector of the i-th wheel
  • the dynamic driving vector is shifted backward by one byte (continue from the beginning after reaching the end of the working pool),
  • vector 0 [0] are the first two bytes of the initial dynamic drive vector vector 0.
  • vector 0 [2] are the third and fourth bytes of the initial dynamic drive vector vector 0.
  • the length of the padded pseudo-random string ms additn is L max .
  • vector 0 [2] is the third byte of the initial dynamic drive vector vector 0.
  • pickbyte i,0 (pickbyte i-1,0 +1)%workbyte(9)
  • vector 0 is the initial driving vector
  • Workbyte is the length of the work pool calculated in bytes (the same below),
  • pickbyte i-1,0 is the first construction byte of the previous round
  • pickbyte 0, 0 is the first construction byte of the first round
  • pickbyte i, 0 in (9) is the construction byte of the i-th round head
  • pickbyte i, 0 is incremented by one round in the work pool SPool work bytes (continue from the beginning after reaching the end of the worker pool).
  • pickbyte i,j (pickbyte i,j-1 +1)%workbyte (9")
  • pickbyte i,j is the jth construction byte of the i-th round, which is progressively advanced byte by byte in the work pool SPool work (continues from the beginning after reaching the end of the work pool).
  • pickdrivelmt 0,0 ((pickbyte 0,0 +workbyte)*8-vector 0 [0])%length(Spool work ) (10)
  • pickdrivelmt i,0 (pickdrivelmt i-1,0 +1)% workbyte (10')
  • pickdrivelmt 0,0 is a position in the working pool, which differs from pickbyte 0,0 by a relative bit difference determined by the pseudo-random key of the key.
  • Step j j+1, repeat the above 9.3.2 and 9.3.3 until the length of the output pseudo-random string reaches ls i .
  • workbyte is the length of the work pool, in bytes.
  • the metabolizebyte i,j is advanced byte by byte in the worker pool SPool work (continues from the beginning after reaching the end of the worker pool).
  • metabolbit i (j) (metabolbit i (j-1)+1)%8 (12')
  • the pos_chain(ls i -L min ) is metabolized in the manner described in 2.7 of the description of the sequence encryption method for the complex reconstructed key.
  • step i i + 1, ls i is calculated, if the length of the plaintext bit segment is less than M i ls i is performed after the following encryption processing, or executes the loop 4-8.
  • Example 1 The encryption/decryption calculation formula and calculation unit 10 metabolize the working pool with the logic of deferred lifting metabolism.
  • Example 2 Progressive chain bit-taking logic/deferred bit-lifting metabolism logic and bit-hopping bit-taking logic/double-stacking & double-metabolism-staggered stacking model with embedded pseudo-random bit-wrapping supported by extracted bit-metabolism logic
  • the regeneration key bit segment sequence group is identified by ( 1, 2 in bsk1 i,q , bsk2 i,q , see 4.5 of the staggered stacking logical structure) and the sub-label of the regenerated key bit segment sequence in the group ( q in bsk1 i,q , bsk2 i, q, see The staggered stacking logical structure 4.5) is merged into '1' or '2', and the stack is replaced by a single buffer.
  • 9.1.1.1 Define the starting byte position of the construction source of the first regeneration key bit segment sequence in the work pool SPool work:
  • pickarea1start 0 vector 0 % workbyte (14)
  • pickarea1start i (pickarea1start i-1 +1)%workbyte (14')
  • (14) is the start byte position of the first round construction source in the work pool SPool work
  • (14') is the start byte position of the other round construction sources in the work pool SPool work .
  • (15) is a construction source composed of ls i bytes starting from pickarea1start i (h is carried in bytes and continues from the beginning when it reaches the end of the working pool).
  • pos_chain(ls i -L min ,j) is the jth position element in the position chain pos_chain(ls i -L min ) having the same length as the length of the bit segment.
  • the metabolic target is the metabolic target area where the key bit segment sequence is first regenerated.
  • pickstart2 i,0 vector i [2] % length(Spool work )
  • the construction source pickarea2 i is composed of the bit string from the construction source starting position pickstart2 i,0 to the tail of the selection pool and the two bit strings from the selection pool head to the construction source starting position pickstart2 i,0 .
  • pickdrivstart2 i,0 (pickstart2 i,0 +length(Spool work )-vector i [4]-1)%length(Spool work )
  • the manipulation source pickdrivearea2 i is composed of the bit string from the starting position of the manipulation source pickdrivstart2 i,0 to the tail of the selection pool and the two bit strings from the head of the selection pool to the starting position of the manipulation source pickdrivstart2 i,0 .
  • the first/second half-bit segment K1f i , K1l i (the first and second half-bit segment of the regeneration key bit segment of the first regeneration key bit segment sequence)
  • the first/second half-bit segment of the secondary key K2f i , K2l i (the first and last half-bit segment of the regeneration key bit segment of the secondary key bit segment sequence)
  • the first/second half-bit segment T1f i X2l i-1 , T11 i X2f i (the first/second half-bit segment encrypted with the secondary regeneration key bit segment sequence after implementing pseudo-random bit winding)
  • Ciphertext first/second half-bit segment Cf i , Cl i (ciphertext first and second half-bit segment)
  • K1l 0 ) of the first regeneration key bit segment sequence is constructed according to the encryption/decryption calculation formula and calculation unit 9 of Embodiment 2.
  • K2l 0 ) of the secondary regeneration key bit segment sequence is constructed according to the encryption/decryption calculation formula and calculation unit 12 of the second embodiment.
  • the working pool is metabolized in the growth phase with the plaintext bit segment M 0 (ie, the pseudo-plaintext pM 0 ) (refer to the single complex reconstruction logical structure 1.5.5.1).
  • Nibble Nibble T1l 0 X generated after the transition time period after the half-section transition section K2f 0 after 11 rearranged encrypted key seq T1l 0 X2f 0.
  • the extracted bits are metabolized using the extracted output pseudo-random string according to the encryption/decryption calculation formula and calculation unit 13 of Embodiment 2. If the pool is not working reach maturity, while the express bit segments M i (i.e., pseudo plaintext pM i) growing metabolic embodiment of the operating tank (see single complex reconfigurable logic structure 1.5.5.1).
  • the decryption process Since the pseudo-random bit winding process is embedded in the encryption process, the decryption process must be processed in reverse encryption order after extracting the regenerated key bit segment and releasing the position chain pos_chain(ls i -L min ) used for the pseudo-random bit winding. :
  • configuration structure control amount dynamic drive vector vector 0 , selection pool Spool, work pool SPool work , maximum length of bit segment L max , minimum length of bit segment L min , length of pseudo-plaintext pM , the end of the plaintext EOP, the position chain set pos_chain.
  • the working pool is metabolized in the growth phase with the plaintext bit segment M 0 (ie, the pseudo-plaintext pM 0 ) (refer to the single complex reconstruction logical structure 1.5.5.1).
  • the extracted bits are metabolized using the extracted output pseudo-random string according to the encryption/decryption calculation formula and calculation unit 13 of Embodiment 2.
  • the present invention can configure the corresponding encryption model according to the needs of the application form, and the application range is wider. And it has some room for adjustment and integration with other methods.
  • the present invention can adapt to the security needs of the increasing computing power. It can be proved that, except for brute force attacking the key, there is no attack algorithm with polynomial time complexity for cracking the key, that is, the present invention provides an example of P ⁇ nP.

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Abstract

本发明公开了一种复重构密钥的序列加密方法：使用一套复合逻辑构建混沌计算结构，实现混沌的bit位段流序列加密。本发明通过混沌的计算结构调度bit取位逻辑、bit代谢逻辑、bit重构逻辑等计算逻辑单元，逐段伪随机重构构造源及操控源，并使用操控源伪随机操控构造源逐bit复重构密钥位段，构造'伪随机错位提取未被代谢的密钥位段构造源bit位或者重位提取已被代谢的密钥位段构造源bit位'的无限不循环的再生密钥位段序列。本发明的核心：(A)构建混沌计算结构，在加密进程中逐段对工作池新陈代谢，进而对工作池承载的操控源、构造源逐段以操控源中的bit位操控bit取位逻辑提取构造源中的bit位，伪随机复重构密钥位段。(B)基于混沌计算结构，整合bit取位逻辑和bit代谢逻辑，构建'伪随机错位提取未被代谢的构造源bit位或者重位提取已被代谢的构造源bit位'的密钥位段无限不循环构建逻辑。(C)基于混沌计算结构对多于一个的不同再生密钥位段序列实现错段叠加加密。本发明的有益效果为：适应计算能力突破性提升，提供一套高效、高密度、具有广泛应用空间的安全加密方法。

Description

复重构密钥的序列加密方法 技术领域
本发明涉及信息安全密码学领域，是一种复重构密钥的序列加密方法。
背景技术
中国专利申请号：201710249427.9公开了一种基于随机二进制序列，具有可调整性的伴随式随机重构密钥的序列加密方法，方法的主要特征是：(1)使用已存在的随机序列动态构造种子随机序列。(2)使用种子随机序列以定长或不定长的位段伪随机构造随机密钥。(3)随机密钥的伪随机构造过程伴随加密过程。(4)利用异或运算的传递性实现密钥对明文的变频非线性异或。(5)通过特征量和其他操控量以及伪随机构造函数的调整实现密钥构造的调整，进而在不增加时间复杂度的前提下实现加密密度的调整。(6)这种伴随式伪随机重构密钥方法中使用的特征量或其他操控量不可能在多项式时间复杂度内被反推。方法的基本原理是：利用随机序列的随机性伪随机操控加密逻辑过程进而实现密钥构造过程的充分混沌和隐蔽，以加/解密双方隐性约定的密约阻断对密文的解析途径。
发明内容
本发明公开了一种使用密钥和结构配置量配置结构操控量实现混沌计算结构，进而以其调度配套的复合逻辑实施混沌的bit位段流序列加密的方法。
本发明的目的通过如下构思实现：基于复合逻辑构建混沌计算结构，对明文按伪随机确定的不定长位段逐轮(或称逐段)加密。加密进程中，依据计算结构的配置逐段伪随机重构密钥位段构造源(或称构造源)及密钥位段操控源(或称操控源)，并使用操控源伪随机操控构造源逐轮逐bit位复重构再生密钥位段。进一步，整合逐段生成的再生密钥位段序列实施无限不循环的bit位段流序列加密。实现构思目标的关键是：调度bit取位逻辑、bit代谢逻辑、bit重构逻辑(包括伪随机bit位重排逻辑和伪随机bit位转换逻辑，见若干要点的说明)复重构‘伪随机错位提取未被代谢的构造源bit位或者重位提取已被代谢的构造源bit位’的再生密钥位段序列，进而：(1)以混沌计算结构消解产生于有限集的再生密钥位段序列的周期率，(2)以多于一个的再生密钥位段序列的错段叠加实现再生密钥位段序列间缠绕并嵌入伪随机bit位缠绕。技术方案包括：
(1)由密钥通过结构配置量构建混沌的计算结构，支撑伪随机确定各段计算参量的逐位段序列加密。
(2)以密钥加载初始工作池，引领逐位段逻辑缠绕的混沌加密进程。
(3)以加密方独立构建的伪明文扩展工作池，进一步混沌加密进程，提升安全阀值。
(4)建立工作池逐轮代谢机制，配套配置bit取位逻辑和bit代谢逻辑，建立‘伪随机错位提取未被代谢的构造源bit位或者重位提取已被代谢的构造源bit位’的再生密钥位段构建逻辑。
(5)以混沌计算结构消解所构建的再生密钥位段序列的有概率出现的周期律。
(6)使用差异的构造源、操控源、bit取位逻辑和bit代谢逻辑构造不同的再生密钥位段序列，并基于混沌计算结构实现不同再生密钥位段序列的嵌入伪随机bit位缠绕的错段叠加加密。
(7)基于密钥建立明文结束符，化解明文结束位置与计算结束位置之间的错位并以明文结束符作为解密计算正确性的效验码。
本发明中，根据加/解密双方隐秘约定的结构配置量和密钥，伪随机确定动态驱动向量的初值、位段长度限定最大值/最小值、密钥位段选取池(或称选取池)的尺寸和伪明文随机串的尺寸等计算结构操控量(或称结构操控量)，逐轮伪随机更新选取池中的构造源和操控源、加密位段长度等，构建混沌的再生密钥位段序列，并进一步通过错段叠加逻辑结构幂级放大混沌效应，整合基于再生密钥位段序列的无限不循环位段流加密(bit-segment stream encryption)。
本发明的有益效果是：为适应计算能力突破性提升，提供一种高效、高密度、具有广阔应用空间的安全加密方法。
若干要点的说明
本发明使用了一个被本说明书称之为混沌计算结构的概念：在加密进程中使用伪随机变化的计算参量造成加密计算轨迹的混沌，迫使攻击者面对混沌的计算形态。由密钥驱动的混沌计算结构的不确定性为位段流序列加密提供了广阔的逻辑整合空间。基于逻辑整合的加/解密混沌轨迹的伪随机变化，加/解密双方对其可控，但攻击者却面对混沌的轨迹形态。本发明的这种混沌计算结构产生的混沌计算形态包括如下方面：使用不同密钥生成的结构操控量的伪随机变化，加密进程中由结构操控量逐段再生的计算参量的伪随机变化，和由计算参量所驱动的加密进程中加密逻辑单元整合形态(bit取位逻辑、bit代谢逻辑和bit重构逻辑的输入/输出及其匹配效应)、再生密钥位段构建形态(长度及构造规律)、再生密钥位段整合形态(错段叠加和嵌入伪随机bit位缠绕)的伪随机变化。
本发明使用选取池作为构造源和操控源的载体，选取池的内容随加密进程逐段更替。选取池在加密之初只有部分内容有效，本说明书称其为密钥位段工作池(或称工作池)。工作池随再生密钥位段的重构而逐段扩展直至填满选取池，本说明书称此阶段为工作池的成长期。渡过成长期后工作池达到成熟期，成熟期中工作池依然随再生密钥位段的重构而更替。本说明书统称工作池成长期中的成长和成熟期中的更替为工作池(或选取池)的新陈代谢(或称代谢)。
本发明在明文之前添加与明文内容无关的伪明文随机串(或称伪明文)。伪明文具有特征：(1)由于随机串不具有可识别性，使得对伪明文的攻击无从辨别成功与否。在工作池的成长期中伪明文逐段嵌入工作池，在工作池达到成熟期后伪明文具有与密钥等效的作用。(2)伪明文并非密钥，而是加密方独立构建的在成长期中扩展工作池的随机串，解密后被视为费码。(3)伪明文在加密过程中具有进一步混沌计算进程的作用，不同的伪明文导致对正式明文加密时构造源、操控源的差异，进而导致再生密钥位段序列的差异。
‘伪随机错位提取未被代谢的构造源bit位或者重位提取已被代谢的构造源bit位’中的‘错位提取’是指不同次提取位置互异的bit位，‘重位提取’是指不同次提取位置相同的bit位。
bit取位逻辑和bit代谢逻辑是实现‘伪随机错位提取未被代谢的构造源bit位或者重位提取已被代谢的构造源bit位’的重要构成逻辑单元。它们的整合效应对于本发明的无限不循环体系不可或缺。本发明的复合逻辑结构需要包容不止一种bit取位逻辑和bit代谢逻辑。不同的bit取位逻辑和bit代谢逻辑可整合成不同组合的计算模型，协同使用不同的bit取位逻辑和bit代谢逻辑构成的错段叠加逻辑结构可以幂级 提升本发明的安全性。本说明书陈列的bit取位逻辑包括密钥位段递进取位逻辑(或称递进取位逻辑)、密钥位段递进链取位逻辑(或称递进链取位逻辑)、密钥位段位跳跃取位逻辑(或称位跳跃取位逻辑)、以及密钥位段顺延提位取位逻辑(或称顺延提位取位逻辑)，本说明书陈列的bit代谢逻辑包括密钥位段选取池顺延提位代谢逻辑(或称顺延提位代谢逻辑)和密钥位段选取池被提取位代谢逻辑(或称被提取位代谢逻辑)。本发明的复合逻辑结构也可以包容其他bit取位逻辑和bit代谢逻辑。
遵循‘伪随机错位提取未被代谢的构造源bit位或者重位提取已被代谢的构造源bit位’的原则，本发明允许在提取bits串后进行伪随机bit位重排生成再生密钥位段，本说明书称此为伪随机bit位重排
Figure PCTCN2021102451-appb-000001
本发明也需要在工作池新陈代谢之前对原始代谢源伪随机串(即生成再生密钥位段前的bit取位逻辑所输出的输出伪随机串，下同)进行(1)伪随机bit位重排，同时(2)逐位对bit值取反(0转1或1转0，或称
Figure PCTCN2021102451-appb-000002
互换)，(3)加糖。本说明书将对原始代谢源伪随机串的伪随机bit位重排、
Figure PCTCN2021102451-appb-000003
互换、加糖合称为伪随机bit位转换
Figure PCTCN2021102451-appb-000004
(详见bit取位逻辑和bit代谢逻辑的关联)。
本发明使用一个贯穿全计算进程的动态驱动向量。动态驱动向量逐轮更替(或称代谢)。在本说明书中使用的动态驱动向量的初始值由密钥伪随机生成，将此初始值改为加/解密双方隐秘约定而非密钥生成的初始值本发明依然可行。这不牵涉加密运算的结构，本说明书不做进一步说明。
由于加密进程中位段长度的伪随机变化，大概率地会形成分段计算的结束位置与明文结束位置错位，本发明使用由密钥伪随机构造的明文结束符标定明文结束位置并以追加伪随机串的方式消解上述错位效应。由于本发明的加/解密进程的层层缠绕具有传导效应，这使得任一加/解密错误都将延续到其后的计算，致使加密、传输、解密过程中的错误将导致解密不能得到明文结束符，所以明文结束符同时具有效验码的功能。
为了清晰表述本发明的复合逻辑结构，本说明书将复重构密钥的序列加密方法的说明拆分成三个逻辑组件(logic component)进行说明：(1)单一复重构逻辑结构，(2)bit取位逻辑和bit代谢逻辑的整合，(3)错段叠加逻辑结构。
本发明的核心：(A)构建混沌计算结构，在加密进程中逐段对工作池新陈代谢，进而对工作池承载的操控源、构造源逐段以操控源中的bit位操控bit取位逻辑提取构造源中的bit位，伪随机复重构再生密钥位段。(B)基于混沌计算结构，整合bit取位逻辑和bit代谢逻辑，构建‘伪随机错位提取未被代谢的构造源bit位或者重位提取已被代谢的构造源bit位’的再生密钥位段无限不循环构建逻辑。(C)基于混沌计算结构对多于一个的不同再生密钥位段序列实现错段叠加加密。
混沌计算结构拓展了‘伪随机错位提取未被代谢的构造源bit位或者重位提取已被代谢的构造源bit位’效应，在了解‘伪随机错位提取未被代谢的构造源bit位或者重位提取已被代谢的构造源bit位’的基本运转原理的基础上才能看清混沌计算结构的拓展效应。所以本说明书在说明bit取位逻辑和bit代谢逻辑的整合后插入混沌计算结构的拓展效应的说明。
作为本发明的实施例，本说明书选择递进取位逻辑/顺延提位代谢逻辑配置的非叠加&单代谢模型作为实施例1，递进链取位逻辑/顺延提位代谢逻辑和位跳跃取位逻辑/被提取位代谢逻辑配置的双叠加&双代谢错段叠加模型作为实施例2。并不排斥其他组合模型。
本发明的有些逻辑单元(或称逻辑步)是可以省略或不省略的，省略或不省略根据不同逻辑搭配而取 舍(例如伪随机bit位重排
Figure PCTCN2021102451-appb-000005
就可根据不同情况而取舍)，除特定情况外本说明书的图示中将以不省略的形式展示。因为这种逻辑单元依然是逻辑结构的一部分，将其展示出来有利于看清逻辑关联。
本说明书中对位置链有三种表示方式:(1)pos_chain，(2)pos_chain(j),j＝0,1,2,…L max-L min，(3)pos_chain(j,k),j＝0,1,2,…L max-L min，k＝0,1,2,…,L min+j-1。其中(1)笼统针对位置链集时使用，(2)针对由各个位置链所构成的集合时使用，(3)针对位置元集时使用。此外，pos_chain(j)特指以j标定的某一位置链，pos_chain(j,k)特指以j、k标定的某一位置元。本说明书中在嵌入伪随机bit位缠绕的错段叠加逻辑结构的位置链表述中采用了一个专述形式——位置链pos_chain(r)，r＝0,1,…,2s-2，此处r不是指位置链集pos_chain(j),j＝0,1,2,…L max-L min中的位置链序号，而是指用于对位置链集中的第ls i-L min个位置链pos_chain(ls i-L min)反复代谢2s-1次中的第r次代谢时的位置链pos_chain(ls i-L min)(参见错段叠加逻辑结构中对4.5.3.2、4.5.4.4的注释)。
本说明书中在说明部分(实施例之前)采用统一目录标号(如上述4.5.3.2)。对各实施例根据所述主题分别采用新的目录标号，其中除标明主题前缀的目录标号(如：‘实施例1的加/解密计算公式及计算单元7’)外，其它实施例叙述文字中的目录标号都指当前主题的目录标号(如：实施例2的加/解密进程操控中的解密20中的‘重复11至19步骤……’是指实施例2的解密11至19)。
本说明书以可行但不唯一的计算公式和计算参量进行说明，并不排斥其他遵循本发明构思的等同配置。可以理解的是，对本发明的技术方案及发明构思加以等同替换、改变或简化都应属于本发明所附权利要求的保护范围。
附图说明
图1为单一复重构逻辑结构的原理示意图。
图2为递进取位逻辑和顺延提位代谢逻辑的配套工作原理示意图。
图3为递进链取位逻辑和被提取位代谢逻辑的配套工作原理示意图。
图4为位跳跃取位逻辑和被提取位代谢逻辑的配套工作原理示意图。
图5为顺延提位代谢效果示意图。
图6为被提取位代谢效果示意图。
图7为简单错段叠加逻辑结构原理示意图。
图8为嵌入伪随机bit位缠绕的错段叠加逻辑结构原理示意图。
图8’为嵌入伪随机bit位缠绕的错段叠加逻辑的计算过程示意图。
图9为与图8的嵌入位置不同的嵌入伪随机bit位缠绕的错段叠加逻辑结构示意图。
复重构密钥的序列加密方法的说明
本发明中复合逻辑结构是实现被复重构的再生密钥位段序列及其整合的基础。为了清晰表述本发明的复合逻辑结构，本说明书将复合逻辑结构拆分成三个逻辑组件(单一复重构逻辑结构，bit取位逻辑和bit代谢逻辑的整合，错段叠加逻辑结构)进行说明。由于混沌计算结构消解再生密钥位段序列的周期率的功效基于bit取位逻辑和bit代谢逻辑的整合，所以在阐述了bit取位逻辑和bit代谢逻辑的整合之后插入混 沌计算结构对‘伪随机错位提取未被代谢的构造源bit位或者重位提取已被代谢的构造源bit位’效应的拓展。错段叠加逻辑结构是本发明的混沌计算结构的复合效应，达成本发明构思的目标。
1单一复重构逻辑结构
单一复重构逻辑结构实现由密钥伪随机调度复重构再生密钥位段序列的过程：在加/解密之初的预处理中，本发明使用加/解密双方隐秘约定的结构配置量结合密钥配置结构操控量，支撑加/解密进程中由结构操控量逐段伪随机重构计算参量，实施对各逻辑单元的操控。在加/解密进程中，基于这种操控所实现的混沌计算结构协同bit取位逻辑和bit代谢逻辑共同支撑‘伪随机错位提取未被代谢的密钥位段构造源bit位或者重位提取已被代谢的密钥位段构造源bit位’运转。
结合附图1介绍本发明构建再生密钥位段序列中各计算单元的关联关系：
1.1图1展示加密进程。由于解密进程仅仅在(1)预处理和后处理中与加密进程存在非结构性差异，(2)工作池成长期中的代谢源存在非结构性差异，所以对解密进程不做赘述，仅在需要说明时进行说明。
1.2图1中
Figure PCTCN2021102451-appb-000006
表示一个以Pnnn标识的计算单元，rvnnn表示一个Pnnn的输出，
Figure PCTCN2021102451-appb-000007
特定表示bit取位逻辑或bit代谢逻辑，s001表示加密对象，
Figure PCTCN2021102451-appb-000008
表示所指计算单元的结构操控量(如rV002)、操控源(如key)，
Figure PCTCN2021102451-appb-000009
表示计算单元间的衔接关系，
Figure PCTCN2021102451-appb-000010
特指一个伪随机bit位重排，
Figure PCTCN2021102451-appb-000011
特指一个伪随机bit位转换，
Figure PCTCN2021102451-appb-000012
特指由原始代谢源伪随机串进行伪随机bit位转换
Figure PCTCN2021102451-appb-000013
1.3通过加/解密双方隐秘约定的结构配置量及密钥，伪随机地配置结构操控量。例如被标记为rV001的位段长度限定最大值(Max length of bit segment，或称L max)和位段长度限定最小值(Min length of bit segment，或称L min) P002，被标记为rV002的选取池(Source pool，或称Spool)的长度和工作池(Source work pool，或称Spool work)的初始长度 P003，被标记为rV003的动态驱动向量的初值(vector 0) P004，被标记为rV004的明文结束符(End-Of-Plaintext，或称EOP) P005，以及初始位置链集pos_chain等。
1.4使用结构配置量配置混沌计算结构及预处理：
1.4.1依据依据结构配置量ctl init配置选取池Spool的长度、初始工作池Spool work的长度、并以密钥加载工作池Spool work的初始内容。
1.4.2依据选取池Spool的长度按比例生成被标记为rV005的伪明文 P006(pseudo plaintext，或称pM)。
1.4.3拼接伪明文pseudo plaintext、明文plaintext、明文结束符EOP，并追加长度为L max的补齐伪随机串ms additn，重构被加密明文 P007s001(rebuild plaintext，或称明文M或被加密明文M)。
1.4.4使用初始动态驱动向量vector 0计算首轮再生密钥位段、明文位段、密文位段的长度(统称为位段长度ls i，或称ls i)，并根据选用的bit取位逻辑m001在工作池中确定构造源和操控源初始位置，根据选用的bit代谢逻辑m002确定选取池中的初始代谢目标区，并重构其它计算参量。 P008
1.5复重构再生密钥位段并进行加密计算
1.5.1以由rV001计算所得的ls i基于上一明文位段M i-1顺延提取被加密明文位段。
1.5.2从工作池(Spool work)中根据rV001计算所得的ls i使用bit取位逻辑m001伪随机提取输出伪随机串。
1.5.3对1.5.2所得输出伪随机串，以等长的位置链pos_chain(ls i-L min)进行(或不进行)伪随机bit位重排
Figure PCTCN2021102451-appb-000014
(例如：顺序地以位置链中的位置元所指定的输出伪随机串的bit位之值进行拼接)获得当轮再生密钥位段 bsk i 。
1.5.4使用再生密钥位段 bsk i 对明文位段M i进行异或计算 P009。
1.5.5工作池新陈代谢
1.5.5.1工作池的成长期(length(Spool work)<length(Spool))中的新陈代谢
加密时按序用长度等于ls i的伪明文位段pM i追加到工作池尾部或逐bit伪随机地插入工作池，直至工作池达到成熟期。
解密时以解密所得的长度等于ls i的伪明文位段pM i追加到工作池尾部或逐bit伪随机地插入工作池，直至工作池达到成熟期。
(注：成长期的最后一个计算位段的长度大概率地大于剩余伪明文子串的长度，此时仅以剩余伪明文子串追加到工作池尾部或逐bit伪随机地插入工作池。详见2.6)
1.5.5.2工作池的成熟期(length(Spool work)＝length(Spool))中的新陈代谢
1.5.5.2.1对原始代谢源伪随机串(图1中m001的输出)以等长的位置链pos_chain(ls i-L min)进行伪随机bit位转换
Figure PCTCN2021102451-appb-000015
(其中的伪随机重排须异于1.5.3。例如：在伪随机bit位重排之前先对位置链pos_chain(ls i-L min)进行代谢)生成代谢源伪随机串。
1.5.5.2.2使用1.5.5.2.1所得的代谢源伪随机串和bit代谢逻辑m002对工作池Spool work新陈代谢。
1.6 i＝i+1，伪随机重置下一段复重构加密的计算参量 P010’P011，并实施下一段加密(循环执行1.5)直至剩余未被加密的明文的长度小于等于位段长度限定最大值L max。
1.7后处理 P012
1.7.1加密时将明文的计算结束位之后的剩余bits串拼接到密文。
1.7.2解密时清除伪明文pM、明文结束符EOP及其后的补齐伪随机串ms additn。
2 bit取位逻辑和bit代谢逻辑的整合
bit取位逻辑和bit代谢逻辑的整合包括bit取位逻辑和bit代谢逻辑之间的关联操控以及支撑这种关联操控的bit重构逻辑(包括伪随机bit位重排逻辑和伪随机bit位转换逻辑)、位置链pos_chain的代谢及初始化、动态驱动向量vector i的代谢。
为了表述bit取位逻辑与bit代谢逻辑间的关联性，图2、图3、图4都将两者进行了交错展示。
bit取位逻辑、bit代谢逻辑由混沌计算结构规范。混沌计算结构、bit取位逻辑和bit代谢逻辑共同支撑‘伪随机错位提取未被代谢的构造源bit位或者重位提取已被代谢的构造源bit位’的无限不循环运转。
bit取位逻辑
2.1递进取位逻辑(go one by one logic)
结合附图2介绍递进取位逻辑：
2.1.1图2展示的是第i再生密钥位段(首行)和第i+1再生密钥位段(第三行)的递进取位逻辑，图2也展示了与递进取位逻辑交错实施的第i轮(次行)和第i+1轮(第四行)的顺延提位代谢逻辑。第 i+1再生密钥位段的构造源的起始字节C按第i再生密钥位段的构造源的起始字节C顺延一个字节(顺延至工作池尾部后从头续延)。
2.1.2各轮计算中，构造起始字节C作为首构造字节pickstart i,0
Figure PCTCN2021102451-appb-000016
并以其开始的ls i个字节(
Figure PCTCN2021102451-appb-000017
所属的byte，到达工作池尾部时从头续延)作为构造源pickarea i(C～D)。以与C相距确定长度的位置作为首构造操控位pickdrivstart i,0(E)，并以其开始的ls i的n(n可选择3或4或8)倍个bits构成的bits子串作为操控源pickdrivearea i(到达工作池尾部时从头续延)，得到ls i个操控元
Figure PCTCN2021102451-appb-000018
(3或4或8个bits)。
2.1.3从各操控元提取确定位置或伪随机定位的3个bits位之值作为操控值，得到操控值序列pickdriver i(j)(j＝0,1,2,…,ls i-1)。
2.1.4顺序配对操控值序列中的操控值与构造源中的字节，得到操控值/构造字节对序列pickdriver i(j)/pickarea i(j)(j＝0,1,2,…,ls i-1)。
2.1.5顺序地从操控值/构造字节对序列pickdriver i(j)/pickarea i(j)(j＝0,1,2,…,ls i-1)提取按操控值指定的构造字节中的bit位之值拼接输出伪随机串tmp_str(j)(j＝0,1,2,…,ls i-1)。
2.1.6根据单一复重构逻辑结构的1.5.3，对上述输出伪随机串tmp_str(j)(j＝0,1,2,…,ls i-1)实施(或不实施)伪随机bit位重排
Figure PCTCN2021102451-appb-000019
得到再生密钥位段 bsk i 。
2.2递进链取位逻辑(go chain logic)
递进链取位逻辑与递进取位逻辑的区别在于将构造源中顺序排列的字节段的顺序改变成按位置链中位置元排列的顺序。
结合附图3介绍递进链取位逻辑：
2.2.1在单一复重构逻辑结构3(P005之后)中构建L max-L min+1个长度分别从L min到L max的位置链pos_chain(j)，j＝0,1,…,L max-L min(如图3所示的Set of pos_chain)，并将其初始化成L max-L min+1个伪随机排列的位置链pos_chain(j)(j＝0,1,2,…,L max-L min)，(详见5.2)。
2.2.2图3展示的是第i再生密钥位段(首行)和第i+1再生密钥位段(第三行)的递进链取位逻辑，图3也展示了与递进链取位逻辑交错实施的第i轮(次行)和第i+1轮(第四行)的被提取位代谢逻辑。第i+1再生密钥位段的构造源的起始字节C按第i再生密钥位段的构造源的起始字节C顺延一个字节(顺延至工作池尾部后从头续延)。
2.2.3以与递进取位方式相同的方法建立操控源pickdrivearea i和构造源pickarea i，及操控值序列pickdriver i(j)(j＝0,1,2,…,ls i-1)。
2.2.4顺序匹配位置链pos_chain(ls i-L min)中位置元和操控值序列中的操控值，然后通过位置元所指定的构造源中的构造字节位置实现操控值/构造字节之间的匹配，得到操控值/构造字节匹配对pickdriver i(j)/pickarea i(pos_chain(ls i-L min,j))(j＝0,1,2,…,ls i-1)。
2.2.5顺序地从操控值/构造字节匹配对pickdriver i(j)/pickarea i(pos_chain(ls i-L min,j))(j＝0,1,2,…,ls i-1)提取按操控值指定的构造字节的bit位之值拼接输出伪随机串tmp_str(j)(j＝0,1,2,…,ls i-1)。
2.2.6依单一复重构逻辑结构的1.5.3，对2.2.5所得输出伪随机串tmp_str(j)(j＝0,1,2,…,ls i-1)实施(或 不实施)伪随机bit位重排
Figure PCTCN2021102451-appb-000020
得到再生密钥位段 bsk i 。
2.3位跳跃取位逻辑(bit jump logic)
结合附图4介绍位跳跃取位逻辑：
2.3.0为了清晰展示，图4中将构造源与操控源的范围进行了压缩分割。理清逻辑关系后请将两者的范围都扩充至全工作池。
2.3.1图4展示的是第i再生密钥位段(首行)和第i+1再生密钥位段(次行)的位跳跃取位逻辑示图，图4也展示了与位跳跃取位逻辑交错实施的第i轮(首行)和第i+1轮(次行)的被提取位代谢逻辑。
2.3.2确定构造源pickarea i和操控源pickdrivearea i：构造源pickarea i由从构造源起始位pickstart i,0到选取池尾部的bits串和从选取池首部到构造源起始位pickstart i,0之前的bits串拼接而成。各轮构造源起始位pickstart i,0由动态驱动向量vector i伪随机确定(例如使用动态驱动向量vector i所表述之值按工作池长度length(Spool work)取模)。操控源pickdrivearea i由从操控源起始位pickdrivstart i,0到选取池尾部的bits串和从选取池首部到操控源起始位pickdrivstart i,0之前的bits串拼接而成，各轮操控源起始位置pickdrivstart i,0与构造源起始位置pickstart i,0相距固定的或伪随机确定的相对位差dif(0<dif≤length(Spool work))：pickdrivstart i,0＝(pickstart i,0+length(Spool work)-dif)％length(Spool work)。
2.3.3从操控源起始位pickdrivstart i,0开始顺序或伪随机跳跃提取ls i个确定长度的bits串构成位跳跃值序列junp_num(j)(j＝0,1,2,…,ls i-1)(到达工作池尾部后从头续延)。
2.3.4依位跳跃值序列junp_num(j)(j＝0,1,2,…,ls i-1)从构造源起始位pickstart i,0开始在构造源中逐跳跃值junp_num(j)跳跃地确定构造bit位(到达构造源尾部从头续延)，提取其值拼接输出伪随机串tmp_str(j)(j＝0,1,2,…,ls i-1)。
2.3.5使用所构造的输出伪随机串tmp_str(j)(j＝0,1,2,…,ls i-1)并对其进行(或不进行)伪随机bit位重排
Figure PCTCN2021102451-appb-000021
作为再生密钥位段 bsk i 。
2.4顺延提位取位逻辑(raise bit logic)
顺延提位取位逻辑的特点是在构造源的轮转周期(即构造源在工作池中逐轮以byte递进时的重复周期)中不存在未被提取的bit位，因此再生密钥位段序列对工作池的使用率更高。
2.4.1由初始动态驱动向量vector 0伪随机确定首轮构造源起始字节pickstart 0。随后各轮构造源起始字节pickstart i逐轮顺延一个字节(顺延到达工作池尾端从头续延)pickstart i＝(pickstart i-1+8)％length(Spool work)。
2.4.2各轮中构造源pickarea i由从构造源起始字节pickstart i开始顺延的ls i个字节构成(顺延到达工作池尾端从头续延)。
2.4.3令上述构造源pickarea i中首构造字节的被提取bit位为该字节的首bit位，随后逐字节提高一个bit位(达到7后从0续延)作为各构造字节的被提取bit位，以其值拼接输出伪随机串tmp_str(j)(j＝0,1,2,…,ls i-1)。
2.4.4使用所构造的输出伪随机串tmp_str(j)(j＝0,1,2,…,ls i-1)并对其进行(或不进行)伪随机bit位重排
Figure PCTCN2021102451-appb-000022
作为再生密钥位段 bsk i 。
Bit代谢逻辑
Bit代谢逻辑是实现本发明的关键之一。本说明书介绍了两种bit代谢逻辑：顺延提位代谢逻辑和被提取位代谢逻辑。围绕本发明的复合逻辑结构，还有其它几个与bit代谢逻辑相关的代谢逻辑需要说明：成长期的工作池bit代谢、动态驱动向量vector i代谢、和位置链pos_chain代谢。
2.4顺延提位代谢逻辑(raise bit metabolic logic)
顺延提位代谢逻辑的特点是在代谢目标区的轮转周期(即代谢目标区在工作池中逐轮以byte递进时的重复周期)中不存在未被代谢bit位，因此工作池对自然数集的覆盖率更高。
结合附图2、附图5介绍顺延提位代谢逻辑：
2.4.1如图2所示，对原始代谢源伪随机串(即bit取位逻辑从工作池提取的输出伪随机串tmp_str(j)，j＝0,1,2,…,ls i-1)实施伪随机bit位转换
Figure PCTCN2021102451-appb-000023
得到代谢源伪随机串metabolsrc i(j)(j＝0,1,2,…,ls i-1)。
2.4.2如图2所示，选择与操控源起始位置E重叠的字节(并不排斥其他字节)作为顺延提位代谢目标区的起始字节metabolstart i。
2.4.3如图2所示，以从该顺延提位代谢目标区的起始字节metabolstart i(E)开始的ls i个字节构成的字节段(E～F)作为顺延提位代谢目标区metabolarea i。即图中所有
Figure PCTCN2021102451-appb-000024
标定的字节。
2.4.4如图5中
Figure PCTCN2021102451-appb-000025
所示，设定在顺延提位代谢目标区metabolarea i中首字节的代谢bit位为首字节的首bit位，随后逐字节提高一个bit位(达到7后从0续延)作为顺延提位目标区各字节的代谢bit位，得到代谢bit位序列metabolbit i(j)(j＝0,1,2,…,ls i-1)。
2.4.5如图5中
Figure PCTCN2021102451-appb-000026
所示，以2.4.1中代谢源伪随机串metabolsrc i(j)(j＝0,1,2,…,ls i-1)的各bit位之值替换顺延提位目标区各字节的代谢bit位之值，metabolbit i(j)＝metabolsrc i(j)(j＝0,1,2,…,ls i-1)。
2.5被提取位代谢逻辑(matched bit metabolic logic)
结合附图4介绍被提取位代谢逻辑：
如图4所示在被提取位代谢逻辑中，被提取位
Figure PCTCN2021102451-appb-000027
与代谢位
Figure PCTCN2021102451-appb-000028
重叠。
2.5.1在任何bit取位逻辑构建输出伪随机串tmp_str(j)(j＝0,1,2,…,ls i-1)时保留各提取位作为被提取位序列pickedbit i(j)(j＝0,1,2,…,ls i-1)。
2.5.2使用位置链pos_chain(ls i-L min,j)(j＝0,1,2,…,ls i-1)对原始代谢源伪随机串进行伪随机bit位转换
Figure PCTCN2021102451-appb-000029
得到代谢源伪随机串metabolsrc i(j)(j＝0,1,2,…,ls i-1)。
2.5.3逐一以代谢源伪随机串metabolsrc i(j)(j＝0,1,2,…,ls i-1)对被提取位序列pickedbit i(j)(j＝0,1,2,…,ls i-1)代谢pickedbit i(j)＝metabolsrc i(j)(j＝0,1,2,…,ls i-1)。
2.6成长期的工作池bit代谢
2.6.1加密中，按序以加密方生成的长度等于或小于ls i的伪明文位段pM i(按序顺延的剩余伪明文长度大于等于ls i时取pM i＝ls i；按序顺延的剩余伪明文长度小于ls i时取pM i＝剩余伪明文长度。)追加到工作池尾部或逐bit伪随机插入工作池。并增长工作池长度length(Spool work)＝length(Spool work)+length(pM i)。
2.6.2解密中，以解密所得的长度等于或小于ls i的伪明文位段pM i(按序顺延的剩余伪明文长度大于等于 ls i时取pM i＝ls i；按序顺延的剩余伪明文长度小于ls i时取pM i＝剩余伪明文长度。)追加到工作池尾部或
伪随机地逐bit插入工作池。同时增长工作池长度length(Spool work)＝length(Spool work)+length(pM i)。注释：2.6.1、2.6.2中，以伪明文位段pM i伪随机地逐bit插入工作池的伪随机算法允许是任意的，因为密钥和伪明文都是随机串，都不具有可识别性。
2.7位置链(pos_chain)代谢
位置链代谢有多种可行方法，本说明书介绍一种由工作池的随机性确定位置链的随机性的方法：
2.7.1建立长度为(1/2)length(vector i)的空的过渡位置链tmp_chain。
2.7.2顺序提取动态驱动向量vector i的每两个bits所表示之值作为跳跃值得到一个跳跃值序列rp j(j＝0,1,…,(1/2)length(vector i)-1)。
2.7.3令p 0＝rp 0，p j＝p j-1+rp j+1，tmp_chain(j)＝pos_chain(ls i-L min,p j)，并逐j从位置链(pos_chain(ls i-L min))中剔除位置元pos_chain(ls i-L min,p j)，j＝0,1,…,min((1/2)length(vector i)-1,ls i-1)。
于是将pos_chain(ls i-L min)部分或全部地导入tmp_chain。
2.7.4当(1/2)length(vector i)<ls i时，将过渡位置链tmp_chain中的(1/2)length(vector i)个位置元追加到位置链pos_chain(ls i-L min)的第ls i-(1/2)length(vector i)之后；当(1/2)length(vector i)≥ls i时，以过渡位置链tmp_chain直接替换位置链pos_chain(ls i-L min)。
2.8动态驱动向量vector i代谢
对动态驱动向量vector i的代谢是保证复重构再生密钥位段的随机性的关键之一。存在多种动态驱动向量vector i的代谢方法。本说明书例举两个由工作池的随机性确定动态驱动向量vector i的随机性的方法：
2.8.1以对工作池中原提取动态驱动向量vector i-1的字节段逐轮在工作池中向后顺延一个字节(到达工作池尾部后从头续延)的方式获得动态驱动向量vector i。
2.8.2从工作池中提取或者加/解密双方隐秘约定初始动态驱动向量vector 0，逐轮以前一轮动态驱动向量vector i-1与工作池中伪随机确定的与前一轮动态驱动向量vector i-1位置不同的等长bits串异或，生成新的动态驱动向量vector i。
bit取位逻辑和bit代谢逻辑的关联
2.9 bit取位逻辑和bit代谢逻辑的配套使用
本说明书展示了四个bit取位逻辑、两个bit代谢逻辑，并不排斥其它bit取位逻辑、bit代谢逻辑。
bit取位逻辑和bit代谢逻辑的配套使用是实现‘伪随机错位提取未被代谢的构造源bit位或者重位提取已被代谢的构造源bit位’的无限不循环再生密钥位段序列的关键之一。两者的不同匹配，可以构造不同的再生密钥位段序列，并且实现再生密钥位段序列对自然数集合的不同的覆盖率。其效应在多个再生密钥位段序列的错段叠加加密中尤为明显。
对于本说明书陈列的bit取位逻辑和bit代谢逻辑，共有八种可以使用的配套。为避免赘述，图2、3、4中各展示了其中一套，基本概括各种配套的特征。其中，图2展示的是递进取位逻辑与顺延提位代谢逻辑的匹配工作形态。图3展示的是递进链取位逻辑与被提取位代谢逻辑的匹配工作形态。图4展示的是位跳跃取位逻辑与被提取位代谢逻辑匹配的工作形态。
2.9.1 bit取位逻辑直接作用于当前轮加密，bit代谢逻辑影响后续轮加密。
2.9.2 bit代谢逻辑对工作池代谢中的随机性越高，再生密钥位段序列对自然数集合的覆盖率越高。再生密钥位段序列对自然数集合的覆盖率越高，本发明越接近perfect secerecy system。
2.9.3对于顺延提位取位逻辑，当选择代谢目标区与构造源重叠时被提取位代谢逻辑和顺延提位代谢逻辑相同。
2.9.4对于顺延提位代谢逻辑，除去匹配顺延提位取位逻辑外，选择代谢目标区的起始位置为操控源的起始位置时随后轮的再生密钥位段的随机性较高。
2.9.5采用被提取位代谢逻辑保证了工作池中不存在重位未被代谢的bit位。采用顺延提位取位逻辑与顺延提位代谢逻辑匹配时，工作池中也不存在重位未被代谢的bit位。
2.9.6顺延提位代谢逻辑与非顺延提位取位逻辑匹配时，尽管当轮的工作池中会出现重位未被代谢的bit位，但由于构造源在工作池的轮转周期中不存在未被代谢的bit位，在逐轮顺延的加密过程中顺延提位代谢逻辑对工作池的整体代谢率更高，这使得工作池对自然数集合的覆盖率更高。
2.9.7图6对比展示了非递进链取位逻辑/被提取位代谢逻辑匹配与递进链取位逻辑/被提取位代谢逻辑匹配的区别。前者中提取位与代谢位顺序对应。后者中由于提取位按位置链指定的顺序排列，提取位与代谢位伪随机地错位。
2.9.8在单一复重构加密模型中顺延提位取位逻辑有概率形成安全漏洞，所以不适合在单一复重构加密模型中使用。但由于其对工作池的使用率更高，在多个再生密钥位段序列的错段叠加加密中顺延提位取位逻辑与非顺延提位取位逻辑混用的效果更好。
2.9.9为保证‘重位提取已被代谢的构造源bit位’，与顺延提位取位逻辑配套的bit代谢逻辑必须是顺延提位代谢逻辑。
2.9.10生成再生密钥位段之前对输出伪随机串的伪随机bit位重排
Figure PCTCN2021102451-appb-000030
是可选的(这里可选指不选择伪随机bit位重排
Figure PCTCN2021102451-appb-000031
并不破坏本发明运行结构的可行性)，在工作池代谢之前的对原始代谢源伪随机串的伪随机bit位转换
Figure PCTCN2021102451-appb-000032
中的伪随机bit位重排是必要的。同时使用伪随机bit位重排
Figure PCTCN2021102451-appb-000033
和伪随机bit位转换
Figure PCTCN2021102451-appb-000034
并保证后者中伪随机bit位重排与前者互异将提高破解攻击难度(阻断再生密钥位段与代谢源伪随机串间互推)。
2.9.11伪随机bit位转换
Figure PCTCN2021102451-appb-000035
有三个目的：保证‘重位提取已被代谢的构造源bit位’、消解工作池中‘0’、‘1’非均匀分布的扩散、避免工作池中‘0’、‘1’分布的绝对均匀化。采用的技术手段包括：伪随机bit位重排、在伪随机bit位重排的同时逐位
Figure PCTCN2021102451-appb-000036
互换、和间隙性地加糖。
伪随机bit位重排的目的是基于工作池中原有‘0’/‘1’比例更新的‘0’/‘1’排列。
在伪随机bit位重排的同时逐位
Figure PCTCN2021102451-appb-000037
互换的目的是消解工作池中有概率出现的‘0’、‘1’bit值的比例失衡，并阻断这种失衡在再生密钥位段序列构建时的扩散。
加糖是指：利用混沌计算结构中计算参量的伪随机变化特性，根据计算参量间隙性出现的状态(例如：(a)、位置链中特定位置的位置元等于0或ls i时；或者(b)、动态驱动向量vector i的某确定字节之 值等于0或者ls i时；(c)、上述(a)或(b)不矛盾地组合成立。(a)或(b)不矛盾地组合成立是指：(1)位置链中特定位置的位置元等于0，并且/或者动态驱动向量vector i的某确定字节之值等于0；(2)位置链中特定位置的位置元等于ls i，并且/或者动态驱动向量vector i的某确定字节之值等于ls i；(3)位置链中特定位置的位置元等于0与动态驱动向量vector i的某确定字节之值等于ls i不同时成立，并且位置链中特定位置的位置元等于ls i与动态驱动向量vector i的某确定字节之值等于0不同时成立。并不排斥其他计算参量间隙性出现的状态。)触发以全‘0’或全‘1’bit串替代代谢源伪随机串。由于逐段逐位的
Figure PCTCN2021102451-appb-000038
互换有概率导致工作池中‘0’、‘1’分布绝对均匀化，这将削弱再生密钥位段序列的随机性，加糖将破坏这种分布绝对均匀化。由于代谢目标分布的随机性和触发条件的间隙性，加糖处理依然能保证工作池中‘0’、‘1’分布的随机性。
2.9.12伪随机bit位转换
Figure PCTCN2021102451-appb-000039
中的伪随机bit位重排必须与伪随机bit位重排
Figure PCTCN2021102451-appb-000040
互异，这保证再生密钥位段序列的伪随机变化轨迹与工作池更替的伪随机变化轨迹之间的相互独立。
2.9.13各轮中对原始代谢源伪随机串必须使用且仅可使用一次
Figure PCTCN2021102451-appb-000041
互换。
2.9.14加糖需要间隔若干轮实施，间隔轮数需要伪随机确定。并且等概率地交替以全‘0’或全‘1’的bit串作为代谢源伪随机串。
实现了‘伪随机错位提取未被代谢的构造源bit位或者重位提取已被代谢的构造源bit位’并不能证明再生密钥位段序列实现了无限不循环。本发明采用两种措施实现再生密钥位段序列的无限不循环加密：混沌计算结构和错段叠加逻辑结构。混沌计算结构消解复重构再生密钥位段序列中有概率周期性出现重复子bits串，但是这种消解并无法被证明是彻底的。再生密钥位段序列的错段叠加逻辑结构在加密进程中进行不同再生密钥位段序列间的缠绕和过渡伪随机串空间对再生密钥位段序列空间的混沌缠绕。彻底阻断再生密钥位段序列变化的周期性。
3混沌计算结构对‘伪随机错位提取未被代谢的构造源bit位或者重位提取已被代谢的构造源bit位’效应的拓展
在固定计算结构下，产生于有限bit集的输出不能保证不出现周期性重复。同样，在固定计算结构下，‘伪随机错位提取未被代谢的构造源bit位或者重位提取已被代谢的构造源bit位’同样不能保证不周期性出现重复的再生密钥位段子序列。混沌计算结构下的bit代谢逻辑对工作池代谢的混沌效应使得由有限集获取再生密钥位段序列的过程具有混沌特性，其效应体现在：
(1)混沌计算结构造成的位段长度的伪随机变化打破了工作池被代谢位变化的规律性。
(2)当构造源起始字节循环地在工作池中逐轮递进取位时，混沌计算结构造成的位段长度的伪随机变化打破了被重复提取位周期性变化的规律性。
上述规律性的破坏源于bit位为单位处理的伪随机性，具有良好的随机性和均匀分布性。
4错段叠加逻辑结构
错段叠加逻辑结构是指：基于混沌计算结构对明文加密时的多于一个的不同再生密钥位段序列对明文 位段的错位叠加加密结构。错段叠加加密与多个再生密钥位段序列的重复加密有本质区别。它是两个或两个以上再生密钥位段序列利用混沌计算结构实现的特定逻辑缠绕加密。由于单一再生密钥位段序列本身具有混沌计算结构，它们的错段叠加产生的再生密钥位段序列的混沌缠绕效应可以达到单一再生密钥位段序列的混沌效应的幂级扩展。
参与错段叠加的再生密钥位段序列都基于相同的混沌计算结构，利用不同再生密钥位段序列间的错位和对再生密钥位段、明文位段、密文位段的同尺度切分实现加密进程中不同再生密钥位段序列的相互缠绕。这样的逻辑结构可以进一步嵌入对加密过程中过渡伪随机串(见4.5)的伪随机bit位缠绕，其实质是过渡伪随机串空间以混沌缠绕方式对再生密钥位段序列空间的拓展。
图7展示的是简单错段叠加逻辑结构。图8展示的是嵌入伪随机bit位缠绕的错段叠加逻辑结构。
结合附图7介绍简单错段叠加逻辑结构：
图7展示的是两个再生密钥位段序列的简单错段叠加逻辑结构。更多重的简单错段叠加逻辑结构同理。
4.1基于混沌计算结构的错段切分后的叠加
如图7所示，加/解密进程中基于混沌计算结构生成的两个再生密钥位段序列(k1f i||k1l i，i＝0,1,…；k2f i||k2l i，i＝0,1,…；其中‘||’为拼接符，下同)错段交替缠绕。其中再生密钥位段 bsk1 i、 bsk2 i被分别切分为两个半位段，k1f i和k1l i，k2f i和k2l i。计算中按序交错地以一个再生密钥位段序列的前半位段与另一个再生密钥位段序列的后半位段叠加加密(k1f i/k2l i-1，k1l i/k2f i)。
4.2错段切分的同步
4.2.1以混沌计算结构逐段确定ls i。
4.2.2确定切分尺度
以与位段长度限定值L min、L max相关的λ((1/2)L min≤λ<(1/2)L max)作为首再生密钥位段序列bsk1 i(i＝0,1,2,…)与次再生密钥位段序列bsk2 i(i＝0,1,2,…)之间的位差segment difference(或称sd，参见图7)。于是两个再生密钥位段序列的各位段之间存在关系：p2s i＝p1s i+sd(p1s i、p2s i分别为bsk1 ibsk2 i的起始位置)。以此sd作为首再生密钥位段序列bsk1 i(i＝0,1,2,…)的前半位段的长度l1f i，以4.2.1中的ls i计算首再生密钥位段序列bsk1 i(i＝0,1,2,…)的后半位段长度l1l i并将其作为次再生密钥位段序列bsk2 i(i＝0,1,2,…)的前半位段长度l2f i：l1l i＝l2f i＝ls i–l1f i，次再生密钥位段序列bsk2 i(i＝0,1,2,…)的后半位段长度l2l i等于首再生密钥位段序列bsk1 i(i＝0,1,2,…)的前半位段的长度l1f i。
由λ的取值公式(1/2)L min≤λ<(1/2)L max可以看出：这种错段叠加方式依然受混沌计算结构制约。
4.3不同再生密钥位段序列间的缠绕
最简单的缠绕方式是直接使用两个再生密钥位段序列的错段对应半位段对明文的两个半位段错段交替异或，这使得明文总是被不同再生密钥位段序列错段叠加加密。更复杂的缠绕见下述嵌入伪随机bit位缠绕的错段叠加逻辑结构。
4.4错段叠加逻辑结构中工作池代谢
4.4.1根据再生密钥位段序列采用的bit取位逻辑选择bit代谢逻辑：顺延提位取位逻辑使用顺延提位代谢逻辑，其它bit取位逻辑使用被提取位代谢逻辑。
4.4.2 bit代谢逻辑采用被提取位代谢逻辑和顺延提位代谢逻辑交替使用的复合形式(bit取位逻辑同样采用非顺延提位取位逻辑与顺延提位取位逻辑交替使用的复合形式)。
4.4.3采用多重错段叠加逻辑结构时，可以使用差异的bit取位逻辑和bit代谢逻辑以及差异的操控源、构造源，获取差异的代谢源以及差异的代谢目标区。可以根据加密效率要求适当降低位置链代谢重度。
结合图8介绍多次嵌入伪随机bit位缠绕的多重错段叠加逻辑结构：
图8展示的是两组各包含两个再生密钥位段序列的嵌入三次伪随机bit位缠绕的错段叠加逻辑结构。更多次嵌入伪随机bit位缠绕的更多重错段叠加逻辑结构同理。将伪随机bit位缠绕向后挪动半个密钥位段(即伪随机bit位缠绕嵌入在次再生密钥位段序列，见图9)的错段叠加逻辑结构同理。
图8省略了再生密钥位段构造、工作池代谢、及错段叠加过程中的栈调度等处理，聚焦在位段切分、同步处理、及嵌入伪随机bit位缠绕的整合。完整的多次嵌入伪随机bit位缠绕的多重错段叠加计算过程请参见图8’(为清晰展示运算次序，图8’的中间计算步仅以新计算元代替旧计算元、新计算元、计算、及其结果)。
下面参照图8介绍两组各包含多个再生密钥位段序列的多次嵌入伪随机bit位缠绕的多重错段叠加逻辑结构。
4.5利用已存在位置链实现过渡伪随机串的伪随机bit位缠绕
过渡伪随机串是指在同一轮各重加密之间前一再生密钥位段序列所生成的或者伪随机bit位缠绕的用于后一伪随机bit位缠绕的或者再生密钥位段序列计算的伪随机串。
伪随机bit位缠绕是指在一个过渡伪随机串中伪随机地进行各个bit位顺序的重新排列处理，这种处理在错段叠加逻辑结构下导致不同轮的过渡伪随机串间的进一步bit位缠绕。与bit取位逻辑的伪随机bit位重排
Figure PCTCN2021102451-appb-000042
和bit代谢逻辑的伪随机bit位转换
Figure PCTCN2021102451-appb-000043
中的伪随机bit位重排所不同的是：(1)伪随机bit位缠绕的对象是过渡伪随机串；(2)缠绕需易于可逆操作。(1)的目的是实现与不同再生密钥位段序列间缠绕的垂直方向的再缠绕；(2)的目的是保证能被解密并且不增加解密计算量。本说明书采用以位段长度等长的位置链pos_chain(ls i-L min)中顺序两两配对的位置元对指定过渡伪随机串中的bit位对进行bit值对调。
4.5.1基于混沌计算结构对明文位段、再生密钥位段、密文位段进行同尺度切分；以4.2.2中的sd确定位段切分尺度：sd，ls i-sd。
4.5.2构造分属于不同切分的两组首再生密钥位段序列和次再生密钥位段序列：组内及组间各再生密钥位段序列互不相同
4.5.2.1建立两组再生密钥位段序列；bsk1 i,q，bsk2 i,q，q＝0,1,…,s i＝0,1,…(其中q为隶属于不同组(1或2)的各再生密钥位段序列的下标，s为各组中再生密钥位段序列数，i为轮序号)。
4.5.2.2各组再生密钥位段序列中的各再生密钥位段分别遵循4.5.1中的尺度切分：k1f i,q(长度为sd)、k1l i,q(长度为ls i-sd)，k2f i,q(长度为ls i-sd)、k2l i,q(长度为sd)；对明文位段也进行同尺度切分Mf i(长度为sd)、Ml i(长度为ls i-sd)。
4.5.2.3为各再生密钥位段序列确定差异的bit取位逻辑、bit代谢逻辑、或者差异的构造源、操控源，以确保各再生密钥位段互异。
4.5.3基于同尺度切分的嵌入伪随机bit位缠绕的不同再生密钥位段序列的错段叠加加密
4.5.3.1使用长度为sd的s个缓存区存储次再生密钥位段序列组中各个后半密钥位段k2l i,q，q＝0,1,2,…,s， 用于滞后的错段加密。
4.5.3.2除首轮外(首轮中不存在k2l 0,-1，所以在次再生密钥位段序列组的错段加密时只实施k2f 0,0的半段加密)，其他轮按下述顺序错段加密(所用标识参见4.5.4.5之后的注释)：
Figure PCTCN2021102451-appb-000044
4.5.4基于同尺度切分的嵌入伪随机bit位缠绕的不同再生密钥位段序列的错段解密
解密时按加密顺序重构或提取所需计算量并完成相应代谢，然后逆序使用所得计算量进行解密计算。
4.5.4.1在混沌计算结构初始化时建立(1)长度为L max的位置链栈stack_chain，用于存储位置链；(2)长度为L max-sd的半段栈stack_k2f，用于存储s个次再生密钥位段的前半位段；(3)长度为sd的半段栈stack_k2l，用于存储下一轮错段拼接用的s个次再生密钥位段的后半位段；(4)长度为sd的错段半段栈s_stack_k2l，用于拷贝出前一轮存储在半段栈stack_k2l中的半密钥位段k2l i-1,q,以便拼接错段的次再生密钥位段k2l i-1,q||k2f i,q；(5)长度为L max的整段栈stack_bsk1，用于存储当前轮使用的首再生密钥位段。
4.5.4.2除首轮外，在各轮解密之初将前一轮压入stack_k2l的全部次再生密钥位段的后半位段拷贝进s_stack_k2l，并清空stack_k2l。
4.5.4.3除首轮外，各轮按照加密处理顺序实施s次计算量重构或提取：(1)复重构再生密钥位段bsk1 i,q并压入整段栈stack_bsk1，并进行位置链pos_chain(ls i-L min)代谢；(2)将位置链pos_chain(ls i-L min)压入位置链栈stack_chain并进行位置链pos_chain(ls i-L min)代谢；(3)复重构再生密钥位段bsk2 i,q，q＝0,1,…,s-1并压入半段栈stack_k2f、stack_k2l并进行位置链pos_chain(ls i-L min)代谢；(4)除第s次外，将位置链pos_chain(ls i-L min)压入位置链栈stack_chain并进行位置链pos_chain(ls i-L min)代谢。
4.5.4.4除首轮外，其它轮按加密逆序错段解密(所用标识参见4.5.4.5之后的注释)：
Figure PCTCN2021102451-appb-000045
4.5.4.5各轮各次解密中半位段长度使用sd或ls i-sd，略去L max-ls i的多余部分。
注释：上述(4.5.3.2)、(4.5.4.4)公式中：
Figure PCTCN2021102451-appb-000046
表示用其后指定的错段或不错段的再生密钥位段对前一步 计算产生的过渡伪随机串异或；
Figure PCTCN2021102451-appb-000047
表示以其后指定的(1)加密时使用的位置链pos_chain(r)，r＝0,1,…,2s-2实施bit位缠绕，或(2)解密时使用的位置链栈stack_chain中释放的位置链pos_chain(r)，r＝2s-2,2s-3,…,1,0解除bit位缠绕(此处r指定位置链集中的第ls i-L min位置链pos_chain(ls i-L min)的用于伪随机bit位缠绕的2s-1次代谢中第r代谢的位置链)；
Figure PCTCN2021102451-appb-000048
表示在伪随机bit位缠绕后对位置链pos_chain(ls i-L min)代谢(解密时，由于在4.5.4.3中已经完成了各个对位置链pos_chain(ls i-L min)的代谢，4.5.4.4中无需再实施对位置链pos_chain(ls i-L min)的代谢)；’；’表示一个计算步结束。
4.6嵌入伪随机bit位缠绕的错段缠绕
由图8所示伪随机bit位缠绕针对首再生密钥位段的全位段实施。由于错段效应，这种伪随机bit位缠绕分别作用于首再生密钥位段加密后的过渡伪随机串和次再生密钥位段的前一轮后半位段与当前轮前半位段错段重组的再生密钥位段加密后的过渡伪随机串，这实现在两组互异再生密钥位段序列间错段缠绕基础上的再一次前后位段间的错段缠绕。
4.7嵌入伪随机bit位缠绕的错段叠加逻辑结构中工作池代谢
4.7.1根据再生密钥位段序列采用的bit取位逻辑选择bit代谢逻辑：位跳跃取位逻辑使用被提取位代谢逻辑，顺延提位取位逻辑使用顺延提位代谢逻辑，其它bit取位逻辑使用被提取位代谢逻辑。
4.7.2在错段叠加模型中，bit代谢逻辑最好采用被提取位代谢逻辑和顺延提位代谢逻辑交替使用的混合形式(bit取位逻辑同样采用非顺延提位取位逻辑与顺延提位取位逻辑交替使用的复合形式)。
5与复重构逻辑结构相关的若干问题
5.1混沌计算结构客户化配置逻辑的关联
混沌计算结构客户化仅运行一次，其开销可以忽略不计。
对复合逻辑结构的不同客户化配置得到不同的混沌计算结构。本发明通过结构配置量及相关配置逻辑实现客户化。本节聚焦于理清这些配置逻辑单元间的承接关联：
5.1.1以结构配置量确定密钥长度，进而确定安全系统的密度及资源消耗的量级。这里列出若干有标尺意义的结构配置量，以明确密度及资源消耗的量级：512，640，768，896…。
5.1.2以结构配置量根据配置逻辑确定密钥尺寸、选取池尺寸、初始工作池尺寸、并根据初始工作池尺寸以密钥加载初始工作池。
5.1.3从工作池中根据密钥伪随机确定动态驱动向量vector 0的获取位置，并提取初始动态驱动向量vector 0。
5.1.4用初始动态驱动向量vector 0计算位段长度限定最大值L max、位段长度限定最小值L min。
5.1.5根据选取池尺寸与初始工作池尺寸之差生成伪明文pM。
5.1.6根据初始动态驱动向量vector 0生成明文结束符EOP。
5.1.7根据位段长度限定最大值L max和位段长度限定最小值L min生成位置链集pos_chain并对其初始化。
5.2存在多种对位置链集pos_chain的初始化方法，本说明书使用一种由密钥的随机性引领位置链的随机性的方法：
5.2.1设定位置链集pos_chain(j),j＝0,1,2,…,L max-L min的初值为{0,1,2,…,L min+j-1}，j＝0,1,2,…,L max-L min。
5.2.2设定位置链初始化操控量pos_init 0为初始动态驱动向量vector 0的首字节之值。
5.2.3逐j(j＝0,1,2,…,L max-L min)循环对位置链pos_chain(j)进行初始化
5.2.3.1以bit取位逻辑和bit代谢逻辑的整合中的2.7所述方法对位置链pos_chain(j)进行(pos_init j％initLmt)+3次代谢(initLmt为由vector 0的头三位bit表示的数字)。
5.2.3.2对每个j+1重置位置链初始化操控量pos_init j+1
Figure PCTCN2021102451-appb-000049
其中：
Figure PCTCN2021102451-appb-000050
为异或运算。
5.2.3.3 j＝j+1。
5.3由于伪随机bit取位逻辑的均匀分布性很高，再生密钥位段中会高概率地(约等于1/256)出现‘0’或‘F’字节，这导致在仅以单一复重构逻辑结构加密的密文中会高概率地直接输出明文字节或其反字节(明文字节与‘F’的异或)。对于嵌入伪随机bit位缠绕的错段叠加逻辑结构不存在上述问题。
实施例
本说明书选择递进取位逻辑/顺延提位代谢逻辑配套的非叠加&单代谢模型作为实施例1，选择递进链取位逻辑/顺延提位代谢逻辑和位跳跃取位逻辑/被提取位代谢逻辑配套的嵌入伪随机bit位缠绕的双叠加&双代谢的错段叠加模型作为实施例2。目的是：(1)通过实施例1说明复合逻辑结构的基本形态以及混沌计算结构与bit取位逻辑、bit代谢逻辑的关联形态；(2)通过实施例2说明复合逻辑结构的更复杂关联形态：混沌计算结构对错段叠加逻辑结构的协同作用、嵌入伪随机bit位缠绕的混沌形态。由于更多重错段叠加的计算结构同理，实施例2仅选择一次嵌入伪随机bit位缠绕的双重叠加模型。
实施例1递进取位逻辑/顺延提位代谢逻辑配置的非叠加&单代谢模型
实施例1的计算参量及计算公式(运算公式都基于实数型式)
混沌计算结构配置
1作为加/解密双方的隐秘约定，定义实施例1的结构配置量ctl init＝640，并且令密钥长度与其相等。
2定义实施例1的选取池、工作池，并定义和生成伪明文
2.1定义选取池SPool
选取池SPool满足：length(SPool)＝2*ctl init        (1)
2.2定义工作池SPool work并加载工作池SPool work
定义初始工作池SPool work满足：length(SPool work)＝ctl init
设定工作池SPool work的初始内容为密钥。
3作为加/解密双方的隐秘约定，定义实施例1的动态驱动向量vector i为选取池Spool中的子串：
Figure PCTCN2021102451-appb-000051
其中：vectstart 0为密钥首三个字节所确定的字节位置
vectstart 0＝((Spool work[0]+Spool work[1]+Spool work[2])％640)/8，
l为正整数，满足64＝l，
length(Spool work)为工作池长度，其初值为密钥长度，
Figure PCTCN2021102451-appb-000052
是由密钥中vectstart 0伪随机指定的长度为l的bits串(h到达工作池尾端后从头续延)。
Figure PCTCN2021102451-appb-000053
vectstart i为第i轮动态驱动向量在工作池中的首字节首位(到达工作池尾端后从头续延)，
vector i为第i轮动态驱动向量，
如(2’)所示动态驱动向量逐轮后移一个字节(到达工作池尾端后从头续延),
由l＝64可知vector i长度为8个bytes。
4计算实施例1的位段长度限定最大值L max、位段长度限定最小值L min
4.1计算位段长度限定最大值L max
L max＝ctl init/12+((vector 0[0]+vector 0[1])％(ctl init/128))+ctl init/128    (3)
其中：vector 0[0]、vector 0[1]为初始动态驱动向量vector 0的头两个字节。
4.2计算位段长度限定最小值L min
L min＝ctl init/12-((vector 0[2]+vector 0[3])％(ctl init/128))-ctl init/128    (4)
其中：vector 0[2]、vector 0[3]为初始动态驱动向量vector 0的第三、第四字节。
5定义实施例1的伪明文pM、明文结束符EOP
5.1根据2生成伪明文pM为长度满足length(pM)＝ctl init的伪随机串。
5.2定义明文结束符EOP为长度满足length(EOP)＝length(vector 0)的由初始工作池中的子串
Figure PCTCN2021102451-appb-000054
与初始动态驱动向量vector 0异或生成的bit串：
Figure PCTCN2021102451-appb-000055
其中：l＝length(vector 0)，
vectstart 0见3。
6定义位置链集并进行初始化
6.1定义位置链集pos_chain(j,k)，j＝0,1,2,…,L max-L min,k＝0,1,…,L min+j-1    (6)
6.2对位置链集pos_chain的初始化遵循复重构密钥的序列加密方法的说明5.2。
实施例1的加/解密计算公式及计算单元
7定义被加密明文M(rebuild plaintext)为伪明文pM、明文plaintext、明文结束符EOP、补齐伪随机串ms additn的拼接
M＝pM||plaintext||EOP||ms additn         (7)
其中：补齐伪随机串ms additn的长度为L max。
8伪随机构造实施例1的各轮加密的ls i
8.1设定首轮位段长度
ls 0＝(vector 0[2])％(L max-L min)+L min       (8)
其中：vector 0[2]为初始动态驱动向量vector 0的第三字节。
8.2定义各轮位段定长函数
ls i＝(vector i[vector i[2]％8])％(L max-L min)+L min      (8’)
9伪随机构造实施例1的再生密钥位段 bsk i
9.1定义构造源SPool work中的构造字节pickbyte i,j(计算公式以byte为单位)：
pickbyte i,0＝(pickbyte i-1,0+1)％workbyte          (9)
pickbyte 0,0＝vector 0％workbyte       (9’)
其中：vector 0为初始驱动向量，
Workbyte为以字节计算的工作池长度(下同)，
pickbyte i-1,0为上一轮首构造字节，
(9’)中pickbyte 0,0为首轮首构造字节，(9)中pickbyte i,0为其后第i轮首构造字节，pickbyte i,0在工作池SPool work中逐轮递进一个字节(到达工作池尾端后从头续延)。
pickbyte i,j＝(pickbyte i,j-1+1)％workbyte        (9”)
其中：pickbyte i,j为第i轮第j个构造字节，在工作池SPool work中逐字节递进(到达工作池尾端后从头续延)。
9.2定义构造操控值pickdriveval i,j
9.2.1定义操控源中的首操控元Pickdrivelmt i,0(计算公式以bit为单位)
pickdrivelmt 0,0＝((pickbyte 0,0+workbyte)＊8-vector 0[0])％length(Spool work)    (10)
pickdrivelmt i,0＝(pickdrivelmt i-1,0+1)％workbyte         (10’)
其中：pickdrivelmt 0,0为工作池中的一个位置，与pickbyte 0,0相差一个由密钥伪随机确定的相对位差。
9.2.2操控源中操控元序列
pickdrivelmt i,j＝(pickdrivelmt i,j-1+4)％length(Spool work),j＝0,…,ls i-1     (10”)
pickdrivelmt i,j在工作池SPool work中逐操控元以4个bits递进(到达工作池尾端后从头续延)，得到操控元序列pickdrivelmt i,j,j＝0,1,…,ls i-1。
9.2.3从操控元中提取操控值pickdriveval i,j
如果操控元pickdrivelmt i,j的最后bit位之值为‘0’则提取其前3个bits位之值作为操控值pickdriveval i,j，否则提取其后3个bits位之值作为操控值pickdriveval i,j，得到操控值序列pickdriveval i,j,j＝0,1,…,ls i-1。
9.3构造再生密钥位段 bsk i
9.3.1提取首操控值pickdriveval i,0，定位构造源的首构造字节Pickbyte i,0，清空输出伪随机串tmp_str(j)，j＝0,1,…,ls i-1。
9.3.2从当前构造字节pickbyte i,j按当前操控值pickdriveval i,j指定的bit位提取其值更新输出伪随机串中元素tmp_str(j)。
9.3.3定位到下一操控值pickdriveval i,j+1及下一构造字节pickbyte i,j+1。
9.3.4步进j＝j+1，重复上述9.3.2、9.3.3直至输出伪随机串的长度达到ls i。
9.3.5以不进行伪随机bit位重排的输出伪随机串tmp_str(j)，j＝0,1,…,ls i-1作为再生密钥位段 bsk i 。
10顺延提位代谢逻辑
10.1定义代谢目标区metabolizebyte i,j，j＝0,1,2,…,ls i-1(计算公式以byte为单位)：
metabolizebyte i,0＝pickdrivelmt i,0        (11)
metabolizebyte i,j＝(metabolizebyte i,j-1+1)％workbyte，j＝0,1,…,ls i-1    (11’)
其中：workbyte为工作池长度，以字节为单位。
metabolizebyte i,j在工作池SPool work中逐字节递进(到达工作池尾端后从头续延)。
10.2获取代谢源伪随机串metabol_str(j)(j＝0,1,2,…,ls i-1)。
10.2.1定义与再生密钥位段 bsk i 等长的代谢源伪随机串metabol_str(j)(j＝0,1,2,…,ls i-1)。
10.2.2如果与再生密钥位段等长的位置链pos_chain(ls i-L min)中pos_chain(ls i-L min,0)＝0则代谢源伪随机串metabol_str(j)＝0，(j＝0,1,2,…,ls i-1)；如果与再生密钥位段等长的位置链pos_chain(ls i-L min)中pos_chain(ls i-L min,0)＝ls i则代谢源伪随机串metabol_str(j)＝1，(j＝0,1,2,…,ls i-1)。
否则
10.2.3对原始代谢源伪随机串(即9.3.6中输出伪随机串tmp_str(j)，j＝0,1,…,ls i-1)逐个以位置链中的位置元指定的bit位之值进行
Figure PCTCN2021102451-appb-000056
互换后，拼接代谢源伪随机串metabol_str(j)＝tmp_str[pos_chain(ls i-L min,j)]，(j＝0,1,2,…,ls i-1)。
10.3以10.2所得代谢源伪随机串metabol_str对工作池中代谢目标区顺延提位代谢
10.3.1定义代谢bit位metabolbit i(0)＝0         (12)
metabolbit i(j)＝(metabolbit i(j-1)+1)％8     (12’)
10.3.2对代谢目标区的各字节中的代谢bit位代谢：
metabolizebyte i,j(metabolbit i(j))＝metabol_str(j)，j＝0,1,2,…,ls i-1   (13)
11位置链pos_chain(ls i-L min)代谢
按复重构密钥的序列加密方法的说明2.7所述方式对pos_chain(ls i-L min)代谢。
实施例1的加/解密进程操控
加密
1令结构配置量ctl init＝640。
2按上述混沌计算结构配置逐一构建选取池Spool、工作池SPool work、位段长度限定最大值L max、位段长度限定最小值L min、计算伪明文pM长度并生成伪明文pM、明文结束符EOP，并构建位置链集pos_chain。
3按实施例1的加/解密计算公式及计算单元7拼接被加密明文M，计算位段长度ls 0，并按实施例1的加/解密计算公式及计算单元8提取初始动态驱动向量vector 0。
4按实施例1的加/解密计算公式及计算单元9.2在操控源中定位首操控元pickdrivelmt i,0并提取首操控值pickdriveval i,0，定位构造源的首构造字节Pickbyte i,0，并清空输出伪随机串tmp_str(j)，j＝0,1,…,ls i-1。
5按实施例1的加/解密计算公式及计算单元9.3循环提取输出伪随机串tmp_str(j)，j＝0,1,…,ls i-1，构造再 生密钥位段 bsk i 。
6顺序从明文M提取长度为ls i的明文位段M i，并用再生密钥位段 bsk i 对明文位段M i进行异或加密。
7如果工作池未达到成熟期，则以明文位段M i(即伪明文pM i)对工作池实施成长期代谢(参见单一复重构逻辑结构1.5.5.1)；否则，按实施例1的加/解密计算公式及计算单元10用顺延提位代谢逻辑对工作池代谢。
8按复重构密钥的序列加密方法的说明2.7对位置链pos_chain(ls i-L min)代谢，vector i在工作池中后移一个字节。
9步进i＝i+1，计算ls i，如果明文位段M i的长度小于ls i则执行下述加密后处理，否则循环执行上述4至8。
10将明文的计算结束位之后的剩余bits串拼接到密文。
解密
1同加密1。
2按上述混沌计算结构配置逐一构建选取池Spool、工作池SPool work、位段长度限定最大值L max、位段长度限定最小值L min、计算伪明文pM长度、明文结束符EOP，并构建位置链集pos_chain。
3计算位段长度ls 0，并按实施例1的加/解密计算公式及计算单元8提取初始动态驱动向量vector 0。
4按实施例1的加/解密计算公式及计算单元9.2在操控源中定位首操控元pickdrivelmt i,0并提取首操控值pickdriveval i,0，定位构造源的首构造字节Pickbyte i,0，并清空输出伪随机串tmp_str(j)，j＝0,1,…,ls i-1。
5按实施例1的加/解密计算公式及计算单元9.3循环提取输出伪随机串tmp_str(j)，j＝0,1,…,ls i-1，构造再生密钥位段 bsk i 。
6顺序从密文C提取长度为ls i的密位段C i，并用再生密钥位段 bsk i 对密文位段C进行异或解密。
7如果工作池未达到成熟期，则以解密所得明文位段M i(即伪明文pM i)对工作池实施成长期代谢(参见单一复重构逻辑结构1.5.5.1)，否则按实施例1的加/解密计算公式及计算单元10用顺延提位代谢逻辑对工作池代谢。
8按复重构密钥的序列加密方法的说明2.7对位置链pos_chain(ls i-L min)代谢，vector i在工作池中后移一个字节。
9步进i＝i+1，计算ls i，如果密文位段C i的长度小于ls i则执行下述解密后处理，否则循环执行上述4至8。
9.1剔除解密所得的明文中的伪明文pM。
9.2在解密所得明文的尾部的倒序L max+length(vector 0)的位置比对明文结束符EOP，如果找到则剔除明文结束符EOP及随后的补齐伪随机串ms additn；如果找不到明文结束符EOP则说明加密、传输、解密过程中出现错误。
实施例2递进链取位逻辑/顺延提位代谢逻辑和位跳跃取位逻辑/被提取位代谢逻辑配套的嵌入伪随机bit位缠绕的双叠加&双代谢错段叠加模型
由于本实施例的各再生密钥位段序列组中仅使用了一个再生密钥位段序列(s＝1，参见错段叠加逻辑结构4.5)，本实施例将再生密钥位段序列组标识(bsk1 i,q、bsk2 i,q中的1、2，参见错段叠加逻辑结构4.5)和组中再生密钥位段序列子标示(bsk1 i,q、bsk2 i,q中的q，参见错段叠加逻辑结构4.5)合并成‘1’或‘2’， 并且以单缓存区代替栈。
实施例2的计算参量及计算公式
混沌计算结构配置
同实施例1的混沌计算结构配置之1～6。
实施例2的加/解密计算公式及计算单元
7同实施例1的加/解密计算公式及计算单元7。
8同实施例1的加/解密计算公式及计算单元8。
9伪随机构造首再生密钥位段序列的再生密钥位段 bsk1：
9.1定义首再生密钥位段序列的构造源pickarea1 i中的构造字节pickbyte1 i,j(计算公式以byte为单位)
9.1.1定义首再生密钥位段序列的构造源pickarea1 i
9.1.1.1定义首再生密钥位段序列的构造源在工作池SPool work中的起始字节位置：
pickarea1start 0＝vector 0％workbyte          (14)
pickarea1start i＝(pickarea1start i-1+1)％workbyte        (14’)
(14)为首轮构造源在工作池SPool work中的起始字节位置，(14’)为其它轮构造源在工作池SPool work中的起始字节位置。
9.1.1.2定义首再生密钥位段序列的构造源pickarea1 i：
Figure PCTCN2021102451-appb-000057
(15)为从pickarea1start i开始的ls i个字节(h以字节进位，到达工作池尾端从头续延)所构成的构造源。
9.1.2定义首再生密钥位段序列的构造字节序列pickbyte1 i,j，j＝0,1,…,ls i-1：
pickbyte1 i,j＝pickarea1 i(pos_chain(ls i-L min,j))％workbyte，j＝0,1,…,ls i-1    (16)
其中：pos_chain(ls i-L min,j)为与位段长度等长的位置链pos_chain(ls i-L min)中第j个位置元。
9.2同实施例1的加/解密计算公式及计算单元9.2。
9.3构造首再生密钥位段序列的再生密钥位段 bsk1 i
9.3.1从首再生密钥位段序列的首操控元pickdrivelmt1 i,0按实施例1的加/解密计算公式及计算单元9.2.3的方法提取首操控值pickdriveval1 i,0，并清空输出伪随机串tmp_str(j)，j＝0,1,…,ls i-1。
9.3.2从当前构造字节pickarea1 i(j)按当前操控值pickdriveval1 i,j指定的bit位，提取其值更新输出伪随机串中的元素tmp_str(j)。
9.3.3将当前操控元pickdrivelmt1 i,j向后移动4个bits作为下一操控元pickdrivelmt1 i,j+1，并按(16)定位到下一构造字节。
9.3.4按实施例1的加/解密计算公式及计算单元9.2.3的方法提取下一操控值pickdriveval1 i,j。
9.3.5步进j＝j+1，重复上述9.3.2、9.3.3、9.3.4直至j＝ls i-1，得到输出伪随机串tmp_str(j)，j＝0,1,…,ls i-1。
9.3.6依输出伪随机串tmp_str(j)，j＝0,1,…,ls i-1进行伪随机bit位重排，并将结果作为首再生密钥位段序列的再生密钥位段 bsk1 i 。
10同实施例1的加/解密计算公式及计算单元10(代谢目标为首再生密钥位段序列的代谢目标区)。
11同实施例1的加/解密计算公式及计算单元11。
12伪随机构造实施例2的次再生密钥位段序列的再生密钥位段 bsk2 i
12.1确定实施例2的次再生密钥位段序列构造源pickarea2 i和操控源pickdrivearea2 i
12.1.1由动态驱动向量vector i伪随机确定次再生密钥位段序列的构造源起始位置:
pickstart2 i,0＝vector i[2]％length(Spool work)
12.1.2构造源pickarea2 i由从构造源起始位置pickstart2 i,0到选取池尾部的bits串和从选取池首部到构造源起始位置pickstart2 i,0之前的两个bits串拼接而成。
12.1.3由动态驱动向量vector i伪随机确定次再生密钥位段序列的操控源起始位置:
pickdrivstart2 i,0＝(pickstart2 i,0+length(Spool work)-vector i[4]-1)％length(Spool work)
12.1.4操控源pickdrivearea2 i由从操控源起始位置pickdrivstart2 i,0到选取池尾部的bits串和从选取池首部到操控源起始位置pickdrivstart2 i,0之前的两个bits串拼接而成。
12.2从操控源起始位置pickdrivstart2 i,0开始顺序(顺延至工作池尾部后从头续延)提取ls i个长度为log 2(workbyte＊8/l max))+1的bits串构成位跳跃值序列jump2_num(j)，j＝1,2,…,ls i-1。
12.3令j＝0，并清空输出伪随机串tmp_str(j)，j＝0,1,…,ls i-1。
12.4使用公式pickbit 0＝pickstart2 i,0，pickbit j＝(pickbit j-1+jump2_num(j))％length(Spool work)，j＝1,…,ls i-1，得到ls i个构造源中的bit位串pickbit j，j＝0,1,…,ls i-1，提取其各个bit位之值构成输出伪随机串tmp_str(j)，j＝0,1,…,ls i-1。
12.5使用单一复重构逻辑结构1.5.3的方法对输出伪随机串tmp_str(j)，j＝0,1,…,ls i-1进行伪随机bit位重排，得到次再生密钥位段序列的再生密钥位段 bsk2 i 。
13被提取位代谢逻辑
13.1在12.4中保留各pickbit j，j＝0,1,…,ls i-1作为被提取位代谢目标区。
13.2使用位置链pos_chain(ls i-L min,j)(j＝0,1,2,…,ls i-1)对12.4所得输出伪随机串tmp_str(j)，j＝0,1,…,ls i-1进行伪随机bit位转换
Figure PCTCN2021102451-appb-000058
获取代谢源伪随机串metabol_str(j)(j＝0,1,2,…,ls i-1)：
13.2.1定义与再生密钥位段 bsk2 i 等长的代谢源伪随机串metabol_str(j)(j＝0,1,2,…,ls i-1)。
13.2.2如果与再生密钥位段 bsk2 i 等长的位置链pos_chain(ls i-L min)中pos_chain(ls i-L min,0)＝0则代谢源伪随机串metabol_str(j)＝0，(j＝0,1,2,…,ls i-1)；如果与再生密钥位段等长的位置链pos_chain(ls i-L min)中pos_chain(ls i-L min,0)＝ls i-1则代谢源伪随机串metabol_str(j)＝1，(j＝0,1,2,…,ls i-1)。
否则
13.2.3逐个以位置链中的位置元指定的输出伪随机串中相应位置的bit位之值进行
Figure PCTCN2021102451-appb-000059
互换后，拼接代谢源伪随机串metabol_str(j)＝tmp_str[pos_chain(ls i-L min,j)]，(j＝0,1,2,…,ls i-1)。
13.3逐一以代谢源伪随机串metabol_str(j)(j＝0,1,2,…,ls i-1)对被提取位代谢目标位(即被提取位)pickbit j，j＝0,1,…,ls i-1代谢：pickbit i(j)＝metabol_str(j)(j＝0,1,2,…,ls i-1)。
14确定位段切分值为(1/2)L min，并设定切分公式
14.1首再生密钥位段序列的上半位段及次再生密钥位段序列的下半位段的长度：
L1f i＝L2l i＝(1/2)L min；
首再生密钥位段序列的下半位段及次再生密钥位段序列的上半位段的长度：
L1l i＝L2f i＝ls i-(1/2)L min。
于是有：
14.2切分后的半位段(或称半段)标示(参见图8)：
明文前/后半位段Mf i，Ml i，(明文前、后半位段)
首密钥前/后半位段K1f i，K1l i，(首再生密钥位段序列的再生密钥位段的前、后半位段)
次密钥前/后半位段K2f i,K2l i，(次再生密钥位段序列的再生密钥位段的前、后半位段)
首过渡前/后半位段T1f i，T1l i，(首再生密钥位段序列加密后的前、后半位段)
缠绕的过渡前/后半位段T1f iX，T1l iX，(首再生密钥位段序列加密后并实施伪随机bit位缠绕的前/后半位段)
次过渡前/后半位段T1f iX2l i-1，T1l iX2f i(实施伪随机bit位缠绕后用次再生密钥位段序列加密的前/后半位段)
密文前/后半位段Cf i，Cl i，(密文前、后半位段)
实施例2的加/解密进程操控
本实施例中只嵌入一次伪随机bit位缠绕，所以省略用于倒序处理的栈(stack_k2f、stack_k2l、s_stack_k2l、stack_bsk1、stack_chain，见图8’-2)。
加密
1按上述混沌计算结构配置1令结构配置量ctl init＝640。
2按上述混沌计算结构配置构建动态驱动向量vector 0、选取池Spool、工作池SPool work、位段长度限定最大值L max、位段长度限定最小值L min、伪明文pM、明文结束符EOP、位置链集pos_chain。
3按实施例2的加/解密计算公式及计算单元生成被加密明文M＝pM||plaintext||EOP||ms additn；计算位段长度ls 0。
4从被加密明文M提取长度为位段长度ls 0的明文位段M 0(Mf 0||Ml 0)。
5按实施例2的加/解密计算公式及计算单元9构造首再生密钥位段序列的首再生密钥位段 bsk1 0 (K1f 0||K1l 0)。按实施例2的加/解密计算公式及计算单元12构造次再生密钥位段序列的首再生密钥位段 bsk2 0 (K2f 0||K2l 0)。以明文位段M 0(即伪明文pM 0)对工作池实施成长期代谢(参见单一复重构逻辑结构1.5.5.1)。
6按实施例2的加/解密计算公式及计算单元11实施位置链pos_chain(ls 0-L min)代谢。
7将次再生密钥位段序列的首再生密钥位段 bsk2 0 的后半段k2l 0存入缓存queue2l。
8以首再生密钥位段序列的首再生密钥位段 bsk1 0 对明文位段M 0进行异或加密生成首过渡位段T1f 0||T1l 0。
9以位置链pos_chain(ls 0-L min)对首过渡位段T1f 0||T1l 0伪随机bit位缠绕，生成重排的过渡位段T1f 0X||T1l 0X。
10按实施例2的加/解密计算公式及计算单元11对位置链pos_chain(ls i-L min)代谢。
11以次密钥后半位段K2f 0加密重排的过渡后半位段T1l 0X，生成次过渡后半位段T1l 0X2f 0。
12 i＝i+1，计算下一ls i。
13提取动态驱动向量vector i，从被加密明文M顺延提取长度为ls i的明文位段M i。
14将queue2l拷贝进q_queue2l，并将queue2l清空。
15按实施例2的加/解密计算公式及计算单元9构造首再生密钥位段序列的再生密钥位段 bsk1 i (K1f i||K1l i)，若工作池达到成熟期则按实施例2的加/解密计算公式及计算单元10使用所提取的输出伪随机串实施顺延提位代谢；按实施例2的加/解密计算公式及计算单元12构造次再生密钥位段序列的再生密钥位段 bsk2 i (K2f i||K2l i)，若工作池达到成熟期则按实施例2的加/解密计算公式及计算单元13使用所提取的输出伪随机串实施被提取位代谢。如果工作池未达到成熟期，则以明文位段M i(即伪明文pM i)对工作池实施成长期代谢(参见单一复重构逻辑结构1.5.5.1)。
16按实施例2的加/解密计算公式及计算单元11实施位置链pos_chain(ls i-L min)代谢。
17以首再生密钥位段序列的再生密钥位段 bsk1 i 对M i计算得到首过渡位段T1f i||T1l i。
18对首过渡位段T1f i||T1l i以位置链pos_chain(ls i-L min)的位置序进行伪随机bit位缠绕生成缠绕的过渡位段T1f iX||T1l iX。
19对位置链pos_chain(ls i-L min)代谢。
20从缓存q_queue2l中提取前一轮次再生密钥位段后半段k2l i-1，错段重组再生密钥位段k2l i-1||k2f i，并用其对T1f iX||T1l iX进行加密生成错段次过渡位段T1f iX2l i-1||T1l iX2f i(即本实施例的密文位段)。
21将本轮生成的次再生密钥位段序列的再生密钥位段的后半段k2l i存入缓存queue2l。
22 i＝i+1，计算下一ls i，并做循环条件判断：
22.1如果ls i大于未加密明文的长度则进行加密后处理23并结束计算。
22.2否则，执行13至22，进行下一轮嵌入伪随机bit位缠绕的错段叠加计算直至22.1的条件成立。
23将22.1中未加密剩余明文追加到密文尾端。
解密
由于在加密进程中嵌入了伪随机bit位缠绕过程，解密处理必须在提取完再生密钥位段和解除伪随机bit位缠绕使用的位置链pos_chain(ls i-L min)后按加密倒序进行处理：
1同加密进程1、2，配置结构操控量：动态驱动向量vector 0、选取池Spool、工作池SPool work、位段长度限定最大值L max、位段长度限定最小值L min、伪明文pM长度、明文结束符EOP、位置链集pos_chain。
2令i＝0，计算位段长度ls 0。
3从密文C提取长度为位段长度ls 0的密文位段C 0(Cf 0||Cl 0)。
4构造首再生密钥位段序列的再生密钥位段 bsk1 0 (K1f 0||K1l 0)；构造次再生密钥位段序列的再生密钥位段 bsk2 0 (K2f 0||K2l 0)。以明文位段M 0(即伪明文pM 0)对工作池实施成长期代谢(参见单一复重构逻辑结构1.5.5.1)。
5按实施例2的加/解密计算公式及计算单元11实施位置链pos_chain(ls i-L min)代谢。
6将次再生密钥位段序列的再生密钥位段的后半段k2l 0存入stack_k2l。
7以次密钥前半位段k2f 0对密文后半位段Cl 0进行异或，得到加密时被重排的过渡后半位段T1l 0X。
8用7中所得T1l 0X与密文前半位段Cf 0拼接，得到重排的过渡位段T1f 0X||T1l 0X，并以位置链pos_chain(ls 0-L min)的位置序进行伪随机bit位解除缠绕，得到首过渡位段T1f 0||T1l 0。
9对位置链pos_chain(ls 0-L min)代谢。
10以首再生密钥位段序列的再生密钥位段 bsk1 0 对所得过渡位段T1f 0||T1l 0解密得到明文位段Mf 0||Ml 0。
11 i＝i+1，并计算ls i，提取动态驱动向量vector i。
11.1如果ls i大于未加密明文的长度，则进行22解密后处理。
11.2否则，从密文C提取长度为ls i的密文位段C i(Cf i||Cl i)。
12拷贝stack_k2l到s_stack_k2l，并清空stack_k2l。
13按实施例2的加/解密计算公式及计算单元9构造首再生密钥位段序列的再生密钥位段 bsk1 i (K1f i||K1l i)，若工作池达到成熟期则按实施例2的加/解密计算公式及计算单元10使用所提取的输出伪随机串实施顺延提位代谢；按实施例2的加/解密计算公式及计算单元12构造次再生密钥位段序列的再生密钥位段 bsk2 i (K2f i||K2l i)，若工作池达到成熟期则按实施例2的加/解密计算公式及计算单元13使用所提取的输出伪随机串实施被提取位代谢。
14按实施例2的加/解密计算公式及计算单元11实施位置链pos_chain(ls i-L min)代谢。
15将次再生密钥位段序列的再生密钥位段的后半段k2l i存入stack_k2l。
16错段重组再生密钥位段k2l i-1||k2f i，然后对密文位段C i(Cf i||Cl i)解密计算，得到加密时被重排的过渡位段T1f iX||T1l iX。
17以位置链pos_chain(ls i-L min)对T1f iX||T1l iX解除伪随机bit位缠绕，得到首过渡位段T1f i||T1l i。
18对位置链pos_chain(ls i-L min)代谢。
19以首再生密钥位段序列的再生密钥位段 bsk1 i 对所得首过渡位段T1f i||T1l i解密得到明文位段Mf i||Ml i。
20如果工作池未达到成熟期，则以解密所得的明文位段M i(即伪明文pM i)对工作池实施成长期代谢(参见单一复重构逻辑结构1.5.5.1)。
21重复11至20步骤进行下一轮嵌入伪随机bit位缠绕的解密计算直至ls i大于未被解密的密文的长度。
22解密后处理
22.1剔除解密所得的明文中的伪明文pM。
22.2效验解密所得明文中的明文结束符EOP是否正确，如果明文结束符EOP正确则剔除明文结束符EOP及随后的补齐伪随机串ms additn；如果明文结束符EOP不正确则说明加密、传输、解密过程中出现错误。
发明特征说明
1采用无限不循环的再生密钥位段序列构造机制实施错段叠加加密，安全性得到充分保证。由于底层循环中以bit位计算为主，本发明实现速度也可以得到保证。
2相较于传统的序列加密方法本发明可以根据应用形态的需要配置相应的加密模型，应用范围更加广阔。并且具有一定的可调整空间和与其它方法的整合空间。
3由于结构配置量可以根据需要调整，本发明可以适应计算能力不断增长的安全需要。可以证明的是：除蛮力攻击密钥外，不存在破解密钥的多项式时间复杂度的攻击算法，即本发明提供一个P<nP的实例。
可以理解的是，对本领域技术人员来说，对本发明的技术方案及发明构思加以等同替换、改变或简化都应属于本发明所附权利要求的保护范围。

Claims (8)

  1. 一种复重构密钥的序列加密方法，其特征在于：使用密钥和结构配置量生成结构操控量，并利用结构操控量操控混沌计算结构调度配套的复合逻辑实现混沌的bit位段流序列加密；逐轮伪随机重构构造源和操控源并利用操控源伪随机操控构造源复重构再生密钥位段；利用对多于一个的再生密钥位段序列的整合实现不同再生密钥位段序列间错段缠绕；利用伪随机bit位缠绕实现与再生密钥位段序列间错段缠绕不相关的前后位段间的错段缠绕；发明核心包括三个紧密关联的计算：(A)构建混沌计算结构，在加密进程中逐段对工作池新陈代谢，进而对工作池承载的操控源、构造源逐段以操控源中的bit位操控bit取位逻辑提取构造源中的bit位，伪随机复重构再生密钥位段；(B)基于混沌计算结构，整合bit取位逻辑和bit代谢逻辑，构建‘伪随机错位提取未被代谢的构造源bit位或者重位提取已被代谢的构造源bit位’的再生密钥位段无限不循环构建逻辑；(C)基于混沌计算结构对多于一个的不同再生密钥位段序列实现错段叠加加密；技术方案包括：
    (1)由密钥通过计算结构配置量构建混沌计算结构，支撑伪随机确定各段计算参量的逐位段序列加密；
    (2)以密钥加载初始工作池，引领逐位段逻辑缠绕的混沌加密进程；
    (3)以加密方独立构建的伪明文扩展工作池，进一步混沌加密进程，提升安全阀值；
    (4)建立工作池逐轮代谢机制，配套配置bit取位逻辑和bit代谢逻辑，建立‘伪随机错位提取未被代谢的构造源bit位或者重位提取已被代谢的构造源bit位’的再生密钥位段构建逻辑；
    (5)以混沌计算结构消解所构建的再生密钥位段序列的有概率出现的周期律；
    (6)使用差异的构造源、操控源、bit取位逻辑和bit代谢逻辑，构造不同的再生密钥位段序列，并基于混沌计算结构实现不同再生密钥位段序列的嵌入伪随机bit位缠绕的错段叠加加密；
    (7)基于密钥建立明文结束符，化解明文结束位置与分段计算结束位置之间的错位并以明文结束符作为解密计算正确性的效验码。
  2. 根据权利要求1所述的复重构密钥的序列加密方法，其特征在于：由密钥通过结构配置量配置结构操控量，操控混沌的不定长分段加密计算：
    (1)使用密钥key结合结构配置量ctl init配置选取池Spool的长度，初始工作池Spool work的长度；
    (2)根据密钥伪随机确定初始动态驱动向量vector 0在工作池Spool work中的提取位置；
    (3)根据选取池Spool的长度和密钥的长度确定伪明文pM的长度；
    (4)根据初始动态驱动向量vector 0伪随机确定位段长度限定最大值L max、位段长度限定最小值L min；
    (5)根据初始动态驱动向量vector 0和密钥中其它bits串生成明文结束符EOP；
    (6)根据位段长度限定最大值L max及位段长度限定最小值L min构建位置链集pos_chain；
    (7)拼接伪明文pM、明文plaintext、明文结束符EOP，并追加长度为L max的补齐伪随机串ms additn，重构计算用明文M；
    (8)通过上述(1)至(6)所得结构操控量操控混沌计算结构加密被重构的明文M。
  3. 根据权利要求1所述的复重构密钥的序列加密方法，其特征在于：使用密钥key初始加载工作池SPool work，启动再生密钥位段序列的构建进程。
  4. 根据权利要求1所述的复重构密钥的序列加密方法，其特征在于：以加密方独立构建的与明文内容无关的伪明文pM扩展工作池SPool work；进而以密钥key和伪明文pM共同引领复重构再生密钥位段序列的进程，提升安全阀值。
  5. 根据权利要求1所述的复重构密钥的序列加密方法，其特征在于：依据计算结构的配置逐轮使用bit代谢逻辑代谢工作池SPool work，进而以操控源操控bit取位逻辑提取构造源的bit值，实现‘伪随机错位提取未被代谢的构造源bit位或者重位提取已被代谢的构造源bit位’的逐bit位复重构再生密钥位段逻辑；
    (1)以bit代谢逻辑实现工作池代谢，以bit取位逻辑从工作池中复重构再生密钥位段；
    (2)所列举的bit取位逻辑：
    (2.1)递进取位逻辑；
    以初始动态驱动向量vector 0伪随机确定首轮构造源在工作池中的起始字节pickstart 0,0；
    以初始动态驱动向量vector 0伪随机获取相对位差dif，dif<length(Spool work)，在工作池中确定首轮操控源起始位置pickdrivstart 0,0＝(pickstart 0,0+length(Spool work)-dif)％length(Spool work)；
    逐轮递进一个字节，到达工作池Spool work尾端后从头续延，确定随后各轮:①构造源起始字节pickstart i,0＝(pickstart i-1,0+8)％length(Spool work)，②操控源起始位置pickdrivstart i,0＝(pickdrivstart i-1,0+8)％length(Spool work)；
    以工作池中从构造源起始字节开始的ls i个字节构成的字节段作为各轮构造源pickarea i；
    以工作池中从操控源起始位置开始的ls i的n倍个bit构成的bits串作为操控源pickdrivearea i，n为3或4或8；
    以操控源pickdrivearea i中顺序地每3或4或8个bits构成的bits串序列构成操控元序列，并提取各操控元中3个bits作为操控值构成操控值序列pickdriver i(j)，j＝0,1,2,…,ls i-1；
    顺序地配对操控值序列中的操控值和构造源中的构造字节pickdriver i(j)/pickarea i(j)，j＝0,1,2,…,ls i-1；
    逐对从操控值指定的构造字节的bit位之值作为输出bit值，拼接输出伪随机串tmp_str(j)，j＝0,1,2,…,ls i-1；
    使用所构造的输出伪随机串tmp_str(j)，j＝0,1,2,…,ls i-1，或对其进行伪随机bit位重排
    Figure PCTCN2021102451-appb-100001
    后，作为再生密钥位段 bsk i；
    (2.2)递进链取位逻辑；
    在配置混沌计算结构时，以位段长度限定最大值L max及位段长度限定最小值L min构建位置链集pos_chain并以密钥对其初始化；
    在工作池中以初始动态驱动向量vector 0伪随机确定首轮构造源起始字节pickstart 0,0；
    以初始动态驱动向量vector 0伪随机获取相对位差dif，dif<length(Spool work)，在工作池中确定首轮操控源起始位置pickdrivstart 0,0＝(pickstart 0,0+length(Spool work)-dif)％length(Spool work)；
    逐轮递进一个字节，到达工作池Spool work尾端后从头续延，确定随后各轮中:①构造源起始字节pickstart i,0＝(pickstart i-1,0+8)％length(Spool work)，②操控源起始bit位pickdrivstart i,0＝(pickdrivstart i-1,0 +8)％length(Spool work)；
    以工作池中从构造源起始字节开始的ls i个字节构成的字节段作为构造源pickarea i；
    以工作池中从操控源起始位置开始的ls i的n，n为3或4或8，倍个bit所组成的bits串作为操控源pickdrivearea i；
    以操控源pickdrivearea i中顺序地每3或4或8个bit构成的bits串作为操控元构成操控元序列，并提取操控元中3个bits作为操控值构成操控值序列pickdriver i(j)，j＝0,1,2,…,ls i-1；
    顺序地配对操控值序列中的操控值和由位置链pos_chain(ls i-L min)中位置元pos_chain(ls i-L min,j)确定的构造源中的构造字节pickdriver i(j)/pickarea i(pos_chain(ls i-L min,j))，j＝0,1,2,…,ls i-1；
    逐对以操控值指定的构造字节中的bit位之值作为输出bit值，拼接输出伪随机串tmp_str(j)，j＝0,1,2,…,ls i-1；
    使用所构造的输出伪随机串tmp_str(j)，j＝0,1,2,…,ls i-1或对其进行伪随机bit位重排
    Figure PCTCN2021102451-appb-100002
    后，作为再生密钥位段 bsk i；
    (2.3)位跳跃取位逻辑；
    以动态驱动向量vector i伪随机确定各轮构造源起始位置pickstart i,0，并以构造源起始位置pickstart i,0到工作池尾端的bits串与从工作池头端到构造源起始位置pickstart i,0之前的bits串拼接构造源pickarea i；
    以动态驱动向量vector i伪随机获取相对位差dif，dif≤length(Spool work)，在工作池中确定各轮操控源起始位置pickdrivstart i,0＝(pickstart i,0+length(Spool work)-dif)％length(Spool work)，并以操控源起始位置pickdrivstart i,0到工作池尾端的bits串与从工作池头端到操控源起始位置pickdrivstart i,0之前的bits串拼接操控源pickdrivearea i；
    从操控源中跳跃或不跳跃地提取ls i个定长bits子串作为位跳跃值构成位跳跃值序列junp_num(j)，j＝0,1,2,…,ls i-1，到达工作池尾部后从头续延；
    逐一，j＝0,1,2,…,ls i-1，依位跳跃值序列中的各位跳跃值为间隔从构造源中跳跃地，到达工作池尾部后从头续延，确定被提取bit位，并以其值拼接输出伪随机串tmp_str(j)，j＝0,1,2,…,ls i-1；
    使用所构造的输出伪随机串tmp_str(j)，j＝0,1,2,…,ls i-1或对其进行伪随机bit位重排
    Figure PCTCN2021102451-appb-100003
    后，作为再生密钥位段 bsk i；
    (2.4)顺延提位取位逻辑：
    由初始动态驱动向量vector 0伪随机确定首轮构造源起始字节pickstart 0；随后各轮构造源起始字节pickstart i逐轮顺延一个字节，顺延到达工作池尾端从头续延，pickstart i＝(pickstart i-1+8)％length(Spool work)；
    各轮中构造源pickarea i由从构造源起始字节pickstart i开始顺延的ls i个字节构成，顺延到达工作池尾端从头续延；
    令上述构造源pickarea i中首构造字节的被提取bit位为第0 bit位，随后构造字节的被提取bit位逐字节 提高一个bit位，达到7后从0续延，顺序地以构造字节的被提取bit位之值拼接输出伪随机串tmp_str(j)，j＝0,1,2,…,ls i-1；
    使用所构造的输出伪随机串tmp_str(j)，j＝0,1,2,…,ls i-1或对其进行伪随机bit位重排
    Figure PCTCN2021102451-appb-100004
    后，作为再生密钥位段 bsk i；
    (3)所列举的bit代谢逻辑及其相关代谢：
    (3.1)对length(SPool work)<length(SPool)的成长期中的工作池SPool work的代谢：
    当length(Spool)-length(Spool work)≥ls i时，加密时追加或伪随机插入从明文中依序提取的长度为ls i的伪明文子串pM i到工作池SPool work并维护工作池SPool work长度length(Spool work)＝length(Spool work)+ls i；解密时追加或伪随机插入从被解密明文中提取的长度为ls i的伪明文子串pM i到工作池SPool work并维护工作池SPool work长度length(Spool work)＝length(Spool work)+ls i；
    当length(Spool)-length(Spool work)<ls i时，加密时追加或伪随机插入从明文中依序提取的长度为length(Spool)-length(Spool work)的伪明文子串pM i到工作池SPool work并且令length(Spool work)＝length(Spool)；解密时追加或伪随机插入从被解密明文中提取的长度为length(Spool)-length(Spool work)的伪明文子串pM i到工作池SPool work并且令length(Spool work)＝length(Spool)；工作池达到成熟期；
    (3.2)对length(SPool work)＝length(SPool)的工作池SPool work成熟期，采用bit代谢逻辑代谢工作池：(3.2.1)顺延提位代谢逻辑：
    在工作池中从操控源起始位置pickdrivstart i,0起选取ls i个字节构成顺延提位代谢目标区metabolarea i；顺延提位代谢目标区metabolarea i在工作池中逐轮后移一个字节，到达工作池尾端从头续延；
    使用位置链pos_chain(ls i-L min)对原始代谢源随机串，即任意bit取位逻辑的输出伪随机串tmp_str(j)，j＝0,1,2,…,ls i-1，进行伪随机bit位转换
    Figure PCTCN2021102451-appb-100005
    其中的伪随机bit重排必须与构造再生密钥位段时的伪随机bit位重排
    Figure PCTCN2021102451-appb-100006
    互异，得到代谢源随机串metabolsrc i(j)，j＝0,1,2,…,ls i-1；
    设定在顺延提位代谢目标区metabolarea i首字节中的代谢bit位为第0 bit位，随后逐字节提高一个bit位，达到7后从0续延，作为顺延提位目标区各字节的代谢bit位，得到被代谢bit位序列metabolbit i(j)，j＝0,1,2,…,ls i-1；
    按序逐bit位以代谢源随机串metabolsrc i(j)，j＝0,1,2,…,ls i-1的bit位之值替换顺延提位目标区相应字节的代谢bit位之值metabolbit i(j)＝metabolsrc i(j)，j＝0,1,2,…,ls i-1；
    (3.2.2)被提取位代谢逻辑：
    在任何bit取位逻辑构建输出伪随机串tmp_str(j)，j＝0,1,2,…,ls i-1时，顺序拼接其bit位作为被提取位序列pickedbit i(j)，j＝0,1,2,…,ls i-1；
    使用位置链pos_chain(ls i-L min)对原始代谢源伪随机串，即任意bit取位逻辑的输出伪随机串tmp_str(j)，j＝0,1,2,…,ls i-1，进行伪随机bit位转换
    Figure PCTCN2021102451-appb-100007
    其中的伪随机bit重排必须与构造再生密钥位段时的伪随机bit位重排
    Figure PCTCN2021102451-appb-100008
    互异，得到代谢源伪随机串metabolsrc i(j)，j＝0,1,2,…,ls i-1；
    实施被提取位代谢pickedbit i(j)＝metabolsrc i(j)，j＝0,1,2,…,ls i-1；
    (3.3)利用密钥的随机性实现位置链pos_chain(ls i-L min)代谢：
    建立长度为(1/2)length(vector i)-1的空过渡位置链tmp_chain；
    顺序提取动态驱动向量vector i的每两个bits所表示之值作为跳跃值得到一个跳跃值序列rp j，j＝0,1,…,min((1/2)length(vector i)-1,ls i-1)；
    令p 0＝rp 0，p j＝p j-1+rp j+1，
    计算：①tmp_chain(j)＝pos_chain(ls i-L min,p j)并②剔除位置元pos_chain(ls i-L min,p j)，j＝0,1,…,(1/2)length(vector i)-1；于是pos_chain(ls i-L min)部分或全部地伪随机导入tmp_chain；
    当(1/2)length(vector i)<ls i时，将新位置链tmp_chain中生成的(1/2)length(vector i)个位置元追加到被压缩了的位置链pos_chain(ls i-L min)的尾端；当(1/2)length(vector i)≥ls i时，以新位置链tmp_chain替换已使用位置链pos_chain(ls i-L min)；
    (3.4)对动态驱动向量vector i以下述两者之一代谢
    (3.4.1)以在工作池中逐轮向后顺延一个字节的方式实现动态驱动向量vector i代谢；
    (3.4.2)逐轮以工作池中与前一轮动态驱动向量vector i-1互异的等长bits串与前一轮动态驱动向量vector i-1异或生成新的vector i；
    (4)在生成再生密钥位段前对输出伪随机串的伪随机bit位重排
    Figure PCTCN2021102451-appb-100009
    在工作池代谢之前对原始代谢源伪随机串，即任意bit取位逻辑的输出伪随机串tmp_str(j)，j＝0,1,2,…,ls i-1，的伪随机bit位转换
    Figure PCTCN2021102451-appb-100010
    (4.1)基于位置链pos_chain(ls i-L min)的随机性对由bit取位逻辑获取的输出伪随机串tmp_str(j)，j＝0,1,2,…,ls i-1，实现伪随机bit位重排
    Figure PCTCN2021102451-appb-100011
    (4.2)基于位置链pos_chain(ls i-L min)的随机性实现对原始代谢源伪随机串，即任意bit取位逻辑的输出伪随机串tmp_str(j)，j＝0,1,2,…,ls i-1，的伪随机bit位转换
    Figure PCTCN2021102451-appb-100012
    包括：
    (4.2.1)基于位置链pos_chain(ls i-L min)的随机性对原始代谢源伪随机串，由任意bit取位逻辑获取的输出伪随机串tmp_str(j)，j＝0,1,2,…,ls i-1，实施与(4.1)不同的伪随机bit位重排；
    (4.2.2)在实施(4.2.1)的伪随机bit位重排时逐bit位
    Figure PCTCN2021102451-appb-100013
    互换；
    (4.2.3)加糖：根据计算参量间隙性出现的状态触发以全‘0’或全‘1’的bit串替代代谢源伪随机串；计算参量间隙性出现的状态的例子：(a)、位置链中特定位置的位置元等于0或ls i，或者(b)、动态驱动向量vector i的某确定字节之值等于0或者ls i，或者(c)、上述(a)或(b)不矛盾地组合成立；
    (5)在混沌计算结构支撑下配套使用bit取位逻辑和bit代谢逻辑及所列其它相关逻辑，构建‘伪随机错位提取未被代谢的构造源bit位或者重位提取已被代谢的构造源bit位’的再生密钥位段序列。
  6. 根据权利要求1所述的复重构密钥的序列加密方法，其特征在于：以混沌计算结构消解被构建的再生密钥位段序列的有概率出现的周期律；
    (1)利用混沌计算结构造成的位段长度ls i的伪随机变化，打乱被代谢位变化的规律性；
    (2)利用混沌计算结构造成的位段长度ls i的伪随机变化，打乱被重复提取位之值变化的规律性。
  7. 根据权利要求1所述的复重构密钥的序列加密方法，其特征在于：基于混沌计算结构实现不同再生密钥位段序列间的错段缠绕并嵌入伪随机bit位缠绕实现前后位段间的错段缠绕的错段叠加加密；
    (1)基于混沌计算结构对明文位段、再生密钥位段、密文位段进行同尺度切分；
    (1.1)以由位段长度限定值L min、L max确定的λ，(1/2)L min≤λ<(1/2)L max，作为位段切分尺度sd；
    (1.2)以sd作为错段位差，确定两组数量同为s的再生密钥位段序列间的位差，s≥1；
    (2)构造差异的分属于不同切分的两组再生密钥位段序列；
    (2.1)建立两组再生密钥位段序列；首再生密钥位段序列组bsk1 i,q，次再生密钥位段序列组bsk2 i,q，q＝1,2,…,s i＝0,1,2,…其中q为隶属于各组的各再生密钥位段序列的下标，s为各组中再生密钥位段序列数，i为轮序号；
    (2.2)各组再生密钥位段序列中的再生密钥位段遵循尺度sd切分：k1f i,q，长度为sd；k1l i,q，长度为ls i-sd；k2f i,q，长度为ls i-sd；k2l i,q，长度为sd；对明文位段也进行同尺度切分：Mf i，长度为sd；Ml i，长度为ls i-sd；
    (2.3)为各再生密钥位段序列确定差异的bit取位逻辑、bit代谢逻辑、或者差异的构造源、操控源；
    (3)确定2s-1个逐轮以位置链pos_chain(ls i-L min,j)，j＝0,1,…,ls-1实现的伪随机bit位重排逻辑；
    (4)基于同尺度切分的嵌入伪随机bit位缠绕的不同再生密钥位段序列的错段叠加加密：
    (4.1)使用长度为sd的s个缓冲区存储次再生密钥位段序列组各后半密钥位段k2l i,q，q＝1,2,…,s；
    (4.2)除首轮外，其他轮按下述顺序错段加密：
    Figure PCTCN2021102451-appb-100014
    (5)基于同尺度切分的嵌入伪随机bit位缠绕的不同再生密钥位段序列的错段解密：
    (5.1)在开始解密前建立：(1)长度为L max的位置链栈stack_chain，用于存储位置链；(2)长度为L max-sd的半段栈stack_k2f，用于存储s个次再生密钥位段的前半位段；(3)长度为sd的半段栈stack_k2l，用于存储下一轮错段拼接用的s个次再生密钥位段的后半位段；(4)长度为sd的错段半段栈s_stack_k2l，用于拷贝出前一轮存储在半段栈stack_k2l中的半密钥位段k2l i-1,q,以便拼接错段的次再生密钥位段k2l i-1,q||k2f i,q；(5)长度为L max的整段栈stack_bsk1，用于存储当前轮使用的首再生密钥位段；
    (5.2)除首轮外，在各轮解密之初将前一轮压入stack_k2l的全部次再生密钥位段的后半位段k2l i-1,q，q＝0,1,…,s-1拷贝进s_stack_k2l，并清空stack_k2l；
    (5.3)除首轮外，各轮按照加密处理顺序实施s次计算量重构或提取：(1)复重构再生密钥位段bsk1 i,q 并压入整段栈stack_bsk1，并进行位置链pos_chain(ls i-L min)代谢；(2)将位置链pos_chain(ls i-L min)压入位置链栈stack_chain并进行位置链pos_chain(ls i-L min)代谢；(3)复重构再生密钥位段bsk2 i,q，q＝0,1,…,s-1并压入半段栈stack_k2f、stack_k2l并进行位置链pos_chain(ls i-L min)代谢；(4)除第s次外，将位置链pos_chain(ls i-L min)压入位置链栈stack_chain并进行位置链pos_chain(ls i-L min)代谢；
    (5.4)除首轮外，其他轮按(5.3)的逆序错段解密：
    Figure PCTCN2021102451-appb-100015
    (5.5)各轮各次解密中半位段长度使用sd或ls i-sd，略去L max_ls i的多余部分。
  8. 根据权利要求1所述的复重构密钥的序列加密方法，其特征在于：以明文结束符EOP化解由混沌加密进程导致的明文结束位与加密结束位的错位；以明文结束符EOP作为解密计算正确性的效验码；
    (1)、在加/解密之初，根据初始动态驱动向量vector 0生成明文结束符EOP，及长度为位段长度限定最大值L max的追加伪随机串ms additn，将两者追加到明文尾端；
    (2)、加密过程中当计算所得位段长度ls i小于未加密明文的长度时停止计算；
    (3)、解密完成后以明文结束符EOP判定明文结束位置，并效验解密生成的明文的正确性。
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