WO2022000371A1 - Procédé et dispositif de génération d'interface et support de stockage lisible par ordinateur - Google Patents

Procédé et dispositif de génération d'interface et support de stockage lisible par ordinateur Download PDF

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Publication number
WO2022000371A1
WO2022000371A1 PCT/CN2020/099739 CN2020099739W WO2022000371A1 WO 2022000371 A1 WO2022000371 A1 WO 2022000371A1 CN 2020099739 W CN2020099739 W CN 2020099739W WO 2022000371 A1 WO2022000371 A1 WO 2022000371A1
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Prior art keywords
instruction
interface
assembly
preset
target
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PCT/CN2020/099739
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English (en)
Chinese (zh)
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沈桂旭
刘延昭
董岚
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深圳市大疆创新科技有限公司
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Priority to PCT/CN2020/099739 priority Critical patent/WO2022000371A1/fr
Publication of WO2022000371A1 publication Critical patent/WO2022000371A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode

Definitions

  • the present invention belongs to the technical field of instructions, and in particular, relates to an interface generation method, an apparatus and a computer-readable storage medium.
  • the interface defining the assembly instruction is usually written manually according to the content of each assembly instruction. In this way, when the assembly instruction is used for driving, the chip can be quickly driven by directly calling the assembly instruction interface.
  • this manual writing method has high cost and low efficiency.
  • the present invention provides an interface generation method, device and computer-readable storage medium, so as to solve the problems of manual interface writing, high cost and low efficiency.
  • an embodiment of the present invention provides an interface generation method, which includes:
  • the category indication information of the target assembly instruction determine a preset general instruction interface that matches the category indication information, and obtain a target general instruction interface; wherein, different types of instruction information correspond to different preset general instruction interfaces;
  • a dedicated instruction interface for describing the target assembly instruction is generated.
  • an embodiment of the present invention provides an interface generation apparatus, the apparatus includes: a memory and a processor,
  • the memory for storing program codes
  • the processor calls the program code, and when the program code is executed, is configured to perform the following operations:
  • the category indication information of the target assembly instruction determine a preset general instruction interface that matches the category indication information, and obtain a target general instruction interface; wherein, different types of instruction information correspond to different preset general instruction interfaces;
  • a dedicated instruction interface for describing the target assembly instruction is generated.
  • an embodiment of the present invention provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the foregoing interface generation method is implemented.
  • a target assembly instruction may be obtained, and according to the category indication information of the target assembly instruction, a preset general instruction interface matching the category indication information may be determined to obtain the target general instruction interface; wherein, different types of indication information correspond to different
  • the preset general instruction interface of the target assembly instruction generates a special instruction interface for describing the target assembly instruction according to the content of the target assembly instruction and the target general instruction interface.
  • the user does not need to manually write the definition interface, and the dedicated instruction interface of the target assembly instruction can be automatically generated. Therefore, to a certain extent, the cost can be reduced and the efficiency can be improved.
  • FIG. 1 is a flow chart of steps of a method for generating an interface provided by an embodiment of the present application
  • FIG. 2 is an abstract schematic diagram of a preset general command interface provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of an interface for generating a general command provided by an embodiment of the present application.
  • FIG. 4 is an abstract schematic diagram of a dedicated instruction interface provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of an interface structure provided by an embodiment of the present application.
  • FIG. 6 is a schematic design diagram of a generation tool provided by an embodiment of the present application.
  • FIG. 7 is a block diagram of an interface generation apparatus provided by an embodiment of the present application.
  • FIG. 8 is a block diagram of a computing processing device provided by an embodiment of the present application.
  • FIG. 9 is a block diagram of a portable or fixed storage unit according to an embodiment of the present application.
  • the chip can be a chip accelerator.
  • chip accelerators are used to support efficient image processing and data operations.
  • a chip accelerator is a special chip, which is usually a dedicated hardware circuit that can be used to implement various functions, so as to obtain higher performance or better energy efficiency than general-purpose microprocessors when performing a set of operations Compare.
  • the driving chip When the driving chip is working, it can be divided into register driving and instruction driving according to the driving mode.
  • the register-driven mode the operation of the accelerator is controlled through the configuration register.
  • the instruction-driven mode the drive needs to be implemented through the assembly instructions supported by the accelerator, that is, to implement accelerator scheduling.
  • the accelerator may include an accelerator module, and various types of accelerator modules can be dispatched through assembly instructions supported by the accelerator, so as to control the accelerator to execute operations corresponding to the assembly instructions.
  • the assembly instruction can be embedded in the native code of the accelerator through mixed programming, so that the operation logic indicated by the assembly instruction is associated with the processing logic of the native code, thereby realizing the scheduling of the assembly instruction in the native code. , which drives the accelerator to perform the corresponding operation.
  • the file in the native code of the accelerator is jointly compiled with the assembler file corresponding to the assembly instruction, so as to realize the scheduling of the assembly instruction in the native code, thereby realizing the scheduling of the accelerator.
  • a mixed programming method of C language programming and assembly programming can usually be adopted.
  • a C language software development system such as keil C
  • embedding can be implemented in the following ways:
  • the inline assembly keyword "__asm" can be used to embed assembly in C:
  • the interface of the assembly instruction is often defined.
  • the interface of the assembler instruction can be directly called, and the assembler instruction can be used for scheduling by running the interface.
  • the interface that defines the assembly instructions is manually written.
  • the number of assembly instructions is often large, which will consume higher labor costs and lower efficiency.
  • the embodiments of the present application provide an interface generation method for automatically generating an interface, so as to reduce costs and improve efficiency.
  • the interface generation method is described in detail below.
  • FIG. 1 is a flowchart of steps of an interface generation method provided by an embodiment of the present application. As shown in FIG. 1 , the method may include:
  • Step 101 obtaining target assembly instructions.
  • the target assembly instruction may be an assembly instruction that needs to generate an interface. There can be one or more target assembly instructions.
  • the target assembly instruction may be actively read from a preset position, or the target assembly instruction input by the user may be received, which is not limited in this embodiment of the present application.
  • Step 102 According to the category indication information of the target assembly instruction, determine a preset general instruction interface that matches the category indication information, and obtain a target general instruction interface; wherein, different types of instruction information correspond to different preset general instruction interfaces .
  • the category indication information may be used to indicate the category to which the assembly instruction belongs. Assembly instructions with the same class designation belong to the same class. Assembly instructions of the same class can have the same content.
  • the preset general instruction interface corresponding to the category indication information of this category can be used to represent the same content that this category of assembly instructions has in common.
  • the determined target general instruction interface that matches the category indication information of the target assembly instruction can be used to characterize the same content shared by other similar assembly instructions in the target assembly instruction, that is, at least can be used to characterize the same content of the target assembly instruction. Part of the target assembly instruction.
  • Step 103 Generate a dedicated instruction interface for describing the target assembly instruction according to the content of the target assembly instruction and the target general instruction interface.
  • the dedicated instruction interface can represent the content of the target assembly instruction and its assembly embedded code, so that the chip can be driven to execute the operation indicated by the target assembly instruction by subsequently calling the dedicated instruction interface.
  • the target general instruction interface can be used to represent part of the content in the target assembly instruction, that is, part of the content in the target assembly instruction has been pre-interfaced. Therefore, by combining the content of the target assembly instruction and the target general instruction interface to generate a dedicated instruction interface, the generation efficiency can be improved to a certain extent.
  • a general instruction interface can describe the same content that a class of assembly instructions has in common, when a dedicated instruction interface is generated for multiple assembly instructions, the general instruction interface can be reused, thereby improving the generation of dedicated instruction interfaces for multiple assembly instructions. time efficiency.
  • the target general instruction interface is obtained by obtaining the target assembly instruction, and according to the category indication information of the target assembly instruction, determining a preset general instruction interface that matches the category indication information;
  • different types of indication information correspond to different preset general instruction interfaces, and according to the content of the target assembly instruction and the target general instruction interface, a dedicated instruction interface for describing the target assembly instruction is generated.
  • the user does not need to manually write the definition interface, and the dedicated instruction interface of the target assembly instruction can be automatically generated. Therefore, to a certain extent, the cost can be reduced and the efficiency can be improved.
  • the category indication information may include the number of operands included in the target assembly instruction and the chip identifier of the chip to which it belongs.
  • the operands can be divided into source operands and destination operands.
  • the chip to which it belongs may be a chip that supports the target assembly instruction.
  • the chip identification can be an identification that can uniquely represent the chip. Since the number of operands between assembly instructions and the chip identification of the chip to which they belong is often the same, the number of operands and the chip identification of the chip to which they belong are used as the category instruction information to improve the accuracy of assembly instructions to a certain extent. Classification effect.
  • the identifiers can be numbers, characters, special symbols, and so on.
  • the above-mentioned preset general command interface can be implemented through the following sub-steps (1) to (3):
  • Sub-step (1) configure m ports for the assembly instructions of each preset category supported by the preset chip; the assembly instructions of the same preset category contain the same number of operands, and the m is not less than the preset category The number of operands contained in the assembly instruction.
  • the preset chip may be one or more chips specified in advance. Preset categories may be pre-divided according to operands of assembly instructions.
  • Step A Divide the assembly instructions that include the same operand in the assembly instructions supported by the preset chip into the same category to get the preset category. Specifically, the number of operands included in each assembly instruction supported by the preset chip may be determined first. Then, the assembly instructions with the same number of operands are divided into one category. For example, assume that the default chip is an accelerator.
  • the instructions in the accelerator instruction pool that is, the assembly instructions supported by the accelerator, can be classified according to operands. It is assumed that among the supported assembly instructions, there is an assembly instruction including one operand, an assembly instruction including two operands, ..., an assembly instruction including N operands. Then, N preset categories can be obtained by division: single-operand category, double-operand category, ..., N-operand category.
  • operands can be input or output through ports. Ports can be recorded in registers.
  • vmadd [0].char,[1].char,[2].char as an example, the assembly instruction is used to implement the accelerator's processing of adding a char type vector.
  • vmadd represents the mnemonic of the assembly instruction
  • [1].char and [2].char represent the source operand of type char, that is, the addend of vector addition.
  • the source operands come from the input ports recorded in internal register 1 and internal register 2 respectively, and the type of vector data is char. [0].char represents the destination operand of type char, that is, the result of vector addition.
  • the destination operand can be output to the output port recorded in internal register 0.
  • port configuration can be performed in units of categories. Taking the category as a unit, configure the port for each category, and the assembly instructions in one category share the port, which can improve the port utilization to a certain extent, thereby saving port resources.
  • x ports can be configured for the preset category, where x represents the number of operations corresponding to the preset category. In this way, the problem of occupying too many ports and leading to waste of resources can be avoided.
  • a single-operand class can be configured with a single port
  • a double-operand class can be configured with a dual port
  • an N-operand class can be configured with N ports.
  • configure the number of ports greater than x so as to avoid the problem that the ports are occupied and other assembly instructions in the category cannot be executed to a certain extent.
  • Sub-step (2) configure an assembly instruction conversion interface; the assembly instruction conversion interface is used to generate an assembly embedded code according to the assembly instruction; the assembly embedded code is used to embed the assembly instruction into the native chip of the preset chip. in the code.
  • the assembly instruction conversion interface may be used to provide a method for mapping assembly embedded codes according to assembly instructions.
  • the assembly instruction conversion interface may be implemented by macros, that is, the assembly instruction conversion interface may be a macro-type interface.
  • the general code segment of the assembly embedded code When configuring the assembly instruction conversion interface, you can first define internal parameters inside the interface: the general code segment of the assembly embedded code. Wherein, the general code segment may be manually set, or obtained by analyzing the same part in multiple assembler embedded codes. Then define the processing method, input and output of the interface. Wherein, the processing method may be a combination of internal parameters and input, the input may be an assembly instruction, and the output may be an assembly embedded code. It should be noted that, since assembly instructions are often character strings, the input may be a character string representing an assembly instruction.
  • the assembly instruction conversion interface may be an inline assembly interface.
  • inline assembly represents a way of inserting assembly language in C language.
  • the inline assembly interface can be used to generate assembly embedded code that can embed assembly instructions into native code developed based on C language in an inline assembly manner.
  • the chip is often developed based on the C language.
  • inline assembly in the C language
  • no additional compiler and linker are required, and the variables in the C language can be used. Therefore, this application implements the In the example, by configuring the inline assembly interface, it can be ensured that the generated general instruction interface has the ability to generate the assembly instructions to be embedded in the native code of the chip in the form of inline assembly, thereby improving the convenience of running the code to a certain extent.
  • Sub-step (3) Generate the preset general instruction interface according to the port information of the m ports, the assembly instruction conversion interface and the chip identifier of the preset chip.
  • the port information of the port may be the port identifier.
  • the port information, the assembly instruction conversion interface and the chip identification of the chip to which the assembly instruction belongs can be combined and spliced according to the preset interface format according to the preset format, so as to realize the modeling of the general instruction interface. to get the preset general command interface.
  • the preset general command interface may also be constructed by manual coding according to the logic of generating the preset general command interface shown in the embodiment of the present application, which is not limited in the embodiment of the present application.
  • Fig. 2 is an abstract schematic diagram of a preset general command interface provided by an embodiment of the present application.
  • module is used to represent the chip identification
  • the number of v is used to represent the number of operands
  • instr_asm is used to represent the assembly instruction conversion interface.
  • opnd is used to represent port information.
  • other forms may also be used to represent, which is not limited in this embodiment of the present application.
  • the generated preset general instruction interface can be expressed as “module_v(instr_asm,opnd)", and for the two-operand instructions in the two-operand category, the preset general instruction interface can be expressed as is “module_vv(instr_asm,opnd1,opnd2)", for N-operand instructions in the N-operand category, the generated preset general instruction interface can be expressed as "module_v...v(instr_asm,opnd1,opnd2,...,opndN)" .
  • the interface format of these general instruction interfaces may be expressed as "module_v..v”
  • the input parameters may be assembly instructions and corresponding specific vector ports.
  • FIG. 3 is a schematic diagram of an interface for generating a general command provided by an embodiment of the present application.
  • the operation of "instruction operand classification" can be realized through the above-mentioned step A
  • the operation of "instruction parameter configuration interface support” can be realized through the above-mentioned sub-step (1)
  • the “instruction-in-instruction” operation can be realized through the above-mentioned sub-step (2).
  • the operation of "connection interface support” is implemented, and the operation of "model splicing" is realized through the above sub-step (3).
  • a general instruction interface is established for each category by classifying the operand instructions.
  • all the assembly instructions supported by the chip can be described and modeled uniformly through a small number of interfaces, and the convenience of the follow-up is simple and fast.
  • the generation-specific instruction interface For example, assuming that the chip supports single-operand instructions, two-operand instructions, and three-operand instructions, only three general instruction interfaces need to be provided: "module_v, module_vv, module_vvv".
  • the category indication information of the target assembly instruction determine a preset general instruction interface that matches the category indication information, and obtain the operation of the target general instruction interface, which can be performed through the following sub-steps (4) to (6) accomplish:
  • Sub-step (4) For any one of the preset general command interfaces, obtain the number of chip identifiers and port information defined in the preset general command interface, as the comparison chip identifiers and the number of comparisons.
  • the preset general command interface can be parsed, and then the chip identification can be extracted therefrom, and the port information can be extracted to determine the quantity of the port information, and then the comparison chip identification and the comparison quantity can be obtained. For example, assuming that the defined chip identifier is "module" and the number is 3, then the comparison chip identifier of the preset general command interface may be "module", and the comparison number may be 3.
  • Sub-step (5) Compare the comparison quantity and the comparison chip identifier with the number of operands included in the target assembly instruction and the chip identifier of the chip to which the target assembly instruction belongs, respectively.
  • the number of operands included in the target assembly instruction and the chip identifier of the chip to which the target assembly instruction belongs may be determined first. For example, the operands contained in the target assembly instruction can be extracted, and then the number of the extracted operands can be counted. According to the preset correspondence between the chip identifier and the assembly instruction, the chip identifier corresponding to the target assembly instruction is searched for.
  • the number of comparisons is compared with the number of operands contained in the target assembly instruction to determine whether the two are the same.
  • the comparison chip identification is compared with the chip identification of the chip to which the target assembly instruction belongs to determine whether the two are the same.
  • Sub-step (6) if the comparison quantity is the same as the number of operands included in the target assembly instruction, and the comparison chip identification is the same as the chip identification of the belonging chip, then the preset general instruction interface is used. Identify the generic instruction interface for the target.
  • the target assembly instruction belongs to the category corresponding to the preset general instruction interface, and then the preset general instruction interface can be determined as the target general instruction interface.
  • the target general-purpose instruction can be more accurately determined. instruction.
  • the step of generating a dedicated instruction interface for describing the target assembly instruction can be implemented through the following sub-steps (7) to (8):
  • Sub-step (7) According to the content of the target assembly instruction and the target general instruction interface, generate an interface name, an interface parameter list and an assembly embedded code of the dedicated instruction interface.
  • the interface name can be used to represent a dedicated instruction interface for easy invocation.
  • the interface parameter list can be used to represent the parameters that will be used when the dedicated command interface is processed.
  • the assembly embedded code of the dedicated instruction interface can be used to embed the target assembly instruction into the native code of the corresponding chip.
  • sub-steps (7a) to (7b) can be used to generate the interface name, interface parameter list and assembly embedded code of the dedicated instruction interface:
  • the mnemonic may be an English word or its abbreviation indicating the function of the instruction.
  • the operand type may be the data type of each operand involved in the target assembly instruction.
  • the flag register also known as the program status word, can be used to store condition flags and control flag registers to reflect the result of instruction execution.
  • the flag register information may be information capable of identifying the flag register, such as the number, symbol, name, and the like of the flag register. It should be noted that, when the flag register information is not included in the assembly instruction, the interface name can be generated only according to the mnemonic, that is, the operand type.
  • the abbreviated characters corresponding to each of the operand types can be obtained; the abbreviated characters can be combined into an abbreviated string; , the abbreviated character string and the flag register information are combined to obtain the interface name.
  • the abbreviated characters corresponding to each operand type in the target assembly instruction can be searched according to the preset correspondence between the operand types and the abbreviated characters, and then these corresponding abbreviations are sorted according to the order in which the operand types appear in the assembly instruction.
  • the characters are combined into an abbreviated string.
  • the corresponding relationship between the preset type and the abbreviated characters may be as follows:
  • the target assembly instruction is "vacmps[0].char,[1].int,[2].int ge", where the operand types are: char, int, int, and the corresponding operand types can be obtained by searching
  • the abbreviated characters are: c, i, i. Combining these abbreviated characters can get the abbreviated string: "cii”.
  • the separator when combining the mnemonic, the abbreviated string and the flag register information, the separator can be used to connect the mnemonic, the abbreviated string and the flag register information in sequence, and then the interface is obtained. name.
  • the specific content of the separator may be preset according to actual requirements, and the connection sequence during connection may also be other sequences, which are not limited in this embodiment of the present application.
  • the delimiter is the underscore “_”
  • the target assembly instruction is "vacmps[0].char,[1].int,[2].int ge”
  • its mnemonic is “vacmps”
  • the operation The abbreviation string corresponding to the number type is "cii”
  • the flag register information is "ge”
  • the interface name can be obtained: "vacmps_cii_ge”.
  • an assembly instruction can be specifically characterized to a certain extent. Therefore, according to the combination of these information, the present application can ensure that the interface name can more accurately represent the target assembly instruction by generating the interface name.
  • an immediate number is equivalent to a constant, which is a number that can directly appear in an assembly instruction without being stored in a register or memory.
  • different assembly instructions have different functions. Therefore, some assembly instructions will include one of operands and immediate values, or both.
  • the interface parameter list may be generated according to both, and if only one is included, the interface parameter list may be generated according to the included one.
  • the included immediate data and operand port information corresponding to each operand can be added to the list.
  • the information of each operand port may be information of a port configured for the operand in advance, and the target general instruction interface may be called to obtain the information of each operand port.
  • its interface parameter list can be expressed as "int dstPort,int src0Port,int src1Port” , int dstPort, int src0Port, int src1Port represent the destination operand, respectively, the corresponding operand port information of source operand 1 and source operand 2.
  • the target general instruction interface may be called, the target assembly instruction may be used as the input of the target general instruction interface, and then the output may be used as the assembly embedded code corresponding to the target assembly instruction.
  • an inline assembly interface may be defined in the target general instruction interface.
  • the target assembly instruction can be converted into inline assembly code based on the inline assembly interface defined in the target general instruction interface to obtain the assembly embedded code.
  • the target assembly instruction can be used as the input of the inline assembly interface, and the assembly embedded code can be obtained by combining the general code segment defined in the inline assembly interface with the target assembly instruction.
  • the assembly embedded code generated by the inline assembly interface can embed assembly instructions into the native code developed based on the C language in the form of inline assembly, thereby improving the convenience of code operation to a certain extent.
  • the target general-purpose instruction interface may be invoked in a macro calling manner or an interface function calling manner.
  • the interface function calling method allocates a temporary memory unit for processing when the code is running.
  • the interface function method can be an intrinsic function.
  • the macro calling method also known as macro expansion, is performed when the code is compiled, and does not need to allocate memory units. Since the macro call method is expanded in the compilation stage, in the embodiment of the present application, the target general instruction interface is called by the macro call method, which can save the code running time to a certain extent. Further, when the target general instruction interface is called by using the interface function calling method, expansion in the compilation phase can be avoided, thereby ensuring the efficiency of the compilation phase.
  • Sub-step (8) Generate the dedicated instruction interface according to the interface name, the interface parameter list and the assembler embedded code.
  • the interface name, the interface parameter list, and the assembly embedded code may be spliced together to obtain the dedicated instruction interface.
  • internal splicing can be performed in the general command interface.
  • the return value of the dedicated instruction interface that is, the type of the output parameter, can be set to void in advance.
  • FIG. 4 is an abstract schematic diagram of a special-purpose instruction interface provided by an embodiment of the present application, and FIG. 4 is used to represent parts with common characteristics in the special-purpose instruction interfaces belonging to the same category of instructions. where "instruction" is used to represent the instruction name, for example, the instruction's mnemonic.
  • the number of x represents the number of abbreviated strings, and opnd is used to represent port information.
  • the dedicated instruction interface can be abstracted as "instruction_x(opnd)", and for the two-operand instructions in the two-operand category, the dedicated instruction interface can be abstracted as "instruction_xx(opnd1, opnd2) ", for N-operand instructions in the N-operand category, the dedicated general-purpose instruction interface can be abstracted as "instruction_x...x(opnd1,opnd2,...,opndN)".
  • the interface format of these general instruction interfaces may be expressed as "module_v..v”, and the input parameters may be assembly instructions and corresponding specific vector ports.
  • a mixed instruction pool may be generated according to the assembly instructions supported by each preset chip; the assembly instruction included in the mixed instruction pool is used as the target assembly instruction, and the The target assembly instruction is obtained from the mixed instruction pool.
  • the preset chip may be one or more chips specified by the user according to actual requirements.
  • the assembly instructions supported by these chips can be stored in the same file, resulting in a mixed instruction pool.
  • the mixed instruction pool can be traversed, and one assembly instruction is fetched each time as a target assembly instruction.
  • the multiple-to-many assembly instructions can be more evenly obtained.
  • the assembly instruction generation interface supported by each chip avoids generating the interface only for the assembly instruction supported by one of the chips, resulting in that the assembly instructions supported by the other chips cannot be processed in time.
  • the parallel generation configuration information may be used to indicate whether a preset waiting command needs to be packaged for the dedicated command interface at present.
  • the configuration information generated in parallel may be set according to actual requirements, and it may be the value of a preset flag bit.
  • the parallel generation configuration information can be obtained by reading the value of the preset flag bit.
  • the configuration information generated in parallel is a specified value, it can be considered that a preset waiting command needs to be packaged for the dedicated command interface at present. Therefore, it is possible to further encapsulate a preset waiting command for the dedicated command interface.
  • the preset waiting instruction can be encapsulated inside the interface, and when the dedicated instruction interface is called by encapsulating the preset waiting instruction, it will wait for the completion of the dedicated instruction interface inside the interface, and then execute other commands.
  • the dedicated instruction interface of the call that is, implements the blocking mode or the serial mode, thereby avoiding the parallel execution of the interface, causing the problem of interface conflict.
  • the preset waiting instruction is not encapsulated, then when the dedicated instruction interface is called, it will not wait for the dedicated instruction interface to complete within the interface, that is, the non-blocking mode or the parallel mode is implemented.
  • the specified value can be set according to the actual situation, and the specified value can be a number, a character, a character string, and so on. By way of example, the specified value may be "wait".
  • a second specified value can also be set, and in the case that the configuration information generated in parallel is the second specified value, the operation of encapsulating the preset waiting instruction for the dedicated instruction interface can be not performed, that is, only the generation does not include the preset waiting instruction.
  • Dedicated instruction switching for instructions can be set according to the actual situation, and the specified value can be a number, a character, a character string, and so on.
  • the specified value may be "wait”.
  • a second specified value can also be set, and in the case that the configuration information generated in parallel is the second specified value, the operation of encapsulating
  • the second specified value may be "nowait”.
  • a third specified value can also be set, and in the case that the configuration information generated in parallel is the third specified value, according to the dedicated instruction interface, a dedicated instruction interface encapsulated with a preset waiting instruction can be generated at the same time, and a preset waiting instruction is not encapsulated.
  • Dedicated command interface for waiting commands Illustratively, the third specified value may be "all”.
  • Step A Acquire designation information according to the dedicated command interface; the designation information at least includes port information in the dedicated command interface and types of output parameters.
  • the specified information may be information set according to actual requirements, and may also include other information in addition to the port information and the type of output parameters, which is not limited in this embodiment of the present application.
  • each port information can be extracted from the dedicated command interface, and the preset output parameter type can be obtained.
  • Step B Combine the specified information according to a preset annotation generation tool to obtain an interface annotation of the dedicated command interface.
  • the annotation generating tool may be a pre-selected tool for generating annotations, for example, a doxygen tool, and correspondingly, the specified information may be information that complies with the rule requirements of the doxygen tool.
  • the annotation generation tool can automatically parse the specified types of information, and arrange and combine them according to preset rules.
  • the specified information can be output to an annotation generation tool, and the specified information can be combined by the annotation generation tool to obtain interface annotations, and these interface annotations form an annotation document.
  • the interface annotation of the special instruction interface is automatically generated according to the annotation generation tool, so that the special instruction interface to be called can be conveniently selected according to the interface annotation in the future, thereby improving the efficiency of interface calling.
  • VALU_vvv("vacmps[0].char,[1].int,[2].int ge",dstPort,src0Port,src1Port) represents the calling target general instruction interface.
  • "vacmps[0].char,[1].int,[2].int ge” in the target general instruction interface is used to convert the target assembly instruction into assembly embedded code
  • VALU indicates the chip identification
  • "dstPort,src0Port, src1Port” indicates port information.
  • the interface prototype of this assembly instruction in the specific model can be expressed as: void vacmps_cii_ge(int dstPort,int src0Port,int src1Port);
  • the target assembly instruction containing three operands by calling the general instruction interface corresponding to the three operands, the underlying assembly scheduling and configuration can be completed, and the specific interface of the abstract encapsulation target assembly instruction can be realized, that is, Dedicated command interface.
  • steps C to D may also be performed:
  • Step C For any of the preset chips, define a dedicated command interface corresponding to the preset chip at the designated position of the native code of the preset chip, and obtain an interface model of the preset chip; It is assumed that the dedicated instruction interface corresponding to the chip is generated according to the target assembly instruction belonging to the preset chip.
  • the specified location may be preset.
  • the specified location may be a header file (include.).
  • the dedicated command interface corresponding to the preset chip can be written into a specified location, so as to realize the construction of the interface model of the preset chip, and obtain the interface models corresponding to different preset chips. That is, according to the preset chips, the interface model of each preset chip is obtained.
  • Step D when receiving an instruction calling request, obtain a dedicated instruction interface matching the instruction calling request from the interface model of the target preset chip; the chip identifier of the target preset chip is in the instruction calling request. The included chip ID matches.
  • the instruction invocation request may be sent when a dedicated instruction interface needs to be invoked. If an instruction call request is received, it can be considered that there is a dedicated instruction interface that needs to be called.
  • the instruction invocation request may contain a chip identifier to indicate which chip the instruction invocation request is used to invoke the dedicated instruction interface of the assembly instruction supported by the chip.
  • a dedicated instruction interface matching the instruction invocation request can be obtained from the interface model in which the chip identification matches the chip identification contained in the instruction invocation request.
  • the instruction invocation request may also include the name of the dedicated instruction interface, and the dedicated instruction interface with the same name included in the instruction invocation request in the interface model may be determined as the dedicated instruction interface matching the instruction invocation request.
  • the interface model of each preset chip is constructed according to the preset chip classification, so that when the dedicated command interface is called later, the corresponding interface model can be conveniently searched and called, and the calling efficiency can be improved to a certain extent.
  • the dedicated instruction interface after generating the dedicated instruction interface, you may further: obtain a preset output path; and output the dedicated instruction interface according to the preset output path.
  • the preset output path may be preset.
  • the dedicated command interface When the dedicated command interface is output, the dedicated command interface can be output to the preset position according to the preset output path.
  • the preset output path is used to output the dedicated command interface according to the preset output path, so that the dedicated command interface can be directly outputted to the preset position, thereby facilitating storage.
  • FIG. 5 is a schematic structural diagram of an interface provided by an embodiment of the present application.
  • the bottom-level assembly instruction may be a target assembly instruction, and the bottom-level assembly configuration may represent a related configuration, for example, configured port information.
  • the general programming model in the first layer may be a target general instruction interface and the specific programming model in the second layer may be a dedicated instruction interface.
  • the underlying assembly instruction is "vmadd[0].char,[1].char,[2].char”
  • the underlying assembly configuration can be expressed as “outVEU_INST0_MAP0,r0”
  • the general programming model can be expressed as "VEU_vvv( "vmadd[0].char,[1].char,[2].char”,dstPort,src0Port,src1Port)”
  • the specific programming model can be expressed as "Vmadd_ccc(dstPort,src0Port,src1Port)”.
  • an automated generation tool may also be constructed according to the above processing logic for generating a dedicated instruction interface.
  • the automatic generation tool When the automatic generation tool is running, the above steps can be implemented.
  • the automatic generation tool can support command line parameter control.
  • the following is part of the command line:
  • FIG. 6 is a schematic design diagram of a generation tool provided by an embodiment of the present application.
  • the generation tool can generate a mixed instruction pool according to the instruction pools corresponding to the X accelerators. That is, according to the assembly instructions supported by each preset chip, a mixed instruction pool is generated. Then, the target assembly instruction is obtained from the mixed instruction pool, and a dedicated instruction interface is generated through subsequent operations. Interface annotations and interface models for each accelerator can also be generated later.
  • FIG. 7 is a block diagram of an interface generation apparatus provided by an embodiment of the present application. As shown in FIG. 7 , the apparatus may include: a memory 201 and a processor 202 .
  • the memory 201 is used to store program codes.
  • the processor 202 calls the program code, and when the program code is executed, is configured to perform the following operations: obtain a target assembly instruction;
  • the matching preset general-purpose instruction interface obtains the target general-purpose instruction interface; wherein, different types of indication information correspond to different preset general-purpose instruction interfaces; according to the content of the target assembly instruction and the target general-purpose instruction interface, generate a description for A dedicated instruction interface for the target assembly instruction.
  • the category indication information includes the number of operands included in the target assembly instruction and the chip identifier of the chip to which it belongs.
  • the processor 202 is further configured to: configure m ports for the assembly instructions of each preset category supported by the preset chip; the assembly instructions of the same preset category contain the same number of operands, the m is not less than the number of operands contained in the assembly instructions of the preset category; configure an assembly instruction conversion interface; the assembly instruction conversion interface is used to generate an assembly embedded code according to the assembly instruction; the assembly embedded code is used to convert The assembly instruction is embedded in the native code of the preset chip;
  • the preset general instruction interface is generated according to the port information of the m ports, the assembly instruction conversion interface, and the chip identifier of the preset chip.
  • the assembly instruction conversion interface is an inline assembly interface.
  • the processor 202 is further configured to: classify the assembly instructions that include the same operand among the assembly instructions supported by the preset chip into the same category to obtain the preset category.
  • the processor 202 is specifically configured to: generate an interface name, an interface parameter list, and an assembly embedded code of the dedicated instruction interface according to the content of the target assembly instruction and the target general instruction interface; The interface name, the interface parameter list and the assembler embedded code are used to generate the dedicated instruction interface.
  • the processor 202 is specifically configured to: generate the interface name of the dedicated instruction interface according to the mnemonic, operand type and flag register information in the target assembly instruction; call the target general instruction an interface to generate an interface parameter list of the dedicated instruction interface according to the operand port information and/or immediate data in the target assembly instruction, and convert the target assembly instruction into an assembly embedded code.
  • the processor 202 is specifically configured to: obtain the abbreviated characters corresponding to each of the operand types; combine the abbreviated characters into an abbreviated character string; , the abbreviated character string and the flag register information are combined to obtain the interface name.
  • the processor 202 is specifically configured to: call the target general instruction interface in a macro calling manner or an interface function calling manner.
  • an inline assembly interface is defined in the target general instruction interface; the processor 202 is specifically configured to: convert the target assembly instruction based on the inline assembly interface defined in the target general instruction interface for inline assembly code.
  • the processor 202 is specifically configured to: for any of the preset general-purpose command interfaces, obtain the number of chip identifiers and port information defined in the preset general-purpose command interface, as the comparison chip identifiers and comparisons.
  • the processor 202 is specifically configured to: generate a mixed instruction pool according to the assembly instructions supported by each preset chip; The target assembly instruction is obtained from the instruction pool.
  • the processor 202 is further configured to: for any of the preset chips, define a dedicated instruction interface corresponding to the preset chip at a designated position of the native code of the preset chip, and obtain the preset chip.
  • the interface model of the preset chip; the dedicated instruction interface corresponding to the preset chip is generated according to the target assembly instruction belonging to the preset chip; when receiving an instruction call request, the interface model of the target preset chip is obtained.
  • a dedicated instruction interface matching the instruction invocation request is obtained; the chip identification of the target preset chip matches the chip identification contained in the instruction invocation request.
  • the processor 202 is further configured to: acquire specified information according to the dedicated instruction interface; the specified information at least includes port information and the type of output parameters in the dedicated instruction interface; The annotation generation tool combines the specified information to obtain the interface annotation of the dedicated instruction interface.
  • the processor 202 is further configured to: obtain preset parallel generation configuration information; if the parallel generation configuration information is a specified value, encapsulate a preset waiting instruction for the dedicated instruction interface; It is assumed that the waiting instruction is used to indicate that when the dedicated instruction interface is called, after the execution of the dedicated instruction interface is completed, other called dedicated instruction interfaces are executed.
  • the processor 202 is further configured to: acquire a preset output path; and output the dedicated instruction interface according to the preset output path.
  • the operations performed by the above-mentioned apparatus are similar to the corresponding steps in the above-mentioned method, and can achieve the same technical effect. To avoid repetition, details are not repeated here.
  • the embodiments of the present application also provide a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, each step in the above-mentioned interface generation method is implemented, and can To achieve the same technical effect, in order to avoid repetition, details are not repeated here.
  • the device embodiments described above are only illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in One place, or it can be distributed over multiple network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution in this embodiment. Those of ordinary skill in the art can understand and implement it without creative effort.
  • Various component embodiments of the present application may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof.
  • FIG. 8 is a block diagram of a computing processing device provided by an embodiment of the present application. As shown in FIG. 8 , FIG.
  • the computing processing device traditionally includes a processor 310 and a computer program product or computer readable medium in the form of a memory 320 .
  • the memory 320 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read Only Memory), EPROM, hard disk, or ROM.
  • the memory 320 has storage space 330 for program code for performing any of the method steps in the above-described methods.
  • the storage space 330 for program codes may include various program codes for implementing various steps in the above methods, respectively. These program codes can be read from or written to one or more computer program products.
  • These computer program products include program code carriers such as hard disks, compact disks (CDs), memory cards or floppy disks. Such computer program products are typically portable or fixed storage units as described with reference to FIG. 9 .
  • the storage unit may have storage segments, storage spaces, etc. arranged similarly to the memory 320 in the computing processing device of FIG. 8 .
  • the program code may, for example, be compressed in a suitable form.
  • the storage unit includes computer readable code, ie code readable by a processor such as 310 for example, which when executed by a computing processing device, causes the computing processing device to perform each of the methods described above. step.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the word “comprising” does not exclude the presence of elements or steps not listed in a claim.
  • the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements.
  • the application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by one and the same item of hardware.
  • the use of the words first, second, and third, etc. do not denote any order. These words can be interpreted as names.

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Abstract

Procédé et dispositif de génération d'interface et support de stockage informatique. Le procédé consiste : à acquérir une instruction d'assemblage cible (101) ; à déterminer, en fonction d'informations d'indication de classe de l'instruction d'assemblage cible, une interface d'instruction universelle pré-configurée correspondant aux informations d'indication de classe, et à acquérir une interface d'instruction universelle cible, différentes informations d'indication de classe correspondant à différentes interfaces d'instructions universelles pré-configurées (102) ; à générer, en fonction du contenu de l'instruction d'assemblage cible et de l'interface d'instruction universelle cible, une interface d'instruction spécialisée, destinée à décrire l'instruction d'assemblage cible (103). Au moyen du procédé, un utilisateur n'a pas besoin de programmer et de définir manuellement une interface, et une interface d'instruction spécialisée d'une instruction d'assemblage cible est automatiquement générée. Par conséquent, les coûts sont réduits et le rendement est amélioré.
PCT/CN2020/099739 2020-07-01 2020-07-01 Procédé et dispositif de génération d'interface et support de stockage lisible par ordinateur WO2022000371A1 (fr)

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Citations (5)

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Publication number Priority date Publication date Assignee Title
US20010016940A1 (en) * 1998-10-29 2001-08-23 Texas Instruments Inc System and method for translating include files
CN101118498A (zh) * 2007-09-13 2008-02-06 上海交通大学 基于用户描述的汇编器及其实现方法
US20140149969A1 (en) * 2012-11-12 2014-05-29 Signalogic Source code separation and generation for heterogeneous central processing unit (CPU) computational devices
CN109947432A (zh) * 2019-03-28 2019-06-28 Oppo广东移动通信有限公司 汇编程序处理方法及相关装置
CN111078290A (zh) * 2019-12-17 2020-04-28 西安电子科技大学 一种用于可扩展指令集的编译器及编译方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010016940A1 (en) * 1998-10-29 2001-08-23 Texas Instruments Inc System and method for translating include files
CN101118498A (zh) * 2007-09-13 2008-02-06 上海交通大学 基于用户描述的汇编器及其实现方法
US20140149969A1 (en) * 2012-11-12 2014-05-29 Signalogic Source code separation and generation for heterogeneous central processing unit (CPU) computational devices
CN109947432A (zh) * 2019-03-28 2019-06-28 Oppo广东移动通信有限公司 汇编程序处理方法及相关装置
CN111078290A (zh) * 2019-12-17 2020-04-28 西安电子科技大学 一种用于可扩展指令集的编译器及编译方法

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