WO2021259476A1

WO2021259476A1 - Method of designing a datapath in a semiconductor component, and semiconductor component having a datapath

Info

Publication number: WO2021259476A1
Application number: PCT/EP2020/067771
Authority: WO
Inventors: Mustafa Badaroglu
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2020-06-25
Filing date: 2020-06-25
Publication date: 2021-12-30

Abstract

A method of designing a datapath between two memory units in a semiconductor component. The datapath includes two or more positions for cells, each cell having a rising edge and a falling edge. The method includes selecting for each of the two or more positions a cell type from a library comprising available cells. Each available cell is able to perform an operation, and each cell having a P region and an N region and being P/N imbalanced. The cell type is selected in dependence of a switching point of a preferred edge to be used in the operation. The preferred edge is either the rising edge or the falling edge of the cell.

Description

METHOD OF DESIGNING A DATAPATH IN A SEMICONDUCTOR COMPONENT, AND SEMICONDUCTOR COMPONENT HAVING A DATAPATH

TECHNICAL FIELD [0001] The present disclosure relates generally to semiconductor components, and more specifically, to a method of designing a datapath between two memory units in a semiconductor component, and a semiconductor component having such datapath.

BACKGROUND

[0002] Advancements in semiconductor technology are leading to reduction in physical footprints of semiconductor devices. Miniaturization or scaling of the semiconductor devices is progressing rapidly to increase the number of such semiconductor devices that can be integrated on a given semiconductor chip. Despite today’s advancements, the miniaturization or scaling is facing newer challenges as single digit nanometre semiconductor devices are being developed. [0003] Conventionally, the miniaturization or scaling of the semiconductor devices, such as Fin field effect transistor (FinFET), Gate-all-around field effect transistor (GAAFET), Multi-bridge channel field effect transistor (MBCFET) and other complementary metal- oxide-semiconductors (CMOS), may be done by reducing number of active fins in such semiconductor devices. Reduction in the number of active fins may cause P/N ratio imbalance in such semiconductor devices. This in turn may cause problem in duty cycle generation, typically for the digital systems relying on 50% duty cycling. Moreover, the imbalanced P/N ratio causes imbalanced switching threshold for data transfer, which in turn causes a degradation in a noise margin. Additionally, the miniaturization of semiconductor devices causes problem related to drive strength of such semiconductor devices. Poor drive strength can further cause delay problem in circuits using such semiconductor devices. For example, poor drive strength may cause delay in data transfer through a datapath, constituted using such semiconductor devices. Typically, the problem of poor drive strength can be resolved via direct cell sizing. However, the concept of direct cell sizing is associated with area penalty and capacitance penalty causing larger power consumption. [0004] Therefore, in light of the foregoing discussion there exists a need to overcome the aforementioned drawbacks associated with conventional semiconductor devices or semiconductor components having such semiconductor devices. SUMMARY

[0005] The present disclosure seeks to provide a method of designing a datapath between two memory units in a semiconductor component. The present disclosure also seeks to provide a semiconductor component comprising a first and a second memory unit and a datapath between the memory units. The datapath of the present disclosure is constituted using two or more cells, i.e. semiconductor devices. The present disclosure seeks to provide a solution to the existing problems of imbalanced drive strength, imbalanced P/N ratio and imbalanced switching threshold causing a degradation in noise margin due to miniaturization of the semiconductor devices. An aim of the present disclosure is to provide a solution that overcomes at least partially the problems encountered in prior art and provide semiconductor devices or semiconductor components (having such semiconductor devices) that provide balanced drive strength, balanced P/N ratio and balanced switching threshold for improvement in the noise margin.

[0006] The object of the present disclosure is achieved by the solutions provided in the enclosed independent claims. Advantageous implementations of the present disclosure are further defined in the dependent claims.

[0007] In a first aspect, the present disclosure provides a method of designing a datapath between two memory units in a semiconductor component. The datapath comprising two or more positions for cells, each cell having a rising edge and a falling edge. The method comprising selecting for each of the two or more positions a cell type from a library comprising available cells, wherein each available cell being able to perform an operation, and each cell having a P region and an N region and being P/N imbalanced. The cell type is selected in dependence of a switching point of a preferred edge to be used in the operation, wherein the preferred edge is either the rising edge or the falling edge of the cell.

[0008] The method of the present disclosure employs hybrid library assignment scheme for the datapath constituted using two or more cells, i.e. semiconductor devices. The datapath employs selective implementation of a cell type for the two or more positions of the cells from a library based on a switching point of a preferred edge, namely the rising edge or falling edge. The hybrid library assignment scheme is implemented to balance the impact of the imbalanced P/N ratio on the total delay time and imbalanced drive strength assignment to each stage in a datapath. The hybrid library assignment comprises satisfying a transition point of each of the two or more cells to improve the noise margin of the datapath. This ensures that no glitch is propagated to be captured by the memory unit at the end of datapath. Moreover, the hybrid library assignment enables the datapath speed to be boosted in P/N imbalanced libraries and preservation of 50% duty cycle by exploiting the preferred edge of each of the cell.

[0009] In an implementation form, the method comprises selecting a cell wherein the P region has a higher drive strength than the N region for a first one of the positions and a cell wherein the N region has a higher drive strength than the P region for a second one of the positions.

[0010] The selection of a cell type for each of the two or more positions for the cells is based on the switching point of the preferred edge and is done to enable the cells to have a higher drive strength in one of the two regions of the cell. Upon increasing the drive strength of the cells, the external load capacitance decreases. Beneficially, the time delay is reduced upon increasing the drive strength of the cell.

[0011] In a further implementation form, the method comprising selecting a cell having a stronger N, for example by having a higher number of fins in the N region than in the P region, for a position that is falling edge dominated.

[0012] The selection of a cell having a stronger N region for a position that is rising edge dominated is implemented via increasing the number of fins in the N region to further increase the drive strength of the cell as compared to a conventional cell. In such an implementation, the size of the cell remains unaltered since only the number of fins is changed (among the N and P regions) to increase the drive strength of the cell.

[0013] In a further implementation form, the method comprising selecting a cell having a stronger P, for example by having a higher number of fins in the P region than in the N region, for a position that is rising edge dominated.

[0014] The selection of a cell having a stronger P region for a position that is falling edge dominated is implemented via increasing the number of fins in the P region to further increase the drive strength of the cell as compared to a conventional cell. As mentioned above, in such an implementation, the size of the cell remains unaltered since only the number of fins is changed (among the P and N regions) to increase the drive strength of the cell.

[0015] In a further implementation form, the datapath comprises a plurality of positions for cells and the number of cells having a stronger N is balanced with the number of cells having a stronger P in the datapath. [0016] Cell balancing of the number of cells having a stronger N with the number of cells having a strong P is employed to enable duty cycle preservation upon requirement. Moreover, the duty cycle preservation is employed in to decrease the total energy dissipation during operation.

[0017] In a further implementation form, the method comprising selecting a cell having a stronger N as the last cell in the datapath if the first cell in the datapath has a stronger P, and selecting a cell having a stronger P as the last cell in the datapath if the first cell in the datapath has a stronger N.

[0018] The selection of a cell having a stronger N as the last cell in the datapath if the first cell in the datapath has a stronger P, and selecting a cell having a stronger P as the last cell in the datapath if the first cell in the datapath has a stronger N is done to exploit the preferred edge characteristics of each of the stronger cells to improve the noise margin of the datapath.

[0019] In a further implementation form, the method comprising selecting cells having the same physical footprint for the two or more cells.

[0020] The selection of cells is done based on the same physical footprint for the two or more cells. In other words, to preserve the same cell footprint to allow the method to efficiently employ an Engineering Changer Order (ECO). Moreover, the selection enables a simple cell swap of the two or more cells in case of replacement.

[0021] In a further implementation form, wherein the memory units are flip-flops.

[0022] The memory units implemented are flip flops to enable edge-sensitive triggering of an input signal. Moreover, flip flops enable an increased number of logic calculations during operation.

[0023] In a second aspect, the present disclosure provides a semiconductor component comprising a first and a second memory unit and a datapath between the memory units, the datapath comprising two or more cells, each cell being arranged to perform an operation and having a rising edge and a falling edge and a P region and an N region and being P/N imbalanced, each cell type being selected in dependence of the switching point of the rising edge or of the falling edge of the cell, depending on whether the rising edge or the falling edge to be used in the operation. [0024] The semiconductor component of the second aspect achieves all the advantages and effects of the first aspect.

[0025] In an implementation form, the semiconductor component comprising one or more cells wherein the P region has a higher drive strength than the N region and one or more cells wherein the N region has a higher drive strength than the P region.

[0026] In a further implementation form, the semiconductor component comprising a cell having a stronger N, for example by having a higher number of fins in the N region than in the P region, for at least one position in the datapath that is falling edge dominated.

[0027] In a further implementation form, the semiconductor component comprising a cell having a stronger P, for example by having a higher number of fins in the P region than in the N region, for at least one position in the datapath that is rising edge dominated.

[0028] In a further implementation form, the datapath comprises a plurality of positions for cells and the number of cells having a stronger N is balanced with the number of cells having a stronger P in the datapath.

[0029] In a further implementation form, the semiconductor component comprising a cell having a stronger N as the last cell in the datapath if the first cell in the datapath has a stronger P, and selecting a cell having a stronger P as the last cell in the datapath if the first cell in the datapath has a stronger N.

[0030] As mentioned herein above, it will be evident that the semiconductor component of the second aspect achieves all the advantages and effects of the first aspect. Additionally, the semiconductor component can be effectively customized to obtain optimized advantages of both the two or more cells and the two memory units. The semiconductor component may require different arrangement of the two or more cells, to exploit the preferred edges of the two or more cells.

[0031] It will be appreciated that all implementation forms discussed hereinabove can be combined. It has to be noted that all devices, elements, circuitry, units and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof. It will be appreciated that features of the present disclosure are susceptible to being combined in various combinations without departing from the scope of the present disclosure as defined by the appended claims.

[0032] Additional aspects, advantages, features and objects of the present disclosure would be made apparent from the drawings and the detailed description of the illustrative implementations construed in conjunction with the appended claims that follow.

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The summary above, as well as the following detailed description of illustrative embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the present disclosure, exemplary constructions of the disclosure are shown in the drawings. However, the present disclosure is not limited to specific methods and instrumentalities disclosed herein. Moreover, those skilled in the art will understand that the drawings are not to scale. Wherever possible, like elements have been indicated by identical numbers.

[0034] Embodiments of the present disclosure will now be described, by way of example only, with reference to the following diagrams wherein:

FIG. 1 illustrates a method of designing a datapath between two memory units in a semiconductor component, in accordance with an embodiment of the present disclosure;

FIG. 2 illustrates is a block diagram of a semiconductor component, in accordance with an embodiment of the present disclosure;

FIG. 3 illustrates is stick diagram of cells, in accordance with an embodiment of the present disclosure; and

FIG. 4 illustrates rising and falling edges of the cells shown in FIG. 3, in accordance with an embodiment of the present disclosure.

[0035] In the accompanying drawings, an underlined number is employed to represent an item over which the underlined number is positioned or an item to which the underlined number is adjacent. A non-underlined number relates to an item identified by a line linking the non-underlined number to the item. When a number is non-underlined and accompanied by an associated arrow, the non-underlined number is used to identify a general item at which the arrow is pointing. DETAILED DESCRIPTION OF EMBODIMENTS

[0036] The following detailed description illustrates embodiments of the present disclosure and ways in which they can be implemented. Although some modes of carrying out the present disclosure have been disclosed, those skilled in the art would recognize that other embodiments for carrying out or practicing the present disclosure are also possible.

[0037] FIG. 1 illustrates a method 100 for designing a datapath between two memory units in a semiconductor component, in accordance with an embodiment of the present disclosure. The method 100 of the present disclosure relates to designing a datapath constituted by employing cells having a hybrid library assignment of cells.

[0038] According to an embodiment, the method 100 for designing the datapath relates to simulating the datapath using programs. Additionally, the method 100 also relate to physically embodying the datapath. In one embodiment, the method 100 for designing the datapath is associated with programs, such as Electronic Design Automation (EDA) or Computer Aided Design (CAD), in which the datapath is designed using standard cells that is developed at a transistor level, in the form of a transistor netlist. Further, the method 100 of the present disclosure is “Engineering Change Order” (or ECO) compatible. Typically, the method 100 may be implemented or applied before the fabrication of the semiconductor component.

[0039] The method 100 is primarily associated with the designing of the datapath between two memory units in the semiconductor component. The term “datapath” used herein refers to a route through which data flows between the two memory units. In other words, the datapath may be a collection of cells configured to perform arithmetic logic operations in order to transfer data between the memory units. The data may be logic voltage levels typically represented using boolean value (0 and 1 , or low and high, or false and true) corresponding to a digital signal. In physical term, the datapath may be a deposition of semiconductor material (i.e. p-type and n-type semiconducting materials) fabricated to perform the arithmetic logic operations for the data transfer, which will be explained in greater detail herein later.

[0040] The method 100 of the present disclosure is associated any integrated circuit having memory units connected by the datapath. According to an embodiment, the memory units are flip-flops. In operation, the flip-flops are implemented for synchronizing variable input signals and for counting the number of pulses in the datapath over a period of time. Further, the flip-flops of the present disclosure may be edge-triggered or synchronous. Additionally, the semiconductor component according to the method 100 can be a processor or a memory chip. Therefore, the method 100 is associated with designing of the datapath between the memory units (i.e. flip-flops) of the semiconductor component (such as the processor or the memory chip).

[0041] The datapath comprises two or more positions for cells. According to the method 100, for constituting the datapath, at least two positions of the cells are considered. At the design flow level, physically position for cell may be considered as spaces where cells can be positioned physically. Therefore, based on the number of positions of the cells, a datapath may have corresponding number of cells constituting the datapath. For example, the datapath may be constituted by two cells filling the two positions of the cells in the datapath. Further, based on various embodiment, the s may include cells in the range of 2- 10, 10-100 or 100 to 1000 depending on the need of the arithmetic logic operations associated with the datapath. Accordingly, a length of the datapath may vary or depend on number of positions of the cells, to be eventually acquired by the cells.

[0042] According to an embodiment, the cell may be a semiconductor device. For example, the cell may be a standard cell associated with a transistor or a group of transistor and interconnect structures that provides a Boolean logic function or a storage function. For example, the cell may be a metal-oxide-semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET), such as p-channel MOSFET or a n-channel MOSFET. Further, when cells are collectively taken into consideration the group of cells may be considered as a Complementary metal-oxide-semiconductor (CMOS). Moreover, the cell of the present disclosure is a fin field-effect transistor (FinFET). Specifically, the cell may be Multi-Bridge Channel field-effect transistor (MBCFET), i.e. a nanosheet transistor. Alternatively, the cell may be Gate-AII-Around field-effect transistor (GAAFET), i.e. a nanowire transistor.

[0043] Each cell includes a rising edge and a falling edge. The rising and falling edges of the cell are operational aspects of the cell with respect to a digital signal processing. In other words, rising and falling edges of the cell may represent operational states of the cell, i.e. logic voltage levels typically represented using Boolean value corresponding to the digital signal. As we know, a signal edge is a transition of the digital signal from low to high (0 to 1) or from high to low (1 to 0). Accordingly, a rising edge (or positive edge) is the low-to- high transition, and a falling edge (or negative edge) is the high-to-low transition. Additionally, the rising edge and the falling edge of the cell is associated with a rising edge and a falling edge of a clock signal of a memory unit, i.e. a flip-flop.

[0044] At step 102, for each of the two or more positions a cell type is selected from a library comprising available cells. As explained herein above, the datapath comprises the two or more positions for cells, therefore each position of the datapath is to be occupied by an individual cell to constitute the datapath. Further, each cell is associated with a cell type, basically having different structural and/or functional attribute associated therewith, would be explained herein later. Further, the term library relates to a collection of cells, referred to as available cells, each having a cell type associated therewith. Therefore, in the method 100 from the datapath design perspective, the available cells (based on the cell type) may be represented using different icons, for example in the EDA platform. Accordingly, the datapath may be designed or constituted by selecting such available cells represented using different graphical icons. Additionally, the EDA platform may be further associated with programs, such as SPICE or Spectre, to simulate the electronic behavior of the datapath. The electronic behavior of the datapath may include selecting input stimulus (voltage or current waveforms) and then calculating the datapath time domain response, such as critical path delay.

[0045] Each available cell being able to perform an operation. The term operation used herein refers to an ability to transfer data, i.e. logic voltage levels corresponding to a digital signal. In the present disclosure, the cells constituting the datapath between the memory units are primarily operable to perform the operation of data transfer between the memory unit. In another operation, the cells constituting the datapath may be operable to perform an inverting operation of an input signal based on the Boolean logic.

[0046] Each cell comprises a P region and an N region and being P/N imbalanced. As mentioned herein above, the cell is a semiconductor device, therefore the P region and the N region thereof may be referred to as portions of the cell having p-doped portion and n- doped portion. Further, the term P/N imbalance used herein refers to difference in structural and functional attributes of the P and N regions of the cells, which is explained in greater detail herein later.

[0047] According to an embodiment, the P/N imbalance for a cell is caused by having different drive strength. The aspect of drive strength can be considered as the functional attribute of the cell. The term drive strength used herein refers to the capacity of the cell to drive a value to the cell connected to its output. According to the present disclosure, the P/N imbalance of a cell is caused by having different drive strengths for a P region and a N region of the cell. Specifically, a cell includes a P region, which includes a higher drive strength as compared to a drive strength of the N region of the cell. Similarly, another cell includes a N region, which includes a higher drive strength as compared to a drive strength of the P region of the cell. The difference in drive strengths between the P and N regions of a cell can be as low as 1.1 -5.0 times lower, to as high as 1.1 -5.0 times higher. [0048] In the present disclosure, a cell is caused to have different drive strengths for a P region and an N region based on a number of fins present in the P region and the N region thereof. The aspect of number of fins can be considered as the structural attribute of the cell. The number of fins in a fin set for a region to be allocated in any given PMOS region or NMOS region of the cell may vary depending on the needs of a particular implementation. The fins may be structure that is implemented on an insulating layer or protrude from the underlying semiconductor substrate. According to an embodiment, a cell of the present disclosure includes a P region, which includes a higher number of fins (causing a higher drive strength for the P region) as compared to a lower number of fins (causing a lower drive strength) for the N region of the cell. Similarly, another cell includes a N region, which includes a higher number of fins (causing a higher drive strength for the N region) as compared to a lower number of fins (causing a lower drive strength) for the P region of the cell. The difference in number of fins in the P and N regions of a cell can be as low as one, to as high as nine.

[0049] According to an embodiment, a cell may be termed or called as a cell having a stronger N, i.e. when the N region of the cell has a higher drive strength (as compared to a P region of the cell). Similarly, a cell may be termed or called as a cell having a stronger P, when the P region of the cell has higher drive strength (as compared to a N region of the cell).

[0050] It will be evident from above description that the cells classified or differentiated as either a cell having a stronger N or a cell having a stronger P. In other words, as explained herein above the term “cell type” is referred to as a cell having a stronger N or a cell having a stronger P. Therefore, according to the method 100, when a cell type is selected for two or more positions for cells of the datapath, it means selection of either one stronger N cell or one stronger P cell for each of the two or more positions for cells in the datapath. This causes a hybrid nature of the datapath. Notably, physically embodying the hybrid nature of the datapath is caused by selecting different type of cells, i.e. stronger N or stronger P cells, constituting the datapath. In the method 100, the cell type is selected in dependence of a switching point of a preferred edge to be used in the operation.

[0051] At step 102, the cell type is selected in dependence of a switching point of a preferred edge to be used in the operation. Specifically, the cell type for the two or more positions for cells in the datapath is selected based on the switching point of the preferred edge to be used in the operation. As explained herein above, each cell has a rising edge and a falling edge, and each cell is able to perform an operation. Therefore, the term “preferred edge” is referred to an edge, i.e. either the rising edge or the falling edge of the cell, which gets triggered or activated for performing the operation of the cell. Accordingly, selection based on the switching point of the preferred edge means selection of cells for the two or more positions in the datapath is based on preferred edge (that triggers the operation) of the cell. It will be evident that the preferred edge is either the rising edge or of the falling edge of the cell.

[0052]As explained herein above, each cell is associated with a cell type, i.e. stronger N or stronger P. Therefore, selection of the cell type based on the switching point of the preferred edge means selection of either stronger N or stronger P cells for the two or more positions for the cells in the datapath. According to an embodiment, each of the two or more positions for the cells in the datapath is either a position that is rising edge dominated or a position that is falling edge dominated. The term “rising edge dominated” referred to an operational attribute of a cell, i.e. a cell that can perform the operation when its rising edge is selected. Similarly, “falling edge dominated” referred to an operational attribute of a cell, i.e. a cell that can perform the operation when its falling edge is selected. Therefore, it will be evident that the two or more positions, each either being rising edge dominated or falling edge dominated, for the cells of the datapath will be occupied either by the stronger N or stronger P cells. Further, selection of either the stronger N or stronger P cells, would depend on logical need, i.e. the switching point of the preferred edge to be used in the operation, for the datapath.

[0053] According to an embodiment, the method 100 comprises selecting a cell having a stronger N, for example by having the higher number of fins in the N region than in the P region, for the position that is falling edge dominated. In other words, any of the two or more positions, for cells in the datapath, which is falling edge dominated would be occupied by the cell (or cell type) having the stronger N.

[0054] According to another embodiment, the method 100 comprises selecting a cell having a stronger P, for example by having the higher number of fins in the P region than in the N region, for the position that is rising edge dominated. In other words, any of the two or more positions, for cells in the datapath, which is rising edge dominated would be occupied by the cell (or cell type) having the stronger P.

[0055] It may be evident that, the cells in the datapath may be arranged or positioned in different ways. For example, the similar cells may be positioned adjacent to each other in the datapath or dissimilar cells may be positioned adjacent to each other in the datapath. Further, the number of cell types (i.e. stronger P or stronger N) may be same or different in the datapath. [0056]As explained herein above, the datapath includes the two or more positions for the cells. According to an embodiment, the method 100 comprises selecting a cell wherein the P region has a higher drive strength than the N region for a first one of the positions, and a cell wherein the N region has a higher drive strength than the P region for a second one of the positions. In an exemplary embodiment, the datapath at basic level is essentially constituted by two positions for the cells (or by the two cells). In such instance, a first position in the datapath may be occupied by the cell that has the P region having the higher drive strength than the N region, and a second position in the datapath may be occupied by the cell that has the N region having a higher drive strength than the P region. The first position in the datapath may be associated with, an output of a memory unit that acts as an input for the datapath. Alternatively, the first position in the datapath may be occupied by the cell that has the N region having the higher drive strength than the P region, and the second position may be occupied by the cell that includes the N region having a higher drive strength than the P region.

[0057] In an example, the datapath may include more than two positions for the cells. In such an instance, the datapath comprises a plurality of positions for cells and the number of cells having a stronger N is balanced with the number of cells having a stronger P in the datapath. Specifically, the datapath includes the plurality of positions for the cells, but even number for such positions, such that number of the cells having the stronger N is equal to the number of the cells having the stronger P in the datapath. For example, the equal number of the stronger N and stronger P cells are arranged or positioned in an alternate manner in the datapath, i.e. dissimilar cells are positioned alternately. Alternatively, the equal number of the stronger N and stronger P cells are arranged or positioned in a random manner in the datapath.

[0058] According to an embodiment, the method 100 comprises selecting a cell having a stronger N as the last cell in the datapath if the first cell in the datapath has a stronger P, and selecting a cell having a stronger P as the last cell in the datapath if the first cell in the datapath has a stronger N. As explained herein, the equal number of the stronger N and stronger P cells may be arranged alternately or randomly in the datapath, however in any such instance, if a first position in the datapath is occupied by the cell having the stronger N then a last position in the datapath is occupied by the cell having the stronger P. Alternatively, even when the number of the stronger N and stronger P cells are unequal similar arrangement of cells in the datapath may be followed.

[0059] In one embodiment, the method 100 comprises selecting cells having the same physical footprint for the two or more cells. The term ‘physical footprint’ refers to a structural attribute of a cell, which includes cell dimensions and cell geometry (shape). Optionally, the physical footprint of the cell may include materials to be used for manufacturing the cell. In an example, the cells (either stronger N or stronger P) of the present disclosure have the same physical footprint. The same physical footprint for the cells provides convenience in designing the datapath. For example, the two or more positions for the cells may be selected and/or altered using different cell types based on the datapath requirement. The selection and alteration of the cells may be managed by ‘Engineering Change Orders’ (ECO), which compensate for design errors during debugging phase or alterations made to the design specification to compensate for problems in the system design. To exploit the advantages of ECO, the method 100 is made fully ECO compatible by preserving the same cell footprint. It can be applied at any stage of design flow, such as RTL-to-gate synthesis, technology migration, placement, and post-P&R ECO stage.

[0060] It will be evident that, the method 100 enables in designing a datapath between two memory units based on the data to be transferred therebetween. For example, the designing of the datapath may be based on an output of a memory unit connected to the datapath. For example, a first memory unit may be connected to one end (i.e. a first or a proximal end) of the datapath for transferring the data to a second memory unit connected to another end (i.e. a second or a distal end) of the datapath. Therefore, based on the output, which can be one of a boolean value (0 and 1), either cell having the stronger N, or the stronger P is selected for the datapath. For example, if the output of a cell in this datapath is 0 then stronger N (corresponding to the rising edge dominated position for the next connected cell in the datapath) may be selected for designing the datapath. Alternatively, if the output of a cell in this datapath is 1 then stronger P (corresponding to the falling edge dominated position for the next connected cell in the datapath) may be selected. In accordance with an embodiment of the present disclosure, the aspect of “falling edge dominated” and “rising edge dominated” may be read in conjunction with a falling edge and rising edge of a clock signal associated with (or used for triggering) the first memory unit.

[0061] Referring now to FIG. 2, illustrated is a block diagram of a semiconductor component 200, in accordance with an embodiment of the present disclosure. The semiconductor component 200 comprises a first and a second memory units 202, 204 and a datapath 210 between the memory units 202, 204. The datapath 210 comprises two or more cells 212, 214. The datapath 210 is constituted by employing cells 212, 214 that is a hybrid library of cells. It will be evident that the datapath 210 between the memory units 202, 204 may be designed using the method 100, explained herein above. [0062] Each cell 212, 214 is arranged to perform an operation. The operation is the ability to transfer data, i.e. logic voltage levels corresponding to a digital signal. Further, each cell has a rising edge and a falling edge, and a P region and an N region and being P/N imbalanced. The rising and falling edges of the cells 212, 214 are operational aspects of the cells 212, 214 with respect to processing of the digital signal, which is better explained herein later in conjunction with FIG. 4. For example, the rising and falling edges of the cells 212, 214 may relate to operational states of the cells 212, 214, i.e. boolean value (corresponding to logic voltage levels) associated with the digital signal.

[0063] The cells 212, 214 of the present disclosure are semiconductor devices, therefore the P region and the N region thereof may be referred to as portions of the cells 212, 214 having p-doped portion and n-doped portion. Further, the P/N imbalanced of the cells 212, 214 relates to difference in structural and functional attributes of the P and N regions. According to an embodiment, the P/N imbalanced of the cells is caused by having different drive strengths. Further, the cells 212, 214 are configured to have different drive strengths for the P region and the N region thereof based on a number of fins present in the P region and the N region thereof. For example, the cell 212 of the present disclosure includes a N region, which includes a higher number of fins (causing a higher drive strength for the N region) as compared to a lower number of fins (causing a lower drive strength) for the P region, which is better explained herein later in conjunction with FIG. 3. Similarly, the cell 214 includes a P region, which includes a higher number of fins (causing a higher drive strength for the P region) as compared to a lower number of fins (causing a lower drive strength) for the N region 212.

[0064] In the datapath 210, each cell type being selected in dependence of the switching point of the rising edge or of the falling edge of the cell. The cell type of the cells 212, 214 is either a cell having a stronger N or a cell having a stronger P. As explained herein above, the cell 212 includes a N region having the higher number of fins (causing a higher drive strength for the N region as compared to P region thereof). Therefore, the cell 212 can be called or termed as cell having a stronger N. Similarly, the cell 214 includes a P region having the higher number of fins (causing a higher drive strength for the P region as compared to N region thereof). Therefore, the cell 214 can be called or termed as cell having a stronger P.

[0065] Further, the cell type (i.e. stronger N, for example the cell 212, or stronger P, for example the cell 214) in the datapath 210 is selected based on the switching point of the rising edge or of the falling edge of the cells 212, 214. Moreover, the cell type in the datapath 210 is selected depending on whether the rising edge or the falling edge to be used in the operation. As explained herein above, each of the cells 212, 214 has a rising edge and a falling edge, and each of the cells 212, 214 is able to perform an operation. Therefore, the selection based on the switching point of the rising edge or of the falling edge of a cell means selection of either a cell having the stronger N or a cell having the stronger P for the datapath 210.

[0066] Additionally, the datapath 210 has two or more positions for cells, and each position being one of a rising edge dominated or a falling edge dominated. The term “rising edge dominated” referred to an operational attribute of a cell, i.e. a cell that can perform the operation when its rising edge is selected. Similarly, the term “falling edge dominated” referred to an operational attribute of a cell, i.e. a cell that can perform the operation when its falling edge is selected. Therefore, the datapath 210 include cells having either stronger N or stronger P, which can be falling edge dominated or rising edge dominated, respectively. Moreover, selection of either the stronger N or stronger P cells, would depend on logical need, i.e. depending on whether the rising edge or the falling edge to be used in the operation (data transfer) for the datapath 210, which will be better explained in conjunction with FIG. 4.

[0067] FIG. 2, typically illustrates a combinatorial datapath 210 of cells 212, 214 across the two memory units 202, 204. The datapath 210 employs a hybrid library assignment i.e. using either stronger P or stronger N cell libraries at each stage of the datapath 210. The hybrid cell library assignment is the selective utilization of a cell library to exploit the rising edge and the falling edge characteristic to be used in the operation of the two or more cells 212, 214. As shown in FIG. 2, the first, third and fifth cells of the datapath 210 are the cells 212 having stronger N, which is employed to exploit the falling edge characteristic of the cells 212. Similarly, the second and fourth cells of the datapath 210 are the cells 214 having stronger P, which is employed to exploit the rising edge characteristic of the cells 214. This shows the aspect of hybrid library of cells for the datapath 210. Further, the hybrid library assignment comprises satisfying transition points of stronger N to stronger P (and vise- versa) to reduce delay in propagation of data from the first memory unit 202 to the second memory unit 204. Further, the datapath 210 maintains a balance in number of types of cells (i.e. stronger N vs stronger P) to provide 50% duty cycle and thereby improving a noise margin of entire datapath 210 such that no glitch is propagated and captured by the second memory unit 204 at the end of datapath 210 when data is transferred from the first memory unit 202.

[0068] According to an embodiment, the semiconductor component 200 comprises one or more cells wherein the P region has a higher drive strength than the N region and one or more cells wherein the N region has a higher drive strength than the P region. Essentially, the datapath 210 of the semiconductor component 200 comprises at least two cells (such as cells 212, 214), out of which one cell (such as the cell 212) has the N region having a higher drive strength than the P region (i.e. strong N), and another cell (such as the cell 214) has the P region having a higher drive strength than the N region (i.e. strong P). Alternatively, the datapath 210 can include more than two cells as shown in FIG. 2.

[0069] In an embodiment, the semiconductor component 200 comprises a cell having a stronger N, for example by having a higher number of fins in the N region than in the P region, for at least one position in the datapath 210 that is falling edge dominated. In other words, for the at least one position in the datapath 210 that is falling edge dominated, that position would be occupied by a cell (such as the cell 212) having the stronger N. It will be evident that based on number of positions in the datapath 210 that are falling edge dominated, the datapath 210 would include corresponding number of cells 212 having the stronger N. As shown in FIG. 2, the datapath 210 includes three cells 212 having strong N, at first, third and fifth positions of the datapath 210.

[0070] In another embodiment, the semiconductor component 200 comprises a cell having a stronger P, for example by having a higher number of fins in the P region than in the N region, for at least one position in the datapath 210 that is rising edge dominated. In other words, for the at least one position in the datapath 210 that is rising edge dominated, that position would be occupied by a cell (such as the cell 214) having the stronger P. It will be evident that based on number of positions in the datapath 210 that are rising edge dominated, the datapath 210 would include corresponding number of cells 214 having the stronger P. As shown in FIG. 2, the datapath 210 includes two cells 214 having strong P, at second and fourth positions of the datapath 210.

[0071] It may be evident that, a datapath (such as the datapath 210) may include plurality of cells, which may be arranged or positioned in different ways. For example, the similar cells may be positioned adjacent to each other in a datapath or dissimilar cells may be positioned adjacent to each other in a datapath. Further, the number of cell types (i.e. stronger P or stronger N) may be same or different in a datapath.

[0072] According to an embodiment, the datapath (such as the datapath 210) comprises a plurality of positions for cells and the number of cells having a stronger N is balanced with the number of cells having a stronger P in the datapath. Specifically, the datapath 210 includes two or more cells 212, 214, but in even number, i.e. number of the cells having the stronger N is equal to the number of the cells having the stronger P for the datapath 210. In such instance, the equal number of the stronger N and stronger P cells are arranged or positioned in an alternate manner in the datapath 210, i.e. dissimilar cells are positioned alternately. Alternatively, the equal number of the stronger N and stronger P cells are arranged or positioned in a random manner in the datapath 210.

[0073] In an embodiment, the semiconductor component 200 comprises selecting a cell having a stronger N as the last cell in the datapath 210 if the first cell in the datapath 210 has a stronger P, and selecting a cell having a stronger P as the last cell in the datapath 210 if the first cell in the datapath 210 has a stronger N. As explained herein, the equal number of the stronger N and stronger P cells may be arranged alternately or randomly in the datapath 210, however in any such instance, if a first position in the datapath 210 is occupied by the cell having the stronger N then a last position in the datapath 210 is occupied by the cell having the stronger P. Alternatively, even when the number of the stronger N and stronger P cells are unequal similar arrangement of cells in the datapath 210 may be followed.

[0074] According to an embodiment, in the semiconductor component 200 all cells have a same physical footprint. The physical footprint of the cells refers to a structural attribute of a cell, which includes cell dimensions and cell geometry (shape). Optionally, the physical footprint of the cells may also include materials to be used for manufacturing of the cell. The cells (either stronger N or stronger P, i.e. cells 212, 214 respectively) of the present disclosure have the same physical footprint, i.e. same cell dimensions and cell geometry. However, the cells having stronger N or stronger P would be structurally different based on the number of fins in the P and N regions of such cells and size of the P and N regions of such cells.

[0075] In one embodiment, in the semiconductor component 200 the two memory units 202, 204 are flip-flops. The flip-flops 202, 204 are implemented for synchronizing variable input signals and for counting the number of pulses in the datapath 210 over a period of time. The flip-flops 202, 204 of the present disclosure are edge-triggered or synchronous. Additionally, the semiconductor component 200 can be a processor or a memory chip.

[0076] Referring now to FIG. 3, illustrated is stick diagram of cells, such as the cells 212, 214 (i.e. stronger N or stronger P, respectively, shown in FIG. 2), in accordance with an embodiment of the present disclosure. It may be evident that the arrangement of the cells 212, 214 as depicted in FIG. 3 may constitute a datapath 210. In other words, the arrangement of the cells 212, 214 may be considered as a hybrid cell library defining the datapath 210.

[0077] As shown, FIG. 3 illustrates the two cells 212 having a stronger N and a stronger P, positioned between the two cells 212, 214. Each of the cells 212, 214 includes various parts, depicted using various hatches. Each of the cells 212 include a N region 302 and P region 304. Similarly, the cell 214 include a N region 312 and P region 314. The N regions 302 of the cells 212 is shown to include two fins 322, and P region 304 of the cells 212 is shown to include one fin 324. The cells 212 are having stronger N because number of fins in the N regions 302 is two, that is more than number of fins in the P regions 304, which is one. Therefore, the N regions 302 of the cells 212 will have higher drive strength than P regions 304 of the cells 214. Also, the cells 212 would correspond to a position in a datapath 210 that is falling edge dominated. Similarly, the cell 214 is having stronger P because number of fins in the P region 314 (is two), that is more than number of fins in the N region 312, which is one. Therefore, the P region 314 of the cell 214 will have higher drive strength than N region 312 of the cell 214. Also, the cells 214 would correspond to a position in a datapath 210 that rising edge dominated. Each of the cells 212, 214 are further shown to include various parts such as, metal layer (i.e. M0), self-aligned contact (SAC), metal port (MP) and polyoxide layers (PO), shown using different hatches or patterns.

[0078] Referring now to FIG. 4, illustrated are rising and falling edges of the cells 212, 214 shown in FIG. 3, in accordance with an embodiment of the present disclosure. As shown, the rising and falling edges 402, 404 corresponds to the two cells 212 (shown in FIG. 3) having stronger N. Further, the falling edges 404 of the cells 212 are dominant edges, accordingly, the cells 212 corresponds to positions in datapath 210 that is falling edge dominated. As explained herein above with FIG. 3, the N regions 302 of the cells 212 will have higher drive strength (more number of fins) than the P regions 304, therefore the falling edges 404 of the cells 212 are dominant edges as compared to the rising edges 402 of the cells 212.

[0079] FIG. 4, also illustrates the rising and falling edges 412, 414 corresponding to the cell 214 (shown in FIG. 3) having stronger P. The rising edges 412 of the cell 214 is dominant edge, accordingly, the cell 214 corresponds to a position in datapath 210 that is rising edge dominated. As explained herein above with FIG. 3, the P regions 314 of the cell 214 will have higher drive strength (more number of fins) than the N regions 312, therefore the rising edges 412 of the cell 214 is dominant edge as compared to the falling edges 414 of the cell 214.

[0080] FIG. 4 also illustrates the triggering points of each of the rising and falling edges 412, 414. As shown, the points marked on each of the edges 412, 414 of the datapath 210 represent the point of triggering along the datapath 210. Typically, the point of triggering refers to the instance when the input is taken along the datapath 210. Moreover generally, the timing for transitioning a signal between different clock levels is different for different values of the input signal. As a result, the different transition times cause the duty cycle of the input signal to lengthen or shorten as the signal crosses between two input domains (for example voltage domain). Beneficially, the method 100 employs a hybrid library assignment to exploit the preferred edge characteristic of each of the cells 212, 214 during transitioning. Said hybrid library assignment enables maintaining a high noise margin and/or the logic cells not to be impacted by a glitch.

[0081] Modifications to embodiments of the present disclosure described in the foregoing are possible without departing from the scope of the present disclosure as defined by the accompanying claims. Expressions such as "including", "comprising", "incorporating", "have", "is" used to describe and claim the present disclosure are intended to be construed in a non-exclusive manner, namely allowing for items, components or elements not explicitly described also to be present. Reference to the singular is also to be construed to relate to the plural. The word "exemplary" is used herein to mean "serving as an example, instance or illustration". Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments and/or to exclude the incorporation of features from other embodiments. The word "optionally" is used herein to mean "is provided in some embodiments and not provided in other embodiments". It is appreciated that certain features of the present disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable combination or as suitable in any other described embodiment of the disclosure.

Claims

1. A method (100) of designing a datapath (210) between two memory units (202, 204) in a semiconductor component (200), the datapath (210) comprising two or more positions for cells (212, 214), each cell having a rising edge (402, 412) and a falling edge (404, 414), the method (100) comprising selecting for each of the two or more positions a cell type from a library comprising available cells, each available cell being able to perform an operation, and each cell having a P region (304, 314) and an N region (302, 312) and being P/N imbalanced, wherein the cell type is selected in dependence of a switching point of a preferred edge to be used in the operation, wherein the preferred edge is either the rising edge (402, 412) or the falling edge (404, 414) of the cell.

2. A method (100) according to claim 1, comprising selecting a cell (214) wherein the P region (314) has a higher drive strength than the N region (312) for a first one of the positions and a cell (212) wherein the N region (302) has a higher drive strength than the P region (304) for a second one of the positions.

3. A method (100) according to any one of the preceding claims, comprising selecting a cell (212) having a stronger N, for example by having a higher number of fins (322) in the N region (302) than in the P region (304), for a position that is falling edge dominated.

4. A method (100) according to any one of the preceding claims, comprising selecting a cell (214) having a stronger P, for example by having a higher number of fins (334) in the P region (314) than in the N region (312), for a position that is rising edge dominated.

5. A method (100) according to any one of the preceding claims, wherein the datapath comprises a plurality of positions for cells (312, 314) and the number of cells (312) having a stronger N is balanced with the number of cells (314) having a stronger P in the datapath.

6. A method (100) according to any one of the preceding claims, comprising selecting a cell (212) having a stronger N as the last cell in the datapath if the first cell in the datapath has a stronger P, and selecting a cell (214) having a stronger P as the last cell in the datapath if the first cell in the datapath has a stronger N.

7. A method (100) according to any one of the preceding claims, comprising selecting cells (212, 214) having the same physical footprint for the two or more cells.

8. A method (100) according to any one of the preceding claims, wherein the memory units (202, 204) are flip-flops.

9. A semiconductor component (200) comprising a first and a second memory units (202, 204) and a datapath (210) between the memory units (202, 204), the datapath (210) comprising two or more cells (212, 214), each cell being arranged to perform an operation and having a rising edge (402, 412) and a falling edge (404, 414) and a P region (304, 314) and an N region (302, 312) and being P/N imbalanced, each cell type being selected in dependence of the switching point of the rising edge (402, 412) or of the falling edge (404, 414) of the cell, depending on whether the rising edge (402, 412) or the falling edge (404, 414) to be used in the operation.

10. A semiconductor component (200) according to claim 9, comprising one or more cells (214) wherein the P region (314) has a higher drive strength than the N region (312) and one or more cells (212) wherein the N region (302) has a higher drive strength than the P region (304).

11. A semiconductor component (200) according to any one of the claims 9 - 10, comprising a cell (212) having a stronger N, for example by having a higher number of fins (322) in the N region (302) than in the P region (304), for at least one position in the datapath (210) that is falling edge (404) dominated.

12. A semiconductor component (200)according to any one of the claims 9 - 11 , comprising a cell (214) having a stronger P, for example by having a higher number of fins (334) in the P region (314) than in the N region (312), for at least one position in the datapath that is rising edge (412) dominated.

13. A semiconductor component (200) according to any one of the claims 9 - 12, wherein the datapath comprises a plurality of positions for cells (312, 314) and the number of cells (312) having a stronger N is balanced with the number of cells (314) having a stronger P in the datapath.

14. A semiconductor component (200) according to any one of the claims 9 - 13, comprising selecting a cell (212) having a stronger N as the last cell in the datapath if the first cell in the datapath has a stronger P, and selecting a cell (214) having a stronger P as the last cell in the datapath if the first cell in the datapath has a stronger N.

15. A semiconductor component (200) according to any one of the claims 9 - 14, wherein all cells (212, 214) have a same physical footprint.

16. A semiconductor component (200) according to any one of the claims 9 - 15, wherein the two memory units (202, 204) are flip-flops.