WO2021256053A1 - Light emission device and distance measurement device - Google Patents

Light emission device and distance measurement device Download PDF

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Publication number
WO2021256053A1
WO2021256053A1 PCT/JP2021/014391 JP2021014391W WO2021256053A1 WO 2021256053 A1 WO2021256053 A1 WO 2021256053A1 JP 2021014391 W JP2021014391 W JP 2021014391W WO 2021256053 A1 WO2021256053 A1 WO 2021256053A1
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WIPO (PCT)
Prior art keywords
conductive layer
light
light source
emitting device
light emitting
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PCT/JP2021/014391
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French (fr)
Japanese (ja)
Inventor
博隆 上野
廉 森本
秀夫 大住
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パナソニックＩｐマネジメント株式会社
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Publication of WO2021256053A1 publication Critical patent/WO2021256053A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/483—Details of pulse systems
    • G01S7/484—Transmitters

Definitions

  • the present invention relates to a light emitting device that emits pulsed light and a distance measuring device that measures a distance to an object using the pulsed light emitted from the light emitting device.
  • a distance measuring device that measures a distance to an object using pulsed light whose intensity changes in a pulse shape.
  • the distance to an object is measured based on the time difference between the timing of emitting the pulsed light and the timing of receiving the reflected light from the object of the pulsed light.
  • Patent Document 1 describes this kind of distance measuring device.
  • the distance measuring device having the above configuration, high intensity and short pulse pulse emission is required in order to improve the distance measurement accuracy.
  • the light source and its drive circuit are mounted on a circuit board, there is a parasitic inductance based on the wiring of the drive circuit, and this parasitic inductance deteriorates the peak intensity and pulse width of the pulsed light.
  • the parasitic inductance can be suppressed by shortening the wiring of the drive circuit, but there is a limit to the suppression of the parasitic inductance by shortening the wiring.
  • the first aspect of the present invention relates to a light emitting device.
  • the light emitting device includes a light source, a power storage element for supplying a drive current to the light source, a switch element for switching between light emission and non-light emission of the light source, and the light source, the power storage element, and the switch element. It is provided with a circuit board to be used.
  • the circuit board includes a first conductive layer for connecting the light source, the power storage element, and the switch element in series, and a second conductive layer arranged so as to face the first conductive layer at a predetermined distance.
  • a connecting portion that connects the first conductive layer and the second conductive layer and causes the drive current to flow through the second conductive layer in a direction opposite to the flow direction of the drive current of the first conductive layer. Have.
  • a driving current flows in the first conductive layer and the second conductive layer in opposite directions to each other. Therefore, the mutual inductance between the first conductive layer and the second conductive layer reduces the parasitic inductance of the path through which the drive current flows. Therefore, deterioration of the characteristics of the pulsed light due to the parasitic inductance can be suppressed.
  • the second aspect of the present invention relates to a distance measuring device.
  • the distance measuring device receives the light emitting device according to the first aspect, the projection optical system that projects the pulsed light emitted from the light emitting device onto the target region, and the reflected light from the object of the pulsed light. It is provided with a light receiving unit and a light receiving unit.
  • the distance measuring device since the light emitting device according to the first aspect is provided, deterioration of the characteristics of the pulsed light due to the parasitic inductance can be suppressed. Therefore, the accuracy of distance measurement can be improved.
  • a third aspect of the present invention relates to a light emitting device.
  • the light emitting device includes a light source, a current source for supplying a drive current to the light source, a switch element for switching between light emission and non-light emission of the light source, and the light source, the current source, and the switch element. It is provided with a circuit board to be used.
  • the circuit board includes a first conductive layer for connecting the light source, the current source, and the switch element in series, and a second conductive layer arranged so as to face the first conductive layer at a predetermined distance.
  • a connecting portion that connects the first conductive layer and the second conductive layer and causes the drive current to flow through the second conductive layer in a direction opposite to the flow direction of the drive current of the first conductive layer. Have.
  • the present invention it is possible to provide a light emitting device and a distance measuring device capable of suppressing deterioration of the characteristics of pulsed light due to parasitic inductance.
  • FIG. 1 is a circuit diagram showing a configuration of a light emitting device according to an embodiment.
  • FIG. 2 is a diagram showing a simulation result obtained by simulating the intensity of pulse emission when the light source is driven by a rectangular pulse signal according to the embodiment.
  • 3A and 3B are diagrams schematically showing the upper surface and the lower surface of the circuit board according to the embodiment, respectively.
  • FIG. 3 (c) is a cross-sectional view of the region of FIG. 3 (a) according to the embodiment when the region is cut along the AA'line.
  • FIG. 4A is a diagram illustrating a parasitic inductance when a current flows through one conductor according to the embodiment.
  • FIG. 4B is a diagram illustrating the parasitic inductance when a current flows through the two conductors according to the embodiment.
  • FIG. 5A is a graph showing a simulation result obtained by simulation for the frequency response of the entire parasitic inductance generated from the first conductive layer and the second conductive layer according to the embodiment.
  • FIG. 5B shows that, according to the embodiment, when the frequency of the drive current is 100 MHz, the total parasitic inductance generated from the first conductive layer and the second conductive layer is between the first conductive layer and the second conductive layer. It is a graph which shows the simulation result which obtained the state which changes according to the change of the interlayer distance of.
  • FIG. 6 is a block diagram showing a configuration of a distance measuring device according to an embodiment.
  • FIG. 7 is a diagram schematically showing the upper surface of the circuit board according to the first modification.
  • 8 (a) and 8 (b) are views schematically showing the upper surface and the lower surface of the circuit board according to the second modification, respectively.
  • FIG. 1 is a circuit diagram showing the configuration of the light emitting device 1.
  • the light emitting device 1 includes a power storage element 11, a light source 12, a switch element 13, a resistor 14, a driver 15, a DC power supply 16, and a pulse generation circuit 17.
  • the power storage element 11, the light source 12, the switch element 13, the resistor 14, and the driver 15 are mounted on the circuit board 2.
  • the power storage element 11 is composed of one capacitor and is connected to the DC power supply 16 via a resistor 14. Charges are accumulated in the power storage element 11 according to the time constant of the circuit including the resistor 14 and the power storage element 11.
  • the power storage element 11 supplies a drive current to the light source 12 according to the conduction of the switch element 13.
  • the light source 12 is a laser diode.
  • the light source 12 emits laser light when a drive current is supplied from the power storage element 11.
  • the light source 12 may be another light emitting element such as an LED (Light Emitting Diode).
  • the switch element 13 is switched between a conductive state and a non-conducting state according to the signal from the driver 15.
  • the switch element 13 is, for example, a FET (Field Effect Transistor).
  • the switch element 13 may be composed of other elements that can be switched between a conductive state and a non-conducting state according to a signal from the driver 15.
  • the switch element 13 switches the light source 12 between a light emitting state and a non-light emitting state by a signal from the driver 15. That is, when the switch element 13 becomes conductive, a drive current is supplied from the power storage element 11 to the light source 12, and the light source 12 emits light. Further, when the switch element 13 becomes non-conducting, the supply of the drive current to the light source 12 is cut off, and the light source 12 is turned off.
  • the driver 15 drives the switch element 13 in response to the pulse signal input from the pulse generation circuit 17.
  • the switch element 13 is an FET
  • the driver 15 supplies a drive signal to the gate of the FET during the period when the pulse signal is rising.
  • the drive current is supplied to the light source 12 during the rising period of the pulse signal, and the light source 12 emits pulse light.
  • the light emitting device 1 having the above configuration When the light emitting device 1 having the above configuration is mounted on a distance measuring device, high intensity and short pulse pulse light emission is required in order to improve the distance measurement accuracy.
  • the power storage element 11, the light source 12, and the switch element 13 are mounted on the circuit board 2, the parasitic inductances LP1 and LP2 based on the wiring on the circuit board 2 exist, and the parasitic inductance LP1, The LP2 deteriorates the peak intensity and the pulse width of the pulsed light.
  • the drive flowing through the light source 12 is used.
  • the current (LD current), the pulse width of the pulse light source (the width in the range of 1 / e 2 or more of the peak intensity), and the pulse rise characteristic are calculated by the following equations (1) to (3), respectively.
  • LD current V BUS ⁇ ⁇ (C BUS / LP TOTAL )... (1)
  • Pulse width ⁇ ⁇ ⁇ (C BUS ⁇ LP TOTAL )...
  • Pulse rise characteristic 1 / (2 ⁇ ⁇ ⁇ (C BUS ⁇ LP TOTAL ))... (3)
  • V BUS is the voltage value of the DC power supply 16
  • C BUS is the capacity value of the power storage element 11.
  • FIG. 2 is a diagram showing a simulation result obtained by simulating the intensity of pulse emission when the light source 12 is driven by a rectangular pulse signal.
  • the peak intensity P2 of the pulsed light when the parasitic inductance LP0 is 2.8 nH is lower than the peak intensity P1 of the pulsed light when the parasitic inductance LP0 is 1.5 nH.
  • the pulse width W2 of the pulsed light when the parasitic inductance LP0 is 2.8 nH is wider than the pulse width W1 of the pulsed light when the parasitic inductance LP0 is 1.5 nH.
  • the pulse rising characteristic Tr2 of the pulsed light when the parasitic inductance LP0 is 2.8 nH is slower than the pulse rising characteristic Tr1 of the pulsed light when the parasitic inductance LP0 is 1.5 nH. As described above, as the parasitic inductance LP0 increases, the characteristics of the pulsed light deteriorate.
  • the parasitic inductance L0 is suppressed by devising the configuration of the circuit board 2.
  • this configuration will be described.
  • FIGS. 3A to 3C are diagrams schematically showing the upper surface and the lower surface of the circuit board 2, respectively.
  • FIG. 3C is a cross-sectional view taken along the line AA'of the region A1 of FIG. 3A.
  • X, Y, and Z axes orthogonal to each other are added.
  • the X-axis and the Y-axis are parallel to the two orthogonal sides of the square-shaped circuit board 2, respectively.
  • the Z-axis direction is the thickness direction of the circuit board 2.
  • the circuit board 2 includes a rectangular region A1 and a region A2 arranged outside the region A1.
  • Regions A1 and A2 each have their own ground. That is, the ground of the region A1 and the ground of the region A2 are connected at a certain place, and the impedance between the ground of the region A1 and the ground of the region A2 becomes high in the high frequency region.
  • the power storage element 11, the light source 12, and the switch element 13 of FIG. 1 are mounted in the region A1.
  • the resistor 14 and the driver 15 of FIG. 1 are mounted in the region A2. In FIGS. 3A and 3B, the resistance 14 and the driver 15 are not shown.
  • a first conductive layer 21 for connecting the power storage element 11, the light source 12, and the switch element 13 in series is formed on the upper surface of the region A1.
  • the first conductive layer 21 is composed of four wiring portions 21a, 21b, 21c, and 21d.
  • the first conductive layer 21 is made of, for example, a copper foil having a predetermined thickness.
  • the power storage element 11, the light source 12, and the switch element 13 are arranged on a straight line parallel to the X axis. Therefore, the first conductive layer 21 extends parallel to the X axis, and the wiring portions 21a, 21b, 21c, and 21d are arranged parallel to the X axis.
  • the width of the wiring portions 21a, 21b, 21c, 21d in the Y-axis direction is equal to the width of the region A1 in the Y-axis direction.
  • the length of the first conductive layer 21 in the X-axis direction is equal to the length of the region A1 in the X-axis direction.
  • a second conductive layer 22 is formed on the lower surface of the region A1.
  • the second conductive layer 22 constitutes the ground of the circuit arranged on the upper surface of the region A1.
  • the second conductive layer 22 has a long rectangular shape parallel to the X-axis.
  • the width of the second conductive layer 22 in the Y-axis direction is equal to the width of the region A1 in the Y-axis direction
  • the length of the second conductive layer 22 in the X-axis direction is equal to the length of the region A1 in the X-axis direction.
  • the width of the region A1 in the Y-axis direction (direction perpendicular to the flow of the drive current) is wider than the width of the power storage element 11, the light source 12, and the switch element 13 in the Y-axis direction. Therefore, the width of the second conductive layer 22 in the Y-axis direction is wider than the width of the power storage element 11, the light source 12, and the switch element 13 in the Y-axis direction, and the width of the first conductive layer 21 in the Y-axis direction is the power storage element. 11.
  • the width of the second conductive layer 22 in the Y-axis direction is the same as the width of the light source 12 and the switch element 13 in the Y-axis direction.
  • the first conductive layer 21 and the second conductive layer 22 are formed on the upper surface and the lower surface of the base material 24 which is the base of the circuit board 2, respectively.
  • the base material 24 is made of an insulating resin material. Therefore, the second conductive layer 22 is arranged to face the first conductive layer 21 at a predetermined distance corresponding to the thickness of the base material 24.
  • the wiring portions 21a and 21d at both ends of the X-axis of the first conductive layer 21 are electrically connected to the second conductive layer 22 by the connecting portions 23, respectively.
  • the connecting portion 23 is composed of, for example, vias.
  • the closed circuit is formed by the first conductive layer 21, the second conductive layer 22, and the two connecting portions 23. It is composed.
  • the drive current that has flowed through the first conductive layer 21 flows into the second conductive layer 22 through the connection portion 23 on the positive side of the X-axis, and flows through the second conductive layer 22 in the negative direction of the X-axis. After that, the drive current flows into the first conductive layer 21 through the connection portion 23 on the negative side of the X-axis.
  • a drive current flows in the first conductive layer 21 and the second conductive layer 22 in opposite directions to each other.
  • the two connecting portions 23 connect the first conductive layer 21 and the second conductive layer 22, and allow the drive current to flow through the second conductive layer 22 in the direction opposite to the flow direction of the drive current of the first conductive layer 21. Play a role.
  • the flow of the drive current in the opposite direction reduces the overall parasitic inductance generated by the first conductive layer 21 and the second conductive layer 22.
  • FIG. 4A is a diagram for explaining a parasitic inductance when a current flows through one conductor
  • FIG. 4B is a diagram for explaining a parasitic inductance when a current flows through two conductors.
  • the parasitic inductance L s of the conductor is calculated by the following equation (4).
  • the parasitic inductance L total of the entire conductor is expressed by the following equation (5).
  • the parasitic inductance L total of the entire two conductors is expressed by the following equation (7).
  • the magnitude of the mutual inductance M can be made closer to the parasitic inductance of a single conductor by making the distance d between the two conductors closer to the radius a of the conductor. Therefore, from the equation (7), by bringing the distance d between the two conductors closer to the radius a of the conductors , the total parasitic inductance L total generated by the two conductors can be brought closer to zero.
  • FIGS. 3 (a) to 3 (c) are equivalent to the configurations shown in FIGS. 4 (b). Therefore, by reducing the distance between the first conductive layer 21 and the second conductive layer 22, the total parasitic inductance generated from the first conductive layer 21 and the second conductive layer 22 can be brought close to zero.
  • FIG. 5A is a graph showing the simulation results obtained by simulating the frequency response of the entire parasitic inductance L0 generated from the first conductive layer 21 and the second conductive layer 22.
  • the horizontal axis is frequency and the vertical axis is inductance.
  • the horizontal axis corresponds to the pulse width of the drive current. That is, when the time length of the pulse width is 10 nsec, the frequency is 100 MHz.
  • the vertical axis is the magnitude of the parasitic inductance generated in the entire first conductive layer 21 and the second conductive layer 22 when the driving current flows through the first conductive layer 21 and the second conductive layer 22.
  • both the first conductive layer 21 and the second conductive layer 22 have the same square size in a plan view.
  • the length of each side of the first conductive layer 21 and the second conductive layer 22 is set to 20 mm
  • the thickness of the first conductive layer 21 and the second conductive layer 22 is set to 0.035 mm.
  • the relative permittivity and the dielectric loss tangent of the first conductive layer 21 and the second conductive layer 22 were set to 4.5 and 0.015, respectively.
  • the interlayer distance d between the first conductive layer 21 and the second conductive layer 22 was set to 0.3 mm.
  • the frequency of the drive current is 100 MHz (the time length of the pulse width is 10 nsec).
  • the overall parasitic inductance L0 was suppressed to about 1.03 nH.
  • the frequency of the drive current is about 50 MHz, which is slightly smaller than 100 MHz, the total parasitic inductance L0 is suppressed to about 1.05 nH, and the time length of the pulse width of the drive current is slightly longer than 10 nsec. It was confirmed that the total parasitic inductance generated from the conductive layer 21 and the second conductive layer 22 can be effectively suppressed.
  • the horizontal axis is the interlayer distance (mm) and the vertical axis is the parasitic inductance (nH).
  • the simulation conditions excluding the interlayer distance are the same as the simulation conditions of FIG. 5A.
  • the mutual inductance between the first conductive layer 21 and the second conductive layer 22 causes the first conductive layer 21 and the second conductive layer 21 to be conductive. It was confirmed that the total parasitic inductance of the layer 22 can be effectively reduced. As a result, deterioration of the characteristics of the pulsed light due to the parasitic inductance can be suppressed, and the light source 12 can be made to emit a pulse with a high intensity and a short pulse.
  • FIG. 6 is a block diagram showing the configuration of the distance measuring device 3.
  • FIG. 6 shows a so-called flash type distance measuring device 3.
  • the distance measuring device 3 includes a light emitting device 1, a projection optical system 30, a light receiving unit 40, a control unit 51, a signal processing unit 52, and a distance calculation unit 53.
  • the light emitting device 1 includes the above-mentioned light source 12 and a drive circuit 10.
  • the drive circuit 10 includes a circuit portion of the circuit shown in FIG. 1 excluding the light source 12.
  • the drive circuit 10 causes the light source 12 to emit light in pulses in response to a command from the control unit 51.
  • the configuration and operation for pulse emission are as described above.
  • the light source 12 is a laser diode and emits a laser beam (projected light) having a predetermined wavelength.
  • the emission wavelength of the light source 12 is set to, for example, an infrared wavelength band (for example, 905 nm).
  • the emission wavelength of the light source 12 may be appropriately changed depending on the usage mode of the distance measuring device 3.
  • the light source 12 may be an LED, a halogen lamp, or the like.
  • the projection optical system 30 is configured to guide the projected light emitted from the light source 12 to the ranging region A10 at a predetermined spread angle and to have a uniform intensity distribution in the ranging region A10.
  • the projection optical system 30 may consist of a single lens or may include a plurality of lenses. Further, the projection optical system 30 may include a concave mirror or the like.
  • the light receiving unit 40 receives the reflected light from the ranging area A10 and outputs a detection signal.
  • the light receiving unit 40 includes a light receiving optical system 41 and an image pickup element 42.
  • the light receiving optical system 41 collects the reflected light from the ranging region A10 and collects it on the light receiving surface 42a of the image pickup element 42.
  • the light receiving optical system 41 may consist of a single lens or may include a plurality of lenses. Further, the light receiving optical system 41 may include a concave mirror or the like.
  • the image sensor 42 receives reflected light by a plurality of pixels arranged on the light receiving surface 42a, and outputs a detection signal according to the intensity of the received reflected light.
  • a large number of pixels are arranged in a matrix on the light receiving surface 42a.
  • an avalanche photodiode is arranged in each pixel.
  • Other photodetection elements may be arranged in each pixel.
  • a filter that transmits the wavelength band of the projected light and blocks the light in other wavelength bands may be arranged between the light receiving optical system 41 and the image pickup element 42. As a result, it is possible to prevent unnecessary light having a wavelength different from that of the projected light from being incident on the light receiving surface 42a of the image pickup device 42. Further, when the light source 12 emits infrared light, the image pickup device 42 may have detection sensitivity only in the infrared wavelength band. As a result, it is possible to prevent the image sensor 42 from detecting visible light, which is unnecessary light.
  • the control unit 51 includes an arithmetic processing circuit and a memory, and is composed of, for example, an FPGA or an MPU.
  • the control unit 51 inputs a control signal to the drive circuit 10 and controls the light source 12 via the drive circuit 10.
  • the drive circuit 10 causes the light source 12 to emit a pulse with a predetermined intensity and pulse width according to the control signal. Further, the control unit 51 also inputs the control signal input to the drive circuit 10 to the distance calculation unit 53 at the same timing as the input to the drive circuit 10.
  • the signal processing unit 52 performs amplification and noise removal processing on the detection signal of each pixel output from the image sensor 42, and outputs the processed detection signal to the distance calculation unit 53.
  • the distance calculation unit 53 is a circuit that includes a calculation processing circuit and a memory and performs a distance calculation.
  • the distance calculation unit 53 is based on the timing at which the control signal is received from the control unit 51 in response to the pulse emission and the timing at which the detection signal of each pixel is received from the signal processing unit 52 for each pixel of the image pickup element 42.
  • the distance to the object in the distance measuring area A10 is calculated for each pixel.
  • the distance calculation unit 53 generates distance image data for one screen (one frame) in which the distance calculated for each pixel is mapped to the position of each pixel, and the generated distance image data is displayed on the distance measuring device 3. It is output to a unit or an external device of the distance measuring device 3.
  • the light emitting device 1 having the above configuration since the light emitting device 1 having the above configuration is provided, deterioration of the characteristics of the pulsed light due to the parasitic inductance can be suppressed, and high-intensity and short-pulse pulsed light can be projected onto the ranging region A10. Therefore, the accuracy of distance measurement can be improved.
  • a drive current flows in the first conductive layer 21 and the second conductive layer 22 in opposite directions to each other. Therefore, as described with reference to FIG. 4B, the mutual inductance M between the first conductive layer 21 and the second conductive layer 22 reduces the parasitic inductance of the path through which the drive current flows. Therefore, deterioration of the characteristics of the pulsed light due to the parasitic inductance can be suppressed.
  • the first conductive layer 21 and the second conductive layer 22 are also arranged. It will extend in one direction. Therefore, the lengths of the first conductive layer 21 and the second conductive layer 22 can be shortened, and the parasitic inductance of the first conductive layer 21 and the second conductive layer 22 can be reduced. Therefore, the parasitic inductance of the entire path through which the drive current flows can be remarkably reduced, and the deterioration of the pulsed light characteristics due to the parasitic inductance can be suppressed more reliably.
  • the width of the first conductive layer 21 and the width of the second conductive layer 22 are equal in the direction perpendicular to the flow of the drive current (Y-axis direction). In this way, by widening the width of the first conductive layer 21 to the width of the second conductive layer 22 in the direction perpendicular to the flow of the drive current, the self-inductance of the first conductive layer 21 can be reduced. Therefore, the parasitic inductance of the entire path through which the drive current flows can be easily reduced, and the deterioration of the pulsed light characteristics due to the parasitic inductance can be suppressed more reliably.
  • the distance measuring device 3 includes the light emitting device 1 shown in FIGS. 3A to 3C, and further, the pulsed light emitted from the light emitting device 1 is set to a target region (distance measuring region).
  • a projection optical system 30 for projecting to A10) and a light receiving unit 40 for receiving reflected light from an object of pulsed light are provided. Since the light emitting device 1 has the configurations shown in FIGS. 3A to 3C, deterioration of the characteristics of the pulsed light due to the parasitic inductance can be suppressed as described above. Therefore, the distance measuring device 3 can project high-intensity and short-pulse pulsed light onto the range-finding region A10. Therefore, the accuracy of distance measurement in the distance measuring device 3 can be improved.
  • the power storage element 11 is composed of one capacitor, but is not limited to this, and may be composed of a plurality of capacitors, for example, as shown in the following modification example 1.
  • FIG. 7 is a diagram schematically showing the upper surface of the circuit board 2 according to the modification example 1.
  • the storage element 11 is composed of ten capacitors 11a connected in parallel with respect to the flow direction of the drive current (X-axis direction) as compared with the above embodiment. Specifically, 10 capacitors 11a of the power storage element 11 are connected in parallel between the wiring portion 21a and the wiring portion 21b.
  • the width of the region A1 in the Y-axis direction (direction perpendicular to the flow of the drive current) is wider than the width of the power storage element 11, the light source 12, and the switch element 13 in the Y-axis direction.
  • Other configurations of the first modification are the same as those of the above embodiment.
  • the capacitance of the power storage element 11 composed of 10 capacitors 11a is the same as the capacitance of the power storage element 11 in the above embodiment. Therefore, even with the configuration of the first modification, the drive current having the same amount of current as that of the above embodiment can be supplied to the light source 12.
  • the power storage element 11 is configured by connecting a plurality of capacitors 11a in parallel, the inductance of the power storage element 11 is remarkable as compared with the case where the power storage element 11 is composed of one capacitor having the same capacitance. Can be reduced to. Therefore, the parasitic inductance of the entire path through which the drive current flows can be further reduced, and the deterioration of the pulsed light characteristics due to the parasitic inductance can be suppressed more reliably.
  • the power storage element 11, the light source 12, and the switch element 13 are arranged on a straight line parallel to the X axis, but they are not necessarily arranged on a straight line, for example, as shown in the following modification example 2. good.
  • 8 (a) and 8 (b) are diagrams schematically showing the upper surface and the lower surface of the circuit board 2 according to the second modification, respectively.
  • the region A1 has a shape bent into a substantially L-shape.
  • the wiring portion 21a is composed of a wiring portion extending in the X-axis direction.
  • the wiring portion 21b is composed of a wiring portion extending in the X-axis direction and a wiring portion extending in a direction inclined by 45 ° with respect to the X-axis and the Y-axis.
  • the wiring portion 21b is composed of a wiring portion extending in a direction inclined by 45 ° with respect to the X-axis and the Y-axis, and a wiring portion extending in the Y-axis direction.
  • the wiring portion 21d is composed of a wiring portion extending in the Y-axis direction.
  • the connection portion 23 is provided near the end of the wiring portion 21a on the negative side of the X-axis and near the end of the wiring portion 21d on the negative side of the Y-axis.
  • the second conductive layer 22 has the same shape as the outer shape of the first conductive layer 21 (wiring portions 21a, 21b, 21c, 21d) shown in FIG. 8A.
  • the second conductive layer 22 is connected to the first conductive layer 21 by two connecting portions 23 near both ends in the longitudinal direction.
  • the power storage element 11 is arranged so as to straddle the wiring portion 21a and the wiring portion 21b, and the light source 12 straddles the wiring portion 21b and the wiring portion 21c.
  • the switch element 13 is arranged so as to straddle the wiring portion 21c and the wiring portion 21d.
  • the power storage element 11, the light source 12, and the switch element 13 are not arranged in one direction, and the first conductive layer 21 and the second conductive layer 22 also have a bent shape. Therefore, the lengths of the first conductive layer 21 and the second conductive layer 22 are longer than those of the above embodiment. Therefore, the parasitic inductance (self-inductance) of the first conductive layer 21 and the second conductive layer 22 is larger than that of the above embodiment.
  • the parasitic inductance (self-inductance) of the first conductive layer 21 and the second conductive layer 22 is small. Therefore, from this viewpoint, as in the above embodiment, the power storage element 11, the light source 12, and the switch element 13 are arranged side by side in one direction, and the first conductive layer 21 and the second conductive layer 22 are extended in one direction. It is preferable to place it in.
  • one connecting portion 23 is provided in each of the wiring portions 21a and 21d of the first conductive layer 21, but a plurality of connecting portions 23 may be provided respectively.
  • the light source 12 is composed of one light emitting element, but the light source 12 is not limited to this, and may be composed of a plurality of light emitting elements.
  • the light source 12 may be composed of a plurality of laser diodes or may be composed of a plurality of LEDs.
  • each light emitting element may be connected in series or in parallel to the circuit.
  • the switch element 13 is composed of one FET, but the present invention is not limited to this, and the switch element 13 may be composed of a plurality of switch elements. Each FET may be connected in series or in parallel to the circuit.
  • the power storage element 11, the light source 12, and the switch element 13 are arranged in this order along the direction in which the drive current flows, but the arrangement order is not limited to this.
  • the power storage element 11, the switch element 13, and the light source 12 may be arranged in this order along the direction in which the drive current flows.
  • the switch element 13 is directly connected to the ground. Therefore, the heat generated by the switch element 13 is likely to propagate to the ground. As a result, the heat dissipation characteristics of the switch element 13 are improved, so that the resistance (on resistance) of the switch element 13 at the time of conduction is suppressed. Therefore, it is preferable that the power storage element 11, the light source 12, and the switch element 13 are arranged in this order as in the above embodiment.
  • the light emitting device 1 is mounted on a so-called flash type distance measuring device 3 that simultaneously irradiates the entire range measuring region A10 with light.
  • the present invention is not limited to this, and the light emitting device 1 may be mounted on a distance measuring device of a method of scanning a line beam in the short side direction or a distance measuring device of a method of scanning a point beam in a two-dimensional direction.
  • the arrangement regions of the first conductive layer 21 and the second conductive layer 22 are viewed in a plan view. They were in agreement with each other (as viewed in the Z-axis direction). However, the arrangement regions of the first conductive layer 21 and the second conductive layer 22 do not necessarily have to coincide with each other in a plan view. For example, the arrangement region of the first conductive layer 21 may be inclined by several degrees with respect to the second conductive layer 22 in a direction parallel to the XY plane.
  • the arrangement region of the first conductive layer 21 may be slightly shifted in the direction parallel to the XY plane with respect to the second conductive layer 22.
  • the contour shapes of the first conductive layer 21 and the second conductive layer 22 in a plan view may be different from each other.
  • the width or length of the first conductive layer 21 may be different from that of the second conductive layer 22.
  • the drive current is supplied to the light source 12 from the power storage element 11, but the drive current may be supplied to the light source 12 by using a current source other than the power storage element 11.
  • a current source other than the power storage element 11.
  • a voltage regulator that is stepped up and down by the laser drive voltage, a current limiting resistor connected in series with the voltage regulator, or a constant current diode is used as a current source for supplying the drive current to the light source 12. You may.
  • the current source is connected in series with the light source 12 and the switch element 13 by the first conductive layer 21, and the second conductive layer 22 is connected by the connecting portion 23.

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Abstract

This light emission device comprises: a light source (12); a power storage element (11) which is for supplying a drive current to the light source (12); a switch element (13) which switches the light source (12) between emitting light and not emitting light; and a circuit board (2) on which the light source (12), the power storage element (11), and the switch element (13) are mounted. The circuit board (2) has: a first conductive layer (21) that connects the light source (12), the power storage element (11), and the switch element (13) in series; a second conductive layer (22) that is disposed so as to face the first conductive layer (21) at a prescribed distance; and a connection part (23) that connects the first conductive layer (21) and the second conductive layer (22) and causes the drive current to flow in the second conductive layer (22) in the direction opposite the flow direction of the drive current in the first conductive layer (21).

Description

発光装置および距離測定装置Light emitting device and distance measuring device
　本発明は、パルス光を出射する発光装置、および当該発光装置から出射されるパルス光を用いて物体との距離を測定する距離測定装置に関する。 The present invention relates to a light emitting device that emits pulsed light and a distance measuring device that measures a distance to an object using the pulsed light emitted from the light emitting device.
　従来、強度がパルス状に変化するパルス光を用いて物体までの距離を測定する距離測定装置が知られている。この種の距離測定装置では、たとえば、パルス光の出射タイミングと、当該パルス光の物体からの反射光の受光タイミングとの時間差に基づいて、物体までの距離が測定される。以下の特許文献１には、この種の距離測定装置が記載されている。 Conventionally, a distance measuring device that measures a distance to an object using pulsed light whose intensity changes in a pulse shape is known. In this type of distance measuring device, for example, the distance to an object is measured based on the time difference between the timing of emitting the pulsed light and the timing of receiving the reflected light from the object of the pulsed light. The following Patent Document 1 describes this kind of distance measuring device.
特開平７－２２９９６７号公報Japanese Unexamined Patent Publication No. 7-229967
　上記構成の距離測定装置では、測距精度を高めるために、高強度かつ短パルスのパルス発光が要求される。しかし、光源およびその駆動回路が回路基板に実装される場合には、駆動回路の配線に基づく寄生インダクタンスが存在し、この寄生インダクタンスによって、パルス光のピーク強度およびパルス幅が劣化してしまう。この場合、駆動回路の配線を短くすることにより寄生インダクタンスを抑制できるが、配線の短縮化による寄生インダクタンスの抑制には限界がある。 In the distance measuring device having the above configuration, high intensity and short pulse pulse emission is required in order to improve the distance measurement accuracy. However, when the light source and its drive circuit are mounted on a circuit board, there is a parasitic inductance based on the wiring of the drive circuit, and this parasitic inductance deteriorates the peak intensity and pulse width of the pulsed light. In this case, the parasitic inductance can be suppressed by shortening the wiring of the drive circuit, but there is a limit to the suppression of the parasitic inductance by shortening the wiring.
　かかる課題に鑑み、本発明は、寄生インダクタンスによるパルス光の特性の劣化を抑制することが可能な発光装置および距離測定装置を提供することを目的とする。 In view of the above problems, it is an object of the present invention to provide a light emitting device and a distance measuring device capable of suppressing deterioration of the characteristics of pulsed light due to parasitic inductance.
　本発明の第１の態様は、発光装置に関する。本態様に係る発光装置は、光源と、前記光源に駆動電流を供給するための蓄電素子と、前記光源の発光および非発光を切り替えるスイッチ素子と、前記光源、前記蓄電素子および前記スイッチ素子が実装される回路基板と、を備える。ここで、前記回路基板は、前記光源、前記蓄電素子および前記スイッチ素子を直列接続する第１導電層と、前記第１導電層に対し所定距離をおいて対向配置された第２導電層と、前記第１導電層と前記第２導電層とを接続して、前記第１導電層の前記駆動電流の流れ方向と逆方向に、前記第２導電層に前記駆動電流を流す接続部と、を有する。 The first aspect of the present invention relates to a light emitting device. The light emitting device according to this embodiment includes a light source, a power storage element for supplying a drive current to the light source, a switch element for switching between light emission and non-light emission of the light source, and the light source, the power storage element, and the switch element. It is provided with a circuit board to be used. Here, the circuit board includes a first conductive layer for connecting the light source, the power storage element, and the switch element in series, and a second conductive layer arranged so as to face the first conductive layer at a predetermined distance. A connecting portion that connects the first conductive layer and the second conductive layer and causes the drive current to flow through the second conductive layer in a direction opposite to the flow direction of the drive current of the first conductive layer. Have.
　本態様に係る発光装置によれば、第１導電層と第２導電層とに互いに逆方向に駆動電流が流れる。このため、第１導電層と第２導電層との間の相互インダクタンスにより、駆動電流が流れる経路の寄生インダクタンスが減少する。よって、寄生インダクタンスによるパルス光の特性の劣化を抑制することができる。 According to the light emitting device according to this aspect, a driving current flows in the first conductive layer and the second conductive layer in opposite directions to each other. Therefore, the mutual inductance between the first conductive layer and the second conductive layer reduces the parasitic inductance of the path through which the drive current flows. Therefore, deterioration of the characteristics of the pulsed light due to the parasitic inductance can be suppressed.
　本発明の第２の態様は、距離測定装置に関する。本態様に係る距離測定装置は、第１の態様に係る発光装置と、前記発光装置から出射されるパルス光を目標領域に投射する投射光学系と、前記パルス光の物体からの反射光を受光する受光部と、を備える。 The second aspect of the present invention relates to a distance measuring device. The distance measuring device according to this aspect receives the light emitting device according to the first aspect, the projection optical system that projects the pulsed light emitted from the light emitting device onto the target region, and the reflected light from the object of the pulsed light. It is provided with a light receiving unit and a light receiving unit.
　本態様に係る距離測定装置によれば、第１の態様に係る発光装置を備えるため、寄生インダクタンスによるパルス光の特性の劣化を抑制できる。よって、測距の精度を高めることができる。 According to the distance measuring device according to this aspect, since the light emitting device according to the first aspect is provided, deterioration of the characteristics of the pulsed light due to the parasitic inductance can be suppressed. Therefore, the accuracy of distance measurement can be improved.
　本発明の第３の態様は、発光装置に関する。本態様に係る発光装置は、光源と、前記光源に駆動電流を供給するための電流源と、前記光源の発光および非発光を切り替えるスイッチ素子と、前記光源、前記電流源および前記スイッチ素子が実装される回路基板と、を備える。ここで、前記回路基板は、前記光源、前記電流源および前記スイッチ素子を直列接続する第１導電層と、前記第１導電層に対し所定距離をおいて対向配置された第２導電層と、前記第１導電層と前記第２導電層とを接続して、前記第１導電層の前記駆動電流の流れ方向と逆方向に、前記第２導電層に前記駆動電流を流す接続部と、を有する。 A third aspect of the present invention relates to a light emitting device. The light emitting device according to this embodiment includes a light source, a current source for supplying a drive current to the light source, a switch element for switching between light emission and non-light emission of the light source, and the light source, the current source, and the switch element. It is provided with a circuit board to be used. Here, the circuit board includes a first conductive layer for connecting the light source, the current source, and the switch element in series, and a second conductive layer arranged so as to face the first conductive layer at a predetermined distance. A connecting portion that connects the first conductive layer and the second conductive layer and causes the drive current to flow through the second conductive layer in a direction opposite to the flow direction of the drive current of the first conductive layer. Have.
　本態様に係る発光装置によれば、上記第１の態様と同様の効果が奏される。 According to the light emitting device according to this aspect, the same effect as that of the first aspect is obtained.
　以上のとおり、本発明によれば、寄生インダクタンスによるパルス光の特性の劣化を抑制することが可能な発光装置および距離測定装置を提供することができる。 As described above, according to the present invention, it is possible to provide a light emitting device and a distance measuring device capable of suppressing deterioration of the characteristics of pulsed light due to parasitic inductance.
　本発明の効果ないし意義は、以下に示す実施の形態の説明により更に明らかとなろう。ただし、以下に示す実施の形態は、あくまでも、本発明を実施化する際の一つの例示であって、本発明は、以下の実施の形態に記載されたものに何ら制限されるものではない。 The effect or significance of the present invention will be further clarified by the description of the embodiments shown below. However, the embodiments shown below are merely examples for implementing the present invention, and the present invention is not limited to those described in the following embodiments.
図１は、実施形態に係る、発光装置の構成を示す回路図である。FIG. 1 is a circuit diagram showing a configuration of a light emitting device according to an embodiment. 図２は、実施形態に係る、光源を矩形のパルス信号で駆動した場合のパルス発光の強度をシミュレーションにより求めたシミュレーション結果を示す図である。FIG. 2 is a diagram showing a simulation result obtained by simulating the intensity of pulse emission when the light source is driven by a rectangular pulse signal according to the embodiment. 図３（ａ）、（ｂ）は、それぞれ、実施形態に係る、回路基板の上面および下面を模式的に示す図である。図３（ｃ）は、実施形態に係る、図３（ａ）の領域をＡ－Ａ’線で切断したときの断面図である。3A and 3B are diagrams schematically showing the upper surface and the lower surface of the circuit board according to the embodiment, respectively. FIG. 3 (c) is a cross-sectional view of the region of FIG. 3 (a) according to the embodiment when the region is cut along the AA'line. 図４（ａ）は、実施形態に係る、１つの導体に電流が流れる場合の寄生インダクタンスを説明する図である。図４（ｂ）は、実施形態に係る、２つの導体に電流が流れる場合の寄生インダクタンスを説明する図である。FIG. 4A is a diagram illustrating a parasitic inductance when a current flows through one conductor according to the embodiment. FIG. 4B is a diagram illustrating the parasitic inductance when a current flows through the two conductors according to the embodiment. 図５（ａ）は、実施形態に係る、第１導電層および第２導電層から生じる全体の寄生インダクタンスの周波数応答をシミュレーションにより求めたシミュレーション結果を示すグラフである。図５（ｂ）は、実施形態に係る、駆動電流の周波数が１００ＭＨｚであるとき第１導電層および第２導電層から生じる全体の寄生インダクタンスが、第１導電層と第２導電層との間の層間距離の変化に応じて変化する様子をシミュレーションにより求めたシミュレーション結果を示すグラフである。FIG. 5A is a graph showing a simulation result obtained by simulation for the frequency response of the entire parasitic inductance generated from the first conductive layer and the second conductive layer according to the embodiment. FIG. 5B shows that, according to the embodiment, when the frequency of the drive current is 100 MHz, the total parasitic inductance generated from the first conductive layer and the second conductive layer is between the first conductive layer and the second conductive layer. It is a graph which shows the simulation result which obtained the state which changes according to the change of the interlayer distance of. 図６は、実施形態に係る、距離測定装置の構成を示すブロック図である。FIG. 6 is a block diagram showing a configuration of a distance measuring device according to an embodiment. 図７は、変更例１に係る、回路基板の上面を模式的に示す図である。FIG. 7 is a diagram schematically showing the upper surface of the circuit board according to the first modification. 図８（ａ）、（ｂ）は、それぞれ、変更例２に係る、回路基板の上面および下面を模式的に示す図である。8 (a) and 8 (b) are views schematically showing the upper surface and the lower surface of the circuit board according to the second modification, respectively.
　ただし、図面はもっぱら説明のためのものであって、この発明の範囲を限定するものではない。 However, the drawings are for illustration purposes only and do not limit the scope of the present invention.
　以下、本発明の実施形態について、図を参照して説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
　図１は、発光装置１の構成を示す回路図である。 FIG. 1 is a circuit diagram showing the configuration of the light emitting device 1.
　発光装置１は、蓄電素子１１と、光源１２と、スイッチ素子１３と、抵抗１４と、ドライバ１５と、直流電源１６と、パルス発生回路１７と、を備える。蓄電素子１１、光源１２、スイッチ素子１３、抵抗１４およびドライバ１５は、回路基板２に実装されている。 The light emitting device 1 includes a power storage element 11, a light source 12, a switch element 13, a resistor 14, a driver 15, a DC power supply 16, and a pulse generation circuit 17. The power storage element 11, the light source 12, the switch element 13, the resistor 14, and the driver 15 are mounted on the circuit board 2.
　蓄電素子１１は、１つのキャパシタからなっており、抵抗１４を介して直流電源１６に接続されている。抵抗１４と蓄電素子１１とからなる回路の時定数に応じて、蓄電素子１１に電荷が蓄積される。蓄電素子１１は、スイッチ素子１３が導通することに応じて、光源１２に駆動電流を供給する。 The power storage element 11 is composed of one capacitor and is connected to the DC power supply 16 via a resistor 14. Charges are accumulated in the power storage element 11 according to the time constant of the circuit including the resistor 14 and the power storage element 11. The power storage element 11 supplies a drive current to the light source 12 according to the conduction of the switch element 13.
　光源１２は、レーザダイオードである。光源１２は、蓄電素子１１から駆動電流が供給されることにより、レーザ光を出射する。光源１２が、ＬＥＤ（Light Emitting Diode）等の他の発光素子であってもよい。 The light source 12 is a laser diode. The light source 12 emits laser light when a drive current is supplied from the power storage element 11. The light source 12 may be another light emitting element such as an LED (Light Emitting Diode).
　スイッチ素子１３は、ドライバ１５からの信号に応じて、導通状態と非導通状態に切り替えられる。スイッチ素子１３は、たとえば、ＦＥＴ（Field Effect Transistor）である。スイッチ素子１３が、ドライバ１５からの信号に応じて導通状態と非導通状態に切り替えられる他の素子により構成されてもよい。 The switch element 13 is switched between a conductive state and a non-conducting state according to the signal from the driver 15. The switch element 13 is, for example, a FET (Field Effect Transistor). The switch element 13 may be composed of other elements that can be switched between a conductive state and a non-conducting state according to a signal from the driver 15.
　スイッチ素子１３は、ドライバ１５からの信号により、光源１２を、発光状態と非発光状態に切り替える。すなわち、スイッチ素子１３が導通状態になると、蓄電素子１１から駆動電流が光源１２に供給されて、光源１２が発光する。また、スイッチ素子１３が非導通状態になると、光源１２に対する駆動電流の供給が遮断されて、光源１２が消灯する。 The switch element 13 switches the light source 12 between a light emitting state and a non-light emitting state by a signal from the driver 15. That is, when the switch element 13 becomes conductive, a drive current is supplied from the power storage element 11 to the light source 12, and the light source 12 emits light. Further, when the switch element 13 becomes non-conducting, the supply of the drive current to the light source 12 is cut off, and the light source 12 is turned off.
　ドライバ１５は、パルス発生回路１７から入力されるパルス信号に応じて、スイッチ素子１３を駆動する。スイッチ素子１３がＦＥＴの場合、ドライバ１５は、パルス信号が立ち上がっている期間において、ＦＥＴのゲートに駆動信号を供給する。これにより、パルス信号の立ち上がり期間において、光源１２に駆動電流が供給され、光源１２がパルス発光する。 The driver 15 drives the switch element 13 in response to the pulse signal input from the pulse generation circuit 17. When the switch element 13 is an FET, the driver 15 supplies a drive signal to the gate of the FET during the period when the pulse signal is rising. As a result, the drive current is supplied to the light source 12 during the rising period of the pulse signal, and the light source 12 emits pulse light.
　上記構成の発光装置１が、距離測定装置に搭載される場合、測距精度を高めるために、高強度かつ短パルスのパルス発光が要求される。しかし、図１のように、蓄電素子１１、光源１２およびスイッチ素子１３が回路基板２に実装される場合、回路基板２上の配線に基づく寄生インダクタンスＬＰ１、ＬＰ２が存在し、この寄生インダクタンスＬＰ１、ＬＰ２によって、パルス光のピーク強度およびパルス幅が劣化してしまう。 When the light emitting device 1 having the above configuration is mounted on a distance measuring device, high intensity and short pulse pulse light emission is required in order to improve the distance measurement accuracy. However, as shown in FIG. 1, when the power storage element 11, the light source 12, and the switch element 13 are mounted on the circuit board 2, the parasitic inductances LP1 and LP2 based on the wiring on the circuit board 2 exist, and the parasitic inductance LP1, The LP2 deteriorates the peak intensity and the pulse width of the pulsed light.
　すなわち、寄生インダクタンスＬＰ１、ＬＰ２を統合した合計の寄生インダクタンスをＬＰ０とし、光源１２、蓄電素子１１およびスイッチ素子１３のインダクタンス成分とＬＰ０とを合計したインダクタンスをＬＰＴＯＴＡＬとした場合、光源１２に流れる駆動電流（ＬＤ電流）と、パルス発光のパルス幅（ピーク強度の１／ｅ２以上の範囲の幅）と、パルス立上り特性は、それぞれ、以下の式（１）～（３）で算出される。 That is, when the total parasitic inductance that integrates the parasitic inductances LP1 and LP2 is LP0 and the total inductance of the inductance components of the light source 12, the power storage element 11 and the switch element 13 and LP0 is LP TOTAL , the drive flowing through the light source 12 is used. The current (LD current), the pulse width of the pulse light source ( the width in the range of 1 / e 2 or more of the peak intensity), and the pulse rise characteristic are calculated by the following equations (1) to (3), respectively.
　ＬＤ電流＝ＶＢＵＳ×√（ＣＢＵＳ／ＬＰＴＯＴＡＬ）　…（１）
　パルス幅＝Π×√（ＣＢＵＳ×ＬＰＴＯＴＡＬ）　…（２）
　パルス立上り特性＝１／（２Π×√（ＣＢＵＳ×ＬＰＴＯＴＡＬ））　…（３） LD current = V BUS × √ (C BUS / LP TOTAL )… (1)
Pulse width = Π × √ (C BUS × LP TOTAL )… (2)
Pulse rise characteristic = 1 / (2Π × √ (C BUS × LP TOTAL ))… (3)
　ここで、ＶＢＵＳは、直流電源１６の電圧値であり、ＣＢＵＳは、蓄電素子１１の容量値である。 Here, V BUS is the voltage value of the DC power supply 16, and C BUS is the capacity value of the power storage element 11.
　図２は、光源１２を矩形のパルス信号で駆動した場合のパルス発光の強度をシミュレーションにより求めたシミュレーション結果を示す図である。 FIG. 2 is a diagram showing a simulation result obtained by simulating the intensity of pulse emission when the light source 12 is driven by a rectangular pulse signal.
　図２の実線は、寄生インダクタンスＬＰ０（ＬＰ０＝ＬＰ１＋ＬＰ２）が１．５ｎＨである場合のシミュレーション結果であり、図２の破線は、寄生インダクタンスＬＰ０が２．８ｎＨである場合のシミュレーション結果である。 The solid line in FIG. 2 is the simulation result when the parasitic inductance LP0 (LP0 = LP1 + LP2) is 1.5 nH, and the broken line in FIG. 2 is the simulation result when the parasitic inductance LP0 is 2.8 nH.
　図２に示すように、寄生インダクタンスＬＰ０が２．８ｎＨである場合のパルス光のピーク強度Ｐ２は、寄生インダクタンスＬＰ０が１．５ｎＨである場合のパルス光のピーク強度Ｐ１に比べて低下する。また、寄生インダクタンスＬＰ０が２．８ｎＨである場合のパルス光のパルス幅Ｗ２は、寄生インダクタンスＬＰ０が１．５ｎＨである場合のパルス光のパルス幅Ｗ１に比べて広がる。また、寄生インダクタンスＬＰ０が２．８ｎＨである場合のパルス光のパルス立上り特性Ｔｒ２は、寄生インダクタンスＬＰ０が１．５ｎＨである場合のパルス光のパルス立上り特性Ｔｒ１に比べて遅い。このように、寄生インダクタンスＬＰ０が大きくなるに伴って、パルス光の特性が劣化する。 As shown in FIG. 2, the peak intensity P2 of the pulsed light when the parasitic inductance LP0 is 2.8 nH is lower than the peak intensity P1 of the pulsed light when the parasitic inductance LP0 is 1.5 nH. Further, the pulse width W2 of the pulsed light when the parasitic inductance LP0 is 2.8 nH is wider than the pulse width W1 of the pulsed light when the parasitic inductance LP0 is 1.5 nH. Further, the pulse rising characteristic Tr2 of the pulsed light when the parasitic inductance LP0 is 2.8 nH is slower than the pulse rising characteristic Tr1 of the pulsed light when the parasitic inductance LP0 is 1.5 nH. As described above, as the parasitic inductance LP0 increases, the characteristics of the pulsed light deteriorate.
　この問題は、回路の配線を短くして寄生インダクタンスを低下させることにより抑制できる。しかし、回路基板２のレイアウトの制約等から、配線の短縮化による寄生インダクタンスの抑制には限界がある。 This problem can be suppressed by shortening the wiring of the circuit and reducing the parasitic inductance. However, due to restrictions on the layout of the circuit board 2, there is a limit to suppressing the parasitic inductance by shortening the wiring.
　そこで、本実施形態では、回路基板２の構成を工夫するにより、寄生インダクタンスＬ０が抑制される。以下、この構成について、説明する。 Therefore, in the present embodiment, the parasitic inductance L0 is suppressed by devising the configuration of the circuit board 2. Hereinafter, this configuration will be described.
　図３（ａ）、（ｂ）は、それぞれ、回路基板２の上面および下面を模式的に示す図である。図３（ｃ）は、図３（ａ）の領域Ａ１をＡ－Ａ’線で切断したときの断面図である。図３（ａ）～（ｃ）には、互いに直交するＸ、Ｙ、Ｚ軸が付記されている。Ｘ軸およびＹ軸は、それぞれ、方形形状の回路基板２の互いに直交する２辺に平行である。Ｚ軸方向は、回路基板２の厚み方向である。 3 (a) and 3 (b) are diagrams schematically showing the upper surface and the lower surface of the circuit board 2, respectively. FIG. 3C is a cross-sectional view taken along the line AA'of the region A1 of FIG. 3A. In FIGS. 3A to 3C, X, Y, and Z axes orthogonal to each other are added. The X-axis and the Y-axis are parallel to the two orthogonal sides of the square-shaped circuit board 2, respectively. The Z-axis direction is the thickness direction of the circuit board 2.
　図３（ａ）を参照して、回路基板２は、矩形の領域Ａ１と、領域Ａ１の外側に配置された領域Ａ２とを備える。領域Ａ１と領域Ａ２は、それぞれ個別にグランドを有する。すなわち、領域Ａ１のグランドと、領域Ａ２のグランドは、とある一か所で接続されており、領域Ａ１のグランドと領域Ａ２のグランドとの間のインピーダンスは、高周波領域で高くなる。このうち、領域Ａ１に、図１の蓄電素子１１、光源１２およびスイッチ素子１３が実装される。図１の抵抗１４およびドライバ１５は、領域Ａ２に実装される。図３（ａ）、（ｂ）では、抵抗１４およびドライバ１５の図示が省略されている。 With reference to FIG. 3A, the circuit board 2 includes a rectangular region A1 and a region A2 arranged outside the region A1. Regions A1 and A2 each have their own ground. That is, the ground of the region A1 and the ground of the region A2 are connected at a certain place, and the impedance between the ground of the region A1 and the ground of the region A2 becomes high in the high frequency region. Of these, the power storage element 11, the light source 12, and the switch element 13 of FIG. 1 are mounted in the region A1. The resistor 14 and the driver 15 of FIG. 1 are mounted in the region A2. In FIGS. 3A and 3B, the resistance 14 and the driver 15 are not shown.
　図３（ａ）および図３（ｃ）に示すように、領域Ａ１の上面には、蓄電素子１１、光源１２およびスイッチ素子１３を直列接続するための第１導電層２１が形成されている。第１導電層２１は、４つの配線部２１ａ、２１ｂ、２１ｃ、２１ｄからなっている。第１導電層２１は、たとえば、所定厚みの銅箔により構成される。蓄電素子１１、光源１２およびスイッチ素子１３は、Ｘ軸に平行な直線上に配置される。したがって、第１導電層２１はＸ軸に平行に延びており、配線部２１ａ、２１ｂ、２１ｃ、２１ｄは、Ｘ軸に平行に並んでいる。配線部２１ａ、２１ｂ、２１ｃ、２１ｄのＹ軸方向の幅は、領域Ａ１のＹ軸方向の幅に等しい。第１導電層２１のＸ軸方向の長さは、領域Ａ１のＸ軸方向の長さに等しい。 As shown in FIGS. 3A and 3C, a first conductive layer 21 for connecting the power storage element 11, the light source 12, and the switch element 13 in series is formed on the upper surface of the region A1. The first conductive layer 21 is composed of four wiring portions 21a, 21b, 21c, and 21d. The first conductive layer 21 is made of, for example, a copper foil having a predetermined thickness. The power storage element 11, the light source 12, and the switch element 13 are arranged on a straight line parallel to the X axis. Therefore, the first conductive layer 21 extends parallel to the X axis, and the wiring portions 21a, 21b, 21c, and 21d are arranged parallel to the X axis. The width of the wiring portions 21a, 21b, 21c, 21d in the Y-axis direction is equal to the width of the region A1 in the Y-axis direction. The length of the first conductive layer 21 in the X-axis direction is equal to the length of the region A1 in the X-axis direction.
　領域Ａ１の下面には、第２導電層２２が形成されている。第２導電層２２は、領域Ａ１の上面に配置された回路のグランドを構成する。図３（ｂ）に示すように、第２導電層２２は、Ｘ軸に平行に長い長方形の形状である。第２導電層２２のＹ軸方向の幅は、領域Ａ１のＹ軸方向の幅に等しく、第２導電層２２のＸ軸方向の長さは、領域Ａ１のＸ軸方向の長さに等しい。 A second conductive layer 22 is formed on the lower surface of the region A1. The second conductive layer 22 constitutes the ground of the circuit arranged on the upper surface of the region A1. As shown in FIG. 3B, the second conductive layer 22 has a long rectangular shape parallel to the X-axis. The width of the second conductive layer 22 in the Y-axis direction is equal to the width of the region A1 in the Y-axis direction, and the length of the second conductive layer 22 in the X-axis direction is equal to the length of the region A1 in the X-axis direction.
　領域Ａ１のＹ軸方向（駆動電流の流れに垂直な方向）の幅は、蓄電素子１１、光源１２およびスイッチ素子１３のＹ軸方向の幅よりも広い。したがって、第２導電層２２のＹ軸方向の幅は、蓄電素子１１、光源１２およびスイッチ素子１３のＹ軸方向の幅よりも広く、第１導電層２１のＹ軸方向の幅は、蓄電素子１１、光源１２およびスイッチ素子１３のＹ軸方向の幅に対して、第２導電層２２のＹ軸方向の幅と同じ幅まで広げられている。 The width of the region A1 in the Y-axis direction (direction perpendicular to the flow of the drive current) is wider than the width of the power storage element 11, the light source 12, and the switch element 13 in the Y-axis direction. Therefore, the width of the second conductive layer 22 in the Y-axis direction is wider than the width of the power storage element 11, the light source 12, and the switch element 13 in the Y-axis direction, and the width of the first conductive layer 21 in the Y-axis direction is the power storage element. 11. The width of the second conductive layer 22 in the Y-axis direction is the same as the width of the light source 12 and the switch element 13 in the Y-axis direction.
　図３（ｃ）に示すように、第１導電層２１と第２導電層２２は、それぞれ、回路基板２のベースとなる基材２４の上面および下面に形成されている。基材２４は、絶縁性の樹脂材料により形成されている。したがって、第２導電層２２は、第１導電層２１に対し、基材２４の厚みに相当する所定距離をおいて、対向配置されている。第１導電層２１のＸ軸両端の配線部２１ａ、２１ｄは、それぞれ、接続部２３によって第２導電層２２に電気的に接続されている。接続部２３は、たとえば、ビアにより構成される。 As shown in FIG. 3C, the first conductive layer 21 and the second conductive layer 22 are formed on the upper surface and the lower surface of the base material 24 which is the base of the circuit board 2, respectively. The base material 24 is made of an insulating resin material. Therefore, the second conductive layer 22 is arranged to face the first conductive layer 21 at a predetermined distance corresponding to the thickness of the base material 24. The wiring portions 21a and 21d at both ends of the X-axis of the first conductive layer 21 are electrically connected to the second conductive layer 22 by the connecting portions 23, respectively. The connecting portion 23 is composed of, for example, vias.
　蓄電素子１１には、領域Ａ２に配置された抵抗１４（図１参照）を介して電荷が蓄積される。領域Ａ２に配置されたドライバ１５（図１参照）により、スイッチ素子１３が導通すると、図３（ｃ）の矢印で示すように、第１導電層２１を駆動電流が流れる。これにより、光源１２がパルス発光する。 Charges are accumulated in the power storage element 11 via a resistor 14 (see FIG. 1) arranged in the region A2. When the switch element 13 is conducted by the driver 15 (see FIG. 1) arranged in the region A2, a driving current flows through the first conductive layer 21 as shown by the arrow in FIG. 3 (c). As a result, the light source 12 emits pulse light.
　このとき、２つの接続部２３によって第１導電層２１と第２導電層２２が接続されているため、第１導電層２１および第２導電層２２と、２つの接続部２３とによって閉回路が構成される。これにより、第１導電層２１を流れた駆動電流は、Ｘ軸正側の接続部２３を通って第２導電層２２へと流れ込み、第２導電層２２を、Ｘ軸負方向に流れる。その後、駆動電流は、Ｘ軸負側の接続部２３を通って第１導電層２１へと流れ込む。 At this time, since the first conductive layer 21 and the second conductive layer 22 are connected by the two connecting portions 23, the closed circuit is formed by the first conductive layer 21, the second conductive layer 22, and the two connecting portions 23. It is composed. As a result, the drive current that has flowed through the first conductive layer 21 flows into the second conductive layer 22 through the connection portion 23 on the positive side of the X-axis, and flows through the second conductive layer 22 in the negative direction of the X-axis. After that, the drive current flows into the first conductive layer 21 through the connection portion 23 on the negative side of the X-axis.
　したがって、第１導電層２１と第２導電層２２には、互いに逆方向に、駆動電流が流れる。２つの接続部２３は、第１導電層２１と第２導電層２２とを接続して、第１導電層２１の駆動電流の流れ方向と逆方向に、第２導電層２２に駆動電流を流す役割を果たす。 Therefore, a drive current flows in the first conductive layer 21 and the second conductive layer 22 in opposite directions to each other. The two connecting portions 23 connect the first conductive layer 21 and the second conductive layer 22, and allow the drive current to flow through the second conductive layer 22 in the direction opposite to the flow direction of the drive current of the first conductive layer 21. Play a role.
　このように、逆向きに駆動電流が流れることにより、以下に説明するように、第１導電層２１および第２導電層２２により生じる全体の寄生インダクタンスが低減される。 As described below, the flow of the drive current in the opposite direction reduces the overall parasitic inductance generated by the first conductive layer 21 and the second conductive layer 22.
　図４（ａ）は、１つの導体に電流が流れる場合の寄生インダクタンスを説明する図であり、図４（ｂ）は、２つの導体に電流が流れる場合の寄生インダクタンスを説明する図である。 FIG. 4A is a diagram for explaining a parasitic inductance when a current flows through one conductor, and FIG. 4B is a diagram for explaining a parasitic inductance when a current flows through two conductors.
　図４（ａ）に示すように、長さｌ、半径ａの１つの導体に電流が流れる場合、当該導体の寄生インダクタンスＬｓは、以下の式（４）で算出される。 As shown in FIG. 4A, when a current flows through one conductor having a length l and a radius a, the parasitic inductance L s of the conductor is calculated by the following equation (4).
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000001
　この場合、導体全体の寄生インダクタンスＬｔｏｔａｌは、次式（５）で表される。 In this case, the parasitic inductance L total of the entire conductor is expressed by the following equation (5).
Figure JPOXMLDOC01-appb-M000002
Figure JPOXMLDOC01-appb-M000002
　他方、図４（ｂ）に示すように、長さｌ、半径ａの２つの導体に互いに逆向きの電流が流れる場合、これら２つの導体間には相互インダクタンスＭが生じる。この場合、導体間の距離をｄとすると、相互インダクタンスＭは、以下の式（６）で算出される。 On the other hand, as shown in FIG. 4B, when currents in opposite directions flow through two conductors having a length l and a radius a, a mutual inductance M is generated between these two conductors. In this case, assuming that the distance between the conductors is d, the mutual inductance M is calculated by the following equation (6).
Figure JPOXMLDOC01-appb-M000003
Figure JPOXMLDOC01-appb-M000003
　この場合、２つの導体全体の寄生インダクタンスＬｔｏｔａｌは、次式（７）で表される。 In this case, the parasitic inductance L total of the entire two conductors is expressed by the following equation (7).
Figure JPOXMLDOC01-appb-M000004
Figure JPOXMLDOC01-appb-M000004
　式（４）および式（６）を参照すると、２つの導体間の距離ｄを導体の半径ａに近づけることにより、相互インダクタンスＭの大きさを導体単体の寄生インダクタンスに近づけることができる。したがって、式（７）から、２つの導体間の距離ｄを導体の半径ａの近づけることにより、２つの導体により生じる全体の寄生インダクタンスＬｔｏｔａｌを、ゼロに近づけることができる。 With reference to equations (4) and (6), the magnitude of the mutual inductance M can be made closer to the parasitic inductance of a single conductor by making the distance d between the two conductors closer to the radius a of the conductor. Therefore, from the equation (7), by bringing the distance d between the two conductors closer to the radius a of the conductors , the total parasitic inductance L total generated by the two conductors can be brought closer to zero.
　図３（ａ）～（ｃ）に示した構成は、図４（ｂ）の構成と等価である。よって、第１導電層２１と第２導電層２２との間の距離を小さくすることにより、第１導電層２１および第２導電層２２から生じる全体の寄生インダクタンスをゼロに近づけることができる。 The configurations shown in FIGS. 3 (a) to 3 (c) are equivalent to the configurations shown in FIGS. 4 (b). Therefore, by reducing the distance between the first conductive layer 21 and the second conductive layer 22, the total parasitic inductance generated from the first conductive layer 21 and the second conductive layer 22 can be brought close to zero.
　図５（ａ）は、第１導電層２１および第２導電層２２から生じる全体の寄生インダクタンスＬ０の周波数応答をシミュレーションにより求めたシミュレーション結果を示すグラフである。 FIG. 5A is a graph showing the simulation results obtained by simulating the frequency response of the entire parasitic inductance L0 generated from the first conductive layer 21 and the second conductive layer 22.
　図５（ａ）において、横軸は周波数、縦軸はインダクタンスである。横軸は、駆動電流のパルス幅に対応する。すなわち、パルス幅の時間長が１０ｎｓｅｃの場合、周波数は１００ＭＨｚとなる。縦軸は、第１導電層２１と第２導電層２２を駆動電流が流れたときの、第１導電層２１および第２導電層２２全体で生じる寄生インダクタンスの大きさである。 In FIG. 5A, the horizontal axis is frequency and the vertical axis is inductance. The horizontal axis corresponds to the pulse width of the drive current. That is, when the time length of the pulse width is 10 nsec, the frequency is 100 MHz. The vertical axis is the magnitude of the parasitic inductance generated in the entire first conductive layer 21 and the second conductive layer 22 when the driving current flows through the first conductive layer 21 and the second conductive layer 22.
　シミュレーションでは、第１導電層２１および第２導電層２２が何れも、平面視において正方形の同じサイズであると想定した。ここでは、第１導電層２１および第２導電層２２の各辺の長さを２０ｍｍに設定し、第１導電層２１および第２導電層２２の厚みを０．０３５ｍｍに設定した。また、第１導電層２１および第２導電層２２の比誘電率および誘電正接を、それぞれ、４．５および０．０１５に設定した。第１導電層２１と第２導電層２２との間の層間距離ｄは、０．３ｍｍに設定した。 In the simulation, it was assumed that both the first conductive layer 21 and the second conductive layer 22 have the same square size in a plan view. Here, the length of each side of the first conductive layer 21 and the second conductive layer 22 is set to 20 mm, and the thickness of the first conductive layer 21 and the second conductive layer 22 is set to 0.035 mm. Further, the relative permittivity and the dielectric loss tangent of the first conductive layer 21 and the second conductive layer 22 were set to 4.5 and 0.015, respectively. The interlayer distance d between the first conductive layer 21 and the second conductive layer 22 was set to 0.3 mm.
　図５（ａ）に示すように、上記シミュレーション条件により第１導電層２１および第２導電層２２が構成されると、駆動電流の周波数が１００ＭＨｚ（パルス幅の時間長が１０ｎｓｅｃ）である場合の全体の寄生インダクタンスＬ０は、１．０３ｎＨ程度に抑制された。また、駆動電流の周波数が１００ＭＨｚよりやや小さい５０ＭＨｚ程度であっても、全体の寄生インダクタンスＬ０は１．０５ｎＨ程度に抑制され、駆動電流のパルス幅の時間長が１０ｎｓｅｃよりやや長い場合も、第１導電層２１および第２導電層２２から生じる全体の寄生インダクタンスを効果的に抑制できることを確認できた。 As shown in FIG. 5A, when the first conductive layer 21 and the second conductive layer 22 are configured under the above simulation conditions, the frequency of the drive current is 100 MHz (the time length of the pulse width is 10 nsec). The overall parasitic inductance L0 was suppressed to about 1.03 nH. Further, even when the frequency of the drive current is about 50 MHz, which is slightly smaller than 100 MHz, the total parasitic inductance L0 is suppressed to about 1.05 nH, and the time length of the pulse width of the drive current is slightly longer than 10 nsec. It was confirmed that the total parasitic inductance generated from the conductive layer 21 and the second conductive layer 22 can be effectively suppressed.
　図５（ｂ）は、駆動電流の周波数が１００ＭＨｚであるとき第１導電層２１および第２導電層２２から生じる全体の寄生インダクタンスが、第１導電層２１と第２導電層２２との間の層間距離ｄの変化に応じて変化する様子をシミュレーションにより求めたシミュレーション結果を示すグラフである。 In FIG. 5B, when the frequency of the drive current is 100 MHz, the total parasitic inductance generated from the first conductive layer 21 and the second conductive layer 22 is between the first conductive layer 21 and the second conductive layer 22. It is a graph which shows the simulation result which obtained the state which changes according to the change of the interlayer distance d by the simulation.
　図５（ｂ）において、横軸は層間距離（ｍｍ）であり、縦軸は寄生インダクタンス（ｎＨ）である。層間距離を除くシミュレーション条件は、図５（ａ）のシミュレーション条件と同様である。 In FIG. 5B, the horizontal axis is the interlayer distance (mm) and the vertical axis is the parasitic inductance (nH). The simulation conditions excluding the interlayer distance are the same as the simulation conditions of FIG. 5A.
　図５（ｂ）のシミュレーション結果から、第１導電層２１と第２導電層２２との間の層間距離ｄが小さくなるに応じて、第１導電層２１および第２導電層２２の全体の寄生インダクタンスが減少することが確認できた。 From the simulation results of FIG. 5B, as the interlayer distance d between the first conductive layer 21 and the second conductive layer 22 becomes smaller, the entire parasitism of the first conductive layer 21 and the second conductive layer 22 It was confirmed that the inductance decreased.
　以上のシミュレーション結果から、図３（ａ）～（ｃ）の構成を用いることで、第１導電層２１と第２導電層２２との間の相互インダクタンスにより、第１導電層２１および第２導電層２２の全体の寄生インダクタンスを効果的に減少させ得ることが確認できた。これにより、寄生インダクタンスによるパルス光の特性の劣化を抑制でき、光源１２を、高強度かつ短パルスでパルス発光させることができる。 From the above simulation results, by using the configurations shown in FIGS. 3A to 3C, the mutual inductance between the first conductive layer 21 and the second conductive layer 22 causes the first conductive layer 21 and the second conductive layer 21 to be conductive. It was confirmed that the total parasitic inductance of the layer 22 can be effectively reduced. As a result, deterioration of the characteristics of the pulsed light due to the parasitic inductance can be suppressed, and the light source 12 can be made to emit a pulse with a high intensity and a short pulse.
　次に、上記構成の発光装置１を距離測定装置に搭載した場合の構成について説明する。 Next, a configuration when the light emitting device 1 having the above configuration is mounted on the distance measuring device will be described.
　図６は、距離測定装置３の構成を示すブロック図である。図６には、いわゆるフラッシュ方式の距離測定装置３が示されている。 FIG. 6 is a block diagram showing the configuration of the distance measuring device 3. FIG. 6 shows a so-called flash type distance measuring device 3.
　距離測定装置３は、発光装置１と、投射光学系３０と、受光部４０と、制御部５１と、信号処理部５２と、距離算出部５３と、を備える。 The distance measuring device 3 includes a light emitting device 1, a projection optical system 30, a light receiving unit 40, a control unit 51, a signal processing unit 52, and a distance calculation unit 53.
　発光装置１は、上述の光源１２と、駆動回路１０と、を備える。駆動回路１０は、図１に示す回路のうち、光源１２を除く回路部分を含む。駆動回路１０は、制御部５１からの指令に応じて、光源１２をパルス発光させる。パルス発光のための構成および動作は、上記のとおりである。 The light emitting device 1 includes the above-mentioned light source 12 and a drive circuit 10. The drive circuit 10 includes a circuit portion of the circuit shown in FIG. 1 excluding the light source 12. The drive circuit 10 causes the light source 12 to emit light in pulses in response to a command from the control unit 51. The configuration and operation for pulse emission are as described above.
　光源１２は、レーザダイオードであり、所定波長のレーザ光（投射光）を出射する。距離測定装置３が車両に搭載される場合、光源１２の出射波長は、たとえば、赤外の波長帯（たとえば９０５ｎｍ）に設定される。距離測定装置３の使用態様に応じて、光源１２の出射波長は適宜変更され得る。光源１２が、ＬＥＤやハロゲンランプ等であってもよい。 The light source 12 is a laser diode and emits a laser beam (projected light) having a predetermined wavelength. When the distance measuring device 3 is mounted on a vehicle, the emission wavelength of the light source 12 is set to, for example, an infrared wavelength band (for example, 905 nm). The emission wavelength of the light source 12 may be appropriately changed depending on the usage mode of the distance measuring device 3. The light source 12 may be an LED, a halogen lamp, or the like.
　投射光学系３０は、光源１２から出射された投射光を所定の広がり角で測距領域Ａ１０に導くとともに、測距領域Ａ１０において均一な強度分布とするように構成される。投射光学系３０は、単一のレンズからなっていてもよく、あるいは、複数のレンズを含んでもよい。また、投射光学系３０が、凹面ミラー等を含んでもよい。 The projection optical system 30 is configured to guide the projected light emitted from the light source 12 to the ranging region A10 at a predetermined spread angle and to have a uniform intensity distribution in the ranging region A10. The projection optical system 30 may consist of a single lens or may include a plurality of lenses. Further, the projection optical system 30 may include a concave mirror or the like.
　受光部４０は、測距領域Ａ１０からの反射光を受光して検出信号を出力する。受光部４０は、受光光学系４１と撮像素子４２を備える。 The light receiving unit 40 receives the reflected light from the ranging area A10 and outputs a detection signal. The light receiving unit 40 includes a light receiving optical system 41 and an image pickup element 42.
　受光光学系４１は、測距領域Ａ１０からの反射光を集光して、撮像素子４２の受光面４２ａに集光する。受光光学系４１は、単一のレンズからなっていてもよく、あるいは、複数のレンズを含んでもよい。また、受光光学系４１が、凹面ミラー等を含んでもよい。 The light receiving optical system 41 collects the reflected light from the ranging region A10 and collects it on the light receiving surface 42a of the image pickup element 42. The light receiving optical system 41 may consist of a single lens or may include a plurality of lenses. Further, the light receiving optical system 41 may include a concave mirror or the like.
　撮像素子４２は、受光面４２ａに配置された複数の画素により反射光を受光して、受光した反射光の強度に応じた検出信号を出力する。受光面４２ａには、多数の画素がマトリクス状に並んでいる。各画素には、たとえば、アバランシェフォトダイオードが配置される。各画素に他の光検出素子が配置されてもよい。 The image sensor 42 receives reflected light by a plurality of pixels arranged on the light receiving surface 42a, and outputs a detection signal according to the intensity of the received reflected light. A large number of pixels are arranged in a matrix on the light receiving surface 42a. For example, an avalanche photodiode is arranged in each pixel. Other photodetection elements may be arranged in each pixel.
　なお、受光光学系４１と撮像素子４２との間に、投射光の波長帯域を透過させ、その他の波長帯域の光を遮断するフィルタが配置されてもよい。これにより、投射光とは異なる波長の不要光が撮像素子４２の受光面４２ａに入射することを抑制できる。また、光源１２が赤外光を出射する場合、撮像素子４２は、赤外の波長帯のみに検出感度を有していてもよい。これにより、不要光である可視光が撮像素子４２により検出されることを抑止できる。 A filter that transmits the wavelength band of the projected light and blocks the light in other wavelength bands may be arranged between the light receiving optical system 41 and the image pickup element 42. As a result, it is possible to prevent unnecessary light having a wavelength different from that of the projected light from being incident on the light receiving surface 42a of the image pickup device 42. Further, when the light source 12 emits infrared light, the image pickup device 42 may have detection sensitivity only in the infrared wavelength band. As a result, it is possible to prevent the image sensor 42 from detecting visible light, which is unnecessary light.
　制御部５１は、演算処理回路とメモリを備え、たとえばＦＰＧＡやＭＰＵにより構成される。制御部５１は、駆動回路１０に制御信号を入力して、駆動回路１０を介して光源１２を制御する。駆動回路１０は、制御信号に応じて、所定の強度およびパルス幅で、光源１２をパルス発光させる。また、制御部５１は、駆動回路１０に入力した制御信号を、駆動回路１０への入力と同じタイミングで、距離算出部５３にも入力する。 The control unit 51 includes an arithmetic processing circuit and a memory, and is composed of, for example, an FPGA or an MPU. The control unit 51 inputs a control signal to the drive circuit 10 and controls the light source 12 via the drive circuit 10. The drive circuit 10 causes the light source 12 to emit a pulse with a predetermined intensity and pulse width according to the control signal. Further, the control unit 51 also inputs the control signal input to the drive circuit 10 to the distance calculation unit 53 at the same timing as the input to the drive circuit 10.
　信号処理部５２は、撮像素子４２から出力された各画素の検出信号に対し、増幅およびノイズ除去の処理を行って、処理後の検出信号を距離算出部５３に出力する。 The signal processing unit 52 performs amplification and noise removal processing on the detection signal of each pixel output from the image sensor 42, and outputs the processed detection signal to the distance calculation unit 53.
　距離算出部５３は、演算処理回路とメモリとを備え、距離の演算を行う回路である。距離算出部５３は、撮像素子４２の画素ごとに、制御部５１からパルス発光に応じて制御信号を受信したタイミングと、信号処理部５２から各画素の検出信号を受信したタイミングとに基づいて、測距領域Ａ１０内の対象物までの距離を、画素ごとに算出する。そして、距離算出部５３は、画素ごとに算出した距離を各画素の位置にマッピングした一画面分（１フレーム分）の距離画像データを生成し、生成した距離画像データを距離測定装置３の表示部や、距離測定装置３の外部の装置などに出力する。 The distance calculation unit 53 is a circuit that includes a calculation processing circuit and a memory and performs a distance calculation. The distance calculation unit 53 is based on the timing at which the control signal is received from the control unit 51 in response to the pulse emission and the timing at which the detection signal of each pixel is received from the signal processing unit 52 for each pixel of the image pickup element 42. The distance to the object in the distance measuring area A10 is calculated for each pixel. Then, the distance calculation unit 53 generates distance image data for one screen (one frame) in which the distance calculated for each pixel is mapped to the position of each pixel, and the generated distance image data is displayed on the distance measuring device 3. It is output to a unit or an external device of the distance measuring device 3.
　図６の構成によれば、上記構成の発光装置１を備えるため、寄生インダクタンスによるパルス光の特性の劣化を抑制でき、高強度かつ短パルスのパルス光を測距領域Ａ１０に投射できる。よって、測距の精度を高めることができる。 According to the configuration of FIG. 6, since the light emitting device 1 having the above configuration is provided, deterioration of the characteristics of the pulsed light due to the parasitic inductance can be suppressed, and high-intensity and short-pulse pulsed light can be projected onto the ranging region A10. Therefore, the accuracy of distance measurement can be improved.
　＜実施形態の効果＞
　上記実施形態によれば、以下の効果が奏され得る。 <Effect of embodiment>
According to the above embodiment, the following effects can be achieved.
　図３（ａ）～（ｃ）に示したように、第１導電層２１と第２導電層２２とに互いに逆方向に駆動電流が流れる。このため、図４（ｂ）を参照して説明したように、第１導電層２１と第２導電層２２との間の相互インダクタンスＭにより、駆動電流が流れる経路の寄生インダクタンスが減少する。よって、寄生インダクタンスによるパルス光の特性の劣化を抑制することができる。 As shown in FIGS. 3A to 3C, a drive current flows in the first conductive layer 21 and the second conductive layer 22 in opposite directions to each other. Therefore, as described with reference to FIG. 4B, the mutual inductance M between the first conductive layer 21 and the second conductive layer 22 reduces the parasitic inductance of the path through which the drive current flows. Therefore, deterioration of the characteristics of the pulsed light due to the parasitic inductance can be suppressed.
　図３（ａ）～（ｃ）に示したように、蓄電素子１１、光源１２およびスイッチ素子１３が、一方向に並んで配置されるため、第１導電層２１および第２導電層２２も、一方向に延びることになる。このため、第１導電層２１および第２導電層２２の長さを短縮でき、第１導電層２１および第２導電層２２の寄生インダクタンスを小さくできる。よって、駆動電流が流れる経路全体の寄生インダクタンスを顕著に減少させることができ、寄生インダクタンスによるパルス光の特性の劣化をより確実に抑制できる。 As shown in FIGS. 3A to 3C, since the power storage element 11, the light source 12, and the switch element 13 are arranged side by side in one direction, the first conductive layer 21 and the second conductive layer 22 are also arranged. It will extend in one direction. Therefore, the lengths of the first conductive layer 21 and the second conductive layer 22 can be shortened, and the parasitic inductance of the first conductive layer 21 and the second conductive layer 22 can be reduced. Therefore, the parasitic inductance of the entire path through which the drive current flows can be remarkably reduced, and the deterioration of the pulsed light characteristics due to the parasitic inductance can be suppressed more reliably.
　図３（ａ）～（ｃ）に示したように、駆動電流の流れに垂直な方向（Ｙ軸方向）において、第１導電層２１の幅および第２導電層２２の幅が等しい。このように、駆動電流の流れに垂直な方向において第１導電層２１の幅を第２導電層２２の幅まで広げることにより、第１導電層２１の自己インダクタンスを小さくできる。よって、駆動電流が流れる経路全体の寄生インダクタンスを容易に減少させることができ、寄生インダクタンスによるパルス光の特性の劣化をより確実に抑制できる。 As shown in FIGS. 3A to 3C, the width of the first conductive layer 21 and the width of the second conductive layer 22 are equal in the direction perpendicular to the flow of the drive current (Y-axis direction). In this way, by widening the width of the first conductive layer 21 to the width of the second conductive layer 22 in the direction perpendicular to the flow of the drive current, the self-inductance of the first conductive layer 21 can be reduced. Therefore, the parasitic inductance of the entire path through which the drive current flows can be easily reduced, and the deterioration of the pulsed light characteristics due to the parasitic inductance can be suppressed more reliably.
　図６に示したように、距離測定装置３は、図３（ａ）～（ｃ）に示した発光装置１を備え、さらに、発光装置１から出射されるパルス光を目標領域（測距領域Ａ１０）に投射する投射光学系３０と、パルス光の物体からの反射光を受光する受光部４０と、を備える。発光装置１は、図３（ａ）～（ｃ）の構成を備えるため、上記のように、寄生インダクタンスによるパルス光の特性の劣化を抑制できる。このため、距離測定装置３は、高強度かつ短パルスのパルス光を測距領域Ａ１０に投射できる。よって、距離測定装置３における測距の精度を高めることができる。 As shown in FIG. 6, the distance measuring device 3 includes the light emitting device 1 shown in FIGS. 3A to 3C, and further, the pulsed light emitted from the light emitting device 1 is set to a target region (distance measuring region). A projection optical system 30 for projecting to A10) and a light receiving unit 40 for receiving reflected light from an object of pulsed light are provided. Since the light emitting device 1 has the configurations shown in FIGS. 3A to 3C, deterioration of the characteristics of the pulsed light due to the parasitic inductance can be suppressed as described above. Therefore, the distance measuring device 3 can project high-intensity and short-pulse pulsed light onto the range-finding region A10. Therefore, the accuracy of distance measurement in the distance measuring device 3 can be improved.
　＜変更例１＞
　上記実施形態では、蓄電素子１１は、１つのキャパシタからなっていたが、これに限らず、たとえば以下に示す変更例１に示すように、複数のキャパシタからなってもよい。 <Change example 1>
In the above embodiment, the power storage element 11 is composed of one capacitor, but is not limited to this, and may be composed of a plurality of capacitors, for example, as shown in the following modification example 1.
　図７は、変更例１に係る、回路基板２の上面を模式的に示す図である。 FIG. 7 is a diagram schematically showing the upper surface of the circuit board 2 according to the modification example 1.
　変更例１では、上記実施形態と比較して、蓄電素子１１が、駆動電流の流れ方向（Ｘ軸方向）に対して並列に接続された１０個のキャパシタ１１ａからなる。具体的には、配線部２１ａと配線部２１ｂとの間に、蓄電素子１１の１０個のキャパシタ１１ａが、並列に接続される。 In the first modification, the storage element 11 is composed of ten capacitors 11a connected in parallel with respect to the flow direction of the drive current (X-axis direction) as compared with the above embodiment. Specifically, 10 capacitors 11a of the power storage element 11 are connected in parallel between the wiring portion 21a and the wiring portion 21b.
　変更例１においても、領域Ａ１のＹ軸方向（駆動電流の流れに垂直な方向）の幅は、蓄電素子１１、光源１２およびスイッチ素子１３のＹ軸方向の幅よりも広い。変更例１のその他の構成は、上記実施形態と同様である。 Also in the modification example 1, the width of the region A1 in the Y-axis direction (direction perpendicular to the flow of the drive current) is wider than the width of the power storage element 11, the light source 12, and the switch element 13 in the Y-axis direction. Other configurations of the first modification are the same as those of the above embodiment.
　また、１０個のキャパシタ１１ａからなる蓄電素子１１の静電容量は、上記実施形態における蓄電素子１１の静電容量と同じである。したがって、変更例１の構成によっても、上記実施形態と同様の電流量の駆動電流を、光源１２に供給できる。 Further, the capacitance of the power storage element 11 composed of 10 capacitors 11a is the same as the capacitance of the power storage element 11 in the above embodiment. Therefore, even with the configuration of the first modification, the drive current having the same amount of current as that of the above embodiment can be supplied to the light source 12.
　＜変更例１の効果＞
　実施形態と同様、第１導電層２１と第２導電層２２とに互いに逆方向に駆動電流が流れるため、第１導電層２１と第２導電層２２との間の相互インダクタンスＭにより、駆動電流が流れる経路の寄生インダクタンスが減少する。よって、寄生インダクタンスによるパルス光の特性の劣化を抑制することができる。 <Effect of change example 1>
As in the embodiment, since the drive current flows in the first conductive layer 21 and the second conductive layer 22 in opposite directions, the drive current is caused by the mutual inductance M between the first conductive layer 21 and the second conductive layer 22. The parasitic inductance of the path through which the current flows is reduced. Therefore, deterioration of the characteristics of the pulsed light due to the parasitic inductance can be suppressed.
　また、蓄電素子１１は、複数のキャパシタ１１ａが並列接続されることにより構成されるため、同じ静電容量の１つのキャパシタで蓄電素子１１が構成される場合に比べ、蓄電素子１１のインダクタンスを顕著に減少させ得る。よって、駆動電流が流れる経路全体の寄生インダクタンスをより一層減少させることができ、寄生インダクタンスによるパルス光の特性の劣化をより確実に抑制できる。 Further, since the power storage element 11 is configured by connecting a plurality of capacitors 11a in parallel, the inductance of the power storage element 11 is remarkable as compared with the case where the power storage element 11 is composed of one capacitor having the same capacitance. Can be reduced to. Therefore, the parasitic inductance of the entire path through which the drive current flows can be further reduced, and the deterioration of the pulsed light characteristics due to the parasitic inductance can be suppressed more reliably.
　＜変更例２＞
　上記実施形態では、蓄電素子１１、光源１２およびスイッチ素子１３は、Ｘ軸に平行な直線上に配置されたが、たとえば以下の変更例２に示すように、必ずしも直線上に配置されなくてもよい。 <Change example 2>
In the above embodiment, the power storage element 11, the light source 12, and the switch element 13 are arranged on a straight line parallel to the X axis, but they are not necessarily arranged on a straight line, for example, as shown in the following modification example 2. good.
　図８（ａ）、（ｂ）は、それぞれ、変更例２に係る、回路基板２の上面および下面を模式的に示す図である。 8 (a) and 8 (b) are diagrams schematically showing the upper surface and the lower surface of the circuit board 2 according to the second modification, respectively.
　図８（ａ）に示すように、変更例２では、領域Ａ１は、略Ｌ字形状に折れ曲がった形状を有している。配線部２１ａは、Ｘ軸方向に延びる配線部により構成される。配線部２１ｂは、Ｘ軸方向に延びる配線部と、Ｘ軸およびＹ軸に対して４５°傾いた方向に延びる配線部とにより構成される。配線部２１ｂは、Ｘ軸およびＹ軸に対して４５°傾いた方向に延びる配線部と、Ｙ軸方向に延びる配線部と、により構成される。配線部２１ｄは、Ｙ軸方向に延びる配線部により構成される。接続部２３は、配線部２１ａのＸ軸負側の端部付近と、配線部２１ｄのＹ軸負側の端部付近と、に設けられる。 As shown in FIG. 8A, in the second modification, the region A1 has a shape bent into a substantially L-shape. The wiring portion 21a is composed of a wiring portion extending in the X-axis direction. The wiring portion 21b is composed of a wiring portion extending in the X-axis direction and a wiring portion extending in a direction inclined by 45 ° with respect to the X-axis and the Y-axis. The wiring portion 21b is composed of a wiring portion extending in a direction inclined by 45 ° with respect to the X-axis and the Y-axis, and a wiring portion extending in the Y-axis direction. The wiring portion 21d is composed of a wiring portion extending in the Y-axis direction. The connection portion 23 is provided near the end of the wiring portion 21a on the negative side of the X-axis and near the end of the wiring portion 21d on the negative side of the Y-axis.
　図８（ｂ）に示すように、第２導電層２２は、図８（ａ）に示す第１導電層２１（配線部２１ａ、２１ｂ、２１ｃ、２１ｄ）の外形と同様の形状である。第２導電層２２は、長手方向の両端付近において、２つの接続部２３により、第１導電層２１と接続されている。 As shown in FIG. 8B, the second conductive layer 22 has the same shape as the outer shape of the first conductive layer 21 ( wiring portions 21a, 21b, 21c, 21d) shown in FIG. 8A. The second conductive layer 22 is connected to the first conductive layer 21 by two connecting portions 23 near both ends in the longitudinal direction.
　変更例２においても、上記実施形態と同様、蓄電素子１１は、配線部２１ａと配線部２１ｂとに跨がって配置され、光源１２は、配線部２１ｂと配線部２１ｃとに跨がって配置され、スイッチ素子１３は、配線部２１ｃと配線部２１ｄとに跨がって配置されている。図８（ａ）、（ｂ）に示すように各部が構成されることにより、蓄電素子１１からの駆動電流が、矢印で示すように第１導電層２１および第２導電層２２を流れる。 Also in the second modification, as in the above embodiment, the power storage element 11 is arranged so as to straddle the wiring portion 21a and the wiring portion 21b, and the light source 12 straddles the wiring portion 21b and the wiring portion 21c. The switch element 13 is arranged so as to straddle the wiring portion 21c and the wiring portion 21d. By configuring each part as shown in FIGS. 8A and 8B, the drive current from the power storage element 11 flows through the first conductive layer 21 and the second conductive layer 22 as shown by the arrows.
　＜変更例２の効果＞
　実施形態と同様、第１導電層２１と第２導電層２２とに互いに逆方向に駆動電流が流れるため、第１導電層２１と第２導電層２２との間の相互インダクタンスＭにより、駆動電流が流れる経路の寄生インダクタンスが減少する。よって、寄生インダクタンスによるパルス光の特性の劣化を抑制することができる。 <Effect of change example 2>
As in the embodiment, since the drive current flows in the first conductive layer 21 and the second conductive layer 22 in opposite directions, the drive current is caused by the mutual inductance M between the first conductive layer 21 and the second conductive layer 22. The parasitic inductance of the path through which the current flows is reduced. Therefore, deterioration of the characteristics of the pulsed light due to the parasitic inductance can be suppressed.
　なお、変更例２では、蓄電素子１１、光源１２およびスイッチ素子１３が、一方向に並ばず、第１導電層２１および第２導電層２２も、折れ曲がった形状を有する。このため、第１導電層２１および第２導電層２２の長さは、上記実施形態よりも長くなる。したがって、第１導電層２１および第２導電層２２の寄生インダクタンス（自己インダクタンス）が上記実施形態に比べて大きくなる。 In the second modification, the power storage element 11, the light source 12, and the switch element 13 are not arranged in one direction, and the first conductive layer 21 and the second conductive layer 22 also have a bent shape. Therefore, the lengths of the first conductive layer 21 and the second conductive layer 22 are longer than those of the above embodiment. Therefore, the parasitic inductance (self-inductance) of the first conductive layer 21 and the second conductive layer 22 is larger than that of the above embodiment.
　駆動電流が流れる経路全体の寄生インダクタンスを簡易かつ円滑に減少させるためには、第１導電層２１および第２導電層２２の寄生インダクタンス（自己インダクタンス）が小さい方が好ましい。よって、この観点からは、上記実施形態のように、蓄電素子１１、光源１２およびスイッチ素子１３を一方向に並んで配置し、第１導電層２１および第２導電層２２を一方向に延びるように配置するのが好ましい。 In order to easily and smoothly reduce the parasitic inductance of the entire path through which the drive current flows, it is preferable that the parasitic inductance (self-inductance) of the first conductive layer 21 and the second conductive layer 22 is small. Therefore, from this viewpoint, as in the above embodiment, the power storage element 11, the light source 12, and the switch element 13 are arranged side by side in one direction, and the first conductive layer 21 and the second conductive layer 22 are extended in one direction. It is preferable to place it in.
　＜その他の変更例＞
　発光装置１および距離測定装置３の構成は、上記実施形態に示した構成以外に、種々の変更が可能である。 <Other changes>
The configurations of the light emitting device 1 and the distance measuring device 3 can be variously changed in addition to the configurations shown in the above embodiment.
　たとえば、上記実施形態では、接続部２３は、第１導電層２１の配線部２１ａ、２１ｄに、それぞれ１つずつ設けられたが、それぞれ複数個ずつ設けられてもよい。 For example, in the above embodiment, one connecting portion 23 is provided in each of the wiring portions 21a and 21d of the first conductive layer 21, but a plurality of connecting portions 23 may be provided respectively.
　また、上記実施形態では、光源１２は、１つの発光素子により構成されたが、これに限らず、複数の発光素子により構成されてもよい。たとえば、光源１２は、複数のレーザダイオードにより構成されてもよく、複数のＬＥＤにより構成されてもよい。光源１２が複数の発光素子により構成される場合、各発光素子は、回路に対して直列に接続されてもよく並列に接続されてもよい。 Further, in the above embodiment, the light source 12 is composed of one light emitting element, but the light source 12 is not limited to this, and may be composed of a plurality of light emitting elements. For example, the light source 12 may be composed of a plurality of laser diodes or may be composed of a plurality of LEDs. When the light source 12 is composed of a plurality of light emitting elements, each light emitting element may be connected in series or in parallel to the circuit.
　また、上記実施形態では、スイッチ素子１３は、１つのＦＥＴにより構成されていたが、これに限らず、複数のスイッチ素子により構成されても良い。各ＦＥＴは、回路に対して直列に接続されてもよく並列に接続されてもよい。 Further, in the above embodiment, the switch element 13 is composed of one FET, but the present invention is not limited to this, and the switch element 13 may be composed of a plurality of switch elements. Each FET may be connected in series or in parallel to the circuit.
　また、上記実施形態では、駆動電流が流れる方向に沿って、蓄電素子１１、光源１２およびスイッチ素子１３がこの順で配置されたが、配置順はこれに限らない。たとえば、駆動電流が流れる方向に沿って、蓄電素子１１、スイッチ素子１３および光源１２がこの順で配置されてもよい。 Further, in the above embodiment, the power storage element 11, the light source 12, and the switch element 13 are arranged in this order along the direction in which the drive current flows, but the arrangement order is not limited to this. For example, the power storage element 11, the switch element 13, and the light source 12 may be arranged in this order along the direction in which the drive current flows.
　なお、上記実施形態にように、駆動電流が流れる方向に沿って、蓄電素子１１、光源１２およびスイッチ素子１３がこの順で配置されると、スイッチ素子１３がグランドに対して直接的に接続されるため、スイッチ素子１３で生じた熱がグランドに伝搬しやすくなる。これにより、スイッチ素子１３の放熱特性が良好となるため、スイッチ素子１３の導通時の抵抗（オン抵抗）が抑制される。よって、上記実施形態のように、蓄電素子１１、光源１２およびスイッチ素子１３がこの順で配置されるのが好ましい。 When the power storage element 11, the light source 12, and the switch element 13 are arranged in this order along the direction in which the drive current flows as in the above embodiment, the switch element 13 is directly connected to the ground. Therefore, the heat generated by the switch element 13 is likely to propagate to the ground. As a result, the heat dissipation characteristics of the switch element 13 are improved, so that the resistance (on resistance) of the switch element 13 at the time of conduction is suppressed. Therefore, it is preferable that the power storage element 11, the light source 12, and the switch element 13 are arranged in this order as in the above embodiment.
　また、上記実施形態では、発光装置１は、測距領域Ａ１０全体に対して同時に光を照射する、いわゆるフラッシュ方式の距離測定装置３に搭載された。しかしながら、これに限らず、発光装置１は、ラインビームを短辺方向に走査する方式の距離測定装置や、点ビームを２次元方向に走査する方式の距離測定装置に搭載されてもよい。 Further, in the above embodiment, the light emitting device 1 is mounted on a so-called flash type distance measuring device 3 that simultaneously irradiates the entire range measuring region A10 with light. However, the present invention is not limited to this, and the light emitting device 1 may be mounted on a distance measuring device of a method of scanning a line beam in the short side direction or a distance measuring device of a method of scanning a point beam in a two-dimensional direction.
　また、上記実施形態では、図３（ａ）、（ｂ）および図８（ａ）、（ｂ）に示したように、第１導電層２１および第２導電層２２の配置領域が、平面視において（Ｚ軸方向に見て）互いに一致していた。しかしながら、第１導電層２１および第２導電層２２の配置領域は、必ずしも、平面視において、互いに一致していなくてもよい。たとえば、第１導電層２１の配置領域が、第２導電層２２に対して、Ｘ－Ｙ平面に平行な方向に数度程度傾いていてもよい。あるいは、第１導電層２１の配置領域が、第２導電層２２に対して、Ｘ－Ｙ平面に平行な方向に多少シフトしていてもよい。また、平面視における第１導電層２１および第２導電層２２の輪郭形状が、互いに異なっていてもよい。たとえば、第１導電層２１の幅または長さが、第２導電層２２に対して相違していてもよい。 Further, in the above embodiment, as shown in FIGS. 3 (a) and 3 (b) and FIGS. 8 (a) and 8 (b), the arrangement regions of the first conductive layer 21 and the second conductive layer 22 are viewed in a plan view. They were in agreement with each other (as viewed in the Z-axis direction). However, the arrangement regions of the first conductive layer 21 and the second conductive layer 22 do not necessarily have to coincide with each other in a plan view. For example, the arrangement region of the first conductive layer 21 may be inclined by several degrees with respect to the second conductive layer 22 in a direction parallel to the XY plane. Alternatively, the arrangement region of the first conductive layer 21 may be slightly shifted in the direction parallel to the XY plane with respect to the second conductive layer 22. Further, the contour shapes of the first conductive layer 21 and the second conductive layer 22 in a plan view may be different from each other. For example, the width or length of the first conductive layer 21 may be different from that of the second conductive layer 22.
　また、上記実施形態では、光源１２に対して蓄電素子１１から駆動電流が供給されたが、蓄電素子１１以外の電流源を用いて、光源１２に駆動電流が供給されてもよい。たとえば、レーザ駆動電圧に昇降圧される電圧レギュレータと、電圧レギュレータに直列に接続された電流制限用の抵抗器、または定電流ダイオードが、光源１２に駆動電流を供給するための電流源として用いられてもよい。この場合も、電流源は、第１導電層２１によって、光源１２およびスイッチ素子１３と直列に接続され、第２導電層２２が接続部２３によって接続される。これにより、上記実施形態と同様、駆動電流が流れる経路の寄生インダクタンスを減少させることができ、寄生インダクタンスによるパルス光の特性の劣化を抑制することができる。 Further, in the above embodiment, the drive current is supplied to the light source 12 from the power storage element 11, but the drive current may be supplied to the light source 12 by using a current source other than the power storage element 11. For example, a voltage regulator that is stepped up and down by the laser drive voltage, a current limiting resistor connected in series with the voltage regulator, or a constant current diode is used as a current source for supplying the drive current to the light source 12. You may. Also in this case, the current source is connected in series with the light source 12 and the switch element 13 by the first conductive layer 21, and the second conductive layer 22 is connected by the connecting portion 23. As a result, as in the above embodiment, the parasitic inductance of the path through which the drive current flows can be reduced, and the deterioration of the characteristics of the pulsed light due to the parasitic inductance can be suppressed.
　この他、本発明の実施の形態は、特許請求の範囲に示された技術的思想の範囲内において、適宜、種々の変更が可能である。 In addition, various modifications of the embodiment of the present invention can be made as appropriate within the scope of the technical idea shown in the claims.
　１　発光装置
　２　回路基板
　３　距離測定装置
　１１　蓄電素子
　１２　光源
　１３　スイッチ素子
　２１　第１導電層
　２２　第２導電層
　２３　接続部
　３０　投射光学系
　４０　受光部
　Ａ１０　測距領域（目標領域） 1 Light emitting device 2 Circuit board 3 Distance measuring device 11 Power storage element 12 Light source 13 Switch element 21 1st conductive layer 22 2nd conductive layer 23 Connection part 30 Projection optical system 40 Light receiving part A10 Distance measurement area (target area)

Claims (7)

  1. 　光源と、
    　前記光源に駆動電流を供給するための蓄電素子と、
    　前記光源の発光および非発光を切り替えるスイッチ素子と、
    　前記光源、前記蓄電素子および前記スイッチ素子が実装される回路基板と、を備え、
    　前記回路基板は、
    　　前記光源、前記蓄電素子および前記スイッチ素子を直列接続する第１導電層と、
    　　前記第１導電層に対し所定距離をおいて対向配置された第２導電層と、
    　　前記第１導電層と前記第２導電層とを接続して、前記第１導電層の前記駆動電流の流れ方向と逆方向に、前記第２導電層に前記駆動電流を流す接続部と、を有する、
    ことを特徴とする発光装置。
          Light source and
    A power storage element for supplying a drive current to the light source, and
    A switch element that switches between light emission and non-light emission of the light source, and
    The light source, the power storage element, and the circuit board on which the switch element is mounted are provided.
    The circuit board is
    A first conductive layer connecting the light source, the power storage element, and the switch element in series,
    A second conductive layer arranged so as to face the first conductive layer at a predetermined distance,
    A connecting portion that connects the first conductive layer and the second conductive layer and causes the drive current to flow through the second conductive layer in the direction opposite to the flow direction of the drive current of the first conductive layer. Have,
    A light emitting device characterized by that.
  2. 　請求項１に記載の発光装置において、
    　前記光源、前記蓄電素子および前記スイッチ素子は、一方向に並んで配置され、
    　前記第１導電層および前記第２導電層は、前記光源、前記蓄電素子および前記スイッチ素子の並び方向に延びている、
    ことを特徴とする発光装置。
          In the light emitting device according to claim 1,
    The light source, the power storage element, and the switch element are arranged side by side in one direction.
    The first conductive layer and the second conductive layer extend in the arrangement direction of the light source, the power storage element, and the switch element.
    A light emitting device characterized by that.
  3. 　請求項１または２に記載の発光装置において、
    　前記蓄電素子、前記光源および前記スイッチ素子が、この順に並んでいる、
    ことを特徴とする発光装置。
          In the light emitting device according to claim 1 or 2.
    The power storage element, the light source, and the switch element are arranged in this order.
    A light emitting device characterized by that.
  4. 　請求項１ないし３の何れか一項に記載の発光装置において、
    　前記蓄電素子は、複数のキャパシタが並列接続されて構成されている、
    ことを特徴とする発光装置。
          In the light emitting device according to any one of claims 1 to 3, the light emitting device
    The power storage element is configured by connecting a plurality of capacitors in parallel.
    A light emitting device characterized by that.
  5. 　請求項１ないし４の何れか一項に記載の発光装置において、
    　前記駆動電流の流れに垂直な方向において、前記第１導電層の幅および第２導電層の幅が等しい、
    ことを特徴とする発光装置。
          In the light emitting device according to any one of claims 1 to 4.
    The width of the first conductive layer and the width of the second conductive layer are equal in the direction perpendicular to the flow of the drive current.
    A light emitting device characterized by that.
  6. 　請求項１ないし５の何れか一項に記載の発光装置と、
    　前記発光装置から出射されるパルス光を目標領域に投射する投射光学系と、
    　前記パルス光の物体からの反射光を受光する受光部と、を備える。
    ことを特徴とする距離測定装置。
          The light emitting device according to any one of claims 1 to 5.
    A projection optical system that projects pulsed light emitted from the light emitting device onto a target region,
    A light receiving unit for receiving the reflected light from the object of the pulsed light is provided.
    A distance measuring device characterized by that.
  7. 　光源と、
    　前記光源に駆動電流を供給するための電流源と、
    　前記光源の発光および非発光を切り替えるスイッチ素子と、
    　前記光源、前記電流源および前記スイッチ素子が実装される回路基板と、を備え、
    　前記回路基板は、
    　　前記光源、前記電流源および前記スイッチ素子を直列接続する第１導電層と、
    　　前記第１導電層に対し所定距離をおいて対向配置された第２導電層と、
    　　前記第１導電層と前記第２導電層とを接続して、前記第１導電層の前記駆動電流の流れ方向と逆方向に、前記第２導電層に前記駆動電流を流す接続部と、を有する、
    ことを特徴とする発光装置。     Light source and
    A current source for supplying a drive current to the light source,
    A switch element that switches between light emission and non-light emission of the light source, and
    The light source, the current source, and the circuit board on which the switch element is mounted are provided.
    The circuit board is
    A first conductive layer connecting the light source, the current source, and the switch element in series,
    A second conductive layer arranged so as to face the first conductive layer at a predetermined distance,
    A connecting portion that connects the first conductive layer and the second conductive layer and causes the drive current to flow through the second conductive layer in the direction opposite to the flow direction of the drive current of the first conductive layer. Have,
    A light emitting device characterized by that.
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US20180278017A1 (en) * 2017-03-23 2018-09-27 Infineon Technologies Ag Circuit and method for driving a laser diode

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WO2023139958A1 (en) * 2022-01-20 2023-07-27 ソニーセミコンダクタソリューションズ株式会社 Semiconductor laser device, distance measurement device, and vehicle-mounted device

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