WO2021254503A1 - 信号检测电路、信号检测方法、指纹识别装置及显示设备 - Google Patents

信号检测电路、信号检测方法、指纹识别装置及显示设备 Download PDF

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WO2021254503A1
WO2021254503A1 PCT/CN2021/101053 CN2021101053W WO2021254503A1 WO 2021254503 A1 WO2021254503 A1 WO 2021254503A1 CN 2021101053 W CN2021101053 W CN 2021101053W WO 2021254503 A1 WO2021254503 A1 WO 2021254503A1
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Prior art keywords
signal
sampling
signals
transistor
period
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PCT/CN2021/101053
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English (en)
French (fr)
Inventor
刘英明
丁小梁
王雷
李秀锋
张晨阳
勾越
崔亮
王玉波
王迎姿
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京东方科技集团股份有限公司
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Publication of WO2021254503A1 publication Critical patent/WO2021254503A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements

Definitions

  • the present disclosure relates to the field of display technology, in particular to a signal detection circuit, a signal detection method, a fingerprint identification device and a display device.
  • ultrasonic signal detection circuits are usually applied to display devices for fingerprint identification.
  • the ultrasonic signal detection circuit in the related art uses a sampling transistor to sample the ultrasonic echo signal.
  • the sampling transistor is turned on for a certain period of time during the positive half period or the negative half period of one cycle of the ultrasonic echo signal, and the sampling transistor During the conduction period, the sampling transistor can sample the piezoelectric signal corresponding to part of the ultrasonic echo signal.
  • the purpose of the embodiments of the present disclosure is to provide a signal detection circuit, a signal detection method, a fingerprint identification device, and a display device.
  • the embodiment of the present disclosure discloses a signal detection circuit, including:
  • the detection module is configured to detect an ultrasonic echo signal and generate a plurality of piezoelectric signals according to the ultrasonic echo signal.
  • the plurality of piezo electron signals correspond to the plurality of periods of ridge signals, or the plurality of piezo electron signals correspond to the plurality of periods of valley signals;
  • sampling module is connected to the detection module, and the sampling module is configured to receive a corresponding sampling signal in each period, and combine the sampling signal corresponding to the period and the plurality of compression
  • the electronic signal is stored at the output terminal of the sampling module.
  • the embodiment of the present disclosure also discloses a fingerprint identification device, which includes a base substrate and the plurality of signal detection circuits, and the plurality of signal detection circuits are arranged on the base substrate.
  • the embodiment of the present disclosure also discloses a display device including a display panel and the fingerprint identification device, and the fingerprint identification device is arranged at the bottom of the display panel.
  • the embodiment of the present disclosure also discloses a signal detection method according to the signal detection circuit, including:
  • the ultrasonic echo signal is detected, and a plurality of piezo electronic signals are generated according to the ultrasonic echo signal, and the plurality of piezo electronic signals correspond to a plurality of periods of the ultrasonic echo signal one-to-one.
  • Each piezo-electronic signal corresponds to the ridge signal of the plurality of ultrasonic echo signals, or the plurality of piezo-electronic signals corresponds to the trough signal of the ultrasonic echo signal; and receiving a corresponding sampling signal in each of the cycles, And the sampling signal and the multiple piezo-electric signals corresponding to the period are stored at the output terminal of the sampling module.
  • the detection module detects multiple cycles of ultrasonic echo signals to generate multiple piezoelectric signals
  • the sampling module receives corresponding sampling signals in each cycle, and combines the sampling signals corresponding to the cycles with Multiple piezoelectric signals are stored at the output of the sampling module. Since multiple piezo-electron signals correspond to multiple-period ridge signals, or multiple piezo-electronic signals correspond to multiple-period valley signals, the signals stored at the output of the sampling module are multiple piezo-electronic signals corresponding to multiple ridge signals.
  • Signal and multiple sampling signals superimposed signal or multiple piezo electronic signals corresponding to multiple trough signals and multiple sampling signals superimposed signal, multiple piezo electronic signals and multiple troughs corresponding to the multiple ridge signals
  • the signal difference between multiple piezo electronic signals corresponding to the signal is greater than the signal difference between the piezoelectric signal corresponding to a single ridge signal and the piezoelectric signal corresponding to a single valley signal in the related art, which is convenient for distinguishing multiple ridges
  • the multiple piezo electronic signals corresponding to the signal and the multiple piezo electronic signals corresponding to the multiple valley signals are beneficial to improve the accuracy of identifying the ridge signal and the valley signal of the product using the signal detection circuit of the embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of an embodiment of a signal detection circuit of the present disclosure
  • FIG. 2 is a schematic structural diagram of another embodiment of a signal detection circuit of the present disclosure.
  • FIG. 3 is a timing diagram of the embodiment of the signal detection circuit in FIG. 1;
  • FIG. 4 is an equivalent circuit diagram of the embodiment of the signal detection circuit in FIG. 1;
  • FIG. 5 is a timing diagram of the embodiment of the signal detection circuit in FIG. 2;
  • Fig. 6 is a structural block diagram of an embodiment of a fingerprint identification device of the present disclosure.
  • FIG. 7 is a schematic structural diagram of an embodiment of a fingerprint identification device of the present disclosure.
  • FIG. 8 is a flow chart of steps of an embodiment of a signal detection method of the present disclosure.
  • a detection module 10 configured to detect an ultrasonic echo signal Vrx, and according to the ultrasonic echo
  • the wave signal Vrx generates multiple piezoelectric signals, and the multiple piezoelectric signals correspond to multiple cycles of the ultrasonic echo signal Vrx one-to-one, and the multiple piezoelectric signals correspond to multiple cycles of ridge signals, or multiple piezoelectric signals correspond to Multiple cycles of trough signals; sampling module 20, sampling module 20 is connected to detection module 10, sampling module 20 is configured to receive the corresponding sampling signal in each cycle, and store the sampling signal corresponding to the cycle and multiple piezoelectric signals At the output of the sampling module 20.
  • the ultrasonic echo signal Vrx Since the ultrasonic echo signal Vrx will oscillate, be absorbed by the material (for example, absorbed by each film layer of the display panel), and gradually attenuate to zero. Therefore, the ultrasonic echo signal Vrx has multiple periods and is stored in the output terminal of the sampling module 20.
  • the signal is a signal in which multiple piezo-electric signals corresponding to multiple ridge signals and multiple sampling signals are superimposed, or a signal in which multiple piezo-electric signals corresponding to multiple valley signals and multiple sampling signals are superimposed, and the multiple waves
  • the signal difference between the multiple piezo-electronic signals corresponding to the ridge signal and the multiple piezo-electronic signals corresponding to the multiple valley signals is larger than the piezoelectric signal corresponding to a single ridge signal and the piezoelectric signal corresponding to a single valley signal in the related art The signal difference between.
  • the product of the detection circuit 100 recognizes the accuracy of the ridge signal and the trough signal.
  • the sampling module 20 may be configured to receive the corresponding sampling signal within the preset time period of the positive half cycle in each cycle, or may be configured to receive the corresponding sampling signal within the preset time period of the negative half cycle in each cycle Corresponding sampling signal.
  • the preset time period may be a time period in which the signal difference between the multiple piezo electronic signals corresponding to the multiple ridge signals and the multiple piezo electronic signals corresponding to the multiple valley signals is maximized.
  • the time length range of the preset time period may be 1/8T to 3/8T out of 0 to 1/2T.
  • the detection module 10 may include an ultrasonic sensor.
  • the ultrasonic sensor may include a transmitting terminal tx, a receiving terminal rx, a piezoelectric material 11, etc., wherein the receiving terminal rx and the output of the sampling module 20 When the potential of the output terminal of the sampling module 20 is low, that is, the potential of the receiving terminal rx is low, the transmitting terminal tx receives the AC signal, and the piezoelectric material 11 in the ultrasonic sensor transmits the ultrasonic signal Vtx; receiving at the transmitting terminal tx When the low-level signal, that is, when the potential of the transmitting terminal tx is low, the receiving terminal rx detects the ultrasonic echo signal Vrx, and the piezoelectric material 11 in the ultrasonic sensor generates a piezoelectric signal according to the ultrasonic echo signal Vrx.
  • the AC signal may be a high frequency and high voltage AC signal.
  • the piezoelectric material 11 may be a polyvinylidene fluoride (PVDF) film type piezoelectric material, an aluminum nitride film (Aluminium nitride film, AlN) piezoelectric material, or a piezoelectric ceramics (Piezoelectric ceramics, PZT) Piezoelectric materials or zinc oxide (ZnO) piezoelectric materials, etc.
  • the piezoelectric material 11 may also be other inorganic piezoelectric materials or organic piezoelectric materials.
  • the piezoelectric material 11 may be arranged between the transmitting terminal tx and the receiving terminal rx.
  • the sampling module 20 may include: a first transistor T1, the first pole of the first transistor T1 is connected to the detection module 10, and in each cycle, the The second electrode of a transistor T1 receives the sampling signal corresponding to the period, the control electrode of the first transistor T1 receives the first control signal corresponding to the period to turn on, and the first electrode of the first transistor T1 serves as the output terminal of the sampling module 20;
  • the level of the sampling signal corresponding to one cycle is lower than the level of the sampling signal corresponding to the following cycle.
  • the sampling signal and the piezoelectric signal corresponding to the period are stored in the first electrode of the first transistor T1.
  • the level of the sampling signal corresponding to the previous cycle is lower than the level of the sampling signal corresponding to the next cycle, which can ensure that the sampling signal and the piezoelectric signal corresponding to the previous cycle are stored in the first pole of the first transistor T1
  • the sampling signal and the piezo-electric signal corresponding to the latter period can continue to be superimposed on the first pole of the first transistor T1. As shown in FIG.
  • sampling signals corresponding to multiple cycles may be in the same sampling waveform Vbias, and first control signals corresponding to multiple cycles may be in the same control waveform Vrst.
  • the sampling signals corresponding to the multiple cycles are sampling signal 1 and sampling signal 2, respectively, and the first control signals corresponding to the multiple cycles are control signal 3 and control signal 4, respectively.
  • the second electrode of the first transistor T1 receives the bias signal corresponding to the cycle, and the bias signal corresponding to the cycle
  • the level of is lower than the level of the sampling signal corresponding to the period.
  • the bias signal corresponding to the period can reduce the voltage difference between the first pole and the second pole of the first transistor T1, so as to reduce the leakage current of the first transistor T1.
  • the bias signals corresponding to multiple cycles can be set in the sampling waveform Vbias. In FIG. 3, there are two multiple cycles, and the bias signals corresponding to the multiple cycles are bias signal 5 and bias signal 6 respectively. Specifically, the time lengths of the bias signals corresponding to the multiple cycles may be the same or at least two different.
  • the equivalent circuit corresponding to the signal detection circuit 100 shown in FIG. 1 may be as shown in FIG. 4, where the parasitic capacitance CP at the output end of the sampling module 20 may be the parasitic capacitance of the receiving end rx of the ultrasonic sensor and the first The equivalent capacitance formed by the parasitic capacitance in the transistor T1, and the equivalent capacitance stores the signal at the output terminal of the sampling module 20.
  • the AC signal received by the transmitting terminal tx may be provided by an AC power source AC outside the signal detection circuit 100
  • the capacitor C0 in FIG. 4 is a parasitic capacitance between the transmitting terminal tx and the receiving terminal rx.
  • the sampling module 20 in the signal detection circuit 100 may further include a diode D1.
  • the anode of the diode D1 is connected to the second electrode of the first transistor T1, and the cathode of the diode D1 is connected to the receiving terminal rx.
  • the diode D1 is turned on, and the sampling signal and piezoelectric signal corresponding to the period are stored at the output of the sampling module 20.
  • the sampling signal is at a high level
  • the first transistor T1 does not need to be turned on.
  • the control waveform Vrst is low level.
  • the sampling module 20 may include a plurality of second transistors T2, and the plurality of second transistors T2 correspond to a plurality of periods in a one-to-one manner.
  • the first pole of the transistor T2 is connected to the detection module 10, the second pole of each second transistor T2 receives a sampling signal of a corresponding period, and the control pole of each second transistor T2 receives a second control signal of a corresponding period to turn on ,
  • the first poles of the plurality of second transistors T2 are used as the output end of the sampling module 20; the level of the sampling signal corresponding to the previous period is lower than the level of the sampling signal corresponding to the next period.
  • the sampling signal and the piezoelectric signal of the corresponding period of the second transistor T2 are stored in the first electrode of the second transistor T2.
  • the multiple sampling signals and multiple piezo-electric signals of the first poles of the multiple second transistors T2 are superimposed and stored at the output end of the sampling module 20. Specifically, the level of the sampling signal corresponding to the previous cycle is lower than the level of the sampling signal corresponding to the next cycle, which can ensure that the sampling signal and piezoelectric signal corresponding to the previous cycle are stored in the second transistor corresponding to the previous cycle.
  • the sampling signal and the piezo electronic signal corresponding to the subsequent period can continue to be superimposed on the output terminal of the sampling module 20.
  • the sampling signals corresponding to the multiple cycles can be in multiple different sampling waveforms (the sampling waveform Vbias1 and the sampling waveform Vbias2), and the second control signal corresponding to the multiple cycles can be Respectively in multiple different control waveforms (control waveform Vrst1 and control waveform Vrst2).
  • the sampling signals corresponding to the multiple cycles are sampling signal 7 and sampling signal 8, respectively
  • the second control signals corresponding to the multiple cycles are control signal 9 and control signal 10, respectively.
  • the plurality of second transistors T2 may be at least two same transistors or different transistors
  • the second pole of the second transistor T2 corresponding to the cycle receives the bias signal corresponding to the cycle; the bias corresponding to the cycle
  • the level of the set signal is lower than the level of the sampling signal corresponding to the period.
  • the bias signal corresponding to the period can reduce the voltage difference between the first pole and the second pole of the second transistor T2, so as to reduce the leakage current of the second transistor T2.
  • the multiple cycles are two, and the bias signals corresponding to the multiple cycles are the bias signal 11 and the bias signal 12 respectively.
  • the bias signal 11 is in the sampling waveform Vbias1
  • the bias signal 12 is in the sampling waveform Vbias2.
  • the time lengths of the bias signals corresponding to the multiple cycles may be the same or at least two different.
  • the signal detection circuit 100 of the embodiment of the present disclosure may further include a signal readout module 30 and a read signal line 40, the signal readout module 30 and the sampling module 20
  • the output terminal is connected to the read signal line 40
  • the signal readout module 30 is configured to turn on the output terminal of the sampling module 20 after a plurality of piezoelectric signals and sampling signals corresponding to each cycle are stored at the output terminal of the sampling module 20
  • the read signal line 40 to output the signal stored at the output terminal of the sampling module 20 from the read signal line 40.
  • the ultrasonic echo signal Vrx is a signal formed by reflecting the ultrasonic signal Vtx from a finger
  • the plurality of piezo electrons corresponding to the plurality of ridge signals The signal can be identified as multiple piezo-electronic signals generated by reflecting the ultrasonic signal Vtx from the ridge of the finger, and multiple piezo-electronic signals corresponding to the multiple valley signals can be identified as multiple piezo-electronic signals generated by reflecting the ultrasonic signal Vtx at the valley of the finger. Therefore, the signal output from the reading signal line 40 can be used as a fingerprint identification signal to realize fingerprint identification.
  • the signal readout module 30 may include a third transistor T3 and a fourth transistor T4.
  • the first electrode of the third transistor T3 is connected to the power supply, and the power supply output voltage VDD,
  • the control electrode of the third transistor T3 is connected to the output terminal of the sampling module 20;
  • the first electrode of the fourth transistor T4 is connected to the second electrode of the third transistor T3, and the control electrode of the fourth transistor T4 is configured to receive the third control signal 13.
  • the second pole of the fourth transistor T4 is connected to the read signal line 40. After the control electrode of the fourth transistor T4 receives the third control signal 13, the fourth transistor T4 is turned on, and the third transistor T3 is turned on.
  • the third transistor T3 is turned off, that is, the fourth transistor
  • the T4 control signal readout module 30 is turned on and off.
  • the third transistor T3 converts the voltage signal stored at the output terminal of the sampling module 20 into a current signal, and the current signal is output to the reading signal line 40 through the fourth transistor T4.
  • the greater the voltage corresponding to the voltage signal stored at the output terminal of the sampling module 20 the greater the current signal output by the third transistor T3. That is, the current signal output by the third transistor T3 follows the voltage signal stored at the output terminal of the sampling module 20.
  • the waveform of the third control signal 13 is Vread
  • the waveform of the current signal output by the fourth transistor T4 to the read signal line 40 is Iout
  • the third transistor T3 and the fourth transistor T4 may be the same or different transistors.
  • FIG. 3 is a timing diagram corresponding to the signal detection circuit 100 shown in FIG. 1, and the timing diagram in FIG. 3 includes four stages:
  • the control waveform Vrst is high, the sampling waveform Vbias is low, the first transistor T1 is turned on, the potential of the receiving terminal rx is low, and the transmitting terminal tx receives the AC signal, the piezoelectric The material 11 vibrates and emits an ultrasonic signal Vtx outward, and the control waveform Vrst becomes a low level.
  • the control signal 3 in the control waveform Vrst is high, the sampling signal 1 in the sampling waveform Vbias is high, the first transistor T1 is turned on, and the receiving terminal rx and the sampling signal 1 are connected to the sampling module 20.
  • the output terminal is charged, the electrical signal is stored on the parasitic capacitance Cp, and the waveform Vrst is controlled to be low, the first transistor T1 is turned off, and the bias signal 5 in the sampling waveform Vbias is applied to the second pole of the first transistor T1.
  • the control signal 4 in the control waveform Vrst is at a high level
  • the sampling signal 2 in the sampling waveform Vbias is at a high level
  • the first transistor T1 is turned on again, and the receiving terminal rx and the sampling signal 2 are sent to the sampling module 20
  • the output terminal of Vbias continues to be charged, and the electrical signal is superimposed and stored on the parasitic capacitance Cp.
  • the control waveform Vrst is low, the first transistor T1 is turned off, and the bias signal 6 in the sampling waveform Vbias is applied to the second pole of the first transistor T1 .
  • control waveform Vrst continues to be at a low level, and the bias signal 6 in the sampling waveform Vbias continues to be applied to the second pole of the first transistor T1.
  • the third control signal 13 in the waveform Vread is at a high level
  • the third transistor T3 and the fourth transistor T4 are turned on
  • the current signal waveform Iout of the read signal line 40 is at a high level.
  • FIG. 5 is a timing diagram corresponding to the signal detection circuit 100 shown in FIG. 2, and the timing diagram in FIG. 5 includes four stages:
  • At least one of the control waveform Vrst1 and the control waveform Vrst2 is at a high level
  • at least one of the corresponding sampling waveform Vbias1 and the sampling waveform Vbias2 is at a low level
  • at least one of the plurality of second transistors T2 is conductive
  • the potential of the receiving terminal rx is low
  • the transmitting terminal tx receives an AC signal
  • the piezoelectric material 11 vibrates and sends out an ultrasonic signal Vtx
  • the high-level control waveform Vrst1 or Vrst2 becomes a low level.
  • the control signal 9 in the control waveform Vrst1 is high
  • the sampling signal 7 in the sampling waveform Vbias1 is high
  • the second transistor T2 corresponding to the sampling signal 7 is turned on
  • the receiving terminal rx and the sampling signal 7 The output terminal of the sampling module 20 is charged, and the electric signal is stored in the equivalent capacitance formed by the parasitic capacitance of the receiving terminal rx of the ultrasonic sensor and the parasitic capacitance in the multiple second transistors T2, and then the control waveform Vrst1 is low, and the sampling signal
  • the second transistor T2 corresponding to 7 is turned off, and the bias signal 11 in the sampling waveform Vbias1 is applied to the second pole of the second transistor T2 corresponding to the sampling signal 7.
  • the control signal 10 is in the control waveform Vrst2 Is high, the sampling signal 8 in the sampling waveform Vbias2 is high, the second transistor T2 corresponding to the sampling signal 8 is turned on, the receiving terminal rx and the sampling signal 8 continue to charge the output terminal of the sampling module 20, and the electrical signal is superimposed and stored
  • the waveform Vrst2 is controlled to be low, the second transistor T2 corresponding to the sampling signal 8 is turned off, and the sampling waveform
  • the bias signal 12 in Vbias2 is applied to the second pole of the second transistor T2 corresponding to the sampling signal 8.
  • the control waveform Vrst1 and the control waveform Vrst2 continue to be low level, the bias signal 11 in the sampling waveform Vbias1 continues to be applied to the second pole of the second transistor T2 corresponding to the sampling signal 7, and the sampling waveform Vbias2 is biased
  • the setting signal 12 continues to be applied to the second pole of the second transistor T2 corresponding to the sampling signal 8.
  • the third control signal 13 in the waveform Vread is at a high level
  • the third transistor T3 and the fourth transistor T4 are turned on
  • the current signal waveform Iout of the read signal line 40 is at a high level.
  • the first transistor T1, the second transistor T2, and the fourth transistor T4 may be turned on when the corresponding control signal is low, and when the corresponding control signal is high Usually disconnected.
  • the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 in the embodiments of the present disclosure may be thin film transistors (TFT).
  • TFT thin film transistors
  • the signal detection circuit of the embodiment of the present disclosure includes the following advantages: the detection module detects multiple cycles of ultrasonic echo signals to generate multiple piezoelectric signals, and the sampling module receives corresponding sampling signals in each cycle, and corresponds to the cycle
  • the sampling signal and multiple piezoelectric signals are stored at the output end of the sampling module.
  • the sampling module may include a first transistor or a plurality of second transistors.
  • the second electrode of the first transistor receives the sampling signal corresponding to the period.
  • the second pole of the two transistors receives the sampling signal of the corresponding period.
  • the signals stored at the output of the sampling module are multiple piezo-electronic signals corresponding to multiple ridge signals.
  • Signal and multiple sampling signals superimposed signal or multiple piezo electronic signals corresponding to multiple trough signals and multiple sampling signals superimposed signal, multiple piezo electronic signals and multiple troughs corresponding to the multiple ridge signals
  • the signal difference between multiple piezo electronic signals corresponding to the signal is greater than the signal difference between the piezoelectric signal corresponding to a single ridge signal and the piezoelectric signal corresponding to a single valley signal in the related art, which is convenient for distinguishing multiple ridges
  • the multiple piezo electronic signals corresponding to the signal and the multiple piezo electronic signals corresponding to the multiple valley signals, even if the ridge signal and the valley signal are distinguished, are beneficial to improve the identification of the ridge signal of the product using the signal detection circuit of the embodiment of the present disclosure. And the accuracy of the trough signal.
  • an embodiment of the present disclosure also discloses a fingerprint identification device 200, which includes a base substrate 300 and a plurality of the above-mentioned signal detection circuits 100, and the plurality of signal detection circuits 100 may be provided on the base substrate 300.
  • the detection module 10 in part of the signal detection circuit 100 is configured to generate multiple piezo electronic signals corresponding to multiple cycles of ridge signals
  • the detection module 10 in the remaining signal detection circuit 100 is configured to generate multiple cycles of ridge signals.
  • the signals correspond to multiple piezo electronic signals, so that the fingerprint identification device 200 can realize the fingerprint identification function after acquiring the signals output by the multiple signal detection circuits 100.
  • the multiple signal detection circuits 100 can be arranged on the base substrate 300 in any manner, including but not limited to the arrangement shown in FIG. 6.
  • the base substrate 300 may be a glass substrate or a polyimide (PI) substrate.
  • PI polyimide
  • the fingerprint identification device 200 may further include: an indium tin oxide (ITO) layer, a flexible printed circuit board mounted on a glass panel (Flexible Printed Circuit On Glass, FOG), and the like.
  • ITO indium tin oxide
  • FOG Flexible Printed Circuit On Glass
  • the ITO layer and FOG may be arranged on the base substrate 300, the ITO layer is connected to the transmitting terminal tx of the detection module 10, the FOG is connected to the ITO layer, and an AC signal is provided to the transmitting terminal tx through the FOG and ITO layer.
  • the fingerprint identification device of the embodiment of the present disclosure includes the following advantages: the detection module in the signal detection circuit detects multiple cycles of ultrasonic echo signals to generate multiple piezoelectric signals, and the sampling module in the signal detection circuit receives the corresponding signals in each cycle.
  • the sampling signal corresponding to the period and a plurality of piezoelectric signals are stored at the output terminal of the sampling module.
  • the sampling module may include a first transistor or a plurality of second transistors, and the second pole of the first transistor receives the period Corresponding to the sampling signal, the second pole of each second transistor receives the sampling signal of the corresponding period.
  • the signals stored at the output of the sampling module are multiple piezo-electronic signals corresponding to multiple ridge signals.
  • Signal and multiple sampling signals superimposed signal or multiple piezo electronic signals corresponding to multiple trough signals and multiple sampling signals superimposed signal, multiple piezo electronic signals and multiple troughs corresponding to the multiple ridge signals
  • the signal difference between multiple piezo electronic signals corresponding to the signal is greater than the signal difference between the piezoelectric signal corresponding to a single ridge signal and the piezoelectric signal corresponding to a single valley signal in the related art, which is convenient for distinguishing multiple ridges
  • the multiple piezo electronic signals corresponding to the signal and the multiple piezo electronic signals corresponding to the multiple valley signals, even if the ridge signal and the valley signal are distinguished, are beneficial to improve the recognition wave of the fingerprint identification device using the signal detection circuit of the embodiment of the present disclosure.
  • the accuracy of the ridge signal and the trough signal are beneficial to improve the recognition wave of the fingerprint identification device using the signal detection circuit of the embodiment of the present disclosure.
  • the embodiment of the present disclosure also discloses a display device, which includes a display panel and the above-mentioned fingerprint identification device, and the fingerprint identification device can be arranged at the bottom of the display panel.
  • a display device with both display function and fingerprint recognition function can be realized.
  • the display device of the embodiment of the present disclosure includes the following advantages: the detection module in the signal detection circuit detects multiple cycles of ultrasonic echo signals to generate multiple piezoelectric signals, and the sampling module in the signal detection circuit receives corresponding signals in each cycle. Sample the signal, and store the sampling signal corresponding to the period and a plurality of piezoelectric signals at the output terminal of the sampling module, where the sampling module may include a first transistor or a plurality of second transistors, and the second electrode of the first transistor receives the period corresponding to The second pole of each second transistor receives the sampling signal of the corresponding period.
  • the signals stored at the output of the sampling module are multiple piezo-electronic signals corresponding to multiple ridge signals.
  • Signal and multiple sampling signals superimposed signal or multiple piezo electronic signals corresponding to multiple trough signals and multiple sampling signals superimposed signal, multiple piezo electronic signals and multiple troughs corresponding to the multiple ridge signals
  • the signal difference between multiple piezo electronic signals corresponding to the signal is greater than the signal difference between the piezoelectric signal corresponding to a single ridge signal and the piezoelectric signal corresponding to a single valley signal in the related art, which is convenient for distinguishing multiple ridges
  • the multiple piezo electronic signals corresponding to the signal and the multiple piezo electronic signals corresponding to the multiple valley signals can distinguish between the ridge signal and the valley signal, thereby helping to improve the recognition of the ridge of the display device using the signal detection circuit of the embodiment of the present disclosure.
  • the accuracy of the signal and the trough signal can be used to distinguish between the ridge signal and the valley signal, thereby helping to improve the recognition of the ridge of the display device using the signal detection circuit of the embodiment of the present disclosure. The accuracy of the signal and the t
  • an embodiment of the present disclosure also discloses a signal detection method according to the above-mentioned signal detection circuit, including:
  • Step 810 in the sampling phase, detect the ultrasonic echo signal, and generate multiple piezo-electronic signals according to the ultrasonic echo signal, the multiple piezo-electronic signals correspond to multiple cycles of the ultrasonic echo signal one-to-one, and the multiple piezo-electronic signals correspond to each other.
  • Multiple cycles of ridge signals, or multiple piezo electronic signals corresponding to multiple cycles of trough signals; and receiving the corresponding sampling signal in each cycle, and storing the sampling signal corresponding to the cycle and multiple piezo signals in the sampling module The output terminal.
  • the sampling module may include a first transistor.
  • the sampling signal corresponding to the cycle is received through the second electrode of the first transistor, and the first transistor is controlled to be turned on by the first control signal corresponding to the cycle.
  • the sampling module may include a plurality of second transistors, and the plurality of second transistors correspond to a plurality of periods in a one-to-one manner.
  • a sampling signal of a corresponding period is received through the second pole of each second transistor, and the period corresponds to The control signal controls the period corresponding to the second transistor to be turned on.
  • the signal detection method of the signal detection circuit of the embodiment of the present disclosure may further include:
  • Step 800 In the signal transmission stage, an ultrasonic signal is transmitted through the detection module.
  • the signal detection circuit may further include a signal readout module and a read signal line.
  • the signal detection method of the signal detection circuit of the embodiment of the present disclosure may further include:
  • Step 820 in the holding phase, store multiple sampling signals and multiple piezo electronic signals corresponding to multiple cycles through the output terminal of the sampling module.
  • step 830 in the signal reading phase, the output terminal of the sampling module and the reading signal line are turned on to output the signal stored at the output terminal of the sampling module from the reading signal line.
  • the signal detection method of the embodiment of the present disclosure includes the following advantages: the detection module detects multiple cycles of ultrasonic echo signals to generate multiple piezo electronic signals, and the sampling module receives the corresponding sampling signal in each cycle, and corresponds the cycle to The sampling signal and multiple piezoelectric signals are stored at the output terminal of the sampling module, and the output terminal of the sampling module and the reading signal line are turned on to output the signal stored at the output terminal of the sampling module from the reading signal line. Since multiple piezo-electron signals correspond to multiple-period ridge signals, or multiple piezo-electronic signals correspond to multiple-period valley signals, the signals stored at the output of the sampling module are multiple piezo-electronic signals corresponding to multiple ridge signals.
  • Signal and multiple sampling signals superimposed signal or multiple piezo electronic signals corresponding to multiple trough signals and multiple sampling signals superimposed signal, multiple piezo electronic signals and multiple troughs corresponding to the multiple ridge signals
  • the signal difference between multiple piezo electronic signals corresponding to the signal is greater than the signal difference between the piezoelectric signal corresponding to a single ridge signal and the piezoelectric signal corresponding to a single valley signal in the related art, which is convenient for distinguishing multiple ridges
  • the multiple piezo electronic signals corresponding to the signal and the multiple piezo electronic signals corresponding to the multiple valley signals, even if the ridge signal and the valley signal are distinguished, are beneficial to improve the identification of the ridge signal of the product using the signal detection circuit of the embodiment of the present disclosure. And the accuracy of the trough signal.
  • the description is relatively simple, and for the relevant parts, please refer to the part of the description of the signal detection circuit embodiment.
  • the embodiments of the embodiments of the present disclosure may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present disclosure may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present disclosure may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing terminal equipment to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction device.
  • the instruction device implements the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.
  • These computer program instructions can also be loaded on a computer or other programmable data processing terminal equipment, so that a series of operation steps are executed on the computer or other programmable terminal equipment to produce computer-implemented processing, so that the computer or other programmable terminal equipment
  • the instructions executed above provide steps for implementing functions specified in a flow or multiple flows in the flowchart and/or a block or multiple blocks in the block diagram.

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Abstract

信号检测电路、信号检测方法、指纹识别装置及显示设备，涉及显示技术领域。信号检测电路包括：检测模块，检测模块被配置为检测超声波回波信号，并根据超声波回波信号生成多个压电子信号，多个压电子信号与超声波回波信号的多个周期一一对应，多个压电子信号对应多个周期的波脊信号，或多个压电子信号对应多个周期的波谷信号；采样模块，采样模块与检测模块连接，采样模块被配置为在每个周期接收对应的采样信号，并将周期对应的采样信号和多个压电子信号存储在采样模块的输出端。

Description

信号检测电路、信号检测方法、指纹识别装置及显示设备
相关申请的交叉引用
本公开要求在2020年06月19日提交中国专利局、申请号为202010567764.4、名称为“信号检测电路、信号检测方法、指纹识别装置及显示设备”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别是涉及一种信号检测电路、一种信号检测方法、一种指纹识别装置和一种显示设备。
背景技术
目前，通常将超声波信号检测电路应用于显示设备中，以用于指纹识别。
相关技术中的超声波信号检测电路通过采样晶体管进行超声波回波信号采样，其中，采样晶体管在超声波回波信号的其中一个周期的正半周期导通一定时间或负半周期导通一定时间，采样晶体管导通期间，采样晶体管可以采样部分超声波回波信号对应的压电信号。
概述
本公开实施例的目的在于提供一种信号检测电路、一种信号检测方法、一种指纹识别装置和一种显示设备。
本公开实施例公开了一种信号检测电路，包括：
检测模块，所述检测模块被配置为检测超声波回波信号，并根据所述超声波回波信号生成多个压电子信号，所述多个压电子信号与所述超声波回波信号的多个周期一一对应，所述多个压电子信号对应所述多个周期的波脊信号，或所述多个压电子信号对应所述多个周期的波谷信号；以及
采样模块，所述采样模块与所述检测模块连接，所述采样模块被配置为在每个所述周期接收对应的采样信号，并将所述周期对应的所述采样信号和所述多个压电子信号存储在所述采样模块的输出端。
本公开实施例还公开了一种指纹识别装置，包括衬底基板和所述多个信 号检测电路，所述多个信号检测电路设置在所述衬底基板上。
本公开实施例还公开了一种显示设备，包括显示面板和所述指纹识别装置，所述指纹识别装置设置在所述显示面板的底部。
本公开实施例还公开了一种根据所述的信号检测电路的信号检测方法，包括：
在采样阶段，检测超声波回波信号，并根据所述超声波回波信号生成多个压电子信号，所述多个压电子信号与所述超声波回波信号的多个周期一一对应，所述多个压电子信号对应所述多个超声波回波信号的波脊信号，或所述多个压电子信号对应所述超声波回波信号的波谷信号；以及在每个所述周期接收对应的采样信号，并将所述周期对应的所述采样信号和所述多个压电子信号存储在所述采样模块的输出端。
本公开实施例包括以下优点：通过检测模块检测多个周期的超声波回波信号以生成多个压电子信号，以及通过采样模块在每个周期接收对应的采样信号，并将周期对应的采样信号和多个压电子信号存储在采样模块的输出端。由于多个压电子信号对应多个周期的波脊信号，或多个压电子信号对应多个周期的波谷信号，因此存储在采样模块的输出端的信号为多个波脊信号对应的多个压电子信号和多个采样信号叠加后的信号，或多个波谷信号对应的多个压电子信号和多个采样信号叠加后的信号，该多个波脊信号对应的多个压电子信号和多个波谷信号对应的多个压电子信号之间的信号差值，大于相关技术中单个波脊信号对应的压电信号和单个波谷信号对应的压电信号之间的信号差值，便于区分多个波脊信号对应的多个压电子信号和多个波谷信号对应的多个压电子信号，从而有利于提高应用本公开实施例的信号检测电路的产品识别波脊信号和波谷信号的精确度。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图简述
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作一简单地介绍，显而易见地，下 面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开的一种信号检测电路实施例的结构示意图；
图2是本公开的另一种信号检测电路实施例的结构示意图；
图3是图1中信号检测电路实施例的时序图；
图4是图1中信号检测电路实施例的等效电路图；
图5是图2中信号检测电路实施例的时序图；
图6是本公开的一种指纹识别装置实施例的结构框图；
图7是本公开的一种指纹识别装置实施例的结构示意图；并且
图8是本公开的一种信号检测方法实施例的步骤流程图。
详细描述
为使本公开的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本公开作进一步详细的说明。显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
参照图1，其示出了本公开的一种信号检测电路100实施例的结构示意图，具体可以包括如下模块：检测模块10，检测模块10被配置为检测超声波回波信号Vrx，并根据超声波回波信号Vrx生成多个压电子信号，多个压电子信号与超声波回波信号Vrx的多个周期一一对应，多个压电子信号对应多个周期的波脊信号，或多个压电子信号对应多个周期的波谷信号；采样模块20，采样模块20与检测模块10连接，采样模块20被配置为在每个周期接收对应的采样信号，并将周期对应的采样信号和多个压电子信号存储在采样模块20的输出端。
由于超声波回波信号Vrx会进行叠荡、被材料吸收(例如被显示面板各膜层吸收)而逐渐衰减为零，因此，超声波回波信号Vrx具有多个周期，存储在采样模块20的输出端的信号为多个波脊信号对应的多个压电子信号和多个采样信号叠加后的信号，或多个波谷信号对应的多个压电子信号和多个采样信号叠加后的信号，该多个波脊信号对应的多个压电子信号和多个波谷信 号对应的多个压电子信号之间的信号差值，大于相关技术中单个波脊信号对应的压电信号和单个波谷信号对应的压电信号之间的信号差值。因此，便于区分多个波脊信号对应的多个压电子信号和多个波谷信号对应的多个压电子信号，即便于区分波脊信号和波谷信号，从而有利于提高应用本公开实施例的信号检测电路100的产品识别波脊信号和波谷信号的精确度。
可选地，采样模块20可以被配置为在每个周期中正半周期的预设时间段内接收对应的采样信号，或可以被配置为在每个周期中负半周期的预设时间段内接收对应的采样信号。其中，预设时间段可以为使多个波脊信号对应的多个压电子信号和多个波谷信号对应的多个压电子信号之间的信号差值最大的时间段。可选地，在本公开的一个实施例中，若每个周期的时间长度为T，则预设时间段的时间长度范围可以为0至1/2T中的1/8T至3/8T。
可选地，如图1和图2所示，检测模块10可以包括超声波传感器，超声波传感器可以包括发射端tx、接收端rx和压电材料11等，其中，接收端rx与采样模块20的输出端连接，在采样模块20的输出端电位为低电平即接收端rx的电位为低电平时，发射端tx接收交流信号，超声波传感器中压电材料11发射超声波信号Vtx；在发射端tx接收低电平信号即发射端tx的电位为低电平时，接收端rx检测超声波回波信号Vrx，超声波传感器中压电材料11根据超声波回波信号Vrx生成压电子信号。具体地，交流信号可以为高频高压的交流信号。可选地，压电材料11可以为聚偏氟乙烯(Polyvinylidene fluoride，PVDF)膜式压电材料、氮化铝膜(Aluminium nitride film，AlN)压电材料、压电陶瓷(Piezoelectric ceramics，PZT)压电材料或氧化锌(Zinc oxide，ZnO)压电材料等，压电材料11还可以为其它的无机压电材料或有机压电材料。可选地，如图1和图2所示，压电材料11可以设置在发射端tx和接收端rx之间。
可选地，在本公开的一个实施例中，如图1所示，采样模块20可以包括：第一晶体管T1，第一晶体管T1的第一极与检测模块10连接，在每个周期，第一晶体管T1的第二极接收周期对应的采样信号，第一晶体管T1的控制极接收周期对应的第一控制信号以导通，第一晶体管T1的第一极作为采样模块20的输出端；前一个周期对应的采样信号的电平低于后一个周期对应的采样信号的电平。其中，第一晶体管T1的控制极接收周期对应的第一控制信号导 通后，周期对应的采样信号和压电子信号存储在第一晶体管T1的第一极。具体地，前一个周期对应的采样信号的电平低于后一个周期对应的采样信号的电平，可以保证在前一个周期对应的采样信号和压电子信号存储在第一晶体管T1的第一极后，后一个周期对应的采样信号和压电子信号可以继续叠加在第一晶体管T1的第一极。如图3所示，多个周期对应的采样信号可以在同一采样波形Vbias中，多个周期对应的第一控制信号可以在同一控制波形Vrst中。图3中，多个周期为两个，多个周期对应的采样信号分别为采样信号1和采样信号2，多个周期对应的第一控制信号分别为控制信号3和控制信号4。
可选地，如图3所示，在每个周期，在检测模块10生成周期对应的压电子信号后，第一晶体管T1的第二极接收周期对应的偏置信号，周期对应的偏置信号的电平低于周期对应的采样信号的电平。通过周期对应的偏置信号可以降低第一晶体管T1的第一极和第二极之间的电压差，实现减小第一晶体管T1的漏电流。如图3所示，多个周期对应的偏置信号可以设置在采样波形Vbias中。图3中，多个周期为两个，多个周期对应的偏置信号分别为偏置信号5和偏置信号6。具体地，多个周期对应的偏置信号的时间长度可以相同或至少两个不同。
可选地，图1所示的信号检测电路100对应的等效电路可以如图4所示，其中，采样模块20的输出端的寄生电容CP可以为超声波传感器的接收端rx的寄生电容和第一晶体管T1中寄生电容构成的等效电容，该等效电容存储采样模块20的输出端的信号。图4中，发射端tx接收的交流信号可以由信号检测电路100外部的交流电源AC提供，图4中电容C0为发射端tx和接收端rx之间的寄生电容。
可选地，如图4所示，信号检测电路100中采样模块20还可以包括二极管D1，二极管D1阳极与第一晶体管T1的第二极连接，二极管D1的阴极与接收端rx连接，在采样波形Vbias中采样信号为高电平时，二极管D1导通，周期对应的采样信号和压电子信号存储在采样模块20的输出端，此时，在采样信号为高电平时，第一晶体管T1无需导通，控制波形Vrst为低电平即可。
可选地，在本公开的另一个实施例中，如图2所示，采样模块20可以包括多个第二晶体管T2，多个第二晶体管T2与多个周期一一对应，多个第二晶体管T2的第一极均与检测模块10连接，每个第二晶体管T2的第二极接收 对应周期的采样信号，每个第二晶体管T2的控制极接收对应周期的第二控制信号以导通，多个第二晶体管T2的第一极作为采样模块20的输出端；前一个周期对应的采样信号的电平低于后一个周期对应的采样信号的电平。其中，第二晶体管T2的控制极接收对应周期的第二控制信号导通后，第二晶体管T2对应周期的采样信号和压电子信号存储在第二晶体管T2的第一极。多个第二晶体管T2的第一极的多个采样信号和多个压电子信号叠加存储在采样模块20的输出端。具体地，前一个周期对应的采样信号的电平低于后一个周期对应的采样信号的电平，可以保证在前一个周期对应的采样信号和压电子信号存储在前一个周期对应的第二晶体管T2的第一极后，后一个周期对应的采样信号和压电子信号可以继续叠加在采样模块20的输出端。如图5所示，多个周期为两个，多个周期对应的采样信号可以分别在多个不同的采样波形(采样波形Vbias1和采样波形Vbias2)中，多个周期对应的第二控制信号可以分别在多个不同的控制波形(控制波形Vrst1和控制波形Vrst2)中。图5中，多个周期为两个，多个周期对应的采样信号分别为采样信号7和采样信号8，多个周期对应的第二控制信号分别为控制信号9和控制信号10。可选地，多个第二晶体管T2可以为至少两个相同的晶体管或不同的晶体管
可选地，如图5所示，在每个周期，在检测模块10生成对应的压电子信号后，周期对应的第二晶体管T2的第二极接收周期对应的偏置信号；周期对应的偏置信号的电平低于周期对应的采样信号的电平。通过周期对应的偏置信号可以降低第二晶体管T2的第一极和第二极之间的电压差，实现减小第二晶体管T2的漏电流。图5中，多个周期为两个，多个周期对应的偏置信号分别为偏置信号11和偏置信号12，偏置信号11在采样波形Vbias1中，偏置信号12在采样波形Vbias2中。具体地，多个周期对应的偏置信号的时间长度可以相同或至少两个不同。
可选地，如图1、图2及图4所示，本公开实施例的信号检测电路100还可以包括信号读出模块30和读取信号线40，信号读出模块30与采样模块20的输出端和读取信号线40连接，信号读出模块30被配置为在多个压电子信号和每个周期对应的采样信号存储在采样模块20的输出端后，导通采样模块20的输出端和读取信号线40，以从读取信号线40输出采样模块20的输出端存储的信号。其中，若超声波回波信号Vrx为由手指反射超声波信号Vtx而 形成的信号，则从读取信号线40输出采样模块20的输出端存储的信号后，多个波脊信号对应的多个压电子信号可以识别为手指的脊反射超声波信号Vtx而生成的多个压电子信号，多个波谷信号对应的多个压电子信号可以识别为手指的谷反射超声波信号Vtx而生成的多个压电子信号，因此，从读取信号线40输出的信号可以作为指纹识别信号，以实现指纹识别。
可选地，如图1、图2及图4所示，信号读出模块30可以包括第三晶体管T3和第四晶体管T4，第三晶体管T3的第一极与电源连接，电源输出电压VDD，第三晶体管T3的控制极与采样模块20的输出端连接；第四晶体管T4的第一极与第三晶体管T3的第二极连接，第四晶体管T4的控制极被配置为接收第三控制信号13，第四晶体管T4的第二极与读取信号线40连接。在第四晶体管T4的控制极接收第三控制信号13后，第四晶体管T4导通，第三晶体管T3导通，在第四晶体管T4断开后，第三晶体管T3断开，即第四晶体管T4控制信号读出模块30的导通与断开。其中，第三晶体管T3导通后，第三晶体管T3将采样模块20的输出端存储的电压信号转换为电流信号，该电流信号通过第四晶体管T4输出至读取信号线40。其中，采样模块20的输出端存储的电压信号对应的电压越大，则第三晶体管T3输出的电流信号越大。即第三晶体管T3输出的电流信号跟随采样模块20的输出端存储的电压信号。可选地，如图3和图5所示，第三控制信号13所在的波形为Vread，第四晶体管T4输出至读取信号线40的电流信号波形为Iout。可选地，第三晶体管T3和第四晶体管T4可以为相同或不同的晶体管。
具体地，图3为图1所示的信号检测电路100对应的时序图，图3中的时序图包括四个阶段：
在信号发射阶段t0-t1，控制波形Vrst为高电平，采样波形Vbias为低电平，第一晶体管T1导通，接收端rx的电位为低电平，发射端tx接收交流信号，压电材料11振动并向外发射超声波信号Vtx，控制波形Vrst变为低电平。
在采样阶段t1-t2，控制波形Vrst中控制信号3为高电平，采样波形Vbias中采样信号1为高电平，第一晶体管T1导通，接收端rx和采样信号1向采样模块20的输出端充电，电信号存储在寄生电容Cp上，进而控制波形Vrst为低电平，第一晶体管T1断开，采样波形Vbias中偏置信号5施加在第一晶体管T1的第二极，此后，在采样阶段t1-t2，控制波形Vrst中控制信号4为 高电平，采样波形Vbias中采样信号2为高电平，第一晶体管T1再次导通，接收端rx和采样信号2向采样模块20的输出端继续充电，电信号叠加存储在寄生电容Cp上，此后控制波形Vrst为低电平，第一晶体管T1断开，采样波形Vbias中偏置信号6施加在第一晶体管T1的第二极。
在保持阶段t2-t3，控制波形Vrst继续为低电平，采样波形Vbias中偏置信号6继续施加在第一晶体管T1的第二极。
在信号读出阶段t3-t4，波形Vread中第三控制信号13为高电平，第三晶体管T3和第四晶体管T4导通，读取信号线40的电流信号波形Iout为高电平。
具体地，图5为图2所示的信号检测电路100对应的时序图，图5中的时序图包括四个阶段：
在信号发射阶段t10-t11，控制波形Vrst1和控制波形Vrst2中至少一个为高电平，对应的采样波形Vbias1和采样波形Vbias2中至少一个为低电平，多个第二晶体管T2中至少一个导通，接收端rx的电位为低电平，发射端tx接收交流信号，压电材料11振动并向外发射超声波信号Vtx，高电平的控制波形Vrst1或Vrst2变为低电平。
在采样阶段t11-t12，控制波形Vrst1中控制信号9为高电平，采样波形Vbias1中采样信号7为高电平，采样信号7对应的第二晶体管T2导通，接收端rx和采样信号7向采样模块20的输出端充电，电信号存储在超声波传感器的接收端rx的寄生电容和多个第二晶体管T2中寄生电容构成的等效电容上，进而控制波形Vrst1为低电平，采样信号7对应的第二晶体管T2断开，采样波形Vbias1中偏置信号11施加在采样信号7对应的第二晶体管T2的第二极，此后，在采样阶段t11-t12，控制波形Vrst2中控制信号10为高电平，采样波形Vbias2中采样信号8为高电平，采样信号8对应的第二晶体管T2导通，接收端rx和采样信号8向采样模块20的输出端继续充电，电信号叠加存储在超声波传感器的接收端rx的寄生电容和多个第二晶体管T2中寄生电容构成的等效电容上，进而控制波形Vrst2为低电平，采样信号8对应的第二晶体管T2断开，采样波形Vbias2中偏置信号12施加在采样信号8对应的第二晶体管T2的第二极。
在保持阶段t12-t13，控制波形Vrst1和控制波形Vrst2继续为低电平，采样波形Vbias1中偏置信号11继续施加在采样信号7对应的第二晶体管T2的 第二极，采样波形Vbias2中偏置信号12继续施加在采样信号8对应的第二晶体管T2的第二极。
在信号读出阶段t13-t14，波形Vread中第三控制信号13为高电平，第三晶体管T3和第四晶体管T4导通，读取信号线40的电流信号波形Iout为高电平。
可选地，在本公开的另一个实施例中，第一晶体管T1、第二晶体管T2以及第四晶体管T4可以在对应的控制信号为低电平时导通，以及在对应的控制信号为高电平时断开。
可选地，本公开实施例中第一晶体管T1、第二晶体管T2、第三晶体管T3以及第四晶体管T4可以为薄膜晶体管(Thin Film Transistor，TFT)。
本公开实施例的信号检测电路包括以下优点：通过检测模块检测多个周期的超声波回波信号以生成多个压电子信号，以及通过采样模块在每个周期接收对应的采样信号，并将周期对应的采样信号和多个压电子信号存储在采样模块的输出端，其中，采样模块可以包括第一晶体管或多个第二晶体管，第一晶体管的第二极接收周期对应的采样信号，每个第二晶体管的第二极接收对应周期的采样信号。由于多个压电子信号对应多个周期的波脊信号，或多个压电子信号对应多个周期的波谷信号，因此存储在采样模块的输出端的信号为多个波脊信号对应的多个压电子信号和多个采样信号叠加后的信号，或多个波谷信号对应的多个压电子信号和多个采样信号叠加后的信号，该多个波脊信号对应的多个压电子信号和多个波谷信号对应的多个压电子信号之间的信号差值，大于相关技术中单个波脊信号对应的压电信号和单个波谷信号对应的压电信号之间的信号差值，便于区分多个波脊信号对应的多个压电子信号和多个波谷信号对应的多个压电子信号，即便于区分波脊信号和波谷信号，从而有利于提高应用本公开实施例的信号检测电路的产品识别波脊信号和波谷信号的精确度。
如图6所示，本公开实施例还公开了一种指纹识别装置200，包括衬底基板300和多个上述的信号检测电路100，多个信号检测电路100可以设置在衬底基板300上。其中，部分信号检测电路100中检测模块10被配置为生成与多个周期的波脊信号对应的多个压电子信号，其余信号检测电路100中检测模块10被配置为生成与多个周期的波谷信号对应的多个压电子信号，从而指 纹识别装置200在获取多个信号检测电路100输出的信号后，可以实现指纹识别功能。需要说明的是，多个信号检测电路100在衬底基板300上可以以任意方式排列，包括但不限于图6所示的排列方式。
可选地，衬底基板300可以为玻璃基板或聚酰亚胺(Polyimide，PI)基板。
可选地，如图7所示，指纹识别装置200还可以包括：氧化铟锡(Indium tin oxide，ITO)层、柔性电路板搭载在玻璃面板上(Flexible Printed Circuit On Glass，FOG)等。其中，ITO层和FOG可以设置在衬底基板300上，ITO层与检测模块10的发射端tx连接，FOG与ITO层连接，通过FOG和ITO层向发射端tx提供交流信号。
本公开实施例的指纹识别装置包括以下优点：通过信号检测电路中检测模块检测多个周期的超声波回波信号以生成多个压电子信号，以及通过信号检测电路中采样模块在每个周期接收对应的采样信号，并将周期对应的采样信号和多个压电子信号存储在采样模块的输出端，其中，采样模块可以包括第一晶体管或多个第二晶体管，第一晶体管的第二极接收周期对应的采样信号，每个第二晶体管的第二极接收对应周期的采样信号。由于多个压电子信号对应多个周期的波脊信号，或多个压电子信号对应多个周期的波谷信号，因此存储在采样模块的输出端的信号为多个波脊信号对应的多个压电子信号和多个采样信号叠加后的信号，或多个波谷信号对应的多个压电子信号和多个采样信号叠加后的信号，该多个波脊信号对应的多个压电子信号和多个波谷信号对应的多个压电子信号之间的信号差值，大于相关技术中单个波脊信号对应的压电信号和单个波谷信号对应的压电信号之间的信号差值，便于区分多个波脊信号对应的多个压电子信号和多个波谷信号对应的多个压电子信号，即便于区分波脊信号和波谷信号，从而有利于提高应用本公开实施例的信号检测电路的指纹识别装置识别波脊信号和波谷信号的精确度。
本公开实施例还公开了一种显示设备，包括显示面板和上述的指纹识别装置，指纹识别装置可以设置在显示面板的底部。从而可以实现同时具有显示功能和指纹识别功能的显示设备。
本公开实施例的显示设备包括以下优点：通过信号检测电路中检测模块检测多个周期的超声波回波信号以生成多个压电子信号，以及通过信号检测 电路中采样模块在每个周期接收对应的采样信号，并将周期对应的采样信号和多个压电子信号存储在采样模块的输出端，其中，采样模块可以包括第一晶体管或多个第二晶体管，第一晶体管的第二极接收周期对应的采样信号，每个第二晶体管的第二极接收对应周期的采样信号。由于多个压电子信号对应多个周期的波脊信号，或多个压电子信号对应多个周期的波谷信号，因此存储在采样模块的输出端的信号为多个波脊信号对应的多个压电子信号和多个采样信号叠加后的信号，或多个波谷信号对应的多个压电子信号和多个采样信号叠加后的信号，该多个波脊信号对应的多个压电子信号和多个波谷信号对应的多个压电子信号之间的信号差值，大于相关技术中单个波脊信号对应的压电信号和单个波谷信号对应的压电信号之间的信号差值，便于区分多个波脊信号对应的多个压电子信号和多个波谷信号对应的多个压电子信号，即便于区分波脊信号和波谷信号，从而有利于提高应用本公开实施例的信号检测电路的显示设备识别波脊信号和波谷信号的精确度。
如图8所示，本公开实施例还公开了一种根据上述的信号检测电路的信号检测方法，包括：
步骤810，在采样阶段，检测超声波回波信号，并根据超声波回波信号生成多个压电子信号，多个压电子信号与超声波回波信号的多个周期一一对应，多个压电子信号对应多个周期的波脊信号，或多个压电子信号对应多个周期的波谷信号；以及在每个周期接收对应的采样信号，并将周期对应的采样信号和多个压电子信号存储在采样模块的输出端。
可选地，采样模块可以包括第一晶体管，步骤810在每个周期，通过第一晶体管的第二极接收周期对应的采样信号，以及通过周期对应的第一控制信号控制第一晶体管导通。
可选地，采样模块可以包括多个第二晶体管，多个第二晶体管与多个周期一一对应，步骤810通过每个第二晶体管的第二极接收对应周期的采样信号，以及通过周期对应的控制信号控制周期对应的第二晶体管导通。
可选地，如图8所示，在步骤810之前，本公开实施例的信号检测电路的信号检测方法还可以包括：
步骤800，在信号发射阶段，通过检测模块发射超声波信号。
可选地，信号检测电路还可以包括信号读出模块和读取信号线，如图8 所示，在步骤810之后，本公开实施例的信号检测电路的信号检测方法还可以包括：
步骤820，在保持阶段，通过采样模块的输出端存储多个周期对应的多个采样信号和多个压电子信号。
步骤830，在信号读出阶段，导通采样模块的输出端和读取信号线，以从读取信号线输出采样模块的输出端存储的信号。
本公开实施例的信号检测方法包括以下优点：通过检测模块检测多个周期的超声波回波信号以生成多个压电子信号，以及通过采样模块在每个周期接收对应的采样信号，并将周期对应的采样信号和多个压电子信号存储在采样模块的输出端，以及通过导通采样模块的输出端和读取信号线，以从读取信号线输出采样模块的输出端存储的信号。由于多个压电子信号对应多个周期的波脊信号，或多个压电子信号对应多个周期的波谷信号，因此存储在采样模块的输出端的信号为多个波脊信号对应的多个压电子信号和多个采样信号叠加后的信号，或多个波谷信号对应的多个压电子信号和多个采样信号叠加后的信号，该多个波脊信号对应的多个压电子信号和多个波谷信号对应的多个压电子信号之间的信号差值，大于相关技术中单个波脊信号对应的压电信号和单个波谷信号对应的压电信号之间的信号差值，便于区分多个波脊信号对应的多个压电子信号和多个波谷信号对应的多个压电子信号，即便于区分波脊信号和波谷信号，从而有利于提高应用本公开实施例的信号检测电路的产品识别波脊信号和波谷信号的精确度。
需要说明的是，对于方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本公开实施例并不受所描述的动作顺序的限制，因为依据本公开实施例，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作并不一定是本公开实施例所必须的。
对于显示面板和信号检测方法实施例而言，由于其基于上述的信号检测电路，所以描述的比较简单，相关之处参见信号检测电路实施例的部分说明即可。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见 即可。
本领域内的技术人员应明白，本公开实施例的实施例可提供为方法、装置、或计算机程序产品。因此，本公开实施例可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本公开实施例可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本公开实施例是参照根据本公开实施例的方法、终端设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理终端设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理终端设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理终端设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理终端设备上，使得在计算机或其他可编程终端设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程终端设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本公开实施例的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例做出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开实施例范围的所有变更和修改。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求 或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者终端设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者终端设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者终端设备中还存在另外的相同要素。
以上对本公开所提供的一种信号检测电路、一种信号检测方法、一种指纹识别装置和一种显示设备，进行了详细介绍，本文中应用了具体个例对本公开的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本公开的方法及其核心思想；同时，对于本领域的一般技术人员，依据本公开的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本公开的限制。

Claims (23)

  1. 一种信号检测电路，其中，所述信号检测电路包括：
    检测模块，所述检测模块被配置为检测超声波回波信号，并根据所述超声波回波信号生成多个压电子信号，所述多个压电子信号与所述超声波回波信号的多个周期一一对应，所述多个压电子信号对应所述多个周期的波脊信号，或所述多个压电子信号对应所述多个周期的波谷信号；以及
    采样模块，所述采样模块与所述检测模块连接，所述采样模块被配置为在每个所述周期接收对应的采样信号，并将所述周期对应的所述采样信号和所述多个压电子信号存储在所述采样模块的输出端。
  2. 根据权利要求1所述的电路，其中，所述采样模块包括：
    第一晶体管，所述第一晶体管的第一极与所述检测模块连接，在每个所述周期，所述第一晶体管的第二极接收所述周期对应的所述采样信号，所述第一晶体管的控制极接收所述周期对应的第一控制信号以导通，所述第一晶体管的第一极作为所述采样模块的所述输出端；
    其中，前一个所述周期对应的所述采样信号的电平低于后一个所述周期对应的所述采样信号的电平。
  3. 根据权利要求2所述的电路，其中，在每个所述周期，在所述检测模块生成所述周期对应的压电子信号后，所述第一晶体管的第二极接收周期对应的偏置信号，所述周期对应的偏置信号的电平低于所述周期对应的所述采样信号的电平。
  4. 根据权利要求2所述的电路，其中，所述检测模块包括超声波传感器；
    所述超声波传感器包括发射端、接收端和压电材料，所述接收端与所述采样模块的所述输出端连接。
  5. 根据权利要求4所述的电路，其中，所述采样模块的所述输出端的寄生电容为所述接收端的寄生电容和所述第一晶体管中的寄生电容构成的等效电容，所述等效电容存储所述采样模块的所述输出端的信号。
  6. 根据权利要求4所述的电路，其中，所述采样模块还包括二极管；
    所述二极管的阳极与所述第一晶体管的所述第二极连接，所述二极管的的阴极与所述接收端连接。
  7. 根据权利要求4所述的电路，其中，在所述采样模块的输出端电位为 低电平，所述接收端的电位为低电平的情况下，所述发射端接收交流信号，所述压电材料发射超声波信号；
    在所述发射端接收低电平信号的情况下，所述接收端检测所述超声波回波信号，所述压电材料根据所述超声波回波信号生成所述压电子信号。
  8. 根据权利要求4所述的电路，其中，所述压电材料为聚偏氟乙烯膜式压电材料、氮化铝压电材料、压电陶瓷或氧化锌压电材料。
  9. 根据权利要求4所述的电路，其中，所述压电材料设置在所述发射端和所述接收端之间。
  10. 根据权利要求1所述的电路，其中，所述采样模块包括多个第二晶体管，所述多个第二晶体管与所述多个周期一一对应，所述多个第二晶体管的第一极均与所述检测模块连接，每个所述第二晶体管的第二极接收对应周期的所述采样信号，每个所述第二晶体管的控制极接收对应周期的第二控制信号以导通，所述多个第二晶体管的第一极作为所述采样模块的输出端；
    其中，前一个周期对应的所述采样信号的电平低于后一个所述周期对应的所述采样信号的电平。
  11. 根据权利要求10所述的电路，其中，在每个所述周期，在所述检测模块生成对应的压电子信号后，所述周期对应的所述第二晶体管的第二极接收周期对应的偏置信号；
    其中，所述周期对应的偏置信号的电平低于所述周期对应的所述采样信号的电平。
  12. 根据权利要求1所述的电路，其中，所述信号检测电路还包括信号读出模块和读取信号线；
    所述信号读出模块与所述采样模块的输出端和所述读取信号线连接，所述信号读出模块被配置为在所述多个所述压电子信号和每个所述周期对应的所述采样信号存储在所述采样模块的输出端后，导通所述采样模块的输出端和所述读取信号线，以从所述读取信号线输出所述采样模块的输出端存储的信号。
  13. 根据权利要求12所述的电路，其中，所述信号读出模块包括第三晶体管和第四晶体管；
    所述第三晶体管的第一极与电源连接，所述第三晶体管的控制极与所述 采样模块的所述输出端连接；
    所述第四晶体管的第一极与所述第三晶体管的第二极连接，所述第四晶体管的控制极被配置为接收第三控制信号，所述第四晶体管的第二极与所述读取信号线连接。
  14. 根据权利要求1所述的电路，其中，所述采样模块被配置为在每个所述周期中正半周期的预设时间段内接收对应的所述采样信号，或者被配置为在每个所述周期中负半周期的预设时间段内接收对应的所述采样信号；
    其中，所述预设时间段为所述多个波瘠信号对应的所述多个压电子信号和所述多个波谷信号对应的所述多个压电自信和之间的信号差值最大的时间段。
  15. 根据权利要求14所述的电路，其中，在每个所述周期的时间长度为T的情况下，所述预设时间段的时间长度范围为1/8T至3/8T。
  16. 一种指纹识别装置，其中，包括衬底基板和多个权利要求1-15中任一项所述的信号检测电路，所述多个信号检测电路设置在所述衬底基板上。
  17. 根据权利要求16所述的指纹识别装置，其中，一部分所述信号检测电路中的所述检测模块被配置为生成与所述多个周期的波瘠信号对应的所述压电子信号，另一部分所述信号检测电路中的所述检测模块被配置为生成与所述多个周期的波谷信号对应的所述多个压电子信号。
  18. 一种显示设备，其中，包括显示面板和权利要求16或17所述的指纹识别装置，所述指纹识别装置设置在所述显示面板的底部。
  19. 一种根据权利要求1-15中任一项所述的信号检测电路的信号检测方法，其中，包括：
    在采样阶段，检测超声波回波信号，并根据所述超声波回波信号生成多个压电子信号，所述多个压电子信号与所述超声波回波信号的多个周期一一对应，所述多个压电子信号对应所述多个周期的波脊信号，或所述多个压电子信号对应所述多个周期的波谷信号；以及在每个所述周期接收对应的采样信号，并将所述周期对应的所述采样信号和所述多个压电子信号存储在所述采样模块的输出端。
  20. 根据权利要求19所述的方法，其中，所述采样模块包括第一晶体管，在每个所述周期，通过所述第一晶体管的第二极接收所述周期对应的所述采 样信号，以及通过周期对应的第一控制信号控制所述第一晶体管导通。
  21. 根据权利要求19所述的方法，其中，所述采样模块包括多个第二晶体管，所述多个第二晶体管与所述多个周期一一对应，通过每个所述第二晶体管的第二极接收对应周期的所述采样信号，以及通过周期对应的控制信号控制所述周期对应的所述第二晶体管导通。
  22. 根据权利要求19所述的方法，其中，所述方法还包括：
    在信号发射阶段，通过所述检测模块发射超声波信号。
  23. 根据权利要求19所述的方法，其中，所述信号检测电路还包括信号读出模块和读取信号线，所述方法还包括：
    在保持阶段，通过所述采样模块的所述输出端存储所述多个周期对应的多个采样信号和所述多个压电子信号；以及
    在信号读出阶段，导通所述采样模块的所述输出端存储的所述多个周期对应的所述多个采样信号和所述多个压电子信号。
PCT/CN2021/101053 2020-06-19 2021-06-18 信号检测电路、信号检测方法、指纹识别装置及显示设备 WO2021254503A1 (zh)

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