WO2021249046A1 - 数据访问方法、控制器、存储器和存储介质 - Google Patents

数据访问方法、控制器、存储器和存储介质 Download PDF

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Publication number
WO2021249046A1
WO2021249046A1 PCT/CN2021/089674 CN2021089674W WO2021249046A1 WO 2021249046 A1 WO2021249046 A1 WO 2021249046A1 CN 2021089674 W CN2021089674 W CN 2021089674W WO 2021249046 A1 WO2021249046 A1 WO 2021249046A1
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address
node
node address
mapping
access
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PCT/CN2021/089674
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English (en)
French (fr)
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吴边
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中兴通讯股份有限公司
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Publication of WO2021249046A1 publication Critical patent/WO2021249046A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store

Definitions

  • This application relates to the field of storage technology, in particular to a data access method, a controller, a memory, and a storage medium.
  • FIG 1 is a schematic diagram of the structure of a dynamic random access memory (Dynamic Random Access Memory, DRAM) controller.
  • the DRAM controller includes two parts of the interface: the application side interface and the DRAM chip interface.
  • the application side passes through the application
  • the end interface is connected to the DRAM controller.
  • the DRAM controller uses the DRAM as a storage space with continuous addresses through the DRAM chip interface, and the DRAM chip meets the required access timing of the DRAM for access.
  • the controller will perform a read and write test on the DRAM chip. If the test fails in part of the address during the read and write, and the reason is that part of the storage area in the DRAM chip is damaged, at this time, if the controller and DRAM chips are independent of each other, so the DRAM chip needs to be replaced. If the controller and the DRAM chip are sealed together, such as an HBM chip, then the entire packaged chip needs to be replaced.
  • the data access method, controller, memory, and storage medium provided in this application can improve the effect of dynamic memory utilization and save product cost.
  • an embodiment of the present application provides a data access method, including:
  • mapping node address determines the mapping node address based on the mapping relationship between the error node address and the mapping node address
  • Read and write access to data based on the access request and the address of the mapping node.
  • an embodiment of the present application provides a controller, including: a record access unit, wherein:
  • the record access unit is configured to receive an access request sent by an application, wherein the access request carries an access address; if any address included in the access address is an error node address, based on the error node address and mapping The node address mapping relationship determines the mapped node address; read and write access to data is performed based on the access request and the mapped node address.
  • an embodiment of the present application provides a memory, including the controller according to any one of the embodiments of the present application.
  • an embodiment of the present application provides a storage medium that stores a computer program that, when executed by a processor, implements the method described in any one of the embodiments of the present application.
  • Figure 1 is a schematic diagram of the structure of a DRAM controller
  • FIG. 2 is a flowchart of a data access method provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a recording method of a mapping relationship provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of testing and recording a mapping relationship provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a controller provided by an embodiment of the present application.
  • FIG. 2 is a flowchart of a memory access method provided in an embodiment of the present application.
  • the memory access method is executed by the controller of the memory.
  • the memory access method provided by the embodiment of the present application mainly includes steps S11, S12, and S13.
  • mapping node address determines the mapping node address based on the mapping relationship between the error node address and the mapping node address.
  • the node address can be understood as the serial number of the storage space for each segment of continuous transmission.
  • the wrong node address can be understood as an address that causes the test to fail when the memory is damaged and cannot be used during the read and write test.
  • the mapped node address can be understood as the address where the memory address can be used normally and the test is successful when the memory is read and written.
  • the access address after the access address is determined, it is determined whether the access address exists in the mapping table that records the mapping relationship between the wrong node address and the mapped node address. If it exists in the above mapping table, it is determined that the access address is the wrong node address. . If it does not exist in the above mapping table, it is determined that the access address is the correct node address, and the original address can be used directly to access the DRAM.
  • the method before the receiving the access request sent by the application terminal, the method further includes: establishing a mapping relationship between the error node address and the mapping node address.
  • mapping relationship between the error node address and the mapped node address can be stored in any storage manner.
  • the above-mentioned mapping relationship is recorded in the form of a mapping relationship table, as shown in Figure 3 for details, "valid flag” indicates whether this record is valid, "error node address” indicates the address of the node that failed the test, and "mapping node “Address” indicates the address of the node used to replace it with a successful test.
  • the determining the mapping relationship between the address of the wrong node and the address of the mapped node includes: performing a read and write test on the storage space in units of nodes; and determining the address of the node that fails the test as the address of the wrong node ; Select any node from the successfully tested node addresses as the mapped node address; establish a mapping relationship between the wrong node address and the mapped node address.
  • a read and write test is performed on the storage space in units of nodes, and the addresses of the nodes that fail the test and the addresses of the nodes that are successful are recorded in turn.
  • the node address that fails the test is determined as the wrong node address, and the node address that succeeds in the test is determined as the correct node address.
  • Count the number of incorrect node addresses and select a specified number of correct node addresses from the correct node addresses as the mapped node addresses of the incorrect node addresses. Among them, the specified number is the number of error node addresses.
  • mapping node mapping address when selecting the mapping node mapping address from the correct node address, it can be selected sequentially from the end of the storage space. For example, there are a total of 16 node storage spaces in DRAM, where addresses 3, 8, and 12 fail the test. Addresses 15, 14, and 13 can be selected as the mapping addresses corresponding to addresses 3, 8, and 12, respectively.
  • the storage space of the memory needs to be divided in units of nodes.
  • the size of a node is determined according to user access characteristics and DRAM characteristics, such as 32B, 64B, 512B, 1024B, etc. .
  • the method before performing a read and write test on the storage space of the dynamic memory in units of nodes, the method further includes: setting a preset number of recording bits; wherein, the recording bits are used to record the address of the error node and the The mapping relationship of the mapping node address is described.
  • a valid identifier is also recorded in the record bit, wherein the valid identifier is used to indicate whether this record is valid.
  • each recording bit includes a valid identifier.
  • the valid identifier When the valid identifier is in the first state, it indicates that this record is valid, and when the valid identifier is in the second state, it indicates that this record is invalid.
  • the first state and the second state can be designed according to actual conditions. For example, the first state can be "1" and the second state can be "0". That is, when the valid identifier is 1, it indicates that this record is valid, and when the valid identifier is 0, it indicates that this record is invalid.
  • the establishing the mapping relationship between the error node address and the mapping node address includes: in the case that the number of the error node address is less than the number of the record bits, setting the corresponding bits in each record The mapping relationship between the error node address and the mapped node address is recorded in sequence.
  • the number of recording bits is determined by the application side.
  • the number of recording bits is determined by the application side. It can be understood that the number of recording bits is determined by the degree of storage loss that the application side can bear.
  • the extent of the tolerable storage loss can be understood as the proportion of the application-side allowable error byte address. For example, there are 16 node storage spaces in DRAM, and the tolerable storage loss is 25%, then the identification application can allow 4 wrong node addresses, that is, the number of recorded bits is 4.
  • the number of error node addresses is greater than the number of recorded bits, it means that the proportion of error node addresses in the entire storage space has exceeded the extent of storage loss that the application can withstand, that is, there are too many error node addresses, and the application The terminal can no longer read data effectively. In this way, a large number of wrong node addresses in the storage space can be avoided, causing access errors.
  • the method further includes: sending the number of the error node addresses to the application side.
  • the number of the wrong node addresses is sent to the application end, and the application end uses the actual test node capacity as the effective space, and considers the effective space to be a continuous space starting from the DRAM start address.
  • a method for determining the mapping relationship between an error node address and the mapped node address and accessing a memory is provided. It should be noted that, in this embodiment, a DRAM is taken as an example for description.
  • the dynamic memory controller divides the entire DRAM storage space with node granularity.
  • the node size is determined according to user access characteristics and DRAM characteristics, such as 32B, 64B, 512B, 1024B, etc.
  • the dynamic memory controller sets a corresponding number of record corresponding bits according to the degree of storage capacity loss that the application can withstand.
  • the number of recording bits is determined by the application side. It can be understood that the number of recording bits is determined by the degree of storage loss that the application side can bear.
  • the extent of the tolerable storage loss can be understood as the proportion of the application-side allowable error byte address. For example, there are 16 node storage spaces in DRAM, and the tolerable storage loss is 25%, then the identification application can allow 4 wrong node addresses, that is, the number of recorded bits is 4.
  • the dynamic memory controller performs a read and write test on the entire DRAM storage space in units of nodes, and records the address of the node that fails the test.
  • the mapping relationship between the failed node address and the tail test succeeded node address in each record position in turn if the number of failed nodes is less than the storage capacity loss that the application can withstand, record the mapping relationship between the failed node address and the tail test succeeded node address in each record position in turn .
  • the fifth step is to inform the application side of the number of nodes that have failed the test.
  • the application side uses the actual test node capacity as the effective space, and considers the effective space to be a continuous space starting from the DRAM start address.
  • the seventh step after receiving the access request from the application side, the dynamic memory controller judges whether the access address is recorded in the record bit. If there is a record, the corresponding node address is used instead of accessing the DRAM, otherwise the original application side is used. The address of DRAM is accessed.
  • the memory access method provided in this embodiment achieves the effect of improving the utilization rate of the dynamic memory, saving product cost, and improving product availability.
  • FIG. 3 is a schematic diagram of a method for recording the mapping relationship provided by an embodiment of the present application, as shown in FIG. 3. As shown, the "valid flag” indicates whether this record is valid, the "error node address” indicates the node address that failed the test, and the "mapped node address” indicates the successful test node address used to replace it.
  • an application example of a memory access method is provided.
  • the specific processing steps are as follows:
  • the DRAM test result is notified to the application side, and the application side accesses the DRAM with 13 nodes in the largest space.
  • the embodiment of the present application further provides a controller.
  • the controller includes a recording access unit, wherein:
  • the record access unit is configured as the record access unit and is configured to receive an access request sent by an application, wherein the access request carries an access address; if any address contained in the access address is wrong
  • the node address determines the mapped node address based on the mapping relationship between the wrong node address and the mapped node address; and accesses data based on the access request and the mapped node address.
  • the controller further includes: a test unit, wherein:
  • the test unit 5 is configured to perform read and write tests on the storage space of the memory in units of nodes, and transmit the address of the node that fails the test to the record access unit;
  • the record access unit is configured to determine the node address that fails the test as the erroneous node address, determine the node address that succeeds in the test at the end of the storage space as the mapping node address, and establish the erroneous node address and the mapping The mapping relationship of node addresses.
  • the test unit also transmits the address of the node that has been successfully tested to the record access unit.
  • the test unit transmits the result of the read and write test to the corresponding bit of the record access unit record, and records the mapping relationship between the node address of the record read and write test failed in the record access unit and the node address used to replace it.
  • the access is recorded
  • the unit judges whether to map and how to map according to the access address, and then accesses the DRAM chip with the final address.
  • the controller provided in this embodiment can execute the memory access method provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing the method.
  • the memory access method provided by any embodiment of the present invention please refer to the memory access method provided by any embodiment of the present invention.
  • the embodiment of the present application further provides a memory, which includes any one of the controllers provided in the above-mentioned embodiments, and can execute the memory access method provided by any embodiment of the present invention, and is capable of executing The corresponding functional modules and beneficial effects of this method.
  • a memory which includes any one of the controllers provided in the above-mentioned embodiments, and can execute the memory access method provided by any embodiment of the present invention, and is capable of executing The corresponding functional modules and beneficial effects of this method.
  • a memory which includes any one of the controllers provided in the above-mentioned embodiments, and can execute the memory access method provided by any embodiment of the present invention, and is capable of executing The corresponding functional modules and beneficial effects of this method.
  • an embodiment of the present application further provides a storage medium containing computer-executable instructions, the computer-executable instructions being used to execute a data access method when executed by a computer processor, including;
  • mapping node address determines the mapping node address based on the mapping relationship between the error node address and the mapping node address
  • the data is accessed based on the access request and the address of the mapping node.
  • a storage medium containing computer-executable instructions provided by an embodiment of the present application is not limited to the method operations described above, and can also execute any of the data access methods provided in any embodiment of the present application. Related operations.
  • user terminal encompasses any suitable type of wireless user equipment, such as a mobile phone, a portable data processing device, a portable web browser, or a vehicle-mounted mobile station.
  • the various embodiments of the present application can be implemented in hardware or dedicated circuits, software, logic or any combination thereof.
  • some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that may be executed by a controller, microprocessor, or other computing device, although the application is not limited thereto.
  • Computer program instructions can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code written in any combination of one or more programming languages or Object code.
  • ISA instruction set architecture
  • the block diagram of any logic flow in the drawings of the present application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions.
  • the computer program can be stored on the memory.
  • the memory can be of any type suitable for the local technical environment and can be implemented using any suitable data storage technology, such as but not limited to read-only memory (ROM), random access memory (RAM), optical storage devices and systems (digital multi-function discs) DVD or CD disc) etc.
  • Computer-readable media may include non-transitory storage media.
  • the data processor can be any type suitable for the local technical environment, such as but not limited to general-purpose computers, special-purpose computers, microprocessors, digital signal processors (DSP), application-specific integrated circuits (ASIC), programmable logic devices (FGPA) And processors based on multi-core processor architecture.
  • DSP digital signal processors
  • ASIC application-specific integrated circuits
  • FGPA programmable logic devices
  • mapping node address is determined based on the mapping relationship between the error node address and the mapping node address; Read and write access to data based on the access request and the address of the mapping node.

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Abstract

一种数据访问方法、控制器、存储器和存储介质，包括：接收应用端发送的访问请求，其中，所述访问请求中携带访问地址(S11)；若所述访问地址中包含的任一地址是错误节点地址，基于错误节点地址与映射节点地址的映射关系确定映射节点地址(S12)；基于所述访问请求和所述映射节点地址对数据进行读写访问(S13)。

Description

数据访问方法、控制器、存储器和存储介质
相关申请的交叉引用
本申请基于申请号为202010525472.4、申请日为2020年6月10日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及存储技术领域，具体涉及一种数据访问方法、控制器、存储器和存储介质。
背景技术
图1是一种动态随机存取存储器(Dynamic Random Access Memory，DRAM)控制器的结构示意图，如图1所示，DRAM控制器包括两部分接口：应用端接口和DRAM芯片接口，应用端通过应用端接口连接DRAM控制器，DRAM控制器通过DRAM芯片接口将DRAM作为地址连续的存储空间进行使用，DRAM芯片满足DRAM所需访问时序进行访问。
在实际应用中，由于DRAM本身的原因，DRAM中可能有部分存储被损坏而无法使用，如果不加识别的访问到这些损坏区域，那么就会造成访问数据出错，从而影响应用端。
一般应用中，芯片上电后，控制器会对DRAM芯片做读写测试，如果读写中部分地址出现测试失败情况，并且原因为DRAM芯片中部分存储区域被损坏的话，此时如果控制器和DRAM芯片是相互独立的，那么需要替换DRAM芯片，如果控制器和DRAM芯片合封在一起，比如HBM芯片，那么就需要替换整个合封芯片。
发明内容
本申请提供的数据访问方法、控制器、存储器和存储介质，以提高动态存储器利用率的效果，节省了产品成本。
第一方面，本申请实施例提供一种数据访问方法，包括:
接收应用端发送的访问请求，其中，所述访问请求中携带访问地址；
若所述访问地址中包含的任一地址是错误节点地址，基于错误节点地址与映射节点地址的映射关系确定映射节点地址；
基于所述访问请求和所述映射节点地址对数据进行读写访问。
第二方面，本申请实施例提供一种控制器，包括：记录访问单元，其中，
所述记录访问单元，被配置为接收应用端发送的访问请求，其中，所述访问请求中携带访问地址；若所述访问地址中包含的任一地址是错误节点地址，基于错误节点地址与映射节点地址的映射关系确定映射节点地址；基于所述访问请求和所述映射节点地址对数据进行读写访问。
第三方面，本申请实施例提供一种存储器，包括如本申请实施例提供的任一项所述的控制器。
第四方面，本申请实施例提供一种存储介质，所述存储介质存储有计算机程序，所述计算机程序被处理器执行时实现他、如本申请实施例提供的任一项所述的方法。
关于本申请的以上实施例和其他方面以及其实现方式，在附图说明、具体实施方式和权利要求中提供更多说明。
附图说明
图1是一种DRAM控制器的结构示意图；
图2是本申请实施例提供的一种数据访问方法的流程图；
图3是本申请实施例提供的一种映射关系的记录方式的示意图；
图4是本申请实施例提供的一种测试并记录映射关系的示意图；
图5是本申请实施例提供的一种控制器的结构示意图；
具体实施方式
为使本申请的目的、技术方案和优点更加清楚明白，下文中将结合附图对本申请的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
在附图的流程图示出的步骤可以在诸如一组计算机可执行指令的计算机系统中执行。并且，虽然在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤。
在一个实施例中，提供一种存储器访问方法，图2是本申请实施例提供的一种存储器访问方法的流程图。所述存储器访问方法由存储器的控制器来执行。
如图2所示，本申请实施例提供的存储器访问方法主要包括步骤S11、S12、S13。
S11、接收应用端发送的访问请求，其中，所述访问请求中携带访问地址。
S12、若所述访问地址中包含的任一地址是错误节点地址，基于错误节点地址与映射节点地址的映射关系确定映射节点地址。
S13、基于所述访问请求和所述映射节点地址对数据进行访问。
在本实施例中，节点地址可以理解为每一段连续传输的存储空间的编号。
在本实施例中，错误节点地址可以理解为存储器进行读写测试时，存储损坏不能使用，导致测试失败的地址。映射节点地址可以理解为存储器进行读写测试时，存储地址能正常使用，测试成功的地址。
在实施例中，确定访问地址之后，判断访问地址是不是在记录错误节点地址与映射节点地址的映射关系的映射表中存在，如果在上述映射表中存在，则 确定访问地址是错误的节点地址。如果在上述映射表中不存在，则确定该访问地址是正确节点地址，可以直接使用原始地址对DRAM进行访问。
在一个示例性的实施方式中，所述接收应用端发送的访问请求之前，还包括：建立错误节点地址与映射节点地址的映射关系。
需要说明的是，确定错误节点地址与映射节点地址的映射关系可以采用任意的存储方式进行存储。本实施例中，上述从映射关系采用映射关系表的方式进行记录，具体参见图3所示，“有效标志”表示本条记录是否有效，“错误节点地址”表示测试失败的节点地址，“映射节点地址”表示用来替换其的测试成功的节点地址。
在一个示例性的实施方式中，所述确定错误节点地址与映射节点地址的映射关系，包括：以节点为单位对存储空间进行读写测试；将测试失败的节点地址确定为所述错误节点地址；从测试成功的节点地址中选择任一节点作为所述映射节点地址；建立所述错误节点地址与所述映射节点地址的映射关系。
在本实例中，以节点为单位对存储空间进行读写测试，并依次记录测试失败的节点地址和测试成功的节点地址。将测试失败的节点地址确定为错误节点地址，将测试成功的节点地址确定为正确节点地址。统计错误节点地址的数量，从正确节点地址选取指定数量的正确节点地址作为错误节点地址的映射节点地址。其中，指定数量是错误节点地址的数量。
进一步的，错误节点地址与映射节点地址是一一对应的关系。
进一步的，从正确节点地址选取映射节点映射地址时，可以从存储空间尾部开始依次选取。例如，在DRAM一共有16个节点存储空间，其中，地址3，8,12测试失败，可以选择地址15，14，13分别作为地址3，8,12对应的映射地址。
在本实施例中，需要以节点为单位对存储器的存储空间进行划分。其中，一个节点大小根据用户访问特性和DRAM的特性而定，比如32B、64B、512B、1024B等。。
在一个示例性的实施方式中，以节点为单位对动态存储器的存储空间进行读写测试之前，还包括：设置预设数量的记录位；其中，所述记录位用于记录错误节点地址与所述映射节点地址的映射关系。
在一个示例性的实施方式中，所述记录位中还记录有效标识，其中，所述有效标识用于指示此条记录是否有效。
在本实施例中，每个记录位均包括一个有效标识。所述有效标识是第一状态时，指示此条记录有效，所述有效标识是第二状态时，指示此条记录无效。第一状态和第二状态可以根据实际情况进行设计，例如：可以第一状态可以是“1”，第二状态可以是“0”。即有效标识是1时，指示此条记录有效，所述有效标识是0时，指示此条记录无效。
在一个示例性的实施方式中，所述建立错误节点地址与所述映射节点地址的映射关系，包括：在所述错误节点地址的数量小于所述记录位的数量情况下，在各个记录对应位中依次记录错误节点地址与所述映射节点地址的映射关系。
在一个示例性的实施方式中，所述记录位的数量由应用端确定。
在本实施例中，记录位的数量由应用端确定来确定可以理解为记录位的数量由应用端可承受的存储量损失程度确定。可承受的存储量损失程度可以理解为应用端允许错误字节地址的占比。例如：在DRAM一共有16个节点存储空间，可承受的存储量损失程度是25％，则标识应用端可允许存在4个错误节点地址，即记录位的数量为4。
进一步的，在错误节点地址的数量大于记录位的数量的情况下，表示整个 存储空间内错误节点地址的占比已经超过应用端可承受的存储量损失程度，即错误节点错误地址太多，应用端已经不能有效读取数据。这样，可以避免存储空间内存在大量的错误节点地址，导致访问出现错误。
在一个示例性的实施方式中，所述建立错误节点地址与所述映射节点地址的映射关系之后，还包括：将所述错误节点地址的数量发送至应用端。
本实施例中，将所述错误节点地址的数量发送至应用端，应用端以实际测试成功的节点容量作为有效空间进行使用，并且认为有效空间是从DRAM起始地址开始的连续空间。
在一个示例性的实施方式中，提供一种确定错误节点地址与所述映射节点地址的映射关系以及访问存储器的方法。需要说明的是，本实施例中，以DRAM为例进行说明。
第一步，动态存储器控制器以节点粒度对整个DRAM存储空间进行划分。
其中，节点大小根据用户访问特性和DRAM的特性而定，比如32B、64B、512B、1024B等。
第二步，动态存储器控制器以应用端可以承受的存储容量损失程度设置相应数目的记录对应位。
在本实施例中，记录位的数量由应用端确定来确定可以理解为记录位的数量由应用端可承受的存储量损失程度确定。可承受的存储量损失程度可以理解为应用端允许错误字节地址的占比。例如：在DRAM一共有16个节点存储空间，可承受的存储量损失程度是25％，则标识应用端可允许存在4个错误节点地址，即记录位的数量为4。
第三步，动态存储器控制器以节点为单位对整个DRAM存储空间进行读写测试，并记录测试失败的节点地址。
第四步，如果测试失败的节点数目少于应用端可以承受的存储容量损失程度，则在各个记录位中依次记录测试失败的节点地址和用来替代其的尾部测试成功的节点地址的映射关系。
第五步，将测试失败的节点数目告知应用端。
第六步，应用端以实际测试成功的节点容量作为有效空间进行使用，并且认为有效空间是从DRAM起始地址开始的连续空间。
第七步，动态存储器控制器收到应用端的访问请求后，判断访问地址是否在记录位中有记录，如果有记录，则使用其对应的节点地址来代替对DRAM进行访问，否则使用应用端原始的地址对DRAM进行访问。
本实施例提供的存储器访问方法，达到了提高动态存储器利用率的效果，节省了产品成本，提高了产品可用度。
在一个示例性的实施方式中，提供一种错误节点地址与所述映射节点地址的映射关系的记录方式，图3是本申请实施例提供的一种映射关系的记录方式的示意图，如图3所示，“有效标志”表示本条记录是否有效，“错误节点地址”表示测试失败的节点地址，“映射节点地址”表示用来替换其的测试成功的节点地址。
在一个应用性实例中，提供一种存储器访问方法的应用实例，具体处理步骤如下：
1.假设DRAM一共有16个节点存储空间，应用端最多可以接受有4个节点不可用。
2.DRAM测试结果发现节点地址3,7,13失败，则生成如图4所示的映射关系表，表示使用节点15、节点14、节点12来替代错误的节点3、节点7、节点13。
3.DRAM测试结果通知给应用端，应用端以最大空间位13个节点来访问DRAM。
4.应用端在访问到节点地址3、7、13时，动态存储器控制器会分别以节点地址15、14、12来替代。
在一个实施例中，本申请实施例还提供一种控制器。
如图5所示，所述控制器包括记录访问单元，其中，
所述记录访问单元，被配置为所述记录访问单元，被配置为接收应用端发送的访问请求，其中，所述访问请求中携带访问地址；若所述访问地址中包含的任一地址是错误节点地址，基于错误节点地址与映射节点地址的映射关系确定映射节点地址；基于所述访问请求和所述映射节点地址对数据进行访问。
在一个实施方式中，所述控制器还包括：测试单元，其中，
测试单元5，被配置为以节点为单位对对存储器的存储空间进行读写测试，并将测试失败的节点地址传输至记录访问单元；
记录访问单元，被配置为将测试失败的节点地址确定为所述错误节点地址，将所述存储空间尾部测试成功的节点地址确定为所述映射节点地址，建立所述错误节点地址与所述映射节点地址的映射关系。
在上述实施例的基础上，测试单元还将测试成功的节点地址传输至记录访问单元。
测试单元将读写测试结果传递给记录访问单元记录对应位，记录访问单元中记录读写测试失败的节点地址和用来替换其的节点地址的映射关系，应用端发起读写访问时，记录访问单元根据访问地址判断是否做映射及如何映射，然后以最终地址来访问DRAM芯片。
本实施例中提供的控制器可执行本发明任意实施例所提供的存储器访问 方法，具备执行该方法相应的功能模块和有益效果。未在本实施例中详尽描述的技术细节，可参见本发明任意实施例所提供的存储器访问方法。
值得注意的是，上述控制器的实施例中，所包括的各个单元和模块只是按照功能逻辑进行划分的，但并不局限于上述的划分，只要能够实现相应的功能即可；另外，各功能单元的具体名称也只是为了便于相互区分，并不用于限制本申请的保护范围。
在一个实施例中，本申请实施例还提供一种存储器，所述存储器包括上述实施例中提供的任一项控制器，并能可执行本发明任意实施例所提供的存储器访问方法，具备执行该方法相应的功能模块和有益效果。未在本实施例中详尽描述的技术细节，可参见本发明任意实施例所提供的存储器访问方法。
在一个示例性的实施方式中，本申请实施例还提供一种包含计算机可执行指令的存储介质，所述计算机可执行指令在由计算机处理器执行时用于执行一种数据访问方法，包括；
接收应用端发送的访问请求，其中，所述访问请求中携带访问地址；
若所述访问地址中包含的任一地址是错误节点地址，基于错误节点地址与映射节点地址的映射关系确定映射节点地址；
基于所述访问请求和所述映射节点地址对数据进行访问。
当然，本申请实施例所提供的一种包含计算机可执行指令的存储介质,其计算机可执行指令不限于如上所述的方法操作,还可以执行本申请任意实施例所提供的数据访问方法中的相关操作。
通过以上关于实施方式的描述，所属领域的技术人员可以清楚地了解到，本申请可借助软件及必需的通用硬件来实现，当然也可以通过硬件实现，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上 或者说对一些情形做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品可以存储在计算机可读存储介质中，如计算机的软盘、只读存储器(Read-Only Memory,ROM)、随机存取存储器(Random Access Memory,RAM)、闪存(FLASH)、硬盘或光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述的方法。
以上所述，仅为本申请的示例性实施例而已，并非用于限定本申请的保护范围。
本领域内的技术人员应明白，术语用户终端涵盖任何适合类型的无线用户设备，例如移动电话、便携数据处理装置、便携网络浏览器或车载移动台。
一般来说，本申请的多种实施例可以在硬件或专用电路、软件、逻辑或其任何组合中实现。例如，一些方面可以被实现在硬件中，而其它方面可以被实现在可以被控制器、微处理器或其它计算装置执行的固件或软件中，尽管本申请不限于此。
本申请的实施例可以通过移动装置的数据处理器执行计算机程序指令来实现，例如在处理器实体中，或者通过硬件，或者通过软件和硬件的组合。计算机程序指令可以是汇编指令、指令集架构(ISA)指令、机器指令、机器相关指令、微代码、固件指令、状态设置数据、或者以一种或多种编程语言的任意组合编写的源代码或目标代码。
本申请附图中的任何逻辑流程的框图可以表示程序步骤，或者可以表示相互连接的逻辑电路、模块和功能，或者可以表示程序步骤与逻辑电路、模块和功能的组合。计算机程序可以存储在存储器上。存储器可以具有任何适合于本地技术环境的类型并且可以使用任何适合的数据存储技术实现，例如但不限于只读存储器(ROM)、随机访问存储器(RAM)、光存储器装置和系统(数码多功 能光碟DVD或CD光盘)等。计算机可读介质可以包括非瞬时性存储介质。数据处理器可以是任何适合于本地技术环境的类型，例如但不限于通用计算机、专用计算机、微处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、可编程逻辑器件(FGPA)以及基于多核处理器架构的处理器。
本申请实施例提供的数据访问方法、控制器、存储器和存储介质，若所述访问地址中包含的任一地址是错误节点地址，基于错误节点地址与映射节点地址的映射关系确定映射节点地址；基于所述访问请求和所述映射节点地址对数据进行读写访问。解决了DRAM芯片中部分存储区域被损坏，便需要更换DRAM芯片的问题，达到了提高DRAM芯片利用率的效果，节省了产品成本，提高了产品可用度。
通过示范性和非限制性的示例，上文已提供了对本申请的示范实施例的详细描述。但结合附图和权利要求来考虑，对以上实施例的多种修改和调整对本领域技术人员来说是显而易见的，但不偏离本发明的范围。因此，本发明的恰当范围将根据权利要求确定。

Claims (13)

  1. 一种数据访问方法，包括:
    接收应用端发送的访问请求，其中，所述访问请求中携带访问地址；
    若所述访问地址中包含的任一地址是错误节点地址，基于错误节点地址与映射节点地址的映射关系确定映射节点地址；
    基于所述访问请求和所述映射节点地址对数据进行访问。
  2. 根据权利要求1所述的方法，其中，所述接收应用端发送的访问请求之前，还包括：
    建立错误节点地址与映射节点地址的映射关系。
  3. 根据权利要求2所述的方法，其中，所述确定错误节点地址与映射节点地址的映射关系，包括：
    以节点为单位对存储空间进行读写测试；
    将测试失败的节点地址确定为所述错误节点地址；
    从测试成功的节点地址中选择任一节点作为所述映射节点地址；
    建立所述错误节点地址与所述映射节点地址的映射关系。
  4. 根据权利要求3所述的方法，其中，所述以节点为单位对存储空间进行读写测试之前，还包括：
    以节点为单位对存储空间进行划分。
  5. 根据权利要求3所述的方法，其中，所述以节点为单位对动态存储器的存储空间进行读写测试之前，还包括：
    设置预设数量的记录位；其中，所述记录位用于记录所述错误节点地址与所述映射节点地址的映射关系。
  6. 根据权利要求5所述的方法，其中，所述记录位中还记录有效标识，其 中，所述有效标识用于指示此条记录是否有效。
  7. 根据权利要求5所述的方法，其中，所述建立错误节点地址与所述映射节点地址的映射关系，包括：
    在所述错误节点地址的数量小于所述记录位的数量情况下，在各个记录位中依次记录所述错误节点地址与所述映射节点地址的映射关系。
  8. 根据权利要求5所述的方法，其中，所述记录位的数量由所述应用端确定。
  9. 根据权利要求3所述的方法，其中，所述建立错误节点地址与所述映射节点地址的映射关系之后，还包括：
    将所述错误节点地址的数量发送至所述应用端。
  10. 一种控制器，包括：记录访问单元，其中，
    所述记录访问单元，被配置为接收应用端发送的访问请求，其中，所述访问请求中携带访问地址；若所述访问地址中包含的任一地址是错误节点地址，基于错误节点地址与映射节点地址的映射关系确定映射节点地址；基于所述访问请求和所述映射节点地址对数据进行访问。
  11. 根据权利要求10所述的控制器，还包括：测试单元，其中，
    测试单元，被配置为以节点为单位对对存储器的存储空间进行读写测试，并将测试失败的节点地址传输至记录访问单元；
    记录访问单元，被配置为将测试失败的节点地址确定为所述错误节点地址，将所述存储空间尾部测试成功的节点地址确定为所述映射节点地址，建立所述错误节点地址与所述映射节点地址的映射关系。
  12. 一种存储器，包括如权利要求10-11中任一项所述的控制器。
  13. 一种存储介质，存储有计算机程序，所述计算机程序被处理器执行时 实现权利要求1-9任一项所述的方法。
PCT/CN2021/089674 2020-06-10 2021-04-25 数据访问方法、控制器、存储器和存储介质 WO2021249046A1 (zh)

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