WO2021246825A1

WO2021246825A1 - Three-dimensional flash memory based on ferroelectric material and operating method thereof

Info

Publication number: WO2021246825A1
Application number: PCT/KR2021/007027
Authority: WO
Inventors: 송윤흡; 최선준
Original assignee: 한양대학교 산학협력단
Priority date: 2020-06-05
Filing date: 2021-06-04
Publication date: 2021-12-09

Abstract

A three-dimensional flash memory based on a ferroelectric material and an operating method thereof are disclosed, and a three-dimensional flash memory which performs a hole injection-based memory operation by a gate induced drain leakage (GIDL) phenomenon in at least one selection line instead of applying a voltage to a substrate is suggested. In addition, a three-dimensional flash memory which performs a program operation in response to a negative program voltage applied to a selected word line of a target memory cell is suggested.

Description

3D flash memory based on ferroelectric material and its operation method

The following embodiments relate to a three-dimensional flash memory, and more particularly, a description of a three-dimensional flash memory based on a ferroelectric material and a program operation method thereof.

A flash memory device is an Electrically Erasable Programmable Read Only Memory (EEPROM), the memory being, for example, a computer, a digital camera, an MP3 player, a game system, a memory stick. ) can be commonly used. Such a flash memory device electrically controls input/output of data by Fowler-Nordheimtunneling or hot electron injection.

Specifically, referring to FIG. 1 showing a conventional three-dimensional flash memory array, the three-dimensional flash memory array includes a common source line CSL, a bit line BL, and a common source line CSL and a bit line BL. ) may include a plurality of cell strings (CSTR) disposed between.

The bit lines are two-dimensionally arranged, and a plurality of cell strings CSTR are connected in parallel to each of the bit lines. The cell strings CSTR may be commonly connected to the common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the plurality of bit lines and one common source line CSL. In this case, there may be a plurality of common source lines CSL, and the plurality of common source lines CSL may be two-dimensionally arranged. Here, the same voltage may be applied to the plurality of common source lines CSL, or each of the plurality of common source lines CSL may be electrically controlled.

Each of the cell strings CSTR includes a ground select transistor GST connected to the common source line CSL, a string select transistor SST connected to the bit line BL, and ground and string select transistors GST and SST. ) may be formed of a plurality of memory cell transistors MCT disposed between. In addition, the ground select transistor GST, the string select transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CSL may be commonly connected to sources of the ground select transistors GST. In addition, the ground select line GSL, the plurality of word lines WL0 - WL3 and the plurality of string select lines SSL disposed between the common source line CSL and the bit line BL are ground selectable. It may be used as electrode layers of the transistor GST, the memory cell transistors MCT, and the string select transistors SST, respectively. In addition, each of the memory cell transistors MCT includes a memory element. Hereinafter, the string selection line SSL may be expressed as an upper selection line USL, and the ground selection line GSL may be expressed as a lower selection line LSL.

On the other hand, the conventional 3D flash memory increases the degree of integration by vertically stacking cells in order to meet the excellent performance and low price demanded by consumers.

For example, referring to FIG. 2 showing the structure of a conventional three-dimensional flash memory, in the conventional three-dimensional flash memory, interlayer insulating layers 211 and horizontal structures 250 are alternately formed on a substrate 200 . Repeatedly formed electrode structures 215 are disposed and manufactured. The interlayer insulating layers 211 and the horizontal structures 250 may extend in the first direction. The interlayer insulating layers 211 may be, for example, a silicon oxide layer, and the lowermost interlayer insulating layer 211a of the interlayer insulating layers 211 may have a thickness smaller than that of the other interlayer insulating layers 211 . Each of the horizontal structures 250 may include first and second blocking

insulating layers

242 and 243 and an electrode layer 245 . A plurality of electrode structures 215 may be provided, and the plurality of electrode structures 215 may be disposed to face each other in a second direction crossing the first direction. The first and second directions may correspond to the x-axis and the y-axis of FIG. 2 , respectively. Trenches 240 separating the plurality of electrode structures 215 may extend in the first direction. Highly doped impurity regions may be formed in the substrate 200 exposed by the trenches 240 , so that a common source line CSL may be disposed. Although not shown, isolation insulating layers filling the trenches 240 may be further disposed.

Vertical structures 230 penetrating the electrode structure 215 may be disposed. For example, in a plan view, the vertical structures 230 may be arranged in a matrix form along the first and second directions. As another example, the vertical structures 230 may be arranged in the second direction, and may be arranged in a zigzag shape in the first direction. Each of the vertical structures 230 may include a passivation layer 224 , a charge storage layer 225 , a tunnel insulating layer 226 , and a channel layer 227 . For example, the channel layer 227 may be disposed in a hollow tube shape therein, and in this case, a buried film 228 filling the inside of the channel layer 227 may be further disposed. A drain region D may be disposed on the channel layer 227 , and a conductive pattern 229 may be formed on the drain region D to be connected to the bit line BL. The bit line BL may extend in a direction crossing the horizontal electrodes 250 , for example, in a second direction. For example, the vertical structures 230 aligned in the second direction may be connected to one bit line BL.

The first and second blocking

insulating layers

242 and 243 included in the horizontal structures 250 and the charge storage layer 225 and the tunnel insulating layer 226 included in the vertical structures 230 are the 3D flash memory. It can be defined as an oxide-nitride-oxide (ONO) layer that is an information storage element. That is, some of the information storage elements may be included in the vertical structures 230 , and others may be included in the horizontal structures 250 . For example, among the information storage elements, the charge storage layer 225 and the tunnel insulating layer 226 are included in the vertical structures 230 , and the first and second blocking

insulating layers

242 and 243 are the horizontal structures 250 . can be included in

Epitaxial patterns 222 may be disposed between the substrate 200 and the vertical structures 230 . The epitaxial patterns 222 connect the substrate 200 and the vertical structures 230 . The epitaxial patterns 222 may contact the horizontal structures 250 of at least one layer. That is, the epitaxial patterns 222 may be disposed to be in contact with the lowermost horizontal structure 250a. According to another embodiment, the epitaxial patterns 222 may be disposed to contact the horizontal structures 250 of a plurality of layers, for example, two layers. Meanwhile, when the epitaxial patterns 222 are disposed to be in contact with the lowermost horizontal structure 250a , the lowermost horizontal structure 250a may be disposed to be thicker than the remaining horizontal structures 250 . The lowermost horizontal structure 250a in contact with the epitaxial patterns 222 may correspond to the ground selection line GSL of the 3D flash memory array described with reference to FIG. 1 , and the vertical structures 230 . The remaining horizontal structures 250 in contact with may correspond to a plurality of word lines WL0-WL3.

Each of the epitaxial patterns 222 has a recessed sidewall 222a. Accordingly, the lowermost horizontal structure 250a in contact with the epitaxial patterns 222 is disposed along the profile of the recessed sidewall 222a. That is, the lowermost horizontal structure 250a may be disposed in a convex shape inward along the recessed sidewalls 222a of the epitaxial patterns 222 .

The conventional three-dimensional flash memory having such a structure generally uses an ONO layer as an information storage element (charge storage layer) as described above, and the vertical cell current decreases as the number of vertical memory cells increases. There is a problem of characteristic deterioration.

Accordingly, a technique of using a ferroelectric material as an information storage element (charge storage layer) in place of the ONO layer has been proposed, but research and development on a program operation when a ferroelectric material is used as the charge storage layer is still insufficient.

Accordingly, there is a need to propose a technique for a program operation in a 3D flash memory using a ferroelectric material as an information storage element.

One embodiment proposes a technique for a program operation in a three-dimensional flash memory using a ferroelectric material as an information storage element.

In more detail, embodiments provide a 3D flash memory that performs a hole injection-based memory operation by a gate induced drain leakage (GIDL) phenomenon in at least one selection line, rather than applying a voltage to the substrate. suggest

In addition, some embodiments propose a 3D flash memory that performs a program operation in response to a negative program voltage being applied to a selected word line of a target memory cell, and a method of operating the same.

According to an exemplary embodiment, in the 3D flash memory, at least one string extending in one direction on a substrate, the at least one string extending in the one direction, and the channel layer extending in the one direction to surround the channel layer including a charge storage layer formed to extend to -; at least one selection line vertically connected to an upper end or lower end of the at least one string; and a plurality of word lines vertically connected to the at least one string while being positioned above or below the at least one selection line, wherein the 3D flash memory includes a GIDL (Gate) in the at least one selection line. It is characterized in that the memory operation based on hole injection by the induced drain leakage phenomenon is performed.

According to one aspect, in the 3D flash memory, a hole is injected into the channel layer by a GIDL phenomenon according to a voltage applied to each of the bit line positioned above the at least one string and the at least one selection line, and Based on the diffusion, it may be characterized in that a hole injection-based program operation is performed on the at least one string.

According to another aspect, in the 3D flash memory, a power voltage is applied to a bit line of a target string including a target memory cell and a GIDL having a value smaller than the power supply voltage is applied to at least one selection line connected to the target string. In response to the voltage being applied and the program voltage being applied to the word line corresponding to the target memory cell, a selective hole injection-based program operation may be performed on the target memory cell based on the GIDL phenomenon.

According to yet another aspect, the 3D flash memory may include a voltage applied to a bit line of a first adjacent string sharing at least one selection line with the target string and a second adjacent bit line sharing the target string and a bit line. A selective hole for controlling a voltage applied to at least one selection line connected to a string so that the hole is not injected into each of the first adjacent string and the second adjacent string and the hole is injected only into the target string It may be characterized in that the injection-based program operation is performed.

According to yet another aspect, the 3D flash memory prevents the hole from being injected into the first adjacent string in response to a voltage having a value smaller than the power supply voltage being applied to the bit line of the first adjacent string. A selective hole injection-based program operation may be performed so that the hole is injected only into the target string by the GIDL phenomenon.

According to another aspect, in the 3D flash memory, in response to the power supply voltage being applied to at least one selection line connected to the second adjacent string, the hole is not injected into the second adjacent string, A selective hole injection-based program operation may be performed so that the hole is injected only into the target string by the GIDL phenomenon.

According to another aspect, the charge storage layer may be formed of a ferroelectric material.

According to another aspect, the ferroelectric material is doped with at least one material of _{HfO x} _{, Al, Zr, or Si having an orthorhombic crystal structure HfO x} , PZT(Pb(Zr, Ti)O ₃ ), PTO(PbTiO ₃ ), SBT(SrBi ₂ Ti ₂ O ₃ ), BLT(Bi(La, Ti)O ₃ ), PLZT(Pb(La, Zr)TiO ₃ ), BST(Bi(Sr, Ti) O ₃ ), barium titanate (BaTiO ₃ ), P(VDF-TrFE), PVDF, AlO _x , ZnO _x , TiO _x , TaO _x or InO _x may be characterized as comprising at least one.

According to an embodiment, the 3D flash memory includes a plurality of strings extending in one direction on a substrate, each of the plurality of strings extending in the one direction and forming the channel layer to surround the channel layer. comprising a charge storage layer extending in a direction and configuring a plurality of memory cells respectively corresponding to a plurality of word lines; and the plurality of word lines vertically connected to each of the plurality of strings, wherein a negative program voltage (negative) is applied to a selected word line corresponding to a target memory cell to be subjected to a program operation among the plurality of word lines. program voltage) is applied, the program operation may be performed.

According to an aspect, the 3D flash memory may include a difference between the negative program voltage applied to the selected word line and a ground voltage applied to a bit line of a selected string including the target memory cell among the plurality of strings. The program operation may be performed on the target memory cell by forming a channel in the selected string through a potential difference.

According to another aspect, in the 3D flash memory, each of the unselected adjacent word lines corresponding to the adjacent memory cells adjacent to the target memory cell among the plurality of word lines is floated or the unselected adjacent word lines a first pass voltage in each of the plurality of word lines, wherein the first pass voltage is a voltage applied to each of the unselected word lines excluding the target word line and the unselected adjacent word lines among the plurality of word lines. In response to the two-pass voltage being applied, it may be characterized in that the breakdown between the selected word line and the non-selected adjacent word lines is improved.

According to another aspect, in the 3D flash memory, neighboring memory cells adjacent to the adjacent memory cells among the unselected word lines—the neighboring memory cells include the target memory cell in each of the adjacent memory cells; By turning on the adjacent memory cells to a fringing field by the first pass voltage applied to unselected neighboring word lines corresponding to including adjacent memory cells, the target memory cell It may be characterized in that the program operation is performed for

According to another aspect, in the 3D flash memory, by not forming a channel in each of the unselected strings that do not include the target memory cell among the plurality of strings, the three-dimensional flash memory is included in each of the unselected strings. It may be characterized in that the memory cells are prevented from being programmed.

One embodiment may propose a technique for a program operation in a 3D flash memory using a ferroelectric material as an information storage element.

In more detail, embodiments provide a 3D flash memory that performs a hole injection-based memory operation by a gate induced drain leakage (GIDL) phenomenon in at least one selection line, rather than applying a voltage to the substrate. can suggest

In addition, exemplary embodiments may propose a 3D flash memory that performs a program operation in response to a negative program voltage being applied to a selected word line of a target memory cell and a method of operating the same.

1 is a simplified circuit diagram illustrating an array of a conventional three-dimensional flash memory.

2 is a perspective view showing the structure of a conventional three-dimensional flash memory.

3 is a Y-Z cross-sectional view illustrating a three-dimensional flash memory according to an exemplary embodiment.

4 is a simplified circuit diagram illustrating a hole injection-based program operation of a 3D flash memory according to an exemplary embodiment.

5 to 6 are simplified circuit diagrams for explaining a selective hole injection-based program operation for allowing holes to be injected only into a target string in a 3D flash memory according to an exemplary embodiment.

7 is a diagram for explaining voltages applied in a hole injection-based program operation of a 3D flash memory according to an exemplary embodiment.

8 is a flowchart illustrating a method of operating a 3D flash memory according to an exemplary embodiment.

9 is a Y-Z cross-sectional view illustrating a three-dimensional flash memory according to another exemplary embodiment.

10 is a simplified circuit diagram for explaining a negative program voltage-based program operation of a 3D flash memory according to another exemplary embodiment.

11 is a simplified circuit diagram illustrating a selective program operation for preventing a program in unselected strings in a 3D flash memory according to another exemplary embodiment.

12 is a flowchart illustrating a method of operating a 3D flash memory according to another exemplary embodiment.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the examples. Also, like reference numerals in each figure denote like members.

In addition, the terms used in this specification are terms used to properly express the preferred embodiment of the present invention, which may vary depending on the intention of a user or operator or customs in the field to which the present invention belongs. Accordingly, definitions of these terms should be made based on the content throughout this specification.

3 is a Y-Z cross-sectional view illustrating a three-dimensional flash memory according to an exemplary embodiment. Hereinafter, for the convenience of description, the 3D flash memory 300 according to an embodiment includes components such as a substrate, a bit line positioned above at least one string, and a source line positioned below the at least one string. It may be shown and described while omitted. However, the 3D flash memory 300 according to an embodiment is not limited thereto, and may further include additional components based on the structure of the existing 3D flash memory illustrated with reference to FIG. 2 . In addition, the 3D flash memory 300 according to an exemplary embodiment is illustrated as including one string, but is not limited thereto and may include a plurality of strings.

Referring to FIG. 3 , the 3D flash memory 300 according to an embodiment includes at least one string 310 , at least one selection line 320 , and a plurality of word lines 330 . can do. Hereinafter, the 3D flash memory 300 essentially includes at least one string 310 , at least one selection line 320 , and a plurality of word lines 330 , and includes a plurality of word lines 330 . It may further include a plurality of insulating layers (not shown) interposed therebetween, a bit line disposed above the at least one string 310 , and a source line disposed below the string 310 .

At least one string 310 is formed to extend in one direction (eg, z-direction) on the substrate, and each includes a channel layer 311 and a charge storage layer 312 , so that a plurality of words are connected in a vertical direction. Memory cells corresponding to each of the lines 330 may be configured.

The charge storage layer 312 is extended to surround the channel layer 311 , and traps charges or holes due to voltages applied through the plurality of word lines 330 , or states of charges (eg, polarization of charges). state), serves as a data storage in the three-dimensional flash memory 300, and may be characterized in that it is formed of a ferroelectric material. Wherein the ferroelectric material is HfO _x, Al, of at least one material selected from the group consisting of Zr or Si doped HfO _x, PZT has an orthorhombic (Orthorhombic) crystalline structure (Pb (Zr, Ti) O 3), PTO (PbTiO 3) , SBT(SrBi ₂ Ti ₂ O ₃ ), BLT(Bi(La, Ti)O ₃ ), PLZT(Pb(La, Zr)TiO ₃ ), BST(Bi(Sr, Ti)O ₃ ), barium titanate ( By including at least one of barium titanate, BaTiO ₃ ), P(VDF-TrFE), PVDF, AlO _x , ZnO _x , TiO _x , TaO _x or InO _x , binary data values can be represented by voltage change due to polarization. , can be used as a charge storage layer.

The channel layer 311 may be formed of single crystalline silicon or polysilicon, and a buried layer (not shown) filling the inside may be further disposed.

The at least one selection line 320 is at least one drain selection line (DSL) vertically connected to the top of the at least one string 310 (the at least one drain selection line is the at least one string 310 ). ) or at least one source selection line (SSL) vertically connected to the lower end of the at least one string 310 (at least one source selection line) is any one of W (tungsten), Ti (titanium), Ta (tantalum), Au (copper) or Au (gold) ) may be formed of a conductive material such as

Hereinafter, at least one selection line 320 is illustrated as one drain selection line in the drawings, but as described above, it is not limited or limited thereto.

The plurality of word lines 330 are positioned above or below the at least one selection line 320 and are vertically connected to the at least one string 310 , and include W (tungsten), Ti (titanium), and Ta (tantalum). ), Au (copper), or Au (gold) may be formed of a conductive material, and a memory operation (such as a read operation, a program operation, and an erase operation) may be performed by applying a voltage to the corresponding memory cells.

In the three-dimensional flash memory 300 having such a structure, since the charge storage layer 312 is formed of a ferroelectric material, a gate induced drain (GIDL) in at least one selection line 320 rather than applying a voltage to the substrate It is characterized in that the memory operation based on hole injection due to the leakage phenomenon is performed. In more detail, in the 3D flash memory 300 , a hole is formed by a GIDL phenomenon according to a voltage applied to each of the bit line positioned above the at least one string 310 and the at least one selection line 320 . Based on the implantation and diffusion into the layer 311 , a hole injection-based program operation may be performed on the at least one string 320 . A detailed description thereof will be provided below.

4 is a simplified circuit diagram for explaining a hole injection-based program operation of a 3D flash memory according to an embodiment, and FIGS. 5 to 6 are selections for injecting holes only into a target string in the 3D flash memory according to an embodiment. It is a simplified circuit diagram for explaining a typical hole injection-based program operation, and FIG. 7 is a diagram for explaining voltages applied in a hole injection-based program operation of a 3D flash memory according to an exemplary embodiment. Hereinafter, the hole injection-based program operation described with reference to FIGS. 4 to 7 may be performed by the 3D flash memory 300 illustrated in FIG. 3 as a subject.

Referring to FIG. 4 , in the 3D flash memory according to an embodiment, a hole is formed into a channel layer by a GIDL phenomenon according to a voltage applied to each of a bit line and at least one selection line positioned above at least one string. Based on the injection and diffusion, a hole injection-based program operation for at least one string may be performed. Hereinafter, at least one string including a target memory cell on which a hole injection-based program operation is performed is referred to as a target string, and a word line corresponding to the target memory cell among a plurality of word lines is referred to as a selected word line, Among the plurality of word lines, word lines corresponding to memory cells other than the target memory cell are referred to as unselected word lines.

In more detail, the 3D flash memory applies a power voltage (eg, 10V) to the bit line 411 of the target string 410 including the target memory cell 400 and at least is connected to the target string 410 . A GIDL voltage (eg, 2V) having a value smaller than the power supply voltage is applied to one selected line 412 , a program voltage (eg, 0V) is applied to the selected word line 413 , and unselected word lines 414 . , 415) by applying a pass voltage (for example, 7V) to each of the bit lines 411 and at least one selection line 412 to generate a GIDL phenomenon due to a voltage difference between the bit line 411 and the at least one selection line 412 so that a hole is formed in the target string 410 By allowing injection and diffusion into the channel layer, a selective hole injection-based program operation for the target memory cell 400 may be performed.

In particular, the three-dimensional flash memory includes a voltage applied to a bit line 421 of a first adjacent string 420 (a string that shares at least one selection line 412 with a target string 410) and a second adjacent string ( The first adjacent string 420 and the second adjacent string 430 by adjusting the voltage applied to at least one selection line 431 of 430 (the string sharing the target string 410 and the bit line 411 ) ), it is possible to perform a selective hole injection-based program operation so that holes are not injected into each and only the target string 410 is injected.

In this regard, referring to FIG. 5 , the 3D flash memory includes a voltage (GIDL voltage applied to at least one selection line 412) and By applying a voltage of a value that does not differ significantly, for example, 4V, the GIDL phenomenon does not occur between the bit line 421 and the at least one selection line 412 of the first adjacent string 420, A hole may not be injected into the first adjacent string 420 . Accordingly, as described above, the 3D flash memory generates a GIDL phenomenon only between the bit line 411 of the target string 410 and the at least one selection line 412 so that a hole is only formed in the channel layer of the target string 410 . Injection and diffusion may be performed, and through this, a selective hole injection-based program operation may be performed on the target string 410 including the target memory cell.

Also, referring to FIG. 6 , the 3D flash memory is connected to a power supply voltage (at least one selection line 412 of the target string 410 ) connected to at least one selection line 431 connected to the second adjacent string 430 . A GIDL phenomenon is generated between the bit line 411 and the at least one selection line 431 of the second adjacent string 430 by applying a voltage having a large difference from the applied GIDL voltage, for example, 10V. By not doing so, it is possible to prevent a hole from being injected into the second adjacent string 430 . Accordingly, as described above, the 3D flash memory generates a GIDL phenomenon only between the bit line 411 of the target string 410 and the at least one selection line 412 so that a hole is only formed in the channel layer of the target string 410 . Injection and diffusion may be performed, and through this, a selective hole injection-based program operation may be performed on the target string 410 including the target memory cell.

As such, in order to perform a selective hole injection-based program operation on the target string (more precisely, the target memory cell), the 3D flash memory uses the bit line 411 of the target string 410 described with reference to FIGS. 4 to 6 . A power supply voltage applied to , a GIDL voltage applied to at least one selection line 412 connected to the target string 410 , a program voltage applied to the selected word line 413 , and unselected word lines 414 and 415 ) A pass voltage applied to each, a voltage applied to the bit line 421 of the first adjacent string 420, and a power supply voltage applied to at least one selection line 431 connected to the second adjacent string 430 are shown. It can be adjusted to a value such as 7.

In addition, the 3D flash memory can perform a selective hole injection-based program operation in a short time of 400 ns by adjusting the timing at which the voltages are applied as shown in FIG. 7 .

As described above, in the 3D flash memory according to an embodiment, while applying a voltage to generate a GIDL phenomenon between the bit line 411 of the target string 410 and the at least one selection line 412 , the target string ( By adjusting voltages applied to the 410 and the

adjacent strings

420 and 430 , a selective hole injection-based program operation for the target string including the target memory cell may be implemented.

Although only the hole injection-based program operation has been described above, the hole injection-based read operation and the erase operation may also be performed in the same principle.

8 is a flowchart illustrating a method of operating a 3D flash memory according to an exemplary embodiment. Hereinafter, the operation method of the 3D flash memory may be performed based on the contents described with reference to FIGS. 4 to 7 , in which the 3D flash memory 300 described with reference to FIG. 3 is the main body.

Referring to FIG. 8 , in operation S810 , the 3D flash memory according to an embodiment may apply a voltage to each of a bit line and at least one selection line positioned above at least one string.

After that, in step S820 , the 3D flash memory is formed in which holes are injected and diffused into the channel layer by a GIDL phenomenon according to a voltage applied to each of the bit line and the at least one selection line positioned above the at least one string. Based on this, a hole injection-based program operation for at least one string may be performed.

In more detail, the manufacturing system applies a power voltage to the bit line of the target string including the target memory cell through step S810 and applies a GIDL voltage having a value smaller than the power supply voltage to at least one selection line connected to the target string. by applying a GIDL phenomenon between the bit line of the target string and at least one selection line and applying a program voltage to the word line corresponding to the target memory cell, through step S820 , the bit line of the target string and at least one A selective hole injection-based program operation may be performed on a target memory cell based on a GIDL phenomenon between selection lines.

In particular, in step S810 , the manufacturing system determines a voltage applied to a bit line of a first adjacent string sharing at least one selection line with the target string and at least one connected to a second adjacent string sharing a bit line with the target string. A selective hole injection-based program operation is performed so that holes are not injected into each of the first and second adjacent strings and only the target string is injected in step S820 by controlling the voltage applied to the selected line of can do.

For example, in the manufacturing system, a voltage of a value smaller than the power supply voltage is applied to the bit line of the first adjacent string in step S810 , so that a hole is not injected into the first adjacent string in step S820 and only in the target string. It is possible to perform a selective hole injection-based program operation for hole injection by the GIDL phenomenon.

For another example, the manufacturing system applies a power voltage to at least one selection line connected to the second adjacent string in step S810 , so that a hole is not injected into the second adjacent string in step S820 and the target string It is possible to perform a selective hole injection-based program operation that allows holes to be injected by the GIDL phenomenon.

9 is a Y-Z cross-sectional view illustrating a three-dimensional flash memory according to another exemplary embodiment. Hereinafter, for convenience of description, the 3D flash memory 900 according to another embodiment includes a substrate, a bit line positioned above each of the plurality of strings, and a source line positioned below each of the plurality of strings. Elements may be shown and described with omissions. However, the 3D flash memory 900 according to another embodiment is not limited thereto, and may further include additional components based on the structure of the existing 3D flash memory illustrated with reference to FIG. 2 . Also, the 3D flash memory 900 according to another exemplary embodiment is illustrated as including two strings, but is not limited thereto and may include three or more strings.

Referring to FIG. 9 , a 3D flash memory 900 according to another embodiment may include a plurality of strings 910 and a plurality of word lines 920 . Hereinafter, in the 3D flash memory 900 , a plurality of insulating layers (not shown) interposed between the plurality of word lines 920 , and at least one drain positioned on top of the plurality of word lines 920 are selected. A line (Drain Selection Line; DSL) (at least one drain selection line is connected to a bit line (not shown) positioned above each of the plurality of strings 910 ) and a plurality of word lines 920 at the lower end At least one source selection line (SSL) positioned (at least one source selection line is connected to a source line (not shown) positioned below each of the plurality of strings 910), a plurality of strings Each of 910 may further include a bit line disposed above and a source line disposed below each of the 910 .

Each of the plurality of strings 910 is formed to extend in one direction (eg, z-direction) on the substrate, and each includes a channel layer 911 and a charge storage layer 912 , so that a plurality of strings connected in a vertical direction are formed. Memory cells respectively corresponding to the word lines 920 may be configured.

The charge storage layer 912 is extended to surround the channel layer 911 and traps charges or holes due to voltages applied through the plurality of word lines 920 , or states of charges (eg, polarization of charges). state), it serves as a data storage in the three-dimensional flash memory 900, and may be characterized in that it is formed of a ferroelectric material. Wherein the ferroelectric material is HfO _x, Al, of at least one material selected from the group consisting of Zr or Si doped HfO _x, PZT has an orthorhombic (Orthorhombic) crystalline structure (Pb (Zr, Ti) O 3), PTO (PbTiO 3) , SBT(SrBi ₂ Ti ₂ O ₃ ), BLT(Bi(La, Ti)O ₃ ), PLZT(Pb(La, Zr)TiO ₃ ), BST(Bi(Sr, Ti)O ₃ ), barium titanate ( By including at least one of barium titanate, BaTiO ₃ ), P(VDF-TrFE), PVDF, AlO _x , ZnO _x , TiO _x , TaO _x or InO _x , binary data values can be represented by voltage change due to polarization. , can be used as a charge storage layer.

The channel layer 911 may be formed of single crystalline silicon or polysilicon, and a buried layer (not shown) filling the inside may be further disposed.

The plurality of word lines 920 are vertically connected to each of the plurality of strings 910 and are conductive such as W (tungsten), Ti (titanium), Ta (tantalum), Au (copper), or Au (gold). It is formed of a material, and a memory operation (such as a read operation, a program operation, and an erase operation) may be performed by applying a voltage to the corresponding memory cells.

In the 3D flash memory 900 having such a structure, as the charge storage layer 912 is formed of a ferroelectric material, a selected word corresponding to a target memory cell to be programmed from among the plurality of word lines 920 . It is characterized in that the program operation is performed by applying a negative program voltage (-Vpgm) to the line. In more detail, the 3D flash memory 900 includes a negative program voltage applied to a selected word line and a ground voltage GND applied to a bit line of a selected string including a target memory cell among the plurality of strings 910 . ; 0V), a channel may be formed in the selected string (more precisely, a channel may be formed on the channel layer 911 included in the selected string) to perform a program operation on the target memory cell. A detailed description thereof will be provided below.

10 is a simplified circuit diagram for explaining a negative program voltage-based program operation of a 3D flash memory according to another exemplary embodiment, and FIG. 11 is a schematic diagram of preventing a program in unselected strings in a 3D flash memory according to another exemplary embodiment. It is a simplified circuit diagram for explaining the optional program operation. Hereinafter, the program operation described with reference to FIGS. 10 to 11 may be performed by the 3D flash memory 900 illustrated in FIG. 9 as a subject.

Referring to FIG. 10 , in the 3D flash memory according to another embodiment, a negative program voltage (-Vpgm; for example, -10V) applied to a selected word line 1010 and a target memory cell 1030 among a plurality of strings A channel is formed in the selected string 1020 through a potential difference between the ground voltage (GND; 0V) applied to the bit line of the selected string 1020 including A program operation may be performed on the target memory cell 1030 by transferring charges or holes to the charge storage layer of the target memory cell 1030 by forming a channel thereon).

Hereinafter, among a plurality of strings, a string including a target memory cell 1030 on which a program operation is performed is referred to as a selected string 1020, and strings excluding the selected string 1020 are referred to as unselected strings 1021, , among the plurality of memory cells, the memory cells closest to the target memory cell 1030 are referred to as adjacent memory cells 1031 , and the memory cells closest to the adjacent memory cells 1031 among the plurality of memory cells (target memory) (memory cells excluding the cell 1030) are referred to as neighboring memory cells 1032, a word line corresponding to the target memory cell 1030 among a plurality of word lines is referred to as a selected word line 1010, and adjacent memory cells The unselected word lines corresponding to 1031 are referred to as unselected adjacent word lines 1011 , and unselected word lines corresponding to the neighboring memory cells 1032 are referred to as unselected neighboring word lines 1012 .

In more detail, the 3D flash memory applies a ground voltage (GND; 0V) to the bit line of the selected string 1020 including the target memory cell 1030 and selects at least one drain connected to the selected string 1020 . The power supply voltage Vcc is applied to the line DSL, the source line of the selected string 1020 and at least one source selection line SSL connected to the selected string 1020 are floated, and the selected word line 1010 is A negative program voltage applied to the selected word line 1010 by applying a negative program voltage (-Vpgm; for example, -10V) and a bit of the selected string 1020 including the target memory cell 1030 among the plurality of strings A potential difference between the ground voltage (GND; 0V) applied to the line may be formed. Accordingly, in the 3D flash memory, the negative program voltage applied to the selected word line 1010 and the ground voltage GND applied to the bit line of the selected string 1020 including the target memory cell 1030 among the plurality of strings ; 0V) to form a channel in the selected string 1020 (more precisely, by forming a channel on the channel layer included in the selected string 1020) to transfer a charge or a hole to the charge of the target memory cell 1030 By transferring to the storage layer, a program operation on the target memory cell 1030 may be performed.

In this case, in the 3D flash memory, the ratio of the selected string 1020 to prevent programming of the

unselected memory cells

1031 and 1032 excluding the target memory cell 1030 among the memory cells included in the selected string 1020 . The selected

memory cells

1031 and 1032 may be turned on.

However, the unselected neighboring word lines 1012 of the neighboring memory cells 1032 are the unselected neighboring word lines 1011 of the neighboring memory cells 1031 which are the memory cells closest to the target memory cell 1030 . When a high first pass voltage Vpass1 (eg, 9V) applied to is applied, the selected word line 1010 to which a negative program voltage is applied and unselected adjacent word lines 1011 to which a high first pass voltage is applied are applied. Breakdown between them may occur. Accordingly, in the 3D flash memory, each of the unselected adjacent word lines 1011 is floated during a program operation to prevent and improve breakdown between the selected word line 1010 and the unselected adjacent word lines 1011 , or A second pass voltage Vpass2 (eg, 2V) having a smaller value than the first pass voltage may be applied to each of the unselected adjacent word lines 1011 .

In this case, the 3D flash memory turns on the adjacent memory cells 1031 as a fringing field by the first pass voltage applied to the unselected neighboring word lines 1012 of the neighboring memory cells 1032 . Thus, only the target memory cell 1030 can be programmed.

In addition, the 3D flash memory does not form a channel in each of the unselected strings 1021 that do not include the target memory cell 1030 among the plurality of strings, so that the memory cells included in each of the unselected strings 1021 are memory cells. can be prevented from being programmed.

For example, referring to FIG. 11 , the 3D flash memory is connected to the unselected string 1021 with respect to the unselected string 1021 sharing at least one drain select line DSL with the selected string 1020 . A channel may not be formed in the unselected string 1021 by applying a negative voltage (eg, -5V) to the bit line.

In the above, only the program operation to which the negative program voltage is applied has been described, but the read operation and the erase operation may also be performed in the same principle.

12 is a flowchart illustrating a method of operating a 3D flash memory according to another exemplary embodiment. Hereinafter, the operation method of the 3D flash memory may be performed based on the contents described with reference to FIGS. 10 to 11 , in which the 3D flash memory 900 described with reference to FIG. 9 is the main body.

Referring to FIG. 12 , in step S1210 , the 3D flash memory according to another exemplary embodiment applies a ground voltage to a bit line of a selected string corresponding to a target memory cell to be subjected to a program operation among a plurality of strings. can

Subsequently, in operation S1220 , the 3D flash memory may apply a negative program voltage to a selected word line corresponding to a target memory cell among a plurality of word lines.

In this case, in operation S1220 , the 3D flash memory floats each of the unselected adjacent word lines corresponding to the adjacent memory cells adjacent to the target memory cell among the plurality of word lines, or each of the unselected adjacent word lines A second pass voltage having a value smaller than the first pass voltage - the first pass voltage is a voltage applied to each of the unselected word lines excluding the target word line and the unselected adjacent word lines among the plurality of word lines - is applied By doing so, it is possible to improve a breakdown between the selected word line and the unselected adjacent word lines.

In addition, in step S1220, the 3D flash memory includes adjacent memory cells among the unselected word lines. By applying the first pass voltage to the unselected neighboring word lines corresponding to -, the adjacent memory cells are turned on to a fringing field by the first pass voltage applied to the unselected neighboring word lines. on) can be turned on. In response to the adjacent memory cells being turned on in operation S1230 to be described later, programming in other memory cells may be prevented and a program operation may be performed on the target memory cell.

Accordingly, in step S1230 , the 3D flash memory may perform a program operation in response to a ground voltage being applied to the bit line of the selected string and a negative program voltage being applied to the selected word line.

In more detail, in the 3D flash memory in operation S1230, the potential difference between the negative program voltage applied to the selected word line and the ground voltage applied to the bit line of the selected string including the target memory cell among the plurality of strings A channel may be formed in the string selected through , and a charge or hole may be transferred to the charge storage layer of the target memory cell, thereby performing a program operation on the target memory cell.

Here, in step S1230, the 3D flash memory does not form a channel in each of the unselected strings that do not include the target memory cell among the plurality of strings, so that the memory cells included in each of the unselected strings are programmed. can be prevented

For example, the 3D flash memory applies a negative voltage (eg, -5V) to a bit line connected to the unselected string for an unselected string that shares at least one drain select line DSL with the selected string. It is possible not to form a channel in the unselected string by applying it.

As described above, although the embodiments have been described with reference to the limited embodiments and drawings, various modifications and variations are possible from the above description by those skilled in the art. For example, the described techniques are performed in an order different from the described method, and/or the described components of the system, structure, apparatus, circuit, etc. are combined or combined in a different form than the described method, or other components Or substituted or substituted by equivalents may achieve an appropriate result.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

.

Claims

In the three-dimensional flash memory,

at least one string extending in one direction on a substrate, the at least one string including a channel layer extending in the one direction and a charge storage layer extending in the one direction to surround the channel layer;

at least one selection line vertically connected to an upper end or a lower end of the at least one string; and

a plurality of word lines positioned above or below the at least one selection line and vertically connected to the at least one string

including,

The three-dimensional flash memory,

and performing a hole injection-based memory operation by a Gate Induced Drain Leakage (GIDL) phenomenon in the at least one selection line.
According to claim 1,

The three-dimensional flash memory,

A hole is injected and diffused into the channel layer by a GIDL phenomenon according to a voltage applied to each of the bit line positioned above the at least one string and the at least one selection line. A three-dimensional flash memory, characterized in that it performs a hole injection-based program operation.
3. The method of claim 2,

The three-dimensional flash memory,

A power voltage is applied to a bit line of a target string including a target memory cell, a GIDL voltage having a value smaller than the power voltage is applied to at least one selection line connected to the target string, and a word line corresponding to the target memory cell and performing a selective hole injection-based program operation on the target memory cell based on the GIDL phenomenon in response to the application of the program voltage to the .
4. The method of claim 3,

The three-dimensional flash memory,

A voltage applied to a bit line of a first adjacent string sharing at least one selection line with the target string and a voltage applied to at least one selection line connected to a second adjacent string sharing a bit line with the target string 3D flash, characterized in that a selective hole injection-based program operation is performed so that the hole is not injected into each of the first and second adjacent strings and the hole is injected only in the target string by adjusting Memory.
5. The method of claim 4,

The three-dimensional flash memory,

to prevent the hole from being injected into the first adjacent string and to inject the hole only into the target string by the GIDL phenomenon in response to a voltage having a value smaller than the power supply voltage being applied to the bit line of the first adjacent string 3D flash memory, characterized in that it performs a selective hole injection-based program operation.
5. The method of claim 4,

The three-dimensional flash memory,

In response to the power supply voltage being applied to at least one selection line connected to the second adjacent string, the hole is not injected into the second adjacent string and the hole is injected only into the target string by the GIDL phenomenon. 3D flash memory, characterized in that it performs a selective hole injection-based program operation.
The method of claim 1,

The charge storage layer,

A three-dimensional flash memory, characterized in that it is formed of a ferroelectric material.
8. The method of claim 7,

The ferroelectric material is

Orthorhombic (Orthorhombic) HfO x, Al, of at least one material selected from the group consisting of Zr or Si doped HfO x, PZT has a crystal structure (Pb (Zr, Ti) O 3), PTO (PbTiO 3), SBT (SrBi 2 Ti 2 O 3 ), BLT(Bi(La, Ti)O 3 ), PLZT(Pb(La, Zr)TiO 3 ), BST(Bi(Sr, Ti)O 3 ), barium titanate (BaTiO 3 ) ), P(VDF-TrFE), PVDF, AlO x , ZnO x , TiO x , TaO x or InO x 3D flash memory comprising at least one.
In the three-dimensional flash memory,

A plurality of strings extending in one direction on a substrate - Each of the plurality of strings includes a channel layer extending in the one direction and a charge storage layer extending in the one direction to surround the channel layer, configuring a plurality of memory cells respectively corresponding to a plurality of word lines; and

the plurality of word lines vertically connected to each of the plurality of strings

including,

The three-dimensional flash memory,

and performing the program operation in response to a negative program voltage being applied to a selected word line corresponding to a target memory cell to be programmed among the plurality of word lines. Memory.
10. The method of claim 9,

The three-dimensional flash memory,

A channel is formed in the selected string through a potential difference between the negative program voltage applied to the selected word line and a ground voltage applied to a bit line of a selected string including the target memory cell among the plurality of strings. and performing the program operation on a target memory cell.
10. The method of claim 9,

The three-dimensional flash memory,

Each of the unselected adjacent word lines corresponding to the adjacent memory cells adjacent to the target memory cell among the plurality of word lines is floated, or a first pass voltage to each of the unselected adjacent word lines - the first pass voltage is A voltage applied to each of the unselected word lines except for the target word line and the unselected adjacent word lines among the plurality of word lines is a voltage applied to each of the plurality of word lines; and a breakdown between the unselected adjacent word lines.
12. The method of claim 11,

The three-dimensional flash memory,

An unselected neighboring word corresponding to neighboring memory cells neighboring the neighboring memory cells among the unselected word lines, each of the neighboring memory cells including a neighboring memory cell except for the target memory cell 3D, characterized in that the program operation is performed on the target memory cell by turning on the adjacent memory cells to a fringing field by the first pass voltage applied to the lines. flash memory.
10. The method of claim 9,

The charge storage layer,

A three-dimensional flash memory, characterized in that it is formed of a ferroelectric material.
14. The method of claim 13,

The ferroelectric material is

Orthorhombic (Orthorhombic) HfO x, Al, of at least one material selected from the group consisting of Zr or Si doped HfO x, PZT has a crystal structure (Pb (Zr, Ti) O 3), PTO (PbTiO 3), SBT (SrBi 2 Ti 2 O 3 ), BLT(Bi(La, Ti)O 3 ), PLZT(Pb(La, Zr)TiO 3 ), BST(Bi(Sr, Ti)O 3 ), barium titanate (BaTiO 3 ) ), P(VDF-TrFE), PVDF, AlO x , ZnO x , TiO x , TaO x or InO x 3D flash memory comprising at least one.
10. The method of claim 9,

The three-dimensional flash memory,

3D characterized in that by not forming a channel in each of the unselected strings that do not include the target memory cell among the plurality of strings, the memory cells included in each of the unselected strings are prevented from being programmed. flash memory.