WO2021244014A1 - Procédé de traitement d'interruption et dispositif de traitement d'interruption - Google Patents

Procédé de traitement d'interruption et dispositif de traitement d'interruption Download PDF

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Publication number
WO2021244014A1
WO2021244014A1 PCT/CN2020/140013 CN2020140013W WO2021244014A1 WO 2021244014 A1 WO2021244014 A1 WO 2021244014A1 CN 2020140013 W CN2020140013 W CN 2020140013W WO 2021244014 A1 WO2021244014 A1 WO 2021244014A1
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WIPO (PCT)
Prior art keywords
floating
instruction
interrupt processing
point register
processing unit
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PCT/CN2020/140013
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English (en)
Chinese (zh)
Inventor
王谦智
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珠海格力电器股份有限公司
珠海零边界集成电路有限公司
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Publication of WO2021244014A1 publication Critical patent/WO2021244014A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/3013—Organisation of register space, e.g. banked or distributed register file according to data content, e.g. floating-point registers, address registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Definitions

  • the present disclosure relates to the field of communication technology, and in particular to an interrupt processing method and interrupt processing device.
  • RISC-V CPU risk-five central processing unit
  • GPR general purpose registers
  • FGPR floating-point registers
  • 64bit it has 64 general purpose registers (GPR) and 64 floating-point registers (FGPR); more registers make RISC-V CPUs unable to perform well in scenarios with high real-time requirements .
  • the reason is that when peripheral interrupts come, all general-purpose registers and floating-point registers (32 general-purpose registers, 32 floating-point registers or 64 general-purpose registers, 64 floating-point registers) of the RISC-V CPU must be interrupted by software. On-site protection and restoration. Therefore, the more general-purpose registers and floating-point registers, the longer the RISC-V CPU spends on-site protection and recovery, resulting in poor real-time performance.
  • the present disclosure discloses an interrupt processing method and an interrupt processing device, which are set to ensure that the interrupt processing device meets scenarios with high real-time requirements and expand the application range of the interrupt processing device.
  • an interrupt handling method including:
  • the interrupt processing unit monitors whether the instructions decoded by the decoder involve floating-point registers
  • the interrupt processing unit monitors whether the decoder decodes each time there is a floating-point register that is operated by the currently decoded instruction. Once the interrupt processing unit determines the instruction decoded by the decoder A certain floating-point register is involved, and the interrupt processing unit protects the floating-point register involved in the instruction.
  • the interrupt processing unit monitors whether the instruction decoded by the decoder involves a floating-point register, which specifically includes:
  • the register-specific data storage unit The data of is re-stored in the corresponding floating-point register.
  • the interrupt processing unit monitors whether the instruction decoded by the decoder involves a floating-point register, including:
  • protecting the floating-point register involved in the instruction specifically includes:
  • an embodiment of the present disclosure provides an interrupt processing device, including: an interrupt processing unit, a decoder, and a floating-point register;
  • the decoder is configured to decode the received instruction
  • the floating-point register is set to store data
  • An interrupt processing device provided by an embodiment of the present disclosure is configured to implement the foregoing interrupt processing method, which can achieve the beneficial effects that can be achieved by the foregoing interrupt processing method, and the description will not be repeated here.
  • the interrupt processing unit is specifically set to:
  • the data of the floating-point register involved in the instruction and the identifier of the floating-point register set to index the data are stored in the register-specific data storage unit.
  • the register-specific data storage unit The data of is re-stored in the corresponding floating-point register.
  • the instruction decoded by the decoder is an interrupt instruction
  • the interrupt processing unit is also set to:
  • the interrupt processing unit is further configured as:
  • the interrupt processing unit monitors whether the instruction decoded by the decoder involves a floating-point register, if the register-specific data storage unit has stored data for the floating-point register involved in the interrupt instruction, it will give up The floating-point registers involved in the instructions are protected.
  • the interrupt processing unit includes an automatic push/pull unit and an exception processing unit;
  • the automatic push/pull unit is set to:
  • Monitor whether the instruction decoded by the decoder involves a floating-point register, and when it is determined that the instruction involves a floating-point register, send a request to the exception processing unit, and after receiving feedback from the exception processing unit, send a request to the The floating-point registers involved in the instruction are protected;
  • the exception handling unit is set to:
  • FIG. 1 is a schematic flowchart of an interrupt handling method provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of the flow of S101 in FIG. 1;
  • FIG. 3 is a schematic diagram of the flow of S102 in FIG. 1;
  • FIG. 4 is a schematic flowchart of another interrupt handling method provided by an embodiment of the present disclosure.
  • FIG. 5 is a structural block diagram of an interrupt processing device provided by an embodiment of the disclosure.
  • FIG. 6 is a structural block diagram of another interrupt processing device provided by an embodiment of the disclosure.
  • FIG. 7 is a structural block diagram of another interrupt processing device provided by an embodiment of the disclosure.
  • FIG. 8 is a schematic diagram of a function of an automatic push/pull unit in another interrupt processing device provided by an embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of another function of an automatic stacking/pulling unit in another interrupt processing device provided by an embodiment of the present disclosure.
  • the RISC-V CPU instruction fetcher obtains instructions from the instruction storage unit (the instruction storage unit can be a non-volatile storage medium, such as Embedded Flash (embedded flash memory), or a volatile storage medium such as SRAM (Static Random-Access) Memory, static random access memory), SDRAM (synchronous dynamic random-access memory), or DDR (Double Data Rate, double-rate synchronous dynamic random access memory)); after the instruction is fetched, RISC- V
  • the CPU decoder is responsible for completing the decoding of the fetched instruction, and after the decoding is completed, it is handed over to the executor to execute the instruction.
  • the data storage unit here refers to a volatile storage medium such as SRAM, SDRAM or DDR.
  • the CPU mode of the RISC-V CPU includes normal mode and interrupt mode. When a peripheral interrupt comes, the RISC-V CPU is in the interrupt mode, and the interrupt needs to be processed. However, more registers make the RISC-V CPU unable to perform well in scenarios with high real-time requirements.
  • embodiments of the present disclosure provide an interrupt handling method. As shown in FIG. 1, the method includes the following steps:
  • the interrupt processing unit monitors whether the instruction decoded by the decoder involves a floating-point register
  • the interrupt processing unit includes an Auto-Un/Stacking Unit (AUSU) and an exception processing unit;
  • AUSU Auto-Un/Stacking Unit
  • the function intervention of the automatic push/pull unit only occurs when the RISC-V CPU is in interrupt mode.
  • the automatic push/pull unit monitors whether the instruction decoded by the decoder involves floating The point register, when the automatic push/pull unit determines that the above instruction involves a floating point register, it sends a request to the exception processing unit, and after receiving the feedback from the exception processing unit, protects and restores the floating point register involved in the above instruction.
  • the interrupt processing unit monitors whether the instruction decoded by the decoder involves a floating-point register, which specifically includes the following steps:
  • the interrupt processing unit judges whether the operand in the instruction decoded by the decoder is the operand corresponding to the floating-point register;
  • the instruction is usually composed of 16-bit or 32-bit 0 or 1.
  • the CPU will parse some 0 and 1 to get the opcode and operand, and the operand corresponds to the data and address.
  • the automatic push/pull unit in the interrupt mode monitors whether a floating-point register is operated by the current decoded instruction every time the decoder decodes.
  • the instruction here is determined by the opcode and the operand.
  • Each floating-point There is a one-to-one correspondence between registers and their corresponding operands; the operation here refers to: the instruction involves data reading and writing between the floating-point register and the data storage unit, or whether there is data exchange between the floating-point registers, etc.
  • the interrupt processing unit monitors whether the instruction decoded by the decoder involves a floating-point register in the following manner:
  • the interrupt processing unit determines that the operand in the instruction decoded by the decoder is the operand corresponding to the floating-point register, it is determined that the above-mentioned instruction involves a floating-point register, and the interrupt processing unit performs on-site protection of the floating-point register; if the interrupt processing The unit determines that the operand in the instruction decoded by the decoder is not the operand corresponding to the floating-point register, and then determines that the above-mentioned instruction does not involve floating-point registers, and the interrupt processing unit will not protect the floating-point registers on site, thereby improving real-time sex.
  • the interrupt processing unit protects the floating-point registers involved in the instruction, which specifically includes the following steps:
  • the interrupt processing unit stores the data of the floating-point register involved in the instruction and the identifier of the floating-point register set as index data in the register exclusive data storage unit;
  • the interrupt processing unit Before the interrupt processing unit protects the floating-point register involved in the instruction, it needs to make sure that the register-specific data storage unit does not store data for the floating-point register involved in the interrupt instruction, and determine the register-specific data storage in the interrupt processing unit After the data for the above floating-point register has been stored in the unit, the protection of the same floating-point register involved in another instruction is abandoned.
  • the interrupt processing unit re-stores the data in the floating-point register stored in the register-specific data storage unit into the corresponding floating-point register according to the identifier of the floating-point register set as index data.
  • the interrupt processing unit protects the floating-point registers involved in the instruction
  • the interrupt processing unit detects that the instruction decoded by the decoder is an exit interrupt instruction
  • the interrupt processing unit will be stored in the register dedicated data storage unit
  • the data of the floating-point register in is stored in the corresponding floating-point register according to the floating-point register identifier that is set to index the above-mentioned data.
  • This index identification method facilitates the termination of the interrupt and can quickly restore the data stored in the register-specific data storage unit to the corresponding floating-point register.
  • FIG. 4 is a schematic flowchart of an interrupt handling method provided by an embodiment of the disclosure. As shown in FIG. 4, it includes the following steps:
  • the automatic push/pull unit adopts a preset cycle to detect the central processing unit mode
  • S402 Determine whether the current central processing unit mode is the normal mode, and if so, perform S403; otherwise, perform S404;
  • S404 Judge whether the current central processing unit mode is the interrupt mode, if yes, execute S403 and S405; otherwise, execute S401;
  • the automatic push/pull unit judges whether the instruction decoded by the decoder involves a floating-point register; if so, execute S406; otherwise, continue to execute S405;
  • S407 Determine whether the register-specific data storage unit stores data for the floating-point register involved in the instruction according to the feedback of the exception processing unit; if so, execute S408; otherwise, execute S409;
  • the automatic push/pull unit stores the data of the floating-point register involved in the instruction and the identifier of the floating-point register set as index data in the register exclusive data storage unit;
  • the automatic push/pull unit judges whether the instruction decoded by the decoder is an exit interrupt instruction, if it is, execute S411; otherwise, continue to execute S410;
  • the automatic push/pull unit stores the data of the floating-point register in the register-specific data storage unit according to the identifier of the floating-point register set as index data, and re-stores the data in the register-specific data storage unit into the corresponding Floating-point register;
  • the automatic push/pull unit While executing S405, the automatic push/pull unit adopts a preset cycle to detect and record the interrupt number of the central processing unit;
  • the automatic push/pull unit sends a return request to the exception handling unit, and returns the control right to the exception handling unit.
  • the RISC-V CPU exception number is added in the exception handling unit, such as 18 (the number only needs to be greater than 16); it is responsible for handling when the exception occurs Protect and restore the floating-point registers at the exception site; for example, exception No. 18 is an exception number; the automatic push/pull unit triggers the exception No. 18 in the RISC-V CPU exception handling unit.
  • the exception handling unit will stop executing instructions, and at the same time, transfer control to the automatic push/pull unit, and the automatic push/pull unit will perform on-site protection of the floating-point registers. That is, 18 exceptions do not require system software intervention. All exception handling is completed by the automatic push/pull unit, and only involves the protection and restoration of RISC-V CPU floating-point registers, and does not involve the operation of general-purpose registers. The purpose of this is to improve the real-time response of the system.
  • the automatic push/pull unit will not repeatedly perform field protection on the same floating-point register obtained by the RISC-V CPU decoder.
  • the interrupt number here is the peripheral IP interrupt number in the chip developed based on the RISC-V CPU (the peripheral can be understood as a serial port, USB, I2C, etc.).
  • the value range is generally: 1 to 1024.
  • Each peripheral corresponds to an interrupt number.
  • the software interrupt handling function of RISC-V CPU usually involves the call of multiple functions, for example, function A calls sub-function B, function B calls sub-function C and so on.
  • Function A uses a certain floating-point register (for example, FGPR3), and at the same time, sub-functions B and C may also use FGPR3.
  • interrupt number 4 preempts the execution of interrupt number 5.
  • the RISC-V CPU then executes the interrupt processing function of interrupt number 4. In the interrupt processing function of interrupt number 4, it involves the call of functions D, E, and F. At the same time, it is entirely possible that D, E, and F use FGPR3. Because the automatic push/pull unit detects that the interrupt number has changed from 5 to 4. Then, FGPR3 used in D, E, and F will be saved again.
  • the automatic push/pull unit triggers the number 18 exception return to the exception handling unit, that is, when the floating-point register field protection and recovery work is completed, the RISC-V CPU recovery instruction Control of execution.
  • the above method does not require system software intervention. All exception handling is completed by the automatic push/pull unit, and only involves the protection and restoration of RISC-V CPU floating-point registers, and does not involve the operation of general-purpose registers. At the same time, the automatic push/pull unit will only save part of the floating-point registers used by the interrupt service routine, saving the software the time to save all 32 or 64 floating-point registers; the purpose is to improve the real-time response of the system sex.
  • the decoder 200 is configured to decode received instructions
  • the floating-point register 300 is set to store data
  • the instruction fetcher 400 obtains instructions from the instruction storage unit 500 (the instruction storage unit 500 may be a non-volatile storage medium, such as Embedded Flash, or a volatile storage medium such as SRAM, SDRAM, or DDR );
  • the decoder 200 is responsible for completing the decoding of the fetched instruction, and the executor 600 executes the instruction after the decoding is completed.
  • the content exchange between the general-purpose register or the floating-point register and the data storage unit 700 is completed.
  • the interrupt processing unit 100 is specifically configured as:
  • the interrupt processing unit 100 is further configured as:
  • the interrupt processing unit 100 detects that the instruction decoded by the decoder 200 is an exit interrupt instruction, according to the identifier of the floating-point register 300 set as index data, the data in the register-specific data storage unit is re-stored into the corresponding Floating point register 300.
  • the instruction decoded by the decoder 200 is an interrupt instruction
  • the interrupt processing unit 100 determines that the instruction involves the floating-point register 300, if it is determined that the register-specific data storage unit does not store data for the floating-point register 300 involved in the interrupt instruction, the floating-point register 300 involved in the instruction is protected.
  • the interrupt processing unit 100 monitors whether the instruction decoded by the decoder 200 involves the floating-point register 300, if the register-specific data storage unit has stored data for the floating-point register 300 involved in the interrupt instruction, it will discard the instruction involved The floating-point register 300 is protected.
  • the interrupt processing unit 100 includes an automatic push/pull unit 120 and an exception processing unit 110;
  • the exception handling unit 110 is set to:
  • the RISC-V CPU instruction fetcher 400 fetches instructions from the instruction storage unit 500 (the instruction storage unit 500 may be a non-volatile storage medium, such as Embedded Flash, or a volatile storage medium Such as SRAM, SDRAM, or DDR); after the instruction is fetched, the RISC-V CPU decoder 200 is responsible for completing the decoding of the fetched instruction, and the executor 600 executes the instruction after the decoding is completed. At the same time, according to the result of executing the instruction, the content exchange between the general-purpose register or the floating-point register and the data storage unit 700 is completed.
  • the data storage unit 700 here refers to a volatile storage medium such as SRAM, SDRAM, or DDR.
  • the embodiment of the present disclosure provides a computer storable medium on which a computer program is stored, and when the program is executed by a processor, the steps of the above interrupt processing method are implemented.
  • the storage medium may be a non-volatile storage medium.
  • the embodiments of the present disclosure can be provided as a method, a system, or a computer program product. Therefore, the present disclosure may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing equipment to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction device.
  • the device implements the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.
  • These computer program instructions can also be loaded on a computer or other programmable data processing equipment, so that a series of operation steps are executed on the computer or other programmable equipment to produce computer-implemented processing, so as to execute on the computer or other programmable equipment.
  • the instructions provide steps for implementing functions specified in a flow or multiple flows in the flowchart and/or a block or multiple blocks in the block diagram.

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Abstract

La présente divulgation se rapporte au domaine des communications. Sont divulgués, un procédé de traitement d'interruption et un dispositif de traitement d'interruption. Le procédé de traitement d'interruption consiste : à surveiller, par une unité de traitement d'interruption, si une instruction décodée par un décodeur est associée à un registre à virgule flottante ; et lorsqu'il est déterminé que l'instruction concerne un registre à virgule flottante, à protéger, par l'unité de traitement d'interruption, le registre à virgule flottante auquel l'instruction est associée. L'unité de traitement d'interruption surveille s'il existe un registre à virgule flottante exploité par l'instruction actuellement décodée à chaque fois que le décodeur effectue un décodage, l'exploitation se référant ici à la lecture et à l'écriture de données entre le registre à virgule flottante et une unité de stockage de données, ou s'il existe un échange de données entre des registres à virgule flottante ; et une fois que l'unité de traitement d'interruption détermine que l'instruction décodée par le décodeur est associée à un certain registre à virgule flottante, l'unité de traitement d'interruption protège le registre à virgule flottante. Par conséquent, l'unité de traitement d'interruption effectue uniquement une protection de champ sur un registre à virgule flottante utilisé, et des registres à virgule flottante n'ont pas besoin d'être stockés lorsque certaines fonctions de traitement d'interruption ne concernent pas les opérations des registres à virgule flottante, ce qui permet d'améliorer les performances en temps réel.
PCT/CN2020/140013 2020-06-04 2020-12-28 Procédé de traitement d'interruption et dispositif de traitement d'interruption WO2021244014A1 (fr)

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CN111782269B (zh) * 2020-06-04 2023-12-12 珠海格力电器股份有限公司 一种中断处理方法及中断处理设备
CN115080122A (zh) * 2022-07-22 2022-09-20 飞腾信息技术有限公司 处理器、用于保存和恢复上下文数据的装置、方法及芯片

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101739368A (zh) * 2008-11-07 2010-06-16 中兴通讯股份有限公司 一种中断加速装置和中断处理系统
CN109710312A (zh) * 2018-12-13 2019-05-03 华东计算技术研究所（中国电子科技集团公司第三十二研究所） 基于risc-v指令集的实时中断处理方法、装置及工控处理器
CN110221861A (zh) * 2019-05-31 2019-09-10 常州市常河电子技术开发有限公司 一种cpu新型寄存器体系结构及其中断处理方法
CN111782269A (zh) * 2020-06-04 2020-10-16 珠海格力电器股份有限公司 一种中断处理方法及中断处理设备

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5852726A (en) * 1995-12-19 1998-12-22 Intel Corporation Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner
JP2004157636A (ja) * 2002-11-05 2004-06-03 Renesas Technology Corp データ処理装置
CN101221492B (zh) * 2008-01-22 2010-07-21 西北工业大学 浮点异常处理装置以及用该装置进行异常处理的方法
CN100555225C (zh) * 2008-03-17 2009-10-28 中国科学院计算技术研究所 一种支持x86虚拟机的risc处理器装置及方法
GB2471138B (en) * 2009-06-19 2014-08-13 Advanced Risc Mach Ltd Handling integer and floating point registers during a context switch
US8336017B2 (en) * 2011-01-19 2012-12-18 Algotochip Corporation Architecture optimizer
CN102521042A (zh) * 2011-12-16 2012-06-27 中船重工（武汉）凌久电子有限责任公司 基于哈佛结构dsp的快速正文切换方法
CN110007964A (zh) * 2019-03-15 2019-07-12 芯来科技(武汉)有限公司 用于risc-v架构的中断系统

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101739368A (zh) * 2008-11-07 2010-06-16 中兴通讯股份有限公司 一种中断加速装置和中断处理系统
CN109710312A (zh) * 2018-12-13 2019-05-03 华东计算技术研究所（中国电子科技集团公司第三十二研究所） 基于risc-v指令集的实时中断处理方法、装置及工控处理器
CN110221861A (zh) * 2019-05-31 2019-09-10 常州市常河电子技术开发有限公司 一种cpu新型寄存器体系结构及其中断处理方法
CN111782269A (zh) * 2020-06-04 2020-10-16 珠海格力电器股份有限公司 一种中断处理方法及中断处理设备

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