WO2021233638A1

WO2021233638A1 - Transmission stage and method for generating a differential voltage between bus lines

Info

Publication number: WO2021233638A1
Application number: PCT/EP2021/060399
Authority: WO
Inventors: Steffen Walker; Sebastian STEGEMANN
Original assignee: Robert Bosch Gmbh
Priority date: 2020-05-22
Filing date: 2021-04-21
Publication date: 2021-11-25
Also published as: DE102020206410A1; CN115552852A; EP4154483A1

Abstract

The invention relates to a transmission stage for generating a differential voltage between a first and a second bus line of a bus of a bus system based on differential voltage signals, in particular for a controller area network bus system. The transmission stage comprises a first and a second transmission block for generating voltage signals on the first and the second bus line; wherein the first transmission block has multiple first current paths arranged in parallel that have first resistor elements, and wherein the second transmission block has multiple second current paths arranged in parallel that have second resistor elements. The current paths are each switchable between a conductive and a nonconductive state. There is provision for a control circuit that is designed to switch each of the first and second current paths within a switching period, which begins with a change in the transmission signal, at respective predetermined times. Additionally, a corresponding method is presented.

Description

description

Transmission stage and method for generating a differential voltage between

Bus lines

The present invention relates to a transmission stage and a method for generating a differential voltage between a first and a second Buslei device of a bus of a bus system based on differential voltage signals, in particular a CAN bus system.

State of the art

In bus systems that transmit information in the form of voltage signals, the timing behavior or timing is an essential factor that limits the bit rate that can be used in practice. Here, requirements are placed on the length of a bit as well as on the transition in the voltage signal between the voltage states that represent the two possible values of a bit. For example, as the bit rate increases, the length of a bit must be within ever narrower limits and accordingly the transition between the voltage states takes place faster, so that steeper edges in the voltage signal are required, which in turn can lead to an increase in conducted electromagnetic emissions, which are negative affect the achievable bit rate.

These effects particularly affect bus systems in which the signals are transmitted in the form of voltage differences between two conductive wires, the so-called bus lines, because there, on the one hand, two voltage signals have to be precisely timed and, in addition, the two voltages applied to the bus lines are changed at the same time must, ie the voltage curves on both bus lines must be symmetrical. An example of such a bus system is the CAN bus (CAN stands for Con- troller Area Network). There, within the framework of the CAN-FD-SIC specification (FD: Flexible Data rate; SIC: Signal Improvement Capability), a usable bit rate of 5 Mbit / s is aimed for, ie a typical bit length of 200 ns, with a variation of the bit length in the range should be from -10 ns to +10 ns. Here, an increase in the edge steepness, caused by inductances in the bus lines, leads in particular to so-called "ringing" in the bus, ie to oscillations in the differential voltage signal, which additionally increases conducted emissions.

Disclosure of the invention

According to the invention, a transmission stage and a method for generating a differential voltage between bus lines of a bus of a bus system based on differential voltage signals with the features of the independent claims are proposed. Advantageous refinements are the subject matter of the subclaims and the description below.

The invention makes use of the measure of gradually switching the voltage level on a bus line by means of iterative connection of several parallel-connected current paths in each of which a resistor or resistor element is angeord net. According to the invention, it is possible to precisely control the timing of the slope of the differential voltage, so that timing requirements can be met. The currents flowing through the individual current paths are precisely defined by the resistors. A high bit rate is thus achieved with low conducted emissions at the same time.

The transmission stage for generating a differential voltage between a first and a second bus line of a bus of a bus system based on differential voltage signals, in particular for a controller area network bus system, comprises a first transmission block for generating a voltage signal on the first bus line corresponding to a transmission signal, and a second transmission block for generating a voltage signal on the second bus line corresponding to the transmission signal (that is, in other words, a first transmission block for transmitting a transmission signal to a first bus line of the bus and a second transmission block for transmitting the transmission signal to a second bus line of the bus). The first transmission block has several between one Connection to a first reference potential and a connection to the first bus line, first current paths connected in parallel, each having a first resistance element and each switchable between a conductive and a non-conductive state (more precisely, switchable in both directions, i.e. back and forth switchable). The second transmission block has a plurality of second current paths connected in parallel between a connection to a second reference potential and a connection to the second bus line, each of which has a second resistance element and which can be switched between a conductive and a non-conductive state. A control circuit is provided which is set up to switch each of the first and second current paths at a predetermined point in time within a switching time period beginning with a change in the transmission signal, the first and second current paths depending on a direction of the change Transmit signal can be switched from the conductive to the non-conductive or from the non-conductive to the conductive state.

A first current path and a second current path each preferably form a pair, the electrical resistance of the first current path and the second current path of a pair deviating from one another by a maximum of 2%, preferably by a maximum of 1%, more preferably by a maximum of 0.5%.

This adjustment of the electrical resistance can essentially be done by adjusting the resistance elements, i.e. the ratio of the resistance values of the two resistance elements in a (current path) pair must be within predetermined, as narrow as possible limits. Preferably, however, the electrical resistances of other elements in the current path, such as switching elements, etc., are also taken into account. Due to the equalization of the first and second current paths in each pair, the voltages on the two bus lines can be generated symmetrically to one another, which leads to a further reduction in conducted emissions.

The current paths of a pair are preferably also matched to one another in terms of their electromagnetic properties. Furthermore, the circuit layout can be designed accordingly, with the two resistance elements of a pair of current paths lying next to one another, for example. be arranged, overall this results in a nested arrangement of the resistance elements in which the first and second resistance elements alternate. The resistance elements of a pair also preferably have the same temperature dependency.

The control circuit is preferably set up in such a way that the times at which the first current paths are switched are each different from one another, and that the times at which the second current paths are switched are each different from one another. This has the advantage that the edges of the voltage signals on the two bus lines can be specifically shaped. For example, the times can be regularly spaced from one another.

Furthermore, the control circuit is preferably set up to switch the first and the second current path, which form the respective pair, at the same point in time for at least one pair. This is more preferably the case for all couples. Each of the pairs is switched over, so to speak, at a respective predetermined point in time. The times for the first and second current paths in different pairs can be different from one another, i.e. different pairs have different switching times. In this way, in particular together with matched resistance elements, mutually symmetrical edges of the two voltages on the first and second bus lines can be achieved.

Each first current path preferably comprises a first switching element which is connected in series with the first resistance element and is configured to switch the current path between the conductive and the non-conductive state, and every second current path a second switching element which is connected in series with the second resistance element and is set up to switch the current path between the conductive and the non-conductive state. Further preferred are the first and the second switching elements transistors, in particular special metal oxide field effect transistors (MOSFETs), the first switching elements being most preferably p-channel MOSFETs of the enhancement type and the second switching elements n-channel MOSFETs of the enhancement type. In this case, the switching elements, in particular the transistors or MOSFETs, a pair of current paths in their electromagnetic properties are also matched to one another, that is, to be aligned with one another.

The control circuit preferably comprises first control elements which control the first switching elements to switch over according to the predetermined times of the first current paths, and second control elements which control the second switching elements to switch over according to the predetermined times of the second current paths; wherein the predetermined times are preferably determined by time constants of the first and second control elements.

For this purpose, the first control elements are preferably each connected to one of the first switching elements and the second control elements are each connected to one of the second switching elements. This is especially designed so that a first and second control element is assigned to each of the first and second switching elements, i.e. there is a 1: 1 assignment.

More preferably, the first control elements are connected in series, so that an output signal of a control element serves as an input signal for the first control element following in the series and as a control signal for the first switching element to which it is connected, and the second control elements are used connected in series, so that an output signal of a second control element serves as an input signal for the second control element following in the series and as a control signal for the second switching element to which it is connected. The output signal of the last control element in the respective row clearly only serves as a control signal for the corresponding switching element. The input signal for the first control elements in the row is the transmission signal or a transmission signal modified by a transmission signal control element in such a way that it is suitable for activating the control elements, i.e. the respective first control element in the row, if this is not directly possible, for example. By arranging the control elements in rows, a simple implementation of the circuit is possible.

In connection with the goal of reducing emissions on the bus lines, it is preferable to switch between (with regard to the order in which the first current paths are switched) the first current path that is switched first. and the first current path, which is switched last, has a first current path, the first resistance element of which has a lowest resistance value, the course (according to the order in which the first current paths are switched) of the resistance values of the first current paths is monotonous, in particular strictly monotonic, ie between the first current path, which is switched first, and the first current path, the first resistance element of which has the lowest resistance value, the resistance values fall (strictly) monotonic, and between the first current path, its first resistance element is one Has the smallest resistance value, and the first current path, which is switched last, the resistance values increase (strictly) monotonically. The same should then apply analogously to the second current paths.

Preferably, a smallest first and a smallest second resistance element are located in the first and second current paths that are switched at times that are in a middle third of the switching period; wherein preferably a largest first and a largest second resistance element of those resistance elements that lie in first and second current paths that are switched in a temporally first third of the switching period, and / or a largest first and largest second resistance element of those resistance elements that lie in first and second current paths, which are switched in the last third of the switching time span, each being greater by a factor k than the smallest first and the smallest second resistance element, the factor k being at least 2, preferably at least 4 . Furthermore, the transmission blocks and / or the control circuit are preferably set up in such a way that a size of the first and second resistance elements, in accordance with their sequence determined by the predetermined points in time, initially decreases down to the smallest first and the smallest second resistance element and then increases again. the decrease and the increase preferably taking place monotonically, more preferably strictly monotonically. For example, the decrease and / or the increase can take place linearly. Also, viewed over time, the resistance values of the resistance elements can follow the course of a cosine function from 0 to 2p, which is suitably normalized, scaled and shifted in the value range, with the function ons values are taken at regularly spaced support points corresponding to the number of first and second current paths.

Overall, it can be achieved in this way that relatively small currents are switched on or off at the beginning and end of the switching time span and relatively large currents are switched on or off in the middle of the switching time span. This is advantageous because it avoids excessive current increases, which would lead to line-related emissions.

Further advantages and embodiments of the invention emerge from the description and the accompanying drawings.

The invention is illustrated schematically in the drawing using exemplary embodiments and is described below with reference to the drawing.

Brief description of the drawings

Figure 1 shows the basic structure of a bus system;

FIG. 2 shows the course of a transmission signal and a corresponding bus differential voltage signal;

FIG. 3 shows a transmission stage according to a preferred embodiment of the invention; and

FIG. 4 shows an illustration of current levels of several current stages. Embodiments of the invention

FIG. 1 shows the structure of a bus system based on differential voltage signals, in particular a CAN bus system. The bus system 6 comprises several bus users 8_1, 8_2, ..., 8_m, which are connected to two bus lines 22, 24 of a bus 20 of the bus system are connected and communicate with each other via the bus. The bus users use differential voltages for this purpose between the two bus lines that are generated and read out by means of transceivers. In the figure, one of the bus users 8_1, more precisely its transceiver, comprises, for example, a transmission stage 10 according to the present invention; however, several or all bus users can also comprise a transmission stage according to the present invention. The bus lines 22, 24 are connected to one another via terminating resistors 26a, 26b, which represent the central impedance of the bus system.

In FIG. 2, a transmission signal 2 and a corresponding differential voltage signal 4 for a CAN bus are shown by way of example. In the figure, both the profile of the voltage V _T * _{D of} the transmission signal and the profile of the differential voltage V _{Diff of} the corresponding differential voltage signal 4 on the bus, ie the profile of the voltage difference between two lines of the bus, are plotted against time t. Individual bits in the transmission signal are coded by corresponding voltage levels, e.g. a logic "1" corresponds to a positive voltage level 2a other than zero and a logic "0" corresponds to a voltage level 2b of 0 V. The differential voltage signal on the bus is therefore 1: 1 Relationship, ie the signal on the bus also has two different differential voltage levels which correspond to the levels of the transmission signal, a high bus differential voltage level not necessarily having to correspond to a high transmission signal voltage level. In particular, the differential voltage can be obtained in a symmetrical manner by voltages on the bus line, ie the voltage on one bus line increases and the voltage on the other bus line decreases in a symmetrical manner.

In the case of the CAN bus, a distinction is made between a "recessive" 4a and a "dominant" 4b state. In the recessive state 4a, the two bus lines are at the same voltage level (nominally 2.5 V relative to ground), ie the differential voltage is 0 V, while in the dominant 4b state there is a differential voltage of 2 V (nominally as CAN_H designated first bus line a voltage of 3.5 V and on the second bus line designated as CAN_L a voltage of 1.5 V). On the CAN bus, a recessive state corresponds to a logical "1" and a dominant state corresponds to a logical "0". Due to the delay until a transmission stage provides the voltages on the two bus lines, the differential voltage signal 4 is shifted in time relative to the transmission signal 2

FIG. 3 shows a circuit for a transmission stage or transmitter stage according to a preferred embodiment of the invention. The circuit or the sensor stage 10 has a connection 12 for a transmission signal TxD and, based on the transmission signal, generates a differential voltage signal for a bus 20.

The circuit comprises a first transmission block 40 and a second transmission block 60, with which a differential voltage between a first bus line 22 and a second bus line 24 of the bus 20 can be generated in accordance with the transmission signal TxD. The transmission blocks are arranged between reference potentials and the bus lines. Here, the first transmission block 40 has a connection 42 for (or to) a first reference potential and a connection 44 for the first bus line 22 and the second transmission block 40 has a connection 62 for a second reference potential and a connection 64 for the second bus line tion 24 on. Typically, the first reference potential is a voltage source or supply voltage (e.g. CAN_SUPPLY) of the bus system and the second reference potential is a ground or a ground potential (e.g. CAN_GND). In particular, the transmission stage can be supplied with a current via these connections at a voltage corresponding to the reference potentials.

The connections 42, 62 for the reference potentials and the connections to the bus lines 44, 64 are connected in both transmission blocks by a plurality of current paths connected in parallel or arranged in parallel. The first transmission block 40 here comprises several parallel-connected first current paths 46_1, 46_2, ... 46_n, which connect the connection 42 for the first reference potential and the connection 44 for the first bus line 22 and the first resistance elements or resistors, 48_1 , 48_2, ..., 48_n, ie there is a resistance element in each current path. The second transmission block 60 comprises several parallel-connected second current paths 66_1, 66_2, ... 66_n, which connect the connection 62 for the second reference potential and the connection 64 for the second bus line 24 and the second resistance elements 68_1, 68_2, ..., 68_n have. By way of example, three current paths are drawn in each case and any further current paths are indicated by dots ""; In general, any number greater than or equal to 2 is possible on the first or second current paths. The same number of current paths is provided in both transmission blocks.

In each case a first and a second current path form or define a pair. In each pair, the two current paths are expediently matched or matched to one another, with at least the resistance elements being matched to one another in terms of their resistance values, so what is known as "matching" of the resistances takes place. The relative deviation of the resistance values of the two resistance elements of a pair of current paths is preferably less than a predetermined limit value. Likewise, it is preferably possible for the ratio of the two resistance elements of a pair of current paths to deviate from a predetermined value only within predetermined limits. Furthermore, the current paths of a pair can be adjusted in that they are arranged side by side in the circuit layout (not shown in the figure), so that disturbances (e.g. electromagnetic or thermal fluctuations) affect both current paths in the same way.

The first and the second current paths are set up in such a way that they can be switched, i.e. switched back and forth, between a conductive and a non-conductive state. For this purpose, first switching elements 50_1, 50_2, ..., 50_n (in the first current paths) and second switching elements 70_1, 70_2, ..., 70_n (in the second current paths) are provided in the current paths, so that each current path is a switching element includes in series with the respective resistance element in the current path.

In the figure, the switching elements are designed, for example, as transistors, in particular metal oxide field effect transistors (MOSFETs). It is preferred to use the enrichment type p-channel MOSFETs in the first current paths (ie, normally-off) and the enrichment type n-channel MOSFETs in the second current paths. The transistors (MOSFETs) are arranged in such a way that the respective current path is connected to the drain and source connection, i.e. the current path runs over the drain-source connection and is is controlled (operated in the saturation range) when a suitable voltage is applied to the gate.

The individual current paths are switched between the conductive and the non-conductive state at predetermined times, which are within a switching period, depending on the transmission signal TxD by means of a control circuit 80 provided for this purpose, which controls the current paths or the switching elements. Here, the first current paths are switched over at predetermined first times, which are preferably different from one another, and the second current paths are switched over at predetermined second times, which are preferably different from one another. The first and the second points in time are preferably the same for current paths which form a pair. The first and second time points each designate points in time within the switching time span, i.e. times relative to the switching time span. The switching period begins with a change in the transmission signal, i.e. the control circuit is set up accordingly. The first and second points in time represent time intervals for changing the transmission signal. Depending on the direction of the change in the transmission signal, whether the transmission signal is transitioned from a high to a low voltage level or vice versa, the current paths are either switched from the non-conductive to the conductive State or switched from the conductive to the non-conductive state. The relative direction of the changes in the transmission signal level and the differential voltage level depends on the correspondence between the voltage levels of the transmission signal and the differential voltage levels, which is specified by the bus system specifications. With the CAN bus, for example, the current paths are switched from the non-conductive to the conductive state when the transmission signal changes from a high to a low level, and from the conductive to the non-conductive state when the transmission signal changes from a low changes to a high level (see FIG. 2). The reverse correspondence can also be implemented in another bus system.

In FIG. 3, control elements or driver elements 52_1, 52_2, ..., 52_n; 72_1, 72_2, ..., 72_n includes. It should be noted here that the control circuit may include components specific to either the first or the second Transmission blocks are, and which can accordingly also be understood as elements of the transmission blocks, as in Figure 3. The control circuit is therefore not necessarily a separate arrangement from the transmission blocks, but elements of the transmission blocks can represent components of the control circuit. More specifically, there are first control elements 52_1, 52_2, ..., 52_n in the first transmission block 40 and second control elements 72_1, 72_2, ..., in the second transmission block 60.

72_n are provided, which are each connected to a different first or second switching element and which control the control elements. In FIG. 3, a control element is provided for each current path or for each switching element; To use control elements that control multiple current paths or switching elements, in particular also control elements that control current paths or switching elements in both the first and the second transmission block. If the switching elements are designed as transistors, in particular as MOSFETs, the switching elements can be gate drivers, i.e. control elements which, depending on an input signal, generate an output signal with which a sufficient current and a sufficient voltage are provided, to switch the transistor (MOSFET), when applied to the gate of the transistor, from the blocking to the non-blocking state. The resistance (between the drain and source of the transistor) should be as small as possible in the connected or controlled state (i.e. in the conductive state, especially in the saturation range). In particular, in the non-blocking state, the drain-source resistance should be negligibly small compared to the resistance of the resistance element in the corresponding current path, so the transistors or MOSFETs are designed accordingly. If this is not the case, the drain-source resistance should be taken into account together with the resistance element; alternatively, in the sense of an equivalent circuit diagram, the transistors can be imagined as ideal switches without resistance and a possibly given drain-source resistance at the resistance value of Consider resistance elements.

The first control elements (gate driver) 52_1, 52_2, ..., 52_n are connected in series in the first transmission block, so that the output signal of a control element controls both a respective switching element (MOSFET) and as an input signal for the one in the series The next control element is used. the Second control elements 72_1, 72_2, 72_n are arranged analogously in the second transmission block 60. With this arrangement, the first and second points in time are determined by time constants of the control elements, ie by the time that elapses until an input signal of a control element is converted into an output signal. Control elements following in the row are activated with a time delay corresponding to the sum of the time constants of the control elements present, so that the switching elements are activated one after the other with increasing time intervals from the original input signal, which essentially corresponds to the transmission signal. In other words, it takes a certain period of time until all current paths are switched over, with the individual current paths being switched in sequence at certain times within this period of time. This time span should be selected so that the edge time required for transmission in accordance with the bus specification is observed for the voltage signal generated on the bus lines.

The first control elements in the two rows (52_1 and 72_1) can in principle be controlled directly by the transmit signal TxD, i.e. directly connected to the connection 12 for the transmit signal. Alternatively, as shown in FIG of the first control elements 52_1, 52_2, ..., 52_n and the second control elements 72_1, 72_2, ..., 72_n is suitable, for example, suitable voltage levels are generated. Due to the arrangement of the first and second control elements in a row, only the inputs of the first control elements in the two rows (52_1 and 72_1) are connected to the output of the transmission signal control element 14.

It should be noted that the precise design of the control circuit, ie its specific components, is not essential to the invention. Deviations from the preferred embodiment shown in FIG. 3 are possible. The control circuit only needs to be set up to open the first and second current paths at predetermined times or time intervals Depending on the transmission signal, to switch between conductive and non-conductive and vice versa.

A polarity diode and / or a cascode can also be provided in each of the transmission blocks. These are switched in series with the current paths. In the first transmission block 40, a first polarity diode 54 and / or a first cascode 56, preferably a p-channel cascode, can be arranged between the parallel-connected first current paths 46_1, 46_2, ..., 46_n and the connection 44 for the first bus line will. Analogously to this, in the second transmission block 60, between the second current paths 66_1, 66_2, ..., 66_n connected in parallel and the connection 64 for the second bus line, a second polarity diode 74 and / or a second cascode 76, preferably an n-channel cascode , to be ordered. With a CAN bus, the cascodes enable maximum nominal parameters to be adhered to (voltage at CAN_H and CAN_L from -27 V to +40 V). A gate of the cascodes is connected to the first or second reference potential.

The function of the transmission stage 10 is briefly described below. When the transmission signal TxD changes, the first and second current paths are switched one after the other, corresponding to the first and second points in time, within the switching time span from the conductive to the non-conductive state or from the non-conductive to the conductive state. In the conductive state, with a given supply voltage (by means of the reference potentials), a current flows through each of the current paths corresponding to the resistance value of the resistance element in the respective current path. The sum of the currents of the individual first and second current paths results in a total current that flows over the bus lines. Between the two bus lines 22, 24 there is a resistor or bus resistor 26 with a value R _Bus , which is given, for example, in a CAN bus system by two 120 ohm terminating resistors between the bus lines, so that a bus resistance R _BUS of 60 ohms results. If a total current I flows through the current paths and over the bus lines connected to the connections for the bus lines, _{a voltage drop occurs across the bus resistor R BUS} , that is, a differential voltage U _Dif r = R _BUS I arises between the bus lines between the bus lines is determined by the current I. This stream in turn is determined by the total resistance of the first and second resistors connected in parallel.

The first and second current paths define, so to speak, the first and second current stages in accordance with the respective resistance values of the resistance elements. A (total) current stage is defined by each pair of a first and a second current path; a current stage is therefore the current that flows through a pair. The sum of the current levels results in the (total) current which flows between the connections 44 and 64 to the bus lines via the bus 20, i.e. the bus lines 22, 24, and which determines the differential voltage. The current paths are switched on or off in sequence at certain times, i.e. switching times, within the switching time span, so that the change in the current intensity over time and thus the change in the differential voltage over time, i.e. the slope of the difference voltage, can be precisely controlled. Due to the equalized current paths, in particular the equalized resistors, and accordingly the first and second current levels matched to one another, the edge profiles of the voltage signals on the two bus lines are symmetrical to one another.

It is advantageous if the current paths that are switched on and off at the beginning and at the end of the switching period cause relatively small current levels, and the current paths that are switched on and off in a central region of the switching period are relatively large Cause current levels. As a result, an increase in current that would lead to conducted emissions can be avoided, especially when the current paths are switched off.

The size of the current steps, ie the current per step, preferably changes in accordance with the sequence of their (switching) times in the switching time period, with a largest current step at a point in time in the middle third of the switching time period. According to the sequence of the (switching) times, the change in the size of the current levels includes an increase up to the largest current level and then a decrease. The increase and / or the decrease are preferably monotonous, more preferably strictly monotonous. The current of the largest current stage is preferably greater by a factor k than the current of a ner smallest current level in the first third of the switching time span and / or as the current of a smallest current level in the last third of the switching time span, where the factor k is preferably at least 2, more preferably at least 4, the factor k should not be greater than 20 be.

Such a change is shown by way of example in FIG. 4, in which the current I, per current stage is shown as a function of the number i of the current stage. Here, 12 current levels are shown as an example, with the 6th current level being the one with the highest current. Starting from the 1st current stage h to the 6th current stage \ &, the current I, first increases and then from this to the 12th current stage 112, this takes place in a strictly monotonic manner.

Since the currents of the current stages are inversely proportional to the resistance values of the resistance elements, this means, in relation to the first and second resistance elements of the current paths, that the resistance values of resistance elements that are switched over in a middle time range of the switching period are relatively small to the resistance values of resistance elements that are switched in areas at the beginning and / or end of the switching period. A first largest and a second largest resistance element of those resistance elements that are in the current paths that are switched in the first third of the switching period, and / or a first largest and second largest resistance element of those resistance elements that are in the current paths that are in the temporal The last third of the switching period are switched, are preferably larger by a factor of k than a smallest first and a smallest second resistance element, which are located in current paths that are switched in the middle third of the switching period. What has been said above applies again to the factor k. Statements about the size of the resistance elements are to be understood as statements about the resistance values of the resistance elements. The increase and decrease in the resistance elements (or their resistance values) is preferably analogous to the increase and decrease in the current levels.

Claims

Expectations

1. Transmission stage (10) for generating a differential voltage between a first and a second bus line (22, 24) of a bus (20) of a bus system (6) based on differential voltage signals, in particular for a controller area network bus system, comprising a first transmission block (40) for generating a voltage signal on the first bus line (22) in accordance with a transmission signal (TxD), and a second transmission block (60) for generating a voltage signal on the second bus line (24) in accordance with the transmission signal (TxD); wherein the first transmission block (40) has a plurality of first current paths (46_1, 46_2, 46_n) connected in parallel between a connection (42) to a first reference potential (CAN_SUPPLY) and a connection (44) to the first bus line (22), each of which has a first resistance element

(48_1, 48_2, ..., 48_n) and which can each be switched between a conductive and a non-conductive state, the second transmission block (60) having several between a connection (62) to a second reference potential (CAN_GND) and a connection (64) has second current paths (66_1, 66_2, ..., 66_n) connected in parallel to the second bus line (24), each of which has a second resistance element (68_1, 68_2, ..., 68_n) and each of which is between a conductive and a non-conductive state can be switched over; wherein a control circuit (80) is provided which is set up to switch each of the first and second current paths at a predetermined point in time within a switching time period beginning with a change in the transmission signal, the first and the second current paths depending on a direction the change in the transmission signal from the conductive to the non-conductive or from the non-conductive to the conductive state.

2. Transmission stage according to claim 1, wherein a first current path and a second current path form a pair, the electrical resistance of the first current path and the second current path of a pair and / or of the first and the second resistance element of the pair by a maximum of 2%, preferably deviate from one another by a maximum of 1%, more preferably by a maximum of 0.5%.

3. Transmitter stage according to claim 2, wherein the control circuit (80) is set up to switch for at least one pair, preferably for all pairs, the first and the second current path, which form the respective pair, at the same time.

4. Transmission stage according to one of the preceding claims, wherein the first current paths (46_1, 46_2, ..., 46_n) comprise first switching elements (50_1, 50_2, ..., 50_n) which are in series with the first resistance elements (48_1, 48_2 , ..., 48_n) are arranged and which are set up to switch the first current paths between the conductive and the non-conductive state; and wherein the second current paths (66_1, 66_2, ..., 66_n) comprise second switching elements (70_ 1, 70_2, ..., 70_n) which are in series with the second resistance elements (68_1, 68_2, ..., 68_n ) are arranged and which are set up to switch the first current paths between the conductive and the non-conductive state.

5. Transmission stage according to claim 4, wherein the first and the second Schaltele elements (50_1, 50_2, ..., 50_n; 70_1, 70_2, ..., 70_n) transistors, preferably metal oxide field effect transistors, MOSFETs are; wherein the first switching elements are preferably p-channel MOSFETs of the enhancement type and the second switching elements are n-channel MOSFETs of the enhancement type.

6. Transmission stage according to one of claims 4 or 5, wherein the control circuit (80) comprises first control elements (52_1, 52_2, ..., 52_n) which control the first switching elements (50_1, 50_2, ..., 50_n), accordingly to switch over the predetermined times of the first current paths, and wherein the control circuit (80) comprises second control elements (72_1, 72_2, ..., 72_n) which control the second switching elements (70_ 1, 70_2, ..., 70_n), corresponding - accordingly switch over the predetermined times of the second current paths; wherein the predetermined times are preferably determined by time constants of the first and second control elements.

7. Transmission stage according to claim 6, wherein the first control elements (52_1, 52_2,

52_n) each with one of the first switching elements (50_1, 50_2,

50_n) are connected, and the second control elements (72_1, 72_2,

72_n) are each connected to one of the second switching elements (70_1, 70_2, 70_n).

8. Transmission stage according to one of claims 6 or 7, wherein the first control elements (52_1, 52_2, ..., 52_n) are connected in series, so that an output signal from a control element as an input signal for the first control element and next in the series serves as a control signal for the first switching element to which it is connected; and wherein the second control elements (72_1, 72_2, ..., 72_n) are connected in series, so that an output signal of a second control element is used as an input signal for the second control element following in the series and as a control signal for the second switching element with which it is connected, serves.

9. Transmission stage according to one of the preceding claims, wherein in each case a smallest first and a smallest second resistance element lie in first and second current paths which are switched at times which lie in a middle third of the switching period; wherein preferably a largest first and a largest second resistance element, which are in first and second current paths, which are switched in a temporal first third of the switching time period, and / or a largest first and a largest second resistance element in the first and second current paths, respectively those that are switched in the last third of the switching period are each a factor k greater than the smallest first and the smallest second resistor element, the factor k being at least 2, preferably at least 4.

10. transmission stage according to claim 9, wherein sizes of the first and second Wi derstandselemente according to their by the predetermined times decrease in a certain sequence, in each case initially up to the smallest first and the smallest second resistance element and then increase again, the decrease and the increase preferably taking place monotonically, more preferably strictly monotonously.

11. Transmission stage according to one of the preceding claims, wherein the first Sen deblock (40) comprises a first polarity diode (54) and / or a first cascode (56) which are connected in series with the first current paths, and wherein the second transmission block ( 60) comprises a second reverse polarity diode (74) and / or a second cascode (76), which are switched in series with the second current paths.

12. A method for generating a differential voltage between a first and a second bus line of a bus of a bus system based on differential voltage signals, in particular a controller area network (CAN) bus system, with several in response to a change in a transmission signal (TxD) re parallel first current paths between a first reference potential and the first bus line at predetermined times within a switching period and several parallel second current paths between the second bus line and a second reference potential at predetermined times within the switching period, connected or disconnected depending on the direction of the change will; wherein the currents in the first and second current paths are determined by first and second resistance elements (48_1, 48_2, ..., 48_n; 68_1, 68_2, ..., 68_n), respectively.

13. The method according to claim 12, which is carried out using a transmission stage according to any one of claims 1 to 11.