WO2021227419A1

WO2021227419A1 - Output circuit of power amplifier

Info

Publication number: WO2021227419A1
Application number: PCT/CN2020/129808
Authority: WO
Inventors: 张勇
Original assignee: 苏州远创达科技有限公司
Priority date: 2020-05-12
Filing date: 2020-11-18
Publication date: 2021-11-18
Also published as: CN111510085B; CN111510085A

Abstract

An output circuit of a power amplifier, comprising: an output network connected to an active device. The output network comprising an impedance matching network and a bias balance network; the bias balance network is connected to an output end of an active device chip by means of a first bonding wire group; the impedance matching network is connected to the output end of the active device chip by means of a second bonding wire group; the bias balance network comprises a first grounding capacitor connected to a transmission line, and the first bonding wire group is connected to one end of the transmission line; an equivalent inductor between the output end of the active device chip and the first grounding capacitor and a drain-source parasitic capacitor of the active device constitute a first resonance loop. The transmission line, the bonding wire groups, and the drain-source parasitic capacitor of the active device form a resonance loop, thereby balancing the drain-source parasitic capacitor of the active device, reducing the number of elements of a matching network, and reducing the size space and the cost of an amplifier.

Description

Output circuit of power amplifier

Technical field

The invention relates to a power amplifier circuit, in particular to an output circuit of a power amplifier.

Background technique

The radio frequency power amplifier is the key component of the transmitter end in the communication base station system. Competition in the communications market is becoming more and more fierce, and new requirements are put forward for key component power amplifiers: such as large bandwidth, high power, high efficiency, and miniaturization.

At the same time, the radio frequency power amplifier in the communication base station system generally has a relatively large power level, such as a few watts to a few hundred watts. Therefore, the physical gate length of the active transistor in this type of power amplifier is relatively large, which leads to large parasitic parameters of the transistor, such as drain-source capacitance. Since power amplifiers generally need to be matched and output to a 50Ohm system, a larger drain-source capacitance will bring great difficulty to the output matching of the power amplifier, especially in the case of large bandwidth. At the same time video bandwidth will also be affected. In view of these technical difficulties, there are generally some approaches to both:

1. Generally, the industry will use the high-pass balance network of bond wire inductance cross combination and chip capacitance to balance the drain-source capacitance. As shown in Figures 1 and 2, the chip capacitance Cb is connected between the output network and the active transistor chip D. To balance the parasitic parameters of the active transistor, the chip capacitance Cb is connected to the active transistor chip D through the bonding wire group Lb, and the active transistor chip D is connected to the output network through the bonding wire group Ld. The output network includes the impedance matching network IM and the bias The bias network and the impedance matching network IM are connected together by a transmission line TL. The bias network includes a capacitor Cd and a capacitor Cv. The capacitor Cd is used for radio frequency decoupling, and the capacitor Cv is used for enhancing the video bandwidth. Figure 1 and Figure 2 are two different packaging forms. Figure 1 is a package form that uses an unpackaged die-loaded module (chip-on-carrier). Figure 2 is a traditional packaging form with chip capacitance Cb and active transistors. The chip D is arranged on the flange F, the chip capacitor Cb and the active transistor chip D are packaged as a module or device 10. One end of the bonding wire group Ld is connected to the active transistor chip D, and the other end is connected to the pin P1. Pin P1 is connected to other circuits, the output network is generally a PCB board, and pin P1 is soldered on the PCB board.

2. A low-pass matching network is used to absorb the drain-source capacitance. As shown in Figures 3 and 4, the chip capacitance Cb is connected between the output network and the active transistor chip D to absorb the parasitic parameters of the active transistor. The chip capacitance Cb The active transistor chip D is connected through the bonding wire group Ld1, and the output network is connected to the output terminal of the chip capacitor Cb through the bonding wire group Ld2. The structure of the output network is the same as that in FIG. 1. Figure 3 and Figure 4 are two different packaging forms. Figure 3 is a package form that uses a chip-on-carrier module without a package. Figure 4 is a traditional packaging form with chip capacitance Cb and active transistors. The chip D is arranged on the flange F. The chip capacitor Cb and the active transistor chip D are packaged into a module or device 20. One end of the bonding wire group Ld2 is connected to the active transistor chip D, and the other end is connected to the pin P1. Pin P1 is connected to other circuits, the output network is generally a PCB board, and pin P1 is soldered on the PCB board.

The above two implementation methods have certain limitations, and good performance cannot be achieved in some specific occasions. In addition, the above two implementation methods currently have the following defects:

Figures 1 and 2 adopt the high-pass balance network method of bonding wire inductance cross combination and chip capacitor, which is limited by physical space layout and the power capacity of bonding wire. It is generally suitable for occasions with relatively small inductance, usually much less than 1nH. . This makes its scope of application greatly limited. At the same time, due to the large inductance between the chip capacitor to the ground and the microfarad (uF) power filter capacitor on the drain bias line, the video bandwidth of the power amplifier is narrowed. In addition, the cross combination of bond wire inductance produces a large mutual inductance, which has an impact on the bandwidth and efficiency of the power amplifier.

In Figures 3 and 4, the low-pass matching network is used to absorb the drain-source capacitance. The bandwidth performance is not good, and the performance of the power amplifier is very limited. At the same time, there is a large inductance between the first grounding capacitor and the microfarad (uF) power filter capacitor on the drain bias line, which leads to a narrower video bandwidth of the power amplifier.

Summary of the invention

In view of the above-mentioned technical problems, the purpose of the present invention is to provide an output circuit of a power amplifier, which utilizes a transmission line and a bonding wire group to form a resonant circuit with the drain-source parasitic capacitance of the active device, thereby balancing the drain of the active device. The function of source parasitic capacitance reduces the components of the matching network and reduces the size space and cost of the amplifier.

In order to solve these problems in the prior art, the technical solution provided by the present invention is:

An output circuit of a power amplifier, including:

An output network connected to the active device, the output network including an impedance matching network and a bias balance network;

The bias balance network is connected to the output terminal of the active device chip through the first bonding wire group;

The impedance matching network is connected to the output terminal of the active device chip through the second bonding wire group;

The bias balance network includes a first grounding capacitor connected to a transmission line, and the first bonding wire group is connected to one end of the transmission line;

The equivalent inductance between the output terminal of the active device chip and the first grounding capacitor and the drain-source parasitic capacitance of the active device form a first resonant loop.

In a preferred technical solution, the transmission line is further connected to a second grounding capacitor, and the other end of the transmission line is connected to a power supply.

In a preferred technical solution, the equivalent inductance between the output terminal of the active device chip and the second grounding capacitor, the drain-source parasitic capacitance of the active device and the equivalent capacitance of the first grounding capacitor form a second resonant loop.

In a preferred technical solution, there are multiple bias balance networks, and the multiple bias balance networks are respectively connected to the output terminals of the active device through different bonding wire groups.

In a preferred technical solution, the first bonding wire group and the second bonding wire group are arranged in separate spaces.

The preferred technical solution includes a plurality of active devices, and two adjacent active devices share a bias balance network.

Compared with the solutions in the prior art, the advantages of the present invention are:

1. Utilize the transmission line and bonding wire group to form a resonant circuit with the drain-source parasitic capacitance of the active device, thereby balancing the drain-source parasitic capacitance of the active device, reducing the components of the matching network, and reducing the size of the amplifier Space and cost. It can improve the RF bandwidth, video bandwidth and efficiency of the power amplifier.

2. In this structure, the transmission line is also used as a drain-level power supply line, which can be directly connected to the filter capacitor, which further expands the video bandwidth.

3. The bias balance network and impedance matching network are connected separately from the output terminal of the active transistor and the connected bond wire groups do not cross each other, which greatly reduces the mutual inductance of the traditional bond wire inductance balance network and further improves the RF bandwidth of the amplifier And efficiency.

Description of the drawings

The present invention will be further described below in conjunction with the accompanying drawings and embodiments:

Figure 1 is a diagram of the output circuit architecture of a traditional Qualcomm balanced network in a packaged form;

Figure 2 is a diagram of the output circuit architecture of the power amplifier of the traditional Qualcomm balanced network in another form of packaging;

Figure 3 is a diagram of the output circuit architecture of the power amplifier of a traditional low-pass absorption network in a packaged form;

Fig. 4 is a diagram of the output circuit structure of the power amplifier of the traditional low-pass absorption network in another form of packaging;

5 is a diagram of the output circuit structure of a packaged power amplifier according to the present invention;

FIG. 6 is a structure diagram of an output circuit of a power amplifier in another package form of the present invention;

FIG. 7 is a structure diagram of an output circuit of a packaged power amplifier according to another embodiment of the present invention;

FIG. 8 is a structure diagram of an output circuit of another packaged power amplifier according to another embodiment of the present invention;

FIG. 9 is a structure diagram of a power amplifier output circuit according to another embodiment of the present invention;

FIG. 10 is a simulation result of the S parameter amplitude of the optimal impedance matching of the circuit architecture of the present invention;

FIG. 11 is a simulation result of S parameter amplitude within the video bandwidth of the circuit architecture of the present invention and the original circuit architecture;

FIG. 12 is the S parameter phase simulation result in the video bandwidth of the circuit architecture of the present invention and the original circuit architecture.

Detailed ways

The above solution will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are used to illustrate the present invention and not to limit the scope of the present invention. The implementation conditions used in the examples can be further adjusted according to the conditions of specific manufacturers, and implementation conditions not specified are usually conditions in routine experiments.

In the first embodiment, as shown in Figs. 5 and 6, an output circuit of a power amplifier includes:

The output network OMN connected with active devices, the active devices may include electron tubes, transistors, integrated circuits, etc. In this embodiment, an active transistor is taken as an example for description.

The output network OMN includes an impedance matching network IM and a bias balance network BCN1.

The bias balance network BCN1 includes a first grounding capacitor Cb1 connected to the transmission line BL1. The transmission line BL1 can be a microstrip line, a strip line or a coplanar waveguide line, etc., and one end of the transmission line BL1 is connected to the active through the first bonding wire group Lb The output terminal of the transistor chip D.

One end of the impedance matching network IM is connected to the output end of the active transistor chip D through the second bonding wire group Ld, and the other end of the impedance matching network IM serves as the radio frequency output port RFout.

Figure 5 and Figure 6 are two different packaging forms. Figure 5 is a package form that uses a chip-on-carrier module without a package. Figure 6 is a traditional packaging form. The active transistor chip D is set in On the flange F and packaged as a module or device 30, one end of the first bonding wire group Lb is connected to the active transistor chip D, the other end is connected to the pin P1, and one end of the second bonding wire group Ld is connected to the active transistor chip D. The source transistor chip D is connected, the other end is connected to pin P2, the output network OMN is generally a PCB board, the pin P1 is soldered to the transmission line BL1 on the PCB board, and the pin P2 is soldered to the connection end of the impedance matching network IM on the PCB board. .

In another embodiment, the first bonding wire group Lb and the second bonding wire group Ld are in separate spaces and are physically separated. The bonding wire groups do not cross each other, reducing the mutual inductance of the two groups of wires. .

The equivalent inductance between the output terminal of the active transistor chip D and the first grounding capacitor Cb1 and the drain-source parasitic capacitance of the active device form a first resonant circuit. So as to balance the drain-source parasitic capacitance of the active transistor. The equivalent inductance between the output terminal of the active transistor chip D and the first grounding capacitor Cb1 includes the equivalent inductance formed by the transmission line BL1 in the bias balance network BCN1 and the first bonding wire group Lb.

The first grounding capacitor Cb1 is used as the radio frequency grounding, and at the same time, it plays a role in radio frequency decoupling. The capacitance value of the first grounding capacitor Cb1 is generally between 1pF-999pF according to the specific application.

The resonant point of the resonant circuit that balances the drain-source parasitic capacitance of the active transistor is calculated by the following formula:

Where f1 is the resonance point frequency, L _eb is the integrated equivalent inductance from the output terminal of the active transistor D to the first pair of ground capacitance Cb1, and the equivalent inductance is the first bond wire group Lb and the first pair of ground capacitance The equivalent inductance formed by the transmission line of Cb1, C _ds is the drain-source parasitic capacitance of the active transistor D.

In another embodiment, the transmission line BL1 is also connected to the second grounding capacitor Cv1, and the other end of the transmission line BL1 is connected to the power supply Vdd.

The second grounding capacitor Cv1 serves as the ground for the video bandwidth range to enhance the video bandwidth and at the same time play a role in power supply filtering. The capacitance of the second grounding capacitor Cv1 is usually chosen to be of the order of uF.

The equivalent inductance between the output terminal of the active transistor chip D and the second grounding capacitor Cv1, the drain-source parasitic capacitance of the active transistor and the equivalent capacitance of the first grounding capacitor Cb1 form a second resonant loop.

The resonance point of the resonant tank within the video bandwidth is calculated by the following formula:

Where f2 is the resonance point frequency, L _ev end comprehensive equivalent inductance between the second pair of capacitors Cv1 active D chip output transistor, a first equivalent inductance Lb and the bonding wire connected to the second group to ground equivalent inductance capacitor Cv1 transmission line formed, C _e comprehensive parasitic capacitance Cb1 equivalent capacitance of the first capacitor is grounded drain-source of the active transistor.

Since the bonding wire group Lb and the transmission line BL1 are used in the architecture of the present invention to jointly balance the drain-source parasitic capacitance of the active transistor, and the transmission line BL1 also serves as a drain-level power supply line, it can be directly connected to the filter capacitor Cv1, which reduces both The circuit size is reduced, the matching components are reduced, and the video bandwidth is expanded. At the same time, it overcomes the shortcomings that the traditional bond wire inductance balance network is difficult to realize in some occasions, such as the application scenarios where large inductance and large current are required, but the area is limited. . In addition, since the bias balance network and the impedance matching network are separately connected from the output terminal of the active transistor and the connected bond wire groups Lb and Ld do not cross each other, the mutual inductance of the traditional bond wire inductance balance network is greatly reduced. Improve the RF bandwidth and efficiency of the amplifier.

In the second embodiment, multiple bias balance networks may be provided, and the multiple bias balance networks are respectively connected to the output terminals of the active device through different bonding wire groups. As shown in Figures 7 and 8, it includes two bias balance networks BCN1 and BCN2.

The bias balance network BCN1 includes a section of transmission line BL1 and two grounded capacitors Cb1 and Cv1 connected to the transmission line BL1. The output terminal of the active transistor chip D is connected to one end of the bias balance network BCN1 through the first bonding wire group Lb1, and the other end of the bias balance network BCN1 is connected to the power supply Vdd.

The bias balance network BCN2 includes a section of transmission line BL2 and two grounding capacitors Cb2 and Cv2 connected to the transmission line BL2. The output terminal of the active transistor chip D is connected to one end of the bias balance network BCN2 through the first bonding wire group Lb2, and the other end of the bias balance network BCN2 is connected to the power supply Vdd.

Figures 7 and 8 are two different packaging forms. Figure 7 is a package form that uses a chip-on-carrier module without a package. Figure 8 is a traditional packaging form. The active transistor chip D is set in On the flange F and packaged as a module 40, one end of the first bonding wire group Lb1 is connected to the output terminal of the active transistor chip D, the other end is connected to the pin P1, and one end of the second bonding wire group Ld is connected to the active transistor The output terminal of chip D, the other end is connected to pin P2, one end of the first bonding wire group Lb2 is connected to the output terminal of active transistor chip D, and the other end is connected to pin P3. The output network OMN is generally a PCB board. The pin P1 is soldered to the transmission line BL1 on the PCB board, the pin P2 is soldered to the connection end of the impedance matching network IM on the PCB board, and the pin P3 is soldered to the transmission line BL2 on the PCB board.

The position of the impedance matching network IM is not limited, and it can be set between the bias balance network BCN1 and the bias balance network BCN2, or it can be set at the uppermost position or the lowermost position.

In another embodiment, the first bonding wire group Lb1, Lb2 and the second bonding wire group Ld are in separate spaces and are physically separated. The bonding wire groups do not cross each other, reducing the two groups of wires. Mutual inductance.

The functional principle of the bias balance network BCN2 is the same as that of the BCN1. The capacitance values of the grounding capacitors Cb1 and Cb2 can be equal or unequal, and the capacitance values of the grounding capacitors Cv2 and Cv1 can be equal or unequal. Bias balance network BCN2 and BCN1, the parallel connection of the two can further enhance the video bandwidth and increase the maximum tolerance of the power supply current.

Where f1 is the resonance point frequency, L _eb is the integrated equivalent inductance after the parallel connection between the output terminal of the active transistor chip D and the first pair of ground capacitors Cb1 and Cb2. The integrated equivalent inductance includes the first bonding wire group Lb1 and Lb2 The parallel inductance of the transmission line connected to the first pair of ground capacitance Cb1 and the parallel inductance of the transmission line connected to the first pair of ground capacitance Cb2, C _ds is the drain-source parasitic capacitance of the active transistor.

Where f2 is the resonance point frequency, L _ev end after the equivalent inductance connected in parallel between the integrated capacitor Cv1 and Cv2 second transistor chip D of an active output inductor comprises a first comprehensive equivalent group bonding wire Lb1 and Lb2 a shunt inductance connected to the second ground capacitor Cv1 and a transmission line connected to the capacitance of the second pair of transmission lines Cv2 shunt inductance, C _e is the active transistor and ground capacitance parasitic capacitance Cb1 and Cb2 parallel with the first pair of drain-source After the comprehensive equivalent capacitance.

In the framework of the present invention, the bonding wire group Lb and the transmission line BL1/BL2 are used to jointly balance the drain-source parasitic capacitance of the active transistor, and the transmission line BL1/BL2 also serves as a drain-level power supply line and can be directly connected to the filter capacitor Cv1/Cv2 .

In the third embodiment, when there are multiple amplifiers, such as in a Doherty circuit application, two adjacent active devices can share a bias balance network. The following uses two amplifiers as an example for description, as shown in Figure 9. As shown, one amplifier is expanded on the basis of Fig. 8. The two amplifiers have the same structure, specifically including two active devices D1 and D2, and adjacent active devices D1 and D2 share a bias balance network BCN2.

The active transistor chip D1 is arranged on the flange F1 and is packaged as a module 40. One end of the first bonding wire group Lb1 is connected to the output terminal of the active transistor chip D1, and the other end is connected to the pin P1. The second bonding wire One end of the group Ld1 is connected to the output terminal of the active transistor chip D1, and the other end is connected to the pin P2. One end of the first bonding wire group Lb2 is connected to the output terminal of the active transistor chip D1, and the other end is connected to the pin P3. The pin P1 is connected to the bias balance network BCN1, the pin P2 is connected to the impedance matching network IM1, the other end of the impedance matching network IM1 is used as the radio frequency output port RFout1, and the pin P3 is connected to the bias balance network BCN2.

The active transistor chip D2 is arranged on the flange F2 and packaged as a module 50. One end of the first bonding wire group Lb3 is connected to the output terminal of the active transistor chip D2, and the other end is connected to the pin P4, and the second bonding wire One end of the group Ld2 is connected to the output terminal of the active transistor chip D2, and the other end is connected to the pin P5. One end of the first bonding wire group Lb4 is connected to the output terminal of the active transistor chip D2, and the other end is connected to the pin P6. The pin P4 is connected to the bias balance network BCN2, the pin P5 is connected to the impedance matching network IM2, the other end of the impedance matching network IM2 is used as the radio frequency output port RFout2, and the pin P6 is connected to the bias balance network BCN3. The bias balance network BCN3 includes a section of transmission line BL3 and two grounding capacitors Cb3 and Cv3 connected to the transmission line BL3. The other end of the transmission line BL3 is connected to the power supply Vdd.

In another embodiment, the transmission line BL2 of the bias balance network BCN2 can be branched from another connection end to connect to the pin P4.

The bias balance network BCN1, the bias balance network BCN2, the bias balance network BCN3, the impedance matching network IM1, and the impedance matching network IM2 can be used as an output network OMN, and the output network OMN is generally a PCB board.

Perform simulation tests on the architecture of the present invention. Fig. 10 uses a power amplifier at 3.5 GHz as a simulation example to show the optimal impedance matching S-parameter amplitude simulation results using the architecture of the present invention. From the results, the matching parameter frequency is below -25dB. The range reaches 800MHz.

FIG. 11 is a simulation result of the S parameter amplitude within the video bandwidth of the circuit architecture of the present invention and the original circuit architecture. The results show that the frequency point (1.4 GHz) of the lowest amplitude point of the architecture of the present invention is much higher than the frequency point (0.7 GHz) of the lowest amplitude point of the original circuit architecture.

FIG. 12 is the S parameter phase simulation result in the video bandwidth of the circuit architecture of the present invention and the original circuit architecture. The result shows that the phase change of the architecture of the present invention is much flatter than that of the original circuit architecture. Therefore, the architecture of the present invention greatly broadens the working bandwidth and video bandwidth of the power amplifier.

It should be understood that the above-mentioned specific embodiments of the present invention are only used to exemplarily illustrate or explain the principle of the present invention, and do not constitute a limitation to the present invention. Therefore, any modifications, equivalent substitutions, improvements, etc. made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. In addition, the appended claims of the present invention are intended to cover all changes and modifications that fall within the scope and boundary of the appended claims, or equivalent forms of such scope and boundary.

Claims

An output circuit of a power amplifier, including:

An output network connected to an active device, the output network including an impedance matching network and a bias balance network, characterized in that:

The bias balance network is connected to the output terminal of the active device chip through the first bonding wire group;

The impedance matching network is connected to the output terminal of the active device chip through the second bonding wire group;

The bias balance network includes a first grounding capacitor connected to a transmission line, and the first bonding wire group is connected to one end of the transmission line;

The equivalent inductance between the output terminal of the active device chip and the first grounding capacitor and the drain-source parasitic capacitance of the active device form a first resonant loop.
The output circuit of the power amplifier according to claim 1, wherein the transmission line is further connected to a second grounding capacitor, and the other end of the transmission line is connected to a power supply.
The output circuit of the power amplifier according to claim 2, wherein the equivalent inductance between the output terminal of the active device chip and the second grounding capacitance is related to the drain-source parasitic capacitance of the active device and the first grounding capacitance. The equivalent capacitance of the capacitor forms the second resonant circuit.
The output circuit of the power amplifier according to claim 1, wherein there are a plurality of bias balancing networks, and the plurality of bias balancing networks are respectively connected to the output terminals of the active device through different bonding wire groups.
The output circuit of the power amplifier according to claim 1, wherein the first bonding wire group and the second bonding wire group are arranged in separate spaces.
The output circuit of the power amplifier according to claim 1, characterized in that it comprises a plurality of active devices, and two adjacent active devices share a bias balance network.