WO2021204301A1 - 码字同步方法、接收器、网络设备及网络系统 - Google Patents

码字同步方法、接收器、网络设备及网络系统 Download PDF

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Publication number
WO2021204301A1
WO2021204301A1 PCT/CN2021/086736 CN2021086736W WO2021204301A1 WO 2021204301 A1 WO2021204301 A1 WO 2021204301A1 CN 2021086736 W CN2021086736 W CN 2021086736W WO 2021204301 A1 WO2021204301 A1 WO 2021204301A1
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Prior art keywords
test data
bits
data blocks
value
synchronization
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PCT/CN2021/086736
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English (en)
French (fr)
Inventor
任浩
何向
王心远
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华为技术有限公司
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Priority claimed from CN202010424884.9A external-priority patent/CN113517949A/zh
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP21784978.5A priority Critical patent/EP4123932A4/en
Priority to AU2021251993A priority patent/AU2021251993A1/en
Priority to BR112022020489A priority patent/BR112022020489A2/pt
Priority to JP2022561604A priority patent/JP2023521133A/ja
Priority to CA3178683A priority patent/CA3178683A1/en
Priority to KR1020227037787A priority patent/KR20220160102A/ko
Priority to MX2022012665A priority patent/MX2022012665A/es
Publication of WO2021204301A1 publication Critical patent/WO2021204301A1/zh
Priority to US17/961,000 priority patent/US20230023776A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/08—Speed or phase control by synchronisation signals the synchronisation signals recurring cyclically
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H04L1/0063—Single parity check
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines

Definitions

  • This application relates to the field of communications, and in particular to a codeword synchronization method, receiver, network equipment and network system.
  • FEC Forward Error Correction
  • block codes can be divided into block codes and convolutional codes according to different processing methods of information sequences.
  • block codes it can be further subdivided into linear block codes and non-linear block codes.
  • Linear block codes are relatively simple to implement in encoding and decoding, and are used in the media access control of the physical layer (physical layer) and the data link layer (data link layer) in the Open System Interconnection Model (OSI) of Ethernet.
  • OSI Open System Interconnection Model
  • the (media access control) sub-layer is widely used.
  • code Word synchronization codeword synchronization
  • frame synchronization frame synchronization
  • AM alignment marker
  • This application provides a self-synchronizing codeword synchronization method, receiver, and network equipment, which are used to solve the technical problem of adding additional data in the AM synchronization solution.
  • this application provides a codeword synchronization method.
  • the method includes: step one, receiving a data sequence, the data sequence including a plurality of bits; step two, determining candidate bits in the data sequence, and the candidate bit is included in the plurality of bits; step Third, determine a synchronization position according to the candidate bit, where the synchronization position is used to indicate the starting position of the codeword in the data sequence.
  • This method is executed by the receiving device in the network. Through this method, the technical effect of high-precision codeword synchronization of the data stream at the receiving end can be realized without inserting additional data in the data stream at the sending end, and the synchronization performance can achieve higher reliability.
  • the step three includes: verifying the candidate bit, and when the verification is successful, determining that the position of the candidate bit is the synchronization position.
  • At least one second test data block is divided in the data sequence according to the candidate bit, and the position of the candidate bit is the beginning of the at least one second test data block.
  • the starting position; the characteristic value of the at least one second test data block is verified, and when the verification is successful, it is determined that the position of the candidate bit is the synchronization position.
  • verifying the characteristic value of the at least one second test data block includes: sequentially accumulating the characteristic value of each second test data block in the at least one second test data block to obtain The accumulated value, until the accumulated value meets the synchronization condition, the verification is successful.
  • the cumulative value of the characteristic value is the number of second test data blocks determined to be correct codewords in the at least one second test data block
  • the synchronization condition is the cumulative The value is greater than or equal to the synchronization threshold
  • the characteristic value is the number of all-zero sequences in the check sequence
  • the synchronization condition is that the cumulative value is greater than or equal to the synchronization threshold; or, the characteristic value is the zero element in the check sequence
  • the synchronization condition is that the cumulative value is greater than or equal to the synchronization threshold; or, the characteristic value is the number of error-correctable test data blocks, and the synchronization condition is that the cumulative value is greater than or equal to the synchronization threshold; or
  • the characteristic value is the number of test data blocks with the same re-check digit and the original check digit, and the synchronization condition is that the cumulative value is greater than or equal to a synchronization threshold; wherein the length of the test data block is n bits, The first k bits of the test data block are information
  • verifying the characteristic value of the at least one second test data block includes: adding the characteristic values of all the second test data blocks in the at least one second test data block to obtain The total value, when the total value meets the synchronization condition, the verification is successful.
  • the total value of the characteristic value is the number of second test data blocks determined to be the correct codeword in the at least one second test data block, and the total value of the characteristic value is The number of second test data blocks determined to be error code words in the at least one second test data block, and the synchronization condition is that the total value is less than or equal to a synchronization threshold; or the characteristic value is a check sequence
  • the synchronization condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value is the number of non-all-zero sequences in the check sequence, and the synchronization condition is that the total value is less than Or equal to the synchronization threshold; or, the characteristic value is the number of zero elements in the check sequence, and the synchronization condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value is the non-zero element in the check sequence
  • the synchronization condition is that the total value is less than or equal to the synchronization threshold; or, the characteristic value is the characteristic value
  • the position of the candidate bit is used as the synchronization position.
  • multiple observation bits are selected from the data sequence; and the candidate bit is selected from the multiple observation bits.
  • the selecting the candidate bits from the multiple observation bits includes: determining multiple sets of first test data blocks from the data sequence according to the multiple observation bits, Wherein, each group of first test data blocks in the plurality of sets of first test data blocks includes at least one first test data block, and the position of each observation bit in the plurality of observation bits is the first test data block in the plurality of sets of first test data blocks. The starting position of each group of first test data blocks in the test data block; according to the characteristic values of the plurality of groups of first test data blocks, one observation bit is selected from the plurality of observation bits as the candidate bit.
  • the selecting an observation bit from the plurality of observation bits as the candidate bit according to the characteristic values of the multiple sets of first test data blocks includes: sequentially judging the Whether the characteristic value of each group of first test data blocks in the multiple groups of first test data blocks meets the candidate condition, until it is determined that the characteristic value of a group of first test data blocks satisfies the candidate condition; Observation bits corresponding to the first set of test data blocks of the condition are used as the candidate bits.
  • the characteristic value of the set of first test data blocks is the total value of the number of all-zero sequences in the check sequences of all the first test data blocks in the set of first test data blocks .
  • the alternative condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value of the set of first test data blocks is the calibration of all the first test data blocks in the set of first test data blocks.
  • the total value of the number of non-zero sequences in the test sequence, the alternative condition is that the total value is less than or equal to the synchronization threshold; or, the characteristic value of the set of first test data blocks is the set of first test The total value of the number of zero elements in the check sequence of all the first test data blocks in the data block, and the alternative condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristics of the set of first test data blocks
  • the value is the total value of the number of non-zero elements in the check sequence of all the first test data blocks in the set of first test data blocks, and the alternative condition is that the total value is less than or equal to the synchronization threshold; or
  • the characteristic value of the set of first test data blocks is the total value of the number of error-correctable test data blocks in all the first test data blocks in the set of first test data blocks, and the candidate condition is the total value Greater than or equal to the synchronization threshold; or, the characteristic value of the set of first test data blocks is the total value
  • the cumulative value of the number of error-correctable test data blocks in a test data block, and the alternative condition is that the cumulative value is greater than or equal to the synchronization threshold; or, the characteristic value of the first set of test data blocks is the one The cumulative value of the number of test data blocks in the first X first test data blocks in the group of first test data blocks that have the same recheck digit as the original check digit, where the alternative condition is that the cumulative value is greater than or equal to a synchronization threshold;
  • the length of the test data block is n bits
  • the first k bits of the test data block Is the information bit
  • the last nk bits of the test data block are the original check bit
  • the recheck bit is obtained based on the information bit
  • the length of the recheck bit is nk bits
  • Said k and said X are integers.
  • the selecting one observation bit from the plurality of observation bits as the candidate bit according to the characteristic values of the plurality of sets of first test data blocks includes: comparing the plurality of observation bits. For the characteristic values of each group of first test data blocks in the group of first test data blocks, an observation bit corresponding to a group of first test data blocks whose characteristic value is an extreme value is used as the candidate bit.
  • the characteristic value is the number of all-zero sequences in the check sequence, and the extreme value is the maximum value; or the characteristic value is the number of non-all-zero sequences in the check sequence, The extreme value is the minimum value; or, the characteristic value is the number of zero elements in the check sequence, and the extreme value is the maximum value; or, the characteristic value is the number of non-zero elements in the check sequence, so The extreme value is the minimum value; or, the characteristic value is the number of error-correctable test data blocks, and the extreme value is the maximum value; or the characteristic value is the number of uncorrectable test data blocks, and the extreme The value is the minimum; or, the characteristic value is the number of test data blocks with the same re-check digit and the original check digit, and the extreme value is the maximum; or, the characteristic value is the re-check digit and the original check digit.
  • the extreme value is the minimum; wherein the length of the test data block is n bits, the first k bits of the test data block are information bits, and the The last nk bits are the original check bits, the recheck bits are obtained based on the information bits, the length of the recheck bits is nk bits, and the n and k are integers.
  • the selecting multiple observation bits from the data sequence includes: selecting one bit from the data sequence at intervals of T bits as the observation bit, where T is An integer greater than zero; or, one bit is selected from each interval of L*n+T bits in the data sequence as the observation bit, where L is the number of test data blocks in the interval, and the number of test data blocks is The length is the n bits, and the L and T are integers greater than zero.
  • the data sequence is a modulated signal
  • the data sequence includes a plurality of modulation symbols
  • the selecting a plurality of observation bits from the first data includes: For every interval of T modulation symbols in the data sequence, the start bit of the modulation symbol is selected as the observation bit, and the T is an integer greater than zero; or, every interval from the data sequence is L*m+T Modulation symbols, the start bit of the modulation symbol is selected as the observation bit, the L is the number of spaced test data blocks, the length of the test data block is the m modulation symbols, the L and the T are integers greater than zero.
  • the number of observation bits is P
  • the P is a positive integer
  • the length of the codeword is the P bits.
  • the determining the candidate bit in the data sequence includes determining the candidate bit in the first subsequence
  • the determining the candidate bit in the data sequence includes dividing at least one second test data block in the second subsequence according to the candidate bit, the first subsequence and The second subsequence is included in the data sequence, and the second subsequence is the same, partly the same or different from the first subsequence.
  • the method further includes: step four, in response to the data sequence being in the unlocked state, determining the update synchronization position of the data sequence.
  • the determining the update synchronization position of the data sequence includes: re-executing the step two and the step three, and using the synchronization position determined in the re-executed step three as the update Sync location.
  • the method further includes: dividing a plurality of synchronization codewords from the data sequence according to the synchronization position, and the synchronization The position is the starting position of the multiple synchronization code words; the characteristic values of the multiple synchronization code words are verified, and when the verification fails, it is determined that the data sequence is in the unlocked state.
  • verifying the characteristic values of the multiple synchronization codewords includes: sequentially accumulating the characteristic values of each synchronization codeword in the multiple synchronization codewords to obtain an accumulated value, until the When the accumulated value meets the lock-out condition, the verification fails.
  • the characteristic value is the number of non-all-zero sequences in the check sequence, and the lock-out condition is that the cumulative value is greater than or equal to the synchronization threshold; or, the characteristic value is check The number of non-zero elements in the sequence, the loss-of-lock condition is that the cumulative value is greater than or equal to the synchronization threshold; or, the characteristic value is the number of uncorrectable codewords, and the loss-of-lock condition is that the cumulative value is greater than Or equal to the synchronization threshold; or, the characteristic value is the number of codewords whose recheck bits are different from the original check bits, and the lock-out condition is that the cumulative value is greater than or equal to the synchronization threshold; wherein, the codeword The length of the codeword is n bits, the first k bits of the codeword are information bits, the last nk bits of the codeword are the original check bits, and the recheck bits are obtained based on the information bits. The length of the re-check bit is
  • verifying the characteristic values of the multiple synchronization codewords includes: adding the characteristic values of all the synchronization codewords in the multiple synchronization codewords to obtain a total value, when the When the total value meets the lock-out condition, the verification fails.
  • the characteristic value is the number of all-zero sequences in the check sequence, and the lock-out condition is that the total value is less than or equal to the synchronization threshold; or, the characteristic value is the check sequence
  • the number of non-all-zero sequences in the field, the lock-out condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value is the number of zero elements in the check sequence, and the lock-out condition is the total value Less than or equal to the synchronization threshold; or, the characteristic value is the number of non-zero elements in the check sequence, and the lock-out condition is that the total value is greater than or equal to the synchronization threshold; or, the characteristic value is an error-correctable code
  • the loss-of-lock condition is that the total value is less than or equal to the synchronization threshold; or, the characteristic value is the number of uncorrectable codewords, and the loss-of-lock condition is that the total value is greater than or equal to the synchronization threshold
  • the data sequence is a linear block code.
  • the present application provides a communication device that executes the first aspect or the method in any one of the possible implementation manners of the first aspect.
  • the network device includes a unit for executing the method in the first aspect or any one of the possible implementation manners of the first aspect.
  • the present application provides a communication device, which includes a processor, a communication interface, and a memory.
  • the communication interface can be a transceiver.
  • the memory may be used to store program code, and the processor is used to call the program code in the memory to execute the foregoing first aspect or any one of the possible implementation methods of the first aspect, which will not be repeated here.
  • the present application provides a network system that includes a sending device and a receiving device.
  • the receiving device is the communication device provided in the aforementioned second or third aspect, and the receiving device is configured to receive the sending device.
  • the sequence of data sent by the device is the communication device provided in the aforementioned second or third aspect.
  • the present application provides a computer-readable storage medium that stores instructions in the computer-readable storage medium, which when run on a computer, causes the computer to execute the methods described in the above aspects.
  • this application provides a computer program product including computer program instructions, when the computer program product runs on a network device, the network device executes the first aspect or any one of the possible implementation manners of the first aspect Method provided in.
  • the present application provides a chip including a memory and a processor, the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory to execute the first aspect and any of the first aspects.
  • the aforementioned chip only includes a processor, and the processor is used to read and execute a computer program stored in the memory.
  • the processor executes the first aspect or any possible implementation method of the first aspect. .
  • the present application provides a network node, which includes a main control board and an interface board.
  • the main control board includes: a first processor and a first memory.
  • the interface board includes: a second processor, a second memory, and an interface card. The main control board and the interface board are coupled.
  • the first memory may be used to store program code
  • the first processor is configured to call the program code in the first memory to perform the following operations: determine candidate bits in the data sequence, where the candidate bits are included in the multiple bits Middle; Determine the synchronization position according to the candidate bit, the synchronization position is used to indicate the starting position of the codeword in the data sequence.
  • the second memory may be used to store program codes, and the second processor is used to call the program codes in the second memory to trigger the interface card to perform the following operations: receiving a data sequence, the data sequence including a plurality of bits.
  • an inter-process communication protocol (IPC) channel is established between the main control board and the interface board, and the main control board and the interface board communicate through the IPC channel.
  • IPC inter-process communication protocol
  • FIG. 1 is a synchronization position of a codeword provided by an embodiment of this application
  • FIG. 2 is a synchronization flowchart provided by an embodiment of this application.
  • FIG. 3 is a synchronization flowchart provided by an embodiment of the application.
  • FIG. 4 is a method for selecting observation bits according to an embodiment of the application.
  • FIG. 5 is a method for selecting observation bits according to an embodiment of the application.
  • FIG. 6 is a method for selecting observation bits according to an embodiment of the application.
  • FIG. 7 is a method for selecting observation bits according to an embodiment of the application.
  • FIG. 8 is the first stage of a synchronization lock judgment provided by an embodiment of the application.
  • FIG. 9 is a second stage of synchronization lock judgment provided by an embodiment of this application.
  • FIG. 10 is a synchronization loss judgment provided by an embodiment of the application.
  • FIG. 11 is a synchronization flowchart provided by an embodiment of this application.
  • FIG. 12 is a schematic structural diagram of a communication device provided by an embodiment of this application.
  • FIG. 13 is a schematic structural diagram of a communication device provided by an embodiment of this application.
  • FIG. 14 is a schematic structural diagram of a communication device provided by an embodiment of this application.
  • FEC is a technology for controlling transmission errors in a communication system.
  • redundant information is sent together with the original data sequence for error recovery during transmission and reducing the bit error rate.
  • FEC can be divided into block codes and convolutional codes according to different processing methods of information sequences. For block codes, it can be subdivided into linear block codes and nonlinear block codes.
  • the sender groups the original data sequence, and the length of each group is k bits. Furthermore, in each packet, according to a specific coding rule, n-k bits of redundant information, also called parity, are added, and finally a codeword with a length of n bits is obtained. Therefore, in a codeword with a length of n bits, the first k bits are original data, also called information bits, and the last n-k bits are check bits, and the entire codeword is composed of information bits and check bits.
  • the receiving end can check and correct the error through the decoding process, and restore the received code word to the one sent by the sender
  • the original data can resist the interference caused by the channel and improve the reliability of the communication system.
  • the realization of the linear block code's error detection and correction functions must be based on the complete code word. Therefore, before the data sequence received by the receiving end is decoded, the code word boundary needs to be determined in the data sequence, that is, to find a complete code word. The start position and end position of the codeword. This process is called codeword synchronization or frame synchronization. If the codeword synchronization is not correct, that is, the true codeword boundary cannot be determined, the due effect of error detection or correction cannot be achieved in the subsequent decoding process, and errors may even increase, resulting in the deterioration of the performance of the communication system.
  • the starting position of each codeword may also be referred to as a synchronization position (synchronization position).
  • Figure 1 shows the synchronization position in the codeword.
  • the length of the entire codeword is n bits, where the first k bits are the original data (information bits), the last nk bits are the extra parity bits added through the encoding rules, and the synchronization position is the codeword
  • the starting position of the codeword that is, the position of the first bit in the codeword.
  • n and k are both integers. It can be seen that, in the data sequence, the number of synchronization positions is multiple, and the multiple synchronization positions are related to each other, and the interval between each synchronization position is fixed, and the interval is the length of the codeword.
  • linear block codes include but are not limited to Reed-Solomon code (Reed-Solomon code, RS code), Bose-Chaudhuri-Hocquenghem code (BCH code), low-density parity Check code (Low-Density Parity-Check code, LDPC code), Hamming code, Golay code, and Reed-Muller code, etc.
  • the embodiment of the present application provides a codeword synchronization method and a device and system based on the method. These methods, equipment and systems are based on the same inventive concept.
  • the method may include two stages. In the first stage, multiple sets of first test data blocks are divided according to multiple observation bits, and one of the multiple observation bits that is most likely to be located at the synchronization position is selected according to the multiple sets of first test data blocks. Observation bits. In the second stage, a group of second test data blocks are divided according to the observation bits that are most likely to be located at the synchronization position, and based on the set of second test data blocks, it is determined whether the observation bits that are most likely to be located at the synchronization position are Sync location.
  • the method may also only include the first stage.
  • the technical effect of high-precision codeword synchronization of the data stream at the receiving end can be realized without inserting additional data in the data stream at the transmitting end, and the synchronization performance can achieve high reliability.
  • Fig. 2 shows a flowchart of a method according to an embodiment of the present application.
  • the method is applied to the receiving end equipment in the communication network.
  • the receiving end device may be various devices that perform FEC, including but not limited to routers, switches, and servers.
  • the steps of the method include:
  • the receiving end receives a data sequence from the sending end, where the data sequence includes a plurality of bits, and each bit is binary data. That is, the data sequence is a sequence composed of multiple bits, and may also be referred to as a bit sequence. In some embodiments, the data sequence is a linear block code.
  • the data sequence is transmitted through the channel, and there may be errors in code, and operations such as error detection and error correction are required.
  • a candidate bit in the data sequence is determined, where the candidate bit is included in the multiple bits.
  • the candidate bit is the observation bit that is most likely to be at the synchronization position among the plurality of observation bits, or in other words, the position of the candidate bit is the most likely synchronization position.
  • the receiving end selects multiple observation bits from the received data sequence.
  • the positions of these observation bits include the synchronization position, that is, the position of a certain observation bit among the observation bits may be the synchronization position, or in other words, the position of these observation bits can cover the synchronization position.
  • the method uses only a part of the data sequence when determining candidate bits in the data sequence, for example, the first subsequence in the data sequence, that is, determining the first subsequence.
  • candidate bits in a subsequence for example, the first subsequence in the data sequence, that is, determining the first subsequence.
  • the first subsequence includes a plurality of bits, and the first subsequence may be any part of the data sequence.
  • the receiving end selects the plurality of observation bits from the first subsequence, and the positions of these observation bits may be synchronization positions.
  • the number of observation bits is P, and P is an integer greater than one.
  • the interval between every two adjacent observation bits in the plurality of observation bits is the same, and each of the plurality of observation bits The position of the observation bit moves backward in turn.
  • test data block is a part of a data sequence, the test data block is composed of several consecutive bits, and the length of the test data block is the same as the length of the codeword. It can be said that the test data block is used to simulate a codeword.
  • the multiple observation bits may be located in the same test data block, and the position of each observation bit in the multiple observation bits in the same test data block moves backward in sequence. Specifically, one bit is selected as the observation bit every interval of T bits, and the T is an integer greater than zero.
  • Figure 4 shows how to select observation bits, where b 1 , b 2 , and b 3 are three adjacent observation bits, corresponding to x(0), x(1), and x(2) in the data sequence. Bits. The interval between each observation bit is 1 bit, that is, T is 1.
  • the three observation bits are located in the same test data block, for example, in the test data block divided by x(0) as the starting position in FIG. 4.
  • the position of b 1 is the first position in the test data block
  • the positions of b 2 and b 3 are the second and third positions in the test data block, namely The position of each observation bit in the same test data block among the three observation bits moves backward in turn.
  • FIG. 4 only shows three observation bits, the selection methods of more observation bits can be deduced by analogy, which will not be repeated here.
  • the plurality of observation bits may be respectively located in a plurality of test data blocks, and the position of each observation bit of the plurality of observation bits in each test data block moves backward in turn.
  • one bit is selected as the observation bit every interval of L*n+T bits, where L is the number of interval test data blocks, the length of the test data block is the n bits, and the L and The T is an integer greater than zero.
  • Fig. 5 shows the selection method of observation bits, where b 1 and b 2 are two adjacent observation bits, corresponding to two bits x(0) and x(L*n+1) in the data sequence, respectively.
  • the two observation bits are located in two different test data blocks, such as the test data block divided by x(0) as the starting position and x(L*n) as the starting position in Figure 5 Out of the test data block.
  • the interval between two test data blocks is L test data blocks, and the interval between two observation bits is L*n+1 bits, that is, T is 1.
  • the position of b 1 is the first position in the test data block, and it is divided with x(L*n) as the starting position
  • the position of b 2 is the second position in the test data block, that is, the position of each observation bit of the two observation bits in each test data block moves backward in turn.
  • the positions of the plurality of observation bits may be made to traverse all positions in the test data block.
  • the positions of the plurality of observation bits can be made to traverse all positions in the same test data block, that is, the positions of the plurality of observation bits Traverse all positions within the same codeword.
  • the length of the codeword is n bits
  • the number of observation bits is P.
  • P is equal to n
  • the positions of the multiple observation bits can traverse the same test data block. All locations within.
  • the same position in each test data block of the plurality of test data blocks is regarded as an equivalent position, for example, in the plurality of test data blocks
  • the first position in each test data block is regarded as an equivalent position, so that the positions of the multiple observation bits traverse all the equivalent positions, that is, the positions of the multiple observation bits traverse all the positions in the multiple test data blocks.
  • the length of the codeword is n bits
  • the number of equivalent positions is n
  • the number of observation bits is P.
  • P is equal to n, the positions of the multiple observation bits That is, all the equivalent positions can be traversed, that is, the positions of the multiple observation bits can be traversed all the positions in the multiple test data blocks.
  • the positions of the plurality of observation bits may not traverse all positions in the codeword. That is, the value of P may be smaller than the n.
  • the signal can be modulated at the transmitting end to obtain a modulated signal.
  • modulation methods include Pulse-Amplitude Modulation (PAM), Quadrature Amplitude Modulation (QAM), Phase-Shift Keying (PSK) and so on.
  • the pulse amplitude of the modulation signal may include multiple orders, and the number of the multiple orders may be referred to as the modulation order.
  • PAM Pulse-Amplitude Modulation
  • QAM Quadrature Amplitude Modulation
  • PSK Phase-Shift Keying
  • the pulse amplitude of the modulation signal may include multiple orders, and the number of the multiple orders may be referred to as the modulation order.
  • PAM when the pulse amplitude of the modulated signal has 2 orders, the modulation order is 2, and the modulation method can be called PAM2; when the pulse amplitude of the modulated signal has 4 orders, the modulation order is 4.
  • the modulation method can be called PAM4, and so on.
  • the modulated signal can be expressed
  • the basic unit of the modulated data sequence is changed from bits to symbols, that is, in the modulated data sequence, the codeword is composed of several symbols, and the symbol is composed of several bits.
  • the number of bits included in the symbol is related to the order of modulation.
  • the modulation order is M
  • the number of bits included in the symbol is log 2 M, where M is an integer multiple of 2.
  • the modulation order is 2
  • the symbol includes 1 bit
  • the modulation order is 4
  • the symbol includes 2 bits. It can be seen that the starting position of a codeword must also be the starting position of a certain symbol, but not other positions of the symbol. Therefore, for a modulated signal, when selecting the plurality of observation bits, only the start bit of the symbol may be considered, and the other bits of the symbol may not be considered.
  • the multiple observation bits are the start bits of multiple symbols, the multiple symbols are in the same test data block, and the multiple symbols are in the same test data block.
  • the position moves backward in turn. Specifically, every interval of T modulation symbols, the start bit of the modulation symbol is selected as the observation bit, and the T is an integer greater than zero. That is, every interval T ⁇ log 2 M bits, the start bit of the modulation symbol is selected as the observation bit.
  • Figure 6 shows the way to select observation bits, where the data sequence is a modulated signal and the modulation order is 4, then the data sequence includes multiple modulation symbols, and each symbol includes 2 bits, such as x(0) Symbols composed of x(1), symbols composed of x(2) and x(3), symbols composed of x(4) and x(5), and so on.
  • b 1 , b 2 , and b 3 are three adjacent observation bits, which respectively correspond to the three bits x(0), x(2), and x(4) in the data sequence.
  • the three observation bits are the start bits of the three symbols respectively, the three symbols are the symbols composed of x(0) and x(1), and the symbols composed of x(2) and x(3), And the symbol composed of x(4) and x(5).
  • T There is an interval of 1 symbol between every two adjacent symbols in the three symbols, that is, T is 1. And, the positions of the three symbols in the same test data block move backward in sequence.
  • FIG. 6 only shows three observation bits, the selection methods of more observation bits can be deduced by analogy, which will not be repeated here.
  • the multiple observation bits are the start bits of multiple symbols, the multiple symbols are respectively located in multiple test data blocks, and each symbol in the multiple symbols is The positions within each test data block move backward in turn.
  • the start bit of the modulation symbol is selected as the observation bit, where L is the number of interval test data blocks, and the length of the test data block is all
  • the L and the T are integers greater than zero. That is, every interval (L ⁇ m+T) ⁇ log 2 M bits, the start bit of the modulation symbol is selected as the observation bit.
  • Figure 7 shows the selection method of observation bits, where the data sequence is a modulated signal and the modulation order is 4, then the data sequence includes multiple modulation symbols, and each symbol includes 2 bits, such as x(0)
  • b1 and b2 are two adjacent observation bits, which respectively correspond to the x(0) and x(L*n+2) bits in the data sequence.
  • the two observation bits are the start bits of the two symbols respectively, and the two symbols are symbols composed of x(0) and x(1), x(L*n+2) and x(L*n). +3) The composed code element. Moreover, the two observation bits are located in two different test data blocks, for example, in the test data block divided by x(0) as the starting position in FIG. 7 and starting with x(L*n) In the test data block divided by the start position.
  • the interval between the two test data blocks is L test data blocks, and the interval between the two observation bits is L*m+1 symbols, that is, T is 1.
  • the symbol of b 1 is the first symbol in the test data block, and the starting position is x(L*n)
  • the symbol where b 2 is located is the second symbol in the test data block, that is, the position of each symbol of the two symbols in each test data block is backward in turn move.
  • FIG. 7 only shows two observation bits, the selection methods of more observation bits can be deduced by analogy, which will not be repeated here. At this time, the interval between adjacent observation bits is longer, and the correlation between observation bits is lower, thereby reducing the impact of burst errors and improving the accuracy of codeword synchronization.
  • S222 Select candidate bits from the multiple observation bits.
  • the candidate bit is one observation bit among the plurality of observation bits, and the candidate bit is the observation bit most likely to be located at a synchronization position.
  • S222 may include two steps, S2221 and S2222.
  • each group of first test data blocks in the plurality of groups of first test data blocks includes at least one first test data block, and the position of each observation bit in the plurality of observation bits is the position of the plurality of groups of first test data blocks. The starting position of each group of the first test data block in a test data block.
  • each observation bit of the plurality of observation bits is used as a starting position, and the following N test data blocks are selected, where N is an integer greater than or equal to 1.
  • the position of each observation bit in the plurality of observation bits is the starting position of each group of the first test data blocks in the plurality of groups of first test data blocks.
  • the N test data blocks selected with each observation bit as the starting position are a group of first test data blocks, and each observation bit in the multiple observation bits is used as the starting position, and the selected groups of N test data
  • the data block is the plurality of first test data blocks.
  • Each group of first test data blocks in the plurality of groups of first test data blocks corresponds to an observation bit as the starting position of the group of first test data blocks, that is, the plurality of groups of first test data blocks and the plurality of There is a one-to-one correspondence between the observation bits.
  • the N test data blocks may be continuous, that is, each group of first test data blocks includes N consecutive data blocks.
  • the length of each test data block is n bits, the following consecutive N*n bits are selected to obtain the N test data blocks.
  • the N test data blocks may also be discontinuous, and the starting position of each test data block in the N test data blocks is associated with the observation bit corresponding to the group of test data blocks.
  • the interval between the starting position of each test data block and the observation bit corresponding to the group of test data blocks is an integer multiple of the length of the codeword, that is, the distance between each two test data blocks in the N test data blocks The interval is an integer multiple of the length of the codeword.
  • the interval between every two test data blocks in the N test data blocks may be the same or different.
  • the group of first test data blocks includes N test data blocks, namely B 1 , B 2 ,... ,B N , the length of each test data block is n bits.
  • the observation bit b 2 or b 3 as the starting position, a group of first test data blocks thereafter can also be selected respectively.
  • the multiple groups of first test data blocks are selected. In FIG. 5, FIG. 6 and FIG. 7, the manner of the multiple groups of first test data blocks is similar to that of FIG. 4, and will not be repeated here.
  • S2222 According to the characteristic values of the plurality of groups of first test data blocks, select one observation bit from the plurality of observation bits as the candidate bit, that is, the observation bit most likely to be located at a synchronization position.
  • the selection method may be early termination The selection method. Specifically, it is sequentially determined whether the characteristic value of each group of the first test data blocks in the plurality of first test data blocks meets the candidate condition, until it is determined that the characteristic value of a group of first test data blocks meets the candidate condition And use observation bits corresponding to the set of first test data blocks that meet the candidate condition as the candidate bits.
  • the selection method may be ergodic Selection method. Specifically, the characteristic values of each group of the first test data blocks in the plurality of groups of first test data blocks are compared, and the observation bit corresponding to a group of the first test data blocks whose characteristic value is an extreme value is used as the candidate Bits.
  • the calculation of the characteristic value can be performed in parallel, that is, multiple calculation units are used to calculate the characteristic values of multiple test data blocks at the same time. For example, 10 calculation units are used to calculate the characteristic values of 10 test data blocks at the same time.
  • Parallel computing can save computing time and reduce time delay.
  • the characteristic value may be the characteristic value of the verification sequence.
  • a parity-check matrix can be generated for each linear block code.
  • the parity-check matrix describes the linear relationship between the data in the codewords of the linear block code, and the parity-check matrix can be applied to the decoding process .
  • the check matrix also exists for the data sequence, which may be referred to as the check matrix of the data sequence.
  • the data sequence and the check matrix of the data sequence satisfy the following relationship:
  • C is a codeword in the data sequence
  • S is the check sequence of the codeword
  • H is the check matrix of the data sequence.
  • the check sequence of the code words in the data sequence can be expressed by the following relational expression:
  • R is a codeword in the data sequence received by the receiving end
  • S R is the check sequence of the codeword
  • H is the check matrix of the original data sequence sent by the sending end.
  • the check sequence of the code word in the data sequence received by the receiving end is the product of the code word and the transposed matrix of the check matrix of the original data sequence sent by the sending end.
  • the check sequence of each group of first test data blocks in the plurality of groups of first test data blocks is calculated separately.
  • the characteristic value may be the number of all-zero sequences in the check sequence.
  • the candidate condition is associated with the characteristic value.
  • the candidate condition may be that the characteristic value of a group of first test data blocks is greater than or equal to the synchronization threshold.
  • the relationship between the number of all-zero sequences in the check sequence of each group of first test data blocks and the synchronization threshold is sequentially determined, until the number of all-zero sequences in the check sequence of a group of first test data blocks is determined
  • the observation bit corresponding to the set of first test data blocks that meets the candidate condition is used as the candidate bit.
  • the observation bits corresponding to a group of first test data blocks are the observation bits that serve as the start bits of the group of first test data blocks.
  • the value of the synchronization threshold can be obtained through simulation analysis. For example, take a piece of data sequence as the data sequence received by the receiving end, design the bit error rate of the data sequence to be within an acceptable range, and count all the check sequences of a group of test data blocks divided based on the synchronization position. The number of zero sequences and the number of all zero sequences in the check sequence of a set of test data blocks divided based on the non-synchronization position, the synchronization threshold is determined according to the difference between the two, so that the synchronization threshold can be used to distinguish the synchronization position And asynchronous location.
  • the characteristic value is the number of all-zero sequences in the check sequence
  • the above-mentioned early termination selection method is adopted, the selection process of the observation bit most likely to be located at the synchronization position can be seen in FIG. 4.
  • the synchronization threshold can be 2.
  • the relationship between the number of all-zero sequences in the check sequence S (1) , S (2) , and S (3) and the synchronization threshold is sequentially determined, for example, the check of the first test data block of the first group
  • the number of all-zero sequences in the sequence Q 1 0, which is less than the synchronization threshold
  • the number of all-zero sequences in the check sequence of the second group of the first test data block Q 2 2 which is equal to the synchronization threshold
  • select b 2 is the observation bit most likely to be located at the synchronization position.
  • the statistical method of early termination may also be adopted for the characteristic value of each group of first test data blocks. That is, the characteristic value of the set of first test data blocks may be the total value of the number of all-zero sequences in the check sequences of all the first test data blocks in the set of first test data blocks, and correspondingly, The alternative condition may be that the total value is greater than or equal to a synchronization threshold.
  • the traversal statistical method may also be adopted for the characteristic value of each group of the first test data block.
  • the characteristic value of the set of first test data blocks may be the cumulative value of the number of all-zero sequences in the check sequence of the first X first test data blocks in the set of first test data blocks, correspondingly Yes, the alternative condition may be that the cumulative value is greater than or equal to the synchronization threshold.
  • the check sequence of each first test data block in the group is calculated to determine whether the total number of all-zero sequences in the group of check sequences meets the alternative condition, that is, the group of check sequences Whether the total value of the number of all-zero sequences is greater than or equal to the synchronization threshold, the specific operation process will not be repeated here.
  • the characteristic value may be the number of all-zero sequences in the check sequence.
  • the extreme value is associated with the characteristic value.
  • the extreme value may be the maximum value. Specifically, the number of all-zero sequences in the check sequence of each group of first test data blocks may be counted, the group of first test data blocks with the largest number of all-zero sequences may be determined, and the group of first test data blocks may correspond to The observation bit of is used as the observation bit most likely to be located at the synchronization position.
  • the selection process of the observation bit most likely to be located at the synchronization position can also be referred to FIG. 4.
  • FIG. 4 count the number of all-zero sequences in the check sequences S (1) , S (2) , and S (3) respectively, denoted as Q 1 , Q 2 , Q 3 , and determine the largest value among them.
  • the characteristic value may be the number of non-all-zero sequences in the check sequence.
  • the candidate condition is associated with the characteristic value.
  • the candidate condition may be that the characteristic value of a group of first test data blocks is less than or equal to the synchronization threshold. Specifically, the relationship between the number of non-all-zero sequences in the check sequence of each group of first test data blocks and the synchronization threshold is sequentially determined, until a non-all-zero sequence in the check sequence of the first test data block is determined When the number of is less than or equal to the synchronization threshold, the observation bit corresponding to the set of first test data blocks that meets the candidate condition is taken as the candidate bit.
  • the value of the synchronization threshold can also be obtained through simulation analysis. The specific process is similar to the synchronization threshold corresponding to the all-zero sequence, and will not be repeated here.
  • the characteristic value may be the number of non-all-zero sequences in the check sequence.
  • the extreme value is associated with the characteristic value.
  • the extreme value may be the minimum value. Specifically, the number of non-all-zero sequences in the check sequence of each group of first test data blocks can be counted, a group of first test data blocks with the least number of non-all-zero sequences can be determined, and the group of first test data The observation bit corresponding to the block is used as the observation bit most likely to be located at the synchronization position.
  • the characteristic value may be the number of zero elements in the check sequence.
  • the candidate condition is associated with the characteristic value.
  • the candidate condition may be that the characteristic value of a group of first test data blocks is greater than or equal to the synchronization threshold.
  • the relationship between the number of zero elements in the check sequence of each group of first test data blocks and the synchronization threshold is sequentially determined, until it is determined that the number of zero elements in the check sequence of a group of first test data blocks is greater than or
  • the observation bit corresponding to the set of first test data blocks that meets the candidate condition is used as the candidate bit.
  • the value of the synchronization threshold can also be obtained through simulation analysis.
  • the characteristic value may be the number of zero elements in the check sequence.
  • the extreme value is associated with the characteristic value.
  • the extreme value may be the maximum value. Specifically, the number of zero elements in the check sequence of each group of first test data blocks can be counted, the group of first test data blocks with the largest number of zero elements can be determined, and the observations corresponding to the group of first test data blocks can be determined. The bit is the observation bit most likely to be located at the synchronization position.
  • the characteristic value may be the number of non-zero elements in the check sequence.
  • the candidate condition is associated with the characteristic value.
  • the candidate condition may be that the characteristic value of a group of first test data blocks is less than or equal to the synchronization threshold. Specifically, the relationship between the number of non-zero elements in the check sequence of each group of first test data blocks and the synchronization threshold is sequentially determined, until the number of non-zero elements in the check sequence of a group of first test data blocks is determined When it is less than or equal to the synchronization threshold, the observation bit corresponding to the set of first test data blocks that meets the candidate condition is used as the candidate bit.
  • the value of the synchronization threshold can also be obtained through simulation analysis.
  • the characteristic value may be the number of non-zero elements in the check sequence.
  • the extreme value is associated with the characteristic value.
  • the extreme value may be the minimum value. Specifically, the number of non-zero elements in the check sequence of each group of first test data blocks can be counted, a group of first test data blocks with the least number of non-zero elements can be determined, and the group of first test data blocks can be corresponding
  • the observation bit of is used as the observation bit most likely to be located at the synchronization position.
  • the characteristic value is a non-all-zero sequence, zero element or non-zero element in the check sequence, in conjunction with the specific implementation process of the data sequence shown in FIG. 4, reference may be made to when the characteristic value is all zeros in the check sequence The introduction of sequence time will not be repeated here.
  • the characteristic value may be an error-correctable characteristic value.
  • the receiving end can determine the state of the codeword, and the state includes an error-correctable state and an error-uncorrectable state.
  • the codeword is also called an error-correctable codeword; when the codeword is in an uncorrectable state, the codeword is also called an uncorrectable codeword.
  • the error-correctable characteristic value of a group of codewords can be associated with the state of the codewords in the group of codewords.
  • the state of the test data block can also be determined, and the state includes an error-correctable state and an error-uncorrectable state.
  • the test data block is also called an error-correctable test data block; when the test data block is in an uncorrectable state, the test data block is also called an uncorrectable test data block.
  • the error-correctable characteristic value of a group of test data blocks may be associated with the state of the test data blocks in the group of test data blocks.
  • the error-correctable characteristic value may be the number of error-correctable test data blocks.
  • the alternative condition is associated with the characteristic value.
  • the candidate condition may be that the characteristic value of a group of first test data blocks is greater than or equal to the synchronization threshold. Specifically, the relationship between the number of error-correctable test data blocks in each group of first test data blocks and the synchronization threshold is sequentially determined, until it is determined that the number of error-correctable test data blocks in a group of first test data blocks is greater than or When it is equal to the synchronization threshold, the observation bit corresponding to the set of first test data blocks that meets the candidate condition is used as the candidate bit.
  • the value of the synchronization threshold can also be obtained through simulation analysis.
  • the synchronization threshold can be 2.
  • the error-correctable characteristic value may be the number of error-correctable test data blocks.
  • the extreme value is associated with the characteristic value.
  • the extreme value may be the maximum value. Specifically, the number of error-correctable test data blocks in each group of first test data blocks can be counted, the group of first test data blocks with the largest number of error-correctable test data blocks can be determined, and the group of first test data blocks can be determined.
  • the observation bit corresponding to the block is used as the observation bit most likely to be located at the synchronization position.
  • the error-correctable characteristic value is the number of error-correctable test data blocks
  • the error-correctable characteristic value may be the number of test data blocks that cannot be corrected.
  • the candidate condition is associated with the characteristic value.
  • the candidate condition may be that the characteristic value of a group of first test data blocks is less than or equal to the synchronization threshold.
  • the relationship between the number of uncorrectable test data blocks in each group of first test data blocks and the synchronization threshold is sequentially determined, until it is determined that the number of uncorrectable test data blocks in a group of first test data blocks is less than or
  • the observation bit corresponding to the set of first test data blocks that meets the candidate condition is used as the candidate bit.
  • the value of the synchronization threshold can also be obtained through simulation analysis.
  • the error-correctable characteristic value may be the number of test data blocks that cannot be corrected.
  • the extreme value is associated with the characteristic value.
  • the extreme value may be the minimum value. Specifically, the number of uncorrectable test data blocks in each group of first test data blocks may be counted, the group of first test data blocks with the least number of uncorrectable test data blocks may be determined, and the group of first test data blocks may be determined.
  • the observation bit corresponding to the block is used as the observation bit most likely to be located at the synchronization position.
  • the characteristic value may be a re-inspection characteristic value.
  • the re-check characteristic value is associated with the relationship between the re-check bit and the original check bit.
  • the first k bits are information bits
  • the last n-k bits are check bits.
  • the check digit of the last n-k bits is calculated based on the previous k bits of information and in accordance with specific coding rules. For the data sequence received by the receiving end, if the starting position of the code word in the data sequence is not found, the divided code word no longer satisfies the above-mentioned relationship between the information bit and the check bit.
  • the last n-k bits and the previous k bits may no longer meet the above-mentioned specific coding rules. Therefore, when the first k bits in each test data block in the data sequence received by the receiving end are used as the basis, the last nk bits recalculated according to the specific coding rule are compared with the data sequence received by the receiving end. Compared with the last nk bits in each test data block, there may be differences.
  • the last nk bits in each test data block in the data sequence received by the receiving end can be called the original check bit, based on the first k bits in each test data block in the data sequence received by the receiving end, The last nk bits recalculated according to the specific coding rule may be called re-check bits.
  • the re-check bit in each test data block in the data sequence received by the receiving end can be compared with the original check bit to achieve codeword synchronization.
  • the re-check bit in each test data block in the data sequence received by the receiving end can be compared with the original check bit, and one observation bit from the multiple observation bits can be selected as the all Describe the observation bit that is most likely to be located at the synchronization position.
  • the re-check characteristic value may be the number of test data blocks whose re-check bit is the same as the original check bit.
  • the candidate condition is associated with the characteristic value.
  • the alternative condition may be greater than or equal to the synchronization threshold. Specifically, the relationship between the number of test data blocks with the same re-check bit and the original check bit in each group of first test data blocks and the synchronization threshold is sequentially determined, until the re-check bit in a group of first test data blocks is determined When the number of test data blocks that are the same as the original check bits is greater than or equal to the synchronization threshold, the observation bits corresponding to the set of first test data blocks that meet the candidate condition are used as the candidate bits.
  • the value of the synchronization threshold can also be obtained through simulation analysis.
  • the synchronization threshold can be 2.
  • the relationship between the number of test data blocks with the same recheck digit and the original check digit in each group of the first test data block and the synchronization threshold is sequentially determined, for example, the recheck in the first test data block of the first group
  • the re-checked characteristic value may be the number of test data blocks whose re-check bit is the same as the original check bit.
  • the extreme value is associated with the characteristic value.
  • the extreme value may be the maximum value. Specifically, the number of test data blocks whose re-check digits are the same as the original check digits in each group of first test data blocks can be counted, and the one with the largest number of test data blocks whose re-check digits are the same as the original check digit can be determined. Group the first test data block, and use the observation bit corresponding to the first test data block as the observation bit most likely to be located at the synchronization position.
  • the re-check characteristic value is the number of test data blocks with the same re-check bit as the original check bit
  • the selection process of the observation bit that is most likely to be located at the synchronization position can also be seen in Fig. 4.
  • the number of test data blocks in each group of first test data blocks with observation bits b 1 , b 2 , and b 3 as the starting bits are counted, and the number of test data blocks with the same re-check bit as the original check bit is recorded respectively.
  • the re-check characteristic value may be the number of test data blocks whose re-check bit is different from the original check bit.
  • the candidate condition is associated with the characteristic value.
  • the alternative condition may be less than or equal to the synchronization threshold. Specifically, the relationship between the number of test data blocks whose recheck digits are different from the original check digits in each group of first test data blocks and the synchronization threshold is sequentially judged, until a group of first test data blocks is determined to be rechecked When the number of test data blocks whose bits are different from the original check bits is less than or equal to the synchronization threshold, the observation bits corresponding to the set of first test data blocks that meet the candidate condition are used as the candidate bits.
  • the value of the synchronization threshold can also be obtained through simulation analysis.
  • the re-check characteristic value may be the number of test data blocks whose re-check bit is different from the original check bit.
  • the extreme value is associated with the characteristic value.
  • the extreme value may be the minimum value. Specifically, the number of test data blocks whose re-check digits are different from the original check digits in each group of first test data blocks can be counted, and the number of test data blocks whose re-check digits are different from the original check digits can be determined to be the least.
  • the observation bit corresponding to the first test data block of the group of the first test data block is used as the observation bit most likely to be located at the synchronization position.
  • the synchronization possibility index (synchronization possibility index) of the plurality of observation bits is determined respectively, and the larger the value of the synchronization possibility index, the observation is The bit position is more likely to be the synchronization position.
  • the synchronization possibility The index may be positively correlated with the number of all-zero sequences, that is, the more the number of all-zero sequences, the greater the value of the synchronization possibility index, which indicates that the position of the observation bit is more likely to be a synchronization position.
  • the characteristic value of the multiple groups of first test data blocks is the number of non-all-zero sequences in the check sequence of each group of the first test data blocks in the multiple groups of first test data blocks
  • the performance index may be negatively correlated with the number of non-all-zero sequences, that is, the smaller the number of non-all-zero sequences, the greater the value of the synchronization possibility index, which indicates that the position of the observation bit is more likely to be a synchronization position.
  • the characteristic value of the multiple sets of first test data blocks is the number of zero elements in the check sequence of each group of the first test data blocks in the multiple sets of first test data blocks, or the number of zero elements in the multiple sets of first test data blocks
  • the characteristic value of a test data block is the number of error-correctable test data blocks in each of the plurality of first test data blocks, or the characteristic value of the plurality of first test data blocks is as follows
  • the synchronization possibility index may be the same as the number of zero elements or may be The number of error correction test data blocks or the number of test data blocks whose recheck bits are the same as the original check bits is positively correlated; when the characteristic value of the plurality of first test data blocks is in the plurality of first test data blocks The number of non-zero elements in the check sequence of each group of first test data blocks, or the characteristic value of the plurality of first test data
  • one of the observation bits may be selected as the most likely synchronization position according to other conditions Observation bits. For example, from the observation bit with the largest value of the synchronization possibility index, one observation bit is randomly selected as the observation bit most likely to be located at the synchronization position. For example, from the observation bits with the largest value of the synchronization possibility index, the observation bit ranked first in the data sequence is selected as the observation bit most likely to be located at the synchronization position.
  • S230 In the second stage, the candidate bit is verified, and when the verification succeeds, it is determined that the position of the candidate bit is the synchronization position.
  • S230 may include two steps S231 and S232.
  • the method divides at least one second test data block in the data sequence according to the candidate bit
  • only a part of the data sequence may be used, for example, the The second subsequence in the data sequence.
  • Divide a group of second test data blocks in the data sequence according to the candidate bits that is, divide a group of second test data blocks in the second subsequence according to the candidate bits.
  • the second subsequence may be the same as the first subsequence in the first stage, that is, all bits of the second subsequence and the first subsequence are the same, and the two subsequences are completely overlapped.
  • the second subsequence may be partially the same as the first subsequence in the first stage, that is, the second subsequence and the first subsequence have the same partial bits, and the two subsequences partially overlap.
  • the second subsequence may be different from the first subsequence in the first stage, that is, all bits of the second subsequence and the first subsequence are different, and the two subsequences have no intersection.
  • a group of second test data blocks is divided in the second subsequence, and the group of second test data blocks includes at least A second test data block.
  • dividing a group of second test data blocks in the second subsequence may be to use the candidate bits as the starting bit of the at least one second test data block, thereby dividing Output the at least one second test data block.
  • the observation bit most likely to be located at the synchronization position divide a group of second test data blocks in the second subsequence, or use the observation bit most likely to be located at the synchronization position as the start bit of the test data block To divide the second sub-sequence into a plurality of test data blocks, and select at least one test data block from the plurality of test data blocks as the at least one second test data block.
  • a number of test data blocks are spaced between the at least one second test data block and the observation bit most likely to be located at the synchronization position, and the at least one second test data block may be located at the most likely synchronization position Before the observation bit, it can also be located after the observation bit that is most likely to be located at the synchronization position.
  • the at least one second test data block may be continuous, that is, the at least one second test data block includes N consecutive data blocks.
  • the length of each test data block is n bits
  • the following consecutive N*n bits are selected to obtain the at least one second test data block.
  • the at least one second test data block may also be discontinuous, and the starting position of each test data block in the at least one second test data block is associated with candidate bits.
  • the interval between the start position of each test data block and the candidate bit is an integer multiple of the length of the codeword, that is, the interval between every two test data blocks in the at least one second test data block is a code An integer multiple of the length of the word.
  • the interval between every two test data blocks in the at least one second test data block may be the same or different.
  • S232 Verify the characteristic value of the at least one second test data block, and when the verification succeeds, determine that the position of the candidate bit is the synchronization position.
  • the characteristic value of the at least one second test data block is verified, and the verification mode may be an early termination verification mode.
  • the characteristic values of each second test data block in the at least one second test data block are sequentially accumulated to obtain an accumulated value, until the accumulated value meets the synchronization condition, the verification is successful, and the position of the candidate bit is determined Is the synchronization position.
  • the synchronization condition is associated with the characteristic value, specifically,
  • the characteristic value is the number of all-zero sequences in the check sequence, and the synchronization condition is that the cumulative value is greater than or equal to the synchronization threshold; or,
  • the characteristic value is the number of zero elements in the check sequence, and the synchronization condition is that the cumulative value is greater than or equal to the synchronization threshold; or,
  • the characteristic value is the number of error-correctable test data blocks, and the synchronization condition is that the cumulative value is greater than or equal to the synchronization threshold; or,
  • the characteristic value is the number of test data blocks whose recheck digits are the same as the original check digits, and the synchronization condition is that the cumulative value is greater than or equal to a synchronization threshold;
  • the value of the synchronization threshold can also be obtained through simulation analysis.
  • the synchronization threshold in step 230 and the synchronization threshold in step 2222 may be the same or different.
  • the characteristic value of the at least one second test data block is verified, and the verification mode may be a traversal verification mode. Specifically, the characteristic values of all the second test data blocks in the at least one second test data block are added together to obtain a total value, and when the total value meets the synchronization condition, the verification is successful, and the position of the candidate bit is determined Is the synchronization position.
  • the synchronization condition is associated with the characteristic value, specifically,
  • the characteristic value is the number of all-zero sequences in the check sequence, and the synchronization condition is that the total value is greater than or equal to the synchronization threshold; or,
  • the characteristic value is the number of non-all-zero sequences in the check sequence, and the synchronization condition is that the total value is less than or equal to the synchronization threshold; or,
  • the characteristic value is the number of zero elements in the check sequence, and the synchronization condition is that the total value is greater than or equal to the synchronization threshold; or,
  • the characteristic value is the number of non-zero elements in the check sequence, and the synchronization condition is that the total value is less than or equal to the synchronization threshold; or,
  • the characteristic value is the number of error-correctable test data blocks, and the synchronization condition is that the total value is greater than or equal to the synchronization threshold; or,
  • the characteristic value is the number of uncorrectable test data blocks, and the synchronization condition is that the total value is less than or equal to the synchronization threshold; or,
  • the characteristic value is the number of test data blocks in which the recheck digit is the same as the original check digit, and the synchronization condition is that the total value is greater than or equal to the synchronization threshold; or,
  • the characteristic value is the number of test data blocks whose recheck bits are different from the original check bits, and the synchronization condition is that the total value is less than or equal to a synchronization threshold.
  • the value of the synchronization threshold can also be obtained through simulation analysis.
  • the synchronization threshold in step 230 and the synchronization threshold in step 2222 may be the same or different.
  • the calculation of the characteristic value can be performed in parallel, that is, multiple calculation units are used to calculate the characteristic values of multiple test data blocks at the same time. For example, 10 calculation units are used to calculate the characteristic values of 10 test data blocks at the same time.
  • Parallel computing can save computing time and reduce time delay.
  • FIGS. 8 to 9 show an exemplary process of determining the observation bit most likely to be located at the synchronization position in the data sequence, and verifying whether the position of the observation bit most likely to be located at the synchronization position is the synchronization position.
  • the linear block code shown in FIG. 8 is a BCH (360, 340) code, that is, the length of each codeword is 360 bits, and the length of information data in each codeword is 340 bits.
  • the modulation mode of the BCH (360,340) code is Non-Return-to-Zero (NRZ), the modulation order M is 2, and each symbol includes 1 bit.
  • the check matrix for the BCH (360,340) code is as follows:
  • ⁇ is the primitive element of Galois Field GF(2 10 ).
  • FIG. 8 shows a part of the data sequence received by the receiving end, and it is necessary to confirm the starting position of the code word in the data sequence, that is, the synchronization position.
  • the observation bit that is most likely to be located at the synchronization position in the data sequence is determined.
  • the T is 1, that is, the modulation code is selected every 1 bit interval
  • the start bit of the element is used as the observation bit. Therefore, continuous 360 bits are selected as observation bits, that is, the number P of observation bits is 360, as shown in FIG.
  • each group of first test data blocks includes 2 test data blocks , As shown in Figure 8 with multiple groups B 1 , B 2 .
  • the check sequence S is a row vector of length 4.
  • the check sequence set of a group of first test data blocks with observation bit b 1 as the starting bit is S (1) , including S 1 (1) , S 2 (1) correspond to test data blocks B 1 , B 2 , and similarly, take observation bits b 2 , b 3 ,..., b 359 , b 360 as the first group of starting bits
  • the check sequence set of a test data block is S (2) , S (3) ,..., S (359) , S (360) .
  • Count the number of all-zero sequences in the check sequence of the first test data block in each group and record them as Q 1 , Q 2 , Q 3 ,..., Q 359 , Q 360 respectively .
  • Q 1 0, that is, there is no all-zero sequence in the check sequence of the first test data block with observation bit b 1 as the starting bit.
  • the observation bit b 359 is taken as the observation bit most likely to be located at the synchronization position. That is, the observation bit b 359 is considered to be the start bit of a test data block, and every 360 bits thereafter are the start bits of the subsequent test data block.
  • a group of second sub-sequences is divided according to b 359 Test data block. That is, a group of second test data blocks is divided in the second subsequence, and the second subsequence is different from the first subsequence.
  • the group of second test data blocks includes 4 test data blocks. The characteristic value of the at least one second test data block is verified, where the characteristic value is the number of all-zero sequences in the check sequence of the at least one second test data block.
  • the above-mentioned traversal verification method is adopted, that is, the number of all-zero sequences in the check sequences of all second test data blocks in the at least one second test data block is added to obtain a total value, when the total value is greater than or equal to the synchronization threshold , The verification is successful, and the synchronization threshold is 2.
  • the number of all-zero sequences is 3, which is greater than 2, so it is determined that the position where b 359 is located is the synchronization position.
  • step S220 is re-executed, that is, the first stage is re-executed, and the observation bit most likely to be located at the synchronization position is reselected.
  • Step S230 is an optional step, that is, the method may only include the first stage. At this time, directly go to step S240 after step S220. At this time, in this method, after determining the candidate bit, the position of the candidate bit is directly determined as the synchronization position. That is, directly use the most probable synchronization position as the synchronization position.
  • the received data sequence can be divided into multiple synchronization code words according to the synchronization position.
  • the data sequence is divided into multiple synchronization code words according to the synchronization position, it can be considered that the data sequence is in the synchronization lock position. That is to say, after determining the synchronization position, the receiving end determines that the data sequence is in the synchronization lock state. When the data sequence is in the synchronization lock state, the receiving end can perform error detection and error correction operations on the data sequence.
  • the receiving end After the receiving end starts to perform operations such as error detection and error correction on the data sequence, it is still necessary to continuously observe whether the codeword division in the data sequence is accurate, that is, whether the synchronization position is accurate.
  • the synchronization position When the synchronization position is inaccurate, the content of each test data block divided according to the synchronization position no longer corresponds to the real codeword. At this time, it can also be said that the synchronization lock state of the data sequence is lost. Therefore, the process of judging whether the synchronization position of the data sequence is accurate can also be referred to as the process of losing lock judgment.
  • a plurality of synchronization code words are divided from the data sequence according to the synchronization position, and the synchronization position is the starting position of the plurality of synchronization code words;
  • the characteristic value of the word is verified, and when the verification fails, it is determined that the data sequence is in the unlocked state.
  • the multiple synchronization codewords may be continuous, that is, the multiple synchronization codewords include consecutive N codewords.
  • the length of each codeword is n bits, the following consecutive N*n bits are selected to obtain the multiple synchronization codewords.
  • the multiple synchronization codewords may also be discontinuous, and the start position of each codeword in the multiple synchronization codewords is associated with a synchronization position.
  • the interval between the start position of each synchronization codeword and the synchronization position is an integer multiple of the length of the codeword, that is, the interval between every two synchronization codewords in the plurality of synchronization codewords is the length of the codeword Integer multiples of.
  • the interval between every two synchronization code words in the plurality of synchronization code words may be the same or different.
  • the characteristic values of the multiple synchronization codewords are verified, and the verification mode may be an early termination verification mode.
  • the characteristic value of each synchronization codeword in the plurality of synchronization codewords is sequentially accumulated to obtain an accumulated value, until the accumulated value meets the lock-out condition, the verification fails, and the position of the candidate bit is determined to be the Sync location.
  • the lock-out condition is associated with the characteristic value, specifically,
  • the characteristic value is the number of non-all-zero sequences in the check sequence, and the lock-out condition is that the cumulative value is greater than or equal to the synchronization threshold; or,
  • the characteristic value is the number of non-zero elements in the check sequence, and the lock-out condition is that the cumulative value is greater than or equal to the synchronization threshold; or,
  • the characteristic value is the number of uncorrectable codewords, and the lock-out condition is that the cumulative value is greater than or equal to the synchronization threshold; or,
  • the characteristic value is the number of codewords whose recheck digits are different from the original check digits, and the lock-out condition is that the accumulated value is greater than or equal to a synchronization threshold;
  • the length of the codeword is n bits
  • the first k bits of the codeword are information bits
  • the last nk bits of the codeword are the original check bits
  • the recheck bits are based on the information
  • the length of the recheck bit is nk bits
  • the n and k are integers.
  • the value of the synchronization threshold can also be obtained through simulation analysis.
  • the synchronization threshold in step 250 and the synchronization threshold in steps 230 and 2222 may be the same or different.
  • the characteristic values of the multiple synchronization codewords are verified, and the verification mode may be a traversal verification mode. Specifically, the characteristic values of all the synchronization code words in the multiple synchronization code words are added to obtain a total value. When the total value meets the lock-out condition, the verification fails, and the position of the candidate bit is determined to be the Sync location.
  • the synchronization condition is associated with the characteristic value, specifically,
  • the characteristic value is the number of all-zero sequences in the check sequence, and the lock-out condition is that the total value is less than or equal to the synchronization threshold; or,
  • the characteristic value is the number of non-all-zero sequences in the check sequence, and the lock-out condition is that the total value is greater than or equal to the synchronization threshold; or,
  • the characteristic value is the number of zero elements in the check sequence, and the lock-out condition is that the total value is less than or equal to the synchronization threshold; or,
  • the characteristic value is the number of non-zero elements in the check sequence, and the lock-out condition is that the total value is greater than or equal to the synchronization threshold; or,
  • the characteristic value is the number of error-correctable codewords, and the lock-out condition is that the total value is less than or equal to the synchronization threshold; or,
  • the characteristic value is the number of uncorrectable codewords, and the lock-out condition is that the total value is greater than or equal to the synchronization threshold; or,
  • the characteristic value is the number of codewords with the same recheck bits as the original check bits, and the lock-out condition is that the total value is less than or equal to the synchronization threshold; or,
  • the characteristic value is the number of codewords whose recheck bits are different from the original check bits, and the lock-out condition is that the total value is greater than or equal to a synchronization threshold;
  • the length of the codeword is n bits
  • the first k bits of the codeword are information bits
  • the last nk bits of the codeword are the original check bits
  • the recheck bits are based on the information
  • the length of the recheck bit is nk bits
  • the n and k are integers.
  • the value of the synchronization threshold can also be obtained through simulation analysis.
  • the synchronization threshold in step 250 and the synchronization threshold in steps 230 and 2222 may be the same or different.
  • the calculation of the characteristic value can be performed in parallel, that is, multiple calculation units are used to calculate the characteristic values of multiple test data blocks at the same time. For example, 10 calculation units are used to calculate the characteristic values of 10 test data blocks at the same time.
  • Parallel computing can save computing time and reduce time delay.
  • Fig. 10 shows an exemplary process for determining loss of lock.
  • 5 synchronization code words are divided from the data sequence according to the synchronization position, and the number of error correction code words among them is counted. For example, in the decoding state, 0 means error correction is not possible, and 1 means error correction is possible. In the five synchronization code words shown in FIG. 10, the number of error correction code words is 1. If the lock-out threshold is 3, the number of error-correctable codewords is less than the lock-out threshold, and it is determined that 5 synchronization code words meet the lock-out condition, and the data sequence is in the lock-out state.
  • the data sequence may continue to move backward for a certain interval, select multiple synchronization code words, and continue to determine the multiple synchronization codes selected backward Whether the word satisfies the lock-out condition.
  • the moving backward for a certain interval may be moving one test data block, that is, starting with each synchronization codeword and observing multiple synchronization codewords backwards to perform lock-out judgment.
  • S260 Determine that the data sequence is in an unlocked state.
  • the data sequence when it is determined that the data sequence is in the unlocked state, continue to determine the update synchronization position of the data sequence. Specifically, the first phase and the second phase are re-executed, and the synchronization position determined in the re-executed second phase is used as the updated synchronization position. In this way, a closed-loop operation of synchronizing lock-loss of lock-synchronizing lock is formed, which ensures that the communication system is in a normal working state of synchronizing lock for as much time as possible.
  • This method can solve the technical problems of adding extra data and poor cascading scalability in the AM synchronization scheme.
  • there is no need to insert additional data into the data stream of the sender and there is no need to introduce an idle code block addition and deletion mechanism on the Ethernet interface, no need to design a corresponding logic processing unit, and no need to reserve bandwidth in advance for the inserted AM sequence.
  • the technical effect of high-precision codeword synchronization of the data stream at the receiving end can be realized, and the synchronization performance can achieve high reliability.
  • Steps S240, S250 and S260 are all optional steps, that is, the method can only be used to determine the synchronization position, the data sequence may not be subjected to error detection or correction processing in the synchronization lock state, or the data sequence may not be Enter the lock-out state for judgment.
  • the codeword synchronization method provided by this application is compared with the existing AM synchronization scheme in terms of the average synchronization lock time, the average occurrence time of false locks, and the average occurrence time of false locks.
  • the provided codeword synchronization methods are superior to existing AM synchronization schemes. Therefore, from an overall point of view, the codeword synchronization method provided by the present application can achieve better synchronization performance than the AM synchronization scheme.
  • Fig. 11 shows a codeword synchronization method according to an embodiment of the present application. The method includes the following steps:
  • Step 1 Receive a data sequence, where the data sequence includes a plurality of bits.
  • the data sequence includes a plurality of bits.
  • Step 2 Determine candidate bits in the data sequence, where the candidate bits are included in the multiple bits.
  • the candidate bit is the observation bit most likely to be located at the synchronization position.
  • Step 3 Determine a synchronization position according to the candidate bit, where the synchronization position is used to indicate the starting position of the codeword.
  • determining the synchronization position according to the candidate bit may be to further verify whether the position of the observation bit most likely to be in the synchronization position is the synchronization position after selecting the observation bit most likely to be in the synchronization position.
  • the candidate bit is the observation bit most likely to be located at the synchronization position.
  • the specific process of the step 3 can refer to the above description of step S230.
  • the method at least includes S210, S220, and S230 shown in FIG. 2.
  • determining the synchronization position according to the candidate bit may also be directly after selecting the observation bit most likely to be located at the synchronization position, and directly use the observation bit most likely to be located at the synchronization position as the synchronization position.
  • the candidate bit is the observation bit that is most likely to be located at the synchronization position.
  • the method at least includes S210 and S220 shown in FIG. 2.
  • the bit located at the synchronization position is included in the candidate bit, and the candidate bit is the most likely synchronization position. Observation bits.
  • the method further includes: determining that the data sequence is in a synchronization lock state.
  • determining that the data sequence is in a synchronization lock state refer to the above description of step S240.
  • the method further includes: lock-out judgment.
  • step S250 For the specific process, refer to the above description of step S250.
  • the method may further include step 4, in response to the data sequence being in the unlocked state, determining the update synchronization position of the data sequence.
  • step 4 in response to the data sequence being in the unlocked state, determining the update synchronization position of the data sequence.
  • the codeword synchronization method in the embodiment of the present application is executed by a communication device, and the communication device may be any device that performs FEC, including but not limited to routers, switches, servers, and terminal devices.
  • FIG. 12 shows a schematic diagram of a possible structure of a communication device involved in an embodiment of the present application.
  • the communication device 1200 includes a receiving unit 1201 and a processing unit 1202. These units can perform the corresponding steps of the method shown in Figures 2-11. for example,
  • the receiving unit 1201 is configured to receive a data sequence, where the data sequence includes a plurality of bits.
  • the processing unit 1202 is configured to determine candidate bits in the data sequence, where the candidate bits are included in the multiple bits; determine a synchronization position according to the candidate bits, and the synchronization position is used to indicate the The starting position of the code word in the data sequence.
  • FIG. 13 is a schematic diagram of another structure of a communication device involved in an embodiment of the present application.
  • the communication device 1300 includes at least one processor 1301 and at least one communication interface 1304.
  • the device 1300 may further include a memory 1303.
  • the processor 1301 may be a central processing unit (CPU), a general-purpose processor, a digital signal processor (digital signal processor, DSP), an application-specific integrated circuit (ASIC), a field programmable gate array Field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various logical blocks, modules, and circuits described in conjunction with the disclosure of the embodiments of the present application.
  • the processor may also be a combination for realizing computing functions, for example, including a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and so on.
  • the processor may be used to determine candidate bits in the data sequence, and determine a synchronization position according to the candidate bits. In order to implement the method provided in the embodiment of the present application.
  • the communication bus 1302 is used to transmit information between the processor 1301, the communication interface 1304, and the memory 1303.
  • the bus may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus.
  • PCI peripheral component interconnect
  • EISA extended industry standard architecture
  • the bus can be divided into an address bus, a data bus, a control bus, and so on. For ease of presentation, only one thick line is used in FIG. 13, but it does not mean that there is only one bus or one type of bus.
  • the memory 1303 can be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, random access memory (RAM), or other types that can store information and instructions
  • the dynamic storage device can also be electrically erasable programmable read-only memory (EEPROM), compact disc read-only Memory (CD-ROM) or other optical disc storage, optical disc storage (Including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or can be used to carry or store desired program codes in the form of instructions or data structures and can be used by a computer Any other media accessed, but not limited to this.
  • the memory 1303 may exist independently, and is connected to the processor 1301 through a communication bus 1302.
  • the memory 1303 may also be integrated with the processor 1301.
  • the memory 1303 is used to store program codes or instructions for executing the solutions of the present application, and the processor 1301 controls the execution.
  • the software or program codes required to perform the functions of each unit in FIG. 12 are stored in the memory 1303 middle.
  • the processor 1301 is configured to execute program codes stored in the memory 1303.
  • One or more software modules can be included in the program code.
  • the processor 1301 itself may also store program codes or instructions for executing the solutions of the present application.
  • the communication interface 1304 uses any device such as a transceiver to communicate with other devices or communication networks.
  • the communication network may be Ethernet, wireless access network (RAN), or wireless local area networks (WLAN).
  • the communication interface 1304 may be used to receive packets sent by other nodes in the segment routing network, and may also send packets to other nodes in the segment routing network.
  • the communication interface 1304 may be an Ethernet interface (Ethernet) interface, a Fast Ethernet (FE) interface, a Gigabit Ethernet (GE) interface, or an asynchronous transfer mode (Asynchronous Transfer Mode, ATM) interface.
  • the device 1300 may include multiple processors, such as the processor 1301 and the processor 1305 shown in FIG. 13. Each of these processors can be a single-CPU (single-CPU) processor or a multi-core (multi-CPU) processor.
  • the processor here may refer to one or more devices, circuits, and/or processing cores for processing data (for example, computer program instructions).
  • the processor 1301 in the network device 1300 is configured to receive a data sequence through a communication interface, the data sequence includes a plurality of bits; to determine a candidate bit in the data sequence, the candidate bit is included in Among the multiple bits, a synchronization position is determined according to the candidate bit, and the synchronization position is used to indicate the starting position of a codeword in the data sequence.
  • steps S210, S220, S230, S240, S250, S260 in the embodiment shown in FIG. 2, steps S221, S222 in the embodiment shown in FIG. 3, and steps shown in FIG. 11
  • steps S210, S220, S230, S240, S250, S260 in the embodiment shown in FIG. 2
  • steps S221, S222 in the embodiment shown in FIG. 3 steps shown in FIG. 11
  • steps S210, S220, S230, S240, S250, S260 in the embodiment shown in FIG. 2
  • steps S221, S222 in the embodiment shown in FIG. 3 steps shown in FIG. 11
  • the communication interface in the network device 1300 is used for the network device 1300 to receive and send data sequences through the network system.
  • S210 in the embodiment shown in FIG. 2 and the detailed description of step 1 shown in FIG. 11, which will not be repeated here.
  • FIG. 14 is a schematic diagram of another structure of a communication device involved in an embodiment of the present application.
  • the communication device can refer to the schematic diagram of the device structure shown in FIG. 14.
  • the device 1400 includes a main control board and one or more interface boards, and the main control board is in communication connection with the interface board.
  • the main control board is also called the main processing unit (MPU) or route processor card.
  • the main control board is responsible for the control and management of each component in the device 1400, including routing calculation, device management and maintenance functions .
  • the interface board is also called a line processing unit (LPU) or a line card (line card), which is used to forward data.
  • LPU line processing unit
  • line card line card
  • the device 1400 may also include a switching network board.
  • the switching network board is in communication connection with the main control board and the interface board.
  • the switching network board is used to forward data between the interface boards.
  • the switching network board may also be called a switching network board.
  • Board unit switch fabric unit, SFU).
  • the interface board includes a central processing unit, a memory, a forwarding chip, and a physical interface card (PIC).
  • the central processing unit is respectively communicatively connected with the memory, the network processor and the physical interface card.
  • the memory is used to store the forwarding table.
  • the forwarding chip is used to forward the received data frame based on the forwarding table stored in the memory.
  • the forwarding chip may be a network processor (NP).
  • the PIC is also called a daughter card, which can be installed on the interface board, and is responsible for converting the photoelectric signal into a data frame and checking the validity of the data frame before forwarding it to the forwarding chip for processing.
  • the central processing unit can also perform the function of a forwarding chip, such as realizing software forwarding based on a general-purpose CPU, so that no forwarding chip is required in the interface board.
  • a forwarding chip such as realizing software forwarding based on a general-purpose CPU, so that no forwarding chip is required in the interface board.
  • the communication connection between the main control board, the interface board, and the switching network board can be realized through a bus.
  • the forwarding chip may be implemented by an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA).
  • ASIC application-specific integrated circuit
  • FPGA field programmable gate array
  • the device 1400 includes a control plane and a forwarding plane.
  • the control plane includes a main control board and a central processing unit.
  • the forwarding plane includes various components that perform forwarding, such as memory, PIC, and NP.
  • the control plane performs functions such as routers, generation of forwarding tables, processing of signaling and protocol messages, configuration and maintenance of the state of PE1.
  • the control plane delivers the generated forwarding tables to the forwarding plane.
  • the NP is based on the control plane’s
  • the forwarding table looks up and forwards the message received by the PIC of the device 1400.
  • the forwarding table issued by the control plane can be stored in the memory. In some embodiments, the control plane and the forwarding plane can be completely separated and not on the same device.
  • the interface board is used to receive a data sequence, and the data sequence includes a plurality of bits.
  • the data sequence includes a plurality of bits.
  • the main control board is used to determine candidate bits in the data sequence, the candidate bits are included in the multiple bits; the synchronization position is determined according to the candidate bits, and the synchronization position is used to indicate all The starting position of the code word in the data sequence.
  • steps S210, S220, S230, S240, S250, S260 in the embodiment shown in Figure 2 above, steps S221, S222 in the embodiment shown in Figure 3, and details of steps 1 to 3 shown in Figure 11 Description, I won’t repeat it here.
  • an inter-process communication protocol (IPC) channel is established between the main control board and the interface board, and the main control board and the interface board communicate through the IPC channel.
  • IPC inter-process communication protocol
  • An embodiment of the present application provides a chip that includes a memory and a processor, the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory to execute the method in the above method embodiment, as shown in FIG. 2 -11 The method in the embodiment shown.
  • the foregoing chip only includes a processor, and the processor is used to read and execute a computer program stored in the memory.
  • the processor executes the method in the foregoing method embodiment, as shown in Figure 2-11. The method in the embodiment.
  • the chip can be used in an application scenario of two-level FEC cascade.
  • the two-level FEC cascade includes an inner layer FEC and an outer layer FEC, and the chip provided in the embodiment of the present application is used for the inner layer FEC.
  • the inner layer FEC adopts the codeword synchronization method described in this application, also called FEC1;
  • the outer layer FEC can adopt the AM synchronization scheme, also called FEC2.
  • the FEC1 and the FEC2 may be located on the same chip or on different chips. That is, the chip provided in the embodiment of the present application may only include the FEC1, or may include the FEC1 and the FEC2.
  • the embodiment of the application provides a network system.
  • the network system includes receiving equipment and sending equipment.
  • the receiving device is used to receive the data sequence sent by the sending device.
  • the receiving device can execute the steps in the embodiment shown in Figs. 2-11.
  • the embodiment of the present application also provides a non-transitory storage medium for storing the software instructions used in the foregoing embodiment, which includes a program for executing the method shown in the foregoing embodiment, when it is on a computer or network device When executed, the computer or network device shown is caused to execute the method in the foregoing method embodiment.
  • the embodiments of the present application also provide a computer program product including computer program instructions.
  • the network node When the computer program product runs on a computer, the network node causes the network node to execute the method in the foregoing method embodiment.
  • any of the device embodiments described above are only illustrative, and the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physically separate.
  • the physical unit can be located in one place or distributed across multiple network units. Some or all of the modules can be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the connection relationship between the modules indicates that they have a communication connection between them, which can be specifically implemented as one or more communication buses or signal lines.
  • the steps of the method or algorithm described in the disclosure of the embodiments of the present application may be implemented in a hardware manner, or may be implemented in a manner in which a processor executes software instructions.
  • Software instructions can be composed of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (erasable programmable ROM, EPROM), electrically erasable programmable read-only memory (electrically erasable programmable read-only memory (EPROM, EEPROM), hard disk, mobile hard disk, optical disk, or any other form of storage medium known in the art.
  • the storage medium is coupled to the processor, so that the processor can read information from the storage medium.
  • the storage medium may also be an integral part of the processor.
  • first, second and other words are used to distinguish the same items or similar items that have basically the same function and function. It should be understood that between “first”, “second” and “nth” There are no logic or timing dependencies, and no restrictions on the number and execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another.
  • the first image may be referred to as the second image, and similarly, the second image may be referred to as the first image. Both the first image and the second image may be images, and in some cases, may be separate and different images.
  • the size of the sequence number of each process does not mean the order of execution.
  • the execution order of each process should be determined by its function and internal logic, and should not correspond to the difference in the embodiments of the present application.
  • the implementation process constitutes any limitation.
  • determining B according to A does not mean that B is determined only according to A, and B can also be determined according to A and/or other information.

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Abstract

一种码字同步方法、接收器及网络设备。该方法在接收端接收数据序列的多个比特中确定备选比特，根据备选比特确定同步位置，所述同步位置用于指示所述数据序列中码字的起始位置。该方法为自同步方法，无需在发送端数据流中插入额外数据，即可实现接收端数据流高精度码字同步的技术效果，其同步性能达到较高的可靠性。

Description

码字同步方法、接收器、网络设备及网络系统
本申请要求于2020年4月10日提交的申请号为202010280832.9、发明名称为“一种码字同步方法、接收器及网络设备”的中国专利申请以及于2020年5月19日提交的申请号为202010424884.9、发明名称为“码字同步方法、接收器、网络设备及网络系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，尤其涉及一种码字同步方法、接收器、网络设备及网络系统。
背景技术
随着生产工艺水平的提高，信道的损耗和噪声已成为限制数据传输速率和距离的关键因素。前向纠错(Forward Error Correction)的出现，为传输中的数据提供了纠错保护，从而提高了信道的数据传输速率以及传输距离。FEC按照对信息序列的处理方式不同可分为分组码(block code)和卷积码(convolutional code)。对于分组码，可再细分为线性分组码(linear block code)与非线性分组码(non-linear block code)。线性分组码由于其编译码实现较为简单而在以太网的开放式系统互联模型(Open System Interconnection Model,OSI)中的物理层(physical layer)以及数据链路层(data link layer)的介质访问控制(media access control)子层中得到广泛应用。
线性分组码的检错及纠错功能实现必须基于完整的码字(codeword)进行，因而需要在数据流中确定码字边界，即找到一个完整码字的开始和结尾，这一过程称为码字同步(codeword synchronization)或者帧同步(frame synchronization)。
目前业界已经有适用于线性分组码的同步方案。以802.3标准内200/400GE中使用的对齐标志(alignment marker,AM)同步方案为例，该方案中每间隔一定长度的码字均须插入一段固定的AM序列，接收端识别该AM序列即可进行码字同步。然而，AM序列的存在相当于在发送端数据流中插入了额外数据，增加了冗余信息。
发明内容
本申请提供了一种自同步的码字同步方法、接收器及网络设备，用于解决AM同步方案中增加额外数据的技术问题。
第一方面，本申请提供了一种码字同步方法。所述方法包括：步骤一，接收数据序列，所述数据序列包括多个比特；步骤二，确定所述数据序列中的备选比特，所述备选比特包括在所述多个比特中；步骤三，根据所述备选比特确定同步位置，所述同步位置用于指示所述数据序列中码字的起始位置。
该方法由网络中的接收设备执行。通过该方法无须在发送端数据流中插入额外数据，即可实现接收端数据流高精度码字同步的技术效果，其同步性能达到较高的可靠性。
在一种可能的实现方式中，所述步骤三包括：对所述备选比特进行验证，当验证成功 时，确定所述备选比特的位置为所述同步位置。
在一种可能的实现方式中，根据所述备选比特在所述数据序列中划分出至少一个第二测试数据块，所述备选比特的位置为所述至少一个第二测试数据块的起始位置；对所述至少一个第二测试数据块的特性值进行验证，当验证成功时，确定所述备选比特的位置为所述同步位置。
在一种可能的实现方式中，对所述至少一个第二测试数据块的特性值进行验证，包括：依次累计所述至少一个第二测试数据块中各个第二测试数据块的特性值以获得累计值，直至所述累计值满足同步条件时，验证成功。
在一种可能的实现方式中，所述特性值的累计值为所述至少一个第二测试数据块中被判定为正确码字的第二测试数据块的数量，所述同步条件为所述累计值大于或等于同步阈值；所述特性值为校验序列中全零序列的数量，所述同步条件为所述累计值大于或等于同步阈值；或者，所述特性值为校验序列中零元素的数量，所述同步条件为所述累计值大于或等于同步阈值；或者，所述特性值为可纠错测试数据块的数量，所述同步条件为所述累计值大于或等于同步阈值；或者，所述特性值为重检验位与原始校验位相同的测试数据块的数量，所述同步条件为所述累计值大于或等于同步阈值；其中，所述测试数据块的长度为n比特，所述测试数据块的前k比特为信息位，所述测试数据块的后n-k比特为所述原始校验位，所述重检验位是根据所述信息位获得的，所述重校验位的长度为n-k比特，所述n和所述k为整数。
在一种可能的实现方式中，对所述至少一个第二测试数据块的特性值进行验证，包括：将所述至少一个第二测试数据块中所有第二测试数据块的特性值相加以获得总值，当所述总值满足同步条件时，验证成功。
在一种可能的实现方式中，所述特性值的总值为所述至少一个第二测试数据块中被判定为正确码字的第二测试数据块的数量，所述特性值的总值为所述至少一个第二测试数据块中被判定为错误码字的第二测试数据块的数量，所述同步条件为所述总值小于或等于同步阈值；或者，所述特性值为校验序列中全零序列的数量，所述同步条件为所述总值大于或等于同步阈值；或者，所述特性值为校验序列中非全零序列的数量，所述同步条件为所述总值小于或等于同步阈值；或者，所述特性值为校验序列中零元素的数量，所述同步条件为所述总值大于或等于同步阈值；或者，所述特性值为校验序列中非零元素的数量，所述同步条件为所述总值小于或等于同步阈值；或者，所述特性值为可纠错测试数据块的数量，所述同步条件为所述总值大于或等于同步阈值；或者，所述特性值为不可纠错测试数据块的数量，所述同步条件为所述总值小于或等于同步阈值；或者，所述特性值为重检验位与原始校验位相同的测试数据块的数量，所述同步条件为所述总值大于或等于同步阈值；或者，所述特性值为重检验位与原始校验位不相同的测试数据块的数量，所述同步条件为所述总值小于或等于同步阈值；其中，所述测试数据块的长度为n比特，所述测试数据块的前k比特为信息位，所述测试数据块的后n-k比特为所述原始校验位，所述重检验位是根据所述信息位获得的，所述重校验位的长度为n-k比特，所述n和所述k为整数。
在一种可能的实现方式中，将所述备选比特的位置作为所述同步位置。
在一种可能的实现方式中，从所述数据序列中选取多个观察比特；从所述多个观察比特中选取所述备选比特。
在一种可能的实现方式中，所述从所述多个观察比特中选取所述备选比特，包括：根据所述多个观察比特从所述数据序列中确定多组第一测试数据块，其中，所述多组第一测试数据块中的每组第一测试数据块包括至少一个第一测试数据块，所述多个观察比特中的每一个观察比特的位置为所述多组第一测试数据块中的每组第一测试数据块的起始位置；根据所述多组第一测试数据块的特性值，从所述多个观察比特中选取一个观察比特作为所述备选比特。
在一种可能的实现方式中，所述根据所述多组第一测试数据块的特性值，从所述多个观察比特中选取一个观察比特作为所述备选比特，包括：依次判断所述多组第一测试数据块中各组第一测试数据块的特性值是否满足备选条件，直至确定出一组第一测试数据块的特性值满足所述备选条件；将满足所述备选条件的所述一组第一测试数据块对应的观察比特作为所述备选比特。
在一种可能的实现方式中，所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块的校验序列中全零序列的数量总值，所述备选条件为所述总值大于或等于同步阈值；或者，所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块的校验序列中非全零序列的数量总值，所述备选条件为所述总值小于或等于同步阈值；或者，所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块的校验序列中零元素的数量总值，所述备选条件为所述总值大于或等于同步阈值；或者，所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块的校验序列中非零元素的数量总值，所述备选条件为所述总值小于或等于同步阈值；或者，所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块中可纠错测试数据块的数量总值，所述备选条件为所述总值大于或等于同步阈值；或者，所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块中不可纠错测试数据块的数量总值，所述备选条件为所述总值小于或等于同步阈值；或者，所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块中重检验位与原始校验位相同的测试数据块的数量总值，所述备选条件为所述总值大于或等于同步阈值；或者，所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块中重检验位与原始校验位不相同的测试数据块的数量总值，所述备选条件为所述总值小于或等于同步阈值；或者，所述一组第一测试数据块的特性值为所述一组第一测试数据块中前X个第一测试数据块的校验序列中全零序列的数量累计值，所述备选条件为所述累计值大于或等于同步阈值；或者，所述一组第一测试数据块的特性值为所述一组第一测试数据块中前X个第一测试数据块的校验序列中零元素的数量累计值，所述备选条件为所述累计值大于或等于同步阈值；或者，所述一组第一测试数据块的特性值为所述一组第一测试数据块中前X个第一测试数据块中可纠错测试数据块的数量累计值，所述备选条件为所述累计值大于或等于同步阈值；或者，所述一组第一测试数据块的特性值为所述一组第一测试数据块中前X个第一测试数据块中重检验位与原始校验位相同的测试数据块的数量累计值，所述备选条件为所述累计值大于或等于同步阈值；其中，所述测试数据块的长度为n比特，所述测试数据块的前k比特为信息位，所述测试数据块的后n-k比特为所述原始校验位，所述重检验位是根据所述信息位获得的，所述重校验位的长度为n-k比特，所述n，所述k和所述X为整数。
在一种可能的实现方式中，所述根据所述多组第一测试数据块的特性值，从所述多个观察比特中选取一个观察比特作为所述备选比特，包括：比较所述多组第一测试数据块中每组第一测试数据块的特性值，将所述特性值为极值的一组第一测试数据块对应的观察比特作为所述备选比特。
在一种可能的实现方式中，所述特性值为校验序列中全零序列的数量，所述极值为最大值；或者，所述特性值为校验序列中非全零序列的数量，所述极值为最小值；或者，所述特性值为校验序列中零元素的数量，所述极值为最大值；或者，所述特性值为校验序列中非零元素的数量，所述极值为最小值；或者，所述特性值为可纠错测试数据块的数量，所述极值为最大值；或者，所述特性值为不可纠错测试数据块的数量，所述极值为最小值；或者，所述特性值为重检验位与原始校验位相同的测试数据块的数量，所述极值为最大值；或者，所述特性值为重检验位与原始校验位不相同的测试数据块的数量，所述极值为最小值；其中，所述测试数据块的长度为n比特，所述测试数据块的前k比特为信息位，所述测试数据块的后n-k比特为所述原始校验位，所述重检验位是根据所述信息位获得的，所述重校验位的长度为n-k比特，所述n和所述k为整数。
在一种可能的实现方式中，所述从所述数据序列中选取多个观察比特，包括：从所述数据序列中每间隔T个比特选取一个比特，作为所述观察比特，所述T为大于零的整数；或者，从所述数据序列中每间隔L*n+T个比特选取一个比特，作为所述观察比特，所述L为间隔的测试数据块的数量，所述测试数据块的长度为所述n个比特，所述L和所述T为大于零的整数。
在一种可能的实现方式中，所述数据序列为调制信号，所述数据序列包括多个调制码元，其中，所述从所述第一数据中选取多个观察比特，包括：从所述数据序列中每间隔T个调制码元，选取调制码元的起始比特，作为所述观察比特，所述T为大于零的整数；或者，从所述数据序列中每间隔L*m+T个调制码元，选取调制码元的起始比特，作为所述观察比特，所述L为间隔的测试数据块的数量，所述测试数据块的长度为所述m个调制码元，所述L和所述T为大于零的整数。
在一种可能的实现方式中，所述观察比特的数量为P，所述P为正整数，所述码字的长度为所述P个比特。
在一种可能的实现方式中，所述步骤二中，所述确定所述数据序列中的备选比特包括，确定第一子序列中的备选比特，所述步骤三中，所述根据所述备选比特在所述数据序列中划分出至少一个第二测试数据块包括，根据所述备选比特在第二子序列中划分出至少一个第二测试数据块，所述第一子序列和所述第二子序列包括在所述数据序列中，所述第二子序列与所述第一子序列相同、部分相同或不同。
在一种可能的实现方式中，在所述步骤三之后，所述方法还包括：步骤四，响应于所述数据序列为失锁状态，确定所述数据序列的更新同步位置。
在一种可能的实现方式中，所述确定所述数据序列的更新同步位置，包括：重新执行所述步骤二和所述步骤三，将重新执行的步骤三所确定的同步位置作为所述更新同步位置。
在一种可能的实现方式中，在所述步骤三之后、所述步骤四之前，所述方法还包括：根据所述同步位置从所述数据序列中划分出多个同步码字，所述同步位置为所述多个同步码字的起始位置；对所述多个同步码字的特性值进行验证，当验证失败时，确定所述数据 序列为所述失锁状态。
在一种可能的实现方式中，对所述多个同步码字的特性值进行验证，包括：依次累计所述多个同步码字中各个同步码字的特性值以获得累计值，直至所述累计值满足失锁条件时，验证失败。
在一种可能的实现方式中，所述特性值为校验序列中非全零序列的数量，所述失锁条件为所述累计值大于或等于同步阈值；或者，所述特性值为校验序列中非零元素的数量，所述失锁条件为所述累计值大于或等于同步阈值；或者，所述特性值为不可纠错码字的数量，所述失锁条件为所述累计值大于或等于同步阈值；或者，所述特性值为重检验位与原始校验位不相同的码字的数量，所述失锁条件为所述累计值大于或等于同步阈值；其中，所述码字的长度为n比特，所述码字的前k比特为信息位，所述码字的后n-k比特为所述原始校验位，所述重检验位是根据所述信息位获得的，所述重校验位的长度为n-k比特，所述n和所述k为整数。
在一种可能的实现方式中，对所述多个同步码字的特性值进行验证，包括：将所述多个同步码字中所有同步码字的特性值相加以获得总值，当所述总值满足失锁条件时，验证失败。
在一种可能的实现方式中，所述特性值为校验序列中全零序列的数量，所述失锁条件为所述总值小于或等于同步阈值；或者，所述特性值为校验序列中非全零序列的数量，所述失锁条件为所述总值大于或等于同步阈值；或者，所述特性值为校验序列中零元素的数量，所述失锁条件为所述总值小于或等于同步阈值；或者，所述特性值为校验序列中非零元素的数量，所述失锁条件为所述总值大于或等于同步阈值；或者，所述特性值为可纠错码字的数量，所述失锁条件为所述总值小于或等于同步阈值；或者，所述特性值为不可纠错码字的数量，所述失锁条件为所述总值大于或等于同步阈值；或者，所述特性值为重检验位与原始校验位相同的码字的数量，所述失锁条件为所述总值小于或等于同步阈值；或者，所述特性值为重检验位与原始校验位不相同的码字的数量，所述失锁条件为所述总值大于或等于同步阈值；其中，所述码字的长度为n比特，所述码字的前k比特为信息位，所述码字的后n-k比特为所述原始校验位，所述重检验位是根据所述信息位获得的，所述重校验位的长度为n-k比特，所述n和所述k为整数。
在一种可能的实现方式中，所述数据序列为线性分组码。
第二方面，本申请提供了一种通信设备，执行第一方面或第一方面的任意一种可能的实现方式中的方法。具体地，该网络设备包括用于执行第一方面或第一方面的任意一种可能的实现方式中的方法的单元。
第三方面，本申请提供了一种通信设备，该通信设备包括：处理器、通信接口和存储器。通信接口可以是收发器。存储器可以用于存储程序代码，处理器用于调用存储器中的程序代码执行前述第一方面或第一方面的任意一种可能的实现方式中的方法，此处不再赘述。
第四方面，本申请提供了一种网络系统，该网络系统包括发送设备和接收设备，所述接收设备为前述第二或第三方面提供的通信设备，所述接收设备用于接收所述发送设备发送的数据序列。
第五方面，本申请提供了一种计算机可读存储介质，所述计算机可读存储介质中存储 有指令，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
第六方面，本申请提供了一种包括计算机程序指令的计算机程序产品，当该计算机程序产品在网络设备上运行时，使得网络设备执行第一方面或第一方面的任意一种可能的实现方式中提供的方法。
第七方面，本申请提供了一种芯片，包括存储器和处理器，存储器用于存储计算机程序，处理器用于从存储器中调用并运行该计算机程序，以执行上述第一方面及其第一方面任意可能的实现方式中的方法。
可选地，上述芯片仅包括处理器，处理器用于读取并执行存储器中存储的计算机程序，当计算机程序被执行时，处理器执行第一方面或第一方面任意可能的实现方式中的方法。
第八方面，本申请提供了一种网络节点，该网络节点包括：主控板和接口板。主控板包括：第一处理器和第一存储器。接口板包括：第二处理器、第二存储器和接口卡。主控板和接口板耦合。
第一存储器可以用于存储程序代码，第一处理器用于调用第一存储器中的程序代码执行如下操作：确定所述数据序列中的备选比特，所述备选比特包括在所述多个比特中；根据所述备选比特确定同步位置，所述同步位置用于指示所述数据序列中码字的起始位置。
第二存储器可以用于存储程序代码，第二处理器用于调用第二存储器中的程序代码，触发接口卡执行如下操作：接收数据序列，所述数据序列包括多个比特。
在一种可能的实现方式中，主控板和接口板之间建立进程间通信协议(inter-process communication，IPC)通道，主控板和接口板之间通过IPC通道进行通信。
附图说明
为了更清楚地说明本申请的技术方案，下面将对实施例中使用的附图作简单地介绍。显而易见地，下面附图只是本申请的一些实施例的附图，对于本领域普通技术人员来说，在不付出创造性劳动性的前提下，还可以根据这些附图获得同样能实现本申请的其他技术方案和附图。
图1为本申请实施例提供的一种码字的同步位置；
图2为本申请实施例提供的一种同步流程图；
图3为本申请实施例提供的一种同步流程图；
图4为本申请实施例提供的一种观察比特的选择方法；
图5为本申请实施例提供的一种观察比特的选择方法；
图6为本申请实施例提供的一种观察比特的选择方法；
图7为本申请实施例提供的一种观察比特的选择方法；
图8为本申请实施例提供的一种同步锁定判断第一阶段；
图9为本申请实施例提供的一种同步锁定判断第二阶段；
图10为本申请实施例提供的一种同步失锁判断；
图11为本申请实施例提供的一种一种同步流程图；
图12为本申请实施例提供的一种通信设备的结构示意图；
图13为本申请实施例提供的一种通信设备的结构示意图；
图14为本申请实施例提供的一种通信设备的结构示意图。
具体实施方式
下面结合附图，对本申请的实施例进行描述。
由于信道损耗和噪声的影响，当信号在信道中传输时会出现错误，影响通信系统的可靠性。当信号表示为多个比特组成的数据序列的形式时，传输错误具体表现为数据序列中部分比特的值发生变化，即出现错误比特。FEC是一种在通信系统中控制传输错误的技术，在FEC技术中，冗余信息与原始数据序列一起发送，以用于传输过程中的错误恢复，降低比特误码率。FEC按照对信息序列的处理方式不同可分为分组码和卷积码。对于分组码，可再细分为线性分组码与非线性分组码。以线性分组码中的系统码(systematic code)为例，发送端将原始数据序列进行分组，每组的长度为k比特(bit)。进而在每个分组中，按照特定编码规则，增加n-k比特的冗余信息，也称为校验位(parity)，最终得到长度为n比特的码字。从而，长度为n比特的码字中，前k比特为原始数据，也称为信息位，后n-k比特为校验位，整个码字由信息位和校验位组成。码字经过信道到达接收端之后，如果码字内错误比特的个数在可纠错范围之内，接收端通过解码过程即可检查并纠正错误，将接收到的码字恢复为发送端发送的原始数据，从而抵抗信道带来的干扰，提高通信系统的可靠性。线性分组码的检错及纠错功能的实现必须基于完整的码字进行，因而，在对接收端所收到的数据序列进行解码之前，需要在数据序列中确定码字边界，即找到一个完整码字的起始位置和结束位置。这一过程称为码字同步或者帧同步。如果码字同步不正确，即未能确定真正的码字边界，则后续解码过程中无法达到检错或纠错的应有效果，甚至可能增加误码，造成通信系统性能的恶化。
每个码字的起始位置也可以称为同步位置(synchronization position)。同样以系统码为例，图1示出了码字中的同步位置。如图1所示，整个码字的长度为n比特，其中前k比特为原始数据(information bits)，后n-k比特为通过编码规则加入的额外校验位(parity bits)，同步位置为码字的起始位置，即码字中的首个比特所在的位置。其中，n和k均为整数。由此可见，在数据序列中，同步位置的数量为多个，且多个同步位置相互关联，其中每个同步位置之间的间隔是固定的，该间隔即为码字的长度。
在本申请实施例中，虽然采用系统码进行举例说明，但本申请并不限于系统码，也适用于非系统码(non-systematic code)，本申请能够适用于所有线性分组码的通信系统。所述线性分组码包括但不限于里德-所罗门码(Reed-Solomon code,RS code)，博斯-查德胡里-霍克金亨码(Bose–Chaudhuri–Hocquenghem code,BCH code)，低密度奇偶校验码(Low-Density Parity-Check code,LDPC code)，汉明码(Hamming code)，格莱码(Golay code)，以及里德-穆勒(Reed–Muller code)，等等。
本申请实施例提供了码字同步方法以及基于该方法的设备和系统。这些方法、设备和系统基于同一发明构思。该方法可以包括两个阶段，在第一阶段中，根据多个观察比特划分多组第一测试数据块，根据多组第一测试数据块从多个观察比特中选取一个最可能位于同步位置的观察比特，在第二阶段中，根据所述最可能位于同步位置的观察比特划分一组第二测试数据块，根据该组第二测试数据块判断所述最可能位于同步位置的观察比特是否为同步位置。该方法还可以只包括所述第一阶段，在确定选取所述最可能位于同步位置的观察比特后，直接将该最可能位于同步位置的观察比特作为同步位置。在该方法中，无需 在发送端数据流中插入额外数据，即可实现接收端数据流高精度码字同步的技术效果，其同步性能达到较高可靠性。
图2示出了本申请实施例的方法流程图。该方法应用于通信网络中的接收端设备。所述接收端设备可以是执行FEC的各种设备，包括但不限于路由器、交换机和服务器。该方法的步骤包括：
S210,接收数据序列。
具体的，接收端接收来自发送端的数据序列，所述数据序列包括多个比特，每个比特为二进制数据。即所述数据序列是多个比特组成的序列，也可以称为比特序列。在一些实施例中，所述数据序列为线性分组码。所述数据序列经过信道传输，可能存在误码，需要进行检错及纠错等操作。
S220,第一阶段，确定所述数据序列中的备选比特，所述备选比特包括在所述多个比特中。所述备选比特是多个观察比特中最可能位于同步位置的观察比特，或者说，所述备选比特的位置是最可能的同步位置。
如图3所示，在第一阶段中，可以包括S221和S222两个步骤：
S221,接收端从接收到的数据序列中选取多个观察比特。这些观察比特的位置包括所述同步位置，即这些观察比特中某个观察比特的位置可能为所述同步位置，或者说，这些观察比特的位置能够覆盖所述同步位置。
可选的，在第一阶段中，该方法在确定所述数据序列中的备选比特时，仅利用所述数据序列中的一部分，例如所述数据序列中的第一子序列，即确定第一子序列中的备选比特。所述第一子序列包括多个比特，所述第一子序列可以是所述数据序列中的任何一个部分。接收端从第一子序列中选取所述多个观察比特，这些观察比特的位置可能为同步位置。例如，所述观察比特的数量为P，P为大于1的整数。
可选的，从接收到的数据序列中选取多个观察比特时，所述多个观察比特中每两个相邻的观察比特之间的间隔是相同的，所述多个观察比特中每个观察比特的位置依次向后移动。
在码字同步过程中，引入测试数据块的概念。所述测试数据块为数据序列中的一部分，所述测试数据块由连续的若干比特组成，所述测试数据块的长度与所述码字的长度相同。可以说，所述测试数据块是用于模拟一个码字的。
可选的，所述多个观察比特可以位于同一个测试数据块内，所述多个观察比特中每个观察比特在同一个测试数据块内的位置依次向后移动。具体的，每间隔T个比特选取一个比特作为所述观察比特，所述T为大于零的整数。图4示出了观察比特的选取方式，其中b 1,b 2,b 3为相邻的三个观察比特，分别对应数据序列中的x(0),x(1),x(2)三个比特。每个观察比特之间的间隔为1比特，即T为1。三个观察比特位于同一个测试数据块内，例如图4中以x(0)为起始位置所划分出的测试数据块内。在该测试数据块内，b 1所在的位置为该测试数据块内的第一个位置，b 2,b 3所在的位置依次为该测试数据块内的第二个和第三个位置，即三个观察比特中每个观察比特在同一个测试数据块内的位置依次向后移动。虽然图4仅示出了三个观察比特，但更多的观察比特的选取方式可以由此类推，在此不再赘述。
可选的，所述多个观察比特可以分别位于多个测试数据块内，所述多个观察比特中每个观察比特在每个测试数据块内的位置依次向后移动。具体的，每间隔L*n+T个比特选取 一个比特作为所述观察比特，所述L为间隔测试数据块的数量，所述测试数据块的长度为所述n个比特，所述L和所述T为大于零的整数。图5示出了观察比特的选取方式，其中b 1,b 2为相邻的两个观察比特，分别对应数据序列中的x(0),x(L*n+1)两个比特。两个观察比特分别位于两个不同的测试数据块内，例如图5中以x(0)为起始位置所划分出的测试数据块内和以x(L*n)为起始位置所划分出的测试数据块内。两个测试数据块之间的间隔为L个测试数据块，两个观察比特之间的间隔为L*n+1个比特，即T为1。在以x(0)为起始位置所划分出的测试数据块内，b 1所在的位置为该测试数据块内的第一个位置，在以x(L*n)为起始位置所划分出的测试数据块内，b 2所在的位置为该测试数据块内的第二个位置，即两个观察比特中每个观察比特在每个测试数据块内的位置依次向后移动。虽然图5仅示出了两个观察比特，但更多的观察比特的选取方式可以由此类推，在此不再赘述。此时，相邻的观察比特之间的间隔更远，观察比特之间的相关性更低，从而能够减少突发误码带来的影响，提高码字同步的准确性。
可选的，在选取所述多个观察比特时，可以使得所述多个观察比特的位置遍历测试数据块内的所有位置。
例如，当所述多个观察比特位于同一个测试数据块内时，可以使得所述多个观察比特的位置遍历该同一个测试数据块内的所有位置，即使得所述多个观察比特的位置遍历该同一个码字内的所有位置。在图4所示的观察比特的选取方式中，码字的长度为n比特，观察比特的数量为P，当P等于n时，所述多个观察比特的位置即可遍历同一个测试数据块内的所有位置。
例如，当所述多个观察比特分别位于多个测试数据块内时，所述多个测试数据块中每个测试数据块内的相同位置视为一个等同位置，例如，多个测试数据块中每个测试数据块内的第一个位置视为一个等同位置，可以使得所述多个观察比特的位置遍历所有等同位置，即所述多个观察比特的位置遍历多个测试数据块内的所有位置。在图5所示的观察比特的选取方式中，码字的长度为n比特，则等同位置的数量为n，观察比特的数量为P，当P等于n时，所述多个观察比特的位置即可遍历所有等同位置，即所述多个观察比特的位置即可遍历多个测试数据块内的所有位置。
可选的，在选取所述多个观察比特时，也可以使得所述多个观察比特的位置不遍历码字内的所有位置。即所述P的值可以小于所述n。
如果所述多个观察比特的位置遍历测试数据块内的所有位置，将使得码字同步结果的准确度更高。然而，随着观察比特的数量增加，码字同步过程所消耗的系统资源也将增加。
在发送端可以对信号进行调制，以获得调制信号。常用的调制方式包括脉冲幅度调制(Pulse-Amplitude Modulation,PAM)、正交幅度调制(Quadrature Amplitude Modulation,QAM)、相移键控(Phase-Shift Keying,PSK)等。调制信号的脉冲幅度可以包括多个阶次，该多个阶次的数量可以称为调制的阶数。以PAM为例，当调制信号的脉冲幅度有2个阶次时，调制阶数为2，调制方式可以称为PAM2；当调制信号的脉冲幅度有4个阶次时，调制阶数为4，调制方式可以称为PAM4，以此类推。调制信号可以表示为调制的数据序列。与未调制的数据序列相比，调制的数据序列的基本单元由比特变更为码元，即调制的数据序列中，码字由若干个码元组成，码元由若干个比特组成。码元中包括的比特数量与调制的阶数相关。当调制阶数为M时，码元包括的比特数量为log 2M，其中M为2的整 数倍。例如，当调制阶数为2时，码元中包括1个比特，当调制阶数为4时，码元中包括2个比特。由此可见，码字的起始位置必然也是某个码元的起始位置，而不会是码元的其他位置。因此，对于调制的信号来说，在选取所述多个观察比特时，可以只考虑码元的起始比特，而不用考虑码元的其他比特。
可选的，所述多个观察比特分别为多个码元的起始比特，所述多个码元在同一个测试数据块内，且所述多个码元在同一个测试数据块内的位置依次向后移动。具体的，每间隔T个调制码元，选取调制码元的起始比特，作为所述观察比特，所述T为大于零的整数。也就是说，每间隔T·log 2M个比特，选取调制码元的起始比特，作为所述观察比特。图6示出了观察比特的选取方式，其中数据序列为调制信号，调制阶数为4，则该数据序列包括多个调制码元，每个码元中包括2个比特，例如x(0)和x(1)组成的码元，x(2)和x(3)组成的码元，以及x(4)和x(5)组成的码元，以此类推。其中b 1,b 2,b 3为相邻的三个观察比特，分别对应数据序列中的x(0),x(2),x(4)三个比特。所述三个观察比特分别为三个码元的起始比特，三个码元为x(0)和x(1)组成的码元，x(2)和x(3)组成的码元，以及x(4)和x(5)组成的码元。所述三个码元中每两个相邻码元之间间隔1个码元，即T为1。并且，所述三个码元在同一个测试数据块内的位置依次向后移动。虽然图6仅示出了三个观察比特，但更多的观察比特的选取方式可以由此类推，在此不再赘述。
可选的，所述多个观察比特分别为多个码元的起始比特，所述多个码元分别位于多个测试数据块内，且所述多个码元中每个码元在每个测试数据块内的位置依次向后移动。具体的，每间隔L*m+T个调制码元，选取调制码元的起始比特，作为所述观察比特，所述L为间隔测试数据块的数量，所述测试数据块的长度为所述m个调制码元，所述L和所述T为大于零的整数。也就是说，每间隔(L·m+T)·log 2M个比特，选取调制码元的起始比特，作为所述观察比特。图7示出了观察比特的选取方式，其中数据序列为调制信号，调制阶数为4，则该数据序列包括多个调制码元，每个码元中包括2个比特，例如x(0)和x(1)组成的码元，x(L*n)和x(L*n+1)组成的码元，以及x(L*n+2)和x(L*n+3)组成的码元，以此类推。其中b1,b2为相邻的两个观察比特，分别对应数据序列中的x(0),x(L*n+2)两个比特。所述两个观察比特分别为两个码元的起始比特，两个码元为x(0)和x(1)组成的码元，x(L*n+2)和x(L*n+3)组成的码元。并且，所述两个观察比特分别位于两个不同的测试数据块内，例如图7中以x(0)为起始位置所划分出的测试数据块内和以x(L*n)为起始位置所划分出的测试数据块内。所述两个测试数据块之间的间隔为L个测试数据块，两个观察比特之间的间隔为L*m+1个码元，即T为1。在以x(0)为起始位置所划分出的测试数据块内，b 1所在的码元为该测试数据块内的第一个码元，在以x(L*n)为起始位置所划分出的测试数据块内，b 2所在的码元为该测试数据块内的第二个码元，即两个码元中每个码元在每个测试数据块内的位置依次向后移动。虽然图7仅示出了两个观察比特，但更多的观察比特的选取方式可以由此类推，在此不再赘述。此时，相邻的观察比特之间的间隔更远，观察比特之间的相关性更低，从而能够减少突发误码带来的影响，提高码字同步的准确性。
S222,从所述多个观察比特中选取备选比特。所述备选比特是所述多个观察比特中的一个观察比特，且所述备选比特是最可能位于同步位置的观察比特。具体的，S222可以包括S2221和S2222两个步骤。
S2221,根据所述多个观察比特从数据序列中划分出多组第一测试数据块，所述多组 第一测试数据块与所述多个观察比特一一对应。具体的，所述多组第一测试数据块中的每组第一测试数据块包括至少一个第一测试数据块，所述多个观察比特中的每一个观察比特的位置为所述多组第一测试数据块中的每组第一测试数据块的起始位置。
可选的，分别以所述多个观察比特中的每个观察比特为起始位置，选取其后的N个测试数据块，其中N为大于等于1的整数。所述多个观察比特中的每一个观察比特的位置为所述多组第一测试数据块中的每组第一测试数据块的起始位置。以每个观察比特为起始位置选取的N个测试数据块为一组第一测试数据块，则分别以多个观察比特中的每个观察比特为起始位置，选取的多组N个测试数据块为所述多组第一测试数据块。所述多组第一测试数据块中的每组第一测试数据块对应作为这组第一测试数据块的起始位置的一个观察比特，即所述多组第一测试数据块与所述多个观察比特一一对应。
可选的，所述N个测试数据块可以是连续的，即每组第一测试数据块包括连续的N个数据块。当每个测试数据块的长度为n比特时，即选取其后的连续N*n个比特，即获得所述N个测试数据块。
可选的，所述N个测试数据块也可以是不连续的，所述N个测试数据块中每个测试数据块的起始位置均与该组测试数据块对应的观察比特相关联。具体的，每个测试数据块的起始位置与该组测试数据块对应的观察比特的间隔均为码字的长度的整数倍，即所述N个测试数据块中每两个测试数据块的间隔均为码字的长度的整数倍。并且，所述N个测试数据块中每两个测试数据块的间隔可以相同，也可以不同。
如图4所示，以观察比特b 1为起始位置，选取其后的一组第一测试数据块，该组第一测试数据块包括N个测试数据块，即B 1,B 2,…,B N，每个测试数据块的长度为n比特。类似的，以观察比特b 2或b 3为起始位置，也能够分别选取出其后的一组第一测试数据块。分别以观察比特b 1，b 2或b 3为起始位置，则选取出所述多组第一测试数据块。图5、图6和图7中，所述多组第一测试数据块的方式与图4类似，在此不再赘述。
S2222,根据所述多组第一测试数据块的特性值，从所述多个观察比特中选取一个观察比特作为所述备选比特，即所述最可能位于同步位置的观察比特。
可选的，当根据所述多组第一测试数据块的特性值，从所述多个观察比特中选取一个观察比特作为所述最可能位于同步位置的观察比特时，选取方式可以是提前终止的选取方式。具体的，依次判断所述多组第一测试数据块中各组第一测试数据块的特性值是否满足备选条件，直至确定出一组第一测试数据块的特性值满足所述备选条件，将满足所述备选条件的所述一组第一测试数据块对应的观察比特作为所述备选比特。
可选的，当根据所述多组第一测试数据块的特性值，从所述多个观察比特中选取一个观察比特作为所述最可能位于同步位置的观察比特时，选取方式可以是遍历的选取方式。具体的，比较所述多组第一测试数据块中每组第一测试数据块的特性值，将所述特性值为极值的一组第一测试数据块对应的观察比特作为所述备选比特。
在所述提前终止的选取方式和所述遍历的选取方式下，针对特性值的计算都可以并行进行，即采用多个计算单元同时计算多个测试数据块的特性值。例如，采用10个计算单元同时计算10个测试数据块的特性值。并行的计算方式能够节约计算时间，降低时延。
可选的，所述特性值可以是校验序列的特性值。
针对每个线性分组码可以生成一个校验矩阵(parity-check matrix)，该校验矩阵描述 了线性分组码的码字内的数据之间的线性关系，并且该校验矩阵可以应用于解码过程。当所述数据序列为线性分组码时，针对所述数据序列也存在所述校验矩阵，可以称为所述数据序列的校验矩阵。具体的，数据序列与该数据序列的校验矩阵之间，满足下列关系式：
Figure PCTCN2021086736-appb-000001
其中，C为数据序列中的一个码字，S为所述码字的校验序列，H为该数据序列的校验矩阵。由上述关系式(1)可知，数据序列中码字的校验序列由码字与该数据序列的校验矩阵的转置矩阵相乘而得，且所述校验序列为一个零向量，也即一个全零矩阵。
如上所述，当该数据序列为接收端所接收到的数据序列时，需要在数据序列中确定码字的起始位置。如果没有以正确的起始位置从数据序列中划分码字，则得到的码字将不再满足上述关系式(1)。此时，该数据序列中码字的校验序列可以用下列关系式表示：
S R＝R·H T       (2)
其中，R为接收端所接收的数据序列中的一个码字，S R为该码字的校验序列，H为发送端所发送的原始数据序列的校验矩阵。在上述关系式(2)中，接收端所接收的数据序列中的码字的校验序列，为该码字与发送端所发送的原始数据序列的校验矩阵的转置矩阵的乘积。由上述分析可知，对于一个接收码字，码字内没有出现错误比特时，S R是全零矩阵；当码字内存在错误比特时，S R极大概率不再为全零矩阵。因此，可以利用接收端所接收的数据序列中测试数据块的校验序列来实现码字同步。具体的，可以利用接收端所接收的数据序列中测试数据块的校验序列，从所述多个观察比特中选取一个观察比特作为所述最可能位于同步位置的观察比特。
可选的，分别计算所述多组第一测试数据块中每组第一测试数据块的校验序列。
如图4所示，计算以观察比特b 1为起始比特的一组第一测试数据块的校验序列，即图4所示的S (1)，包括S 1 (1),S 2 (1),…,S N (1)，分别对应测试数据块B 1,B 2,…,B N。以此类推，分别计算以观察比特b 2,b 3为起始比特的一组第一测试数据块的校验序列，即图4所示的S (2),S (3)。虽然图4仅示出了以三个观察比特为起始比特的一组第一测试数据块的校验序列的计算方式，但更多的校验序列的计算方式可以由此类推，在此不再赘述。图5、图6和图7中，所述多组第一测试数据块的校验序列的计算方式与图4类似，在此不再赘述。
例如，所述特性值可以是校验序列中全零序列的数量。当采取上述提前终止的选取方式时，所述备选条件与所述特性值相关联。所述备选条件可以是一组第一测试数据块的特性值大于或等于同步阈值。具体的，依次判断所述各组第一测试数据块的校验序列中全零序列的数量与同步阈值的关系，直至确定出一组第一测试数据块的校验序列中全零序列的数量大于或等于同步阈值时，就将满足所述备选条件的所述一组第一测试数据块对应的观察比特作为所述备选比特。一组第一测试数据块对应的观察比特，也就是作为该组第一测试数据块的起始比特的观察比特。
所述同步阈值的取值可以通过仿真分析获得。例如，将一段数据序列作为接收端所接收到的数据序列，设计该数据序列的误码率在可接受的范围内，分别统计基于同步位置所划分的一组测试数据块的校验序列中全零序列的数量，以及基于非同步位置所划分的一组测试数据块的校验序列中全零序列的数量，根据两者的区别确定同步阈值，以使得所述同步阈值能够用于区别同步位置和非同步位置。
当特性值为校验序列中全零序列的数量，采取上述提前终止的选取方式时，所述最可 能位于同步位置的观察比特的选取过程可以参见图4。其中，同步阈值可以为2。如图4所示，依次判断校验序列S (1),S (2),S (3)中全零序列的数量与同步阈值的关系，例如，第一组第一测试数据块的校验序列中全零序列的数量Q 1＝0，小于所述同步阈值，第二组第一测试数据块的校验序列中全零序列的数量Q 2＝2，等于所述同步阈值，则选取b 2为所述最可能位于同步位置的观察比特。并且，当判断至b 2时，确定b 2满足所述备选条件，则不再判断后续的观察比特对应的校验序列中全零序列的数量与同步阈值的关系，即不再判断S (3)中全零序列的数量与同步阈值的关系。
可选的，在上述提前终止的选取方式中，对于每组第一测试数据块的特性值，也可以采取提前终止的统计方式。也就是说，所述一组第一测试数据块的特性值可以是所述一组第一测试数据块中所有第一测试数据块的校验序列中全零序列的数量总值，相应的，所述备选条件可以是所述总值大于或等于同步阈值。如图4所示的选取过程中，依次判断各组校验序列S (1),S (2),S (3)中全零序列的数量与同步阈值的关系时，对于每组第一测试数据块，依次计算其中每个测试数据块的校验序列，当校验序列为全零序列时，则将全零序列的数量增加1，当所述全零序列的数量累积值满足备选条件，即所述全零序列的数量累积值大于或等于所述同步阈值时，则认为该组第一测试数据块已经满足备选条件，对于该组中后续未计算校验序列的测试数据块将不再进行计算。例如，对于第二组第一测试数据块来说，如果S 1 (2),S 2 (2)均为全零序列，则认为第二组第一测试数据块的校验序列中全零序列的数量Q 2已累积至2，达到所述同步阈值，该组第一测试数据块已经满足备选条件，则选取b 2为所述最可能位于同步位置的观察比特，不再计算后续S 3 (2)至S N (2)的校验序列。可选的，在上述提前终止的选取方式中，对于每组第一测试数据块的特性值，也可以采取遍历的统计方式。也就是说，所述一组第一测试数据块的特性值可以是所述一组第一测试数据块中前X个第一测试数据块的校验序列中全零序列的数量累计值，相应的，所述备选条件可以是所述累计值大于或等于同步阈值。在具体选取过程中，计算该组中每个第一测试数据块的校验序列，以确定该组校验序列中全零序列的数量总值是否满足备选条件，即该组校验序列中全零序列的数量总值是否大于或等于所述同步阈值，具体操作过程在此不再赘述。
例如，所述特性值可以是校验序列中全零序列的数量。当采取上述遍历的选取方式时，所述极值与所述特性值相关联。所述极值可以是最大值。具体的，可以统计所述每组第一测试数据块的校验序列中全零序列的数量，确定全零序列的数量最多的一组第一测试数据块，将该组第一测试数据块对应的观察比特作为所述最可能位于同步位置的观察比特。
当特性值为校验序列中全零序列的数量，采取上述遍历的选取方式时，所述最可能位于同步位置的观察比特的选取过程也可以参见图4。如图4所示，分别统计校验序列S (1),S (2),S (3)中全零序列的数量，分别记为Q 1,Q 2,Q 3,确定其中的最大数值，例如，Q 1＝0,Q 2＝0,Q 3＝2,即最大数值为Q 3＝2，则选取b 3为所述最可能位于同步位置的观察比特，b 3所在的位置为最可能的同步位置。
例如，所述特性值可以是校验序列中非全零序列的数量。当采取上述提前终止的选取方式时，所述备选条件与所述特性值相关联。所述备选条件可以是一组第一测试数据块的特性值小于或等于同步阈值。具体的，依次判断所述各组第一测试数据块的校验序列中非全零序列的数量与同步阈值的关系，直至确定出一组第一测试数据块的校验序列中非全零序列的数量小于或等于同步阈值时，就将满足所述备选条件的所述一组第一测试数据块对 应的观察比特作为所述备选比特。所述同步阈值的取值也可以通过仿真分析获得，具体过程与全零序列对应的同步阈值类似，在此不再赘述。
例如，所述特性值可以是校验序列中非全零序列的数量。当采取上述遍历的选取方式时，所述极值与所述特性值相关联。所述极值可以是最小值。具体的，可以统计所述每组第一测试数据块的校验序列中非全零序列的数量，确定非全零序列的数量最少的一组第一测试数据块，将该组第一测试数据块对应的观察比特作为所述最可能位于同步位置的观察比特。
例如，所述特性值可以是校验序列中零元素的数量。当采取上述提前终止的选取方式时，所述备选条件与所述特性值相关联。所述备选条件可以是一组第一测试数据块的特性值大于或等于同步阈值。具体的，依次判断所述各组第一测试数据块的校验序列中零元素的数量与同步阈值的关系，直至确定出一组第一测试数据块的校验序列中零元素的数量大于或等于同步阈值时，就将满足所述备选条件的所述一组第一测试数据块对应的观察比特作为所述备选比特。所述同步阈值的取值也可以通过仿真分析获得。
例如，所述特性值可以是校验序列中零元素的数量。当采取上述遍历的选取方式时，所述极值与所述特性值相关联。所述极值可以是最大值。具体的，可以统计所述每组第一测试数据块的校验序列中零元素的数量，确定零元素的数量最多的一组第一测试数据块，将该组第一测试数据块对应的观察比特作为所述最可能位于同步位置的观察比特。
例如，所述特性值可以是校验序列中非零元素的数量。当采取上述提前终止的选取方式时，所述备选条件与所述特性值相关联。所述备选条件可以是一组第一测试数据块的特性值小于或等于同步阈值。具体的，依次判断所述各组第一测试数据块的校验序列中非零元素的数量与同步阈值的关系，直至确定出一组第一测试数据块的校验序列中非零元素的数量小于或等于同步阈值时，就将满足所述备选条件的所述一组第一测试数据块对应的观察比特作为所述备选比特。所述同步阈值的取值也可以通过仿真分析获得。
例如，所述特性值可以是校验序列中非零元素的数量。当采取上述遍历的选取方式时，所述极值与所述特性值相关联。所述极值可以是最小值。具体的，可以统计所述每组第一测试数据块的校验序列中非零元素的数量，确定非零元素的数量最少的一组第一测试数据块，将该组第一测试数据块对应的观察比特作为所述最可能位于同步位置的观察比特。
当所述特性值为校验序列中非全零序列、零元素或非零元素时，结合图4所示的数据序列的具体实现过程，可以参考当所述特性值为校验序列中全零序列时的介绍，在此不再赘述。
可选的，所述特性值可以是可纠错特性值。接收端在数据序列中划分出码字后，能够确定码字的状态，所述状态包括可纠错状态和不可纠错状态。当码字处于可纠错状态时，该码字也称为可纠错码字；当码字处于不可纠错状态时，该码字也称为不可纠错码字。一组码字的可纠错特性值可以与该组码字中码字的状态相关联。类似的，对于接收端接收到的数据序列中划出的测试数据块来说，也能够确定测试数据块的状态，所述状态包括可纠错状态和不可纠错状态。当测试数据块处于可纠错状态时，该测试数据块也称为可纠错测试数据块；当测试数据块处于不可纠错状态时，该测试数据块也称为不可纠错测试数据块。一组测试数据块的可纠错特性值可以与该组测试数据块中测试数据块的状态相关联。
例如，所述可纠错特性值可以是可纠错测试数据块的数量。当采取上述提前终止的选 取方式时，所述备选条件与所述特性值相关联。所述备选条件可以是一组第一测试数据块的特性值大于或等于同步阈值。具体的，依次判断所述各组第一测试数据块中可纠错测试数据块的数量与同步阈值的关系，直至确定出一组第一测试数据块中可纠错测试数据块的数量大于或等于同步阈值时，就将满足所述备选条件的所述一组第一测试数据块对应的观察比特作为所述备选比特。所述同步阈值的取值也可以通过仿真分析获得。
当所述可纠错特性值是可纠错测试数据块的数量，采取上述提前终止的选取方式时，所述最可能位于同步位置的观察比特的选取过程可以参见图4。其中，同步阈值可以为2。如图4所示，依次判断各组第一测试数据块中可纠错测试数据块的数量与同步阈值的关系，例如，第一组第一测试数据块中可纠错测试数据块的数量Q 1＝0，小于所述同步阈值，第二组第一测试数据块中可纠错测试数据块的数量Q 2＝2，等于所述同步阈值，则选取b 2为所述最可能位于同步位置的观察比特。并且，当判断至b 2时，确定b 2满足所述备选条件，则不再判断后续的观察比特对应的可纠错测试数据块的数量与同步阈值的关系，即不再判断Q 3与同步阈值的关系。
例如，所述可纠错特性值可以是可纠错测试数据块的数量。当采取上述遍历的选取方式时，所述极值与所述特性值相关联。所述极值可以是最大值。具体的，可以统计所述每组第一测试数据块中可纠错测试数据块的数量，确定可纠错测试数据块的数量最多的一组第一测试数据块，将该组第一测试数据块对应的观察比特作为所述最可能位于同步位置的观察比特。
当所述可纠错特性值是可纠错测试数据块的数量，采取上述遍历的选取方式时，所述最可能位于同步位置的观察比特的选取过程也可以参见图4。如图4所示，分别统计以观察比特b 1,b 2,b 3为起始比特的各组第一测试数据块中可纠错测试数据块的数量，分别记为Q 1,Q 2,Q 3,确定其中的最大数值，例如，Q 1＝0,Q 2＝0,Q 3＝2,即最大数值为Q 3＝2，则选取b 3为所述最可能位于同步位置的观察比特，b 3所在的位置为最可能的同步位置。
例如，所述可纠错特性值可以是不可纠错测试数据块的数量。当采取上述提前终止的选取方式时，所述备选条件与所述特性值相关联。所述备选条件可以是一组第一测试数据块的特性值小于或等于同步阈值。具体的，依次判断所述各组第一测试数据块中不可纠错测试数据块的数量与同步阈值的关系，直至确定出一组第一测试数据块中不可纠错测试数据块的数量小于或等于同步阈值时，就将满足所述备选条件的所述一组第一测试数据块对应的观察比特作为所述备选比特。所述同步阈值的取值也可以通过仿真分析获得。
例如，所述可纠错特性值可以是不可纠错测试数据块的数量。当采取上述遍历的选取方式时，所述极值与所述特性值相关联。所述极值可以是最小值。具体的，可以统计所述每组第一测试数据块中不可纠错测试数据块的数量，确定不可纠错测试数据块的数量最少的一组第一测试数据块，将该组第一测试数据块对应的观察比特作为所述最可能位于同步位置的观察比特。
可选的，所述特性值可以是重检验特性值。所述重校验特性值与重校验位与原始校验位之间的关系相关联。结合以上描述，长度为n比特的码字中，前k比特为信息位，后n-k比特为校验位。后n-k比特的校验位是以前k比特的信息位为依据、按照特定编码规则而计算得出的。对于接收端收到的数据序列来说，如果没有找到数据序列中码字的起始位置，则划分出的码字中，不再满足上述信息位与校验位之间的关系。也就是说，即便按照 相同的特征编码规则，以该前k比特为依据，也将无法得出与每个测试数据块中后n-k比特相同的内容。接收端收到的数据序列中的每个测试数据块中，后n-k比特与前k比特之前可能不再满足上述特定编码规则。所以，当以接收端收到的数据序列中的每个测试数据块中的前k比特为依据、按照所述特定编码规则重新计算得出的后n-k比特，与接收端收到的数据序列中的每个测试数据块中的后n-k比特相比，可能存在差异。接收端收到的数据序列中的每个测试数据块中的后n-k比特可以称为原始校验位，以接收端收到的数据序列中的每个测试数据块中的前k比特为依据、按照所述特定编码规则重新计算得出的后n-k比特可以称为重校验位。
由上述分析可知，当测试数据块内存在错误比特时，所述重校验位与所述原始校验位不相同。因此，可以对接收端所接收的数据序列中每个测试数据块中的所述重校验位与所述原始校验位进行比较，来实现码字同步。具体的，可以对接收端所接收的数据序列中每个测试数据块中的所述重校验位与所述原始校验位进行比较，从所述多个观察比特中选取一个观察比特作为所述最可能位于同步位置的观察比特。
例如，所述重校验特性值可以是重检验位与原始校验位相同的测试数据块的数量。当采取上述提前终止的选取方式时，所述备选条件与所述特性值相关联。所述备选条件可以是大于或等于同步阈值。具体的，依次判断所述各组第一测试数据块中重检验位与原始校验位相同的测试数据块的数量与同步阈值的关系，直至确定出一组第一测试数据块中重检验位与原始校验位相同的测试数据块的数量大于或等于同步阈值时，就将满足所述备选条件的所述一组第一测试数据块对应的观察比特作为所述备选比特。所述同步阈值的取值也可以通过仿真分析获得。
当所述重校验特性值是重检验位与原始校验位相同的测试数据块的数量，采取上述提前终止的选取方式时，所述最可能位于同步位置的观察比特的选取过程可以参见图4。其中，同步阈值可以为2。如图4所示，依次判断各组第一测试数据块中重检验位与原始校验位相同的测试数据块的数量与同步阈值的关系，例如，第一组第一测试数据块中重检验位与原始校验位相同的测试数据块的数量Q 1＝0，小于所述同步阈值，第二组第一测试数据块中重检验位与原始校验位相同的测试数据块的数量Q 2＝2，等于所述同步阈值，则选取b 2为所述最可能位于同步位置的观察比特。并且，当判断至b 2时，确定b 2满足所述备选条件，则不再判断后续的观察比特对应的重检验位与原始校验位相同的测试数据块的数量与同步阈值的关系，即不再判断Q 3与同步阈值的关系。
例如，所重校验特性值可以是重检验位与原始校验位相同的测试数据块的数量。当采取上述遍历的选取方式时，所述极值与所述特性值相关联。所述极值可以是最大值。具体的，可以统计所述每组第一测试数据块中重检验位与原始校验位相同的测试数据块的数量，确定重检验位与原始校验位相同的测试数据块的数量最多的一组第一测试数据块，将该组第一测试数据块对应的观察比特作为所述最可能位于同步位置的观察比特。
当所述重校验特性值是重检验位与原始校验位相同的测试数据块的数量，采取上述遍历的选取方式时，所述最可能位于同步位置的观察比特的选取过程也可以参见图4。如图4所示，分别统计以观察比特b 1,b 2,b 3为起始比特的各组第一测试数据块中重检验位与原始校验位相同的测试数据块的数量，分别记为Q 1,Q 2,Q 3,确定其中的最大数值，例如，Q 1＝0,Q 2＝0,Q 3＝2,即最大数值为Q 3＝2，则选取b 3为所述最可能位于同步位置的观察比特， b 3所在的位置为最可能的同步位置。
例如，所述重校验特性值可以是重检验位与原始校验位不相同的测试数据块的数量。当采取上述提前终止的选取方式时，所述备选条件与所述特性值相关联。所述备选条件可以是小于或等于同步阈值。具体的，依次判断所述各组第一测试数据块中重检验位与原始校验位不相同的测试数据块的数量与同步阈值的关系，直至确定出一组第一测试数据块中重检验位与原始校验位不相同的测试数据块的数量小于或等于同步阈值时，就将满足所述备选条件的所述一组第一测试数据块对应的观察比特作为所述备选比特。所述同步阈值的取值也可以通过仿真分析获得。
例如，所述重校验特性值可以是重检验位与原始校验位不相同的测试数据块的数量。当采取上述遍历的选取方式时，所述极值与所述特性值相关联。所述极值可以是最小值。具体的，可以统计所述每组第一测试数据块中重检验位与原始校验位不相同的测试数据块的数量，确定重检验位与原始校验位不相同的测试数据块的数量最少的一组第一测试数据块，将该组第一测试数据块对应的观察比特作为所述最可能位于同步位置的观察比特。
可选的，根据所述多组第一测试数据块的特性值，分别确定所述多个观察比特的同步可能性指标(synchronization possibility index)，该同步可能性指标的数值越大，表明该观察比特的位置为同步位置的可能性越大。例如，当所述多组第一测试数据块的特性值为所述多组第一测试数据块中每组第一测试数据块的校验序列中全零序列的数量时，所述同步可能性指标可以与所述全零序列的数量正相关，即全零序列的数量越多，同步可能性指标的数值越大，表明该观察比特的位置为同步位置的可能性越大。例如，当所述多组第一测试数据块的特性值为所述多组第一测试数据块中每组第一测试数据块的校验序列中非全零序列的数量时，所述同步可能性指标可以与所述非全零序列的数量负相关，即非全零序列的数量越少，同步可能性指标的数值越大，表明该观察比特的位置为同步位置的可能性越大。同理，当所述多组第一测试数据块的特性值为所述多组第一测试数据块中每组第一测试数据块的校验序列中零元素的数量，或者所述多组第一测试数据块的特性值为所述多组第一测试数据块中每组第一测试数据块中可纠错测试数据块的数量，或者所述多组第一测试数据块的特性值为所述多组第一测试数据块中每组第一测试数据块中重检验位与原始校验位相同的测试数据块的数量时，所述同步可能性指标可以与所述零元素的数量或者可纠错测试数据块的数量或者重检验位与原始校验位相同的测试数据块的数量正相关；当所述多组第一测试数据块的特性值为所述多组第一测试数据块中每组第一测试数据块的校验序列中非零元素的数量，或者所述多组第一测试数据块的特性值为所述多组第一测试数据块中每组第一测试数据块中不可纠错测试数据块的数量，或者所述多组第一测试数据块的特性值为所述多组第一测试数据块中每组第一测试数据块中重检验位与原始校验位不相同的测试数据块的数量时，所述同步可能性指标可以与所述非零元素的数量或者不可纠错测试数据块的数量或者重检验位与原始校验位不相同的测试数据块的数量负相关；在此不再赘述。
可选的，当所述多组第一测试数据块中，同步可能性指标的数值最大的观察比特的数量大于1个时，可以根据其他条件选择其中一个观察比特作为所述最可能位于同步位置的观察比特。例如，从同步可能性指标的数值最大的观察比特中，随机选取一个观察比特作为所述最可能位于同步位置的观察比特。例如，从同步可能性指标的数值最大的观察比特 中，选取在所述数据序列中排序最前的观察比特作为所述最可能位于同步位置的观察比特。
S230,第二阶段，对所述备选比特进行验证，当验证成功时，确定所述备选比特的位置为所述同步位置。具体的，S230可以包括S231和S232两个步骤。
S231,根据所述备选比特，在数据序列中划分出一组第二测试数据块，该组第二测试数据块包括至少一个第二测试数据块。所述备选比特即所述最可能位于同步位置的观察比特。
可选的，在第二阶段中，该方法在根据所述备选比特在所述数据序列中划分出至少一个第二测试数据块时，可以仅利用所述数据序列中的一部分，例如所述数据序列中的第二子序列。根据所述备选比特在数据序列中划分出一组第二测试数据块，也就是根据所述备选比特在第二子序列中划分出一组第二测试数据块。
可选的，该第二子序列与第一阶段中的第一子序列可以是相同的，即第二子序列与第一子序列的所有比特均相同，两个子序列完全重合。可选的，该第二子序列与第一阶段中的第一子序列也可以是部分相同的，即第二子序列和第一子序列的部分比特相同，两个子序列部分重合。可选的，该第二子序列与第一阶段中的第一子序列也可以是不同的，即第二子序列和第一子序列的所有比特均不同，两个子序列没有交集。
当所述第一阶段和所述第二阶段所使用的数据之间交集越少时，所述第一阶段和所述第二阶段所使用的数据之间的独立性越强，码字同步结果的准确性更高。因此，当第一子序列与第二子序列不同时，码字同步结果的准确性更高。
在第二阶段中，根据所述备选比特，即所述最可能位于同步位置的观察比特，在第二子序列中划分出一组第二测试数据块，该组第二测试数据块包括至少一个第二测试数据块。
其中，根据所述备选比特，在第二子序列中划分出一组第二测试数据块，可以是将所述备选比特作为所述至少一个第二测试数据块的起始比特，从而划分出所述至少一个第二测试数据块。
根据所述最可能位于同步位置的观察比特，在第二子序列中划分出一组第二测试数据块，也可以是将所述最可能位于同步位置的观察比特作为测试数据块的起始比特，以将所述第二子序列划分为多个测试数据块，在所述多个测试数据块选取至少一个测试数据块作为所述至少一个第二测试数据块。此时，所述至少一个第二测试数据块与所述最可能位于同步位置的观察比特之间间隔若干测试数据块，且所述至少一个第二测试数据块可以位于所述最可能位于同步位置的观察比特之前，也可以位于所述最可能位于同步位置的观察比特之后。
可选的，所述至少一个第二测试数据块可以是连续的，即至少一个第二测试数据块包括连续的N个数据块。当每个测试数据块的长度为n比特时，即选取其后的连续N*n个比特，即获得所述至少一个第二测试数据块。
可选的，所述至少一个第二测试数据块也可以是不连续的，所述至少一个第二测试数据块中每个测试数据块的起始位置均与备选比特相关联。具体的，每个测试数据块的起始位置与备选比特的间隔均为码字的长度的整数倍，即所述至少一个第二测试数据块中每两个测试数据块的间隔均为码字的长度的整数倍。并且，所述至少一个第二测试数据块中每两个测试数据块的间隔可以相同，也可以不同。
S232,对所述至少一个第二测试数据块的特性值进行验证，当验证成功时，确定所述 备选比特的位置为所述同步位置。
可选的，对所述至少一个第二测试数据块的特性值进行验证，验证方式可以是提前终止的验证方式。具体的，依次累计所述至少一个第二测试数据块中各个第二测试数据块的特性值以获得累计值，直至所述累计值满足同步条件时，验证成功，确定所述备选比特的位置为所述同步位置。
其中，所述同步条件和所述特性值相关联，具体的，
所述特性值为校验序列中全零序列的数量，所述同步条件为所述累计值大于或等于同步阈值；或者，
所述特性值为校验序列中零元素的数量，所述同步条件为所述累计值大于或等于同步阈值；或者，
所述特性值为可纠错测试数据块的数量，所述同步条件为所述累计值大于或等于同步阈值；或者，
所述特性值为重检验位与原始校验位相同的测试数据块的数量，所述同步条件为所述累计值大于或等于同步阈值；
其中，所述同步阈值的值也可以通过仿真分析获得。并且，该步骤230中的同步阈值与上述步骤2222中的同步阈值，可以为相同取值，也可以为不相同取值。
可选的，对所述至少一个第二测试数据块的特性值进行验证，验证方式可以是遍历的验证方式。具体的，将所述至少一个第二测试数据块中所有第二测试数据块的特性值相加以获得总值，当所述总值满足同步条件时，验证成功，确定所述备选比特的位置为所述同步位置。
其中，所述同步条件和所述特性值相关联，具体的，
所述特性值为校验序列中全零序列的数量，所述同步条件为所述总值大于或等于同步阈值；或者，
所述特性值为校验序列中非全零序列的数量，所述同步条件为所述总值小于或等于同步阈值；或者，
所述特性值为校验序列中零元素的数量，所述同步条件为所述总值大于或等于同步阈值；或者，
所述特性值为校验序列中非零元素的数量，所述同步条件为所述总值小于或等于同步阈值；或者，
所述特性值为可纠错测试数据块的数量，所述同步条件为所述总值大于或等于同步阈值；或者，
所述特性值为不可纠错测试数据块的数量，所述同步条件为所述总值小于或等于同步阈值；或者，
所述特性值为重检验位与原始校验位相同的测试数据块的数量，所述同步条件为所述总值大于或等于同步阈值；或者，
所述特性值为重检验位与原始校验位不相同的测试数据块的数量，所述同步条件为所述总值小于或等于同步阈值。
其中，所述同步阈值的值也可以通过仿真分析获得。并且，该步骤230中的同步阈值与上述步骤2222中的同步阈值，可以为相同取值，也可以为不相同取值。
在所述提前终止的验证方式和所述遍历的验证方式下，针对特性值的计算都可以并行进行，即采用多个计算单元同时计算多个测试数据块的特性值。例如，采用10个计算单元同时计算10个测试数据块的特性值。并行的计算方式能够节约计算时间，降低时延。
图8至图9示出了确定所述数据序列中最可能位于同步位置的观察比特，以及验证所述最可能位于同步位置的观察比特的位置是否为同步位置的一个示例性过程。图8所示的线性分组码为BCH(360,340)码，即其中每个码字的长度为360比特，每个码字内的信息数据的长度为340比特。该BCH(360,340)码的调制方式为非归零码(Non-Return-to-Zero,NRZ)，调制阶数M为2，则每个码元包括1个比特。针对该BCH(360,340)码的校验矩阵如下所示：
Figure PCTCN2021086736-appb-000002
其中α为伽罗华域GF(2 10)的本原元(primitive element)。
图8示出了接收端所接收到的数据序列的一部分，需要确认该数据序列中码字的起始位置，即同步位置。结合以上描述，在所述第一阶段，确定该数据序列中最可能位于同步位置的观察比特。如图8所示，在第一阶段中，每间隔T·log 2M个比特，选取调制码元的起始比特，作为观察比特，所述T为1，即每间隔1个比特选取调制码元的起始比特，作为观察比特。因而，选取连续的360个比特作为观察比特，即所述观察比特的数量P为360，如图8所示的b 1,b 2,b 3,…,b 359,b 360。根据这些观察比特，从数据序列中划分出多组第一测试数据块，每组第一测试数据块中测试数据块的数量N为2，即每组第一测试数据块包括2个测试数据块，如图8所示的多组B 1,B 2。
结合以上描述，图8所示的数据序列中多个观察比特的位置中，只有一个观察比特的位置是该数据序列真正的同步位置。将所述每组第一测试数据块的校验序列中全零序列的数量，作为选取所述最可能位于同步位置的观察比特的依据。如图8所示，校验序列S是一个长度为4的行向量，例如，以观察比特b 1为起始比特的一组第一测试数据块的校验序列集合为S (1)，包括S 1 (1),S 2 (1)，分别对应测试数据块B 1,B 2,类似的，以观察比特b 2,b 3,…,b 359,b 360为起始比特的一组第一测试数据块的校验序列集合，分别为S (2),S (3),…,S (359),S (360)。统计每组第一测试数据块的校验序列中全零序列的数量，分别记为Q 1,Q 2,Q 3,…,Q 359,Q 360。如图8所示，其中Q 1＝0,即以观察比特b 1为起始比特的一组第一测试数据块的校验序列中没有全零序列，类似的，Q 2＝0,Q 3＝1,…,Q 359＝2,Q 360＝0。假设最终在所有的360个Q值中Q 359的值最大，则将观察比特b 359作为所述最可能位于同步位置的观察比特。即认为观察比特b 359为一个测试数据块的起始比特，其后每隔360比特均为后续测试数据块的起始比特。
在选取所述最可能位于同步位置的观察比特为b 359之后，在第一阶段所使用的数据序列的部分之后，即在所述第一子序列之后，根据该b 359划分出一组第二测试数据块。即在第二子序列中划分出一组第二测试数据块，所述第二子序列与所述第一子序列不同。如图9所示，该组第二测试数据块包括4个测试数据块。对所述至少一个第二测试数据块的特性值进行验证，所述特性值为所述至少一个第二测试数据块的校验序列中全零序列的数量。 采用上述遍历的验证方式，即将所述至少一个第二测试数据块中所有第二测试数据块的校验序列中全零序列的数量相加以获得总值，当所述总值大于或等于同步阈值，验证成功，所述同步阈值为2。如图9所示，4个测试数据块的校验序列中，全零序列的数量为3，大于2，因而确定b 359所在的位置为同步位置。
可选的，当验证未成功时，重新执行上述步骤S220，即重新执行所述第一阶段，重新选取所述最可能位于同步位置的观察比特。
步骤S230为可选步骤，即该方法可以仅包括所述第一阶段。此时，在步骤S220之后直接进入步骤S240。此时，在该方法中，在确定所述备选比特后，直接将该备选比特的位置确定为所述同步位置。即直接将所述最可能的同步位置作为所述同步位置。
S240,确定所述数据序列为同步锁定状态。
接收端确定同步位置以后，可以根据该同步位置将接收到的数据序列划分为多个同步码字。当数据序列根据同步位置被划分为多个同步码字时，可以认为该数据序列处于同步锁定位置。也就是说，在确定同步位置以后，接收端确定所述数据序列为同步锁定状态。当数据序列处于同步锁定状态时，接收端可以对该数据序列进行检错以及纠错等操作。
S250,失锁判断。
在接收端开始对所述数据序列进行检错、纠错等操作以后，仍然需要持续观察所述数据序列中的码字划分是否准确，即所述同步位置是否准确。当同步位置不准确时，根据该同步位置划分出的每个测试数据块的内容不再对应真正的码字，此时，也可以称为该数据序列的同步锁定状态丢失。因此，判断数据序列的同步位置是否准确的过程，也可以称为失锁判断过程。
在失锁判断过程中，根据所述同步位置从所述数据序列中划分出多个同步码字，所述同步位置为所述多个同步码字的起始位置；对所述多个同步码字的特性值进行验证，当验证失败时，确定所述数据序列为所述失锁状态。
可选的，所述多个同步码字可以是连续的，即多个同步码字包括连续的N个码字。当每个码字的长度为n比特时，即选取其后的连续N*n个比特，即获得所述多个同步码字。
可选的，所述多个同步码字也可以是不连续的，所述多个同步码字中每个码字的起始位置均与同步位置相关联。具体的，每个同步码字的起始位置与同步位置的间隔均为码字的长度的整数倍，即所述多个同步码字中每两个同步码字的间隔均为码字的长度的整数倍。并且，所述多个同步码字中每两个同步码字的间隔可以相同，也可以不同。
可选的，对所述多个同步码字的特性值进行验证，验证方式可以是提前终止的验证方式。具体的，依次累计所述多个同步码字中各个同步码字的特性值以获得累计值，直至所述累计值满足失锁条件时，验证失败，确定所述备选比特的位置为所述同步位置。
其中，所述失锁条件和所述特性值相关联，具体的，
所述特性值为校验序列中非全零序列的数量，所述失锁条件为所述累计值大于或等于同步阈值；或者，
所述特性值为校验序列中非零元素的数量，所述失锁条件为所述累计值大于或等于同步阈值；或者，
所述特性值为不可纠错码字的数量，所述失锁条件为所述累计值大于或等于同步阈值；或者，
所述特性值为重检验位与原始校验位不相同的码字的数量，所述失锁条件为所述累计值大于或等于同步阈值；
其中，所述码字的长度为n比特，所述码字的前k比特为信息位，所述码字的后n-k比特为所述原始校验位，所述重检验位是根据所述信息位获得的，所述重校验位的长度为n-k比特，所述n和所述k为整数。
其中，所述同步阈值的值也可以通过仿真分析获得。并且，该步骤250中的同步阈值与上述步骤230,2222中的同步阈值，可以为相同取值，也可以为不相同取值。
可选的，对所述多个同步码字的特性值进行验证，验证方式可以是遍历的验证方式。具体的，将所述多个同步码字中所有同步码字的特性值相加以获得总值，当所述总值满足失锁条件时，验证失败，确定所述备选比特的位置为所述同步位置。
其中，所述同步条件和所述特性值相关联，具体的，
所述特性值为校验序列中全零序列的数量，所述失锁条件为所述总值小于或等于同步阈值；或者，
所述特性值为校验序列中非全零序列的数量，所述失锁条件为所述总值大于或等于同步阈值；或者，
所述特性值为校验序列中零元素的数量，所述失锁条件为所述总值小于或等于同步阈值；或者，
所述特性值为校验序列中非零元素的数量，所述失锁条件为所述总值大于或等于同步阈值；或者，
所述特性值为可纠错码字的数量，所述失锁条件为所述总值小于或等于同步阈值；或者，
所述特性值为不可纠错码字的数量，所述失锁条件为所述总值大于或等于同步阈值；或者，
所述特性值为重检验位与原始校验位相同的码字的数量，所述失锁条件为所述总值小于或等于同步阈值；或者，
所述特性值为重检验位与原始校验位不相同的码字的数量，所述失锁条件为所述总值大于或等于同步阈值；
其中，所述码字的长度为n比特，所述码字的前k比特为信息位，所述码字的后n-k比特为所述原始校验位，所述重检验位是根据所述信息位获得的，所述重校验位的长度为n-k比特，所述n和所述k为整数。
其中，所述同步阈值的值也可以通过仿真分析获得。并且，该步骤250中的同步阈值与上述步骤230,2222中的同步阈值，可以为相同取值，也可以为不相同取值。
在所述提前终止的验证方式和所述遍历的验证方式下，针对特性值的计算都可以并行进行，即采用多个计算单元同时计算多个测试数据块的特性值。例如，采用10个计算单元同时计算10个测试数据块的特性值。并行的计算方式能够节约计算时间，降低时延。
图10示出了失锁判断的一种示例性过程。如图10所示，根据所述同步位置从数据序列中划分出5个同步码字，统计其中可纠错码字的数量。例如，在解码状态(decoding state)中，0表示不可纠错，1表示可纠错，则在图10所示的5个同步码字中，可纠错码字的数量为1。若失锁阈值为3，则可纠错码字的数量小于失锁阈值，确定5个同步码字满足失 锁条件，所述数据序列为失锁状态。
可选的，当验证未失败时，确定所述数据序列的同步锁定状态未丢失。
可选的，当确定所述数据序列的同步锁定状态未丢失以后，可以在所述数据序列中继续向后移动一定间隔，选取多个同步码字，继续判断该向后选取的多个同步码字是否满足失锁条件。可选的，所述向后移动一定间隔可以是移动一个测试数据块，即对每一个同步码字均以其为开始向后观察多个同步码字，以进行失锁判断。
S260,确定所述数据序列为失锁状态。
可选的，当确定所述数据序列为失锁状态时，继续确定所述数据序列的更新同步位置。具体的，重新执行所述第一阶段和所述第二阶段，将重新执行的所述第二阶段中确定的同步位置作为所述更新同步位置。如此便形成了一个同步锁定-失锁-同步锁定的闭环操作，保证了通信系统在尽可能多的时间内处于同步锁定的正常工作状态。
通过该方法能够解决AM同步方案中增加额外数据、级联扩展性差的技术问题。并且，无须在发送端数据流中插入额外数据，从而也无须在以太接口上需要引入空闲(Idle)码块增删机制，无须设计相应的逻辑处理单元，无须为插入的AM序列提前预留带宽。如果需要在原有FEC基础上，增加一级FEC，采用两级FEC级联时，可以避免原有的空闲码块增删机制无法适用于对第二级FEC的AM序列、以及针对第二级FEC增加AM序列影响高精度时钟同步性能的技术问题。通过该方法可以实现接收端数据流高精度码字同步的技术效果，其同步性能达到较高可靠性。
步骤S240,S250和S260均为可选步骤，即该方法可以仅用于确定同步位置，可以不对所述数据序列进行同步锁定状态下的检错或纠错处理，也可以不对该数据序列后续是否进入失锁状态进行判断。
通过仿真比较，本申请所提供的码字同步方法与现有的AM同步方案相比，在平均同步锁定时间、误锁定平均出现时间以及误失锁平均出现时间等各项性能指标上，本申请所提供的码字同步方法均优于现有的AM同步方案。因此，从整体来看，本申请所提供的码字同步方法可以达到比AM同步方案更优的同步性能。
图11示出了本申请实施例的码字同步方法。该方法包括如下步骤：
步骤一，接收数据序列，所述数据序列包括多个比特。所述步骤一的具体过程可以参见上述对步骤S210的描述。
步骤二，确定所述数据序列中的备选比特，所述备选比特包括在所述多个比特中。所述备选比特为所述最可能位于同步位置的观察比特。所述步骤二的具体过程可以参见上述对步骤S220的描述。
步骤三，根据所述备选比特确定同步位置，所述同步位置用于指示所述码字的起始位置。
可选的，根据所述备选比特确定同步位置可以是在选取所述最可能位于同步位置的观察比特后，进一步验证所述最可能位于同步位置的观察比特的位置是否为同步位置。所述备选比特为所述最可能位于同步位置的观察比特。此时，所述步骤三的具体过程可以参见上述对步骤S230的描述。此时，该方法至少包括图2所示的S210,S220,S230。
可选的，根据所述备选比特确定同步位置也可以是在选取所述最可能位于同步位置的观察比特后，直接将该最可能位于同步位置的观察比特作为同步位置。所述备选比特为所 述最可能位于同步位置的观察比特。此时，该方法至少包括图2所示的S210,S220。
可以看出，在上述两种根据所述备选比特确定同步位置的方式中，位于所述同步位置的比特包括在所述备选比特中，所述备选比特为所述最可能位于同步位置的观察比特。
可选的，在所述步骤三之后，所述方法还包括：确定所述数据序列为同步锁定状态。具体过程可以参见上述对步骤S240的描述。
可选的，在所述步骤三之后，所述方法还包括：失锁判断。具体过程可以参见上述对步骤S250的描述。
可选的，所述方法还可以包括步骤四，响应于所述数据序列为失锁状态，确定所述数据序列的更新同步位置。具体过程可以参见上述对步骤S260的描述。
本申请实施例的码字同步方法由通信设备执行，所述通信设备可以是任何执行FEC的设备，包括但不限于路由器、交换机、服务器、以及终端设备。
图12示出了本申请实施例所涉及的通信设备的一种可能的结构示意图，参阅图12，通信设备1200包括：接收单元1201和处理单元1202。这些单元可以执行上述图2-11所示的方法的相应步骤。举例来说，
接收单元1201，用于接收数据序列，所述数据序列包括多个比特。
处理单元1202，用于确定所述数据序列中的备选比特，所述备选比特包括在所述多个比特中；根据所述备选比特确定同步位置，所述同步位置用于指示所述数据序列中码字的起始位置。
图13是本申请实施例所涉及的通信设备的另一种结构示意图。参见图13，该通信设备1300包括至少一个处理器1301以及至少一个通信接口1304，可选地，该设备1300还可以包括存储器1303。
处理器1301可以是中央处理器(central processing unit，CPU)、通用处理器，数字信号处理器(digital signal processor，DSP)、专用集成电路(application-specific integrated circuit，ASIC)、现场可编程门阵列(field programmable gate array，FPGA)或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。其可以实现或执行结合本申请实施例公开内容所描述的各种逻辑方框、模块和电路。所述处理器也可以是实现计算功能的组合，例如包括一个或多个微处理器组合，DSP和微处理器的组合等等。处理器可以用于确定所述数据序列中的备选比特，以及根据所述备选比特确定同步位置。以实现本申请实施例中提供的方法。
可选的，通信总线1302用于在处理器1301、通信接口1304和存储器、1303之间传送信息。总线可以是外设部件互连标准(peripheral component interconnect，简称PCI)总线或扩展工业标准结构(extended industry standard architecture，简称EISA)总线等。所述总线可以分为地址总线、数据总线、控制总线等。为便于表示，图13中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
存储器1303可以是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其它类型的静态存储设备，随机存取存储器(random access memory，RAM)或者可存储信息和指令的其它类型的动态存储设备，也可以是电可擦可编程只读存储器(electrically erasable programmable read-only memory，EEPROM)、只读光盘(compact disc read-only  Memory，CD-ROM)或其它光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其它磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其它介质，但不限于此。存储器1303可以是独立存在，通过通信总线1302与处理器1301相连接。存储器1303也可以和处理器1301集成在一起。
可选地，存储器1303用于存储执行本申请方案的程序代码或指令，并由处理器1301来控制执行。在实现图12所示实施例的情况下，且图12实施例中所描述的各单元为通过软件实现的情况下，执行图12中各个单元的功能所需的软件或程序代码存储在存储器1303中。处理器1301用于执行存储器1303中存储的程序代码。程序代码中可以包括一个或多个软件模块。可选地，处理器1301自身也可以存储执行本申请方案的程序代码或指令。
通信接口1304，使用任何收发器一类的装置，用于与其它设备或通信网络通信，通信网络可以为以太网、无线接入网(RAN)或无线局域网(wireless local area networks，WLAN)等。在本申请实施例中，通信接口1304可以用于接收分段路由网络中的其他节点发送的报文，也可以向分段路由网络中的其他节点发送报文。通信接口1304可以为以太接口(Ethernet)接口、快速以太(Fast Ethernet，FE)接口、千兆以太(Gigabit Ethernet，GE)接口或异步传输模式(Asynchronous Transfer Mode，ATM)接口。
在具体实现中，作为一种实施例，设备1300可以包括多个处理器，例如图13中所示的处理器1301和处理器1305。这些处理器中的每一个可以是一个单核(single-CPU)处理器，也可以是一个多核(multi-CPU)处理器。这里的处理器可以指一个或多个设备、电路、和/或用于处理数据(例如计算机程序指令)的处理核。
在具体实施例中，网络设备1300中的处理器1301用于通过通信接口接收数据序列，所述数据序列包括多个比特；确定所述数据序列中的备选比特，所述备选比特包括在所述多个比特中；根据所述备选比特确定同步位置，所述同步位置用于指示所述数据序列中码字的起始位置。该处理器的详细处理过程请参考上述图2所示实施例中的步骤S210,S220,S230,S240,S250,S260,图3所示实施例中的步骤S221,S222,以及图11所示步骤一至三的详细描述，这里不再赘述。
网络设备1300中的通信接口用于网络设备1300通过网络系统接收和发送数据序列。具体的过程请参考上述图2所示实施例中S210，以及图11所示步骤一的详细描述，这里不再赘述。
图14本申请实施例所涉及的通信设备的另一种结构示意图。当通信设备为网络中的转发设备，例如路由器或交换机时，该通信设备可以参见图14所示的设备结构示意图。设备1400包括主控板和一个或多个接口板，主控板与接口板通信连接。主控板也称为主处理单元(main processing unit，MPU)或路由处理卡(route processor card)，主控板负责对设备1400中各个组件的控制和管理，包括路由计算、设备管理和维护功能。接口板也称为线卡(line processing unit，LPU)或线卡(line card)，用于转发数据。在一些实施例中，设备1400也可以包括交换网板，交换网板与主控板、接口板通信连接，交换网板用于转发接口板之间的数据，交换网板也可以称为交换网板单元(switch fabric unit，SFU)。接口板包括中央处理器、存储器、转发芯片和物理接口卡(physical interface card，PIC)。 中央处理器与存储器、网络处理器和物理接口卡分别通信连接。存储器用于存储转发表。转发芯片用于基于存储器中保存的转发表转发接收到的数据帧，如果数据帧的目的地址为设备1400的地址，则将该数据帧上送CPU处理；如果数据帧的目的地址不是设备1400的地址，则根据该目的地址从转发表中查找到该目的地址对应的下一跳和出接口，将该数据帧转发到该目的地址对应的出接口。转发芯片可以是网络处理器(network processor，NP)。PIC也称为子卡，可安装在接口板上，负责将光电信号转换为数据帧并对数据帧进行合法性检查后转发给转发芯片处理。在一些实施例中，中央处理器也可执行转发芯片的功能，比如基于通用CPU实现软件转发，从而接口板中不需要转发芯片。主控板、接口板、交换网板之间的通信连接可以通过总线来实现。在一些实施例中，转发芯片可以通过专用集成电路(application-specific integrated circuit，ASIC)或现场可编程门阵列(field programmable gate array，FPGA)实现。
在逻辑上，设备1400包括控制面和转发面，控制面包括主控板和中央处理器，转发面包括执行转发的各个组件，比如存储器、PIC和NP。控制面执行路由器、生成转发表、处理信令和协议报文、配置与维护PE1的状态等功能，控制面将生成的转发表下发给转发面，在转发面，NP基于控制面下发的转发表对设备1400的PIC收到的报文查表转发。控制面下发的转发表可以保存在存储器中。在有些实施例中，控制面和转发面可以完全分离，不在同一设备上。
在具体实施例中，所述接口板用于接收数据序列，所述数据序列包括多个比特。具体的过程请参考上述图2所示实施例中S210，以及图11所示步骤一的详细描述，这里不再赘述。所述主控板用于确定所述数据序列中的备选比特，所述备选比特包括在所述多个比特中；根据所述备选比特确定同步位置，所述同步位置用于指示所述数据序列中码字的起始位置。详细处理过程请参考上述图2所示实施例中的步骤S210,S220,S230,S240,S250,S260,图3所示实施例中的步骤S221,S222,以及图11所示步骤一至三的详细描述，这里不再赘述。
在一种可能的实现方式中，主控板和接口板之间建立进程间通信协议(inter-process communication，IPC)通道，主控板和接口板之间通过IPC通道进行通信。
本申请实施例提供一种芯片，该芯片包括存储器和处理器，存储器用于存储计算机程序，处理器用于从存储器中调用并运行该计算机程序，以执行上述方法实施例中的方法，即图2-11所示实施例中的方法。
可选地，上述芯片仅包括处理器，处理器用于读取并执行存储器中存储的计算机程序，当计算机程序被执行时，处理器执行上述方法实施例中的方法，即图2-11所示实施例中的方法。
可选的，所述芯片可以用于两级FEC级联的应用场景。具体的，两级FEC级联包括内层FEC和外层FEC，本申请实施例提供的芯片用于所述内层FEC。内层FEC采用本申请所述的码字同步方法，也称为FEC1；外层FEC可以采用AM同步方案，也称为FEC2。此时，所述FEC1与所述FEC2可以位于同一芯片上，也可位于不同芯片上。即本申请实施例所提供的芯片可以仅包括所述FEC1，也可以包括所述FEC1和所述FEC2。
本申请实施例提供一种网络系统。该网络系统包括接收设备和发送设备。所述接收设备用于接收所述发送设备发送的数据序列。所述接收设备可以执行上述图2-11所示实施 例中的步骤。
本申请实施例还提供了一种非瞬态存储介质，用于储存前述实施例中所用的软件指令，其包括用于执行前述实施例所示的方法的程序，当其在计算机或网络设备上执行时，使得所示计算机或网络设备执行前述方法实施例中的方法。
本申请实施例还提供了一种包括计算机程序指令的计算机程序产品，当该计算机程序产品在计算机上运行时，使得网络节点执行前述方法实施例中的方法。
需说明的是，以上描述的任意装置实施例都仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。另外，本申请提供的网络设备或主机的实施例附图中，模块之间的连接关系表示它们之间具有通信连接，具体可以实现为一条或多条通信总线或信号线。本领域普通技术人员在不付出创造性劳动的情况下，即可以理解并实施。
本申请实施例公开内容所描述的方法或者算法的步骤可以硬件的方式来实现，也可以是由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于随机存取存储器(random access memory，RAM)、闪存、只读存储器(read-only memory，ROM)、可擦除可编程只读存储器(erasable programmable ROM，EPROM)、电可擦可编程只读存储器(electrically EPROM，EEPROM)、硬盘、移动硬盘、光盘或者本领域熟知的任何其它形式的存储介质中。存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息。当然，存储介质也可以是处理器的组成部分。
以上所述的具体实施方式，对本申请的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本申请的具体实施方式而已，并不用于限定本申请的保护范围，凡在本申请的技术方案的基础之上，所做的任何修改、替换、改进等，均应包括在本申请的保护范围之内。
本申请中术语“第一”“第二”等字样用于对作用和功能基本相同的相同项或相似项进行区分，应理解，“第一”、“第二”、“第n”之间不具有逻辑或时序上的依赖关系，也不对数量和执行顺序进行限定。还应理解，尽管以下描述使用术语第一、第二等来描述各种元素，但这些元素不应受术语的限制。这些术语只是用于将一元素与另一元素区别分开。例如，在不脱离各种所述示例的范围的情况下，第一图像可以被称为第二图像，并且类似地，第二图像可以被称为第一图像。第一图像和第二图像都可以是图像，并且在某些情况下，可以是单独且不同的图像。
本申请中术语“至少一个”的含义是指一个或多个，本申请中术语“多个”的含义是指两个或两个以上，例如，多个第二报文是指两个或两个以上的第二报文。本文中术语“系统”和“网络”经常可互换使用。
应理解，在本文中对各种所述示例的描述中所使用的术语只是为了描述特定示例，而并非旨在进行限制。如在对各种所述示例的描述和所附权利要求书中所使用的那样，单数形式“一个(“a”“，an”)”和“该”旨在也包括复数形式，除非上下文另外明确地指示。
还应理解，本文中所使用的术语“和/或”是指并且涵盖相关联的所列出的项目中的一个或多个项目的任何和全部可能的组合。术语“和/或”，是一种描述关联对象的关联关系， 表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本申请中的字符“/”，一般表示前后关联对象是一种“或”的关系。
还应理解，在本申请的各个实施例中，各个过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
应理解，根据A确定B并不意味着仅仅根据A确定B，还可以根据A和/或其它信息确定B。
还应理解，术语“包括”(也称“includes”、“including”、“comprises”和/或“comprising”)当在本说明书中使用时指定存在所陈述的特征、整数、步骤、操作、元素、和/或部件，但是并不排除存在或添加一个或多个其他特征、整数、步骤、操作、元素、部件、和/或其分组。
还应理解，术语“如果”可被解释为意指“当...时”(“when”或“upon”)或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定...”或“如果检测到[所陈述的条件或事件]”可被解释为意指“在确定...时”或“响应于确定...”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
应理解，说明书通篇中提到的“一个实施例”、“一实施例”、“一种可能的实现方式”意味着与实施例或实现方式有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”、“一种可能的实现方式”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。

Claims (56)

  1. 一种码字同步方法，其特征在于，所述方法包括：
    步骤一，接收数据序列，所述数据序列包括多个比特；
    步骤二，确定所述数据序列中的备选比特，所述备选比特包括在所述多个比特中；
    步骤三，根据所述备选比特确定同步位置，所述同步位置用于指示所述数据序列中码字的起始位置。
  2. 根据权利要求1所述的方法，其特征在于，所述步骤三包括：
    对所述备选比特进行验证，当验证成功时，确定所述备选比特的位置为所述同步位置。
  3. 根据权利要求2所述的方法，其特征在于，所述步骤三包括：
    根据所述备选比特在所述数据序列中划分出至少一个第二测试数据块，所述备选比特的位置为所述至少一个第二测试数据块的起始位置；
    对所述至少一个第二测试数据块的特性值进行验证，当验证成功时，确定所述备选比特的位置为所述同步位置。
  4. 根据权利要求3所述的方法，其特征在于，
    对所述至少一个第二测试数据块的特性值进行验证，包括：
    依次累计所述至少一个第二测试数据块中各个第二测试数据块的特性值以获得累计值，直至所述累计值满足同步条件时，验证成功。
  5. 根据权利要求4所述的方法，其特征在于，
    所述特性值为被判定为正确码字的第二测试数据块的数量，所述同步条件为所述累计值大于或等于同步阈值；或者
    所述特性值为校验序列中全零序列的数量，所述同步条件为所述累计值大于或等于同步阈值；或者，
    所述特性值为校验序列中零元素的数量，所述同步条件为所述累计值大于或等于同步阈值；或者，
    所述特性值为可纠错测试数据块的数量，所述同步条件为所述累计值大于或等于同步阈值；或者，
    所述特性值为重检验位与原始校验位相同的测试数据块的数量，所述同步条件为所述累计值大于或等于同步阈值；
    其中，所述测试数据块的长度为n比特，所述测试数据块的前k比特为信息位，所述测试数据块的后n-k比特为所述原始校验位，所述重检验位是根据所述信息位获得的，所述重校验位的长度为n-k比特，所述n和所述k为整数。
  6. 根据权利要求3所述的方法，其特征在于，
    对所述至少一个第二测试数据块的特性值进行验证，包括：
    将所述至少一个第二测试数据块中所有第二测试数据块的特性值相加以获得总值，当所述总值满足同步条件时，验证成功。
  7. 根据权利要求6所述的方法，其特征在于，
    所述特性值为所述所有第二测试数据块中被判定为正确码字的测试数据块的数量，所述同步条件为所述累计值大于或等于同步阈值；或者
    所述特性值为所述所有第二测试数据块中被判定为错误码字的测试数据块的数量，所 述同步条件为所述累计值小于或等于同步阈值；或者
    所述特性值为校验序列中全零序列的数量，所述同步条件为所述总值大于或等于同步阈值；或者，
    所述特性值为校验序列中非全零序列的数量，所述同步条件为所述总值小于或等于同步阈值；或者，
    所述特性值为校验序列中零元素的数量，所述同步条件为所述总值大于或等于同步阈值；或者，
    所述特性值为校验序列中非零元素的数量，所述同步条件为所述总值小于或等于同步阈值；或者，
    所述特性值为可纠错测试数据块的数量，所述同步条件为所述总值大于或等于同步阈值；或者，
    所述特性值为不可纠错测试数据块的数量，所述同步条件为所述总值小于或等于同步阈值；或者，
    所述特性值为重检验位与原始校验位相同的测试数据块的数量，所述同步条件为所述总值大于或等于同步阈值；或者，
    所述特性值为重检验位与原始校验位不相同的测试数据块的数量，所述同步条件为所述总值小于或等于同步阈值；
    其中，所述测试数据块的长度为n比特，所述测试数据块的前k比特为信息位，所述测试数据块的后n-k比特为所述原始校验位，所述重检验位是根据所述信息位获得的，所述重校验位的长度为n-k比特，所述n和所述k为整数。
  8. 根据权利要求1所述的方法，其特征在于，所述步骤三包括：
    将所述备选比特的位置作为所述同步位置。
  9. 根据权利要求1所述的方法，其特征在于，所述步骤二包括：
    从所述数据序列中选取多个观察比特；
    从所述多个观察比特中选取所述备选比特。
  10. 根据权利要求9所述的方法，其特征在于，所述从所述多个观察比特中选取所述备选比特，包括：
    根据所述多个观察比特从所述数据序列中确定多组第一测试数据块，其中，所述多组第一测试数据块中的每组第一测试数据块包括至少一个第一测试数据块，所述多个观察比特中的每一个观察比特的位置为所述多组第一测试数据块中的每组第一测试数据块的起始位置；
    根据所述多组第一测试数据块的特性值，从所述多个观察比特中选取一个观察比特作为所述备选比特。
  11. 根据权利要求10所述的方法，其特征在于，其中，
    所述根据所述多组第一测试数据块的特性值，从所述多个观察比特中选取一个观察比特作为所述备选比特，包括：
    依次判断所述多组第一测试数据块中各组第一测试数据块的特性值是否满足备选条件，直至确定出一组第一测试数据块的特性值满足所述备选条件；
    将满足所述备选条件的所述一组第一测试数据块对应的观察比特作为所述备选比特。
  12. 根据权利要求11所述的方法，其特征在于，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中被判定为正确码字的第一测试数据块的数量总值，所述备选条件为所述累计值大于或等于同步阈值；或者
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中被判定为正确码字的第一测试数据块的数量总值，所述备选条件为所述累计值小于或等于同步阈值；或者
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块的校验序列中全零序列的数量总值，所述备选条件为所述总值大于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块的校验序列中非全零序列的数量总值，所述备选条件为所述总值小于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块的校验序列中零元素的数量总值，所述备选条件为所述总值大于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块的校验序列中非零元素的数量总值，所述备选条件为所述总值小于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块中可纠错测试数据块的数量总值，所述备选条件为所述总值大于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块中不可纠错测试数据块的数量总值，所述备选条件为所述总值小于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块中重检验位与原始校验位相同的测试数据块的数量总值，所述备选条件为所述总值大于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块中重检验位与原始校验位不相同的测试数据块的数量总值，所述备选条件为所述总值小于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中前X个第一测试数据块的校验序列中全零序列的数量累计值，所述备选条件为所述累计值大于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中前X个第一测试数据块的校验序列中零元素的数量累计值，所述备选条件为所述累计值大于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中前X个第一测试数据块中可纠错测试数据块的数量累计值，所述备选条件为所述累计值大于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中前X个第一测试数据块中重检验位与原始校验位相同的测试数据块的数量累计值，所述备选条件为所述累计值大于或等于同步阈值；
    其中，所述测试数据块的长度为n比特，所述测试数据块的前k比特为信息位，所述测试数据块的后n-k比特为所述原始校验位，所述重检验位是根据所述信息位获得的，所述重校验位的长度为n-k比特，所述n，所述k和所述X均为整数。
  13. 根据权利要求10所述的方法，其特征在于，其中，
    所述根据所述多组第一测试数据块的特性值，从所述多个观察比特中选取一个观察比特作为所述备选比特，包括：
    比较所述多组第一测试数据块中每组第一测试数据块的特性值，将所述特性值为极值的一组第一测试数据块对应的观察比特作为所述备选比特。
  14. 根据权利要求13所述的方法，其特征在于，
    所述特性值为被判定为正确码字的第一测试数据块的数量，所述极值为最大值；或者
    所述特性值为被判定为错误码字的第一测试数据块的数量，所述极值为最小值；或者
    所述特性值为校验序列中全零序列的数量，所述极值为最大值；或者，
    所述特性值为校验序列中非全零序列的数量，所述极值为最小值；或者，
    所述特性值为校验序列中零元素的数量，所述极值为最大值；或者，
    所述特性值为校验序列中非零元素的数量，所述极值为最小值；或者，
    所述特性值为可纠错测试数据块的数量，所述极值为最大值；或者，
    所述特性值为不可纠错测试数据块的数量，所述极值为最小值；或者，
    所述特性值为重检验位与原始校验位相同的测试数据块的数量，所述极值为最大值；或者，
    所述特性值为重检验位与原始校验位不相同的测试数据块的数量，所述极值为最小值；
    其中，所述测试数据块的长度为n比特，所述测试数据块的前k比特为信息位，所述测试数据块的后n-k比特为所述原始校验位，所述重检验位是根据所述信息位获得的，所述重校验位的长度为n-k比特，所述n和所述k为整数。
  15. 根据权利要求9-14任一项所述的方法，其特征在于，其中，
    所述从所述数据序列中选取多个观察比特，包括：
    从所述数据序列中每间隔T个比特选取一个比特，作为所述观察比特，所述T为大于零的整数；或者，
    从所述数据序列中每间隔L*n+T个比特选取一个比特，作为所述观察比特，所述L为间隔的测试数据块的数量，所述测试数据块的长度为所述n个比特，所述L和所述T为大于零的整数。
  16. 根据权利要求9-14任一项所述的方法，其特征在于，所述数据序列为调制信号，所述数据序列包括多个调制码元，其中，
    所述从所述数据序列中选取多个观察比特，包括：
    从所述数据序列中每间隔T个调制码元，选取调制码元的起始比特，作为所述观察比特，所述T为大于零的整数；或者，
    从所述数据序列中每间隔L*m+T个调制码元，选取调制码元的起始比特，作为所述观察比特，所述L为间隔的测试数据块的数量，所述测试数据块的长度为所述m个调制码元，所述L和所述T为大于零的整数。
  17. 根据权利要求9-16任一项所述的方法，其特征在于，所述观察比特的数量为P， 所述P为正整数，所述码字的长度为所述P个比特。
  18. 根据权利要求3-7任一项所述的方法，其特征在于，其中，
    所述步骤二中，所述确定所述数据序列中的备选比特包括，确定第一子序列中的备选比特，所述步骤三中，所述根据所述备选比特在所述数据序列中划分出至少一个第二测试数据块包括，根据所述备选比特在第二子序列中划分出至少一个第二测试数据块，所述第一子序列和所述第二子序列包括在所述数据序列中，所述第二子序列与所述第一子序列相同、部分相同或不同。
  19. 根据权利要求1-18任一项所述的方法，其特征在于，在所述步骤三之后，所述方法还包括：
    步骤四，响应于所述数据序列为失锁状态，确定所述数据序列的更新同步位置。
  20. 根据权利要求19所述的方法，其特征在于，其中，所述确定所述数据序列的更新同步位置，包括：
    重新执行所述步骤二和所述步骤三，将重新执行的步骤三所确定的同步位置作为所述更新同步位置。
  21. 根据权利要求19或20所述的方法，其特征在于，其中，在所述步骤三之后、所述步骤四之前，所述方法还包括：
    根据所述同步位置从所述数据序列中划分出多个同步码字，所述同步位置为所述多个同步码字的起始位置；
    对所述多个同步码字的特性值进行验证，当验证失败时，确定所述数据序列为所述失锁状态。
  22. 根据权利要求21所述的方法，其特征在于，
    对所述多个同步码字的特性值进行验证，包括：
    依次累计所述多个同步码字中各个同步码字的特性值以获得累计值，直至所述累计值满足失锁条件时，验证失败。
  23. 根据权利要求22所述的方法，其特征在于，
    所述特性值为所述多个同步码字中被判定为错误码字的数量，所述失锁条件为所述累计值大于或等于同步阈值；或者
    所述特性值为校验序列中非全零序列的数量，所述失锁条件为所述累计值大于或等于同步阈值；或者，
    所述特性值为校验序列中非零元素的数量，所述失锁条件为所述累计值大于或等于同步阈值；或者，
    所述特性值为不可纠错码字的数量，所述失锁条件为所述累计值大于或等于同步阈值；或者，
    所述特性值为重检验位与原始校验位不相同的码字的数量，所述失锁条件为所述累计值大于或等于同步阈值；
    其中，所述码字的长度为n比特，所述码字的前k比特为信息位，所述码字的后n-k比特为所述原始校验位，所述重检验位是根据所述信息位获得的，所述重校验位的长度为n-k比特，所述n和所述k为整数。
  24. 根据权利要求21所述的方法，其特征在于，
    对所述多个同步码字的特性值进行验证，包括：
    将所述多个同步码字中所有同步码字的特性值相加以获得总值，当所述总值满足失锁条件时，验证失败。
  25. 根据权利要求24所述的方法，其特征在于，
    所述特性值总值为所述多个同步码字中被判定为错误码字的总数量，所述失锁条件为所述总值大于或等于同步阈值；或者
    所述特性值总值为所述多个同步码字中被判定为正确码字的总数量，所述失锁条件为所述总值小于或等于同步阈值；或者所述特性值为校验序列中全零序列的数量，所述失锁条件为所述总值小于或等于同步阈值；或者，
    所述特性值为校验序列中非全零序列的数量，所述失锁条件为所述总值大于或等于同步阈值；或者，
    所述特性值为校验序列中零元素的数量，所述失锁条件为所述总值小于或等于同步阈值；或者，
    所述特性值为校验序列中非零元素的数量，所述失锁条件为所述总值大于或等于同步阈值；或者，
    所述特性值为可纠错码字的数量，所述失锁条件为所述总值小于或等于同步阈值；或者，
    所述特性值为不可纠错码字的数量，所述失锁条件为所述总值大于或等于同步阈值；或者，
    所述特性值为重检验位与原始校验位相同的码字的数量，所述失锁条件为所述总值小于或等于同步阈值；或者，
    所述特性值为重检验位与原始校验位不相同的码字的数量，所述失锁条件为所述总值大于或等于同步阈值；
    其中，所述码字的长度为n比特，所述码字的前k比特为信息位，所述码字的后n-k比特为所述原始校验位，所述重检验位是根据所述信息位获得的，所述重校验位的长度为n-k比特，所述n和所述k为整数。
  26. 根据权利要求1-25任一项所述的方法，其特征在于，所述数据序列为线性分组码。
  27. 一种通信设备，其特征在于，所述通信设备包括：
    接收单元，用于执行步骤一：接收数据序列，所述数据序列包括多个比特；
    处理单元，用于执行步骤二：确定所述数据序列中的备选比特，所述备选比特包括在所述多个比特中；以及步骤三：根据所述备选比特确定同步位置，所述同步位置用于指示所述数据序列中码字的起始位置。
  28. 根据权利要求27所述的通信设备，其特征在于，
    所述处理单元，还用于对所述备选比特进行验证，当验证成功时，确定所述备选比特的位置为所述同步位置。
  29. 根据权利要求28所述的通信设备，其特征在于，
    所述处理单元，还用于根据所述备选比特在所述数据序列中划分出至少一个第二测试数据块，所述备选比特的位置为所述至少一个第二测试数据块的起始位置；对所述至少一个第二测试数据块的特性值进行验证，当验证成功时，确定所述备选比特的位置为所述同 步位置。
  30. 根据权利要求29所述的通信设备，其特征在于，
    所述处理单元，还用于依次累计所述至少一个第二测试数据块中各个第二测试数据块的特性值以获得累计值，直至所述累计值满足同步条件时，验证成功。
  31. 根据权利要求30所述的通信设备，其特征在于，
    所述特性值为被判定为正确码字的第二测试数据块的数量，所述同步条件为所述累计值大于或等于同步阈值；或者
    所述特性值为校验序列中全零序列的数量，所述同步条件为所述累计值大于或等于同步阈值；或者，
    所述特性值为校验序列中零元素的数量，所述同步条件为所述累计值大于或等于同步阈值；或者，
    所述特性值为可纠错测试数据块的数量，所述同步条件为所述累计值大于或等于同步阈值；或者，
    所述特性值为重检验位与原始校验位相同的测试数据块的数量，所述同步条件为所述累计值大于或等于同步阈值；
    其中，所述测试数据块的长度为n比特，所述测试数据块的前k比特为信息位，所述测试数据块的后n-k比特为所述原始校验位，所述重检验位是根据所述信息位获得的，所述重校验位的长度为n-k比特，所述n和所述k为整数。
  32. 根据权利要求29所述的通信设备，其特征在于，
    所述处理单元，还用于将所述至少一个第二测试数据块中所有第二测试数据块的特性值相加以获得总值，当所述总值满足同步条件时，验证成功。
  33. 根据权利要求32所述的通信设备，其特征在于，
    所述特性值为所述所有第二测试数据块中被判定为正确码字的测试数据块的数量，所述同步条件为所述累计值大于或等于同步阈值；或者
    所述特性值为所述所有第二测试数据块中被判定为错误码字的测试数据块的数量，所述同步条件为所述累计值小于或等于同步阈值；或者
    所述特性值为校验序列中全零序列的数量，所述同步条件为所述总值大于或等于同步阈值；或者，
    所述特性值为校验序列中非全零序列的数量，所述同步条件为所述总值小于或等于同步阈值；或者，
    所述特性值为校验序列中零元素的数量，所述同步条件为所述总值大于或等于同步阈值；或者，
    所述特性值为校验序列中非零元素的数量，所述同步条件为所述总值小于或等于同步阈值；或者，
    所述特性值为可纠错测试数据块的数量，所述同步条件为所述总值大于或等于同步阈值；或者，
    所述特性值为不可纠错测试数据块的数量，所述同步条件为所述总值小于或等于同步阈值；或者，
    所述特性值为重检验位与原始校验位相同的测试数据块的数量，所述同步条件为所述 总值大于或等于同步阈值；或者，
    所述特性值为重检验位与原始校验位不相同的测试数据块的数量，所述同步条件为所述总值小于或等于同步阈值；
    其中，所述测试数据块的长度为n比特，所述测试数据块的前k比特为信息位，所述测试数据块的后n-k比特为所述原始校验位，所述重检验位是根据所述信息位获得的，所述重校验位的长度为n-k比特，所述n和所述k为整数。
  34. 根据权利要求27所述的通信设备，其特征在于，
    所述处理单元，还用于将所述备选比特的位置作为所述同步位置。
  35. 根据权利要求27所述的通信设备，其特征在于，
    所述处理单元，还用于从所述数据序列中选取多个观察比特；从所述多个观察比特中选取所述备选比特。
  36. 根据权利要求35所述的通信设备，其特征在于，
    所述处理单元，还用于根据所述多个观察比特从所述数据序列中确定多组第一测试数据块，其中，所述多组第一测试数据块中的每组第一测试数据块包括至少一个第一测试数据块，所述多个观察比特中的每一个观察比特的位置为所述多组第一测试数据块中的每组第一测试数据块的起始位置；根据所述多组第一测试数据块的特性值，从所述多个观察比特中选取一个观察比特作为所述备选比特。
  37. 根据权利要求36所述的通信设备，其特征在于，其中，
    所述处理单元，还用于依次判断所述多组第一测试数据块中各组第一测试数据块的特性值是否满足备选条件，直至确定出一组第一测试数据块的特性值满足所述备选条件；将满足所述备选条件的所述一组第一测试数据块对应的观察比特作为所述备选比特。
  38. 根据权利要求37所述的通信设备，其特征在于，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中被判定为正确码字的第一测试数据块的数量总值，所述备选条件为所述累计值大于或等于同步阈值；或者
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中被判定为正确码字的第一测试数据块的数量总值，所述备选条件为所述累计值小于或等于同步阈值；或者
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块的校验序列中全零序列的数量总值，所述备选条件为所述总值大于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块的校验序列中非全零序列的数量总值，所述备选条件为所述总值小于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块的校验序列中零元素的数量总值，所述备选条件为所述总值大于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块的校验序列中非零元素的数量总值，所述备选条件为所述总值小于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块中可纠错测试数据块的数量总值，所述备选条件为所述总值大于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块中不可纠错测试数据块的数量总值，所述备选条件为所述总值小于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块中重检验位与原始校验位相同的测试数据块的数量总值，所述备选条件为所述总值大于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中所有第一测试数据块中重检验位与原始校验位不相同的测试数据块的数量总值，所述备选条件为所述总值小于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中前X个第一测试数据块的校验序列中全零序列的数量累计值，所述备选条件为所述累计值大于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中前X个第一测试数据块的校验序列中零元素的数量累计值，所述备选条件为所述累计值大于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中前X个第一测试数据块中可纠错测试数据块的数量累计值，所述备选条件为所述累计值大于或等于同步阈值；或者，
    所述一组第一测试数据块的特性值为所述一组第一测试数据块中前X个第一测试数据块中重检验位与原始校验位相同的测试数据块的数量累计值，所述备选条件为所述累计值大于或等于同步阈值；
    其中，所述测试数据块的长度为n比特，所述测试数据块的前k比特为信息位，所述测试数据块的后n-k比特为所述原始校验位，所述重检验位是根据所述信息位获得的，所述重校验位的长度为n-k比特，所述n，所述k和所述X为整数。
  39. 根据权利要求36所述的通信设备，其特征在于，
    所述处理单元，还用于比较所述多组第一测试数据块中每组第一测试数据块的特性值，将所述特性值为极值的一组第一测试数据块对应的观察比特作为所述备选比特。
  40. 根据权利要求39所述的通信设备，其特征在于，
    所述特性值为被判定为正确码字的第一测试数据块的数量，所述极值为最大值；或者，
    所述特性值为被判定为错误码字的第一测试数据块的数量，所述极值为最小值；或者，
    所述特性值为校验序列中全零序列的数量，所述极值为最大值；或者，
    所述特性值为校验序列中非全零序列的数量，所述极值为最小值；或者，
    所述特性值为校验序列中零元素的数量，所述极值为最大值；或者，
    所述特性值为校验序列中非零元素的数量，所述极值为最小值；或者，
    所述特性值为可纠错测试数据块的数量，所述极值为最大值；或者，
    所述特性值为不可纠错测试数据块的数量，所述极值为最小值；或者，
    所述特性值为重检验位与原始校验位相同的测试数据块的数量，所述极值为最大值；或者，
    所述特性值为重检验位与原始校验位不相同的测试数据块的数量，所述极值为最小值；
    其中，所述测试数据块的长度为n比特，所述测试数据块的前k比特为信息位，所述测试数据块的后n-k比特为所述原始校验位，所述重检验位是根据所述信息位获得的，所述重校验位的长度为n-k比特，所述n和所述k为整数。
  41. 根据权利要求35-40任一项所述的通信设备，其特征在于，
    所述处理单元，还用于从所述数据序列中每间隔T个比特选取一个比特，作为所述观察比特，所述T为大于零的整数；或者，
    所述处理单元，还用于从所述数据序列中每间隔L*n+T个比特选取一个比特，作为所述观察比特，所述L为间隔的测试数据块的数量，所述测试数据块的长度为所述n个比特，所述L和所述T为大于零的整数。
  42. 根据权利要求35-40任一项所述的通信设备，其特征在于，
    所述处理单元，还用于从所述数据序列中每间隔T个调制码元，选取调制码元的起始比特，作为所述观察比特，所述T为大于零的整数；或者，
    所述处理单元，还用于从所述数据序列中每间隔L*m+T个调制码元，选取调制码元的起始比特，作为所述观察比特，所述L为间隔的测试数据块的数量，所述测试数据块的长度为所述m个调制码元，所述L和所述T为大于零的整数。
  43. 根据权利要求35-42任一项所述的通信设备，其特征在于，所述观察比特的数量为P，所述P为正整数，所述码字的长度为所述P个比特。
  44. 根据权利要求29-33任一项所述的通信设备，其特征在于，其中，
    所述步骤二中，所述确定所述数据序列中的备选比特包括，确定第一子序列中的备选比特，所述步骤三中，所述根据所述备选比特在所述数据序列中划分出至少一个第二测试数据块包括，根据所述备选比特在第二子序列中划分出至少一个第二测试数据块，所述第一子序列和所述第二子序列包括在所述数据序列中，所述第二子序列与所述第一子序列相同、部分相同或不同。
  45. 根据权利要求27-44任一项所述的通信设备，其特征在于，
    所述处理单元，还用于执行步骤四：响应于所述数据序列为失锁状态，确定所述数据序列的更新同步位置。
  46. 根据权利要求45所述的通信设备，其特征在于，
    所述处理单元，还用于重新执行所述步骤二和所述步骤三，将重新执行的步骤三所确定的同步位置作为所述更新同步位置。
  47. 根据权利要求45或46所述的通信设备，其特征在于，
    所述处理单元，还用于根据所述同步位置从所述数据序列中划分出多个同步码字，所述同步位置为所述多个同步码字的起始位置；对所述多个同步码字的特性值进行验证，当验证失败时，确定所述数据序列为所述失锁状态。
  48. 根据权利要求47所述的通信设备，其特征在于，
    所述处理单元，还用于依次累计所述多个同步码字中各个同步码字的特性值以获得累计值，直至所述累计值满足失锁条件时，验证失败。
  49. 根据权利要求48所述的通信设备，其特征在于，
    所述特性值的累计值为所述多个同步码字中被判定为错误码字的总数量，所述失锁条件为所述累计值大于或等于同步阈值；或者，
    所述特性值为校验序列中非全零序列的数量，所述失锁条件为所述累计值大于或等于同步阈值；或者，
    所述特性值为校验序列中非零元素的数量，所述失锁条件为所述累计值大于或等于同步阈值；或者，
    所述特性值为不可纠错码字的数量，所述失锁条件为所述累计值大于或等于同步阈值；或者，
    所述特性值为重检验位与原始校验位不相同的码字的数量，所述失锁条件为所述累计值大于或等于同步阈值；
    其中，所述码字的长度为n比特，所述码字的前k比特为信息位，所述码字的后n-k比特为所述原始校验位，所述重检验位是根据所述信息位获得的，所述重校验位的长度为n-k比特，所述n和所述k为整数。
  50. 根据权利要求47所述的通信设备，其特征在于，
    所述处理单元，还用于将所述多个同步码字中所有同步码字的特性值相加以获得总值，当所述总值满足失锁条件时，验证失败。
  51. 根据权利要求50所述的通信设备，其特征在于，
    所述特性值的总值为所述多个同步码字中被判定为正确码字的总数量，所述失锁条件为所述总值小于或等于同步阈值；或者，
    所述特性值的总值为所述多个同步码字中被判定为错误码字的总数量，所述失锁条件为所述总值大于或等于同步阈值；或者，
    所述特性值为校验序列中全零序列的数量，所述失锁条件为所述总值小于或等于同步阈值；或者，
    所述特性值为校验序列中非全零序列的数量，所述失锁条件为所述总值大于或等于同步阈值；或者，
    所述特性值为校验序列中零元素的数量，所述失锁条件为所述总值小于或等于同步阈值；或者，
    所述特性值为校验序列中非零元素的数量，所述失锁条件为所述总值大于或等于同步阈值；或者，
    所述特性值为可纠错码字的数量，所述失锁条件为所述总值小于或等于同步阈值；或者，
    所述特性值为不可纠错码字的数量，所述失锁条件为所述总值大于或等于同步阈值；或者，
    所述特性值为重检验位与原始校验位相同的码字的数量，所述失锁条件为所述总值小于或等于同步阈值；或者，
    所述特性值为重检验位与原始校验位不相同的码字的数量，所述失锁条件为所述总值大于或等于同步阈值；
    其中，所述码字的长度为n比特，所述码字的前k比特为信息位，所述码字的后n-k比特为所述原始校验位，所述重检验位是根据所述信息位获得的，所述重校验位的长度为n-k比特，所述n和所述k为整数。
  52. 根据权利要求27-51任一项所述的通信设备，其特征在于，所述数据序列为线性 分组码。
  53. 一种通信设备，其特征在于，所述通信设备包括：处理器、通信接口和存储器，存储器可以用于存储程序代码，处理器用于调用存储器中的程序代码执行权利要求1-26任一项所述的方法。
  54. 一种芯片，其特征在于，所述芯片包括存储器和处理器，存储器用于存储计算机程序，处理器用于从存储器中调用并运行所述计算机程序，以执行权利要求1-26任一项所述的方法。
  55. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有计算机程序，当所述计算机程序在处理器上运行时，实现权利要求1-26任一项所述的方法。
  56. 一种网络系统，其特征在于，所述网络系统包括发送设备和接收设备，所述接收设备为权利要求27-53任一项所述的通信设备。
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