WO2021201247A1 - Signal detection circuit, drive/detection circuit, sensor array, and sensor system - Google Patents

Signal detection circuit, drive/detection circuit, sensor array, and sensor system Download PDF

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Publication number
WO2021201247A1
WO2021201247A1 PCT/JP2021/014220 JP2021014220W WO2021201247A1 WO 2021201247 A1 WO2021201247 A1 WO 2021201247A1 JP 2021014220 W JP2021014220 W JP 2021014220W WO 2021201247 A1 WO2021201247 A1 WO 2021201247A1
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Prior art keywords
signal
wiring
circuit
thin film
film transistor
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PCT/JP2021/014220
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French (fr)
Japanese (ja)
Inventor
守 石▲崎▼
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凸版印刷株式会社
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Priority to JP2022511141A priority Critical patent/JPWO2021201247A1/ja
Publication of WO2021201247A1 publication Critical patent/WO2021201247A1/en

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01LMEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L1/00Measuring force or stress, in general
    • G01L1/18Measuring force or stress, in general using properties of piezo-resistive materials, i.e. materials of which the ohmic resistance varies according to changes in magnitude or direction of force applied to the material
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01LMEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L5/00Apparatus for, or methods of, measuring force, work, mechanical power, or torque, specially adapted for specific purposes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present disclosure relates to signal detection circuits, drive detection circuits, sensor arrays and sensor systems.
  • an in-plane pressure distribution can be detected by using a pressure sensor array that combines a thin film transistor array and a pressure sensitive medium.
  • the pressure-sensitive medium there are those whose resistance changes depending on the pressure (Patent Document 1) and those whose potential difference changes depending on the pressure (Patent Document 2).
  • an in-plane temperature distribution can be detected by using a temperature sensor array that combines a thin film transistor array and a temperature sensitive medium.
  • a sensor array usually has detection points (referred to as "pixels") corresponding to intersections of a plurality of scanning wires and a plurality of signal wires, and a circuit that detects a signal from the sensor array when the number of signal wires increases. Will also grow in scale.
  • the most easily conceivable signal detection circuit is to provide the same number of load resistors 122, voltage detection amplifier 123, and AD converter 124 as the number of signal wiring 115 as shown in FIG. 29, but requires a large area and cost. ..
  • the signal detection circuit inputs the outputs of the plurality of signal wirings 115 to one switching circuit 100 after passing through the voltage detection amplifier 123, and outputs the output of one switching circuit 100 to one AD converter 124.
  • I'm typing For example, in the circuit described in Patent Document 3, the outputs from a plurality of electrodes are input to one multiplexer after passing through an operational amplifier, and the output of the one multiplexer is input to one A / D converter. You are typing.
  • a drive circuit including a signal detection circuit as shown in FIG. 30 is shown in FIG. The drive detection circuit of FIG.
  • the present disclosure has been made in view of the situation of the prior art, and an object of the present invention is to provide a signal detection circuit having a small scale. Another object of the present invention is to provide a drive detection circuit having a small scale and a small error when the drive detection circuit includes a drive circuit and a control circuit in the signal detection circuit.
  • a is a plurality of signal lines are divided into M 2 blocks one by one M, in each of the M 2 blocks are first the signal lines of one M is connected to the input
  • a second switching circuit is provided, and a load resistance and voltage detection amplifier connected to the output of the first switching circuit are provided, and each output from the M 2 blocks is connected to an input.
  • It is a signal detection circuit having a switching circuit and an AD converter connected to the output of the second switching circuit.
  • a pixel electrode including a plurality of pixel portions including a second thin film transistor, a drain wiring for supplying power to the drain electrode of the first thin film transistor, a sensor portion connected to the pixel electrode, and a common electrode connected to the sensor portion.
  • the drain electrode of the first thin film transistor is connected to the drain wiring
  • the source electrode of the first thin film transistor is connected to the drain electrode of the second thin film transistor
  • the gate electrode of the second thin film transistor is the scanning wiring.
  • the source electrode of the second thin film transistor is a sensor array connected to the signal wiring.
  • a sensor system comprising a sensor array and a signal detection circuit, wherein the sensor array includes a plurality of signal wirings, a plurality of scanning wirings intersecting the signal wirings, and a signal wiring.
  • a plurality of pixel portions including a pixel electrode, a first thin film, and a second thin film, a drain wiring for supplying power to the drain electrode of the first thin film, and a pixel electrode, which are provided corresponding to each of the intersections of the scanning wiring and the scanning wiring.
  • a sensor unit to be connected and a common electrode connected to the sensor unit are provided, the pixel electrode is connected to the gate electrode of the first thin film, the drain electrode of the first thin film is connected to the drain wiring, and the source of the first thin film is connected.
  • the electrode is connected to the drain electrode of the second thin film, the gate electrode of the second thin film is connected to the scanning wiring, the source electrode of the second thin film is connected to the signal wiring, and the signal detection circuit has a plurality of signal wirings.
  • a second switching circuit is provided with a connected load resistance and voltage detection amplifier, and each output from the M2 blocks is connected to the input, and an AD converter connected to the output of the second switching circuit. It is a sensor system having and.
  • the drive detection circuit includes the drive circuit and the control circuit in the signal detection circuit, it is possible to provide a drive detection circuit having a small scale and a small error.
  • FIG. 1 is a circuit diagram illustrating an exemplary signal detection circuit according to the first embodiment of the present disclosure.
  • FIG. 2 is a circuit diagram illustrating an exemplary drive detection circuit including the signal detection circuit of FIG.
  • FIG. 3 is a circuit diagram showing another example of the drive detection circuit including the signal detection circuit of FIG.
  • FIG. 4 is an explanatory diagram showing a simple signal detection method.
  • FIG. 5 is an explanatory diagram schematically showing the signal detection method of the present disclosure.
  • FIG. 6 is a circuit diagram schematically showing a sensor array applied to the first embodiment.
  • FIG. 7 is an explanatory diagram illustrating an exemplary signal detection circuit according to the second embodiment of the present disclosure.
  • FIG. 8 is an explanatory diagram illustrating an exemplary drive detection circuit including the signal detection circuit of FIG. 7.
  • FIG. 9 is an explanatory diagram schematically showing the signal detection method of the present disclosure.
  • FIG. 10 is a circuit diagram schematically showing a sensor array applied to the second embodiment.
  • FIG. 11 is an explanatory diagram showing an example of a pixel circuit according to the third embodiment of the present disclosure.
  • FIG. 12 is a plan view and a cross-sectional view showing a specific example of the pixel circuit of FIG.
  • FIG. 13 is an explanatory diagram showing an example of a pixel circuit according to the fourth embodiment of the present disclosure.
  • 14 is a plan view and a cross-sectional view showing a specific example of the pixel circuit of FIG. 13.
  • FIG. 15 is an explanatory diagram showing an example of a pixel circuit according to a fifth embodiment of the present disclosure.
  • FIG. 16 is a plan view and a cross-sectional view showing a specific example of the pixel circuit of FIG.
  • FIG. 17 is an explanatory diagram showing an example of a pixel circuit according to a sixth embodiment of the present disclosure.
  • FIG. 18 is a plan view and a cross-sectional view showing a specific example of the pixel circuit of FIG.
  • FIG. 19 is a block diagram schematically showing the nursing care data collection / determination system of the present disclosure.
  • FIG. 20 is an explanatory diagram showing an arrangement example of the nursing care sensor device of the present disclosure.
  • FIG. 21 is a circuit diagram schematically showing a sensor array applied to the first embodiment.
  • FIG. 22 is a circuit diagram schematically showing a current limiting circuit applied to the seventh embodiment.
  • FIG. 23 is an explanatory diagram including an example of a detection circuit connected to the pixel circuit of FIG.
  • FIG. 24 is an explanatory diagram including another example of the detection circuit connected to the pixel circuit of FIG.
  • FIG. 25 is an explanatory diagram including an example of a detection circuit connected to the pixel circuit of FIG.
  • FIG. 26 is an explanatory diagram including another example of the detection circuit connected to the pixel circuit of FIG.
  • FIG. 27 is an explanatory diagram showing an example of a conventional pixel circuit.
  • FIG. 28 is an explanatory diagram showing another example of the conventional pixel circuit.
  • FIG. 29 is a circuit diagram illustrating a conventional signal detection circuit as an example.
  • FIG. 30 is a circuit diagram showing another example of a conventional signal detection circuit.
  • FIG. 31 is a circuit diagram illustrating a conventional drive detection circuit as an example.
  • each aspect of the present disclosure is an aspect of a group of embodiments based on a single invention.
  • Each configuration of the present disclosure may have each aspect of the present disclosure.
  • Each feature of the present disclosure can be combined to form each configuration. Therefore, each feature of the present disclosure, each configuration of the present disclosure, each aspect of the present disclosure, and each embodiment of the present disclosure can be combined, and the combination exerts a cooperative function and exerts a synergistic effect. Can be done.
  • FIG. 1 shows a circuit diagram showing an example of a signal detection circuit according to the first embodiment of the present disclosure.
  • the target sensor array to which this signal detection circuit is applied has M signal wirings 15.
  • M of signal lines 15 are divided into one by one M M 2 blocks (broken line in the portion surrounded by the Figure 1).
  • the signal wiring 15 of each block is referred to as signal wiring A to M 1
  • the signal wiring A to M 1 is connected to the input of the first switching circuit 101, and the first switching circuit It has two blocks in which the output of 101 is connected to the load resistor 20 and the voltage detection amplifier 53.
  • the presence of the first switching circuit 101, the number of required load resistor 20 and the voltage detecting amplifier 53 is not the M becomes a two M, can be reduced than the number of signal wires 15.
  • the output of the voltage detection amplifier 53 of each block is connected to the input of the second switching circuit 102, and the output of the second switching circuit 102 is connected to the input of the AD converter 25.
  • the number of inputs of one second switching circuit 102 is L
  • the number of AD converters 25 need not the two M, becomes (M 2 / L) number, can be reduced than the number of the voltage detection amplifier 53 .
  • the number of inputs L of the second switching circuit 102 is equal to M 2
  • the number of AD converters 25 required is one.
  • the number of load resistance 20 and the voltage detection amplifier 53 can be reduced from the number of signal wirings 15, and the number of AD converters 25 can be detected by voltage. Since the number can be reduced from the number of amplifiers 53, the scale of the signal detection circuit can be reduced, and the installation area and manufacturing cost can be suppressed.
  • the voltage detection amplifier 53 is described as a voltage follower in FIG. 1, the present invention is not limited to this, and a circuit having an amplification factor other than 1 or an inverting amplifier circuit may be used. Further, the voltage detection amplifier 53 may have a known oscillation prevention circuit, phase compensation circuit, capacitance correction circuit, and protection circuit. Further, a FET (Field Effect Transistor) or the like may be used instead of using an operational amplifier. Further, in FIG. 1, it is described that the load resistor 20 is installed between the signal line and the GND, but when the voltage detection amplifier 53 is an inverting amplifier circuit, it is between the signal line and the output of the voltage detection amplifier 53. It may be installed in.
  • the first switching circuit 101 is an analog multiplexer. If an analog multiplexer is used, switching can be performed at high speed without losing the information of the analog signal. However, if the signal voltage range is too large for the analog multiplexer to handle, a relay may be used.
  • the load resistance 20 is not on the input side but on the output side of the first switching circuit 101, a current flows through the first switching circuit 101 to lower the impedance, and the circuit is less susceptible to noise. Further, since the current flows only in the signal line of the input switched to the output of the first switching circuit 101 among the signal wiring 15 connected to the first switching circuit 101, the power consumption can be suppressed.
  • FIG. 2 shows a circuit diagram showing an example of a drive detection circuit including the signal detection circuit of FIG.
  • the sensor array to which this drive detection circuit is applied has M signal wirings 15 and N scanning wirings 12.
  • the drive detection circuit of FIG. 2 includes a control circuit 5 and a drive circuit 6 in addition to the signal detection circuit according to the present embodiment, and includes a first switching circuit 101, a second switching circuit 102, and an AD.
  • the converter 25 and the drive circuit 6 are controlled by the control circuit 5.
  • digital wiring 48 having the number of bits n (where 2 n-1 ⁇ M 1 ⁇ 2 n ) that can switch the switching circuit having the number of inputs M 1 is required.
  • the digital wiring 48 for switching the input of each block can be made one by one.
  • FIG. 4 shows an easily conceivable signal detection method when the drive detection circuit of FIGS. 2 and 3 is applied.
  • the second switching circuit 102 is switched to the block 1 in advance.
  • the first switching circuit 101 of the block 1 is set to the signal A, and the data of the signal A is read by the AD converter 25.
  • the first switching circuit 101 is set to signal B, and the data of signal B is read by the AD converter 25.
  • the second switching circuit 102 is switched to the block 2, and the signals A to M 1 of the block 2 are read in order in the same manner as the block 1. ..
  • the data can be read in the order of pixel arrangement, which is easy to understand, but has the following problems.
  • the improved signal detection method will be described with reference to FIG. In FIG. 5, all the first switching circuits 101 are switched to the signal A in advance. After applying the on-voltage to the first line of the scanning wiring 12, wait for a certain period of time.
  • the second switching circuit 102 is switched to the block 1, the data of the signal A of the block 1 is read by the AD converter 25, and then the first switching circuit 101 of the block 1 is set to the signal B.
  • the second switching circuit 102 is switched to the block 2, the data of the signal A of the block 2 is read by the AD converter 25, and then the first switching circuit 101 of the block 2 is set to the signal B.
  • block 3, block 4, also performed on ... also applies to the block M 2, i.e., by switching the second switching circuit 102 to the block M 2, the data signal A of the block M 2 AD
  • the first switching circuit 101 of the block M 2 is set to the signal B.
  • the second switching circuit 102 is switched to the block 1, the data of the signal B of the block 1 is read by the AD converter 25, and then the first switching circuit 101 of the block 1 is set to the signal C.
  • the second switching circuit 102 is switched to the block 2, the data of the signal B of the block 2 is read by the AD converter 25, and then the first switching circuit 101 of the block 2 is set to the signal C.
  • block 3, block 4, also performed on ... also applies to the block M 2, i.e., by switching the second switching circuit 102 to the block M 2, AD converter data signal B block M2
  • the first switching circuit 101 of the block M 2 is set to the signal C.
  • block 3, block 4 do the same for., Same for block M 2, i.e., by switching the second switching circuit 102 to the block M 2, the data of the signal M 1 of the block M 2 after reading the AD converter 25, the first switching circuit 101 of the block M 2 to the signal a.
  • this description is specifically described for the sake of clarity , and does not limit the signal M 1 to be later than the signal E, that is, does not limit it to M 1 > 5.
  • 1 may be an integer of 2 or more.
  • the block M 2 is not limited to being later than the block 4, that is, it is not limited to M 2 > 4, and M 2 may be an integer of 2 or more.
  • the characteristics of the signal detection method of FIG. 5 will be shown.
  • the measurement of the signal of the signal wiring selected by the first switching circuit of the other block is performed one or more times. As a result, it is possible to gain time from switching the first switching circuit 101 until the signal stabilizes, and it is possible to improve the accuracy of signal measurement.
  • the number of blocks is two M
  • the switching of the first signal switching circuit 101, between the measurement of the switching signal, the other (M 2 -1) measurements easily be performed can.
  • the control circuit 5 performs a first process of causing the drive circuit 6 to apply an on-voltage to one scanning wiring selected from the plurality of scanning wirings 12. After applying the on-voltage, wait for a certain period of time. Then, in one block selected by the second switching circuit, the signal of one signal wiring selected by the first switching circuit is read out via the AD converter 25, and one by the first switching circuit 101. A procedure for selecting another block different from one block by the second switching circuit 102 after selecting another signal line different from the signal wiring and before reading the signal of the selected other signal wiring 15.
  • a second process is performed in which the signals of the sensor unit for one line corresponding to the one scanning wiring 12 are read out in order.
  • the drive circuit 6 is subjected to a third process of applying an off voltage to one scanning wiring 12 selected after the completion of the second process.
  • the signals of all the sensor units are read out by repeating the first process, the standby, the second process, and the third process for all the scanning wirings 12.
  • the procedure of selecting another signal line different from one signal wiring 15 by the first switching circuit 101 and the selection of another block different from one block by the second switching circuit 102 may be reversed. That is, the second process is performed after reading the signal of one signal wiring 15 selected by the first switching circuit 101 in one block selected by the second switching circuit 102 via the AD converter 25. After selecting another block different from one block by the second switching circuit 102 and selecting another signal line different from one signal wiring 15 for the first switching circuit 101 of one block, 1 Before reading the signal of the other signal wiring 15 of one block, the procedure of reading the signal of the other block, the procedure of switching the second switching circuit 102, and the procedure of switching the first switching circuit 101 of the other block. , And, by these processes, the signal of one line of the sensor unit corresponding to one selected scanning wiring 12 may be read out in order.
  • the "predetermined time” is the measurement time of the AD converter 25 (M 2 -1) times or more. Then, regarding the signal A of the block 1, which is the first measurement of one screen, the measurement of the AD converter 25 is performed after the first switching circuit 101 is switched to the signal A and before the measurement of the signal A is performed. to be able to sandwich the time ⁇ (M 2 -1) or more, the signal as with the measurement of other signals can earn time to stabilize, improve the accuracy of signal measurement to the same extent as the other signal be able to.
  • FIG. 6 is a circuit diagram showing an example of a sensor array applied to the first embodiment.
  • a pixel circuit consisting of the first thin film transistor T1 and the second thin film transistor T2 is assembled at the intersection of the matrix of N scanning wires 12 and M signal wirings 15, and the gate of the first thin film transistor T1 is formed.
  • a pressure-sensitive medium 9, for example, is provided as a sensor unit 109 between the electrode and the common electrode 10.
  • the drain wiring 14 is connected to the drain of the first thin film transistor T1, the source of the first thin film transistor T1 is connected to the drain of the second thin film transistor T2, and the gate of the second thin film transistor T2 is connected to the scanning wiring 12.
  • the source of the second thin film transistor T2 is connected to the signal wiring 15.
  • a pressure-dependent voltage is generated in the pressure-sensitive medium 9.
  • a pressure sensitive medium 9 for example, polyvinylidene fluoride (PVDF) or polyvinylidene fluoride-trifluoroethylene copolymer is suitable. Note that FIG.
  • FIG. 21 is a circuit diagram showing an example of a sensor array applied to the first embodiment.
  • a pixel circuit by the thin film transistor 38 is assembled at the intersection of the matrix of N scanning wires 12 and M signal wires 15, and the pressure is sensitive between the drain electrode of the thin film transistor 38 and the power supply wiring 36. It has a medium 39.
  • the gate of the thin film transistor 38 is connected to the scanning wire 12, and the source of the thin film transistor 38 is connected to the signal wire 15.
  • the resistance value of the pressure sensitive medium 39 changes depending on the pressure. When one of the scanning wires 12 is turned on, a current that depends on the pressure of the pixels in that row flows through the signal wires 15.
  • the pressure sensitive medium 39 rubber or the like in which conductive particles are dispersed is suitable.
  • another sensor unit 109 may be adopted and used for another type of pressure sensor, displacement sensor, temperature sensor, or the like.
  • the power supply wiring 36 may have a current limiting circuit 40 described later in the seventh embodiment.
  • the number of the load resistance 20 and the voltage detection amplifier 53 is increased by providing the first switching circuit 101 on the upstream side of the load resistance 20 and the voltage detection amplifier 53. Further, by providing the second switching circuit 102 on the downstream side of the voltage detection amplifier 53, the number of AD converters 25 can be reduced, and the scale of the signal detection circuit can be reduced. Further, by applying the signal detection circuit, the scale of the drive detection circuit can be reduced. Further, after the signal is switched by the first switching circuit 101 and before the measurement of the signal is performed, the switched and unmeasured signals of other blocks are measured, so that the measurement is performed after the switching signal becomes stable. It can be performed.
  • FIG. 7 is an explanatory diagram showing an example of the signal detection circuit according to the second embodiment of the present disclosure.
  • the sensor array to which this signal detection circuit is applied has M signal wirings 15 and M reference signal wirings 16.
  • Signal lines 15 and the reference signal lines 16 are divided into M 2 blocks one by one each M.
  • the signal wirings A to M 1 of each block are connected to the input of the first switching circuit 101, and the output of the first switching circuit 101 is connected to the load resistance 20 and the voltage detection amplifier 53.
  • the reference signal wirings A to M 1 of each block are connected to the input of the third switching circuit 103, and the output of the third switching circuit 103 is connected to the load resistance 21 and the voltage detection amplifier 54. Therefore, the required load resistance and the number of voltage detection amplifiers are not the total of the signal wiring 15 and the reference signal wiring 16 (M ⁇ 2), but twice the number of blocks (M 2 ⁇ 2).
  • the output of the voltage detection amplifier 53 of the signal and the output of the voltage detection amplifier 54 of the reference signal corresponding to the signal are input to the differential amplifier circuit 24.
  • the number of differential amplifier circuits 24 required is M 2 , which is the same as the number of blocks.
  • the output of the differential amplifier circuit 24 is connected to the input of the second switching circuit 102, and the output of the second switching circuit 102 is connected to the input of the AD converter 25.
  • the number of inputs of the second switching circuit 102 is L
  • the number of AD converters 25 need not the two M, becomes (M 2 / L) number, it can be reduced than the number of the differential amplifier circuit 24.
  • the number of inputs L of the second switching circuit 102 is equal to M 2 , the number of AD converters 25 required is one.
  • the number of the load resistance 20 and the voltage detection amplifier 53 can be reduced from the number of the signal wiring 15. Since the number of load resistors 21 and voltage detection amplifiers 54 can be reduced from the number of reference signal wirings 16 and the number of AD converters 25 can be reduced from the number of differential amplifier circuits 24, the scale of the signal detection circuits can be reduced and installed. Area and cost can be reduced.
  • the present invention is not limited to this, and a circuit having an amplification factor other than 1 or an inverting amplifier circuit may be used. Further, the voltage detection amplifiers 53 and 54 may have known oscillation prevention circuits, phase compensation circuits, capacitance correction circuits, and protection circuits. Further, FET or the like may be used instead of the operational amplifier. Further, in FIG. 7, it is described that the load resistors 20 and 21 are installed between the signal line and the GND, but when the voltage detection amplifiers 53 and 54 are inverting amplifier circuits, the output of the signal line and the inverting amplifier circuit It may be installed between.
  • the differential amplifier circuit 24 may be a circuit in which the amplification factor is 1 and the difference between the signal and the reference signal is observed, but the amplification factor may be other than 1. Further, the differential amplifier circuit 24 can shift the output voltage by the base voltage Vbase. In the differential amplifier circuit 24, by adding Vbase to the signal wiring output-reference output, even when the signal wiring output-reference output is small or negative, it can be reliably detected.
  • the first switching circuit 101 and the third switching circuit 103 are analog multiplexers.
  • an analog multiplexer switching is possible at high speed without losing the information of the analog signal.
  • a relay may be used.
  • FIG. 8 is an explanatory diagram showing an example of a drive detection circuit including the signal detection circuit of FIG.
  • the sensor array to which this drive detection circuit is applied has M signal wirings 15, M reference signal wirings 16, and N scanning wirings 12.
  • the drive detection circuit of FIG. 8 includes a control circuit 5 and a drive circuit 6 in addition to the signal detection circuit according to the present embodiment, and includes a first switching circuit 101, a third switching circuit 103, and a third switching circuit 103.
  • the switching circuit 102 of 2, the AD converter 25, and the drive circuit 6 are controlled by the control circuit 5.
  • the counter 49 is used to control the first switching circuit 101 and the third switching circuit 103. If the counter 49 is used, the digital wiring 48 for switching the input of each block can be made one by one.
  • the signal detection method shown in FIG. 9 is desirable instead of the simple signal detection method as in the first embodiment.
  • the data corresponding to the difference between the signal A of the block 1 and the reference signal A is read by the AD converter 25, and then the first switching circuit 101 of the block 1 is used as the signal B and the third switching circuit 103 of the block 1 is used.
  • the second switching circuit 102 is switched to the block 2
  • the data corresponding to the difference between the signal A and the reference signal A of the block 2 is read by the AD converter 25, and then the first switching circuit 101 of the block 2 is used.
  • the third switching circuit 103 of the block 2 is used as the reference signal B.
  • the second switching circuit 102 is switched to the block 1, the data corresponding to the difference between the signal B and the reference signal B of the block 1 is read by the AD converter 25, and then the first switching circuit 101 of the block 1 is signaled.
  • the third switching circuit 103 of the block 1 is used as the reference signal C.
  • the second switching circuit 102 is switched to the block 2, the data corresponding to the difference between the signal B and the reference signal B of the block 2 is read by the AD converter 25, and then the first switching circuit 101 of the block 2 is used.
  • the third switching circuit 103 of the block 2 is used as the reference signal C.
  • the second switching circuit 102 by switching the second switching circuit 102 to the block 2, the data corresponding to the difference between the signal M 1 and the reference signal M 1 of the block 2 from the loading by the AD converter 25, a first switching circuit block 2 101 is used as the signal A, and the third switching circuit 103 of the block 2 is used as the reference signal A.
  • the same applies to the block M 2 that is, the second switching circuit 102 is switched to the block M 2 , and the signal M 1 and the reference signal of the block M 2 are switched.
  • data corresponding to the difference between M 1 after reading the AD converter 25 a first switching circuit 101 of the block M 2 to the signal a, the third switching circuit 103 of the block M 2 in the reference signal a.
  • the signal M 1 may be later than the signal E, that is, does not limit it to M 1 > 5.
  • 1 may be an integer of 2 or more.
  • the block M 2 is not limited to being later than the block 4, that is, it is not limited to M 2 > 4, and M 2 may be an integer of 2 or more.
  • the feature of the signal detection method of FIG. 9 is that after switching to the signal wiring selected by the first switching circuit 101 and the reference signal corresponding to the signal wiring, before measuring the signal difference between them, the other The measurement of the difference between the signal of the signal wiring selected by the first switching circuit 101 of the block and the signal of the reference signal wiring corresponding to the signal wiring is performed one or more times. As a result, it is possible to gain time from switching the first switching circuit 101 and the third switching circuit 103 until the signal stabilizes, and it is possible to improve the accuracy of signal measurement. Especially when the number of blocks is two M, it can be easily sandwich the measurements (M 2 -1) times.
  • the control circuit 5 performs a first process of causing the drive circuit 6 to apply an on-voltage to one scanning wiring 12 selected from the plurality of scanning wirings 12. After applying the on-voltage, wait for a certain period of time. Then, in one block selected by the second switching circuit 102, one signal wiring 15 selected by the first switching circuit 101 and one signal wiring 15 selected by the third switching circuit 103. The signal difference of the reference signal wiring 16 corresponding to the above is read out via the AD converter 25, and one signal wiring 15 and another signal line different from the reference signal wiring 16 and the reference signal wiring 16 are read by the first and third switching circuits.
  • the procedure of selecting another block different from one block by the second switching circuit 102 and the signal difference After selecting, and before reading the signal difference of the other selected signal wiring 15 and the reference signal wiring 16, the procedure of selecting another block different from one block by the second switching circuit 102 and the signal difference. There is a procedure of reading out, a procedure of switching the first and third switching circuits of other blocks, and a procedure of selecting one block by the second switching circuit 102, and the selection is performed by these processes. A second process is performed in which the signal difference of one line of the sensor unit corresponding to the one scanning wiring 12 is read out in order. Further, the drive circuit 6 is subjected to a third process of applying an off voltage to one scanning wiring 12 selected after the completion of the second process. The signals of all the sensor units are read out by repeating the first process, the standby, the second process, and the third process for all the scanning wirings 12.
  • a procedure for selecting another signal wiring 15 and a reference signal wiring 16 different from one signal wiring 15 and the reference signal wiring 16 by the first and third switching circuits in one block, and a second switching circuit 102 may be reversed. That is, in the second process, in one block selected by the second switching circuit 102, the signal difference between the one signal wiring 15 and the reference signal wiring 16 selected by the first and third switching circuits is AD. After reading through the converter 25, another block different from one block is selected by the second switching circuit 102, and the first and third switching circuits of one block are connected to one signal wiring 15 and a reference signal.
  • the signals of one line of the sensor unit corresponding to 12 may be read out in order.
  • the first switching circuit 101 and the third switching circuit 103 of one block select the other signal wiring 15 and the reference wiring 16 different from the one signal wiring 15 and the reference signal wiring 16. After that, before reading the signal difference of the other signal wiring 15 and the reference signal wiring 16 of one block, at least the procedure of reading the signal difference of the other block, the procedure of switching the second switching circuit 102, and other procedures. The procedure for switching the first switching circuit 101 and the third switching circuit 103 of the block is repeated.
  • the "predetermined time” is the measurement time of the AD converter 25 (M 2 -1) times or more. Then, regarding the difference between the signal A and the reference signal A of the block 1, which is the first measurement on one screen, the signal after switching the first switching circuit 101 and the third switching circuit 103 to the signal A by performing the measurement of the difference between a and the reference signal a, to be able to sandwich the measuring time ⁇ (M 2 -1) or more AD converters 25, is measured as well as signal and reference signals of the other signal difference It is possible to gain time until it stabilizes, and the accuracy of signal measurement can be improved to the same level as other signal differences. Further, since the measurement is performed after the signal and the reference signal are stable, the time constant until the signal stabilizes and the time constant until the reference signal stabilizes do not necessarily have to match.
  • FIG. 10 is a circuit diagram showing an example of a sensor array applied to the second embodiment.
  • a pixel circuit consisting of the first thin film transistor T1 and the second thin film transistor T2 is assembled at the intersection of the matrix of N scanning wires 12 and M signal wirings 15, and the gate of the first thin film transistor T1 is formed.
  • a pressure-sensitive medium 9, for example, is provided as a sensor unit 109 between the electrode and the common electrode 10.
  • a reference circuit by a third thin film transistor T3 and a fourth thin film transistor T4 is assembled at the intersection of N scanning wires 12 and M reference signal wirings 16, and the third thin film transistor T3 becomes the first thin film transistor T1.
  • the channel length / channel width of the third thin film transistor T3 is equal to the channel length / channel width of the first thin film transistor T1
  • the channel length / channel width of the fourth thin film transistor T4 is the channel length / channel of the second thin film transistor T2.
  • the drain wiring 14 is connected to the drain of the first thin film transistor T1, the source of the first thin film transistor T1 is connected to the drain of the second thin film transistor T2, and the gate of the second thin film transistor T2 is connected to the scanning wiring 12.
  • the source of the second thin film transistor T2 is connected to the signal wiring 15. A voltage that depends on the stimulus (pressure, etc.) is generated in the sensor unit 109.
  • the common electrode 10 is connected to the gate of the third thin film transistor T3, the drain wiring 14 is connected to the drain of the third thin film transistor T3, and the source of the third thin film transistor T3 is the drain of the fourth thin film transistor T4.
  • the gate of the fourth thin film transistor T4 is connected to the scanning wire 12, and the source of the fourth thin film transistor T4 is connected to the reference signal wire 16.
  • a current that depends on the pressure of the pixels in that row flows through the signal wiring 15, and a current that has characteristics similar to those of the pixel circuit in that row and does not depend on stimuli (pressure, etc.).
  • a pressure sensitive medium 9 for example, polyvinylidene fluoride (PVDF) or polyvinylidene fluoride-trifluoroethylene copolymer is suitable.
  • PVDF polyvinylidene fluoride
  • the sensor array applicable to this embodiment is not limited to the sensor array having the structure shown in FIG.
  • a pressure-sensitive medium whose resistance changes depending on the pressure may be used, and a signal of an element to which pressure is applied and a reference signal of an element to which pressure is not applied may be used.
  • another sensor unit 109 may be adopted and used for another type of pressure sensor, displacement sensor, temperature sensor, or the like.
  • the drain wiring 14 may have a current limiting circuit 40 described later in the seventh embodiment.
  • the in-plane distribution of the thin film transistor array can be canceled because the characteristics of the adjacent thin film transistors are similar. Further, since the temperatures of the adjacent thin film transistors are the same, most of the temperature dependence of the thin film transistors can be canceled.
  • the first switching circuit 101 is located upstream of the load resistance 20 and the voltage detection amplifier 53, and the first switching circuit 101 is located upstream of the load resistance 21 and the voltage detection amplifier 54.
  • the switching circuit 103 of 3 the number of load resistors 20 and 21 and the voltage detection amplifiers 53 and 54 can be reduced, and further, a second switching circuit 102 is provided on the downstream side of the differential amplifier circuit 24. Therefore, the number of AD converters 25 can be reduced, and the scale of the signal detection circuit can be reduced. Further, by applying the signal detection circuit, the scale of the drive detection circuit can be reduced.
  • the switched and unmeasured signal differences of other blocks are measured before the signal difference is measured.
  • the measurement can be performed after the switching signal becomes stable, and a signal detection method with a small error can be provided.
  • Patent Document 2 In the conventional sensor array, there is a problem that the pressure-sensitive medium whose resistance changes tends to deteriorate. Therefore, it has been studied to use a pressure-sensitive medium of a type in which the potential difference changes as in Patent Document 2 (FIG. 28). However, there is a problem that a circuit having a load resistance in a pixel and reading a potential as in Patent Document 2 is vulnerable to noise. Further, since the first thin film transistor 41 is used as the grounded-source circuit, there is a problem that it is easily affected by the mobility of the thin film transistor and the variation of the threshold value. Further, the pressure-sensitive medium of Patent Document 2 is an inorganic substance, and has a problem of being vulnerable to mechanical impact.
  • the pressure-sensitive medium 130 which is a sensor unit, is of a type in which the resistance changes depending on the pressure, and one end is connected to the common electrode and the other end is connected to the drain electrode of the thin film transistor 31.
  • a power supply is connected to the common electrode.
  • a gate voltage (on voltage) that turns on the thin film transistor 31 is applied to one of the scanning wires 32, and a gate voltage (off voltage) that turns off the thin film transistor 31 is applied to the other scanning wires 32.
  • a current flowing through the pressure-sensitive medium 130 of the corresponding pixel flows through the signal wiring 33 through the thin film transistor 31 belonging to the scanning wiring 32 to which the on-voltage is applied.
  • FIG. 28 shows another example of the conventional pixel circuit.
  • the pressure-sensitive medium 140 which is a sensor unit, is of a type in which the potential difference changes depending on the pressure.
  • One end of the pressure sensitive medium 140 is connected to the gate electrode of the first thin film transistor 41, the other end is connected to the source electrode of the first thin film transistor 41, and the first thin film transistor 41 is connected to the power supply via the drain resistance 43 in the pixel.
  • the first thin film transistor 41 is a source grounded circuit.
  • a gate voltage (on voltage) that turns on the second thin film transistor 42 is applied to one of the scanning wires 44, and a gate voltage (off voltage) that turns off the second thin film transistor 42 is applied to the other scanning wires 44. Apply.
  • the drain voltage of the corresponding pixel is drawn out to the signal wiring 45 through the second thin film transistor 42 belonging to the scanning wiring 44 to which the on-voltage is applied.
  • the scanning wiring 44 By sequentially changing the scanning wiring 44 to be turned on one by one, the pressure data of all lines can be read out.
  • the circuit that reads out the voltage has a high input impedance, if the signal wiring 45 is long, noise is likely to be mixed in the signal. Further, if the impedance of the detection circuit is lowered so that noise is less likely to be mixed in this circuit, the drain resistor 43 flows through the detection circuit (not necessarily) in addition to the current flowing through the first thin film 41 (depending on the pressure). A current (which does not depend on the pressure) flows, and the voltage drop of the drain resistor 43 due to the current flowing through the detection circuit becomes an error. Further, since the source grounded circuit amplifies both the voltage and the current, the sensitivity is high, but the signal voltage is easily affected by the mobility and the variation of the threshold value of the first thin film transistor 41.
  • the pixel circuit of the third embodiment of the present disclosure is shown in FIG.
  • the sensor unit 109 (for example, the pressure sensitive medium 9) is of a type in which the potential difference changes depending on a stimulus (pressure or the like).
  • One end of the sensor unit 109 is connected to the common electrode 10, the other end is connected to the gate electrode G1 of the first thin film transistor, and the drain electrode D1 of the first thin film transistor is connected to the power supply Vdd via the drain wiring 14, and the first
  • the source electrode S1 of the thin film transistor is connected to the drain electrode D2 of the second thin film transistor, the gate electrode G2 of the second thin film transistor is connected to the scanning wiring 12, and the source electrode S2 of the second thin film transistor is connected to the signal wiring 15.
  • the first thin film transistor is a drain ground circuit (source follower).
  • a gate voltage (on voltage) that turns on the second thin film transistor is applied to one of the scanning wires 12, and a gate voltage (off voltage) that turns off the second thin film transistor is applied to the other scanning wires 12. ..
  • the source electrode S1 of the corresponding pixel is connected to the signal wiring 15 and connected to the load resistance 20 in the signal detection circuit through the second thin film transistor belonging to the scanning wiring 12 to which the on-voltage is applied. That is, since the load resistor 20 is outside the array, a current flows through the signal wiring 15, so that the impedance is low and noise is unlikely to be mixed into the signal.
  • the pressure data of each line can be read out by sequentially changing the scanning wiring 12 to be turned on one by one.
  • the operating point is determined by the potential of the common electrode 10. Can be adjusted.
  • the signal detection circuit, the drive detection circuit, and the signal detection method according to the first embodiment can be preferably used.
  • the number of scanning wires 12 of the sensor array is N
  • the number of signal wires 15 is M.
  • the pressure sensitive medium 9 (type in which the potential difference changes) is suitable. However, it is also possible to use another pressure-sensitive medium, a displacement-sensitive medium, a temperature-sensitive medium, or the like as the sensor unit 109.
  • the maximum potential change amount is the amount of change in the pixel electrode potential from the state in which no stimulus (pressure, etc.) is applied to the sensor to the time when the stimulus of the maximum value in the detection range set in the sensor is applied. be.
  • the maximum potential change amount is 4 [V]
  • FIG. 11 A specific example of the sensor array shown in FIG. 11 is shown in FIG. It has gate electrodes G1 and G2 on the insulating substrate 1 (G2 is connected to the scanning wiring 12), has a gate insulating film 3 on it, has semiconductors SC1 and SC2 on it, and has semiconductors SC1 and SC2 on it. It has source electrodes S1 and S2 and drain electrodes D1 and D2 (S1 is connected to D2 via a connection wire 17, D1 is connected to a drain wire 14, and S2 is connected to a signal wire 15), on which the source electrodes S1 and S2 are provided.
  • the pixel electrode 8 has an interlayer insulating film 7 and a pixel electrode 8 on the interlayer insulating film 7 (the pixel electrode 8 has a gate electrode G1 via via wires 18U and 18L provided in the opening of the interlayer insulating film 7 and the opening of the gate insulating film 3). It is connected to the. Further, it has a sensor unit 109 and a common electrode 10. The sensor unit 109 is in contact with or bonded to the pixel electrode 8.
  • An insulating etching stopper layer may be provided on the semiconductors SC1 and SC2, and semiconductors are provided at the interface between the semiconductors SC1 and SC2 and the source electrodes S1 and S2 and at the interface between the semiconductors SC1 and SC2 and the drain electrodes D1 and D2. It may have a contact layer having a resistance lower than 4.
  • the pixel electrode 8 when the pixel electrode 8 is thick, there may be a gap in the portion where the pixel electrode 8 is not provided, or it may be filled with an insulating material.
  • the pixel electrode 8 is also the back gate electrode of the first thin film transistor.
  • the operation becomes more stable than when the pixel electrode 8 is simply connected to the gate electrode G1 without covering the channel portion of the first thin film transistor.
  • a back gate electrode may be provided in the second thin film transistor, and a common electrode potential, a GND potential, or a specific constant potential may be connected thereto. As a result, the operation of the second thin film transistor becomes stable.
  • the insulating substrate 1 may be glass, but organic substances (for example, PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PES (polyether sulfone), PI (polyimide), PC (polycarbonate), etc.) are suitable.
  • organic substances for example, PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PES (polyether sulfone), PI (polyimide), PC (polycarbonate), etc.
  • metals for example, Al, Ti, Mo, Ta, etc. or alloys containing these as main components
  • the gate insulating film 3 is preferably an organic substance (acrylic, epoxy, etc.) or an inorganic substance (SiO 2 , SiN, etc.) or a laminate or mixture thereof.
  • the semiconductors SC1 and SC2 are preferably organic semiconductors, oxide semiconductors, and amorphous Si.
  • the source electrodes S1 and S2 and the drain electrodes D1 and D2 are preferably made of metal (for example, Al, Ti, Mo, Ta or the like or an alloy containing these as main components).
  • the interlayer insulating film 7 is preferably an organic substance (acrylic, epoxy, etc.) or an inorganic substance (SiO 2 , SiN, etc.) or a laminate or mixture thereof.
  • the pixel electrode 8 is preferably made of a metal (for example, Al, Ti, Mo, Ta or the like or an alloy containing these as a main component) or a mixture of metal particles and a resin (Ag paste or the like).
  • a pressure-sensitive medium 9 particularly an organic piezoelectric material (polyvinylidene fluoride, polyvinylidene fluoride / ethylene trifluoride copolymer, polylactic acid, porous electret type, etc.) is suitable, but it is a displacement-sensitive medium. Or a temperature sensitive medium.
  • the common electrode 10 is preferably a metal (for example, Al, Ti, Mo, Ta, etc. or an alloy containing these as a main component).
  • the main components of the insulating substrate 1, the gate insulating film 3, the interlayer insulating film 7, and the sensor unit 109 are organic substances. Is particularly desirable.
  • the pixel electrode 8 is made of metal, it is easy to make the pixel electrode 8 thin, and it is possible to eliminate the gap between the interlayer insulating film 7 and the sensor unit 109 (pressure sensitive medium 9 or the like) other than the pixel electrode 8. It can improve the uniformity of measurement. If the pixel electrode 8 is a mixture of metal particles and resin, it is easy to thicken the pixel electrode 8, and a gap between the interlayer insulating film 7 and the sensor portion 109 (pressure sensitive medium 9 or the like) other than the pixel electrode 8 can be formed. It can be increased and a predetermined pressure can be obtained with a smaller force, that is, the sensitivity can be increased.
  • FIG. 12 shows the case of bottom gate and top contact, but the present disclosure is not limited to this, and top gate and bottom contact may be used.
  • FIG. 13 The pixel circuit of the fourth embodiment of the present disclosure is shown in FIG.
  • a third thin film transistor is further provided in the pixel circuit of FIG. 11, the drain electrode D3 of the third thin film transistor is connected to the pixel electrode 8, the source electrode S3 is connected to the common wiring 11, and the gate electrode G3 is It is connected to the reset wiring 13.
  • a voltage (on voltage) for turning on the third thin film transistor is applied to the reset wiring 13 in a state where no stimulus (pressure or the like) is applied to the sensor unit 109. Then, the pixel electrode 8 is connected to the common wiring 11 via the third thin film transistor, and the electric charge accumulated in the pixel electrode 8 can be reduced to zero.
  • the common wiring 11 has the same potential as the common electrode 10. Then, a voltage (off voltage) for turning off the third thin film transistor is applied to the reset wiring 13, and a voltage Vdd is applied to the drain wiring 14.
  • the sensor unit 109 which changes the potential difference depending on the pressure like a piezoelectric element, has a potential difference of 0 when the stimulus (pressure, etc.) is 0 in a steady state, but depending on the past history, for example, the stimulus (pressure) until just before use. Etc.), an error due to the residual charge of the sensor unit 109 occurs, such that the potential difference is not 0 even if the stimulus (pressure or the like) is 0.
  • the charge of the pixel electrode 8 can be reset by turning on the third thin film transistor immediately before the measurement, it is possible to eliminate the error caused by the residual charge of the sensor unit 109.
  • the gate-drain electrode capacitance of the first thin film transistor (including the pixel electrode 8 connected to the gate electrode G1 and the drain wiring 14 connected to the drain electrode D1) is Cgd1
  • the gate-drain capacitance of the third thin film transistor (including the gate-drain capacitance).
  • the reset wiring 13 connected to the gate electrode G3 and the capacitance of the pixel electrode 8 connected to the drain electrode D3 are set to Cgd3, and the capacitance between the pixel electrode 8 and the common electrode 10 is set to Cp. do.
  • the former In the case of an n-channel TFT, the former is negative and the latter is positive, and in the case of a p-channel TFT, the former is positive and the latter is negative, and in each case, there is an effect of canceling each other's voltage changes. Further, this voltage change needs to be sufficiently smaller than the maximum potential change amount of the pressure sensitive medium 9, and needs to be suppressed within 10% of the maximum potential change amount, for example.
  • the maximum potential change amount is the pixel electrode potential change amount when the pressure of the maximum value in the pressure detection range set in the pressure sensor is applied from the state where the pressure is not applied to the pressure sensor. ..
  • Vdd ⁇ Cgd1 / (Cgd1 + Cp + Cgd3)- ⁇ Vreset (on) -Vreset (off) ⁇ ⁇ Cgd3 / (Cgd3 + Cp + Cgd1)
  • the measurement method is the same as that of the third embodiment, and the sensor array detection method in the third embodiment preferably includes, for example, the signal detection circuit, the drive detection circuit, and the signal detection method according to the first embodiment. Can be used for.
  • FIG. 13 A specific example of FIG. 13 is shown in FIG. It has gate electrodes G1, G2, and G3 on the insulating substrate 1 (G2 is connected to the scanning wiring 12 and G3 is connected to the reset wiring 13), has a gate insulating film 3 on it, and has a gate insulating film 3 on it. It has semiconductors SC1, SC2, SC3, and has source electrodes S1, S2, S3 and drain electrodes D1, D2, D3 on it (S1 is connected to D2 via a connection wiring 17, and D3 is a gate insulating film. It is connected to the gate electrode G1 via the via wiring 18L provided in the opening of 3, D1 is connected to the drain wiring 14, S2 is connected to the signal wiring 15, S3 is connected to the common wiring 11), and above.
  • the pixel electrode 8 has an interlayer insulating film 7 and a pixel electrode 8 on the interlayer insulating film 7 (the pixel electrode 8 is connected to the drain electrode D3 via a via wiring 18U provided in the opening of the interlayer insulating film 7). Further, it has a sensor unit 109 (for example, a pressure sensitive medium 9) and a common electrode 10. The sensor unit 109 is in contact with or bonded to the pixel electrode 8.
  • An insulating etching stopper layer may be provided on the semiconductors SC1, SC2, and SC3, the interface between the semiconductors SC1, SC2, and SC3 and the source electrodes S1, S2, and S3, and the semiconductors SC1, SC2, SC3 and the drain electrode.
  • a contact layer having a lower resistance than the semiconductors SC1, SC2, and SC3 may be provided at the interface between D1, D2, and D3.
  • the pixel electrode 8 when the pixel electrode 8 is thick, there may be a gap in the portion where the pixel electrode 8 is not provided, or it may be filled with an insulating material.
  • the pixel electrode 8 is also the back gate electrode of the first thin film transistor.
  • the operation becomes more stable than when the pixel electrode 8 is simply connected to the gate electrode G1 without covering the channel portion of the first thin film transistor.
  • a back gate electrode may be provided in the second thin film transistor, and a common electrode potential, a GND potential, or a specific constant potential may be connected thereto.
  • a back gate electrode may be provided on the third thin film transistor, and a pixel electrode potential, a common electrode potential, a GND potential, or a specific constant potential may be connected thereto. As a result, the operation of the third thin film transistor becomes stable.
  • each component is the same as that of the third embodiment.
  • FIG. 14 shows the case of bottom gate and top contact, but the present disclosure is not limited to this, and top gate and bottom contact may be used.
  • the pixel circuit of the fifth embodiment of the present disclosure is shown in FIG.
  • the sensor unit 109 (for example, the pressure sensitive medium 9) is of a type in which the potential difference changes depending on a stimulus (pressure or the like).
  • One end of the sensor unit 109 is connected to the common electrode 10, the other end is connected to the gate electrode G1 of the first thin film transistor, and the drain electrode D1 of the first thin film transistor is connected to the power supply Vdd via the drain wiring 14, and the first
  • the source electrode S1 of the thin film transistor is connected to the drain electrode D2 of the second thin film transistor, the gate electrode G2 of the second thin film transistor is connected to the scanning wiring 12, and the source electrode S2 of the second thin film transistor is connected to the signal wiring 15.
  • the first thin film transistor is a drain ground circuit (source follower). Since the load resistor 20 is outside the array, a current flows through the signal wiring 15, so the impedance is low and noise is less likely to be mixed. Further, since it is a drain ground (source follower) circuit, only the current is amplified and the voltage is almost unchanged, so that it is not easily affected by the mobility and the variation of the threshold value of the first thin film transistor.
  • the common wiring 11 is connected to the gate electrode G4 of the fourth thin film transistor, the drain electrode D4 of the fourth thin film transistor is connected to the power supply Vdd via the drain wiring 14, and the source electrode S4 of the fourth thin film transistor is the fifth.
  • the thin film transistor drain electrode D5 of the thin film transistor, the gate electrode G5 of the fifth thin film transistor is connected to the scanning wiring 12, the source electrode S5 of the fifth thin film transistor is connected to the reference signal wiring 16, and the load resistance in the signal detection circuit.
  • the fourth thin film transistor is a drain ground circuit (source follower).
  • the mobility variation and the threshold value change of the first thin film transistor can be determined. It is possible to cancel by the mobility variation or the threshold value change of the fourth thin film transistor, and to cancel the mobility variation or the mobility change of the second thin film transistor by the mobility variation or the threshold value change of the fifth thin film transistor. .. This is because the variation and characteristic change are greatly affected by the in-plane distribution, and therefore the variation and characteristic change of the thin film transistors formed in the same pixel are similar.
  • the shape of the first thin film transistor (channel width and channel length) and the shape of the fourth thin film transistor (channel width and channel length) are made equal, and the shape of the second thin film transistor (channel width and channel length) and the fifth thin film transistor are made equal to each other.
  • the shapes of the thin film transistors (channel width and channel length) should be equal.
  • the signal detection circuit, the drive detection circuit, and the signal detection method according to the second embodiment can be preferably used.
  • the number of scanning wires 12 of the sensor array is N
  • the number of signal wires 15 is M.
  • the pressure sensitive medium 9 (type in which the potential difference changes) is suitable. However, it is also possible to use another pressure-sensitive medium, a displacement-sensitive medium, a temperature-sensitive medium, or the like as the sensor unit 109.
  • the potential deviation of the pixel electrode 8 may be set to
  • FIG. 15 A specific example of FIG. 15 is shown in FIG. It has gate electrodes G1, G2, G4, and G5 on the insulating substrate 1 (G2 and G5 are connected to the scanning wiring 12), has a gate insulating film 3 on it, and semiconductors SC1, SC2, on the gate insulating film 3. It has SC4 and SC5, and has source electrodes S1, S2, S4, S5 and drain electrodes D1, D2, D4, D5 on it (S1 is connected to D2 via a connection wiring 17, and S4 is a connection wiring. It is connected to D5 via 17, D1 and D4 are connected to the drain wiring 14, S2 is connected to the signal wiring 15, S5 is connected to the reference signal wiring 16), and has an interlayer insulating film 7 on it.
  • a pixel electrode 8 and a common wiring 11 are provided on the pixel electrode 8 (the pixel electrode 8 is connected to the gate electrode G1 via via wires 18U and 18L provided in the opening of the interlayer insulating film 7 and the opening of the gate insulating film 3).
  • the common wiring 11 is connected to the gate electrode G4 via via wirings 18U and 18L provided in the opening of the interlayer insulating film 7 and the opening of the gate insulating film 3).
  • it has a sensor unit 109 (for example, a pressure sensitive medium 9) and a common electrode 10. The sensor unit 109 is in contact with or bonded to the pixel electrode 8.
  • An insulating etching stopper layer may be provided on the semiconductors SC1, SC2, SC4, and SC5, or the interface between the semiconductors SC1, SC2, SC4, SC5 and the source electrodes S1, S2, S4, S5 and the semiconductor SC1,
  • a contact layer having a lower resistance than the semiconductors SC1, SC2, SC4, and SC5 may be provided at the interface between the SC2, SC4, and SC5 and the drain electrodes D1, D2, D4, and D5.
  • the pixel electrode 8 when the pixel electrode 8 is thick, there may be a gap in the portion where the pixel electrode 8 is not provided, or it may be filled with an insulating material.
  • the common wiring 11 may or may not be in contact with the sensor unit 109.
  • the pixel electrode 8 is the back gate electrode of the first thin film transistor, and the common wiring 11 is the back gate electrode of the fourth thin film transistor.
  • the pixel electrode 8 is only connected to the gate electrode G1 without covering the channel portion of the first thin film transistor, or the common wiring 11 is connected to the gate electrode G4 without covering the channel portion of the fourth thin film transistor.
  • the operation is more stable than when it is just connected.
  • a back gate electrode may be provided in the second thin film transistor, and a pixel electrode potential, a common electrode potential, a GND potential, or a specific constant potential may be connected thereto.
  • a back gate electrode may be provided on the fifth thin film transistor, and a common electrode potential, a GND potential, or a specific constant potential may be connected thereto. As a result, the operation of the fifth thin film transistor becomes stable.
  • each component is the same as that of the third embodiment.
  • FIG. 16 shows the case of bottom gate and top contact, but the present disclosure is not limited to this, and top gate and bottom contact may be used.
  • FIG. 17 The pixel circuit of the sixth embodiment of the present disclosure is shown in FIG. In FIG. 17, a third thin film transistor is further provided in the pixel circuit of FIG. 15, the drain electrode D3 of the third thin film transistor is connected to the pixel electrode 8, the source electrode S3 is connected to the common wiring 11, and the gate electrode G3 is It is connected to the reset wiring 13.
  • a voltage (on voltage) for turning on the third thin film is applied to the reset wiring 13 in a state where no stimulus (pressure or the like) is applied to the sensor unit 109. Then, the pixel electrode 8 is connected to the common wiring 11 via the third thin film transistor, and the electric charge accumulated in the pixel electrode 8 can be reduced to zero. Then, a voltage (off voltage) for turning off the third thin film transistor is applied to the reset wiring 13, and a power supply Vdd is applied to the drain wiring 14.
  • the measurement method is the same as that of the fifth embodiment, and the sensor array detection method in the sixth embodiment preferably includes, for example, the signal detection circuit, the drive detection circuit, and the signal detection method according to the second embodiment. Can be used for.
  • FIG. 17 A specific example of FIG. 17 is shown in FIG.
  • the gate electrodes G1, G2, G3, G4, and G5 are provided on the insulating substrate 1 (G2 and G5 are connected to the scanning wiring 12 and G3 is connected to the reset wiring 13), and the gate insulating film 3 is placed on the gate electrodes G1 and G2, G3, G4, and G5.
  • It has semiconductors SC1, SC2, SC3, SC4, SC5 on it, and has source electrodes S1, S2, S3, S4, S5 and drain electrodes D1, D2, D3, D4, D5 on it ( S1 is connected to D2 via the connecting wiring 17, D3 is connected to the gate electrode G1 via the via wiring 18L provided in the opening of the gate insulating film 3, and S4 is connected to D5 via the connecting wiring 17.
  • D1 and D4 are connected to the drain wiring 14
  • S2 is connected to the signal wiring
  • S5 is connected to the reference signal wiring 16
  • S3 is connected to the common wiring 11
  • the interlayer insulating film 7 is provided therein.
  • a pixel electrode 8 and a common wiring 11 are provided on the pixel electrode 8 (the pixel electrode 8 is connected to the drain electrode D3 via a via wiring 18U provided in the opening of the interlayer insulating film 7, and the common wiring 11 is an interlayer insulating film. It is connected to the gate electrode G4 via via wires 18U and 18L provided in the openings of the gate 7 and the gate insulating film 3.).
  • it has a sensor unit 109 (for example, a pressure sensitive medium 9) and a common electrode 10. The sensor unit 109 is in contact with or bonded to the pixel electrode 8.
  • An insulating etching stopper layer may be provided on the semiconductors SC1, SC2, SC3, SC4, and SC5, or the semiconductors SC1, SC2, SC3, SC4, SC5 and the source electrodes S1, S2, S3, S4, and S5. And the interface between the semiconductors SC1, SC2, SC3, SC4, SC5 and the drain electrodes D1, D2, D3, D4, D5 have a contact layer with lower resistance than the semiconductors SC1, SC2, SC3, SC4, SC5. May be good.
  • the pixel electrode 8 when the pixel electrode 8 is thick, there may be a gap in the portion where the pixel electrode 8 is not provided, or it may be filled with an insulating material.
  • the common wiring 11 may or may not be in contact with the sensor unit 109.
  • each component is the same as that of the third embodiment.
  • the pixel electrode 8 is the back gate electrode of the first thin film transistor, and the common wiring 11 is the back gate electrode of the fourth thin film transistor.
  • the pixel electrode 8 is only connected to the gate electrode G1 without covering the channel portion of the first thin film transistor, or the common wiring 11 is connected to the gate electrode G4 without covering the channel portion of the fourth thin film transistor.
  • the operation is more stable than when it is just connected.
  • a back gate electrode may be provided in the second thin film transistor, and a pixel electrode potential, a common electrode potential, a GND potential, or a specific constant potential may be connected thereto. As a result, the operation of the second thin film transistor becomes stable.
  • a back gate electrode may be provided on the third thin film transistor, and a pixel electrode potential, a common electrode potential, a GND potential, or a specific constant potential may be connected thereto. As a result, the operation of the third thin film transistor becomes stable.
  • a back gate electrode may be provided on the fifth thin film transistor, and a common electrode potential, a GND potential, or a specific constant potential may be connected thereto. As a result, the operation of the fifth thin film transistor becomes stable.
  • FIG. 18 shows the case of bottom gate and top contact, but the present disclosure is not limited to this, and top gate and bottom contact may be used.
  • the signal voltage at the time of no stimulation is adjusted to somewhere between 0 and +2 [V]. Is good. Then, when an AD converter having a 0 to + 5 V input is used in signal detection, a detection range of 5 to 3 V can be used. When the sensor unit 109 is oriented so that the potential on the pixel electrode 8 side drops during + stimulation (pressurization, etc.), it is better to adjust the signal voltage without stimulation to somewhere between +3 and +5 [V]. .. Then, when using an AD converter with 0 to + 5V input, a detection range of 3 to 5V can be used.
  • the voltage Vbase to be added by the differential amplifier circuit 24 is somewhere between 0 and +2 [V]. It is better to adjust to. Then, when using an AD converter with 0 to + 5V input, a detection range of 5 to 3V can be used. When the sensor unit 109 is oriented so that the potential on the pixel electrode 8 side drops during + stimulation (pressurization, etc.), the voltage Vbase added by the differential amplifier circuit 24 is adjusted to somewhere between +3 and +5 [V]. It is better to do it. Then, when using an AD converter with 0 to + 5V input, a detection range of 3 to 5V can be used.
  • FIG. 19 is a block diagram showing an example of the nursing care data collection / determination system of the present disclosure.
  • the long-term care data collection / judgment system includes a long-term care sensor device and a data collection / judgment device.
  • the care sensor device is a signal detection circuit of the first or second embodiment to which a communication circuit is added, and includes a signal detection circuit, a communication circuit, a pressure-sensitive sensor array, a microcomputer, and a drive circuit.
  • the communication circuit of the care sensor device is a circuit that communicates data with an external circuit and is capable of wired communication and wireless communication, but wireless communication such as Bluetooth (registered trademark) and Wi-Fi (registered trademark) is particularly preferable. Yes, and it is preferable to connect to the Internet.
  • the data collection / judgment device has a communication circuit, a computer, and a database. (1) The data detected by the long-term care sensor device is stored in the database as it is or after being processed. At that time, the medical condition of the care recipient can also be saved together. (2) Using artificial intelligence, analyze big data in the database by machine learning or the like to clarify the relationship between posture and medical condition. (3) The data detected by the long-term care sensor device is compared with the data in the database to determine the medical condition. It is possible to perform three operations.
  • One data collection / judgment device may be connected to only one care sensor device, or one data collection / judgment device may be connected to a plurality of care sensor devices.
  • one data collection / judgment device may be connected to a plurality of care sensor devices.
  • data can be easily exchanged, but the response speed of the long-term care sensor device needs to be high.
  • the speed of the data collection / judgment device does not have to be very high.
  • data exchange becomes complicated, but the operating speed of each long-term care sensor device may be slow.
  • the speed of the data collection / judgment device needs to be high.
  • the computer and the database are in one data collection / judgment device in FIG. 19, the computer and the database may communicate with each other via a communication circuit.
  • FIG. 20 An example of the long-term care sensor device is shown in FIG.
  • the care sensor device 200 is described so as to be visible on the bed 201, but in reality, the sheets are placed on the bed 201 and the care recipient is asked to sleep on the sheets.
  • the nursing care sensor device 200 of FIGS. 20A and 20B has a large sheet-shaped sensor array 200A (for example, a pressure sensor array) on the bed.
  • 200G is a drive circuit
  • 200S is a signal detection circuit
  • 200C is a control / communication circuit.
  • the short side may be the driving side as shown in FIG. 20A, or the long side may be the driving side as shown in FIG. 20B.
  • the care sensor device 200 of FIG. 20C has a plurality of band-shaped sensor arrays 200A, connects all the short sides of the band-shaped sensor array 200A to the signal detection circuit 200S, and drives wiring next to each other on the long side of the band. By connecting with the inter-connection component 200WG, all the gate wirings are connected to one drive circuit 200G, and one control / communication circuit 200C is provided.
  • the care sensor device 200 of FIG. 20D has a plurality of small sheet-shaped sensor arrays 200A, and the signal wirings of the small sheet-shaped sensor arrays 200A are connected to each other by a signal wiring connection component 200WS to connect the signal detection circuit 200S.
  • the drive wirings of the small sheet-shaped sensor array 200A are connected to each other by the drive wiring connection component 200WG to be connected to one drive circuit 200G, and have one control / communication circuit 200C.
  • 20 (c) and 20 (d) replace the large sheet-shaped sensor array of FIG. 20 (a) with a plurality of strip-shaped sensor arrays or a plurality of small sheet-shaped sensor arrays.
  • the drive side and the signal side may be interchanged as shown in FIG. 20 (b). These operate as one care sensor device 200.
  • the nursing care sensor device 200 of FIG. 20 has a plurality of band-shaped sensor arrays 200A, connects the short side of the band-shaped sensor array 200A to the signal detection circuit 200S, and connects each band-shaped sensor to the plurality of drive circuits 200G.
  • the long sides of the array 200A are connected to each other, and a plurality of control / communication circuits 200C are provided.
  • the care sensor device 200 of FIG. 20F has a plurality of small sheet-shaped sensor arrays 200A, and the signal wirings of the small sheet-shaped sensor arrays 200A are connected to each other by a signal wiring connection component 200WS to form a strip-shaped set.
  • each band-shaped set is connected to the plurality of drive circuits 200G, and has a plurality of control / communication circuits 200C.
  • 20 (e) and 20 (f) operate as a plurality of care sensor devices 200.
  • the sensor array when the sensor array is applied to the determination of the posture, the determination is possible even if the stimulation values (pressure, etc.) of all the pixels are not accurately measured. Even if a problem occurs in the detection unit of one pixel and it becomes abnormal data, it can be determined by interpolating from the data of surrounding pixels. Further, even if a problem occurs in the detection unit of a plurality of pixels and the data becomes abnormal, it can be determined by interpolating from the data of the surrounding pixels. In this case, if the pixels in which the problem occurs are dispersed, it is easier to interpolate the data as compared with the case where the pixels are densely packed. However, even when it is dense, constant interpolation is possible.
  • the sensor array is not limited to the pressure sensor.
  • a displacement sensor or a temperature sensor can be used as a sensor array. That is, it can also be applied to a displacement sensor array and a temperature sensor array. Furthermore, it can be applied to a composite sensor array having both a temperature sensor and a pressure sensor, for example.
  • the drain wiring 14 With a current limiting circuit 40.
  • the power supply may be branched after passing through one current limiting circuit 40 and connected to all the drain wirings 14, but in that case, due to an abnormality at one place.
  • the voltage of all the drain wires 14 drops, and the entire sensor array shows an abnormal value. Therefore, as shown in FIG. 22B, it is desirable that the power supply is branched, each of the branches passes through the current limiting circuit 40, and then connected to the individual drain wiring 14.
  • each of the plurality of current limiting circuits 40 may be assigned a plurality of column wirings or row wirings. At that time, as shown in FIG. 22D, the column wiring or row wiring in charge of one current limiting circuit 40 is not adjacent to each other, and the column wiring or row wiring in charge of another current limiting circuit 40 is provided between them.
  • the current limiting circuit 40 is not limited to the circuit shown in FIG. 22A, and may be another type of current limiting circuit.
  • the long-term care data collection capable of estimating the health condition can be performed.
  • -A judgment system can be provided.
  • the signal detection circuit of FIG. 1 was manufactured.
  • the first switching circuit 101 is an analog multiplexer with 8 inputs and 1 output
  • the load resistance 20 is a metal film resistance of 1 M ⁇
  • the voltage detection amplifier 53 is a voltage follower using an operational amplifier
  • the second switching circuit 102 is an analog multiplexer with 8 inputs and 1 output.
  • the AD converter 25 has a 0 to + 5 V input and a 0 to 255 level (8 bit) output.
  • An oscillation prevention circuit was incorporated in the voltage detection amplifier 53, and an AD converter input protection circuit was provided on the output side of the voltage detection amplifier 53.
  • the first switching circuit 101 was controlled by using a microcomputer and a 3-bit counter, and the second switching circuit 102 and the AD converter 25 were also controlled by the same microcomputer to detect the signal of the pressure sensor array of 1 row and 64 columns.
  • the time constant of the response of the output of the first switching circuit 101, since (M 2 -1) ⁇ AD converter measurement time small compared to 1092Myuesu, the signal detection method of FIG. 5, signals from the stable high I was able to measure the accuracy.
  • Example 2 The microcomputer and the counter used in the first embodiment were added to the signal detection circuit of the first embodiment as the control circuit 5 and the counter 49, and the drive circuit 6 was further added to prepare the drive detection circuit of FIG.
  • the drive circuit outputs + 15V as the on voltage or -15V as the off voltage.
  • the signal of the pressure sensor array of 8 rows and 64 columns was detected by the signal detection method of FIG.
  • the time constant of the output response of the second switching circuit 102 is about 3 ⁇ s
  • the time constant of the output response of the first switching circuit 101. was about 500 ⁇ s.
  • Example 3 The signal detection circuit of FIG. 7 was manufactured.
  • Each set of analog multiplexers (8 inputs, 1 output x 2 sets) is used for the first switching circuit 101 and the third switching circuit 103, and the load resistors 20 and 21 are 1 M ⁇ metal film resistors, the voltage detection amplifier 53, and the like.
  • 54 is a non-inverting amplifier circuit using an operational amplifier
  • the differential amplifier circuit 24 is a circuit using an operational amplifier
  • the second switching circuit 102 is an analog multiplexer with 8 inputs and 1 output
  • the AD converter 25 is 0 to 255 levels (8 bits) with 0 to + 5 V inputs. It was used as an output.
  • An oscillation prevention circuit was incorporated in the voltage detection amplifiers 53 and 54, and an AD converter input protection circuit was provided on the output side of the voltage detection amplifiers 53 and 54.
  • the first switching circuit 101 and the third switching circuit 103 are controlled by using a microcomputer and a 3-bit counter, and the second switching circuit 102 and the AD converter 25 are also controlled by the same microcomputer.
  • a signal was detected.
  • the time constant of the response of the output of the first switching circuit 101, since (M 2 -1) ⁇ AD converter measurement time small compared to 1092Myuesu, the signal detection method of FIG. 9, signals from the stable high I was able to measure the accuracy.
  • Example 4 The microcomputer and the counter used in the third embodiment were added to the signal detection circuit of the third embodiment, and the drive circuit 6 was further added to prepare the drive detection circuit of FIG.
  • the drive circuit 6 outputs + 15V as an on voltage or -15V as an off voltage.
  • the signal of the pressure sensor array of 8 rows and 64 columns was detected by the signal detection method of FIG.
  • the time constant of the output response of the second switching circuit 102 is about 3 ⁇ s
  • the first switching circuit 101 and the third switching circuit 103 The time constant of the response of the output of was about 500 ⁇ s.
  • Example 5 The sensor array of FIG. 12 was manufactured. Using a PET film on a glass substrate as the insulating substrate 1, Mo was formed by film formation, resist film formation, pattern exposure, development, etching, and resist removal to form gate electrodes G1 and G2 and scanning wiring 12. Next, the photosensitive acrylic was formed into a film, exposed to a pattern, and developed to form a gate insulating film 3 with an opening. Further, the amorphous InGaZnO was formed by film formation, resist film formation, pattern exposure, development, etching, and resist removal to form semiconductor patterns SC1 and SC2. Then, a SiO 2 pattern was formed as an etching stopper layer on the portions of the semiconductor patterns SC1 and SC2 to be channels (not shown).
  • Mo is formed into a film, resist film, pattern exposure, development, etching, and resist removal to remove the source electrodes S1 and S2, the drain electrodes D1 and D2, the connection wiring 17 (between S1 and D2), the signal wiring 15, and the drain.
  • the wiring 14 and the via wiring 18L (lower half between the pixel electrode and G1) were formed.
  • the photosensitive acrylic was formed into a film, exposed to a pattern, and developed to form an interlayer insulating film 7 with an opening.
  • Mo was formed into a film, a resist film, pattern exposure, development, etching, and resist removal to form a pixel electrode 8 and a via wiring 18U (upper half between the pixel electrodes 8 and G1).
  • the pixel electrode 8 was connected to the gate electrode G1 by via wires 18U and 18L.
  • a pressure-sensitive medium (polyvinylidene fluoride triethylene ethylene copolymer, polarized) having Mo attached to the entire surface of one side is installed so that the pressure-sensitive medium side is in contact with the pixel electrode 8, and the sensor unit 109 ( The pressure-sensitive medium 9) and the common electrode 10 were used. Then, the glass substrate was peeled off from the PET film which is the insulating substrate 1. Since the pixel electrode 8 is thin, the sensor unit 109 (pressure sensitive medium 9) is in contact with the interlayer insulating film 7 in a portion other than the pixel electrode 8, and there is almost no gap.
  • a pressure-sensitive medium polyvinylidene fluoride triethylene ethylene copolymer, polarized
  • + 1V is applied to the common electrode 10
  • + 10V is applied to the drain wiring 14
  • an on voltage + 15V is applied to one of the scanning wirings 12, and an off voltage of -15V is applied to the other, and a pressure-dependent signal for one pixel is applied.
  • a pressure-dependent signal for one line was obtained.
  • the same operation was performed by changing the on-voltage position of the scanning wiring 12, and pressure-dependent signals of all pixels were obtained. From the pressure-dependent signal, the pressure of each pixel can be known.
  • the potential change of the pixel electrode 8 when Vdd is applied is 0.24 V and the maximum potential change amount of the pressure sensitive medium 9 (at a pressure of 800 kPa) is 4 V, the error due to the potential change of the pixel electrode 8 when Vdd is applied is It is sufficiently small, 6% of the maximum potential change amount.
  • Example 6 The sensor array of FIG. 14 was manufactured. Using a polyimide film on a glass substrate as the insulating substrate 1, Mo is formed, resist filmed, pattern exposed, developed, etched, and resist removed to form gate electrodes G1, G2, G3, scanning wiring 12, and reset wiring 13. Formed. Next, the photosensitive acrylic was formed into a film, exposed to a pattern, and developed to form a gate insulating film 3 with an opening. Further, the amorphous InGaZnO was formed by film formation, resist film formation, pattern exposure, development, etching, and resist removal to form semiconductor patterns SC1, SC2, and SC3. Then, a SiO 2 pattern was formed as an etching stopper layer on the portions of the semiconductor patterns SC1, SC2, and SC3 to be channels (not shown).
  • Mo is formed into a film, resist film, pattern exposure, development, etching, and resist removal to remove the source electrodes S1, S2, S3, drain electrodes D1, D2, D3, connection wiring 17 (between S1 and D2), and vias.
  • the wiring 18L (between D3-G1), the signal wiring 15, and the drain wiring 14 were formed.
  • the photosensitive acrylic was formed into a film, exposed to a pattern, and developed to form an interlayer insulating film 7 with an opening.
  • the Ag paste was screen-printed to form the pixel electrode 8 and the via wiring 18U (between the pixel electrodes 8 and D3).
  • the pixel electrode 8 was connected to the drain electrode D3 and the gate electrode G1 by the via wires 18U and 18L.
  • a pressure-sensitive medium having Mo on the entire surface of one side (polyvinylidene fluoride triethylene ethylene copolymer, polarization-treated) is installed so that the pressure-sensitive medium side is bonded to the pixel electrode 8, and the sensor unit 109 ( The pressure-sensitive medium 9) and the common electrode 10 were used. Further, the glass substrate was peeled off from the polyimide film which is the insulating substrate 1. Since the pixel electrode 8 is thick, the sensor unit 109 (pressure sensitive medium 9) is not in contact with the interlayer insulating film 7, and there is a gap in the portion where the pixel electrode 8 is not provided.
  • the gate-drain capacitance of the third thin film transistor (including the capacitance between the pixel electrode and the drain wiring).
  • Cgd3 0.69pF
  • an on-voltage + 15V was applied to the reset wiring 13 with + 1V to the common electrode 10 and 0V to the drain wiring 14.
  • the potential of the reset wiring 13 was set to an off voltage of -15V, and the potential of the drain wiring 14 was set to + 15V.
  • Example 7 The sensor array of FIG. 16 was manufactured. Using a PET film on a glass substrate as the insulating substrate 1, Mo was formed by film formation, resist film formation, pattern exposure, development, etching, and resist removal to form gate electrodes G1, G2, G4, G5, and scanning wiring 12. .. Next, the photosensitive acrylic was formed into a film, exposed to a pattern, and developed to form a gate insulating film 3 with an opening. Further, the amorphous InGaZnO was formed by film formation, resist film formation, pattern exposure, development, etching, and resist removal to form semiconductor patterns SC1, SC2, SC4, and SC5. Then, a SiO 2 pattern was formed as an etching stopper layer on the channel portions of the semiconductor patterns SC1, SC2, SC4, and SC5 (not shown).
  • connection wiring 17 (between S4-D5), signal wiring 15, reference signal wiring 16, drain wiring 14, common wiring 11, via wiring 18L (lower half between pixel electrodes 8 and G1), via wiring 18L (common) The lower half of the wiring 11-G4) was formed.
  • the photosensitive acrylic was formed into a film, exposed to a pattern, and developed to form an interlayer insulating film 7 with an opening.
  • the Ag paste is screen-printed to form the pixel electrode 8, the common wiring 11, the via wiring 18U (upper half between the pixel electrodes 8 and G1), and the via wiring 18U (the upper half between the common wiring 11 and G4). bottom.
  • the pixel electrode 8 was connected to the gate electrode G1, and the common wiring 11 was connected to the gate electrode G4.
  • a pressure-sensitive medium having Mo on the entire surface of one side (polyvinylidene fluoride triethylene ethylene copolymer, polarization-treated) is installed so that the pressure-sensitive medium side is bonded to the pixel electrode 8, and the sensor unit 109 ( The pressure-sensitive medium 9) and the common electrode 10 were used. Further, the glass substrate was peeled off from the PET film which is the insulating substrate 1.
  • + 1V is applied to the common electrode 10
  • + 10V is applied to the drain wiring 14
  • an on voltage + 15V is applied to one of the scanning wirings 12
  • an off voltage of -15V is applied to the other
  • a pressure-dependent signal for one pixel is applied.
  • a pressure-dependent signal for one line was obtained.
  • the same operation was performed by changing the on-voltage position of the scanning wiring 12, and pressure-dependent signals of all pixels were obtained. From the pressure-dependent signal, the pressure of each pixel can be known.
  • Example 8 The sensor array of FIG. 18 was manufactured. Using a polyimide film on a glass substrate as the insulating substrate 1, Mo is formed by film formation, resist film formation, pattern exposure, development, etching, and resist removal, and the gate electrodes G1, G2, G3, G4, G5, scanning wiring 12, The reset wiring 13 was formed. Next, the photosensitive acrylic was formed into a film, exposed to a pattern, and developed to form a gate insulating film 3 with an opening. Further, the amorphous InGaZnO was formed by film formation, resist film formation, pattern exposure, development, etching, and resist removal to form semiconductor patterns SC1, SC2, SC3, SC4, and SC5. Then, a SiO 2 pattern was formed as an etching stopper layer on the channel portions of the semiconductor patterns SC1, SC2, SC3, SC4, and SC5 (not shown).
  • Mo is formed into a film, resist is formed, pattern is exposed, developed, etched, and resist is removed, and the source electrodes S1, S2, S3, S4, S5, drain electrodes D1, D2, D3, D4, D5, and connection wiring 17 are formed. (Between S1-D2), via wiring 18L (between D3-G1), connection wiring 17 (between S4-D5), signal wiring 15, drain wiring 14, via wiring 18L (lower half of common wiring 11-G4 wiring) was formed.
  • the photosensitive acrylic was formed into a film, exposed to a pattern, and developed to form an interlayer insulating film 7 with an opening.
  • the Ag paste was screen-printed to form the pixel electrode 8, the via wiring 18U (between the pixel electrodes 8 and D1), the common wiring 11, and the via wiring 18U (the upper half between the common wiring 11 and G4).
  • the pixel electrode 8 was connected to the drain electrode D3 and the gate electrode G1, and the common wiring 11 was connected to the gate electrode G4.
  • a pressure-sensitive medium having Mo on the entire surface of one side (polyvinylidene fluoride triethylene ethylene copolymer, polarization-treated) is installed so that the pressure-sensitive medium side is bonded to the pixel electrode 8, and the sensor unit 109 ( The pressure-sensitive medium 9) and the common electrode 10 were used. Further, the glass substrate was peeled off from the polyimide film which is the insulating substrate 1.
  • the gate-drain capacitance of the third thin film transistor (including the capacitance between the pixel electrode and the drain wiring).
  • Cgd3 0.69pF
  • an on-voltage + 15V was applied to the reset wiring 13 with + 1V to the common electrode 10 and 0V to the drain wiring 14.
  • the potential of the reset wiring 13 was set to an off voltage of -15V, and the potential of the drain wiring 14 was set to + 15V.
  • the pixel electrode 8 when Vreset is off and Vdd is applied is 0.027V and the maximum potential change amount of the pressure sensitive medium 9 (at a pressure of 800 kPa) is 4V, the pixel electrode 8 when Vreset is off and Vdd is applied is 4V.
  • the error due to the potential change is 0.7% of the maximum potential change, which is sufficiently small.
  • the signal detection circuit of FIG. 30 was manufactured.
  • the switching circuit 100 uses eight analog multiplexers with 8 inputs and 1 output, the load resistance 122 is a metal film resistance of 1 M ⁇ , the voltage detection amplifier 123 is a voltage follower using an operational amplifier, and the AD converter 124 is 0 to 255 levels with 0 to + 5 V inputs ( 8 bits) Output.
  • a load resistor 122 and 64 voltage detection amplifiers 123 were used in this circuit. This circuit corresponds to a sensor array having 64 signal wires 15.
  • the switching circuit 100 was controlled by using a microcomputer, and the AD converter 124 was also controlled by the same microcomputer to detect the signal of the pressure sensor array of 1 row and 64 columns.
  • This disclosure can be used as a signal detection circuit or a drive detection circuit for various sensor arrays. Further, it can be used for various sensor arrays using a type of sensor unit in which the potential difference changes. Furthermore, it can be used for sensor systems including a health condition estimation system.
  • Analog switch 24 ... Differential amplification circuit 25 ... Analog-digital conversion circuit (AD converter) 31 ... Thin film transistor 32 ... Scanning wiring 33 ... Signal wiring 36 ... Power supply wiring 38 ... TFT 39 ... Pressure-sensitive medium (type in which resistance changes) 40 ... Current limiting circuit 41 ... First thin film transistor 42 ... Second thin film transistor 43 ... Drain resistance 44 ... Scanning wiring 45 ... Signal wiring 48 ... Control signal (digital wiring) 49 ... Counters 53, 54 ... Voltage detection amplifier 100 ... Switching circuit 101 ... First switching circuit 102 ... Second switching circuit 103 ... Third switching circuit 109 ... Sensor unit 115 ... Signal wiring 122 ... Load resistance 123 ...

Abstract

Provided is a smaller-scale signal detection circuit. Also provided is a drive/detection circuit constructed by including a drive circuit and a control circuit in the signal detection circuit, the drive/detection circuit having a smaller scale and making fewer errors. The signal detection circuit is for a sensor array that detects external stimuli to sensors corresponding to intersections of a matrix of scanning lines and signal lines. In the signal detection circuit, a group of M1 signal lines make up each of M2 blocks, and M2 blocks each house a first switching circuit having input terminals connected to M1 signal lines, and a load resistance and a voltage detection amplifier that are connected to an output terminal of the first switching circuit. The signal detection circuit includes a second switching circuit having input terminals connected respectively to output terminals of M2 blocks, and an AD converter connected to an output terminal of the second switching circuit.

Description

信号検出回路、駆動検出回路、センサアレイおよびセンサシステムSignal detection circuit, drive detection circuit, sensor array and sensor system
 本開示は、信号検出回路、駆動検出回路、センサアレイおよびセンサシステムに関する。 The present disclosure relates to signal detection circuits, drive detection circuits, sensor arrays and sensor systems.
 近年、人々の健康への関心が高まり、ヘルスケア分野の進展が見込まれている。それに伴い、センサをアレイ状に配置して、圧力、温度等の外部刺激値の情報を2次元的に得ることが、人の体勢、動き、異常等を把握するために重要になっている。例えば、薄膜トランジスタアレイと感圧媒体を組み合わせた圧力センサアレイを用いて、面内の圧力分布を検出できる。感圧媒体としては、圧力によって抵抗が変化するものや(特許文献1)、圧力によって電位差が変化するものがある(特許文献2)。あるいは、薄膜トランジスタアレイと感温媒体を組み合わせた温度センサアレイを用いて、面内の温度分布を検出できる。 In recent years, people's interest in health has increased, and progress in the healthcare field is expected. Along with this, it is important to arrange the sensors in an array to obtain information on external stimulus values such as pressure and temperature in two dimensions in order to grasp a person's posture, movement, abnormality, and the like. For example, an in-plane pressure distribution can be detected by using a pressure sensor array that combines a thin film transistor array and a pressure sensitive medium. As the pressure-sensitive medium, there are those whose resistance changes depending on the pressure (Patent Document 1) and those whose potential difference changes depending on the pressure (Patent Document 2). Alternatively, an in-plane temperature distribution can be detected by using a temperature sensor array that combines a thin film transistor array and a temperature sensitive medium.
 センサアレイは通常、複数の走査配線と複数の信号配線の交点に対応する検知点(ここでは「画素」と呼ぶ)を有し、信号配線数が大きくなると、センサアレイからの信号を検出する回路も規模が大きくなる。最も容易に考えられる信号検出回路は、図29のように信号配線115の数と同数の負荷抵抗122と電圧検出アンプ123およびADコンバータ124を設けるものであるが、大きな面積とコストが必要である。 A sensor array usually has detection points (referred to as "pixels") corresponding to intersections of a plurality of scanning wires and a plurality of signal wires, and a circuit that detects a signal from the sensor array when the number of signal wires increases. Will also grow in scale. The most easily conceivable signal detection circuit is to provide the same number of load resistors 122, voltage detection amplifier 123, and AD converter 124 as the number of signal wiring 115 as shown in FIG. 29, but requires a large area and cost. ..
 そこで、信号検出回路の規模を小さくする方法として、図30のように、切替回路100を適用することによって下流側の回路の数を減らすことが提案されている。当該信号検出回路は、複数の信号配線115の出力を、電圧検出アンプ123を通した後で1個の切替回路100に入力し、1個の切替回路100の出力を1個のADコンバータ124に入力している。例えば、特許文献3に記載の回路は、複数の電極からの出力を、オペアンプを通した後で1個のマルチプレクサに入力し、当該1個のマルチプレクサの出力を1個のA/D変換器に入力している。また、図30のような信号検出回路を含む駆動回路の例を図31に示す。図31の駆動検出回路は、図30の信号検出回路に、制御回路125と、駆動回路126を加えたものであり、走査配線127にオン電圧を印加することで、センサ点の信号を検出する。特許文献4では、多数の信号配線出力を、電圧検出アンプを通した後で少数の切替回路に入力し、切替回路と同数のADコンバータに入力している。これらによれば、電圧検出アンプおよび負荷抵抗の数は減らないが、ADコンバータの数を減らすことができる。 Therefore, as a method of reducing the scale of the signal detection circuit, it has been proposed to reduce the number of circuits on the downstream side by applying the switching circuit 100 as shown in FIG. The signal detection circuit inputs the outputs of the plurality of signal wirings 115 to one switching circuit 100 after passing through the voltage detection amplifier 123, and outputs the output of one switching circuit 100 to one AD converter 124. I'm typing. For example, in the circuit described in Patent Document 3, the outputs from a plurality of electrodes are input to one multiplexer after passing through an operational amplifier, and the output of the one multiplexer is input to one A / D converter. You are typing. Further, an example of a drive circuit including a signal detection circuit as shown in FIG. 30 is shown in FIG. The drive detection circuit of FIG. 31 is obtained by adding a control circuit 125 and a drive circuit 126 to the signal detection circuit of FIG. 30, and detects a signal at a sensor point by applying an on-voltage to the scanning wiring 127. .. In Patent Document 4, a large number of signal wiring outputs are input to a small number of switching circuits after passing through a voltage detection amplifier, and are input to the same number of AD converters as the switching circuits. According to these, the number of voltage detection amplifiers and load resistors is not reduced, but the number of AD converters can be reduced.
特開2014-119375号公報Japanese Unexamined Patent Publication No. 2014-119375 特許第2943437号公報Japanese Patent No. 2943437 特許第4160251号公報Japanese Patent No. 4160251 特許第3667058号公報Japanese Patent No. 3667058
 しかしながら、これらの回路では、切替回路の下流側にあるADコンバータの数を減らせるものの、切替回路の上流側にある電圧検出アンプおよび負荷抵抗を信号配線と同数だけ用意しなければならず、信号検出回路全体の規模をあまり小さくできないという問題があった。 However, in these circuits, although the number of AD converters on the downstream side of the switching circuit can be reduced, the same number of voltage detection amplifiers and load resistors on the upstream side of the switching circuit must be prepared as the number of signal wirings. There was a problem that the scale of the entire detection circuit could not be reduced very much.
 本開示は、係る従来技術の状況に鑑みてなされたもので、規模の小さい信号検出回路を提供することを課題とする。また、信号検出回路に駆動回路および制御回路を含めた駆動検出回路の時、規模が小さく、誤差の少ない駆動検出回路を提供することを課題とする。 The present disclosure has been made in view of the situation of the prior art, and an object of the present invention is to provide a signal detection circuit having a small scale. Another object of the present invention is to provide a drive detection circuit having a small scale and a small error when the drive detection circuit includes a drive circuit and a control circuit in the signal detection circuit.
 上記課題を解決するための、本開示の一局面は、複数の走査配線と、複数の信号配線と、のマトリクスの交点に対応したセンサ部の外部刺激を検出するセンサアレイ用の、信号検出回路であって、複数の信号配線がM本ずつM個のブロックに分けられており、M個のブロックのそれぞれの中には、M本の前記信号配線が入力に接続された第1の切替回路と、前記第1の切替回路の出力に接続された負荷抵抗および電圧検出アンプと、が設けられ、M個の前記ブロックからのそれぞれの出力が入力に接続された第2の切替回路と、第2の切替回路の出力に接続されたADコンバータと、を有する信号検出回路である。 One aspect of the present disclosure for solving the above problems is a signal detection circuit for a sensor array that detects an external stimulus of a sensor unit corresponding to an intersection of a matrix of a plurality of scanning wirings and a plurality of signal wirings. a is a plurality of signal lines are divided into M 2 blocks one by one M, in each of the M 2 blocks are first the signal lines of one M is connected to the input A second switching circuit is provided, and a load resistance and voltage detection amplifier connected to the output of the first switching circuit are provided, and each output from the M 2 blocks is connected to an input. It is a signal detection circuit having a switching circuit and an AD converter connected to the output of the second switching circuit.
 また、本開示の他の局面は、複数の信号配線と、信号配線と交差する複数の走査配線と、信号配線と走査配線の交点のそれぞれに対応して設けられ、画素電極と第1薄膜トランジスタと第2薄膜トランジスタを含む複数の画素部と、第1薄膜トランジスタのドレイン電極に給電するためのドレイン配線と、画素電極に接続されるセンサ部と、センサ部に接続される共通電極とを備え、画素電極は第1薄膜トランジスタのゲート電極に接続され、第1薄膜トランジスタのドレイン電極はドレイン配線に接続され、第1薄膜トランジスタのソース電極は第2薄膜トランジスタのドレイン電極に接続され、第2薄膜トランジスタのゲート電極は走査配線に接続され、第2薄膜トランジスタのソース電極は信号配線に接続されているセンサアレイである。 Further, another aspect of the present disclosure is provided corresponding to each of a plurality of signal wirings, a plurality of scanning wirings intersecting the signal wirings, and intersections of the signal wirings and the scanning wirings, and the pixel electrodes and the first thin film transistor. A pixel electrode including a plurality of pixel portions including a second thin film transistor, a drain wiring for supplying power to the drain electrode of the first thin film transistor, a sensor portion connected to the pixel electrode, and a common electrode connected to the sensor portion. Is connected to the gate electrode of the first thin film transistor, the drain electrode of the first thin film transistor is connected to the drain wiring, the source electrode of the first thin film transistor is connected to the drain electrode of the second thin film transistor, and the gate electrode of the second thin film transistor is the scanning wiring. The source electrode of the second thin film transistor is a sensor array connected to the signal wiring.
 また、本開示の他の局面は、センサシステムであって、センサアレイと、信号検出回路とを備え、センサアレイは、複数の信号配線と、信号配線と交差する複数の走査配線と、信号配線と走査配線の交点のそれぞれに対応して設けられ、画素電極と第1薄膜トランジスタと第2薄膜トランジスタを含む複数の画素部と、第1薄膜トランジスタのドレイン電極に給電するためのドレイン配線と、画素電極に接続されるセンサ部と、センサ部に接続される共通電極とを備え、画素電極は第1薄膜トランジスタのゲート電極に接続され、第1薄膜トランジスタのドレイン電極はドレイン配線に接続され、第1薄膜トランジスタのソース電極は第2薄膜トランジスタのドレイン電極に接続され、第2薄膜トランジスタのゲート電極は走査配線に接続され、第2薄膜トランジスタのソース電極は信号配線に接続されており、信号検出回路は、複数の信号配線がM1本ずつM2個のブロックに分けられており、M2個のブロックのそれぞれの中には、M1本の信号配線が入力に接続された第1の切替回路と、第1の切替回路の出力に接続された負荷抵抗および電圧検出アンプと、が設けられ、M2個のブロックからのそれぞれの出力が入力に接続された第2の切替回路と、第2の切替回路の出力に接続されたADコンバータとを有する、センサシステムである。 Another aspect of the present disclosure is a sensor system comprising a sensor array and a signal detection circuit, wherein the sensor array includes a plurality of signal wirings, a plurality of scanning wirings intersecting the signal wirings, and a signal wiring. A plurality of pixel portions including a pixel electrode, a first thin film, and a second thin film, a drain wiring for supplying power to the drain electrode of the first thin film, and a pixel electrode, which are provided corresponding to each of the intersections of the scanning wiring and the scanning wiring. A sensor unit to be connected and a common electrode connected to the sensor unit are provided, the pixel electrode is connected to the gate electrode of the first thin film, the drain electrode of the first thin film is connected to the drain wiring, and the source of the first thin film is connected. The electrode is connected to the drain electrode of the second thin film, the gate electrode of the second thin film is connected to the scanning wiring, the source electrode of the second thin film is connected to the signal wiring, and the signal detection circuit has a plurality of signal wirings. It is divided into M2 blocks by M1 each, and in each of the M2 blocks, the first switching circuit to which the M1 signal wiring is connected to the input and the output of the first switching circuit A second switching circuit is provided with a connected load resistance and voltage detection amplifier, and each output from the M2 blocks is connected to the input, and an AD converter connected to the output of the second switching circuit. It is a sensor system having and.
 本開示によれば、規模の小さい信号検出回路を提供することができる。また、信号検出回路に駆動回路および制御回路を含めた駆動検出回路の時、規模が小さく、誤差の少ない駆動検出回路を提供することができる。 According to the present disclosure, it is possible to provide a signal detection circuit on a small scale. Further, when the drive detection circuit includes the drive circuit and the control circuit in the signal detection circuit, it is possible to provide a drive detection circuit having a small scale and a small error.
図1は、本開示の第1の実施形態に係る信号検出回路を例示的に示す回路図である。FIG. 1 is a circuit diagram illustrating an exemplary signal detection circuit according to the first embodiment of the present disclosure. 図2は、図1の信号検出回路を含む駆動検出回路を例示的に示す回路図である。FIG. 2 is a circuit diagram illustrating an exemplary drive detection circuit including the signal detection circuit of FIG. 図3は、図1の信号検出回路を含む駆動検出回路の他の実例を示す回路図である。FIG. 3 is a circuit diagram showing another example of the drive detection circuit including the signal detection circuit of FIG. 図4は、単純な信号検出方法を示す説明図である。FIG. 4 is an explanatory diagram showing a simple signal detection method. 図5は、本開示の信号検出方法を例示的に示す説明図である。FIG. 5 is an explanatory diagram schematically showing the signal detection method of the present disclosure. 図6は、第1の実施形態に適用するセンサアレイを例示的に示す回路図である。FIG. 6 is a circuit diagram schematically showing a sensor array applied to the first embodiment. 図7は、本開示の第2の実施形態に係る信号検出回路を例示的に示す説明図である。FIG. 7 is an explanatory diagram illustrating an exemplary signal detection circuit according to the second embodiment of the present disclosure. 図8は、図7の信号検出回路を含む駆動検出回路を例示的に示す説明図である。FIG. 8 is an explanatory diagram illustrating an exemplary drive detection circuit including the signal detection circuit of FIG. 7. 図9は、本開示の信号検出方法を例示的に示す説明図である。FIG. 9 is an explanatory diagram schematically showing the signal detection method of the present disclosure. 図10は、第2の実施形態に適用するセンサアレイを例示的に示す回路図である。FIG. 10 is a circuit diagram schematically showing a sensor array applied to the second embodiment. 図11は、本開示の第3の実施形態に係る画素回路の一例を示す説明図である。FIG. 11 is an explanatory diagram showing an example of a pixel circuit according to the third embodiment of the present disclosure. 図12は、図11の画素回路の具体例を示す平面図および断面図である。FIG. 12 is a plan view and a cross-sectional view showing a specific example of the pixel circuit of FIG. 図13は、本開示の第4の実施形態に係る画素回路の一例を示す説明図である。FIG. 13 is an explanatory diagram showing an example of a pixel circuit according to the fourth embodiment of the present disclosure. 図14は、図13の画素回路の具体例を示す平面図および断面図である。14 is a plan view and a cross-sectional view showing a specific example of the pixel circuit of FIG. 13. 図15は、本開示の第5の実施形態に係る画素回路の一例を示す説明図である。FIG. 15 is an explanatory diagram showing an example of a pixel circuit according to a fifth embodiment of the present disclosure. 図16は、図15の画素回路の具体例を示す平面図および断面図である。16 is a plan view and a cross-sectional view showing a specific example of the pixel circuit of FIG. 図17は、本開示の第6の実施形態に係る画素回路の一例を示す説明図である。FIG. 17 is an explanatory diagram showing an example of a pixel circuit according to a sixth embodiment of the present disclosure. 図18は、図17の画素回路の具体例を示す平面図および断面図である。FIG. 18 is a plan view and a cross-sectional view showing a specific example of the pixel circuit of FIG. 図19は、本開示の介護データ収集・判定システムを例示的に示すブロック図である。FIG. 19 is a block diagram schematically showing the nursing care data collection / determination system of the present disclosure. 図20は、本開示の介護センサ装置の配置例を示す説明図である。FIG. 20 is an explanatory diagram showing an arrangement example of the nursing care sensor device of the present disclosure. 図21は、第1の実施形態に適用するセンサアレイを例示的に示す回路図である。FIG. 21 is a circuit diagram schematically showing a sensor array applied to the first embodiment. 図22は、第7の実施形態に適用する電流制限回路を例示的に示す回路図である。FIG. 22 is a circuit diagram schematically showing a current limiting circuit applied to the seventh embodiment. 図23は、図11の画素回路に接続する検出回路の一例を含む説明図である。FIG. 23 is an explanatory diagram including an example of a detection circuit connected to the pixel circuit of FIG. 図24は、図11の画素回路に接続する検出回路の他の例を含む説明図である。FIG. 24 is an explanatory diagram including another example of the detection circuit connected to the pixel circuit of FIG. 図25は、図15の画素回路に接続する検出回路の一例を含む説明図である。FIG. 25 is an explanatory diagram including an example of a detection circuit connected to the pixel circuit of FIG. 図26は、図15の画素回路に接続する検出回路の他の例を含む説明図である。FIG. 26 is an explanatory diagram including another example of the detection circuit connected to the pixel circuit of FIG. 図27は、従来の画素回路の一例を示す説明図である。FIG. 27 is an explanatory diagram showing an example of a conventional pixel circuit. 図28は、従来の画素回路の他の例を示す説明図である。FIG. 28 is an explanatory diagram showing another example of the conventional pixel circuit. 図29は、従来の信号検出回路を例示的に示す回路図である。FIG. 29 is a circuit diagram illustrating a conventional signal detection circuit as an example. 図30は、従来の信号検出回路の他の実例を示す回路図である。FIG. 30 is a circuit diagram showing another example of a conventional signal detection circuit. 図31は、従来の駆動検出回路を例示的に示す回路図である。FIG. 31 is a circuit diagram illustrating a conventional drive detection circuit as an example.
 本開示の実施の形態について、以下に図面を使用して詳細に説明する。なお、以下に使用する図面では、説明を判り易くするために縮尺は正確には描かれていない。また、本開示の実施形態は、独自の単一の発明を元とする一群の実施形態である。また、本開示の各局面は、単一の発明を元とした一群の実施形態の局面である。本開示の各構成は、本開示の各局面を有しうる。本開示の各特徴は組み合わせ可能であり、各構成をなせる。したがって、本開示の各特徴、本開示の各構成、本開示の各局面、本開示の各実施形態は、組み合わせることが可能であり、その組み合わせは協同機能を発現し、相乗的な効果を発揮しうる。 The embodiments of the present disclosure will be described in detail below with reference to the drawings. In the drawings used below, the scale is not drawn accurately for the sake of clarity. Also, the embodiments of the present disclosure are a group of embodiments based on a single invention of its own. In addition, each aspect of the present disclosure is an aspect of a group of embodiments based on a single invention. Each configuration of the present disclosure may have each aspect of the present disclosure. Each feature of the present disclosure can be combined to form each configuration. Therefore, each feature of the present disclosure, each configuration of the present disclosure, each aspect of the present disclosure, and each embodiment of the present disclosure can be combined, and the combination exerts a cooperative function and exerts a synergistic effect. Can be done.
[第1の実施形態]
 図1に本開示の第1の実施形態に係る信号検出回路の一例を示す回路図を示す。この信号検出回路を適用する対象のセンサアレイは、信号配線15をM本有する。図1において、M本の信号配線15は、M本ずつM個のブロック(図1の破線で囲まれた部分)に分けられる。各ブロックの信号配線15を信号配線A~Mと呼ぶとき、本実施形態の信号検出回路は、信号配線A~Mが第1の切替回路101の入力に接続され、第1の切替回路101の出力が負荷抵抗20および電圧検出アンプ53に接続されるブロックを、M個有する。第1の切替回路101の存在によって、必要な負荷抵抗20と電圧検出アンプ53の数はM個ではなく、M個となり、信号配線15の数より減らすことができる。
[First Embodiment]
FIG. 1 shows a circuit diagram showing an example of a signal detection circuit according to the first embodiment of the present disclosure. The target sensor array to which this signal detection circuit is applied has M signal wirings 15. In Figure 1, M of signal lines 15 are divided into one by one M M 2 blocks (broken line in the portion surrounded by the Figure 1). When the signal wiring 15 of each block is referred to as signal wiring A to M 1 , in the signal detection circuit of the present embodiment, the signal wiring A to M 1 is connected to the input of the first switching circuit 101, and the first switching circuit It has two blocks in which the output of 101 is connected to the load resistor 20 and the voltage detection amplifier 53. The presence of the first switching circuit 101, the number of required load resistor 20 and the voltage detecting amplifier 53 is not the M becomes a two M, can be reduced than the number of signal wires 15.
 さらに各ブロックの電圧検出アンプ53の出力は第2の切替回路102の入力に接続され、第2の切替回路102の出力はADコンバータ25の入力に接続される。1つの第2の切替回路102の入力数をLとすると、必要なADコンバータ25の数はM個ではなく、(M/L)個となり、電圧検出アンプ53の数より減らすことができる。第2の切替回路102の入力数LがMに等しい場合、必要なADコンバータ25の数は1個である。 Further, the output of the voltage detection amplifier 53 of each block is connected to the input of the second switching circuit 102, and the output of the second switching circuit 102 is connected to the input of the AD converter 25. When the number of inputs of one second switching circuit 102 is L, the number of AD converters 25 need not the two M, becomes (M 2 / L) number, can be reduced than the number of the voltage detection amplifier 53 .. When the number of inputs L of the second switching circuit 102 is equal to M 2 , the number of AD converters 25 required is one.
 このように、第1の切替回路101と第2の切替回路102を組み合わせることで、負荷抵抗20と電圧検出アンプ53の数を信号配線15の数より減らせ、かつADコンバータ25の数を電圧検出アンプ53の数より減らせるので、信号検出回路の規模を小さくでき、設置面積や製造コストを抑えられる。 In this way, by combining the first switching circuit 101 and the second switching circuit 102, the number of load resistance 20 and the voltage detection amplifier 53 can be reduced from the number of signal wirings 15, and the number of AD converters 25 can be detected by voltage. Since the number can be reduced from the number of amplifiers 53, the scale of the signal detection circuit can be reduced, and the installation area and manufacturing cost can be suppressed.
 なお、図1では電圧検出アンプ53をボルテージフォロワとして記載しているが、これに限定されず、増幅率が1以外の回路や、反転増幅回路でもよい。また電圧検出アンプ53は、既知の発振防止回路、位相補償回路、容量補正回路、保護回路を有してもよい。さらには、オペアンプを用いずにFET(Field EffectTransistor)等で代用してもよい。また、図1では負荷抵抗20を信号線とGNDの間に設置するように記載しているが、電圧検出アンプ53が反転増幅回路の場合は、信号線と電圧検出アンプ53の出力との間に設置してもよい。 Although the voltage detection amplifier 53 is described as a voltage follower in FIG. 1, the present invention is not limited to this, and a circuit having an amplification factor other than 1 or an inverting amplifier circuit may be used. Further, the voltage detection amplifier 53 may have a known oscillation prevention circuit, phase compensation circuit, capacitance correction circuit, and protection circuit. Further, a FET (Field Effect Transistor) or the like may be used instead of using an operational amplifier. Further, in FIG. 1, it is described that the load resistor 20 is installed between the signal line and the GND, but when the voltage detection amplifier 53 is an inverting amplifier circuit, it is between the signal line and the output of the voltage detection amplifier 53. It may be installed in.
 また、第1の切替回路101は、アナログマルチプレクサであることが望ましい。アナログマルチプレクサを用いれば、アナログ信号の情報を失うことなく、高速で切り替えが可能である。ただし、信号電圧の範囲が大きくてアナログマルチプレクサで対応できない場合などでは、リレーを用いてもよい。 Further, it is desirable that the first switching circuit 101 is an analog multiplexer. If an analog multiplexer is used, switching can be performed at high speed without losing the information of the analog signal. However, if the signal voltage range is too large for the analog multiplexer to handle, a relay may be used.
 第1の切替回路101の入力側でなく出力側に負荷抵抗20があることにより、第1の切替回路101に電流が流れてインピーダンスが低くなり、ノイズの影響を受けにくい回路となる。また、第1の切替回路101に接続された信号配線15のうち第1の切替回路101の出力に切り替えられた入力の信号線のみに、電流が流れるので、消費電力を抑えることができる。 Since the load resistance 20 is not on the input side but on the output side of the first switching circuit 101, a current flows through the first switching circuit 101 to lower the impedance, and the circuit is less susceptible to noise. Further, since the current flows only in the signal line of the input switched to the output of the first switching circuit 101 among the signal wiring 15 connected to the first switching circuit 101, the power consumption can be suppressed.
 次に、図1の信号検出回路を含む駆動検出回路の一例を示す回路図を図2に示す。この駆動検出回路を適用する対象のセンサアレイは、信号配線15をM本と、走査配線12をN本有する。図2の駆動検出回路は、本実施形態に係る信号検出回路に、制御回路5と、駆動回路6を加えたものであり、第1の切替回路101と、第2の切替回路102と、ADコンバータ25と、駆動回路6とは、制御回路5によって制御される。第1の切替回路101を制御するには、入力数Mの切替回路を切り替えられるビット数n(ただし2n-1<M≦2)のデジタル配線48が必要であり、例えば、各ブロックで必要なデジタル配線48の本数は、M=4なら2本、M=8なら3本、M=16なら4本となる。 Next, FIG. 2 shows a circuit diagram showing an example of a drive detection circuit including the signal detection circuit of FIG. The sensor array to which this drive detection circuit is applied has M signal wirings 15 and N scanning wirings 12. The drive detection circuit of FIG. 2 includes a control circuit 5 and a drive circuit 6 in addition to the signal detection circuit according to the present embodiment, and includes a first switching circuit 101, a second switching circuit 102, and an AD. The converter 25 and the drive circuit 6 are controlled by the control circuit 5. In order to control the first switching circuit 101, digital wiring 48 having the number of bits n (where 2 n-1 <M 1 ≤ 2 n ) that can switch the switching circuit having the number of inputs M 1 is required. The number of digital wiring 48 required in the block is 2 if M 1 = 4, 3 if M 1 = 8, and 4 if M 1 = 16.
 制御回路5のデジタル出力数が少ない場合、図3のように、カウンタ49を用いて第1の切替回路101を制御するとよい。これにより、各ブロックの入力を切り替えるためのデジタル配線48を、1本ずつにすることができる。 When the number of digital outputs of the control circuit 5 is small, it is preferable to control the first switching circuit 101 by using the counter 49 as shown in FIG. As a result, the digital wiring 48 for switching the input of each block can be made one by one.
 図2や図3の駆動検出回路を適用する場合の、容易に考えられる信号検出方法を図4に示す。図4では、予め第2の切替回路102をブロック1に切り替えておく。走査配線12の1行目にオン電圧を印加した後、ブロック1の第1の切替回路101を信号Aにして、信号AのデータをADコンバータ25で読み込む。次に第1の切替回路101を信号Bにして、信号BのデータをADコンバータ25で読み込む。同様にして、信号Mまでのデータを順にADコンバータ25で読み込んだ後、第2の切替回路102をブロック2に切り替えて、ブロック1と同様に、ブロック2の信号A~Mを順に読み込む。そして、ブロック1、2と同様にして、ブロックMまでを読み込む。この場合、画素の配列順にデータを読み込むことができてわかりやすいが、以下の問題がある。 FIG. 4 shows an easily conceivable signal detection method when the drive detection circuit of FIGS. 2 and 3 is applied. In FIG. 4, the second switching circuit 102 is switched to the block 1 in advance. After applying the on-voltage to the first line of the scanning wiring 12, the first switching circuit 101 of the block 1 is set to the signal A, and the data of the signal A is read by the AD converter 25. Next, the first switching circuit 101 is set to signal B, and the data of signal B is read by the AD converter 25. Similarly, after reading the data up to the signal M 1 in order by the AD converter 25, the second switching circuit 102 is switched to the block 2, and the signals A to M 1 of the block 2 are read in order in the same manner as the block 1. .. Then, in the same manner as in blocks 1 and 2, read until the block M 2. In this case, the data can be read in the order of pixel arrangement, which is easy to understand, but has the following problems.
 第1の切替回路101を切り替えてすぐにそのデータをADコンバータ25で読み込むので、信号が安定しないうちに読み込むことになり、誤差が大きくなる。 Since the data is read by the AD converter 25 immediately after switching the first switching circuit 101, the data is read before the signal is stable, and the error becomes large.
 それを改善した、信号検出方法を図5を用いて説明する。図5では、予め全ての第1の切替回路101を信号Aに切り替えておく。走査配線12の1行目にオン電圧を印加した後、一定時間待つ。 The improved signal detection method will be described with reference to FIG. In FIG. 5, all the first switching circuits 101 are switched to the signal A in advance. After applying the on-voltage to the first line of the scanning wiring 12, wait for a certain period of time.
 その後、第2の切替回路102をブロック1に切り替えて、ブロック1の信号AのデータをADコンバータ25で読み込んでから、ブロック1の第1の切替回路101を信号Bにする。次に、第2の切替回路102をブロック2に切り替えて、ブロック2の信号AのデータをADコンバータ25で読み込んでから、ブロック2の第1の切替回路101を信号Bにする。以下、ブロック3、ブロック4、・・・についても同様に行い、ブロックMについても同様、即ち、第2の切替回路102をブロックMに切り替えて、ブロックMの信号AのデータをADコンバータ25で読み込んでから、ブロックMの第1の切替回路101を信号Bにする。(以上が、「信号A読取・信号Bに切替工程」) After that, the second switching circuit 102 is switched to the block 1, the data of the signal A of the block 1 is read by the AD converter 25, and then the first switching circuit 101 of the block 1 is set to the signal B. Next, the second switching circuit 102 is switched to the block 2, the data of the signal A of the block 2 is read by the AD converter 25, and then the first switching circuit 101 of the block 2 is set to the signal B. Hereinafter, block 3, block 4, also performed on ..., also applies to the block M 2, i.e., by switching the second switching circuit 102 to the block M 2, the data signal A of the block M 2 AD After being read by the converter 25, the first switching circuit 101 of the block M 2 is set to the signal B. (The above is the "signal A reading / switching to signal B process")
 その後、第2の切替回路102をブロック1に切り替えて、ブロック1の信号BのデータをADコンバータ25で読み込んでから、ブロック1の第1の切替回路101を信号Cにする。次に、第2の切替回路102をブロック2に切り替えて、ブロック2の信号BのデータをADコンバータ25で読み込んでから、ブロック2の第1の切替回路101を信号Cにする。以下、ブロック3、ブロック4、・・・についても同様に行い、ブロックMについても同様、即ち、第2の切替回路102をブロックMに切り替えて、ブロックM2の信号BのデータをADコンバータ25で読み込んでから、ブロックMの第1の切替回路101を信号Cにする。(以上が、「信号B読取・信号Cに切替工程」) After that, the second switching circuit 102 is switched to the block 1, the data of the signal B of the block 1 is read by the AD converter 25, and then the first switching circuit 101 of the block 1 is set to the signal C. Next, the second switching circuit 102 is switched to the block 2, the data of the signal B of the block 2 is read by the AD converter 25, and then the first switching circuit 101 of the block 2 is set to the signal C. Hereinafter, block 3, block 4, also performed on ..., also applies to the block M 2, i.e., by switching the second switching circuit 102 to the block M 2, AD converter data signal B block M2 After reading at 25, the first switching circuit 101 of the block M 2 is set to the signal C. (The above is the "signal B reading / switching to signal C process")
 その後、「信号A読取・信号Bに切替工程」および「信号B読取・信号Cに切替工程」と同様にして、「信号C読取・信号Dに切替工程」、「信号D読取・信号Eに切替工程」、・・・と続き、「信号M読取・信号Aに切替工程」を行う、即ち、第2の切替回路102をブロック1に切り替えて、ブロック1の信号MのデータをADコンバータ25で読み込んでから、ブロック1の第1の切替回路101を信号Aにする。次に、第2の切替回路102をブロック2に切り替えて、ブロック2の信号MのデータをADコンバータ25で読み込んでから、ブロック2の第1の切替回路101を信号Aにする。以下、ブロック3、ブロック4、・・・についても同様に行い、ブロックMについても同様、即ち、第2の切替回路102をブロックMに切り替えて、ブロックMの信号MのデータをADコンバータ25で読み込んでから、ブロックMの第1の切替回路101を信号Aにする。ただし、この記載は分かり易くするために具体的に記載したものであって、信号Mが信号Eより後であると限定するものではなく、即ちM>5と限定するものではなく、Mは2以上の整数であればよい。また、ブロックMはブロック4より後であると限定するものではなく、即ちM>4と限定するものではなく、Mは2以上の整数であればよい。 After that, in the same manner as the "signal A reading / switching to signal B" and "signal B reading / switching to signal C", "signal C reading / switching to signal D" and "signal D reading / switching to signal E". switching step ", ... and continued, to switch process" to "signal M 1 read-signal a, i.e., by switching the second switching circuit 102 to block 1, the data of the signal M 1 of the block 1 AD After being read by the converter 25, the first switching circuit 101 of the block 1 is set to the signal A. Next, the second switching circuit 102 is switched to the block 2, the data of the signal M 1 of the block 2 is read by the AD converter 25, and then the first switching circuit 101 of the block 2 is set to the signal A. Hereinafter, block 3, block 4, do the same for., Same for block M 2, i.e., by switching the second switching circuit 102 to the block M 2, the data of the signal M 1 of the block M 2 after reading the AD converter 25, the first switching circuit 101 of the block M 2 to the signal a. However, this description is specifically described for the sake of clarity , and does not limit the signal M 1 to be later than the signal E, that is, does not limit it to M 1 > 5. 1 may be an integer of 2 or more. Further, the block M 2 is not limited to being later than the block 4, that is, it is not limited to M 2 > 4, and M 2 may be an integer of 2 or more.
 続いて、走査配線12の1行目にオフ電圧を印加した後、走査配線12の2行目にオン電圧を印加し、「一定時間」待つ。走査配線12の1行目の時と同様に、「信号A読取・信号Bに切替工程」~「信号M読取・信号Aに切替工程」を行う。 Subsequently, an off voltage is applied to the first line of the scanning wiring 12, and then an on voltage is applied to the second line of the scanning wiring 12, and the process waits for a “fixed time”. As in the case of the first row of the scanning lines 12, performs "signal A read-signal B to the switching process" - "signal M 1 read-signal A to the switching process."
 以下同様の動作を、走査配線12のN行目まで行い、走査配線12のN行目にオフ電圧を印加する。ここまでで、1画面分のセンサ情報が得られる。さらに同じ動作を繰り返すことで、複数画面分のデータ、即ち、全画素の信号の時間依存データが得られる。(ただし、N>2と限定するものではなく、Nは1以上の整数であればよい。) The same operation is performed up to the Nth line of the scanning wiring 12, and the off voltage is applied to the Nth line of the scanning wiring 12. Up to this point, sensor information for one screen can be obtained. Further, by repeating the same operation, data for a plurality of screens, that is, time-dependent data of signals of all pixels can be obtained. (However, it is not limited to N> 2, and N may be an integer of 1 or more.)
 図5の信号検出方法の特徴を、より一般的に示すと、第1の切替回路101によって選択されている信号配線を異なる他の信号配線に切り替えた後、その信号の測定を行う前に、他のブロックの第1の切替回路によって選択されている信号配線の信号の測定を1回以上行うことである。これにより、第1の切替回路101を切り替えてから、信号が安定するまでの時間を稼ぐことができ、信号測定の精度を高めることができる。特にブロック数がM個の場合、第1の切替回路101の信号の切り替えと、当該切り替えた信号の測定との間に、他の(M-1)回の測定を行うことが容易にできる。 More generally, the characteristics of the signal detection method of FIG. 5 will be shown. After switching the signal wiring selected by the first switching circuit 101 to another different signal wiring, before measuring the signal, The measurement of the signal of the signal wiring selected by the first switching circuit of the other block is performed one or more times. As a result, it is possible to gain time from switching the first switching circuit 101 until the signal stabilizes, and it is possible to improve the accuracy of signal measurement. Especially when the number of blocks is two M, the switching of the first signal switching circuit 101, between the measurement of the switching signal, the other (M 2 -1) measurements easily be performed can.
 また、図5の信号検出方法の特徴を、もう少し具体的に示す。制御回路5は、駆動回路6に、複数の走査配線12から選択された1本の走査配線にオン電圧を印加させる第1の処理を行う。オン電圧の印加後、一定時間待機する。そして、第2の切替回路によって選択された1つのブロックにおいて、第1の切替回路によって選択されている1つの信号配線の信号をADコンバータ25を介して読み出し、第1の切替回路101によって1つの信号配線とは異なる他の信号線を選択した後、選択された他の信号配線15の信号を読み出す前に、第2の切替回路102によって1つのブロックとは異なる他のブロックを選択する手順と、信号を読み出す手順と、他のブロックの第1の切替回路101を切替える手順と、の繰り返しと、第2の切替回路102によって1つのブロックを選択する手順を有し、これらのプロセスにより、選択された1本の走査配線12に対応する1行分のセンサ部の信号を順に読み出す第2の処理を行う。さらに、駆動回路6に、第2の処理の終了後に選択された1本の走査配線12にオフ電圧を印加させる第3の処理を行う。全ての走査配線12について、第1の処理、待機、第2の処理及び第3の処理を繰り返すことにより、全てのセンサ部の信号を読み出す。 In addition, the features of the signal detection method of FIG. 5 will be shown a little more concretely. The control circuit 5 performs a first process of causing the drive circuit 6 to apply an on-voltage to one scanning wiring selected from the plurality of scanning wirings 12. After applying the on-voltage, wait for a certain period of time. Then, in one block selected by the second switching circuit, the signal of one signal wiring selected by the first switching circuit is read out via the AD converter 25, and one by the first switching circuit 101. A procedure for selecting another block different from one block by the second switching circuit 102 after selecting another signal line different from the signal wiring and before reading the signal of the selected other signal wiring 15. , A procedure for reading a signal, a procedure for switching the first switching circuit 101 of another block, and a procedure for selecting one block by the second switching circuit 102, which are selected by these processes. A second process is performed in which the signals of the sensor unit for one line corresponding to the one scanning wiring 12 are read out in order. Further, the drive circuit 6 is subjected to a third process of applying an off voltage to one scanning wiring 12 selected after the completion of the second process. The signals of all the sensor units are read out by repeating the first process, the standby, the second process, and the third process for all the scanning wirings 12.
 ただし、1つのブロックにおいて第1の切替回路101によって1つの信号配線15とは異なる他の信号線を選択する手順と、第2の切替回路102によって1つのブロックとは異なる他のブロックを選択する手順は、逆でもよい。即ち第2の処理は、第2の切替回路102によって選択された1つのブロックにおいて、第1の切替回路101によって選択されている1つの信号配線15の信号をADコンバータ25を介して読み出した後、第2の切替回路102によって1つのブロックとは異なる他のブロックを選択し、1つのブロックの第1の切替回路101を1つの信号配線15とは異なる他の信号線を選択した後、1つのブロックの他の信号配線15の信号を読み出す前に、他のブロックの信号を読み出す手順と、第2の切替回路102を切替える手順と、他のブロックの第1の切替回路101を切替える手順と、の繰り返しを有し、これらのプロセスにより、選択された1本の走査配線12に対応する1行分のセンサ部の信号を順に読み出すものでもよい。 However, in one block, the procedure of selecting another signal line different from one signal wiring 15 by the first switching circuit 101 and the selection of another block different from one block by the second switching circuit 102. The procedure may be reversed. That is, the second process is performed after reading the signal of one signal wiring 15 selected by the first switching circuit 101 in one block selected by the second switching circuit 102 via the AD converter 25. After selecting another block different from one block by the second switching circuit 102 and selecting another signal line different from one signal wiring 15 for the first switching circuit 101 of one block, 1 Before reading the signal of the other signal wiring 15 of one block, the procedure of reading the signal of the other block, the procedure of switching the second switching circuit 102, and the procedure of switching the first switching circuit 101 of the other block. , And, by these processes, the signal of one line of the sensor unit corresponding to one selected scanning wiring 12 may be read out in order.
 よって第2の処理は、1つのブロックの第1の切替回路101によって1つの信号配線15とは異なる他の信号配線15を選択した後、1つのブロックの他の信号配線15の信号を読み出す前に、少なくとも、他のブロックの信号を読み出す手順と、第2の切替回路102を切替える手順と、他のブロックの第1の切替回路101を切替える手順と、の繰り返しを有する。 Therefore, in the second process, after selecting another signal wiring 15 different from one signal wiring 15 by the first switching circuit 101 of one block, and before reading the signal of the other signal wiring 15 of one block. At least, the procedure of reading the signal of the other block, the procedure of switching the second switching circuit 102, and the procedure of switching the first switching circuit 101 of the other block are repeated.
 また、N本の走査配線12のうち1本にオン電圧を印加してから一定時間待つ、その「一定時間」は、ADコンバータ25の測定時間の(M-1)倍以上が望ましい。そうすれば、1画面の最初の測定である、ブロック1の信号Aについても、第1の切替回路101を信号Aに切り替えた後、その信号Aの測定を行うまでに、ADコンバータ25の測定時間×(M-1)以上を挟むことができて、他の信号の測定と同様に信号が安定するまでの時間を稼ぐことができ、信号測定の精度を他の信号と同程度まで高めることができる。 Further, waits a predetermined time from the turn-on voltage is applied to the one of the N of scanning lines 12, the "predetermined time" is the measurement time of the AD converter 25 (M 2 -1) times or more. Then, regarding the signal A of the block 1, which is the first measurement of one screen, the measurement of the AD converter 25 is performed after the first switching circuit 101 is switched to the signal A and before the measurement of the signal A is performed. to be able to sandwich the time × (M 2 -1) or more, the signal as with the measurement of other signals can earn time to stabilize, improve the accuracy of signal measurement to the same extent as the other signal be able to.
 本実施の形態の信号検出回路、駆動検出回路、信号検出方法に適したセンサアレイの実例を説明する。図6は、第1の実施形態に適用するセンサアレイの一例を示す回路図である。センサアレイは、N本の走査配線12と、M本の信号配線15と、のマトリクスの交点に第1の薄膜トランジスタT1と第2の薄膜トランジスタT2による画素回路が組まれ、第1の薄膜トランジスタT1のゲート電極と、共通電極10の間に、センサ部109として例えば感圧媒体9を有する。第1の薄膜トランジスタT1のドレインにはドレイン配線14が接続され、第1の薄膜トランジスタT1のソースは第2の薄膜トランジスタT2のドレインに接続され、第2の薄膜トランジスタT2のゲートは走査配線12に接続され、第2の薄膜トランジスタT2のソースは信号配線15に接続されている。感圧媒体9には圧力に依存する電圧が発生する。走査配線12のうち1本をオンにした時、その行の画素の刺激(圧力等)に依存する電流が、信号配線15に流れる。センサ部109としては、感圧媒体9、例えばポリビニリデンジフロライド(PVDF)や、ポリ(ビニリデンジフロライド-トリフロロエチレン共重合体)が好適である。なお、図6は一例であり、この構造のセンサアレイに限定されるものではない。図21は、第1の実施形態に適用するセンサアレイの一例を示す回路図である。センサアレイは、N本の走査配線12と、M本の信号配線15と、のマトリクスの交点に薄膜トランジスタ38による画素回路が組まれ、薄膜トランジスタ38のドレイン電極と、電源配線36の間に、感圧媒体39を有する。薄膜トランジスタ38のゲートは走査配線12に接続され、薄膜トランジスタ38のソースは信号配線15に接続されている。感圧媒体39の抵抗値は圧力によって変化する。走査配線12のうち1本をオンにした時、その行の画素の圧力に依存する電流が、信号配線15に流れる。感圧媒体39としては、導電粒子を分散させたゴム等が好適である。あるいは他のセンサ部109を採用して、他の種類の圧力センサや、変位センサ、温度センサ等に用いてもよい。また、電源配線36は、第7の実施形態に後述する電流制限回路40を有してもよい。 An example of a sensor array suitable for the signal detection circuit, the drive detection circuit, and the signal detection method of the present embodiment will be described. FIG. 6 is a circuit diagram showing an example of a sensor array applied to the first embodiment. In the sensor array, a pixel circuit consisting of the first thin film transistor T1 and the second thin film transistor T2 is assembled at the intersection of the matrix of N scanning wires 12 and M signal wirings 15, and the gate of the first thin film transistor T1 is formed. A pressure-sensitive medium 9, for example, is provided as a sensor unit 109 between the electrode and the common electrode 10. The drain wiring 14 is connected to the drain of the first thin film transistor T1, the source of the first thin film transistor T1 is connected to the drain of the second thin film transistor T2, and the gate of the second thin film transistor T2 is connected to the scanning wiring 12. The source of the second thin film transistor T2 is connected to the signal wiring 15. A pressure-dependent voltage is generated in the pressure-sensitive medium 9. When one of the scanning wires 12 is turned on, a current depending on the stimulation (pressure, etc.) of the pixels in that row flows through the signal wiring 15. As the sensor unit 109, a pressure sensitive medium 9, for example, polyvinylidene fluoride (PVDF) or polyvinylidene fluoride-trifluoroethylene copolymer is suitable. Note that FIG. 6 is an example, and the present invention is not limited to the sensor array having this structure. FIG. 21 is a circuit diagram showing an example of a sensor array applied to the first embodiment. In the sensor array, a pixel circuit by the thin film transistor 38 is assembled at the intersection of the matrix of N scanning wires 12 and M signal wires 15, and the pressure is sensitive between the drain electrode of the thin film transistor 38 and the power supply wiring 36. It has a medium 39. The gate of the thin film transistor 38 is connected to the scanning wire 12, and the source of the thin film transistor 38 is connected to the signal wire 15. The resistance value of the pressure sensitive medium 39 changes depending on the pressure. When one of the scanning wires 12 is turned on, a current that depends on the pressure of the pixels in that row flows through the signal wires 15. As the pressure sensitive medium 39, rubber or the like in which conductive particles are dispersed is suitable. Alternatively, another sensor unit 109 may be adopted and used for another type of pressure sensor, displacement sensor, temperature sensor, or the like. Further, the power supply wiring 36 may have a current limiting circuit 40 described later in the seventh embodiment.
 以上のように、第1の実施形態に係る信号検出回路では、負荷抵抗20および電圧検出アンプ53の上流側に第1の切替回路101を設けることで、負荷抵抗20および電圧検出アンプ53の数を減らすことができ、さらに、電圧検出アンプ53の下流側に第2の切替回路102を設けることで、ADコンバータ25の数も減らすことができ、信号検出回路の規模を小さくすることができる。また、当該信号検出回路を適用することで、駆動検出回路の規模も小さくすることができる。また、第1の切替回路101で信号を切り替えた後、その信号の測定を行う前に、他のブロックの切り替え済みかつ未測定の信号の測定を行うことで、切替信号が安定してから測定を行うことができる。 As described above, in the signal detection circuit according to the first embodiment, the number of the load resistance 20 and the voltage detection amplifier 53 is increased by providing the first switching circuit 101 on the upstream side of the load resistance 20 and the voltage detection amplifier 53. Further, by providing the second switching circuit 102 on the downstream side of the voltage detection amplifier 53, the number of AD converters 25 can be reduced, and the scale of the signal detection circuit can be reduced. Further, by applying the signal detection circuit, the scale of the drive detection circuit can be reduced. Further, after the signal is switched by the first switching circuit 101 and before the measurement of the signal is performed, the switched and unmeasured signals of other blocks are measured, so that the measurement is performed after the switching signal becomes stable. It can be performed.
[第2の実施形態]
 図7を用いて本開示の第2の実施形態について説明する。図7は、本開示の第2の実施形態に係る信号検出回路の一例を示す説明図である。この信号検出回路を適用する対象のセンサアレイは、信号配線15をM本と、リファレンス信号配線16をM本を有する。信号配線15とリファレンス信号配線16は、各M本ずつM個のブロックに分けられる。各ブロックの信号配線A~Mは第1の切替回路101の入力に接続され、第1の切替回路101の出力は負荷抵抗20および電圧検出アンプ53に接続される。また、各ブロックのリファレンス信号配線A~Mは第3の切替回路103の入力に接続され、第3の切替回路103の出力は負荷抵抗21および電圧検出アンプ54に接続される。よって、必要な負荷抵抗と電圧検出アンプの数は信号配線15とリファレンス信号配線16との合計(M×2)ではなく、ブロックの数の二倍(M×2)となる。
[Second Embodiment]
A second embodiment of the present disclosure will be described with reference to FIG. 7. FIG. 7 is an explanatory diagram showing an example of the signal detection circuit according to the second embodiment of the present disclosure. The sensor array to which this signal detection circuit is applied has M signal wirings 15 and M reference signal wirings 16. Signal lines 15 and the reference signal lines 16 are divided into M 2 blocks one by one each M. The signal wirings A to M 1 of each block are connected to the input of the first switching circuit 101, and the output of the first switching circuit 101 is connected to the load resistance 20 and the voltage detection amplifier 53. Further, the reference signal wirings A to M 1 of each block are connected to the input of the third switching circuit 103, and the output of the third switching circuit 103 is connected to the load resistance 21 and the voltage detection amplifier 54. Therefore, the required load resistance and the number of voltage detection amplifiers are not the total of the signal wiring 15 and the reference signal wiring 16 (M × 2), but twice the number of blocks (M 2 × 2).
 さらに信号の電圧検出アンプ53の出力と、その信号に対応するリファレンス信号の電圧検出アンプ54の出力は、差動増幅回路24に入力される。必要な差動増幅回路24の数はブロック数と同じM個である。差動増幅回路24の出力は第2の切替回路102の入力に接続され、第2の切替回路102の出力はADコンバータ25の入力に接続される。第2の切替回路102の入力数をLとすると、必要なADコンバータ25の数はM個ではなく、(M/L)個となり、差動増幅回路24の数より減らすことができる。第2の切替回路102の入力数LがMに等しい場合、必要なADコンバータ25の数は1個である。 Further, the output of the voltage detection amplifier 53 of the signal and the output of the voltage detection amplifier 54 of the reference signal corresponding to the signal are input to the differential amplifier circuit 24. The number of differential amplifier circuits 24 required is M 2 , which is the same as the number of blocks. The output of the differential amplifier circuit 24 is connected to the input of the second switching circuit 102, and the output of the second switching circuit 102 is connected to the input of the AD converter 25. When the number of inputs of the second switching circuit 102 is L, the number of AD converters 25 need not the two M, becomes (M 2 / L) number, it can be reduced than the number of the differential amplifier circuit 24. When the number of inputs L of the second switching circuit 102 is equal to M 2 , the number of AD converters 25 required is one.
 このように、第1の切替回路101、第3の切替回路103と、第2の切替回路102を組み合わせることで、負荷抵抗20と電圧検出アンプ53の数を信号配線15の数よりも減らせ、負荷抵抗21と電圧検出アンプ54の数をリファレンス信号配線16の数よりも減らせ、かつADコンバータ25の数を差動増幅回路24の数より減らせるので、信号検出回路の規模を小さくでき、設置面積やコストを抑えられる。 In this way, by combining the first switching circuit 101, the third switching circuit 103, and the second switching circuit 102, the number of the load resistance 20 and the voltage detection amplifier 53 can be reduced from the number of the signal wiring 15. Since the number of load resistors 21 and voltage detection amplifiers 54 can be reduced from the number of reference signal wirings 16 and the number of AD converters 25 can be reduced from the number of differential amplifier circuits 24, the scale of the signal detection circuits can be reduced and installed. Area and cost can be reduced.
 なお、図7では電圧検出アンプ53、54をボルテージフォロワとして記載しているが、これに限定されず、増幅率が1以外の回路や、反転増幅回路でもよい。また電圧検出アンプ53、54は、既知の発振防止回路、位相補償回路、容量補正回路、保護回路を有してもよい。さらには、オペアンプを用いずにFET等で代用してもよい。また、図7では負荷抵抗20、21を信号線とGNDの間に設置するように記載しているが、電圧検出アンプ53および54が反転増幅回路の場合は、信号線と反転増幅回路の出力の間に設置してもよい。さらに、差動増幅回路24は、増幅率が1の、信号とリファレンス信号の差を見る回路であってもよいが、増幅率が1以外であってもよい。また差動増幅回路24は、ベース電圧Vbase分だけ出力電圧をシフトできる。差動増幅回路24では、信号配線出力-リファレンス出力にVbaseを加算することで、信号配線出力-リファレンス出力が小さい場合や負の場合でも、確実に検出できる。 Although the voltage detection amplifiers 53 and 54 are described as voltage followers in FIG. 7, the present invention is not limited to this, and a circuit having an amplification factor other than 1 or an inverting amplifier circuit may be used. Further, the voltage detection amplifiers 53 and 54 may have known oscillation prevention circuits, phase compensation circuits, capacitance correction circuits, and protection circuits. Further, FET or the like may be used instead of the operational amplifier. Further, in FIG. 7, it is described that the load resistors 20 and 21 are installed between the signal line and the GND, but when the voltage detection amplifiers 53 and 54 are inverting amplifier circuits, the output of the signal line and the inverting amplifier circuit It may be installed between. Further, the differential amplifier circuit 24 may be a circuit in which the amplification factor is 1 and the difference between the signal and the reference signal is observed, but the amplification factor may be other than 1. Further, the differential amplifier circuit 24 can shift the output voltage by the base voltage Vbase. In the differential amplifier circuit 24, by adding Vbase to the signal wiring output-reference output, even when the signal wiring output-reference output is small or negative, it can be reliably detected.
 また、第1の切替回路101、第3の切替回路103は、アナログマルチプレクサであることが望ましい。アナログマルチプレクサなら、アナログ信号の情報を失うことなく、高速で切り替えが可能である。ただし、信号電圧の範囲が大きくてアナログマルチプレクサで対応できない場合などでは、リレーを用いてもよい。 Further, it is desirable that the first switching circuit 101 and the third switching circuit 103 are analog multiplexers. With an analog multiplexer, switching is possible at high speed without losing the information of the analog signal. However, if the signal voltage range is too large for the analog multiplexer to handle, a relay may be used.
 第1の切替回路101および第3の切替回路103の、入力側でなく出力側に負荷抵抗20および21があることにより、第1の切替回路101および第3の切替回路103に電流が流れてインピーダンスが低くなり、ノイズの影響を受けにくい回路となる。また、第1の切替回路101に接続された信号配線15のうち第1の切替回路101の出力に切り替えられた入力の信号線のみと、第3の切替回路103に接続されたリファレンス信号配線16のうち第3の切替回路103の出力に切り替えられた入力のリファレンス信号線のみに、電流が流れるので、消費電力を抑えることができる。 Due to the load resistors 20 and 21 on the output side of the first switching circuit 101 and the third switching circuit 103 instead of the input side, a current flows through the first switching circuit 101 and the third switching circuit 103. The impedance becomes low, and the circuit is less susceptible to noise. Further, of the signal wiring 15 connected to the first switching circuit 101, only the input signal line switched to the output of the first switching circuit 101 and the reference signal wiring 16 connected to the third switching circuit 103. Since the current flows only through the reference signal line of the input switched to the output of the third switching circuit 103, the power consumption can be suppressed.
 次に、本実施形態に係る駆動検出回路について説明する。図8は、図5の信号検出回路を含む駆動検出回路の一例を示す説明図である。この駆動検出回路を適用する対象のセンサアレイは、信号配線15をM本と、リファレンス信号配線16をM本と、走査配線12をN本有する。図8の駆動検出回路は、本実施形態に係る信号検出回路に、制御回路5と、駆動回路6を加えたものであり、第1の切替回路101と、第3の切替回路103と、第2の切替回路102と、ADコンバータ25と、駆動回路6と、は、制御回路5によって制御される。制御回路5のデジタル出力数が少ない場合、カウンタ49を用いて第1の切替回路101および第3の切替回路103を制御する。カウンタ49を用いれば、各ブロックの入力を切り替えるためのデジタル配線48を、1本ずつにすることができる。 Next, the drive detection circuit according to this embodiment will be described. FIG. 8 is an explanatory diagram showing an example of a drive detection circuit including the signal detection circuit of FIG. The sensor array to which this drive detection circuit is applied has M signal wirings 15, M reference signal wirings 16, and N scanning wirings 12. The drive detection circuit of FIG. 8 includes a control circuit 5 and a drive circuit 6 in addition to the signal detection circuit according to the present embodiment, and includes a first switching circuit 101, a third switching circuit 103, and a third switching circuit 103. The switching circuit 102 of 2, the AD converter 25, and the drive circuit 6 are controlled by the control circuit 5. When the number of digital outputs of the control circuit 5 is small, the counter 49 is used to control the first switching circuit 101 and the third switching circuit 103. If the counter 49 is used, the digital wiring 48 for switching the input of each block can be made one by one.
 図8に示す駆動検出回路を適用する場合も、第1の実施形態と同様に、単純な信号検出方法ではなく図9に示す信号検出方法が望ましい。 Even when the drive detection circuit shown in FIG. 8 is applied, the signal detection method shown in FIG. 9 is desirable instead of the simple signal detection method as in the first embodiment.
 図9では、予め全ての第1の切替回路101を信号Aに、第3の切替回路103をリファレンス信号Aに、第2の切替回路102をブロック1に切り替えておく。走査配線12の1行目にオン電圧を印加した後、「一定時間」待つ。 In FIG. 9, all the first switching circuits 101 are switched to the signal A, the third switching circuit 103 is switched to the reference signal A, and the second switching circuit 102 is switched to the block 1. After applying the on-voltage to the first line of the scanning wiring 12, wait for a "fixed time".
 その後、ブロック1の信号Aとリファレンス信号Aの差に対応するデータをADコンバータ25で読み込んでから、ブロック1の第1の切替回路101を信号Bに、ブロック1の第3の切替回路103をリファレンス信号Bにする。次に、第2の切替回路102をブロック2に切り替えて、ブロック2の信号Aとリファレンス信号Aの差に対応するデータをADコンバータ25で読み込んでから、ブロック2の第1の切替回路101を信号Bに、ブロック2の第3の切替回路103をリファレンス信号Bにする。以下、ブロック3、ブロック4、・・・についても同様に行い、ブロックMについても同様、即ち、第2の切替回路102をブロックMに切り替えて、ブロックMの信号Aとリファレンス信号Aの差に対応するデータをADコンバータ25で読み込んでから、ブロックMの第1の切替回路101を信号Bに、ブロックMの第3の切替回路103をリファレンス信号Bにする。(以上が、「信号差A読取・信号Bに切替工程」) After that, the data corresponding to the difference between the signal A of the block 1 and the reference signal A is read by the AD converter 25, and then the first switching circuit 101 of the block 1 is used as the signal B and the third switching circuit 103 of the block 1 is used. Set to reference signal B. Next, the second switching circuit 102 is switched to the block 2, the data corresponding to the difference between the signal A and the reference signal A of the block 2 is read by the AD converter 25, and then the first switching circuit 101 of the block 2 is used. For the signal B, the third switching circuit 103 of the block 2 is used as the reference signal B. Hereinafter, the same applies to the blocks 3, the blocks 4, ..., And the same applies to the block M 2 , that is, the second switching circuit 102 is switched to the block M 2 , and the signal A and the reference signal A of the block M 2 are switched. data corresponding to the difference from the loading by the AD converter 25, a first switching circuit 101 of the block M 2 to the signal B, and the third switching circuit 103 of the block M 2 in the reference signal B. (The above is the "signal difference A reading / switching to signal B process")
 その後、第2の切替回路102をブロック1に切り替えて、ブロック1の信号Bとリファレンス信号Bの差に対応するデータをADコンバータ25で読み込んでから、ブロック1の第1の切替回路101を信号Cに、ブロック1の第3の切替回路103をリファレンス信号Cにする。次に、第2の切替回路102をブロック2に切り替えて、ブロック2の信号Bとリファレンス信号Bの差に対応するデータをADコンバータ25で読み込んでから、ブロック2の第1の切替回路101を信号Cに、ブロック2の第3の切替回路103をリファレンス信号Cにする。以下、ブロック3、ブロック4、・・・についても同様に行い、ブロックMについても同様、即ち、第2の切替回路102をブロックMに切り替えて、ブロックMの信号Bとリファレンス信号Bの差に対応するデータをADコンバータ25で読み込んでから、ブロックMの第1の切替回路101を信号Cに、ブロックMの第3の切替回路103をリファレンス信号Cにする。(以上が、「信号差B読取・信号Cに切替工程」) After that, the second switching circuit 102 is switched to the block 1, the data corresponding to the difference between the signal B and the reference signal B of the block 1 is read by the AD converter 25, and then the first switching circuit 101 of the block 1 is signaled. In C, the third switching circuit 103 of the block 1 is used as the reference signal C. Next, the second switching circuit 102 is switched to the block 2, the data corresponding to the difference between the signal B and the reference signal B of the block 2 is read by the AD converter 25, and then the first switching circuit 101 of the block 2 is used. For the signal C, the third switching circuit 103 of the block 2 is used as the reference signal C. Hereinafter, the same applies to the blocks 3, the blocks 4, ..., And the same applies to the block M 2 , that is, the second switching circuit 102 is switched to the block M 2 , and the signal B and the reference signal B of the block M 2 are switched. data corresponding to the difference from the loading by the AD converter 25, a first switching circuit 101 of the block M 2 to the signal C, and a third switching circuit 103 of the block M 2 in the reference signal C. (The above is the "signal difference B reading / switching to signal C process")
 その後、「信号差A読取・信号Bに切替工程」、「信号差B読取・信号Cに切替工程」
と同様にして、「信号差C読取・信号Dに切替工程」、「信号差D読取・信号Eに切替工程」、・・・と続き、「信号差M1読取・信号Aに切替工程」を行う、即ち、第2の切替回路102をブロック1に切り替えて、ブロック1の信号Mとリファレンス信号Mの差に対応するデータをADコンバータ25で読み込んでから、ブロック1の第1の切替回路101を信号Aに、ブロック1の第3の切替回路103をリファレンス信号Aにする。次に、第2の切替回路102をブロック2に切り替えて、ブロック2の信号Mとリファレンス信号Mの差に対応するデータをADコンバータ25で読み込んでから、ブロック2の第1の切替回路101を信号Aに、ブロック2の第3の切替回路103をリファレンス信号Aにする。以下、ブロック3、ブロック4、・・・についても同様に行い、ブロックMについても同様、即ち、第2の切替回路102をブロックMに切り替えて、ブロックMの信号Mとリファレンス信号Mの差に対応するデータをADコンバータ25で読み込んでから、ブロックMの第1の切替回路101を信号Aに、ブロックMの第3の切替回路103をリファレンス信号Aにする。ただし、この記載は分かり易くするために具体的に記載したものであって、信号Mが信号Eより後であると限定するものではなく、即ちM>5と限定するものではなく、Mは2以上の整数であればよい。また、ブロックMはブロック4より後であると限定するものではなく、即ちM>4と限定するものではなく、Mは2以上の整数であればよい。
After that, "Signal difference A reading / switching to signal B", "Signal difference B reading / switching to signal C"
In the same manner as above, "Signal difference C reading / switching to signal D", "Signal difference D reading / switching to signal E", and so on, followed by "Signal difference M1 reading / switching to signal A". That is, the second switching circuit 102 is switched to the block 1, the data corresponding to the difference between the signal M 1 of the block 1 and the reference signal M 1 is read by the AD converter 25, and then the first switching of the block 1 is performed. The circuit 101 is used as the signal A, and the third switching circuit 103 of the block 1 is used as the reference signal A. Then, by switching the second switching circuit 102 to the block 2, the data corresponding to the difference between the signal M 1 and the reference signal M 1 of the block 2 from the loading by the AD converter 25, a first switching circuit block 2 101 is used as the signal A, and the third switching circuit 103 of the block 2 is used as the reference signal A. Hereinafter, the same applies to the blocks 3, the blocks 4, ..., And the same applies to the block M 2 , that is, the second switching circuit 102 is switched to the block M 2 , and the signal M 1 and the reference signal of the block M 2 are switched. data corresponding to the difference between M 1 after reading the AD converter 25, a first switching circuit 101 of the block M 2 to the signal a, the third switching circuit 103 of the block M 2 in the reference signal a. However, this description is specifically described for the sake of clarity , and does not limit the signal M 1 to be later than the signal E, that is, does not limit it to M 1 > 5. 1 may be an integer of 2 or more. Further, the block M 2 is not limited to being later than the block 4, that is, it is not limited to M 2 > 4, and M 2 may be an integer of 2 or more.
 続いて、走査配線12の1行目にオフ電圧を印加した後、走査配線12の2行目にオン電圧を印加し、「一定時間」待つ。走査配線12の1行目の時と同様に、「信号差A読取・信号Bに切替工程」~「信号差M読取・信号Aに切替工程」を行う。 Subsequently, an off voltage is applied to the first line of the scanning wiring 12, and then an on voltage is applied to the second line of the scanning wiring 12, and the process waits for a “fixed time”. Similar to the first line of the scanning wiring 12, "signal difference A reading / switching to signal B" to "signal difference M 1 reading / switching to signal A" are performed.
 以下同様の動作を、走査配線12のN行目まで行い、走査配線12のN行目にオフ電圧を印加する。ここまでで、1画面分のセンサ情報が得られる。さらに同じ動作を繰り返すことで、複数画面分のデータ、即ち、全画素の信号差の時間依存データが得られる。(ただし、N>2と限定するものではなく、Nは1以上の整数であればよい。) The same operation is performed up to the Nth line of the scanning wiring 12, and the off voltage is applied to the Nth line of the scanning wiring 12. Up to this point, sensor information for one screen can be obtained. Further, by repeating the same operation, data for a plurality of screens, that is, time-dependent data of signal differences of all pixels can be obtained. (However, it is not limited to N> 2, and N may be an integer of 1 or more.)
 図9の信号検出方法の特徴は、第1の切替回路101で選択されている信号配線と、当該信号配線に対応するリファレンス信号に切り替えた後、それらの信号差の測定を行う前に、他のブロックの第1の切替回路101で選択されている信号配線の信号と当該信号配線に対応するリファレンス信号配線の信号との差の測定を1回以上行うことである。これにより、第1の切替回路101および第3の切替回路103を切り替えてから、信号が安定するまでの時間を稼ぐことができ、信号測定の精度を高めることができる。特にブロック数がM個の場合、(M-1)回の測定を挟むことが容易にできる。 The feature of the signal detection method of FIG. 9 is that after switching to the signal wiring selected by the first switching circuit 101 and the reference signal corresponding to the signal wiring, before measuring the signal difference between them, the other The measurement of the difference between the signal of the signal wiring selected by the first switching circuit 101 of the block and the signal of the reference signal wiring corresponding to the signal wiring is performed one or more times. As a result, it is possible to gain time from switching the first switching circuit 101 and the third switching circuit 103 until the signal stabilizes, and it is possible to improve the accuracy of signal measurement. Especially when the number of blocks is two M, it can be easily sandwich the measurements (M 2 -1) times.
 また、図9の信号検出方法の特徴を、もう少し具体的に示す。制御回路5は、駆動回路6に、複数の走査配線12から選択された1本の走査配線12にオン電圧を印加させる第1の処理を行う。オン電圧の印加後、一定時間待機する。そして、第2の切替回路102によって選択された1つのブロックにおいて、第1の切替回路101によって選択されている1つの信号配線15と第3の切替回路103によって選択されている1つの信号配線15に対応するリファレンス信号配線16の信号差をADコンバータ25を介して読み出し、第1および第3の切替回路によって1つの信号配線15およびリファレンス信号配線16とは異なる他の信号線およびリファレンス信号配線16を選択した後、選択された他の信号配線15およびリファレンス信号配線16の信号差を読み出す前に、第2の切替回路102によって1つのブロックとは異なる他のブロックを選択する手順と、信号差を読み出す手順と、他のブロックの第1および第3の切替回路を切替える手順と、の繰り返しと、第2の切替回路102によって1つのブロックを選択する手順を有し、これらのプロセスにより、選択された1本の走査配線12に対応する1行分のセンサ部の信号差を順に読み出す第2の処理を行う。さらに、駆動回路6に、第2の処理の終了後に選択された1本の走査配線12にオフ電圧を印加させる第3の処理を行う。全ての走査配線12について、第1の処理、待機、第2の処理及び第3の処理を繰り返すことにより、全てのセンサ部の信号を読み出す。 In addition, the features of the signal detection method of FIG. 9 will be shown a little more concretely. The control circuit 5 performs a first process of causing the drive circuit 6 to apply an on-voltage to one scanning wiring 12 selected from the plurality of scanning wirings 12. After applying the on-voltage, wait for a certain period of time. Then, in one block selected by the second switching circuit 102, one signal wiring 15 selected by the first switching circuit 101 and one signal wiring 15 selected by the third switching circuit 103. The signal difference of the reference signal wiring 16 corresponding to the above is read out via the AD converter 25, and one signal wiring 15 and another signal line different from the reference signal wiring 16 and the reference signal wiring 16 are read by the first and third switching circuits. After selecting, and before reading the signal difference of the other selected signal wiring 15 and the reference signal wiring 16, the procedure of selecting another block different from one block by the second switching circuit 102 and the signal difference. There is a procedure of reading out, a procedure of switching the first and third switching circuits of other blocks, and a procedure of selecting one block by the second switching circuit 102, and the selection is performed by these processes. A second process is performed in which the signal difference of one line of the sensor unit corresponding to the one scanning wiring 12 is read out in order. Further, the drive circuit 6 is subjected to a third process of applying an off voltage to one scanning wiring 12 selected after the completion of the second process. The signals of all the sensor units are read out by repeating the first process, the standby, the second process, and the third process for all the scanning wirings 12.
 ただし、1つのブロックにおいて第1および第3の切替回路によって1つの信号配線15およびリファレンス信号配線16とは異なる他の信号配線15およびリファレンス信号配線16を選択する手順と、第2の切替回路102によって1つのブロックとは異なる他のブロックを選択する手順は、逆でもよい。即ち第2の処理は、第2の切替回路102によって選択された1つのブロックにおいて、第1および第3の切替回路によって選択されている1つの信号配線15およびリファレンス信号配線16の信号差をADコンバータ25を介して読み出した後、第2の切替回路102によって1つのブロックとは異なる他のブロックを選択し、1つのブロックの第1および第3の切替回路を1つの信号配線15およびリファレンス信号配線16とは異なる他の信号配線15およびリファレンス信号配線16を選択した後、1つのブロックの他の信号配線15およびリファレンス信号配線16の信号差を読み出す前に、他のブロックの信号差を読み出す手順と、第2の切替回路102を切替える手順と、他のブロックの第1および第3の切替回路を切替える手順と、の繰り返しを有し、これらのプロセスにより、選択された1本の走査配線12に対応する1行分のセンサ部の信号を順に読み出すものでもよい。 However, a procedure for selecting another signal wiring 15 and a reference signal wiring 16 different from one signal wiring 15 and the reference signal wiring 16 by the first and third switching circuits in one block, and a second switching circuit 102. The procedure for selecting another block that is different from one block may be reversed. That is, in the second process, in one block selected by the second switching circuit 102, the signal difference between the one signal wiring 15 and the reference signal wiring 16 selected by the first and third switching circuits is AD. After reading through the converter 25, another block different from one block is selected by the second switching circuit 102, and the first and third switching circuits of one block are connected to one signal wiring 15 and a reference signal. After selecting another signal wiring 15 and reference signal wiring 16 different from the wiring 16, read the signal difference of the other block before reading the signal difference of the other signal wiring 15 and the reference signal wiring 16 of one block. It has a repetition of a procedure, a procedure for switching the second switching circuit 102, and a procedure for switching the first and third switching circuits of other blocks, and one scanning wiring selected by these processes. The signals of one line of the sensor unit corresponding to 12 may be read out in order.
 よって第2の処理は、1つのブロックの第1の切替回路101および第3の切替回路103によって1つの信号配線15およびリファレンス信号配線16とは異なる他の信号配線15およびリファレンス配線16を選択した後、1つのブロックの他の信号配線15およびリファレンス信号配線16の信号差を読み出す前に、少なくとも、他のブロックの信号差を読み出す手順と、第2の切替回路102を切替える手順と、他のブロックの第1の切替回路101および第3の切替回路103を切替える手順と、の繰り返しを有する。 Therefore, in the second process, the first switching circuit 101 and the third switching circuit 103 of one block select the other signal wiring 15 and the reference wiring 16 different from the one signal wiring 15 and the reference signal wiring 16. After that, before reading the signal difference of the other signal wiring 15 and the reference signal wiring 16 of one block, at least the procedure of reading the signal difference of the other block, the procedure of switching the second switching circuit 102, and other procedures. The procedure for switching the first switching circuit 101 and the third switching circuit 103 of the block is repeated.
 また、N本の走査配線12のうち1本にオン電圧を印加してから一定時間待つ、その「一定時間」は、ADコンバータ25の測定時間の(M-1)倍以上が望ましい。そうすれば、1画面の最初の測定である、ブロック1の信号Aとリファレンス信号Aの差についても、第1の切替回路101と第3の切替回路103を信号Aに切り替えた後、その信号Aとリファレンス信号Aとの差の測定を行うまでに、ADコンバータ25の測定時間×(M-1)以上を挟むことができて、他の信号差の測定と同様に信号とリファレンス信号が安定するまでの時間を稼ぐことができ、信号測定の精度を他の信号差と同程度まで高めることができる。また、信号とリファレンス信号が安定してから測定を行うので、信号が安定するまでの時定数と、リファレンス信号が安定するまでの時定数が、必ずしも一致していなくてもよい。 Further, waits a predetermined time from the turn-on voltage is applied to the one of the N of scanning lines 12, the "predetermined time" is the measurement time of the AD converter 25 (M 2 -1) times or more. Then, regarding the difference between the signal A and the reference signal A of the block 1, which is the first measurement on one screen, the signal after switching the first switching circuit 101 and the third switching circuit 103 to the signal A by performing the measurement of the difference between a and the reference signal a, to be able to sandwich the measuring time × (M 2 -1) or more AD converters 25, is measured as well as signal and reference signals of the other signal difference It is possible to gain time until it stabilizes, and the accuracy of signal measurement can be improved to the same level as other signal differences. Further, since the measurement is performed after the signal and the reference signal are stable, the time constant until the signal stabilizes and the time constant until the reference signal stabilizes do not necessarily have to match.
 本実施形態の信号検出回路、駆動検出回路、信号検出方法に適用できる好適なセンサアレイを説明する。図10は、第2の実施形態に適用するセンサアレイの実例を示す回路図である。センサアレイは、N本の走査配線12と、M本の信号配線15と、のマトリクスの交点に第1の薄膜トランジスタT1と第2の薄膜トランジスタT2による画素回路が組まれ、第1の薄膜トランジスタT1のゲート電極と、共通電極10の間に、センサ部109として例えば感圧媒体9を有する。また、N本の走査配線12と、M本のリファレンス信号配線16の交点に第3の薄膜トランジスタT3と第4の薄膜トランジスタT4によるリファレンス回路が組まれ、第3の薄膜トランジスタT3は第1の薄膜トランジスタT1に隣接する。第3の薄膜トランジスタT3のチャネル長/チャネル幅は、第1の薄膜トランジスタT1のチャネル長/チャネル幅に等しく、第4の薄膜トランジスタT4のチャネル長/チャネル幅は、第2の薄膜トランジスタT2のチャネル長/チャネル幅に等しいことが望ましい。第1の薄膜トランジスタT1のドレインにはドレイン配線14が接続され、第1の薄膜トランジスタT1のソースは第2の薄膜トランジスタT2のドレインに接続され、第2の薄膜トランジスタT2のゲートは走査配線12に接続され、第2の薄膜トランジスタT2のソースは信号配線15に接続されている。センサ部109には刺激(圧力等)に依存する電圧が発生する。一方、第3の薄膜トランジスタT3のゲートには共通電極10が接続され、第3の薄膜トランジスタT3のドレインにはドレイン配線14が接続され、第3の薄膜トランジスタT3のソースは第4の薄膜トランジスタT4のドレインに接続され、第4の薄膜トランジスタT4のゲートは走査配線12に接続され、第4の薄膜トランジスタT4のソースはリファレンス信号配線16に接続されている。走査配線12のうち1本をオンにした時、その行の画素の圧力に依存する電流が信号配線15に流れ、その行の画素回路に特性が近く、かつ刺激(圧力等)に依存しない電流がリファレンス信号配線16に流れる。センサ部109としては、感圧媒体9、例えばポリビニリデンジフロライド(PVDF)や、ポリ(ビニリデンジフロライド-トリフロロエチレン共重合体)が好適である。なお、本実施形態に適用できるセンサアレイは、図10に示す構造のセンサアレイに限定されるものではない。例えば、圧力によって抵抗が変わる感圧媒体を用い、圧力がかかる素子の信号と、圧力がかからない素子のリファレンス信号を用いてもよい。あるいは他のセンサ部109を採用して、他の種類の圧力センサや、変位センサ、温度センサ等に用いてもよい。また、ドレイン配線14は、第7の実施形態に後述する電流制限回路40を有してもよい。 A suitable sensor array applicable to the signal detection circuit, drive detection circuit, and signal detection method of the present embodiment will be described. FIG. 10 is a circuit diagram showing an example of a sensor array applied to the second embodiment. In the sensor array, a pixel circuit consisting of the first thin film transistor T1 and the second thin film transistor T2 is assembled at the intersection of the matrix of N scanning wires 12 and M signal wirings 15, and the gate of the first thin film transistor T1 is formed. A pressure-sensitive medium 9, for example, is provided as a sensor unit 109 between the electrode and the common electrode 10. Further, a reference circuit by a third thin film transistor T3 and a fourth thin film transistor T4 is assembled at the intersection of N scanning wires 12 and M reference signal wirings 16, and the third thin film transistor T3 becomes the first thin film transistor T1. Adjacent. The channel length / channel width of the third thin film transistor T3 is equal to the channel length / channel width of the first thin film transistor T1, and the channel length / channel width of the fourth thin film transistor T4 is the channel length / channel of the second thin film transistor T2. Ideally equal to width. The drain wiring 14 is connected to the drain of the first thin film transistor T1, the source of the first thin film transistor T1 is connected to the drain of the second thin film transistor T2, and the gate of the second thin film transistor T2 is connected to the scanning wiring 12. The source of the second thin film transistor T2 is connected to the signal wiring 15. A voltage that depends on the stimulus (pressure, etc.) is generated in the sensor unit 109. On the other hand, the common electrode 10 is connected to the gate of the third thin film transistor T3, the drain wiring 14 is connected to the drain of the third thin film transistor T3, and the source of the third thin film transistor T3 is the drain of the fourth thin film transistor T4. Connected, the gate of the fourth thin film transistor T4 is connected to the scanning wire 12, and the source of the fourth thin film transistor T4 is connected to the reference signal wire 16. When one of the scanning wires 12 is turned on, a current that depends on the pressure of the pixels in that row flows through the signal wiring 15, and a current that has characteristics similar to those of the pixel circuit in that row and does not depend on stimuli (pressure, etc.). Flows through the reference signal wiring 16. As the sensor unit 109, a pressure sensitive medium 9, for example, polyvinylidene fluoride (PVDF) or polyvinylidene fluoride-trifluoroethylene copolymer is suitable. The sensor array applicable to this embodiment is not limited to the sensor array having the structure shown in FIG. For example, a pressure-sensitive medium whose resistance changes depending on the pressure may be used, and a signal of an element to which pressure is applied and a reference signal of an element to which pressure is not applied may be used. Alternatively, another sensor unit 109 may be adopted and used for another type of pressure sensor, displacement sensor, temperature sensor, or the like. Further, the drain wiring 14 may have a current limiting circuit 40 described later in the seventh embodiment.
 信号配線15からの検出電圧から、隣接するリファレンス信号配線16での検出電圧を差し引くことで、隣接する薄膜トランジスタの特性が似ていることにより、薄膜トランジスタアレイの面内分布をキャンセルすることができる。また、隣接する薄膜トランジスタの温度が同等であることにより、薄膜トランジスタの温度依存性の大部分をキャンセルすることができる。 By subtracting the detection voltage from the adjacent reference signal wiring 16 from the detection voltage from the signal wiring 15, the in-plane distribution of the thin film transistor array can be canceled because the characteristics of the adjacent thin film transistors are similar. Further, since the temperatures of the adjacent thin film transistors are the same, most of the temperature dependence of the thin film transistors can be canceled.
 以上のように、第2の実施形態に係る信号検出回路では、負荷抵抗20および電圧検出アンプ53の上流側に第1の切替回路101を、負荷抵抗21および電圧検出アンプ54の上流側に第3の切替回路103を設けることで、負荷抵抗20、21および電圧検出アンプ53、54の数を減らすことができ、さらに、差動増幅回路24の下流側に第2の切替回路102を設けることで、ADコンバータ25の数も減らすことができ、信号検出回路の規模を小さくすることができる。また、当該信号検出回路を適用することで、駆動検出回路の規模も小さくすることができる。また、第1の切替回路101および第3の切替回路103で信号を切り替えた後、その信号差の測定を行う前に、他のブロックの切り替え済みかつ未測定の信号差の測定を行うことで、切替信号が安定してから測定を行うことができ、誤差の小さい信号検出方法を提供することができる。 As described above, in the signal detection circuit according to the second embodiment, the first switching circuit 101 is located upstream of the load resistance 20 and the voltage detection amplifier 53, and the first switching circuit 101 is located upstream of the load resistance 21 and the voltage detection amplifier 54. By providing the switching circuit 103 of 3, the number of load resistors 20 and 21 and the voltage detection amplifiers 53 and 54 can be reduced, and further, a second switching circuit 102 is provided on the downstream side of the differential amplifier circuit 24. Therefore, the number of AD converters 25 can be reduced, and the scale of the signal detection circuit can be reduced. Further, by applying the signal detection circuit, the scale of the drive detection circuit can be reduced. Further, after the signals are switched by the first switching circuit 101 and the third switching circuit 103, the switched and unmeasured signal differences of other blocks are measured before the signal difference is measured. , The measurement can be performed after the switching signal becomes stable, and a signal detection method with a small error can be provided.
 従来のセンサアレイにおいて、抵抗が変化する感圧媒体は、劣化しやすいという問題があった。そこで、特許文献2のように電位差が変化するタイプの感圧媒体を使うことが検討されている(図28)。しかし、特許文献2のように画素内に負荷抵抗を有し電位を読み出す回路はノイズに弱いという問題があった。また、第1の薄膜トランジスタ41をソース接地回路として使っているので、薄膜トランジスタの移動度やしきい値のばらつきの影響を受けやすいという問題があった。さらに、特許文献2の感圧媒体は無機物であり、機械的衝撃に弱いという問題があった。 In the conventional sensor array, there is a problem that the pressure-sensitive medium whose resistance changes tends to deteriorate. Therefore, it has been studied to use a pressure-sensitive medium of a type in which the potential difference changes as in Patent Document 2 (FIG. 28). However, there is a problem that a circuit having a load resistance in a pixel and reading a potential as in Patent Document 2 is vulnerable to noise. Further, since the first thin film transistor 41 is used as the grounded-source circuit, there is a problem that it is easily affected by the mobility of the thin film transistor and the variation of the threshold value. Further, the pressure-sensitive medium of Patent Document 2 is an inorganic substance, and has a problem of being vulnerable to mechanical impact.
 そのため、薄膜トランジスタの移動度やしきい値のばらつきの影響が小さく、ノイズに強いセンサアレイを第3~6の実施形態で説明する。 Therefore, a sensor array that is less affected by variations in the mobility of the thin film transistor and the threshold value and is resistant to noise will be described in the third to sixth embodiments.
[第3の実施形態]
 従来の画素回路の一例を、図27に示す。図27で、センサ部である感圧媒体130は圧力によって抵抗が変化するタイプであり、一端が共通電極に、他端が薄膜トランジスタ31のドレイン電極に接続されている。共通電極には電源が接続されている。走査配線32のうち1本に薄膜トランジスタ31がオンになるゲート電圧(オン電圧)を印加し、他の走査配線32には薄膜トランジスタ31がオフになるゲート電圧(オフ電圧)を印加する。オン電圧が印加された走査配線32に属する薄膜トランジスタ31を通して、該当する画素の感圧媒体130を流れる電流が信号配線33に流れる。オンにする走査配線32を順次1本ずつ変えることで、全行の圧力データを読み出す。
[Third Embodiment]
An example of a conventional pixel circuit is shown in FIG. In FIG. 27, the pressure-sensitive medium 130, which is a sensor unit, is of a type in which the resistance changes depending on the pressure, and one end is connected to the common electrode and the other end is connected to the drain electrode of the thin film transistor 31. A power supply is connected to the common electrode. A gate voltage (on voltage) that turns on the thin film transistor 31 is applied to one of the scanning wires 32, and a gate voltage (off voltage) that turns off the thin film transistor 31 is applied to the other scanning wires 32. A current flowing through the pressure-sensitive medium 130 of the corresponding pixel flows through the signal wiring 33 through the thin film transistor 31 belonging to the scanning wiring 32 to which the on-voltage is applied. By sequentially changing the scanning wiring 32 to be turned on one by one, the pressure data of all lines is read out.
 従来の画素回路の他の例を、図28に示す。図28で、センサ部である感圧媒体140は圧力によって電位差が変化するタイプである。感圧媒体140の一端が第1の薄膜トランジスタ41のゲート電極に、他端が第1の薄膜トランジスタ41のソース電極に接続され、第1の薄膜トランジスタ41は画素内のドレイン抵抗43を介して電源に接続され、第1の薄膜トランジスタ41はソース接地回路になっている。走査配線44のうち1本に第2の薄膜トランジスタ42がオンになるゲート電圧(オン電圧)を印加し、他の走査配線44には第2の薄膜トランジスタ42がオフになるゲート電圧(オフ電圧)を印加する。そして、オン電圧が印加された走査配線44に属する第2の薄膜トランジスタ42を通して、該当する画素のドレイン電圧が信号配線45に引き出される。オンにする走査配線44を順次1本ずつ変えることで、全行の圧力データを読み出すことができる。 FIG. 28 shows another example of the conventional pixel circuit. In FIG. 28, the pressure-sensitive medium 140, which is a sensor unit, is of a type in which the potential difference changes depending on the pressure. One end of the pressure sensitive medium 140 is connected to the gate electrode of the first thin film transistor 41, the other end is connected to the source electrode of the first thin film transistor 41, and the first thin film transistor 41 is connected to the power supply via the drain resistance 43 in the pixel. The first thin film transistor 41 is a source grounded circuit. A gate voltage (on voltage) that turns on the second thin film transistor 42 is applied to one of the scanning wires 44, and a gate voltage (off voltage) that turns off the second thin film transistor 42 is applied to the other scanning wires 44. Apply. Then, the drain voltage of the corresponding pixel is drawn out to the signal wiring 45 through the second thin film transistor 42 belonging to the scanning wiring 44 to which the on-voltage is applied. By sequentially changing the scanning wiring 44 to be turned on one by one, the pressure data of all lines can be read out.
 しかし、電圧を読み出す回路は入力インピーダンスが高いので、信号配線45が長いと信号にノイズが混入しやすい。また、この回路で、仮にノイズが混入しにくいように検出回路のインピーダンスを下げると、ドレイン抵抗43に、第1の薄膜トランジスタ41を流れる(圧力に依存した)電流以外に、検出回路を流れる(必ずしも圧力に依存しない)電流が流れ、検出回路を流れる電流によるドレイン抵抗43の電圧降下分が誤差になってしまう。また、ソース接地回路は電圧・電流とも増幅するので感度は高いが、信号電圧は第1の薄膜トランジスタ41の移動度やしきい値のばらつきの影響を受け易い。 However, since the circuit that reads out the voltage has a high input impedance, if the signal wiring 45 is long, noise is likely to be mixed in the signal. Further, if the impedance of the detection circuit is lowered so that noise is less likely to be mixed in this circuit, the drain resistor 43 flows through the detection circuit (not necessarily) in addition to the current flowing through the first thin film 41 (depending on the pressure). A current (which does not depend on the pressure) flows, and the voltage drop of the drain resistor 43 due to the current flowing through the detection circuit becomes an error. Further, since the source grounded circuit amplifies both the voltage and the current, the sensitivity is high, but the signal voltage is easily affected by the mobility and the variation of the threshold value of the first thin film transistor 41.
 そこで、本開示の第3の実施形態の画素回路を図11に示す。図11で、センサ部109(例えば感圧媒体9)は刺激(圧力等)によって電位差が変化するタイプである。センサ部109の一端が共通電極10に、他端が第1の薄膜トランジスタのゲート電極G1に接続され、第1の薄膜トランジスタのドレイン電極D1はドレイン配線14を介して電源Vddに接続され、第1の薄膜トランジスタのソース電極S1は第2の薄膜トランジスタのドレイン電極D2に接続され、第2の薄膜トランジスタのゲート電極G2は走査配線12に接続され、第2の薄膜トランジスタのソース電極S2は信号配線15に接続され、信号検出回路内の負荷抵抗20を含めると、第1の薄膜トランジスタはドレイン接地回路(ソースフォロワ)になっている。走査配線12のうち1本に第2の薄膜トランジスタがオンになるゲート電圧(オン電圧)を印加し、他の走査配線12には第2の薄膜トランジスタがオフになるゲート電圧(オフ電圧)を印加する。すると、オン電圧が印加された走査配線12に属する第2の薄膜トランジスタを通して、該当する画素のソース電極S1が信号配線15に接続され、信号検出回路内の負荷抵抗20に接続される。即ち、負荷抵抗20がアレイ外にあるため、信号配線15には電流が流れるので、インピーダンスが低く、信号にノイズが混入しにくい。また、ドレイン接地(ソースフォロワ)回路なので、電流のみが増幅され、ソース電位はゲート電位に近いので、信号電圧は第1の薄膜トランジスタの移動度のばらつきの影響を受けにくい。オンにする走査配線12を順次1本ずつ変えることで、各行の圧力データを読み出すことができる。 Therefore, the pixel circuit of the third embodiment of the present disclosure is shown in FIG. In FIG. 11, the sensor unit 109 (for example, the pressure sensitive medium 9) is of a type in which the potential difference changes depending on a stimulus (pressure or the like). One end of the sensor unit 109 is connected to the common electrode 10, the other end is connected to the gate electrode G1 of the first thin film transistor, and the drain electrode D1 of the first thin film transistor is connected to the power supply Vdd via the drain wiring 14, and the first The source electrode S1 of the thin film transistor is connected to the drain electrode D2 of the second thin film transistor, the gate electrode G2 of the second thin film transistor is connected to the scanning wiring 12, and the source electrode S2 of the second thin film transistor is connected to the signal wiring 15. Including the load resistance 20 in the signal detection circuit, the first thin film transistor is a drain ground circuit (source follower). A gate voltage (on voltage) that turns on the second thin film transistor is applied to one of the scanning wires 12, and a gate voltage (off voltage) that turns off the second thin film transistor is applied to the other scanning wires 12. .. Then, the source electrode S1 of the corresponding pixel is connected to the signal wiring 15 and connected to the load resistance 20 in the signal detection circuit through the second thin film transistor belonging to the scanning wiring 12 to which the on-voltage is applied. That is, since the load resistor 20 is outside the array, a current flows through the signal wiring 15, so that the impedance is low and noise is unlikely to be mixed into the signal. Further, since it is a drain ground (source follower) circuit, only the current is amplified and the source potential is close to the gate potential, so that the signal voltage is not easily affected by the variation in mobility of the first thin film transistor. The pressure data of each line can be read out by sequentially changing the scanning wiring 12 to be turned on one by one.
 なお、共通電極10の電位は、センサ部109の刺激(圧力等)に依存する電位差に加算されて、第1の薄膜トランジスタのゲート電極G1に印加されるので、共通電極10の電位によって動作点を調整できる。 Since the potential of the common electrode 10 is added to the potential difference depending on the stimulation (pressure or the like) of the sensor unit 109 and applied to the gate electrode G1 of the first thin film, the operating point is determined by the potential of the common electrode 10. Can be adjusted.
 第3の実施形態におけるセンサアレイの検出方法は、例えば、第1の実施形態に係る信号検出回路、駆動検出回路、信号検出方法を好適に用いることができる。このとき、センサアレイの走査配線12はN本であり、信号配線15はM本である。 As the sensor array detection method in the third embodiment, for example, the signal detection circuit, the drive detection circuit, and the signal detection method according to the first embodiment can be preferably used. At this time, the number of scanning wires 12 of the sensor array is N, and the number of signal wires 15 is M.
 センサ部109としては、感圧媒体9(電位差が変化するタイプ)が好適である。ただし、センサ部109として他の感圧媒体や、感変位媒体、感温媒体等を用いることも可能である。 As the sensor unit 109, the pressure sensitive medium 9 (type in which the potential difference changes) is suitable. However, it is also possible to use another pressure-sensitive medium, a displacement-sensitive medium, a temperature-sensitive medium, or the like as the sensor unit 109.
 なお、測定を行う直前にドレイン配線14の電位を0→Vddにする場合、第1の薄膜トランジスタのゲート・ドレイン電極間容量(ゲート電極G1に接続された画素電極8、ドレイン電極D1に接続されたドレイン配線14を含む)をCgd1、画素電極8・共通電極10間容量をCpとすると、画素電極8の電位はΔVp=Vdd×Cgd1/(Cgd1+Cp)だけずれる。このずれが、センサ部109の最大電位変化量に比べて充分に小さい必要があり、例えば最大電位変化量の10%以内に抑える必要がある。上記ずれを最大電位変化量の10%以内に抑えるには、|Vdd×Cgd1/(Cgd1+Cp)|≦最大電位変化量×0.1にすればよい。ここで、最大電位変化量とは、センサに刺激(圧力等)を印加していない状態から、センサに設定された検出範囲の最大値の刺激を印加した時への、画素電極電位変化量である。例えば最大電位変化量が4[V]の場合、|Vdd×Cgd1/(Cgd1+Cp)|≦0.4とする。 When the potential of the drain wiring 14 is changed from 0 to Vdd immediately before the measurement, the capacitance between the gate and drain electrodes of the first thin film transistor (the pixel electrode 8 connected to the gate electrode G1 and the drain electrode D1 are connected). Assuming that (including the drain wiring 14) is Cgd1 and the capacitance between the pixel electrode 8 and the common electrode 10 is Cp, the potential of the pixel electrode 8 is shifted by ΔVp = Vdd × Cgd1 / (Cgd1 + Cp). This deviation needs to be sufficiently smaller than the maximum potential change amount of the sensor unit 109, and needs to be suppressed within 10% of the maximum potential change amount, for example. In order to suppress the above deviation within 10% of the maximum potential change amount, | Vdd × Cgd1 / (Cgd1 + Cp) | ≦ maximum potential change amount × 0.1 may be set. Here, the maximum potential change amount is the amount of change in the pixel electrode potential from the state in which no stimulus (pressure, etc.) is applied to the sensor to the time when the stimulus of the maximum value in the detection range set in the sensor is applied. be. For example, when the maximum potential change amount is 4 [V], | Vdd × Cgd1 / (Cgd1 + Cp) | ≦ 0.4.
 図11に示したセンサアレイの具体例を、図12に示す。絶縁基板1上に、ゲート電極G1、G2を有し(G2は走査配線12に接続され)、その上にゲート絶縁膜3を有し、その上に半導体SC1、SC2を有し、その上にソース電極S1、S2とドレイン電極D1、D2を有し(S1は接続配線17を介してD2に接続され、D1はドレイン配線14に接続され、S2は信号配線15に接続され)、その上に層間絶縁膜7を有し、その上に画素電極8を有し(画素電極8は層間絶縁膜7の開口およびゲート絶縁膜3の開口に設けられたビア配線18U、18Lを介してゲート電極G1に接続され)ている。さらにセンサ部109および共通電極10を有している。センサ部109は、画素電極8に接触または接合している。 A specific example of the sensor array shown in FIG. 11 is shown in FIG. It has gate electrodes G1 and G2 on the insulating substrate 1 (G2 is connected to the scanning wiring 12), has a gate insulating film 3 on it, has semiconductors SC1 and SC2 on it, and has semiconductors SC1 and SC2 on it. It has source electrodes S1 and S2 and drain electrodes D1 and D2 (S1 is connected to D2 via a connection wire 17, D1 is connected to a drain wire 14, and S2 is connected to a signal wire 15), on which the source electrodes S1 and S2 are provided. It has an interlayer insulating film 7 and a pixel electrode 8 on the interlayer insulating film 7 (the pixel electrode 8 has a gate electrode G1 via via wires 18U and 18L provided in the opening of the interlayer insulating film 7 and the opening of the gate insulating film 3). It is connected to the. Further, it has a sensor unit 109 and a common electrode 10. The sensor unit 109 is in contact with or bonded to the pixel electrode 8.
 半導体SC1、SC2の上には絶縁性のエッチングストッパ層を有してもよいし、半導体SC1、SC2とソース電極S1、S2の界面および半導体SC1、SC2とドレイン電極D1、D2の界面には半導体4よりも抵抗が低いコンタクト層を有してもよい。 An insulating etching stopper layer may be provided on the semiconductors SC1 and SC2, and semiconductors are provided at the interface between the semiconductors SC1 and SC2 and the source electrodes S1 and S2 and at the interface between the semiconductors SC1 and SC2 and the drain electrodes D1 and D2. It may have a contact layer having a resistance lower than 4.
 また、画素電極8が厚い場合、画素電極8のない部分には隙間があいていてもよいし、絶縁物で埋められていてもよい。 Further, when the pixel electrode 8 is thick, there may be a gap in the portion where the pixel electrode 8 is not provided, or it may be filled with an insulating material.
 なお、図12では、画素電極8が第1の薄膜トランジスタのバックゲート電極にもなっている。これにより、画素電極8が第1の薄膜トランジスタのチャネル部を覆わずにゲート電極G1に接続されているだけの場合よりも、安定した動作になる。また、図12には記載していないが、第2の薄膜トランジスタにバックゲート電極を設け、そこに共通電極電位またはGND電位または特定の一定電位を接続してもよい。これにより、第2の薄膜トランジスタの動作は、安定する。 In FIG. 12, the pixel electrode 8 is also the back gate electrode of the first thin film transistor. As a result, the operation becomes more stable than when the pixel electrode 8 is simply connected to the gate electrode G1 without covering the channel portion of the first thin film transistor. Further, although not shown in FIG. 12, a back gate electrode may be provided in the second thin film transistor, and a common electrode potential, a GND potential, or a specific constant potential may be connected thereto. As a result, the operation of the second thin film transistor becomes stable.
 絶縁基板1は、ガラスでもよいが、有機物(例えばPET(ポリエチレンテレフタレート)、PEN(ポリエチレンナフタレート)、PES(ポリエーテルスルホン)、PI(ポリイミド)、PC(ポリカーボネート)等)が好適である。ゲート電極G1、G2は、金属(例えばAl、Ti、Mo、Ta等またはこれらを主成分とする合金)が好適である。ゲート絶縁膜3は、有機物(アクリル、エポキシ等)または無機物(SiO、SiN等)またはそれらの積層または混合物が好適である。半導体SC1、SC2は、有機半導体、酸化物半導体、非晶質Siが好適である。ソース電極S1、S2、ドレイン電極D1、D2は金属(例えばAl、Ti、Mo、Ta等またはこれらを主成分とする合金)が好適である。層間絶縁膜7は有機物(アクリル、エポキシ等)または無機物(SiO、SiN等)またはそれらの積層または混合物が好適である。画素電極8は、金属(例えばAl、Ti、Mo、Ta等またはこれらを主成分とする合金)または、金属粒子と樹脂の混合物(Agペースト等)が好適である。センサ部109としては、感圧媒体9、特に有機圧電体(ポリフッ化ビニリデン、ポリフッ化ビニリデン・3フッ化エチレン共重合体、ポリ乳酸、多孔性エレクトレット型等)が好適であるが、感変位媒体や感温媒体でもよい。共通電極10は、金属(例えばAl、Ti、Mo、Ta等またはこれらを主成分とする合金)が好適である。 The insulating substrate 1 may be glass, but organic substances (for example, PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PES (polyether sulfone), PI (polyimide), PC (polycarbonate), etc.) are suitable. As the gate electrodes G1 and G2, metals (for example, Al, Ti, Mo, Ta, etc. or alloys containing these as main components) are suitable. The gate insulating film 3 is preferably an organic substance (acrylic, epoxy, etc.) or an inorganic substance (SiO 2 , SiN, etc.) or a laminate or mixture thereof. The semiconductors SC1 and SC2 are preferably organic semiconductors, oxide semiconductors, and amorphous Si. The source electrodes S1 and S2 and the drain electrodes D1 and D2 are preferably made of metal (for example, Al, Ti, Mo, Ta or the like or an alloy containing these as main components). The interlayer insulating film 7 is preferably an organic substance (acrylic, epoxy, etc.) or an inorganic substance (SiO 2 , SiN, etc.) or a laminate or mixture thereof. The pixel electrode 8 is preferably made of a metal (for example, Al, Ti, Mo, Ta or the like or an alloy containing these as a main component) or a mixture of metal particles and a resin (Ag paste or the like). As the sensor unit 109, a pressure-sensitive medium 9, particularly an organic piezoelectric material (polyvinylidene fluoride, polyvinylidene fluoride / ethylene trifluoride copolymer, polylactic acid, porous electret type, etc.) is suitable, but it is a displacement-sensitive medium. Or a temperature sensitive medium. The common electrode 10 is preferably a metal (for example, Al, Ti, Mo, Ta, etc. or an alloy containing these as a main component).
 ただし、センサアレイはフレキシブル性が望まれる場合が多く、フレキシブル性を確保するために絶縁基板1・ゲート絶縁膜3・層間絶縁膜7・センサ部109(感圧媒体9等)は有機物が主成分であることが特に望ましい。 However, flexibility is often desired for the sensor array, and in order to ensure flexibility, the main components of the insulating substrate 1, the gate insulating film 3, the interlayer insulating film 7, and the sensor unit 109 (pressure sensitive medium 9, etc.) are organic substances. Is particularly desirable.
 また、画素電極8が金属ならば画素電極8を薄くすることが容易であり、画素電極8以外の部分の層間絶縁膜7とセンサ部109(感圧媒体9等)との隙間をなくすことができ、測定の均一性を向上できる。画素電極8が金属粒子と樹脂の混合物ならば画素電極8を厚くすることが容易であり、画素電極8以外の部分の層間絶縁膜7とセンサ部109(感圧媒体9等)との隙間を大きくすることができ、より小さい力で所定圧力が得られる、即ち感度を上げることができる。 Further, if the pixel electrode 8 is made of metal, it is easy to make the pixel electrode 8 thin, and it is possible to eliminate the gap between the interlayer insulating film 7 and the sensor unit 109 (pressure sensitive medium 9 or the like) other than the pixel electrode 8. It can improve the uniformity of measurement. If the pixel electrode 8 is a mixture of metal particles and resin, it is easy to thicken the pixel electrode 8, and a gap between the interlayer insulating film 7 and the sensor portion 109 (pressure sensitive medium 9 or the like) other than the pixel electrode 8 can be formed. It can be increased and a predetermined pressure can be obtained with a smaller force, that is, the sensitivity can be increased.
 図12はボトムゲート・トップコンタクトの場合を示すが、本開示はこれに限定されず、トップゲートやボトムコンタクトでもよい。 FIG. 12 shows the case of bottom gate and top contact, but the present disclosure is not limited to this, and top gate and bottom contact may be used.
[第4の実施形態]
 本開示の第4の実施形態の画素回路を図13に示す。図13では、図11の画素回路にさらに第3の薄膜トランジスタを有し、第3の薄膜トランジスタのドレイン電極D3は画素電極8に接続され、ソース電極S3は共通配線11に接続され、ゲート電極G3はリセット配線13に接続されている。
[Fourth Embodiment]
The pixel circuit of the fourth embodiment of the present disclosure is shown in FIG. In FIG. 13, a third thin film transistor is further provided in the pixel circuit of FIG. 11, the drain electrode D3 of the third thin film transistor is connected to the pixel electrode 8, the source electrode S3 is connected to the common wiring 11, and the gate electrode G3 is It is connected to the reset wiring 13.
 測定を行う前に、センサ部109に刺激(圧力等)が印加されていない状態で、リセット配線13に第3の薄膜トランジスタがオンになる電圧(オン電圧)を印加する。すると画素電極8が第3の薄膜トランジスタを介して共通配線11に接続され、画素電極8に蓄積されていた電荷を0にできる。ここで、共通配線11は共通電極10と同電位である。そして、リセット配線13に第3の薄膜トランジスタがオフになる電圧(オフ電圧)を印加し、かつドレイン配線14に電圧Vddを印加する。 Before performing the measurement, a voltage (on voltage) for turning on the third thin film transistor is applied to the reset wiring 13 in a state where no stimulus (pressure or the like) is applied to the sensor unit 109. Then, the pixel electrode 8 is connected to the common wiring 11 via the third thin film transistor, and the electric charge accumulated in the pixel electrode 8 can be reduced to zero. Here, the common wiring 11 has the same potential as the common electrode 10. Then, a voltage (off voltage) for turning off the third thin film transistor is applied to the reset wiring 13, and a voltage Vdd is applied to the drain wiring 14.
 圧電素子のように圧力によって電位差が変化するタイプのセンサ部109は、定常では刺激(圧力等)が0の時に電位差は0であるが、過去の履歴によっては、例えば使用する直前まで刺激(圧力等)がかかり続けていた場合等には、刺激(圧力等)が0であっても電位差が0でないといった、センサ部109の残留電荷に起因する誤差が生じる。本実施形態に係るセンサアレイは、測定の直前に、第3の薄膜トランジスタをオンにして画素電極8の電荷をリセットできるので、センサ部109の残留電荷に起因する誤差をなくすことができる。 The sensor unit 109, which changes the potential difference depending on the pressure like a piezoelectric element, has a potential difference of 0 when the stimulus (pressure, etc.) is 0 in a steady state, but depending on the past history, for example, the stimulus (pressure) until just before use. Etc.), an error due to the residual charge of the sensor unit 109 occurs, such that the potential difference is not 0 even if the stimulus (pressure or the like) is 0. In the sensor array according to the present embodiment, since the charge of the pixel electrode 8 can be reset by turning on the third thin film transistor immediately before the measurement, it is possible to eliminate the error caused by the residual charge of the sensor unit 109.
 第1の薄膜トランジスタのゲート・ドレイン電極間容量(ゲート電極G1に接続された
画素電極8、ドレイン電極D1に接続されたドレイン配線14を含む)をCgd1、第3の薄膜トランジスタのゲート・ドレイン間容量(ゲート電極G3に接続されたリセット配線13、ドレイン電極D3に接続された画素電極8の容量を含む)をCgd3、画素電極8・共通電極10間容量をCpとし、他の寄生容量は小さいので無視する。リセット配線13にオフ電圧を印加して第3の薄膜トランジスタをオフにする時、画素電極8の電位はΔVp=-{Vreset(on)-Vreset(off)}×Cgd3/(Cgd3+Cp+Cgd1)だけずれる。また、ドレイン配線14の電位を0→Vddにする時、画素電極8の電位はΔVp=Vdd×Cgd1/(Cgd1+Cp+Cgd3)だけずれる。nチャネルTFTの場合、前者は負、後者は正であり、pチャネルTFTの場合、前者は正、後者は負であり、いずれの場合も互いの電圧変化を打ち消す効果がある。また、この電圧変化が、感圧媒体9の最大電位変化量に比べて充分に小さい必要があり、例えば最大電位変化量の10%以内に抑える必要がある。上記電圧変化を最大電位変化量の10%以内に抑えるには、|Vdd×Cgd1/(Cgd1+Cp+Cgd3)-{Vreset(on)-Vreset(off)}×Cgd3/(Cgd3+Cp+Cgd1)|≦最大電位変化量×0.1にすればよい。ここで、最大電位変化量とは、圧力センサに圧力を印加していない状態から、圧力センサに設定された圧力検出範囲の最大値の圧力を印加した時への、画素電極電位変化量である。例えば最大電位変化量が4[V]の場合、|Vdd×Cgd1/(Cgd1+Cp+Cgd3)-{Vreset(on)-Vreset(off)}×Cgd3/(Cgd3+Cp+Cgd1)|≦0.4とする。
The gate-drain electrode capacitance of the first thin film transistor (including the pixel electrode 8 connected to the gate electrode G1 and the drain wiring 14 connected to the drain electrode D1) is Cgd1, and the gate-drain capacitance of the third thin film transistor (including the gate-drain capacitance). The reset wiring 13 connected to the gate electrode G3 and the capacitance of the pixel electrode 8 connected to the drain electrode D3 are set to Cgd3, and the capacitance between the pixel electrode 8 and the common electrode 10 is set to Cp. do. When an off voltage is applied to the reset wiring 13 to turn off the third thin film transistor, the potential of the pixel electrode 8 shifts by ΔVp = − {Vreset (on) -Vreset (off)} × Cgd3 / (Cgd3 + Cp + Cgd1). Further, when the potential of the drain wiring 14 is changed from 0 to Vdd, the potential of the pixel electrode 8 is deviated by ΔVp = Vdd × Cgd1 / (Cgd1 + Cp + Cgd3). In the case of an n-channel TFT, the former is negative and the latter is positive, and in the case of a p-channel TFT, the former is positive and the latter is negative, and in each case, there is an effect of canceling each other's voltage changes. Further, this voltage change needs to be sufficiently smaller than the maximum potential change amount of the pressure sensitive medium 9, and needs to be suppressed within 10% of the maximum potential change amount, for example. In order to suppress the above voltage change within 10% of the maximum potential change amount, | Vdd × Cgd1 / (Cgd1 + Cp + Cgd3)-{Vreset (on) -Vreset (off)} × Cgd3 / (Cgd3 + Cp + Cgd1) | ≦ Maximum potential change amount × It may be 0.1. Here, the maximum potential change amount is the pixel electrode potential change amount when the pressure of the maximum value in the pressure detection range set in the pressure sensor is applied from the state where the pressure is not applied to the pressure sensor. .. For example, when the maximum potential change amount is 4 [V], | Vdd × Cgd1 / (Cgd1 + Cp + Cgd3)-{Vreset (on) -Vreset (off)} × Cgd3 / (Cgd3 + Cp + Cgd1) | ≦ 0.4.
 測定の方法は、第3の実施形態と同様であり、第3の実施形態におけるセンサアレイの検出方法は、例えば、第1の実施形態に係る信号検出回路、駆動検出回路、信号検出方法を好適に用いることができる。 The measurement method is the same as that of the third embodiment, and the sensor array detection method in the third embodiment preferably includes, for example, the signal detection circuit, the drive detection circuit, and the signal detection method according to the first embodiment. Can be used for.
 図13の具体例を、図14に示す。絶縁基板1上に、ゲート電極G1、G2、G3を有し(G2は走査配線12に接続され、G3はリセット配線13に接続され)、その上にゲート絶縁膜3を有し、その上に半導体SC1、SC2、SC3を有し、その上にソース電極S1、S2、S3とドレイン電極D1、D2、D3を有し(S1は接続配線17を介してD2に接続され、D3はゲート絶縁膜3の開口に設けられたビア配線18Lを介してゲート電極G1に接続され、D1はドレイン配線14に接続され、S2は信号配線15に接続され、S3は共通配線11に接続され)、その上に層間絶縁膜7を有し、その上に画素電極8を有し(画素電極8は層間絶縁膜7の開口に設けられたビア配線18Uを介してドレイン電極D3と接続され)ている。さらにセンサ部109(例えば感圧媒体9)および共通電極10を有している。センサ部109は、画素電極8に接触または接合している。 A specific example of FIG. 13 is shown in FIG. It has gate electrodes G1, G2, and G3 on the insulating substrate 1 (G2 is connected to the scanning wiring 12 and G3 is connected to the reset wiring 13), has a gate insulating film 3 on it, and has a gate insulating film 3 on it. It has semiconductors SC1, SC2, SC3, and has source electrodes S1, S2, S3 and drain electrodes D1, D2, D3 on it (S1 is connected to D2 via a connection wiring 17, and D3 is a gate insulating film. It is connected to the gate electrode G1 via the via wiring 18L provided in the opening of 3, D1 is connected to the drain wiring 14, S2 is connected to the signal wiring 15, S3 is connected to the common wiring 11), and above. It has an interlayer insulating film 7 and a pixel electrode 8 on the interlayer insulating film 7 (the pixel electrode 8 is connected to the drain electrode D3 via a via wiring 18U provided in the opening of the interlayer insulating film 7). Further, it has a sensor unit 109 (for example, a pressure sensitive medium 9) and a common electrode 10. The sensor unit 109 is in contact with or bonded to the pixel electrode 8.
 半導体SC1、SC2、SC3の上には絶縁性のエッチングストッパ層を有してもよいし、半導体SC1、SC2、SC3とソース電極S1、S2、S3の界面および半導体SC1、SC2、SC3とドレイン電極D1、D2、D3の界面には半導体SC1、SC2、SC3よりも抵抗が低いコンタクト層を有してもよい。 An insulating etching stopper layer may be provided on the semiconductors SC1, SC2, and SC3, the interface between the semiconductors SC1, SC2, and SC3 and the source electrodes S1, S2, and S3, and the semiconductors SC1, SC2, SC3 and the drain electrode. A contact layer having a lower resistance than the semiconductors SC1, SC2, and SC3 may be provided at the interface between D1, D2, and D3.
 また、画素電極8が厚い場合、画素電極8のない部分には隙間があいていてもよいし、絶縁物で埋められていてもよい。 Further, when the pixel electrode 8 is thick, there may be a gap in the portion where the pixel electrode 8 is not provided, or it may be filled with an insulating material.
 なお、図14では、画素電極8が第1の薄膜トランジスタのバックゲート電極にもなっている。これにより、画素電極8が第1の薄膜トランジスタのチャネル部を覆わずにゲート電極G1に接続されているだけの場合よりも、安定した動作になる。また、図14には記載していないが、第2の薄膜トランジスタにバックゲート電極を設け、そこに共通電極電位またはGND電位または特定の一定電位を接続してもよい。これにより、第2の薄膜トランジスタの動作は、安定する。同様に、第3の薄膜トランジスタにバックゲート電極を設け、そこに画素電極電位または共通電極電位またはGND電位または特定の一定電位を接続してもよい。これにより、第3の薄膜トランジスタの動作は、安定する。 In FIG. 14, the pixel electrode 8 is also the back gate electrode of the first thin film transistor. As a result, the operation becomes more stable than when the pixel electrode 8 is simply connected to the gate electrode G1 without covering the channel portion of the first thin film transistor. Further, although not shown in FIG. 14, a back gate electrode may be provided in the second thin film transistor, and a common electrode potential, a GND potential, or a specific constant potential may be connected thereto. As a result, the operation of the second thin film transistor becomes stable. Similarly, a back gate electrode may be provided on the third thin film transistor, and a pixel electrode potential, a common electrode potential, a GND potential, or a specific constant potential may be connected thereto. As a result, the operation of the third thin film transistor becomes stable.
 各構成要素の材質は、第3の実施形態と同様である。 The material of each component is the same as that of the third embodiment.
 図14はボトムゲート・トップコンタクトの場合を示すが、本開示はこれに限定されず、トップゲートやボトムコンタクトでもよい。 FIG. 14 shows the case of bottom gate and top contact, but the present disclosure is not limited to this, and top gate and bottom contact may be used.
[第5の実施形態]
 本開示の第5の実施形態の画素回路を図15に示す。図15で、センサ部109(例えば感圧媒体9)は刺激(圧力等)によって電位差が変化するタイプである。センサ部109の一端が共通電極10に、他端が第1の薄膜トランジスタのゲート電極G1に接続され、第1の薄膜トランジスタのドレイン電極D1はドレイン配線14を介して電源Vddに接続され、第1の薄膜トランジスタのソース電極S1は第2の薄膜トランジスタのドレイン電極D2に接続され、第2の薄膜トランジスタのゲート電極G2は走査配線12に接続され、第2の薄膜トランジスタのソース電極S2は信号配線15に接続され、後述する検出回路内の負荷抵抗20を含めると、第1の薄膜トランジスタはドレイン接地回路(ソースフォロワ)になっている。負荷抵抗20がアレイ外にあるため、信号配線15には電流が流れるので、インピーダンスが低く、ノイズが混入しにくい。また、ドレイン接地(ソースフォロワ)回路なので電流のみが増幅され、電圧はほぼ不変なので、第1の薄膜トランジスタの移動度やしきい値のばらつきの影響を受けにくい。
[Fifth Embodiment]
The pixel circuit of the fifth embodiment of the present disclosure is shown in FIG. In FIG. 15, the sensor unit 109 (for example, the pressure sensitive medium 9) is of a type in which the potential difference changes depending on a stimulus (pressure or the like). One end of the sensor unit 109 is connected to the common electrode 10, the other end is connected to the gate electrode G1 of the first thin film transistor, and the drain electrode D1 of the first thin film transistor is connected to the power supply Vdd via the drain wiring 14, and the first The source electrode S1 of the thin film transistor is connected to the drain electrode D2 of the second thin film transistor, the gate electrode G2 of the second thin film transistor is connected to the scanning wiring 12, and the source electrode S2 of the second thin film transistor is connected to the signal wiring 15. Including the load resistance 20 in the detection circuit described later, the first thin film transistor is a drain ground circuit (source follower). Since the load resistor 20 is outside the array, a current flows through the signal wiring 15, so the impedance is low and noise is less likely to be mixed. Further, since it is a drain ground (source follower) circuit, only the current is amplified and the voltage is almost unchanged, so that it is not easily affected by the mobility and the variation of the threshold value of the first thin film transistor.
 また、共通配線11が第4の薄膜トランジスタのゲート電極G4に接続され、第4の薄膜トランジスタのドレイン電極D4はドレイン配線14を介して電源Vddに接続され、第4の薄膜トランジスタのソース電極S4は第5の薄膜トランジスタのドレイン電極D5に接続され、第5の薄膜トランジスタのゲート電極G5は走査配線12に接続され、第5の薄膜トランジスタのソース電極S5はリファレンス信号配線16に接続され、信号検出回路内の負荷抵抗20を含めると、第4の薄膜トランジスタはドレイン接地回路(ソースフォロワ)になっている。 Further, the common wiring 11 is connected to the gate electrode G4 of the fourth thin film transistor, the drain electrode D4 of the fourth thin film transistor is connected to the power supply Vdd via the drain wiring 14, and the source electrode S4 of the fourth thin film transistor is the fifth. The thin film transistor drain electrode D5 of the thin film transistor, the gate electrode G5 of the fifth thin film transistor is connected to the scanning wiring 12, the source electrode S5 of the fifth thin film transistor is connected to the reference signal wiring 16, and the load resistance in the signal detection circuit. Including 20, the fourth thin film transistor is a drain ground circuit (source follower).
 センサ部109および第1~第2の薄膜トランジスタからなる信号回路と、第4~第5の薄膜トランジスタからなるリファレンス回路との差を見ることにより、第1の薄膜トランジスタの移動度ばらつきやしきい値変化を第4の薄膜トランジスタの移動度ばらつきやしきい値変化でキャンセルし、かつ第2の薄膜トランジスタの移動度ばらつきや移動度変化を第5の薄膜トランジスタの移動度ばらつきやしきい値変化でキャンセルすることができる。なぜなら、ばらつきや特性変化は面内分布の影響が大きいので、同一画素内に形成された薄膜トランジスタのばらつきや特性変化が似ているからである。特に、第1の薄膜トランジスタの形状(チャネル幅とチャネル長)と第4の薄膜トランジスタの形状(チャネル幅とチャネル長)を等しくし、第2の薄膜トランジスタの形状(チャネル幅とチャネル長)と第5の薄膜トランジスタの形状(チャネル幅とチャネル長)を等しくするとよい。 By observing the difference between the signal circuit composed of the sensor unit 109 and the first to second thin film transistors and the reference circuit composed of the fourth to fifth thin film transistors, the mobility variation and the threshold value change of the first thin film transistor can be determined. It is possible to cancel by the mobility variation or the threshold value change of the fourth thin film transistor, and to cancel the mobility variation or the mobility change of the second thin film transistor by the mobility variation or the threshold value change of the fifth thin film transistor. .. This is because the variation and characteristic change are greatly affected by the in-plane distribution, and therefore the variation and characteristic change of the thin film transistors formed in the same pixel are similar. In particular, the shape of the first thin film transistor (channel width and channel length) and the shape of the fourth thin film transistor (channel width and channel length) are made equal, and the shape of the second thin film transistor (channel width and channel length) and the fifth thin film transistor are made equal to each other. The shapes of the thin film transistors (channel width and channel length) should be equal.
 第5の実施形態におけるセンサアレイの検出方法は、例えば、第2の実施形態に係る信号検出回路、駆動検出回路、信号検出方法を好適に用いることができる。このとき、センサアレイの走査配線12はN本であり、信号配線15はM本である。 As the sensor array detection method in the fifth embodiment, for example, the signal detection circuit, the drive detection circuit, and the signal detection method according to the second embodiment can be preferably used. At this time, the number of scanning wires 12 of the sensor array is N, and the number of signal wires 15 is M.
 センサ部109としては、感圧媒体9(電位差が変化するタイプ)が好適である。ただし、センサ部109として他の感圧媒体や、感変位媒体、感温媒体等を用いることも可能である。 As the sensor unit 109, the pressure sensitive medium 9 (type in which the potential difference changes) is suitable. However, it is also possible to use another pressure-sensitive medium, a displacement-sensitive medium, a temperature-sensitive medium, or the like as the sensor unit 109.
 なお、測定を行う直前にドレイン配線14の電位を0→Vddにする場合、画素電極8の電位ずれを|Vdd×Cgd1/(Cgd1+Cp)|≦最大電位変化量×0.1にすればよいことは、第3の実施形態と同様である。 When the potential of the drain wiring 14 is changed from 0 to Vdd immediately before the measurement, the potential deviation of the pixel electrode 8 may be set to | Vdd × Cgd1 / (Cgd1 + Cp) | ≦ maximum potential change amount × 0.1. Is the same as in the third embodiment.
 図15の具体例を、図16に示す。絶縁基板1上に、ゲート電極G1、G2、G4、G5を有し(G2とG5は走査配線12に接続され)、その上にゲート絶縁膜3を有し、その上に半導体SC1、SC2、SC4、SC5を有し、その上にソース電極S1、S2、S4、S5とドレイン電極D1、D2、D4、D5を有し(S1は接続配線17を介してD2に接続され、S4は接続配線17を介してD5に接続され、D1とD4はドレイン配線14に接続され、S2は信号配線15に接続され、S5はリファレンス信号配線16に接続され)、その上に層間絶縁膜7を有し、その上に画素電極8と共通配線11を有し(画素電極8は層間絶縁膜7の開口およびゲート絶縁膜3の開口に設けられたビア配線18U、18Lを介してゲート電極G1に接続され、共通配線11は層間絶縁膜7の開口およびゲート絶縁膜3の開口に設けられたビア配線18U、18Lを介してゲート電極G4に接続され)ている。さらにセンサ部109(例えば感圧媒体9)および共通電極10を有している。センサ部109は、画素電極8に接触または接合している。 A specific example of FIG. 15 is shown in FIG. It has gate electrodes G1, G2, G4, and G5 on the insulating substrate 1 (G2 and G5 are connected to the scanning wiring 12), has a gate insulating film 3 on it, and semiconductors SC1, SC2, on the gate insulating film 3. It has SC4 and SC5, and has source electrodes S1, S2, S4, S5 and drain electrodes D1, D2, D4, D5 on it (S1 is connected to D2 via a connection wiring 17, and S4 is a connection wiring. It is connected to D5 via 17, D1 and D4 are connected to the drain wiring 14, S2 is connected to the signal wiring 15, S5 is connected to the reference signal wiring 16), and has an interlayer insulating film 7 on it. A pixel electrode 8 and a common wiring 11 are provided on the pixel electrode 8 (the pixel electrode 8 is connected to the gate electrode G1 via via wires 18U and 18L provided in the opening of the interlayer insulating film 7 and the opening of the gate insulating film 3). The common wiring 11 is connected to the gate electrode G4 via via wirings 18U and 18L provided in the opening of the interlayer insulating film 7 and the opening of the gate insulating film 3). Further, it has a sensor unit 109 (for example, a pressure sensitive medium 9) and a common electrode 10. The sensor unit 109 is in contact with or bonded to the pixel electrode 8.
 半導体SC1、SC2、SC4、SC5の上には絶縁性のエッチングストッパ層を有してもよいし、半導体SC1、SC2、SC4、SC5とソース電極S1、S2、S4、S5の界面および半導体SC1、SC2、SC4、SC5とドレイン電極D1、D2、D4、D5の界面には半導体SC1、SC2、SC4、SC5よりも抵抗が低いコンタクト層を有してもよい。 An insulating etching stopper layer may be provided on the semiconductors SC1, SC2, SC4, and SC5, or the interface between the semiconductors SC1, SC2, SC4, SC5 and the source electrodes S1, S2, S4, S5 and the semiconductor SC1, A contact layer having a lower resistance than the semiconductors SC1, SC2, SC4, and SC5 may be provided at the interface between the SC2, SC4, and SC5 and the drain electrodes D1, D2, D4, and D5.
 また、画素電極8が厚い場合、画素電極8のない部分には隙間があいていてもよいし、絶縁物で埋められていてもよい。共通配線11はセンサ部109に接触していてもよいし、接触していなくてもよい。 Further, when the pixel electrode 8 is thick, there may be a gap in the portion where the pixel electrode 8 is not provided, or it may be filled with an insulating material. The common wiring 11 may or may not be in contact with the sensor unit 109.
 なお、図16では、画素電極8が第1の薄膜トランジスタのバックゲート電極になっており、共通配線11が第4の薄膜トランジスタのバックゲート電極になっている。これにより、画素電極8が第1の薄膜トランジスタのチャネル部を覆わずにゲート電極G1に接続されているだけの場合や、共通配線11が第4の薄膜トランジスタのチャネル部を覆わずにゲート電極G4に接続されているだけの場合よりも、安定した動作になる。また、図16には記載していないが、第2の薄膜トランジスタにバックゲート電極を設け、そこに画素電極電位または共通電極電位またはGND電位または特定の一定電位を接続してもよい。これにより、第2の薄膜トランジスタの動作は、安定する。同様に、第5の薄膜トランジスタにバックゲート電極を設け、そこに共通電極電位またはGND電位または特定の一定電位を接続してもよい。これにより、第5の薄膜トランジスタの動作は、安定する。 In FIG. 16, the pixel electrode 8 is the back gate electrode of the first thin film transistor, and the common wiring 11 is the back gate electrode of the fourth thin film transistor. As a result, the pixel electrode 8 is only connected to the gate electrode G1 without covering the channel portion of the first thin film transistor, or the common wiring 11 is connected to the gate electrode G4 without covering the channel portion of the fourth thin film transistor. The operation is more stable than when it is just connected. Further, although not shown in FIG. 16, a back gate electrode may be provided in the second thin film transistor, and a pixel electrode potential, a common electrode potential, a GND potential, or a specific constant potential may be connected thereto. As a result, the operation of the second thin film transistor becomes stable. Similarly, a back gate electrode may be provided on the fifth thin film transistor, and a common electrode potential, a GND potential, or a specific constant potential may be connected thereto. As a result, the operation of the fifth thin film transistor becomes stable.
 各構成要素の材質は、第3の実施形態と同様である。 The material of each component is the same as that of the third embodiment.
 図16はボトムゲート・トップコンタクトの場合を示すが、本開示はこれに限定されず、トップゲートやボトムコンタクトでもよい。 FIG. 16 shows the case of bottom gate and top contact, but the present disclosure is not limited to this, and top gate and bottom contact may be used.
[第6の実施形態]
 本開示の第6の実施形態の画素回路を図17に示す。図17では、図15の画素回路にさらに第3の薄膜トランジスタを有し、第3の薄膜トランジスタのドレイン電極D3は画素電極8に接続され、ソース電極S3は共通配線11に接続され、ゲート電極G3はリセット配線13に接続されている。
[Sixth Embodiment]
The pixel circuit of the sixth embodiment of the present disclosure is shown in FIG. In FIG. 17, a third thin film transistor is further provided in the pixel circuit of FIG. 15, the drain electrode D3 of the third thin film transistor is connected to the pixel electrode 8, the source electrode S3 is connected to the common wiring 11, and the gate electrode G3 is It is connected to the reset wiring 13.
 圧力測定を行う前に、センサ部109に刺激(圧力等)が印加されていない状態で、リセット配線13に第3の薄膜トランジスタがオンになる電圧(オン電圧)を印加する。すると画素電極8が第3の薄膜トランジスタを介して共通配線11に接続され、画素電極8に蓄積されていた電荷を0にできる。そして、リセット配線13に第3の薄膜トランジスタがオフになる電圧(オフ電圧)を印加し、かつドレイン配線14に電源Vddを印加する。 Before measuring the pressure, a voltage (on voltage) for turning on the third thin film is applied to the reset wiring 13 in a state where no stimulus (pressure or the like) is applied to the sensor unit 109. Then, the pixel electrode 8 is connected to the common wiring 11 via the third thin film transistor, and the electric charge accumulated in the pixel electrode 8 can be reduced to zero. Then, a voltage (off voltage) for turning off the third thin film transistor is applied to the reset wiring 13, and a power supply Vdd is applied to the drain wiring 14.
 なお、リセット配線13にオフ電圧を印加して第3の薄膜トランジスタをオフにする時、画素電極8の電位はΔVp=(Vreset(off)-Vreset(on))×Cgd3/(Cgd3+Cp+Cgd1)だけずれ、ドレイン配線14の電位を0→Vddにする時、画素電極8の電位はΔVp=Vdd×Cgd1/(Cgd1+Cp+Cgd3)だけずれ、両者が打ち消しあう効果があることは、第2の実施形態と同様である。第2の実施形態と同様に、|Vdd×Cgd1/(Cgd1+Cp+Cgd3)-{Vreset(on)-Vreset(off)}×Cgd3/(Cgd3+Cp+Cgd1)|≦最大電位変化量×0.1であればよい。 When an off voltage is applied to the reset wiring 13 to turn off the third thin film transistor, the potential of the pixel electrode 8 shifts by ΔVp = (Vreset (off) -Vreset (on)) × Cgd3 / (Cgd3 + Cp + Cgd1). When the potential of the drain wiring 14 is changed from 0 to Vdd, the potential of the pixel electrode 8 deviates by ΔVp = Vdd × Cgd1 / (Cgd1 + Cp + Cgd3), and both have the effect of canceling each other, as in the second embodiment. .. Similar to the second embodiment, | Vdd × Cgd1 / (Cgd1 + Cp + Cgd3)-{Vreset (on) -Vreset (off)} × Cgd3 / (Cgd3 + Cp + Cgd1) | ≦ Maximum potential change amount × 0.1.
 測定の方法は、第5の実施形態と同様であり、第6の実施形態におけるセンサアレイの検出方法は、例えば、第2の実施形態に係る信号検出回路、駆動検出回路、信号検出方法を好適に用いることができる。 The measurement method is the same as that of the fifth embodiment, and the sensor array detection method in the sixth embodiment preferably includes, for example, the signal detection circuit, the drive detection circuit, and the signal detection method according to the second embodiment. Can be used for.
 図17の具体例を、図18に示す。絶縁基板1上に、ゲート電極G1、G2、G3、G4、G5を有し(G2とG5は走査配線12に接続され、G3はリセット配線13に接続され)、その上にゲート絶縁膜3を有し、その上に半導体SC1、SC2、SC3、SC4、SC5を有し、その上にソース電極S1、S2、S3、S4、S5とドレイン電極D1、D2、D3、D4、D5を有し(S1は接続配線17を介してD2に接続され、D3はゲート絶縁膜3の開口に設けられたビア配線18Lを介してゲート電極G1に接続され、S4は接続配線17を介してD5に接続され、D1とD4はドレイン配線14に接続され、S2は信号配線15に接続され、S5はリファレンス信号配線16に接続され、S3は共通配線11に接続され)、その上に層間絶縁膜7を有し、その上に画素電極8および共通配線11を有し(画素電極8は層間絶縁膜7の開口に設けられたビア配線18Uを介してドレイン電極D3に接続され、共通配線11は層間絶縁膜7およびゲート絶縁膜3の開口に設けられたビア配線18U、18Lを介してゲート電極G4に接続され)ている。さらにセンサ部109(例えば感圧媒体9)および共通電極10を有している。センサ部109は、画素電極8に接触または接合している。 A specific example of FIG. 17 is shown in FIG. The gate electrodes G1, G2, G3, G4, and G5 are provided on the insulating substrate 1 (G2 and G5 are connected to the scanning wiring 12 and G3 is connected to the reset wiring 13), and the gate insulating film 3 is placed on the gate electrodes G1 and G2, G3, G4, and G5. It has semiconductors SC1, SC2, SC3, SC4, SC5 on it, and has source electrodes S1, S2, S3, S4, S5 and drain electrodes D1, D2, D3, D4, D5 on it ( S1 is connected to D2 via the connecting wiring 17, D3 is connected to the gate electrode G1 via the via wiring 18L provided in the opening of the gate insulating film 3, and S4 is connected to D5 via the connecting wiring 17. , D1 and D4 are connected to the drain wiring 14, S2 is connected to the signal wiring 15, S5 is connected to the reference signal wiring 16, S3 is connected to the common wiring 11), and the interlayer insulating film 7 is provided therein. A pixel electrode 8 and a common wiring 11 are provided on the pixel electrode 8 (the pixel electrode 8 is connected to the drain electrode D3 via a via wiring 18U provided in the opening of the interlayer insulating film 7, and the common wiring 11 is an interlayer insulating film. It is connected to the gate electrode G4 via via wires 18U and 18L provided in the openings of the gate 7 and the gate insulating film 3.). Further, it has a sensor unit 109 (for example, a pressure sensitive medium 9) and a common electrode 10. The sensor unit 109 is in contact with or bonded to the pixel electrode 8.
 半導体SC1、SC2、SC3、SC4、SC5の上には絶縁性のエッチングストッパ層を有してもよいし、半導体SC1、SC2、SC3、SC4、SC5とソース電極S1、S2、S3、S4、S5の界面および半導体SC1、SC2、SC3、SC4、SC5とドレイン電極D1、D2、D3、D4、D5の界面には半導体SC1、SC2、SC3、SC4、SC5よりも抵抗が低いコンタクト層を有してもよい。 An insulating etching stopper layer may be provided on the semiconductors SC1, SC2, SC3, SC4, and SC5, or the semiconductors SC1, SC2, SC3, SC4, SC5 and the source electrodes S1, S2, S3, S4, and S5. And the interface between the semiconductors SC1, SC2, SC3, SC4, SC5 and the drain electrodes D1, D2, D3, D4, D5 have a contact layer with lower resistance than the semiconductors SC1, SC2, SC3, SC4, SC5. May be good.
 また、画素電極8が厚い場合、画素電極8のない部分には隙間があいていてもよいし、絶縁物で埋められていてもよい。共通配線11はセンサ部109に接触していてもよいし、接触していなくてもよい。 Further, when the pixel electrode 8 is thick, there may be a gap in the portion where the pixel electrode 8 is not provided, or it may be filled with an insulating material. The common wiring 11 may or may not be in contact with the sensor unit 109.
 各構成要素の材質は、第3の実施形態と同様である。 The material of each component is the same as that of the third embodiment.
 なお、図18では、画素電極8が第1の薄膜トランジスタのバックゲート電極になっており、共通配線11が第4の薄膜トランジスタのバックゲート電極になっている。これにより、画素電極8が第1の薄膜トランジスタのチャネル部を覆わずにゲート電極G1に接続されているだけの場合や、共通配線11が第4の薄膜トランジスタのチャネル部を覆わずにゲート電極G4に接続されているだけの場合よりも、安定した動作になる。また、図12には記載していないが、第2の薄膜トランジスタにバックゲート電極を設け、そこに画素電極電位または共通電極電位またはGND電位または特定の一定電位を接続してもよい。これにより、第2の薄膜トランジスタの動作は、安定する。同様に、第3の薄膜トランジスタにバックゲート電極を設け、そこに画素電極電位または共通電極電位またはGND電位または特定の一定電位を接続してもよい。これにより、第3の薄膜トランジスタの動作は、安定する。同様に、第5の薄膜トランジスタにバックゲート電極を設け、そこに共通電極電位またはGND電位または特定の一定電位を接続してもよい。これにより、第5の薄膜トランジスタの動作は、安定する。 In FIG. 18, the pixel electrode 8 is the back gate electrode of the first thin film transistor, and the common wiring 11 is the back gate electrode of the fourth thin film transistor. As a result, the pixel electrode 8 is only connected to the gate electrode G1 without covering the channel portion of the first thin film transistor, or the common wiring 11 is connected to the gate electrode G4 without covering the channel portion of the fourth thin film transistor. The operation is more stable than when it is just connected. Further, although not shown in FIG. 12, a back gate electrode may be provided in the second thin film transistor, and a pixel electrode potential, a common electrode potential, a GND potential, or a specific constant potential may be connected thereto. As a result, the operation of the second thin film transistor becomes stable. Similarly, a back gate electrode may be provided on the third thin film transistor, and a pixel electrode potential, a common electrode potential, a GND potential, or a specific constant potential may be connected thereto. As a result, the operation of the third thin film transistor becomes stable. Similarly, a back gate electrode may be provided on the fifth thin film transistor, and a common electrode potential, a GND potential, or a specific constant potential may be connected thereto. As a result, the operation of the fifth thin film transistor becomes stable.
 図18はボトムゲート・トップコンタクトの場合を示すが、本開示はこれに限定されず、トップゲートやボトムコンタクトでもよい。 FIG. 18 shows the case of bottom gate and top contact, but the present disclosure is not limited to this, and top gate and bottom contact may be used.
 また、センサ部109を、+の刺激(加圧等)の時に画素電極8側の電位が上がる向きにした場合、刺激なし時の信号電圧を0~+2[V]のどこかに調整するのがよい。そうすれば、信号検出において0~+5V入力のADコンバータを用いる場合に、5~3Vの検出範囲を使用できる。センサ部109を、+の刺激(加圧等)の時に画素電極8側の電位が下がる向きにした場合、刺激なし時の信号電圧を+3~+5[V]のどこかに調整するのがよい。そうすれば、0~+5V入力のADコンバータを用いる場合に、3~5Vの検出範囲を使用できる。 Further, when the sensor unit 109 is oriented so that the potential on the pixel electrode 8 side rises at the time of + stimulation (pressurization, etc.), the signal voltage at the time of no stimulation is adjusted to somewhere between 0 and +2 [V]. Is good. Then, when an AD converter having a 0 to + 5 V input is used in signal detection, a detection range of 5 to 3 V can be used. When the sensor unit 109 is oriented so that the potential on the pixel electrode 8 side drops during + stimulation (pressurization, etc.), it is better to adjust the signal voltage without stimulation to somewhere between +3 and +5 [V]. .. Then, when using an AD converter with 0 to + 5V input, a detection range of 3 to 5V can be used.
 また、センサ部109を、+の刺激(加圧等)の時に画素電極8側の電位が上がる向きにした場合、差動増幅回路24で加算する電圧Vbaseを0~+2[V]のどこかに調整するのがよい。そうすれば、0~+5V入力のADコンバータを用いる場合に、5~3Vの検出範囲を使用できる。センサ部109を、+の刺激(加圧等)の時に画素電極8側の電位が下がる向きにした場合、差動増幅回路24で加算する電圧Vbaseを+3~+5[V]のどこかに調整するのがよい。そうすれば、0~+5V入力のADコンバータを用いる場合に、3~5Vの検出範囲を使用できる。 Further, when the sensor unit 109 is oriented so that the potential on the pixel electrode 8 side rises at the time of + stimulation (pressurization, etc.), the voltage Vbase to be added by the differential amplifier circuit 24 is somewhere between 0 and +2 [V]. It is better to adjust to. Then, when using an AD converter with 0 to + 5V input, a detection range of 5 to 3V can be used. When the sensor unit 109 is oriented so that the potential on the pixel electrode 8 side drops during + stimulation (pressurization, etc.), the voltage Vbase added by the differential amplifier circuit 24 is adjusted to somewhere between +3 and +5 [V]. It is better to do it. Then, when using an AD converter with 0 to + 5V input, a detection range of 3 to 5V can be used.
[第7の実施形態]
 図19に基づいて、第1の実施形態の信号検出回路または駆動検出回路、あるいは第2の実施形態の信号検出回路または駆動検出回路を用いた、健康状態推定システムを説明する。図19は本開示の介護データ収集・判定システムの実例を示すブロック図である。介護データ収集・判定システムは、介護センサ装置とデータ収集・判定装置を備える。介護センサ装置は、第1または第2の実施形態の信号検出回路に通信回路を追加したものであり、信号検出回路、通信回路、感圧センサアレイ、マイクロコンピュータ、駆動回路を備える。介護センサ装置の通信回路は、外部回路とデータ通信する回路であり、有線通信と無線通信が可能であるが、特にブルートゥース(登録商標)、Wi-Fi(登録商標)等の無線通信が好適であり、さらにはインターネットに接続することが好適である。データ収集・判定装置は、通信回路とコンピュータとデータベースとを有し、(1)介護センサ装置で検出したデータをそのまま、あるいは加工して、データベースに保存する。その際、被介護者の病状もいっしょに保存することもできる。(2)人工知能を用いてデータベース内のビッグデータを機械学習等により解析し、体勢と病状との関係を明らかにする。(3)介護センサ装置で検出したデータをデータベースのデータと比較し、病状の判定を行う。という3つの動作を行うことができる。
[7th Embodiment]
A health state estimation system using the signal detection circuit or drive detection circuit of the first embodiment or the signal detection circuit or drive detection circuit of the second embodiment will be described with reference to FIG. FIG. 19 is a block diagram showing an example of the nursing care data collection / determination system of the present disclosure. The long-term care data collection / judgment system includes a long-term care sensor device and a data collection / judgment device. The care sensor device is a signal detection circuit of the first or second embodiment to which a communication circuit is added, and includes a signal detection circuit, a communication circuit, a pressure-sensitive sensor array, a microcomputer, and a drive circuit. The communication circuit of the care sensor device is a circuit that communicates data with an external circuit and is capable of wired communication and wireless communication, but wireless communication such as Bluetooth (registered trademark) and Wi-Fi (registered trademark) is particularly preferable. Yes, and it is preferable to connect to the Internet. The data collection / judgment device has a communication circuit, a computer, and a database. (1) The data detected by the long-term care sensor device is stored in the database as it is or after being processed. At that time, the medical condition of the care recipient can also be saved together. (2) Using artificial intelligence, analyze big data in the database by machine learning or the like to clarify the relationship between posture and medical condition. (3) The data detected by the long-term care sensor device is compared with the data in the database to determine the medical condition. It is possible to perform three operations.
 1つのデータ収集・判定装置が1つの介護センサ装置とのみ接続してもよいし、1つのデータ収集・判定装置が複数の介護センサ装置と接続してもよい。1つの介護センサ装置とのみ接続する場合、データのやりとりが容易であるが、介護センサ装置の応答速度が速い必要がある。あるいはデータ収集・判定装置の速度はあまり速くなくてよい。複数の介護センサ装置と接続する場合、データのやりとりは複雑になるが、各々の介護センサ装置の動作速度は遅くてもよい。あるいはデータ収集・判定装置の速度は速い必要がある。 One data collection / judgment device may be connected to only one care sensor device, or one data collection / judgment device may be connected to a plurality of care sensor devices. When connecting to only one long-term care sensor device, data can be easily exchanged, but the response speed of the long-term care sensor device needs to be high. Alternatively, the speed of the data collection / judgment device does not have to be very high. When connecting to a plurality of long-term care sensor devices, data exchange becomes complicated, but the operating speed of each long-term care sensor device may be slow. Alternatively, the speed of the data collection / judgment device needs to be high.
 また、図19でコンピュータとデータベースは1つのデータ収集・判定装置内にあるが、コンピュータとデータベースとが通信回路を介して通信してもよい。 Further, although the computer and the database are in one data collection / judgment device in FIG. 19, the computer and the database may communicate with each other via a communication circuit.
 介護センサ装置の実例を、図20に示す。図20ではベッド201上に介護センサ装置200が見えるように記載しているが、実際にはこの上にシーツを乗せて、その上に被介護者に寝てもらう。図20(a)と(b)の介護センサ装置200は、ベッド上に大型シート状のセンサアレイ200A(例えば圧力センサアレイ)を有する。200Gが駆動回路、200Sが信号検出回路、200Cが制御・通信回路である。図20(a)のように短辺を駆動側にしてもよいし、(b)のように、長辺を駆動側にしてもよい。 An example of the long-term care sensor device is shown in FIG. In FIG. 20, the care sensor device 200 is described so as to be visible on the bed 201, but in reality, the sheets are placed on the bed 201 and the care recipient is asked to sleep on the sheets. The nursing care sensor device 200 of FIGS. 20A and 20B has a large sheet-shaped sensor array 200A (for example, a pressure sensor array) on the bed. 200G is a drive circuit, 200S is a signal detection circuit, and 200C is a control / communication circuit. The short side may be the driving side as shown in FIG. 20A, or the long side may be the driving side as shown in FIG. 20B.
 図20(c)の介護センサ装置200は、帯状のセンサアレイ200Aを複数有し、信号検出回路200Sに帯状のセンサアレイ200Aの短辺を全て接続し、帯状の長辺の隣同士を駆動配線間接続部品200WGで接続することで1つの駆動回路200Gに全てのゲート配線を接続し、1つの制御・通信回路200Cを有する。図20(d)の介護センサ装置200は、小型シート状のセンサアレイ200Aを複数有し、小型シート状のセンサアレイ200Aの信号配線同士を信号配線間接続部品200WSで接続して信号検出回路200Sに接続し、小型シート状のセンサアレイ200Aの駆動配線同士を駆動配線間接続部品200WGで接続して1つの駆動回路200Gに接続し、1つの制御・通信回路200Cを有する。図20(c)と図20(d)は、図20(a)の大型シート状のセンサアレイを、複数の帯状のセンサアレイ、または複数の小型シート状のセンサアレイで代替したものである。図20(b)のように駆動側と信号側を入れ替えてもよい。これらは、1つの介護センサ装置200として動作する。 The care sensor device 200 of FIG. 20C has a plurality of band-shaped sensor arrays 200A, connects all the short sides of the band-shaped sensor array 200A to the signal detection circuit 200S, and drives wiring next to each other on the long side of the band. By connecting with the inter-connection component 200WG, all the gate wirings are connected to one drive circuit 200G, and one control / communication circuit 200C is provided. The care sensor device 200 of FIG. 20D has a plurality of small sheet-shaped sensor arrays 200A, and the signal wirings of the small sheet-shaped sensor arrays 200A are connected to each other by a signal wiring connection component 200WS to connect the signal detection circuit 200S. The drive wirings of the small sheet-shaped sensor array 200A are connected to each other by the drive wiring connection component 200WG to be connected to one drive circuit 200G, and have one control / communication circuit 200C. 20 (c) and 20 (d) replace the large sheet-shaped sensor array of FIG. 20 (a) with a plurality of strip-shaped sensor arrays or a plurality of small sheet-shaped sensor arrays. The drive side and the signal side may be interchanged as shown in FIG. 20 (b). These operate as one care sensor device 200.
 図20(e)の介護センサ装置200は、帯状のセンサアレイ200Aを複数有し、信号検出回路200Sに帯状のセンサアレイ200Aの短辺を接続し、複数の駆動回路200Gに各々の帯状のセンサアレイ200Aの長辺を接続し、複数の制御・通信回路200Cを有する。図20(f)の介護センサ装置200は、小型シート状のセンサアレイ200Aを複数有し、小型シート状のセンサアレイ200Aの信号配線同士を信号配線間接続部品200WSで接続して帯状セットを形成して信号検出回路200Sに接続し、複数の駆動回路200Gに各々の帯状セットを接続し、複数の制御・通信回路200Cを有する。図20(e)と図20(f)は、複数の介護センサ装置200として動作する。 The nursing care sensor device 200 of FIG. 20 (e) has a plurality of band-shaped sensor arrays 200A, connects the short side of the band-shaped sensor array 200A to the signal detection circuit 200S, and connects each band-shaped sensor to the plurality of drive circuits 200G. The long sides of the array 200A are connected to each other, and a plurality of control / communication circuits 200C are provided. The care sensor device 200 of FIG. 20F has a plurality of small sheet-shaped sensor arrays 200A, and the signal wirings of the small sheet-shaped sensor arrays 200A are connected to each other by a signal wiring connection component 200WS to form a strip-shaped set. Then, it is connected to the signal detection circuit 200S, each band-shaped set is connected to the plurality of drive circuits 200G, and has a plurality of control / communication circuits 200C. 20 (e) and 20 (f) operate as a plurality of care sensor devices 200.
 また、センサアレイを体勢の判定に適用する場合、全ての画素の刺激値(圧力等)が正確に測定される場合でなくても判定は可能である。1画素の検知部に不具合が発生して異常データとなっても、周囲の画素のデータから補間して判定することができる。また複数の画素の検知部に不具合が発生して異常データとなっても、周囲の画素のデータから補間して判定することができる。この場合は、不具合が生じる画素が分散している場合であれば、密集している場合と比べて、データを補間がしやすい。しかし密集している場合でも、一定の補間は可能である。尚、センサアレイは圧力センサに限らない。具体的には、変位センサや温度センサをセンサアレイとできる。つまり、変位センサアレイや温度センサアレイにも適用可能である。さらには、例えば温度センサと圧力センサの両方を備えた、複合センサアレイにも適用できる。 Further, when the sensor array is applied to the determination of the posture, the determination is possible even if the stimulation values (pressure, etc.) of all the pixels are not accurately measured. Even if a problem occurs in the detection unit of one pixel and it becomes abnormal data, it can be determined by interpolating from the data of surrounding pixels. Further, even if a problem occurs in the detection unit of a plurality of pixels and the data becomes abnormal, it can be determined by interpolating from the data of the surrounding pixels. In this case, if the pixels in which the problem occurs are dispersed, it is easier to interpolate the data as compared with the case where the pixels are densely packed. However, even when it is dense, constant interpolation is possible. The sensor array is not limited to the pressure sensor. Specifically, a displacement sensor or a temperature sensor can be used as a sensor array. That is, it can also be applied to a displacement sensor array and a temperature sensor array. Furthermore, it can be applied to a composite sensor array having both a temperature sensor and a pressure sensor, for example.
 さらに図22のように、ドレイン配線14には電流制限回路40を設けることが好適である。アレイ内でドレイン配線14と他配線(走査配線12、信号配線15、リファレンス信号配線16、共通電極37等)との間に短絡が発生した場合に、過大電流が流れることを防止する。その際、図22(a)のように電源が1つの電流制限回路40を通ってから分岐して、全てのドレイン配線14に接続されてもよいが、その場合には1か所の異常によって全てのドレイン配線14の電圧が低下し、センサアレイ全体が異常値を示す。そこで図22(b)のように、電源を分岐して、分岐したそれぞれが電流制限回路40を通ってから、個々のドレイン配線14に接続されることが望ましい。通常は、ドレイン配線14を列毎または行毎に設けるので、そのドレイン配線14毎に1個ずつの電流制限回路40を設けることが好適である。この場合、1か所の異常によって1本のドレイン配線14の電圧が低下し、1列または1行のセンサが異常値を示すことになるが、1列や1行の異常は補間によって補正することができる。あるいは図22(c)のように、複数の電流制限回路40のそれぞれに、複数の列配線または行配線を担当させることもできる。その際、図22(d)のように1個の電流制限回路40が担当する列配線または行配線を隣接させず間に別の電流制限回路40が担当する列配線または行配線を設けることにより、1か所の異常が複数列または複数行の連続した異常になることを回避でき、補間が可能になる。なお、電流制限回路40は、図22(a)に示す回路に限定されず、他の方式の電流制限回路でもよい。 Further, as shown in FIG. 22, it is preferable to provide the drain wiring 14 with a current limiting circuit 40. When a short circuit occurs between the drain wiring 14 and other wiring (scanning wiring 12, signal wiring 15, reference signal wiring 16, common electrode 37, etc.) in the array, it prevents an excessive current from flowing. At that time, as shown in FIG. 22A, the power supply may be branched after passing through one current limiting circuit 40 and connected to all the drain wirings 14, but in that case, due to an abnormality at one place. The voltage of all the drain wires 14 drops, and the entire sensor array shows an abnormal value. Therefore, as shown in FIG. 22B, it is desirable that the power supply is branched, each of the branches passes through the current limiting circuit 40, and then connected to the individual drain wiring 14. Normally, since the drain wiring 14 is provided for each column or row, it is preferable to provide one current limiting circuit 40 for each drain wiring 14. In this case, the voltage of one drain wiring 14 drops due to an abnormality at one place, and the sensor in one column or one row shows an abnormal value, but the abnormality in one column or one row is corrected by interpolation. be able to. Alternatively, as shown in FIG. 22C, each of the plurality of current limiting circuits 40 may be assigned a plurality of column wirings or row wirings. At that time, as shown in FIG. 22D, the column wiring or row wiring in charge of one current limiting circuit 40 is not adjacent to each other, and the column wiring or row wiring in charge of another current limiting circuit 40 is provided between them. It is possible to prevent an abnormality in one place from becoming a continuous abnormality of a plurality of columns or a plurality of rows, and interpolation becomes possible. The current limiting circuit 40 is not limited to the circuit shown in FIG. 22A, and may be another type of current limiting circuit.
 以上のように、第1の実施形態の信号検出回路または駆動検出回路、あるいは第2の実施形態の信号検出回路または駆動検出回路を適用することで、健康状態推定を行うことができる介護データ収集・判定システムを提供することができる。 As described above, by applying the signal detection circuit or drive detection circuit of the first embodiment or the signal detection circuit or drive detection circuit of the second embodiment, the long-term care data collection capable of estimating the health condition can be performed. -A judgment system can be provided.
(実施例1)
 図1の信号検出回路を作製した。第1の切替回路101は8入力1出力のアナログマルチプレクサ、負荷抵抗20は1MΩの金属皮膜抵抗、電圧検出アンプ53はオペアンプによるボルテージフォロワ、第2の切替回路102は8入力1出力のアナログマルチプレクサ、ADコンバータ25は0~+5V入力で0~255レベル(8bit)出力とした。この回路はM=8、M=8、L=8であり、M=64本の信号配線15を有するセンサアレイに対応する。電圧検出アンプ53には発振防止回路を組み込み、電圧検出アンプ53の出力側にはADコンバータ入力保護回路を設けた。
(Example 1)
The signal detection circuit of FIG. 1 was manufactured. The first switching circuit 101 is an analog multiplexer with 8 inputs and 1 output, the load resistance 20 is a metal film resistance of 1 MΩ, the voltage detection amplifier 53 is a voltage follower using an operational amplifier, and the second switching circuit 102 is an analog multiplexer with 8 inputs and 1 output. The AD converter 25 has a 0 to + 5 V input and a 0 to 255 level (8 bit) output. This circuit has M 1 = 8, M 2 = 8, L = 8, and corresponds to a sensor array having M = 64 signal wires 15. An oscillation prevention circuit was incorporated in the voltage detection amplifier 53, and an AD converter input protection circuit was provided on the output side of the voltage detection amplifier 53.
 マイコンと3bitカウンタを用いて第1の切替回路101を制御し、同マイコンで第2の切替回路102とADコンバータ25も制御し、1行64列の圧力センサアレイの信号を検出した。ADコンバータ25の測定時間を(準備時間104μs+実計測時間52μs)=156μsとし、第2の切替回路102の出力の応答の時定数は3μs程度、第1の切替回路101の出力の応答の時定数は500μs程度であった。第1の切替回路101の出力の応答の時定数が、(M-1)×ADコンバータ測定時間=1092μsに比べて小さいので、図5の信号検出方法によって、信号が安定してからの高精度の測定ができた。 The first switching circuit 101 was controlled by using a microcomputer and a 3-bit counter, and the second switching circuit 102 and the AD converter 25 were also controlled by the same microcomputer to detect the signal of the pressure sensor array of 1 row and 64 columns. The measurement time of the AD converter 25 is (preparation time 104 μs + actual measurement time 52 μs) = 156 μs, the time constant of the output response of the second switching circuit 102 is about 3 μs, and the time constant of the output response of the first switching circuit 101. Was about 500 μs. The time constant of the response of the output of the first switching circuit 101, since (M 2 -1) × AD converter measurement time = small compared to 1092Myuesu, the signal detection method of FIG. 5, signals from the stable high I was able to measure the accuracy.
(実施例2)
 実施例1の信号検出回路に、実施例1で用いたマイコンおよびカウンタを制御回路5とカウンタ49として加え、さらに駆動回路6を追加して、図3の駆動検出回路を作製した。駆動回路は、オン電圧として+15Vを、またはオフ電圧として-15Vを出力する。
(Example 2)
The microcomputer and the counter used in the first embodiment were added to the signal detection circuit of the first embodiment as the control circuit 5 and the counter 49, and the drive circuit 6 was further added to prepare the drive detection circuit of FIG. The drive circuit outputs + 15V as the on voltage or -15V as the off voltage.
 この駆動検出回路を用いて、図5の信号検出方法によって、8行64列の圧力センサアレイの信号を検出した。ADコンバータ25の測定時間を(準備時間104μs+実計測時間52μs)=156μsとし、第2の切替回路102の出力の応答の時定数は3μs程度、第1の切替回路101の出力の応答の時定数は500μs程度であった。第1の切替回路101の出力の応答の時定数が、(M-1)×ADコンバータ測定時間=1092μsに比べて小さいので、図5の信号検出方法によって、信号が安定してからの高精度の測定ができた。 Using this drive detection circuit, the signal of the pressure sensor array of 8 rows and 64 columns was detected by the signal detection method of FIG. The measurement time of the AD converter 25 is (preparation time 104 μs + actual measurement time 52 μs) = 156 μs, the time constant of the output response of the second switching circuit 102 is about 3 μs, and the time constant of the output response of the first switching circuit 101. Was about 500 μs. The time constant of the response of the output of the first switching circuit 101, since (M 2 -1) × AD converter measurement time = small compared to 1092Myuesu, the signal detection method of FIG. 5, signals from the stable high I was able to measure the accuracy.
(実施例3)
 図7の信号検出回路を作製した。第1の切替回路101および第3の切替回路103には(8入力1出力×2セット)のアナログマルチプレクサの各セットを用い、負荷抵抗20、21は1MΩの金属皮膜抵抗、電圧検出アンプ53、54はオペアンプによる非反転増幅回路、差動増幅回路24はオペアンプによる回路、第2の切替回路102は8入力1出力のアナログマルチプレクサ、ADコンバータ25は0~+5V入力で0~255レベル(8bit)出力とした。この回路はM=8、M=8、L=8であり、M=64本の信号配線と64本のリファレンス信号配線を有するセンサアレイに対応する。電圧検出アンプ53、54には発振防止回路を組み込み、電圧検出アンプ53、54の出力側にはADコンバータ入力保護回路を設けた。
(Example 3)
The signal detection circuit of FIG. 7 was manufactured. Each set of analog multiplexers (8 inputs, 1 output x 2 sets) is used for the first switching circuit 101 and the third switching circuit 103, and the load resistors 20 and 21 are 1 MΩ metal film resistors, the voltage detection amplifier 53, and the like. 54 is a non-inverting amplifier circuit using an operational amplifier, the differential amplifier circuit 24 is a circuit using an operational amplifier, the second switching circuit 102 is an analog multiplexer with 8 inputs and 1 output, and the AD converter 25 is 0 to 255 levels (8 bits) with 0 to + 5 V inputs. It was used as an output. This circuit has M 1 = 8, M 2 = 8, L = 8, and corresponds to a sensor array with M = 64 signal wires and 64 reference signal wires. An oscillation prevention circuit was incorporated in the voltage detection amplifiers 53 and 54, and an AD converter input protection circuit was provided on the output side of the voltage detection amplifiers 53 and 54.
 マイコンおよび3bitカウンタを用いて第1の切替回路101および第3の切替回路103を制御し、同マイコンで第2の切替回路102とADコンバータ25も制御し、1行64列の圧力センサアレイの信号を検出した。ADコンバータ25の測定時間を(準備時間104μs+実計測時間52μs)=156μsとし、第2の切替回路102の出力の応答の時定数は3μs程度、第1の切替回路101の出力の応答の時定数は500μs程度であった。第1の切替回路101の出力の応答の時定数が、(M-1)×ADコンバータ測定時間=1092μsに比べて小さいので、図9の信号検出方法によって、信号が安定してからの高精度の測定ができた。 The first switching circuit 101 and the third switching circuit 103 are controlled by using a microcomputer and a 3-bit counter, and the second switching circuit 102 and the AD converter 25 are also controlled by the same microcomputer. A signal was detected. The measurement time of the AD converter 25 is (preparation time 104 μs + actual measurement time 52 μs) = 156 μs, the time constant of the output response of the second switching circuit 102 is about 3 μs, and the time constant of the output response of the first switching circuit 101. Was about 500 μs. The time constant of the response of the output of the first switching circuit 101, since (M 2 -1) × AD converter measurement time = small compared to 1092Myuesu, the signal detection method of FIG. 9, signals from the stable high I was able to measure the accuracy.
(実施例4)
 実施例3の信号検出回路に、実施例3で用いたマイコンおよびカウンタを加え、さらに駆動回路6を追加して、図8の駆動検出回路を作製した。駆動回路6は、オン電圧として+15Vを、またはオフ電圧として-15Vを出力する。
(Example 4)
The microcomputer and the counter used in the third embodiment were added to the signal detection circuit of the third embodiment, and the drive circuit 6 was further added to prepare the drive detection circuit of FIG. The drive circuit 6 outputs + 15V as an on voltage or -15V as an off voltage.
 この駆動検出回路を用いて、図9の信号検出方法によって、8行64列の圧力センサアレイの信号を検出した。ADコンバータ25の測定時間を(準備時間104μs+実計測時間52μs)=156μsとし、第2の切替回路102の出力の応答の時定数は3μs程度、第1の切替回路101および第3の切替回路103の出力の応答の時定数は500μs程度であった。第1の切替回路101および第3の切替回路103の出力の応答の時定数が、(M-1)×ADコンバータ測定時間=1092μsに比べて小さいので、図9の信号検出方法によって、信号が安定してからの高精度の測定ができた。 Using this drive detection circuit, the signal of the pressure sensor array of 8 rows and 64 columns was detected by the signal detection method of FIG. The measurement time of the AD converter 25 is (preparation time 104 μs + actual measurement time 52 μs) = 156 μs, the time constant of the output response of the second switching circuit 102 is about 3 μs, and the first switching circuit 101 and the third switching circuit 103. The time constant of the response of the output of was about 500 μs. The time constant of the response of the output of the first switching circuit 101 and the third switching circuit 103, since (M 2 -1) × AD converter measurement time = small compared to 1092Myuesu, the signal detection method of FIG. 9, the signal Was able to measure with high accuracy after it became stable.
(実施例5)
 図12のセンサアレイを作製した。絶縁基板1としてガラス基板上のPET膜を用い、Moを成膜・レジスト成膜・パターン露光・現像・エッチング・レジスト除去して、ゲート電極G1、G2と走査配線12を形成した。次に、感光性アクリルを成膜・パターン露光・現像して、開口付きのゲート絶縁膜3を形成した。また、非晶質InGaZnOを成膜・レジスト成膜・パターン露光・現像・エッチング・レジスト除去して、半導体パターンSC1、SC2を形成した。そして、半導体パターンSC1、SC2の、チャネルとなる部分の上にエッチングストッパ層としてSiOパターンを形成した(図示せず)。
(Example 5)
The sensor array of FIG. 12 was manufactured. Using a PET film on a glass substrate as the insulating substrate 1, Mo was formed by film formation, resist film formation, pattern exposure, development, etching, and resist removal to form gate electrodes G1 and G2 and scanning wiring 12. Next, the photosensitive acrylic was formed into a film, exposed to a pattern, and developed to form a gate insulating film 3 with an opening. Further, the amorphous InGaZnO was formed by film formation, resist film formation, pattern exposure, development, etching, and resist removal to form semiconductor patterns SC1 and SC2. Then, a SiO 2 pattern was formed as an etching stopper layer on the portions of the semiconductor patterns SC1 and SC2 to be channels (not shown).
 さらに、Moを成膜・レジスト成膜・パターン露光・現像・エッチング・レジスト除去して、ソース電極S1、S2、ドレイン電極D1、D2、接続配線17(S1-D2間)、信号配線15、ドレイン配線14、ビア配線18L(画素電極-G1間の下半分)を形成した。 Further, Mo is formed into a film, resist film, pattern exposure, development, etching, and resist removal to remove the source electrodes S1 and S2, the drain electrodes D1 and D2, the connection wiring 17 (between S1 and D2), the signal wiring 15, and the drain. The wiring 14 and the via wiring 18L (lower half between the pixel electrode and G1) were formed.
 そして、感光性アクリルを成膜・パターン露光・現像して、開口付きの層間絶縁膜7を形成した。次に、Moを成膜・レジスト成膜・パターン露光・現像・エッチング・レジスト除去して、画素電極8およびビア配線18U(画素電極8-G1間の上半分)を形成し
た。この時、画素電極8はビア配線18U、18Lによってゲート電極G1に接続された。
Then, the photosensitive acrylic was formed into a film, exposed to a pattern, and developed to form an interlayer insulating film 7 with an opening. Next, Mo was formed into a film, a resist film, pattern exposure, development, etching, and resist removal to form a pixel electrode 8 and a via wiring 18U (upper half between the pixel electrodes 8 and G1). At this time, the pixel electrode 8 was connected to the gate electrode G1 by via wires 18U and 18L.
 さらに、片側全面にMoが付いた感圧媒体(ポリフッ化ビニリデン3フッ化エチレン共重合体、分極処理済)を、感圧媒体側が画素電極8に接触するように設置して、センサ部109(感圧媒体9)および共通電極10とした。そして、絶縁基板1であるPET膜から、ガラス基板を剥離した。画素電極8が薄いので、センサ部109(感圧媒体9)は画素電極8以外の部分では層間絶縁膜7に接触しており、隙間はほとんどない。 Further, a pressure-sensitive medium (polyvinylidene fluoride triethylene ethylene copolymer, polarized) having Mo attached to the entire surface of one side is installed so that the pressure-sensitive medium side is in contact with the pixel electrode 8, and the sensor unit 109 ( The pressure-sensitive medium 9) and the common electrode 10 were used. Then, the glass substrate was peeled off from the PET film which is the insulating substrate 1. Since the pixel electrode 8 is thin, the sensor unit 109 (pressure sensitive medium 9) is in contact with the interlayer insulating film 7 in a portion other than the pixel electrode 8, and there is almost no gap.
 ここで、第1の薄膜トランジスタのゲート・ドレイン間容量(画素電極・ドレイン配線間容量を含む)Cgd1=1.53pF、画素電極8・共通電極10間容量Cp=63.1pFであった。 Here, the gate-drain capacitance (including the pixel electrode-drain wiring capacitance) of the first thin film transistor was Cgd1 = 1.53 pF, and the pixel electrode 8 / common electrode 10 capacitance Cp = 63.1 pF.
 図23の検出回路を用い、共通電極10に+1V、ドレイン配線14に+10V、走査配線12のうち1本にオン電圧+15V、他にオフ電圧-15Vを印加して、1画素分の圧力依存信号を得た。アナログスイッチ22を切り替えることで、1行分の圧力依存信号を得た。走査配線12のオン電圧位置を変えて同様の操作を行い、全画素の圧力依存信号を得た。圧力依存信号から、各画素の圧力がわかる。また、Vdd印加時の画素電極8の電位変化は0.24Vであり、感圧媒体9の最大電位変化量(圧力800kPa時)が4Vなので、Vdd印加時の画素電極8の電位変化による誤差は最大電位変化量の6%と充分に小さい。 Using the detection circuit of FIG. 23, + 1V is applied to the common electrode 10, + 10V is applied to the drain wiring 14, an on voltage + 15V is applied to one of the scanning wirings 12, and an off voltage of -15V is applied to the other, and a pressure-dependent signal for one pixel is applied. Got By switching the analog switch 22, a pressure-dependent signal for one line was obtained. The same operation was performed by changing the on-voltage position of the scanning wiring 12, and pressure-dependent signals of all pixels were obtained. From the pressure-dependent signal, the pressure of each pixel can be known. Further, since the potential change of the pixel electrode 8 when Vdd is applied is 0.24 V and the maximum potential change amount of the pressure sensitive medium 9 (at a pressure of 800 kPa) is 4 V, the error due to the potential change of the pixel electrode 8 when Vdd is applied is It is sufficiently small, 6% of the maximum potential change amount.
(実施例6)
 図14のセンサアレイを作製した。絶縁基板1としてガラス基板上のポリイミド膜を用い、Moを成膜・レジスト成膜・パターン露光・現像・エッチング・レジスト除去して、ゲート電極G1、G2、G3、走査配線12、リセット配線13を形成した。次に、感光性アクリルを成膜・パターン露光・現像して、開口付きのゲート絶縁膜3を形成した。また、非晶質InGaZnOを成膜・レジスト成膜・パターン露光・現像・エッチング・レジスト除去して、半導体パターンSC1、SC2、SC3を形成した。そして、半導体パターンSC1、SC2、SC3の、チャネルとなる部分の上にエッチングストッパ層としてSiOパターンを形成した(図示せず)。
(Example 6)
The sensor array of FIG. 14 was manufactured. Using a polyimide film on a glass substrate as the insulating substrate 1, Mo is formed, resist filmed, pattern exposed, developed, etched, and resist removed to form gate electrodes G1, G2, G3, scanning wiring 12, and reset wiring 13. Formed. Next, the photosensitive acrylic was formed into a film, exposed to a pattern, and developed to form a gate insulating film 3 with an opening. Further, the amorphous InGaZnO was formed by film formation, resist film formation, pattern exposure, development, etching, and resist removal to form semiconductor patterns SC1, SC2, and SC3. Then, a SiO 2 pattern was formed as an etching stopper layer on the portions of the semiconductor patterns SC1, SC2, and SC3 to be channels (not shown).
 さらに、Moを成膜・レジスト成膜・パターン露光・現像・エッチング・レジスト除去して、ソース電極S1、S2、S3、ドレイン電極D1、D2、D3、接続配線17(S1-D2間)、ビア配線18L(D3-G1間)、信号配線15、ドレイン配線14を形成した。 Further, Mo is formed into a film, resist film, pattern exposure, development, etching, and resist removal to remove the source electrodes S1, S2, S3, drain electrodes D1, D2, D3, connection wiring 17 (between S1 and D2), and vias. The wiring 18L (between D3-G1), the signal wiring 15, and the drain wiring 14 were formed.
 そして、感光性アクリルを成膜・パターン露光・現像して、開口付きの層間絶縁膜7を形成した。次に、Agペーストをスクリーン印刷して、画素電極8とビア配線18U(画素電極8-D3間)を形成した。この時、画素電極8はビア配線18U、18Lによってドレイン電極D3およびゲート電極G1に接続された。 Then, the photosensitive acrylic was formed into a film, exposed to a pattern, and developed to form an interlayer insulating film 7 with an opening. Next, the Ag paste was screen-printed to form the pixel electrode 8 and the via wiring 18U (between the pixel electrodes 8 and D3). At this time, the pixel electrode 8 was connected to the drain electrode D3 and the gate electrode G1 by the via wires 18U and 18L.
 さらに、片側全面にMoが付いた感圧媒体(ポリフッ化ビニリデン3フッ化エチレン共重合体、分極処理済)を、感圧媒体側が画素電極8に接合するように設置して、センサ部109(感圧媒体9)および共通電極10とした。また、絶縁基板1であるポリイミド膜から、ガラス基板を剥離した。画素電極8が厚いので、センサ部109(感圧媒体9)は層間絶縁膜7に接触しておらず、画素電極8がない部分には隙間がある。 Further, a pressure-sensitive medium having Mo on the entire surface of one side (polyvinylidene fluoride triethylene ethylene copolymer, polarization-treated) is installed so that the pressure-sensitive medium side is bonded to the pixel electrode 8, and the sensor unit 109 ( The pressure-sensitive medium 9) and the common electrode 10 were used. Further, the glass substrate was peeled off from the polyimide film which is the insulating substrate 1. Since the pixel electrode 8 is thick, the sensor unit 109 (pressure sensitive medium 9) is not in contact with the interlayer insulating film 7, and there is a gap in the portion where the pixel electrode 8 is not provided.
 ここで、第1の薄膜トランジスタのゲート・ドレイン間容量(画素電極・ドレイン配線間容量を含む)Cgd1=1.53pF、第3の薄膜トランジスタのゲート・ドレイン間
容量(画素電極・ドレイン配線間容量を含む)Cgd3=0.69pF、画素電極8・共通電極10間容量Cp=63.1pFであった。
Here, the gate-drain capacitance of the first thin film transistor (including the capacitance between the pixel electrode and the drain wiring) Cgd1 = 1.53pF, and the gate-drain capacitance of the third thin film transistor (including the capacitance between the pixel electrode and the drain wiring). ) Cgd3 = 0.69pF, and the capacitance between the pixel electrode 8 and the common electrode 10 was Cp = 63.1pF.
 図24の検出回路を用い、最初に、共通電極10に+1V、ドレイン配線14に0Vの状態で、リセット配線13にオン電圧+15Vを印加した。次に、リセット配線13の電位をオフ電圧-15Vに、ドレイン配線14の電位を+15Vにした。 Using the detection circuit of FIG. 24, first, an on-voltage + 15V was applied to the reset wiring 13 with + 1V to the common electrode 10 and 0V to the drain wiring 14. Next, the potential of the reset wiring 13 was set to an off voltage of -15V, and the potential of the drain wiring 14 was set to + 15V.
 走査配線12のうち1本にオン電圧+15V、他にオフ電圧-15Vを印加して、1画素分の圧力依存信号を得た。アナログスイッチ22を切り替えることで、1行分の圧力依存信号を得た。走査配線12のオン電圧位置を変えて同様の操作を行い、全画素の圧力依存信号を得た。圧力依存信号から、各画素の圧力がわかる。また、VresetオフかつVdd印加時の画素電極8の電位変化は0.027Vであり、感圧媒体9の最大電位変化量(圧力800kPa時)が4Vなので、VresetオフかつVdd印加時の画素電極8の電位変化による誤差は最大電位変化量の0.7%と充分に小さい。 An on voltage of + 15V and an off voltage of -15V were applied to one of the scanning wires 12 to obtain a pressure-dependent signal for one pixel. By switching the analog switch 22, a pressure-dependent signal for one line was obtained. The same operation was performed by changing the on-voltage position of the scanning wiring 12, and pressure-dependent signals of all pixels were obtained. From the pressure-dependent signal, the pressure of each pixel can be known. Further, since the potential change of the pixel electrode 8 when Vreset is off and Vdd is applied is 0.027V and the maximum potential change amount of the pressure sensitive medium 9 (at a pressure of 800 kPa) is 4V, the pixel electrode 8 when Vreset is off and Vdd is applied is 4V. The error due to the potential change is 0.7% of the maximum potential change, which is sufficiently small.
(実施例7)
 図16のセンサアレイを作製した。絶縁基板1としてガラス基板上のPET膜を用い、Moを成膜・レジスト成膜・パターン露光・現像・エッチング・レジスト除去して、ゲート電極G1、G2、G4、G5、走査配線12を形成した。次に、感光性アクリルを成膜・パターン露光・現像して、開口付きのゲート絶縁膜3を形成した。また、非晶質InGaZnOを成膜・レジスト成膜・パターン露光・現像・エッチング・レジスト除去して、半導体パターンSC1、SC2、SC4、SC5を形成した。そして、半導体パターンSC1、SC2、SC4、SC5の、チャネルとなる部分の上にエッチングストッパ層としてSiOパターンを形成した(図示せず)。
(Example 7)
The sensor array of FIG. 16 was manufactured. Using a PET film on a glass substrate as the insulating substrate 1, Mo was formed by film formation, resist film formation, pattern exposure, development, etching, and resist removal to form gate electrodes G1, G2, G4, G5, and scanning wiring 12. .. Next, the photosensitive acrylic was formed into a film, exposed to a pattern, and developed to form a gate insulating film 3 with an opening. Further, the amorphous InGaZnO was formed by film formation, resist film formation, pattern exposure, development, etching, and resist removal to form semiconductor patterns SC1, SC2, SC4, and SC5. Then, a SiO 2 pattern was formed as an etching stopper layer on the channel portions of the semiconductor patterns SC1, SC2, SC4, and SC5 (not shown).
 さらに、Moを成膜・レジスト成膜・パターン露光・現像・エッチング・レジスト除去して、ソース電極S1、S2、S4、S5、ドレイン電極D1、D2、D4、D5、接続配線17(S1-D2間)、接続配線17(S4-D5間)、信号配線15、リファレンス信号配線16、ドレイン配線14、共通配線11、ビア配線18L(画素電極8-G1間の下半分)、ビア配線18L(共通配線11-G4間の下半分)を形成した。 Further, Mo is formed into a film, resist is formed, pattern is exposed, developed, etched, and resist is removed to remove the source electrodes S1, S2, S4, S5, drain electrodes D1, D2, D4, D5, and connection wiring 17 (S1-D2). (Between), connection wiring 17 (between S4-D5), signal wiring 15, reference signal wiring 16, drain wiring 14, common wiring 11, via wiring 18L (lower half between pixel electrodes 8 and G1), via wiring 18L (common) The lower half of the wiring 11-G4) was formed.
 そして、感光性アクリルを成膜・パターン露光・現像して、開口付きの層間絶縁膜7を形成した。次に、Agペーストをスクリーン印刷して、画素電極8、共通配線11、ビア配線18U(画素電極8-G1間の上半分)、ビア配線18U(共通配線11-G4間の上半分)を形成した。この時、画素電極8はゲート電極G1に接続され、共通配線11はゲート電極G4に接続された。 Then, the photosensitive acrylic was formed into a film, exposed to a pattern, and developed to form an interlayer insulating film 7 with an opening. Next, the Ag paste is screen-printed to form the pixel electrode 8, the common wiring 11, the via wiring 18U (upper half between the pixel electrodes 8 and G1), and the via wiring 18U (the upper half between the common wiring 11 and G4). bottom. At this time, the pixel electrode 8 was connected to the gate electrode G1, and the common wiring 11 was connected to the gate electrode G4.
 さらに、片側全面にMoが付いた感圧媒体(ポリフッ化ビニリデン3フッ化エチレン共重合体、分極処理済)を、感圧媒体側が画素電極8に接合するように設置して、センサ部109(感圧媒体9)および共通電極10とした。また、絶縁基板1であるPET膜から、ガラス基板を剥離した。 Further, a pressure-sensitive medium having Mo on the entire surface of one side (polyvinylidene fluoride triethylene ethylene copolymer, polarization-treated) is installed so that the pressure-sensitive medium side is bonded to the pixel electrode 8, and the sensor unit 109 ( The pressure-sensitive medium 9) and the common electrode 10 were used. Further, the glass substrate was peeled off from the PET film which is the insulating substrate 1.
 ここで、第1の薄膜トランジスタのゲート・ドレイン間容量(画素電極・ドレイン配線間容量を含む)Cgd1=1.53pF、画素電極8・共通電極10間容量Cp=63.1pFであった。 Here, the gate-drain capacitance (including the pixel electrode-drain wiring capacitance) of the first thin film transistor was Cgd1 = 1.53 pF, and the pixel electrode 8 / common electrode 10 capacitance Cp = 63.1 pF.
 図25の検出回路を用い、共通電極10に+1V、ドレイン配線14に+10V、走査配線12のうち1本にオン電圧+15V、他にオフ電圧-15Vを印加して、1画素分の圧力依存信号を得た。アナログスイッチ22を切り替えることで、1行分の圧力依存信号を得た。走査配線12のオン電圧位置を変えて同様の操作を行い、全画素の圧力依存信号を得た。圧力依存信号から、各画素の圧力がわかる。また、Vdd印加時の画素電極8の電位変化は0.24Vであり、感圧媒体9の最大電位変化量(圧力800kPa時)が4Vなので、Vdd印加時の画素電極8の電位変化による誤差は最大電位変化量の6%と充分に小さい。なお、検出回路のVbase=0.5[V]とした。 Using the detection circuit of FIG. 25, + 1V is applied to the common electrode 10, + 10V is applied to the drain wiring 14, an on voltage + 15V is applied to one of the scanning wirings 12, and an off voltage of -15V is applied to the other, and a pressure-dependent signal for one pixel is applied. Got By switching the analog switch 22, a pressure-dependent signal for one line was obtained. The same operation was performed by changing the on-voltage position of the scanning wiring 12, and pressure-dependent signals of all pixels were obtained. From the pressure-dependent signal, the pressure of each pixel can be known. Further, since the potential change of the pixel electrode 8 when Vdd is applied is 0.24 V and the maximum potential change amount of the pressure sensitive medium 9 (at a pressure of 800 kPa) is 4 V, the error due to the potential change of the pixel electrode 8 when Vdd is applied is It is sufficiently small, 6% of the maximum potential change amount. The detection circuit was set to Vbase = 0.5 [V].
(実施例8)
 図18のセンサアレイを作製した。絶縁基板1としてガラス基板上のポリイミド膜を用い、Moを成膜・レジスト成膜・パターン露光・現像・エッチング・レジスト除去して、ゲート電極G1、G2、G3、G4、G5、走査配線12、リセット配線13を形成した。次に、感光性アクリルを成膜・パターン露光・現像して、開口付きのゲート絶縁膜3を形成した。また、非晶質InGaZnOを成膜・レジスト成膜・パターン露光・現像・エッチング・レジスト除去して、半導体パターンSC1、SC2、SC3、SC4、SC5を形成した。そして、半導体パターンSC1、SC2、SC3、SC4、SC5の、チャネルとなる部分の上にエッチングストッパ層としてSiOパターンを形成した(図示せず)。
(Example 8)
The sensor array of FIG. 18 was manufactured. Using a polyimide film on a glass substrate as the insulating substrate 1, Mo is formed by film formation, resist film formation, pattern exposure, development, etching, and resist removal, and the gate electrodes G1, G2, G3, G4, G5, scanning wiring 12, The reset wiring 13 was formed. Next, the photosensitive acrylic was formed into a film, exposed to a pattern, and developed to form a gate insulating film 3 with an opening. Further, the amorphous InGaZnO was formed by film formation, resist film formation, pattern exposure, development, etching, and resist removal to form semiconductor patterns SC1, SC2, SC3, SC4, and SC5. Then, a SiO 2 pattern was formed as an etching stopper layer on the channel portions of the semiconductor patterns SC1, SC2, SC3, SC4, and SC5 (not shown).
 さらに、Moを成膜・レジスト成膜・パターン露光・現像・エッチング・レジスト除去して、ソース電極S1、S2、S3、S4、S5、ドレイン電極D1、D2、D3、D4、D5、接続配線17(S1-D2間)、ビア配線18L(D3-G1間)、接続配線17(S4-D5間)、信号配線15、ドレイン配線14、ビア配線18L(共通配線11-G4間配線の下半分)を形成した。 Further, Mo is formed into a film, resist is formed, pattern is exposed, developed, etched, and resist is removed, and the source electrodes S1, S2, S3, S4, S5, drain electrodes D1, D2, D3, D4, D5, and connection wiring 17 are formed. (Between S1-D2), via wiring 18L (between D3-G1), connection wiring 17 (between S4-D5), signal wiring 15, drain wiring 14, via wiring 18L (lower half of common wiring 11-G4 wiring) Was formed.
 そして、感光性アクリルを成膜・パターン露光・現像して、開口付きの層間絶縁膜7を形成した。次に、Agペーストをスクリーン印刷して、画素電極8、ビア配線18U(画素電極8-D1間)、共通配線11、ビア配線18U(共通配線11-G4間の上半分)を形成した。この時、画素電極8はドレイン電極D3およびゲート電極G1に接続され、共通配線11はゲート電極G4に接続された。 Then, the photosensitive acrylic was formed into a film, exposed to a pattern, and developed to form an interlayer insulating film 7 with an opening. Next, the Ag paste was screen-printed to form the pixel electrode 8, the via wiring 18U (between the pixel electrodes 8 and D1), the common wiring 11, and the via wiring 18U (the upper half between the common wiring 11 and G4). At this time, the pixel electrode 8 was connected to the drain electrode D3 and the gate electrode G1, and the common wiring 11 was connected to the gate electrode G4.
 さらに、片側全面にMoが付いた感圧媒体(ポリフッ化ビニリデン3フッ化エチレン共重合体、分極処理済)を、感圧媒体側が画素電極8に接合するように設置して、センサ部109(感圧媒体9)および共通電極10とした。また、絶縁基板1であるポリイミド膜から、ガラス基板を剥離した。 Further, a pressure-sensitive medium having Mo on the entire surface of one side (polyvinylidene fluoride triethylene ethylene copolymer, polarization-treated) is installed so that the pressure-sensitive medium side is bonded to the pixel electrode 8, and the sensor unit 109 ( The pressure-sensitive medium 9) and the common electrode 10 were used. Further, the glass substrate was peeled off from the polyimide film which is the insulating substrate 1.
 ここで、第1の薄膜トランジスタのゲート・ドレイン間容量(画素電極・ドレイン配線間容量を含む)Cgd1=1.53pF、第3の薄膜トランジスタのゲート・ドレイン間容量(画素電極・ドレイン配線間容量を含む)Cgd3=0.69pF、画素電極8・共通電極10間容量Cp=63.1pFであった。 Here, the gate-drain capacitance of the first thin film transistor (including the capacitance between the pixel electrode and the drain wiring) Cgd1 = 1.53pF, and the gate-drain capacitance of the third thin film transistor (including the capacitance between the pixel electrode and the drain wiring). ) Cgd3 = 0.69pF, and the capacitance between the pixel electrode 8 and the common electrode 10 was Cp = 63.1pF.
 図26の検出回路を用い、最初に、共通電極10に+1V、ドレイン配線14に0Vの状態で、リセット配線13にオン電圧+15Vを印加した。次に、リセット配線13の電位をオフ電圧-15Vに、ドレイン配線14の電位を+15Vにした。 Using the detection circuit of FIG. 26, first, an on-voltage + 15V was applied to the reset wiring 13 with + 1V to the common electrode 10 and 0V to the drain wiring 14. Next, the potential of the reset wiring 13 was set to an off voltage of -15V, and the potential of the drain wiring 14 was set to + 15V.
 走査配線12のうち1本にオン電圧+15V、他にオフ電圧-15Vを印加して、1画素のうち感圧側の信号を得た。アナログスイッチ22を切り替えることで、非感圧側の信号を得た。さらにアナログスイッチ22を切り替えることで、1行分の感圧側および非感圧側の信号を得た。走査配線12のオン電圧位置を変えて同様の操作を行い、全画素の感圧側および非感圧側の信号を得た。感圧側信号から非感圧側信号を引いた値から、各画素の圧力がわかる。また、VresetオフかつVdd印加時の画素電極8の電位変化は0.027Vであり、感圧媒体9の最大電位変化量(圧力800kPa時)が4Vなので、VresetオフかつVdd印加時の画素電極8の電位変化による誤差は最大電位変化量
の0.7%と充分に小さい。なお、検出回路のVbase=1.0[V]とした。
An on-voltage of + 15V and an off-voltage of -15V were applied to one of the scanning wires 12, and a signal on the pressure-sensitive side of one pixel was obtained. By switching the analog switch 22, a signal on the non-pressure sensitive side was obtained. Further, by switching the analog switch 22, signals on the pressure-sensitive side and the non-pressure-sensitive side for one line were obtained. The same operation was performed by changing the on-voltage position of the scanning wiring 12, and signals on the pressure-sensitive side and the non-pressure-sensitive side of all the pixels were obtained. The pressure of each pixel can be found from the value obtained by subtracting the non-pressure sensitive signal from the pressure sensitive signal. Further, since the potential change of the pixel electrode 8 when Vreset is off and Vdd is applied is 0.027V and the maximum potential change amount of the pressure sensitive medium 9 (at a pressure of 800 kPa) is 4V, the pixel electrode 8 when Vreset is off and Vdd is applied is 4V. The error due to the potential change is 0.7% of the maximum potential change, which is sufficiently small. The detection circuit was set to Vbase = 1.0 [V].
(比較例1)
 図30の信号検出回路を作製した。切替回路100は8入力1出力のアナログマルチプレクサを8個用い、負荷抵抗122は1MΩの金属皮膜抵抗、電圧検出アンプ123はオペアンプによるボルテージフォロワ、ADコンバータ124は0~+5V入力で0~255レベル(8bit)出力とした。この回路には、負荷抵抗122と電圧検出アンプ123を64個用いた。この回路は、64本の信号配線15を有するセンサアレイに対応する。
(Comparative Example 1)
The signal detection circuit of FIG. 30 was manufactured. The switching circuit 100 uses eight analog multiplexers with 8 inputs and 1 output, the load resistance 122 is a metal film resistance of 1 MΩ, the voltage detection amplifier 123 is a voltage follower using an operational amplifier, and the AD converter 124 is 0 to 255 levels with 0 to + 5 V inputs ( 8 bits) Output. A load resistor 122 and 64 voltage detection amplifiers 123 were used in this circuit. This circuit corresponds to a sensor array having 64 signal wires 15.
 マイコンを用いて切替回路100を制御し、同マイコンでADコンバータ124も制御し、1行64列の圧力センサアレイの信号を検出した。ADコンバータ124の測定時間を(準備時間104μs+実計測時間52μs)=156μsとし、切替回路100の出力の応答の時定数は500μs程度であった。切替回路100の出力の応答の時定数が、ADコンバータ測定時間=156μsに比べて大きいので、信号が安定せず測定精度が悪かった。 The switching circuit 100 was controlled by using a microcomputer, and the AD converter 124 was also controlled by the same microcomputer to detect the signal of the pressure sensor array of 1 row and 64 columns. The measurement time of the AD converter 124 was (preparation time 104 μs + actual measurement time 52 μs) = 156 μs, and the time constant of the output response of the switching circuit 100 was about 500 μs. Since the time constant of the output response of the switching circuit 100 is larger than the AD converter measurement time = 156 μs, the signal is not stable and the measurement accuracy is poor.
(比較例2)
 実施例2の信号検出回路を用いて、図4の信号検出方法によって、8行64列の圧力センサアレイの信号を検出した。ADコンバータ25の測定時間を(準備時間104μs+実計測時間52μs)=156μsとし、第2の切替回路102の出力の応答の時定数は3μs程度、第1の切替回路101の出力の応答の時定数は500μs程度であった。第1の切替回路101の出力の応答の時定数が、ADコンバータ測定時間=156μsに比べて大きいので、図4の信号検出方法によって、信号が安定せず測定精度が悪かった。
(Comparative Example 2)
Using the signal detection circuit of Example 2, the signal of the pressure sensor array of 8 rows and 64 columns was detected by the signal detection method of FIG. The measurement time of the AD converter 25 is (preparation time 104 μs + actual measurement time 52 μs) = 156 μs, the time constant of the output response of the second switching circuit 102 is about 3 μs, and the time constant of the output response of the first switching circuit 101. Was about 500 μs. Since the time constant of the output response of the first switching circuit 101 is larger than the AD converter measurement time = 156 μs, the signal is not stable and the measurement accuracy is poor by the signal detection method of FIG.
 本開示は、各種センサアレイ用の信号検出回路や駆動検出回路として利用できる。また、電位差が変化するタイプのセンサ部を用いた各種センサアレイに利用できる。さらには、健康状態推定システムを含むセンサシステムに利用できる。 This disclosure can be used as a signal detection circuit or a drive detection circuit for various sensor arrays. Further, it can be used for various sensor arrays using a type of sensor unit in which the potential difference changes. Furthermore, it can be used for sensor systems including a health condition estimation system.
1  … 絶縁基板
G1、G2、G3、G4、G5  … ゲート電極
3  … ゲート絶縁膜
SC1、SC2、SC3、SC4、SC5  … 半導体パターン
S1、S2、S3、S4、S5  … ソース電極
D1、D2、D3、D4、D5  … ドレイン電極
5  … 制御回路
6  … 駆動回路
7  … 層間絶縁膜
8  … 画素電極
9  … 感圧媒体(電位差が変化するタイプ)
10  … 共通電極
11  … 共通配線
12  … 走査配線
13  … リセット配線
14  … ドレイン配線
15  … 信号配線
16  … リファレンス信号配線
17(S1-D2、S4-D5)  … 接続配線
18L、18U  … ビア配線
20、21  … 負荷抵抗
22  … アナログスイッチ
24  … 差動増幅回路
25  … アナログ-デジタル変換回路(ADコンバータ)
31  … 薄膜トランジスタ
32  … 走査配線
33  … 信号配線
36  … 電源配線
38  … TFT
39  … 感圧媒体(抵抗が変化するタイプ)
40  … 電流制限回路
41  … 第1の薄膜トランジスタ
42  … 第2の薄膜トランジスタ
43  … ドレイン抵抗
44  … 走査配線
45  … 信号配線
48  … 制御信号(デジタル配線)
49  … カウンタ
53、54  …電圧検出アンプ
100  … 切替回路
101  … 第1の切替回路
102  … 第2の切替回路
103  … 第3の切替回路
109  … センサ部
115  … 信号配線
122  … 負荷抵抗
123  … 電圧検出アンプ
124  … ADコンバータ
125  … 制御回路
126  … 駆動回路
127  … 走査配線
130  … 感圧媒体(抵抗が変化するタイプ)
140  … 無機感圧媒体(電位差が変化するタイプ)
200  … 介護センサ装置
200A  … 圧力センサアレイ
200G  … 駆動回路
200S  … 信号検出回路
200C  … 制御・通信回路
200WG  … 駆動配線間接続部品
200WS  … 信号配線間接続部品
201  … ベッド
T1  … TFT1
T2  … TFT2
T3  … TFT3
T4  … TFT4
1 ... Insulation substrate G1, G2, G3, G4, G5 ... Gate electrode 3 ... Gate insulating film SC1, SC2, SC3, SC4, SC5 ... Semiconductor pattern S1, S2, S3, S4, S5 ... Source electrodes D1, D2, D3 , D4, D5 ... Drain electrode 5 ... Control circuit 6 ... Drive circuit 7 ... Interlayer insulating film 8 ... Pixel electrode 9 ... Pressure sensitive medium (type in which the potential difference changes)
10 ... Common electrode 11 ... Common wiring 12 ... Scanning wiring 13 ... Reset wiring 14 ... Drain wiring 15 ... Signal wiring 16 ... Reference signal wiring 17 (S1-D2, S4-D5) ... Connection wiring 18L, 18U ... Via wiring 20, 21 ... Load resistance 22 ... Analog switch 24 ... Differential amplification circuit 25 ... Analog-digital conversion circuit (AD converter)
31 ... Thin film transistor 32 ... Scanning wiring 33 ... Signal wiring 36 ... Power supply wiring 38 ... TFT
39 ... Pressure-sensitive medium (type in which resistance changes)
40 ... Current limiting circuit 41 ... First thin film transistor 42 ... Second thin film transistor 43 ... Drain resistance 44 ... Scanning wiring 45 ... Signal wiring 48 ... Control signal (digital wiring)
49 ... Counters 53, 54 ... Voltage detection amplifier 100 ... Switching circuit 101 ... First switching circuit 102 ... Second switching circuit 103 ... Third switching circuit 109 ... Sensor unit 115 ... Signal wiring 122 ... Load resistance 123 ... Voltage Detection amplifier 124 ... AD converter 125 ... Control circuit 126 ... Drive circuit 127 ... Scanning wiring 130 ... Pressure-sensitive medium (type in which resistance changes)
140 ... Inorganic pressure-sensitive medium (type in which the potential difference changes)
200 ... Nursing sensor device 200A ... Pressure sensor array 200G ... Drive circuit 200S ... Signal detection circuit 200C ... Control / communication circuit 200WG ... Drive wiring connection parts 200WS ... Signal wiring connection parts 201 ... Bed T1 ... TFT1
T2 ... TFT2
T3 ... TFT3
T4 ... TFT4

Claims (18)

  1.  複数の走査配線と、複数の信号配線と、のマトリクスの交点に対応したセンサ部の外部刺激を検出するセンサアレイ用の、信号検出回路であって、
     複数の前記信号配線がM本ずつM個のブロックに分けられており、
     M個の前記ブロックのそれぞれの中には、
      M本の前記信号配線が入力に接続された第1の切替回路と、
      前記第1の切替回路の出力に接続された負荷抵抗および電圧検出アンプと、が設けられ、
     M個の前記ブロックからのそれぞれの出力が入力に接続された第2の切替回路と、
     前記第2の切替回路の出力に接続されたADコンバータと、
    を有する信号検出回路。
    A signal detection circuit for a sensor array that detects an external stimulus of the sensor unit corresponding to the intersection of a matrix of a plurality of scanning wires and a plurality of signal wires.
    The plurality of signal wirings are divided into M 2 blocks, M 1 each.
    In each of the two M blocks,
    A first switching circuit M 1 present in the signal line is connected to the input,
    A load resistor and a voltage detection amplifier connected to the output of the first switching circuit are provided.
    M A second switching circuit in which each output from the two blocks is connected to an input,
    With the AD converter connected to the output of the second switching circuit,
    Signal detection circuit with.
  2.  前記第1の切替回路はアナログマルチプレクサである、請求項1に記載の信号検出回路。 The signal detection circuit according to claim 1, wherein the first switching circuit is an analog multiplexer.
  3.  請求項1または2に記載の信号検出回路と、制御回路と、駆動回路と、を備え、
     前記駆動回路は前記走査配線にオン電圧またはオフ電圧を印加する回路であり、
     前記第1の切替回路、前記第2の切替回路、前記ADコンバータ、および前記駆動回路は、前記制御回路によって制御される、駆動検出回路。
    The signal detection circuit, the control circuit, and the drive circuit according to claim 1 or 2 are provided.
    The drive circuit is a circuit that applies an on voltage or an off voltage to the scanning wiring.
    A drive detection circuit in which the first switching circuit, the second switching circuit, the AD converter, and the drive circuit are controlled by the control circuit.
  4.  前記制御回路は、カウンタを介して前記第1の切替回路を制御する、請求項3に記載の駆動検出回路。 The drive detection circuit according to claim 3, wherein the control circuit controls the first switching circuit via a counter.
  5.  前記制御回路は、
     M個の前記ブロックのうちの1つのブロックにおいて、
      前記第1の切替回路によって選択されている1つの信号配線を、前記1つの信号配線とは異なる他の信号配線に切り替えた後、前記他の信号配線の信号の測定を行う前に、
     前記1つのブロックとは異なる他のブロックにおいて、
      前記第1の切替回路によって選択されている1つの信号配線の信号の測定を1回以上行う、請求項3または4に記載の駆動検出回路。
    The control circuit
    In one block of the M 2 pieces of the blocks,
    After switching one signal wiring selected by the first switching circuit to another signal wiring different from the one signal wiring, before measuring the signal of the other signal wiring,
    In another block different from the one block
    The drive detection circuit according to claim 3 or 4, wherein the signal of one signal wiring selected by the first switching circuit is measured one or more times.
  6.  前記制御回路は、
     前記駆動回路に、複数の前記走査配線から選択された1本の走査配線にオン電圧を印加させる第1の処理と、
     前記オン電圧の印加後、一定時間の待機と、
     前記第2の切替回路によって選択された1つのブロックにおいて、前記第1の切替回路によって選択されている1つの信号配線の信号を前記ADコンバータを介して読み出し、前記1つのブロックの第1の切替回路によって前記1つの信号配線とは異なる他の信号線を選択した後、前記1つのブロックの前記他の信号配線の信号を読み出す前に、少なくとも、前記第2の切替回路によって前記1つのブロックとは異なる他のブロックを選択する手順と、前記他のブロックの信号を読み出す手順と、前記他のブロックの第1の切替回路を切替える手順と、の繰り返しを有し、これらのプロセスにより、前記選択された1本の走査配線に対応する1行分の前記センサ部の信号を順に読み出す第2の処理と、
     前記駆動回路に、前記第2の処理の終了後に前記選択された1本の走査配線にオフ電圧を印加させる第3の処理とを実行可能であり、
     全ての前記走査配線について、前記第1の処理、前記待機、前記第2の処理及び前記第3の処理を繰り返すことにより、全ての前記センサ部の信号を読み出す、請求項5に記載
    の駆動検出回路。
    The control circuit
    A first process of applying an on-voltage to the drive circuit to one scanning wiring selected from the plurality of scanning wirings,
    After applying the on-voltage, wait for a certain period of time,
    In one block selected by the second switching circuit, the signal of one signal wiring selected by the first switching circuit is read out through the AD converter, and the first switching of the one block is performed. After selecting another signal line different from the one signal wiring by the circuit, and before reading the signal of the other signal wiring of the one block, at least by the second switching circuit, the one block Has a repetition of a procedure of selecting a different other block, a procedure of reading a signal of the other block, and a procedure of switching the first switching circuit of the other block, and the selection is performed by these processes. A second process of sequentially reading the signals of the sensor unit for one line corresponding to one scanning wiring, and
    It is possible to execute the third process of applying an off voltage to the selected scanning wiring to the drive circuit after the completion of the second process.
    The drive detection according to claim 5, wherein all the signals of the sensor unit are read out by repeating the first process, the standby, the second process, and the third process for all the scanning wirings. circuit.
  7.  前記待機の時間が、前記ADコンバータの読取時間の(M-1)倍以上の長さである、請求項6に記載の駆動検出回路。 The time of waiting, the a (M 2 -1) times the length of the AD converter reading time, driving detection circuit according to claim 6.
  8.  M本の前記信号配線の各々に並行して設けられる、前記センサ部の外部刺激の影響を受けないM本のリファレンス信号配線をさらに有し、
     M本の前記リファレンス信号配線はM本ずつM組の前記ブロックに分けられ、
     M個の前記ブロックのそれぞれの中には、
      M本の前記リファレンス信号配線が入力に接続された第3の切替回路と、
      前記第3の切替回路の出力に接続された負荷抵抗およびリファレンス電圧検出アンプと、
      差動増幅回路と、が設けられており、
     前記電圧検出アンプの出力が前記差動増幅回路の+入力に接続され、
     前記リファレンス電圧検出アンプの出力が前記差動増幅回路の-入力に接続された、請求項1または2に記載の信号検出回路。
    Further, it has M reference signal wirings which are provided in parallel with each of the M signal wirings and are not affected by the external stimulus of the sensor unit.
    The reference signal lines of the M is divided into M 2 pairs of the blocks one by one M,
    In each of the two M blocks,
    A third switching circuit M 1 present in the reference signal line is connected to the input,
    The load resistance and reference voltage detection amplifier connected to the output of the third switching circuit,
    A differential amplifier circuit is provided,
    The output of the voltage detection amplifier is connected to the + input of the differential amplifier circuit,
    The signal detection circuit according to claim 1 or 2, wherein the output of the reference voltage detection amplifier is connected to the-input of the differential amplifier circuit.
  9.  請求項8に記載の信号検出回路と、制御回路と、駆動回路と、を備え、
     前記駆動回路は前記走査配線にオン電圧またはオフ電圧を印加する回路であり、
     前記第1の切替回路、前記第3の切替回路、前記第2の切替回路、前記ADコンバータ、および前記駆動回路は、前記制御回路によって制御される、駆動検出回路。
    The signal detection circuit, a control circuit, and a drive circuit according to claim 8 are provided.
    The drive circuit is a circuit that applies an on voltage or an off voltage to the scanning wiring.
    A drive detection circuit in which the first switching circuit, the third switching circuit, the second switching circuit, the AD converter, and the drive circuit are controlled by the control circuit.
  10.  前記制御回路は、
     M個の前記ブロックのうちのいずれか1つにおいて、
      前記第1の切替回路によって選択されている1つの信号配線および前記1つの信号配線に対応するリファレンス信号配線を、前記1つの信号配線および前記1つの信号配線に対応するリファレンス信号配線とは異なる、他の信号配線および他の信号配線に対応する他のリファレンス信号配線に切り替えた後、前記他の信号配線および他のリファレンス信号配線の信号差の測定を行う前に、
     前記1つのブロックとは異なる他のブロックにおいて、
      前記第1の切替回路によって選択されている1つの信号配線および前記1つの信号配線に対応するリファレンス信号配線の信号差の測定を1回以上行う、請求項9に記載の駆動検出回路。
    The control circuit
    In any one of the M 2 pieces of the blocks,
    The one signal wiring selected by the first switching circuit and the reference signal wiring corresponding to the one signal wiring are different from the one signal wiring and the reference signal wiring corresponding to the one signal wiring. After switching to the other signal wiring and other reference signal wiring corresponding to the other signal wiring, and before measuring the signal difference between the other signal wiring and the other reference signal wiring,
    In another block different from the one block
    The drive detection circuit according to claim 9, wherein the signal difference between the one signal wiring selected by the first switching circuit and the reference signal wiring corresponding to the one signal wiring is measured one or more times.
  11.  前記制御回路は、
     前記駆動回路に、複数の前記走査配線から選択された1本の走査配線にオン電圧を印加させる第1の処理と、
     前記オン電圧の印加後、一定時間の待機と、
     前記第2の切替回路によって選択された1つのブロックにおいて、前記第1および第3の切替回路によって選択されている1つの信号配線と前記1つの信号配線に対応するリファレンス信号配線との信号差を前記ADコンバータを介して読み出し、前記1つのブロックの第1の切替回路および第3の切替回路によって前記1つの信号配線と前記1つの信号配線に対応するリファレンス信号配線とは異なる他の信号配線とその信号線に対応するリファレンス信号配線を選択した後、前記1つのブロックの前記他の信号配線と前記他のリファレンス信号配線との信号差を読み出す前に、少なくとも、前記他のブロックの信号差を読み出す手順と、前記第2の切替回路102を切替える手順と、前記他のブロックの第1および第3の切替回路を切替える手順と、の繰り返しを有し、これらのプロセスにより、前記選択された1本の走査配線に対応する1行分の前記センサ部の信号差を順に読み出す第2の処理と、
     前記駆動回路に、前記第2の処理の終了後に前記選択された1本の走査配線にオフ電圧を印加させる第3の処理とを実行可能であり、
     全ての前記走査配線について、前記第1の処理、前記待機、前記第2の処理及び前記第3の処理を繰り返すことにより、全ての前記センサ部の信号を読み出す、請求項10に記載の駆動検出回路。
    The control circuit
    A first process of applying an on-voltage to the drive circuit to one scanning wiring selected from the plurality of scanning wirings,
    After applying the on-voltage, wait for a certain period of time,
    In one block selected by the second switching circuit, the signal difference between one signal wiring selected by the first and third switching circuits and the reference signal wiring corresponding to the one signal wiring is obtained. Read through the AD converter, and the first switching circuit and the third switching circuit of the one block allow the one signal wiring and another signal wiring different from the reference signal wiring corresponding to the one signal wiring. After selecting the reference signal wiring corresponding to the signal line, at least the signal difference of the other block is set before reading the signal difference between the other signal wiring of the one block and the other reference signal wiring. The procedure of reading, the procedure of switching the second switching circuit 102, and the procedure of switching the first and third switching circuits of the other block are repeated, and the selected 1 is obtained by these processes. The second process of reading out the signal difference of the sensor unit for one line corresponding to the scanning wiring of the book in order, and
    It is possible to execute the third process of applying an off voltage to the selected scanning wiring to the drive circuit after the completion of the second process.
    The drive detection according to claim 10, wherein signals of all the sensor units are read out by repeating the first process, the standby, the second process, and the third process for all the scanning wirings. circuit.
  12.  複数の信号配線と、
     信号配線と交差する複数の走査配線と、
     前記信号配線と前記走査配線の交点のそれぞれに対応して設けられ、画素電極と第1薄膜トランジスタと第2薄膜トランジスタを含む複数の画素部と、
     第1薄膜トランジスタのドレイン電極に給電するためのドレイン配線と、
     前記画素電極に接続されるセンサ部と、
     前記センサ部に接続される共通電極とを備え、
     前記画素電極は前記第1薄膜トランジスタのゲート電極に接続され、前記第1薄膜トランジスタのドレイン電極は前記ドレイン配線に接続され、前記第1薄膜トランジスタのソース電極は前記第2薄膜トランジスタのドレイン電極に接続され、前記第2薄膜トランジスタのゲート電極は前記走査配線に接続され、前記第2薄膜トランジスタのソース電極は前記信号配線に接続されている、センサアレイ。
    With multiple signal wiring
    Multiple scanning wires that intersect the signal wires,
    A plurality of pixel portions including a pixel electrode, a first thin film transistor, and a second thin film transistor, which are provided corresponding to each of the intersections of the signal wiring and the scanning wiring,
    Drain wiring for supplying power to the drain electrode of the first thin film transistor,
    The sensor unit connected to the pixel electrode and
    It is provided with a common electrode connected to the sensor unit.
    The pixel electrode is connected to the gate electrode of the first thin film transistor, the drain electrode of the first thin film transistor is connected to the drain wiring, and the source electrode of the first thin film transistor is connected to the drain electrode of the second thin film transistor. A sensor array in which the gate electrode of the second thin film transistor is connected to the scanning wiring and the source electrode of the second thin film transistor is connected to the signal wiring.
  13.  前記画素部はさらに第3薄膜トランジスタを含み、
     前記センサアレイは前記第3薄膜トランジスタのソース電極に給電するための共通配線と、前記第3薄膜トランジスタのゲート電極に給電するためのリセット配線とを有し、
     前記第3薄膜トランジスタのドレイン電極は前記画素電極に接続され、前記第3薄膜トランジスタのソース電極は前記共通配線に接続され、前記第3薄膜トランジスタのゲート電極は前記リセット配線に接続されている、請求項12のセンサアレイ。
    The pixel portion further includes a third thin film transistor.
    The sensor array has a common wiring for supplying power to the source electrode of the third thin film transistor and a reset wiring for supplying power to the gate electrode of the third thin film transistor.
    12. The drain electrode of the third thin film transistor is connected to the pixel electrode, the source electrode of the third thin film transistor is connected to the common wiring, and the gate electrode of the third thin film transistor is connected to the reset wiring. Sensor array.
  14.  前記画素部はさらに第4薄膜トランジスタと第5薄膜トランジスタを含み、
     前記センサアレイは前記信号配線に並行する複数のリファレンス信号配線と、前記第4薄膜トランジスタのゲート電極に給電するための共通配線とを有し、
     前記第4薄膜トランジスタのゲート電極は前記共通配線に接続され、前記第4薄膜トランジスタのドレイン電極は前記ドレイン配線に接続され、前記第4薄膜トランジスタのソース電極は前記第5薄膜トランジスタのドレイン電極に接続され、前記第5薄膜トランジスタのゲート電極は前記走査配線に接続され、第5薄膜トランジスタのソース電極は前記リファレンス信号配線に接続されている、請求項12または13に記載のセンサアレイ。
    The pixel portion further includes a fourth thin film transistor and a fifth thin film transistor.
    The sensor array has a plurality of reference signal wirings parallel to the signal wiring and common wiring for supplying power to the gate electrode of the fourth thin film transistor.
    The gate electrode of the fourth thin film transistor is connected to the common wiring, the drain electrode of the fourth thin film transistor is connected to the drain wiring, and the source electrode of the fourth thin film transistor is connected to the drain electrode of the fifth thin film transistor. The sensor array according to claim 12 or 13, wherein the gate electrode of the fifth thin film transistor is connected to the scanning wiring, and the source electrode of the fifth thin film transistor is connected to the reference signal wiring.
  15.  前記センサ部が有機圧電体である、請求項12~14のいずれかに記載のセンサアレイ。 The sensor array according to any one of claims 12 to 14, wherein the sensor unit is an organic piezoelectric material.
  16.  前記第1~第5の薄膜トランジスタは絶縁基板上に設けられ、ゲート電極と、ゲート絶縁膜と、半導体と、ソース電極と、ドレイン電極とを有し、前記第1~第5の薄膜トランジスタ上に層間絶縁膜を有し、前記画素電極は少なくとも第1の薄膜トランジスタ上の前記層間絶縁膜の上に設けられ、前記絶縁基板と前記ゲート絶縁膜と前記層間絶縁膜は有機絶縁物が主成分である、請求項15に記載のセンサアレイ。 The first to fifth thin film transistors are provided on an insulating substrate, have a gate electrode, a gate insulating film, a semiconductor, a source electrode, and a drain electrode, and are laminated on the first to fifth thin film transistors. It has an insulating film, the pixel electrode is provided on at least the interlayer insulating film on the first thin film transistor, and the insulating substrate, the gate insulating film, and the interlayer insulating film are mainly composed of an organic insulating material. The sensor array according to claim 15.
  17.  画素電極は導電性粒子と有機バインダの混合体である、請求項16に記載のセンサアレイ。 The sensor array according to claim 16, wherein the pixel electrode is a mixture of conductive particles and an organic binder.
  18.  センサシステムであって、
     センサアレイと、
     信号検出回路とを備え、
     前記センサアレイは、
      複数の信号配線と、
      信号配線と交差する複数の走査配線と、
      前記信号配線と前記走査配線の交点のそれぞれに対応して設けられ、画素電極と第1薄膜トランジスタと第2薄膜トランジスタを含む複数の画素部と、
      第1薄膜トランジスタのドレイン電極に給電するためのドレイン配線と、
      前記画素電極に接続されるセンサ部 と、
      前記センサ部に接続される共通電極とを備え、
      前記画素電極は前記第1薄膜トランジスタのゲート電極に接続され、前記第1薄膜トランジスタのドレイン電極は前記ドレイン配線に接続され、前記第1薄膜トランジスタのソース電極は前記第2薄膜トランジスタのドレイン電極に接続され、前記第2薄膜トランジスタのゲート電極は前記走査配線に接続され、前記第2薄膜トランジスタのソース電極は前記信号配線に接続されており、
     前記信号検出回路は、
      複数の前記信号配線がM本ずつM個のブロックに分けられており、
      M個の前記ブロックのそれぞれの中には、
       M本の前記信号配線が入力に接続された第1の切替回路と、
       前記第1の切替回路の出力に接続された負荷抵抗および電圧検出アンプと、が設けられ、
      M個の前記ブロックからのそれぞれの出力が入力に接続された第2の切替回路と、
      前記第2の切替回路の出力に接続されたADコンバータとを有する、センサシステム。
    It ’s a sensor system,
    With the sensor array
    Equipped with a signal detection circuit
    The sensor array is
    With multiple signal wiring
    Multiple scanning wires that intersect the signal wires,
    A plurality of pixel portions including a pixel electrode, a first thin film transistor, and a second thin film transistor, which are provided corresponding to each of the intersections of the signal wiring and the scanning wiring,
    Drain wiring for supplying power to the drain electrode of the first thin film transistor,
    The sensor unit connected to the pixel electrode and
    It is provided with a common electrode connected to the sensor unit.
    The pixel electrode is connected to the gate electrode of the first thin film transistor, the drain electrode of the first thin film transistor is connected to the drain wiring, and the source electrode of the first thin film transistor is connected to the drain electrode of the second thin film transistor. The gate electrode of the second thin film transistor is connected to the scanning wiring, and the source electrode of the second thin film transistor is connected to the signal wiring.
    The signal detection circuit
    The plurality of signal wirings are divided into M 2 blocks, M 1 each.
    In each of the two M blocks,
    A first switching circuit M 1 present in the signal line is connected to the input,
    A load resistor and a voltage detection amplifier connected to the output of the first switching circuit are provided.
    M A second switching circuit in which each output from the two blocks is connected to an input,
    A sensor system having an AD converter connected to the output of the second switching circuit.
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JPH0259633A (en) * 1988-08-25 1990-02-28 Murata Mfg Co Ltd Detector for pressure distribution
JPH05215625A (en) * 1991-10-15 1993-08-24 Xerox Corp Capacitive tactile sensor array
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