WO2021200442A1 - Electronic circuit unit and battery pack - Google Patents

Electronic circuit unit and battery pack Download PDF

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Publication number
WO2021200442A1
WO2021200442A1 PCT/JP2021/012181 JP2021012181W WO2021200442A1 WO 2021200442 A1 WO2021200442 A1 WO 2021200442A1 JP 2021012181 W JP2021012181 W JP 2021012181W WO 2021200442 A1 WO2021200442 A1 WO 2021200442A1
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WO
WIPO (PCT)
Prior art keywords
electronic circuit
circuit unit
input
coupling capacitor
circuit
Prior art date
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PCT/JP2021/012181
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French (fr)
Japanese (ja)
Inventor
修 大橋
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三洋電機株式会社
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Publication of WO2021200442A1 publication Critical patent/WO2021200442A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries

Definitions

  • the present invention relates to an electronic circuit unit that switches between an operation mode and a power saving mode to reduce power consumption in the operation mode.
  • Electronic circuit units that switch between operation mode and power saving mode to reduce power consumption are used for various purposes.
  • a battery pack equipped with this electronic circuit unit has a feature that power consumption in an unused state can be reduced to prolong the battery usage time, and the storage period can be extended as a power saving mode in the storage state.
  • This electronic circuit unit includes a circuit module that switches the operation mode to the power saving mode, and this circuit module detects a start signal and switches the power saving mode to the operation mode. (See Patent Document 1)
  • the electronic circuit unit that switches between the operation mode and the power saving mode switches between the power saving mode and the operation mode by the external trigger signal input to the external input terminal.
  • the device equipped with the electronic circuit unit In the operation mode, the device equipped with the electronic circuit unit is used, and in the power saving mode, the power consumption is reduced.
  • the electronic circuit unit that switches between the operation mode and the power saving mode needs to switch the operation mode to the power saving mode depending on the usage environment.
  • the built-in microcomputer or the like determines this state and switches the operation mode to the power saving mode.
  • the electronic circuit unit is provided with a start terminal inside in order to switch to the operation mode by an external trigger signal input from the outside.
  • the electronic circuit unit switches to the operation mode when a trigger signal is input from the outside and a "High” level switching pulse signal is input to the start terminal.
  • the electronic circuit unit switches the operation mode to the power saving mode to reduce the power consumption under the condition that the electronic circuit unit is switched to the operation mode and is not used for a long time. If the start terminal is at the "High” level while the operation mode is switched to the power saving mode, the power saving mode cannot be switched. Therefore, the conventional electronic circuit unit cannot be switched to the power saving mode.
  • a short circuit is provided to set the "High" level to the "Low” level after a predetermined time.
  • the short circuit changes the switching element to the ON state, short-circuits the start terminal to the ground line, forcibly switches to "Low", and forcibly sets the High level of the start terminal to the Low level. It is said. Since a switching element such as an FET is turned on and the start terminal is held at the Low level, there is a drawback that power is consumed via the FET in the on state.
  • the present invention has been developed for the purpose of eliminating the above-mentioned drawbacks, and one of the purposes of the present invention is an extremely simple one-shot pulse circuit, which is activated after a predetermined time after switching to an operation mode. It is an object of the present invention to provide an electronic circuit unit capable of switching a terminal to a "Low" level and switching an operation mode to a power saving mode at a required timing.
  • a trigger circuit that outputs a switching pulse signal by an external trigger signal input to an external input terminal and a switching pulse signal of the trigger circuit are input to a start terminal to obtain a switching pulse signal. It is equipped with a circuit module that switches between the operation mode and the power saving mode.
  • the trigger circuit is a one-shot of a semiconductor switching element that is controlled by an external trigger signal and outputs a switching pulse signal to the start terminal, the load resistance of the semiconductor switching element, and the switching pulse signal input to the start terminal with a predetermined pulse width. It is equipped with a one-shot pulse circuit that makes a pulse.
  • the start terminal is connected to the connection between the semiconductor switching element and the load resistor, and the one-shot pulse circuit is a coupling capacitor connected between the input side of the semiconductor switching element and the external input terminal, and a coupling capacitor. It is composed of the charging resistance of, and the pulse width of the one-shot pulse is specified by the time constant of the coupling capacitor and the charging resistance. Since the semiconductor switching element is turned off according to the time constant, it is possible to reduce the power consumption due to the load resistance.
  • the battery pack according to an aspect of the present invention is a battery pack including the electronic circuit unit described above and a rechargeable battery, and supplies battery voltage to the electronic circuit unit and the semiconductor switching element.
  • the above electronic circuit unit reduces power consumption in the operation mode by making the one-shot pulse circuit an extremely simple circuit configuration consisting of a coupling capacitor and a charging resistor.
  • FIG. 1 It is a block diagram of the battery pack which concerns on one Embodiment of this invention. It is a timing chart which shows the operating state of the electronic circuit unit of the battery pack shown in FIG. It is a block diagram of a conventional battery pack.
  • FIG. 3 shows a block diagram of the conventional electronic circuit unit 80.
  • the electronic circuit unit 80 shown in this figure includes a circuit module 82 including a circuit for switching an operation mode, and a trigger circuit 83 for converting an external trigger signal into a switching pulse signal and inputting the external trigger signal to the start terminal 82a of the circuit module 82. ing.
  • the trigger circuit 83 connects the p-channel FET 85 to the positive side of the power supply line 91, and inputs the voltage of the load resistance 86 of the FET 85 to the start terminal 82a.
  • the trigger circuit 83 switches the FET 85 to the ON state by an external trigger signal input to the gate of the FET 85 of the p channel via the external input terminal 89 and the inverting circuit 88, and is energized by the FET 85 in the ON state to carry the load resistance 86.
  • the "High" signal generated in the above is input to the start terminal 82a of the circuit module 82 as a switching pulse signal.
  • the circuit module 82 switches the power saving mode to the operation mode at the timing when the switching pulse signal input to the start terminal 82a is switched from “Low” to "High".
  • the electronic circuit unit 80 of FIG. 3 has a short FET 95 that forcibly sets the voltage of the start terminal 82a to the “Low” level in order to set the start terminal 82a to the “Low” level after the set time after switching to the operation mode.
  • the short FET 95 is on / off controlled by the short circuit 96.
  • the short FET 95 is provided outside the circuit module 82, and the short circuit 96 is mounted on the circuit module 82.
  • the short circuit 96 When the short circuit 96 is switched to the operation mode and a predetermined time elapses, the short circuit 96 outputs an on voltage to the gate of the short FET 95 and switches to the on state.
  • the short FET 95 in the ON state connects the start terminal 82a to the ground line 92 and forcibly switches the “High” level of the start terminal 82a to “Low”.
  • the switching element such as the short FET 95 is turned on and the start terminal 82a is forcibly held at the Low level. Therefore, the short FET 95 in the on state consumes power to consume power in the operation mode. There is a drawback to increasing it.
  • the "High" of the switching pulse signal of the start terminal 82a can be switched to "Low” by the "short circuit 96", but the start terminal 82a is forcibly set to "Low”. Since the short FET 95 is energized to reach the "level”, the short FET 95 consumes power. Therefore, the electronic circuit unit 80 of FIG. 3 consumes power in an operation mode in which power consumption is required to be reduced as much as possible, and further circuits a short FET 95 and a short circuit 96 for controlling the short FET 95 on and off. Since it is necessary to provide the module 82, the circuit configuration becomes complicated and the manufacturing cost becomes high.
  • a trigger circuit that outputs a switching pulse signal by an external trigger signal input to an external input terminal and a switching pulse signal of the trigger circuit are input to a start terminal for switching. It is equipped with a circuit module that switches between operation mode and power saving mode with a pulse signal.
  • the trigger circuit is a one-shot of a semiconductor switching element that is controlled by an external trigger signal and outputs a switching pulse signal to the start terminal, the load resistance of the semiconductor switching element, and the switching pulse signal input to the start terminal with a predetermined pulse width. It is equipped with a one-shot pulse circuit that makes a pulse.
  • the start terminal is connected to the connection between the semiconductor switching element and the load resistor, and the one-shot pulse circuit is coupled with a coupling capacitor connected between the input side of the semiconductor switching element and the external input terminal. It is composed of the charging resistance of the capacitor, and the pulse width of the one-shot pulse is specified by the time constant of the coupling capacitor and the charging resistance.
  • the above electronic circuit unit realizes a one-shot pulse circuit with an extremely simple circuit consisting of a coupling capacitor and a charging resistor. Therefore, while making the circuit configuration extremely simple, the power consumption of the circuit can be reduced in the operation mode. It has the advantage of extremely low power consumption.
  • the electronic circuit unit adjusts the pulse width of the one-shot pulse with a time constant consisting of the product of the capacitance of the coupling capacitor and the electrical resistance of the charging resistor.
  • the electronic circuit unit of the second embodiment of the present invention has a time constant in which the capacitance of the coupling capacitor and the electrical resistance of the charging resistor set the pulse width of the one-shot pulse to 1 msec or more.
  • the electronic circuit unit of the third embodiment of the present invention uses a semiconductor switching element as an FET.
  • the electronic circuit unit of the fourth embodiment of the present invention includes a charging resistor connected between the input side of the semiconductor switching element and the coupling capacitor, and the coupling capacitor is a series resistance of the charging resistor and the charging resistor. I am trying to charge it with.
  • a charging resistor is connected to an external input terminal and a power supply line.
  • the circuit module switches the power saving mode to the operation mode by the high level switching pulse signal, and switches the high level to the start terminal when the semiconductor switching element is on.
  • a pulse signal is input, and the one-shot pulse circuit charges the coupling capacitor with a charging resistor to change the starting terminal from High level to Low level.
  • FIG. 1 shows a battery pack 100 including an electronic circuit unit 10.
  • the electronic circuit unit 10 of the battery pack 100 is switched to an operation mode in a state where the battery pack 100 is connected to a connected device and charged / discharged, and a power saving mode in a state where charging / discharging does not continue, thereby reducing power consumption.
  • the electronic circuit unit 10 in the power saving mode is switched to the operation mode by an external trigger signal input from the connected device.
  • the electronic circuit unit 10 mounted on the battery pack 100 includes a circuit module 2 such as an analog front end (AFE) that mounts a protection circuit of the battery 1 and the like, and a trigger circuit 3 that switches the circuit module 2 to an operation mode.
  • the trigger circuit 3 sets the circuit module 2 as an operation mode by an external trigger signal input from a device to which the battery pack 100 is connected.
  • the trigger circuit 3 inputs a switching pulse signal for switching between “High” and “Low” with an external trigger signal to the start terminal 2a of the circuit module 2, and sets the circuit module 2 as the operation mode.
  • the circuit module 2 switched to the operation mode by the external trigger signal switches the circuit module 2 to the power saving mode to reduce the power consumption when a specific condition is satisfied, for example, when the unused state continues for a predetermined time.
  • the circuit module 2 is switched to the power saving mode by a signal from a microcomputer 4 or the like that determines that a specific condition is satisfied. If the start terminal 2a is at the "High" level at the timing of switching to the power saving mode in the microcomputer 4, the circuit module 2 holds the operation mode and cannot switch to the power saving mode. Therefore, the trigger circuit 3 inputs a "High" level switching pulse signal to the start terminal 2a, switches the circuit module 2 to the operation mode, and then controls the switching pulse signal to the "Low" level.
  • the trigger circuit 3 presets the semiconductor switching element 5 to which the external trigger signal is input, the load resistance 6 of the semiconductor switching element 5, and the “High” level of the switching pulse signal input to the start terminal 2a. It is provided with a one-shot pulse circuit 7 that switches to the "Low” level after an hour.
  • the one-shot pulse circuit 7 includes a coupling capacitor 13 connected to the input side of the semiconductor switching element 5, and a charging resistor 14 connected between the coupling capacitor 13 and the power supply line 11.
  • the semiconductor switching element 5 is a p-channel FET 5A.
  • the p-channel FET 5A is turned off when the on-voltage is not input from the coupling capacitor 13, and is turned on when the on-voltage is input from the coupling capacitor 13.
  • the p-channel FET 5A energizes the load resistor 6 only in the on state, and the load resistor 6 generates a voltage in the energized state and inputs a “High” level switching pulse signal to the start terminal 2a.
  • the "High" level switching pulse signal input to the start terminal 2a sets the circuit module 2 as the operation mode.
  • the p-channel FET 5A is turned on at the timing when a negative on voltage is input to the gate, and the circuit module 2 is set to the operation mode. Since the circuit module 2 is set to the operation mode at the "High" level of the external trigger signal, the trigger circuit 3 in FIG. 1 is placed on the input side of the p-channel FET 5A in order to turn on the p-channel FET 5A at this timing.
  • An inverting circuit 8 is connected to invert the external trigger signals "High” and “Low", and the signals are input to the gate of the p-channel FET 5A.
  • the inverting circuit 8 of FIG. 1 is a photocoupler 15 composed of a light emitting diode 16 and a phototransistor 17, in which a collector of the phototransistor 17 is connected to a power supply line 11 on the positive side via a pull-up resistor 18, and an emitter is a ground line. It is connected to 12.
  • the photocoupler 15 of the inversion circuit 8 the light emitting diode 16 is turned on by the external trigger signal "High", and the phototransistor 17 is turned on.
  • the phototransistor 17 in the ON state connects the pull-up resistor 18 to the ground line 12 to set the output to “Low”.
  • the photocoupler 15 When the light emitting diode 16 is not lit by the "Low” signal of the external trigger signal, the photocoupler 15 turns off the phototransistor 17 and outputs a "High” signal via the pull-up resistor 18.
  • the inverting circuit in the figure is a photocoupler, the inverting circuit is not limited to the photocoupler and may be composed of a switching element such as an FET.
  • the trigger circuit 3 that connects the inverting circuit 8 to the input side
  • the external trigger signal "High” is input to the external input terminal 19 of the inverting circuit 8
  • the power line 11 on the positive side is connected to the gate of the FET 5A of the p channel.
  • a negative on voltage is input and the FET 5A is turned on.
  • the p-channel FET 5A in the ON state inputs the "High" signal generated in the load resistor 6 to the start terminal 2a as a switching pulse signal, and sets the circuit module 2 as the operation mode.
  • the circuit module 2 may be switched from the operation mode to the power saving mode. This state occurs when the battery pack 100 does not supply power to the connected device for a long time.
  • the start terminal 2a is at the "High” level, the circuit module 2 cannot switch the operation mode to the power saving mode. Therefore, after switching to the operation mode so that the operation mode can be switched to the power saving mode, the start terminal 2a Must be at the "Low” level.
  • the trigger circuit 3 includes a one-shot pulse circuit 7 in order to forcibly switch the start terminal 2a from “High” to “Low” after the operation mode is switched.
  • the one-shot pulse circuit 7 switches the "High” level switching pulse signal to the "Low” level after a predetermined time, and sets the switching pulse signal as a one-shot pulse having a predetermined pulse width.
  • the one-shot pulse circuit 7 specifies the on-time of the p-channel FET 5A, and sets the switching pulse signal input to the start terminal 2a as a one-shot pulse.
  • the one-shot pulse circuit 7 is composed of a coupling capacitor 13 connected to the input side of the FET 5A and a charging resistor 14 of the coupling capacitor 13.
  • the charging resistor 14 is connected to the first charging resistor 14A which is connected between the coupling capacitor 13 and the gate of the FET 5A, and the gate of the FET 5A and the power supply line 11 are connected to each other. It is composed of a series resistance with the second charging resistance 14B.
  • the second charging resistor 14B connects the gate of the FET 5A to the power supply line 11 on the positive side and holds the FET 5A in the off state in the normal state.
  • the time constant of the coupling capacitor 13 and the charging resistor 14 is specified by the electrical resistance obtained by adding the electrical resistances of the first charging resistor 14A and the second charging resistor 14B.
  • the second charging resistor 14B can be used in combination with the input resistor that holds the gate voltage (VGS) of the FET 5A in the off state in the normal state.
  • the FET 5A has an input resistor between the gate and the source, and this input resistor is connected in parallel with the second charging resistor 14B to substantially reduce the electrical resistance of the second charging resistor 14B. Since the input resistance of the FET 5A is considerably large, this can be ignored and the time constant can be specified from the electrical resistances of the first charging resistance 14A and the second charging resistance 14B. However, when the input resistance of the FET 5A is large, the electric resistance of the second charging resistance 14B is specified in consideration of the input resistance.
  • the coupling capacitor 13 is in the "Low” state of the external trigger signal, that is, in the power saving mode, the voltage at both ends becomes the voltage of the power supply line 11 on the positive side, and the voltage becomes 0V, that is, the state of being discharged.
  • a "Low” signal is input from the inverting circuit 8 to one side of the coupling capacitor 13, the coupling capacitor 13 starts charging via the charging resistor 14, and the input voltage input to the gate of the p-channel FET 5A becomes. It drops momentarily and becomes "Low".
  • the voltage change of the coupling capacitor 13 specifies the on-time of the FET 5A, that is, the pulse width of the one-shot pulse.
  • the voltage change of the coupling capacitor 13 is specified by a time constant specified by the product of the capacitance of the coupling capacitor 13 and the electric resistance of the charging resistor 14. When the time constant becomes large, the voltage change of the coupling capacitor 13 becomes slow, so that the pulse width of the one-shot pulse becomes large, that is, the on-time of the p-channel FET 5A becomes long.
  • the time constants of the coupling capacitor 13 and the charging resistor 14 are set so that the pulse width of the one-shot pulse is, for example, 1 msec or more.
  • the on-time of the p-channel FET 5A is set to 1 msec or more, and the timing for holding the start terminal 2a at the “High” level is set to 1 msec or more.
  • the pulse width of the one-shot pulse can be increased by increasing the time constants of the coupling capacitor 13 and the charging resistor 14, that is, increasing the capacitance of the coupling capacitor 13 and the electrical resistance of the charging resistor 14.
  • FIG. 2 shows changes in the [A] external trigger signal, the [B] inverting circuit output signal, the [C] FET gate input voltage, and the [D] switching pulse signal in the electronic circuit unit 10 shown in FIG. It is a timing chart.
  • [C] of FIG. 2 shows the characteristic that the input voltage input from the coupling capacitor 13 to the gate of the p-channel FET 5A changes.
  • the input voltage input to the gate of the FET 5A is the timing at which the external trigger signal rises from “Low” to "High”, in other words, the output signal of the inverting circuit 8 changes from "High” to "Low”.
  • the voltage drops momentarily to "Low”, and then gradually rises to the voltage of the power supply line 11 on the positive side.
  • the p-channel FET 5A is held in the ON state when the difference between the input voltage of the gate and the voltage of the power supply line 11 on the positive side, that is, the gate voltage (VGS), which is the potential difference between the gate and the source, is larger than the cutoff voltage. Will be done. Therefore, when the gate voltage (VGS) of the p-channel FET 5A becomes smaller than the cutoff voltage, the gate input voltage becomes "High” and the p-channel FET 5A is switched to the off state.
  • VGS gate voltage
  • the on-time of the p-channel FET 5A is specified by the state in which the gate voltage (VGS) changes, that is, the time constant of the coupling capacitor 13 and the charging resistor 14.
  • VGS gate voltage
  • the time constant of the coupling capacitor 13 and the charging resistor 14 is such that the pulse width of the one-shot pulse is, for example, 1 msec or more and 100 msec or less, preferably 1 msec or more and 10 msec or less.
  • the pulse width of the one-shot pulse is lengthened, the capacitance of the coupling capacitor 13 and the electrical resistance of the charging resistor 14 become large, resulting in large parts and high cost. On the contrary, if the pulse width is too short, reliable switching is performed. Therefore, it is possible to switch to the operation mode without fail, and set the above range in consideration of the component cost.
  • the electronic circuit unit 10 of FIG. 1 switches between a power saving mode and an operation mode by the following operation, and switches the operation mode to the power saving mode.
  • An external trigger signal is input to the electronic circuit unit 10 from the connected device. As shown in [A] of FIG. 2, the external trigger signal changes from “Low” to “High” at the timing of switching from the power saving mode to the operation mode.
  • the external trigger signal is input to the coupling capacitor 13 of the trigger circuit 3 by inverting "High” and "Low” in the inverting circuit 8. As shown in [A] of FIG. 2, the external trigger signal rises from the “Low” level to the “High” level at the timing of switching the power saving mode to the operation mode, and is therefore input from the inverting circuit 8 to the coupling capacitor 13.
  • the signal changes from "High” to "Low” at the timing of switching to the operation mode, as shown in [B] of FIG.
  • the input voltage input to the gate of the FET 5A of the p channel is the voltage of the power supply line 11 on the positive side as shown in [C] of FIG. The voltage drops significantly to the minus side.
  • the p-channel FET 5A is switched to the on state by inputting a “Low” on voltage to the gate.
  • the p-channel FET 5A in the ON state energizes the load resistor 6 and inputs "High” signals generated at both ends of the load resistor 6 to the start terminal 2a of the circuit module 2 as a switching pulse signal.
  • the "High" switching pulse signal input to the operation mode switches the circuit module 2 to the operation mode.
  • the p-channel FET 5A is switched to the off state.
  • the p-channel FET 5A that has been turned off cuts off the current of the load resistor 6 and switches the switching pulse signal input to the start terminal 2a of the circuit module 2 to "Low".
  • the switching pulse signal input to the start terminal 2a is a one-shot pulse having a pulse width of the time from the timing when the p-channel FET 5A is turned on to the timing when it is switched off.
  • the activation terminal 2a Is set to "Low” so that the mode can be switched to the power saving mode.
  • the circuit module 2 in which the start terminal 2a is held at the "Low” level can switch the circuit module 2 to the power saving mode by the signal from the microcomputer 4 to reduce the power consumption.
  • the battery pack 100 shown in FIG. 1 includes an electronic circuit unit 10 having the above structure and a rechargeable battery 1.
  • the battery pack 100 supplies operating power from the built-in battery 1 to the circuit module 2, the semiconductor switching element 5, and the microcomputer 4 constituting the electronic circuit unit 10.
  • the present invention can be suitably used as an electronic circuit unit built in a battery pack that can switch between an operation mode and a power saving mode to reduce power consumption in the power saving mode.

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
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  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
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Abstract

The present invention switches a start terminal to "Low" after a prescribed time after switching to an operating mode using a simple one-shot pulse circuit.　An electronic circuit unit comprises: a trigger circuit (3) that outputs a switching pulse signal by using an external trigger signal; and a circuit module (2) that switches from an operating mode to a power-saving mode by the switching pulse signal inputted to a start terminal (2a). The trigger circuit (3) comprises: a semiconductor switching element (5) that is controlled by the external trigger signal and outputs the switching pulse signal; a load resistor (6) of the semiconductor switching element (5); and a one-shot pulse circuit (7) that converts the switching pulse signal into a one-shot pulse having a prescribed pulse width. The one-shot pulse circuit (7) is constituted by a coupling capacitor (13) connected to the input side of the semiconductor switching element (5), and a charging resistor (14) of the coupling capacitor (13), and the pulse width of the one-shot pulse is specified by a time constant of the coupling capacitor (13) and the charging resistance (14).

Description

電子回路ユニットと電池パックElectronic circuit unit and battery pack
　本発明は、動作モードと省電力モードを切り換えて、動作モードで電力消費を削減する
電子回路ユニットに関する。 The present invention relates to an electronic circuit unit that switches between an operation mode and a power saving mode to reduce power consumption in the operation mode.
　動作モードと省電力モードを切り換えて、電力消費を削減する電子回路ユニットは種々の用途に使用されている。たとえば、この電子回路ユニットを装備する電池パックは、使用されない状態での電力消費を削減して電池の使用時間を長くし、また保存状態で省電力モードとして保存期間を長くできる特長がある。この電子回路ユニットは、動作モードを省電力モードに切り換える回路モジュールを備えており、この回路モジュールが起動信号を検出して省電力モードを動作モードに切り換えている。（特許文献１参照） Electronic circuit units that switch between operation mode and power saving mode to reduce power consumption are used for various purposes. For example, a battery pack equipped with this electronic circuit unit has a feature that power consumption in an unused state can be reduced to prolong the battery usage time, and the storage period can be extended as a power saving mode in the storage state. This electronic circuit unit includes a circuit module that switches the operation mode to the power saving mode, and this circuit module detects a start signal and switches the power saving mode to the operation mode. (See Patent Document 1)
特開２０１７－０８３８０１号公報JP-A-2017-083801
　動作モードと省電力モードを切り換える電子回路ユニットは、外部入力端子に入力される外部トリガー信号で省電力モードと動作モードを切り換えている。動作モードは、電子回路ユニットを装備する機器を使用状態とし、省電力モードは使用しない状態で電力消費を削減する。動作モードと省電力モードを切り換えする電子回路ユニットは、使用環境によって、動作モードを省電力モードに切り換える必要がある。使用しない時間が長くなるなど、あらかじめ設定している条件を満足すると、内蔵するマイコン等でこの状態を判別して、動作モードを省電力モードに切り換えている。電子回路ユニットは、外部から入力される外部トリガー信号で動作モードに切り換えるために、内部に起動端子を設けている。電子回路ユニットは、外部からトリガー信号が入力されて、起動端子に”Ｈｉｇｈ”レベルの切換パルス信号が入力されると動作モードに切り換えている。電子回路ユニットは、動作モードに切り換えられた状態で、使用しない時間が長くなる等の条件では、動作モードを省電力モードに切り換えて電力消費を削減している。動作モードを省電力モードに切り換える状態で、起動端子が”Ｈｉｇｈ”レベルにあると、省電力モードに切り換えできないので、従来の電子回路ユニットは、動作モードに切り換えた後、一定の時間経過すると、起動端子を強制的に”Ｌｏｗ”に切り換えるために、”Ｈｉｇｈ”レベルを所定の時間後に”Ｌｏｗ”レベルとするショート回路を設けている。 The electronic circuit unit that switches between the operation mode and the power saving mode switches between the power saving mode and the operation mode by the external trigger signal input to the external input terminal. In the operation mode, the device equipped with the electronic circuit unit is used, and in the power saving mode, the power consumption is reduced. The electronic circuit unit that switches between the operation mode and the power saving mode needs to switch the operation mode to the power saving mode depending on the usage environment. When the preset conditions are satisfied, such as when the product is not used for a long time, the built-in microcomputer or the like determines this state and switches the operation mode to the power saving mode. The electronic circuit unit is provided with a start terminal inside in order to switch to the operation mode by an external trigger signal input from the outside. The electronic circuit unit switches to the operation mode when a trigger signal is input from the outside and a "High" level switching pulse signal is input to the start terminal. The electronic circuit unit switches the operation mode to the power saving mode to reduce the power consumption under the condition that the electronic circuit unit is switched to the operation mode and is not used for a long time. If the start terminal is at the "High" level while the operation mode is switched to the power saving mode, the power saving mode cannot be switched. Therefore, the conventional electronic circuit unit cannot be switched to the power saving mode. In order to forcibly switch the start terminal to "Low", a short circuit is provided to set the "High" level to the "Low" level after a predetermined time.
　ショート回路は、所定の時間経過すると、スイッチング素子をオン状態に換えて、起動端子をグランドラインに短絡して、強制的に”Ｌｏｗ”に切り換えて、起動端子のＨｉｇｈレベルを強制的にＬｏｗレベルとしている。ＦＥＴなどのスイッチング素子をオン状態として、起動端子をＬｏｗレベルに保持するので、オン状態のＦＥＴを経由して電力を消費する欠点がある。 When a predetermined time elapses, the short circuit changes the switching element to the ON state, short-circuits the start terminal to the ground line, forcibly switches to "Low", and forcibly sets the High level of the start terminal to the Low level. It is said. Since a switching element such as an FET is turned on and the start terminal is held at the Low level, there is a drawback that power is consumed via the FET in the on state.
　本発明は、さらに以上の欠点を解消することを目的に開発されたもので、本発明の目的の一は、極めて簡単なワンショットパルス回路で、動作モードに切り換えた後、所定の時間後に起動端子を”Ｌｏｗ”レベルに切り換えして、必要なタイミングにおいて、動作モードを省電力モードに切り換えできる電子回路ユニットを提供することにある。 The present invention has been developed for the purpose of eliminating the above-mentioned drawbacks, and one of the purposes of the present invention is an extremely simple one-shot pulse circuit, which is activated after a predetermined time after switching to an operation mode. It is an object of the present invention to provide an electronic circuit unit capable of switching a terminal to a "Low" level and switching an operation mode to a power saving mode at a required timing.
　本発明のある態様に係る電子回路ユニットは、外部入力端子に入力される外部トリガー信号で切換パルス信号を出力するトリガー回路と、トリガー回路の切換パルス信号が起動端子に入力されて、切換パルス信号で動作モードと省電力モードとを切り換える回路モジュールとを備えている。トリガー回路は、外部トリガー信号で制御されて起動端子に切換パルス信号を出力する半導体スイッチング素子と、半導体スイッチング素子の負荷抵抗と、起動端子に入力される切換パルス信号を所定のパルス幅のワンショットパルスとするワンショットパルス回路とを備えている。起動端子は、半導体スイッチング素子と負荷抵抗との接続部に接続され、ワンショットパルス回路は、半導体スイッチング素子の入力側と外部入力端子との間に接続してなるカップリングコンデンサと、カップリングコンデンサの充電抵抗とで構成されており、カップリングコンデンサと充電抵抗の時定数で、ワンショットパルスのパルス幅を特定している。時定数に応じて半導体スイッチング素子がオフ状態となるため、負荷抵抗による電力消費を削減することが可能となる。 In the electronic circuit unit according to an embodiment of the present invention, a trigger circuit that outputs a switching pulse signal by an external trigger signal input to an external input terminal and a switching pulse signal of the trigger circuit are input to a start terminal to obtain a switching pulse signal. It is equipped with a circuit module that switches between the operation mode and the power saving mode. The trigger circuit is a one-shot of a semiconductor switching element that is controlled by an external trigger signal and outputs a switching pulse signal to the start terminal, the load resistance of the semiconductor switching element, and the switching pulse signal input to the start terminal with a predetermined pulse width. It is equipped with a one-shot pulse circuit that makes a pulse. The start terminal is connected to the connection between the semiconductor switching element and the load resistor, and the one-shot pulse circuit is a coupling capacitor connected between the input side of the semiconductor switching element and the external input terminal, and a coupling capacitor. It is composed of the charging resistance of, and the pulse width of the one-shot pulse is specified by the time constant of the coupling capacitor and the charging resistance. Since the semiconductor switching element is turned off according to the time constant, it is possible to reduce the power consumption due to the load resistance.
　本発明のある態様に係る電池パックは、以上に記載される電子回路ユニットと、充電できる電池を備える電池パックであって、電子回路ユニットと半導体スイッチング素子に電池電圧を供給している。 The battery pack according to an aspect of the present invention is a battery pack including the electronic circuit unit described above and a rechargeable battery, and supplies battery voltage to the electronic circuit unit and the semiconductor switching element.
　以上の電子回路ユニットは、ワンショットパルス回路を、カップリングコンデンサと充電抵抗とからなる極めて簡単な回路構成として、動作モードにおける電力消費を削減する。 The above electronic circuit unit reduces power consumption in the operation mode by making the one-shot pulse circuit an extremely simple circuit configuration consisting of a coupling capacitor and a charging resistor.
本発明の一実施形態に係る電池パックのブロック図である。It is a block diagram of the battery pack which concerns on one Embodiment of this invention. 図１に示す電池パックの電子回路ユニットの動作状態を示すタイミングチャートである。It is a timing chart which shows the operating state of the electronic circuit unit of the battery pack shown in FIG. 従来の電池パックのブロック図である。It is a block diagram of a conventional battery pack.
　図３は、従来の電子回路ユニット８０のブロック図を示している。この図に示す電子回路ユニット８０は、動作モードを切り換える回路を備える回路モジュール８２と、外部トリガー信号を切換パルス信号に変換して、回路モジュール８２の起動端子８２ａに入力するトリガー回路８３とを備えている。トリガー回路８３は、電源ライン９１のプラス側にｐチャンネルのＦＥＴ８５を接続して、ＦＥＴ８５の負荷抵抗８６の電圧を起動端子８２ａに入力している。このトリガー回路８３は、外部入力端子８９と反転回路８８を介して、ｐチャンネルのＦＥＴ８５のゲートに入力される外部トリガー信号でＦＥＴ８５をオン状態に切り換え、オン状態のＦＥＴ８５に通電されて負荷抵抗８６に発生する”Ｈｉｇｈ”信号を切換パルス信号として回路モジュール８２の起動端子８２ａに入力している。回路モジュール８２は、起動端子８２ａに入力される切換パルス信号が、”Ｌｏｗ”から”Ｈｉｇｈ”に切り換えられるタイミングで、省電力モードを動作モードに切り換える。 FIG. 3 shows a block diagram of the conventional electronic circuit unit 80. The electronic circuit unit 80 shown in this figure includes a circuit module 82 including a circuit for switching an operation mode, and a trigger circuit 83 for converting an external trigger signal into a switching pulse signal and inputting the external trigger signal to the start terminal 82a of the circuit module 82. ing. The trigger circuit 83 connects the p-channel FET 85 to the positive side of the power supply line 91, and inputs the voltage of the load resistance 86 of the FET 85 to the start terminal 82a. The trigger circuit 83 switches the FET 85 to the ON state by an external trigger signal input to the gate of the FET 85 of the p channel via the external input terminal 89 and the inverting circuit 88, and is energized by the FET 85 in the ON state to carry the load resistance 86. The "High" signal generated in the above is input to the start terminal 82a of the circuit module 82 as a switching pulse signal. The circuit module 82 switches the power saving mode to the operation mode at the timing when the switching pulse signal input to the start terminal 82a is switched from "Low" to "High".
　図３の電子回路ユニット８０は、動作モードに切り換えた後、設定時間後に起動端子８２ａを”Ｌｏｗ”レベルとするために、起動端子８２ａの電圧を強制的に”Ｌｏｗ”レベルとするショートＦＥＴ９５を備えている。このショートＦＥＴ９５は、ショート回路９６によりオンオフ制御されている。ショートＦＥＴ９５は回路モジュール８２の外部に設けられて、ショート回路９６は回路モジュール８２に実装される。ショート回路９６は、動作モードに切り換えられて所定の時間経過すると、ショートＦＥＴ９５のゲートにオン電圧を出力してオン状態に切り換える。オン状態のショートＦＥＴ９５は、起動端子８２ａをグランドライン９２に接続して、起動端子８２ａの”Ｈｉｇｈ”レベルを強制的に”Ｌｏｗ”に切り換える。このショート回路９６は、ショートＦＥＴ９５などのスイッチング素子をオン状態として、起動端子８２ａを強制的にＬｏｗレベルに保持するので、オン状態のショートＦＥＴ９５が電力を消費して、動作モードでの消費電力を増加させる欠点がある。 The electronic circuit unit 80 of FIG. 3 has a short FET 95 that forcibly sets the voltage of the start terminal 82a to the “Low” level in order to set the start terminal 82a to the “Low” level after the set time after switching to the operation mode. I have. The short FET 95 is on / off controlled by the short circuit 96. The short FET 95 is provided outside the circuit module 82, and the short circuit 96 is mounted on the circuit module 82. When the short circuit 96 is switched to the operation mode and a predetermined time elapses, the short circuit 96 outputs an on voltage to the gate of the short FET 95 and switches to the on state. The short FET 95 in the ON state connects the start terminal 82a to the ground line 92 and forcibly switches the “High” level of the start terminal 82a to “Low”. In this short circuit 96, the switching element such as the short FET 95 is turned on and the start terminal 82a is forcibly held at the Low level. Therefore, the short FET 95 in the on state consumes power to consume power in the operation mode. There is a drawback to increasing it.
　図３の電子回路ユニット８０は、動作モードに切り換えられた後、起動端子８２ａの切換パルス信号の”Ｈｉｇｈ”を”ショート回路９６でＬｏｗ”に切り換えできるが、起動端子８２ａを強制的に”Ｌｏｗ”レベルとするためにショートＦＥＴ９５に通電するので、ショートＦＥＴ９５が電力を消費する。したがって、図３の電子回路ユニット８０は、電力消費を極力削減することが要求される動作モードにおいて電力を消費し、さらにショートＦＥＴ９５や、このショートＦＥＴ９５をオンオフに制御するためのショート回路９６を回路モジュール８２に設ける必要があって、回路構成が複雑となって製造コストが高くなる。 After the electronic circuit unit 80 of FIG. 3 is switched to the operation mode, the "High" of the switching pulse signal of the start terminal 82a can be switched to "Low" by the "short circuit 96", but the start terminal 82a is forcibly set to "Low". Since the short FET 95 is energized to reach the "level", the short FET 95 consumes power. Therefore, the electronic circuit unit 80 of FIG. 3 consumes power in an operation mode in which power consumption is required to be reduced as much as possible, and further circuits a short FET 95 and a short circuit 96 for controlling the short FET 95 on and off. Since it is necessary to provide the module 82, the circuit configuration becomes complicated and the manufacturing cost becomes high.
　以下、図面に基づいて本発明を詳細に説明する。なお、以下の説明では、必要に応じて特定の方向や位置を示す用語（例えば、「上」、「下」、及びそれらの用語を含む別の用語）を用いるが、それらの用語の使用は図面を参照した発明の理解を容易にするためであって、それらの用語の意味によって本発明の技術的範囲が制限されるものではない。また、複数の図面に表れる同一符号の部分は同一もしくは同等の部分又は部材を示す。
　さらに以下に示す実施形態は、本発明の技術思想の具体例を示すものであって、本発明を以下に限定するものではない。また、以下に記載されている構成部品の寸法、材質、形状、その相対的配置等は、特定的な記載がない限り、本発明の範囲をそれのみに限定する趣旨ではなく、例示することを意図したものである。また、一の実施の形態、実施例において説明する内容は、他の実施の形態、実施例にも適用可能である。また、図面が示す部材の大きさや位置関係等は、説明を明確にするため、誇張していることがある。 Hereinafter, the present invention will be described in detail with reference to the drawings. In the following description, terms indicating a specific direction or position (for example, "upper", "lower", and other terms including those terms) are used as necessary, but the use of these terms is used. This is for facilitating the understanding of the invention with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention. Further, the parts having the same reference numerals appearing in a plurality of drawings indicate the same or equivalent parts or members.
Further, the embodiments shown below show specific examples of the technical idea of the present invention, and do not limit the present invention to the following. In addition, the dimensions, materials, shapes, relative arrangements, etc. of the components described below are not intended to limit the scope of the present invention to the specific description, but are exemplified. It was intended. Further, the contents described in one embodiment and the embodiment can be applied to other embodiments and the examples. In addition, the size and positional relationship of the members shown in the drawings may be exaggerated in order to clarify the explanation.
　本発明の第１の実施態様の電子回路ユニットは、外部入力端子に入力される外部トリガー信号で切換パルス信号を出力するトリガー回路と、トリガー回路の切換パルス信号が起動端子に入力されて、切換パルス信号で動作モードと省電力モードとを切り換える回路モジュールとを備えている。トリガー回路は、外部トリガー信号で制御されて起動端子に切換パルス信号を出力する半導体スイッチング素子と、半導体スイッチング素子の負荷抵抗と、起動端子に入力される切換パルス信号を所定のパルス幅のワンショットパルスとするワンショットパルス回路とを備えている。起動端子は、半導体スイッチング素子と負荷抵抗との接続部に接続されて、ワンショットパルス回路は、半導体スイッチング素子の入力側と外部入力端子との間に接続してなるカップリングコンデンサと、カップリングコンデンサの充電抵抗とで構成されており、カップリングコンデンサと充電抵抗の時定数で、ワンショットパルスのパルス幅を特定している。 In the electronic circuit unit of the first embodiment of the present invention, a trigger circuit that outputs a switching pulse signal by an external trigger signal input to an external input terminal and a switching pulse signal of the trigger circuit are input to a start terminal for switching. It is equipped with a circuit module that switches between operation mode and power saving mode with a pulse signal. The trigger circuit is a one-shot of a semiconductor switching element that is controlled by an external trigger signal and outputs a switching pulse signal to the start terminal, the load resistance of the semiconductor switching element, and the switching pulse signal input to the start terminal with a predetermined pulse width. It is equipped with a one-shot pulse circuit that makes a pulse. The start terminal is connected to the connection between the semiconductor switching element and the load resistor, and the one-shot pulse circuit is coupled with a coupling capacitor connected between the input side of the semiconductor switching element and the external input terminal. It is composed of the charging resistance of the capacitor, and the pulse width of the one-shot pulse is specified by the time constant of the coupling capacitor and the charging resistance.
　以上の電子回路ユニットは、ワンショットパルス回路を、カップリングコンデンサと充電抵抗からなる極めて簡単な回路で実現するので、回路構成を極めて簡単にしながら、動作モードにおいて回路の電力消費を削減して、極めて低電力消費にできる特長がある。電子回路ユニットは、ワンショットパルスのパルス幅を、カップリングコンデンサの静電容量と充電抵抗の電気抵抗の積からなる時定数で調整する。 The above electronic circuit unit realizes a one-shot pulse circuit with an extremely simple circuit consisting of a coupling capacitor and a charging resistor. Therefore, while making the circuit configuration extremely simple, the power consumption of the circuit can be reduced in the operation mode. It has the advantage of extremely low power consumption. The electronic circuit unit adjusts the pulse width of the one-shot pulse with a time constant consisting of the product of the capacitance of the coupling capacitor and the electrical resistance of the charging resistor.
　本発明の第２の実施態様の電子回路ユニットは、カップリングコンデンサの静電容量と、充電抵抗の電気抵抗が、ワンショットパルスのパルス幅を１ｍｓｅｃ以上とする時定数としている。 The electronic circuit unit of the second embodiment of the present invention has a time constant in which the capacitance of the coupling capacitor and the electrical resistance of the charging resistor set the pulse width of the one-shot pulse to 1 msec or more.
　本発明の第３の実施態様の電子回路ユニットは、半導体スイッチング素子をＦＥＴとしている。 The electronic circuit unit of the third embodiment of the present invention uses a semiconductor switching element as an FET.
　本発明の第４の実施態様の電子回路ユニットは、半導体スイッチング素子の入力側とカップリングコンデンサとの間に接続してなる充電抵抗を備え、カップリングコンデンサが、充電抵抗と充電抵抗の直列抵抗で充電されるようにしている。 The electronic circuit unit of the fourth embodiment of the present invention includes a charging resistor connected between the input side of the semiconductor switching element and the coupling capacitor, and the coupling capacitor is a series resistance of the charging resistor and the charging resistor. I am trying to charge it with.
　本発明の第５の実施態様の電子回路ユニットは、充電抵抗を、外部入力端子と電源ラインとに接続している。 In the electronic circuit unit of the fifth embodiment of the present invention, a charging resistor is connected to an external input terminal and a power supply line.
　本発明の第６の実施態様の電子回路ユニットは、回路モジュールが、Ｈｉｇｈレベルの切換パルス信号で省電力モードを動作モードに切り換えると共に、半導体スイッチング素子のオン状態で、起動端子にＨｉｇｈレベルの切換パルス信号が入力され、ワンショットパルス回路が、充電抵抗でカップリングコンデンサを充電して、起動端子をＨｉｇｈレベルからＬｏｗレベルとしている。 In the electronic circuit unit of the sixth embodiment of the present invention, the circuit module switches the power saving mode to the operation mode by the high level switching pulse signal, and switches the high level to the start terminal when the semiconductor switching element is on. A pulse signal is input, and the one-shot pulse circuit charges the coupling capacitor with a charging resistor to change the starting terminal from High level to Low level.
（実施の形態１）
　図１は電子回路ユニット１０を備える電池パック１００を示している。電池パック１００の電子回路ユニット１０は、電池パック１００が接続機器に接続されて充放電される状態で動作モード、充放電が継続しない状態で省電力モードに切り換えられて、消費電力を削減している。省電力モードにある電子回路ユニット１０は、接続機器から入力される外部トリガー信号で動作モードに切り換えられる。 (Embodiment 1)
FIG. 1 shows a battery pack 100 including an electronic circuit unit 10. The electronic circuit unit 10 of the battery pack 100 is switched to an operation mode in a state where the battery pack 100 is connected to a connected device and charged / discharged, and a power saving mode in a state where charging / discharging does not continue, thereby reducing power consumption. There is. The electronic circuit unit 10 in the power saving mode is switched to the operation mode by an external trigger signal input from the connected device.
（電池回路ユニット１０）
　電池パック１００に実装される電子回路ユニット１０は、電池１の保護回路などを実装するアナログフロントエンド（ＡＦＥ）などの回路モジュール２と、この回路モジュール２を動作モードに切り換えるトリガー回路３を備える。トリガー回路３は、電池パック１００を接続する機器から入力される外部トリガー信号で回路モジュール２を動作モードとする。トリガー回路３は、外部トリガー信号で”Ｈｉｇｈ”と”Ｌｏｗ”に切り換える切換パルス信号を回路モジュール２の起動端子２ａに入力して、回路モジュール２を動作モードとする。外部トリガー信号で動作モードに切り換えられた回路モジュール２は、特定の条件を満たすと、例えば使用しない状態が所定の時間継続すると、回路モジュール２を省電力モードに切り換えて電力消費を削減する。回路モジュール２は、特定の条件を満足することを判定するマイコン４などからの信号で省電力モードに切り換えられる。マイコン４で省電力モードに切り換えるタイミングで、起動端子２ａが”Ｈｉｇｈ”レベルにあると、回路モジュール２は動作モードを保持して、省電力モードに切り換えできない。このため、トリガー回路３は、起動端子２ａに”Ｈｉｇｈ”レベルの切換パルス信号を入力して、回路モジュール２を動作モードに切り換えた後、切換パルス信号を”Ｌｏｗ”レベルに制御する。 (Battery circuit unit 10)
The electronic circuit unit 10 mounted on the battery pack 100 includes a circuit module 2 such as an analog front end (AFE) that mounts a protection circuit of the battery 1 and the like, and a trigger circuit 3 that switches the circuit module 2 to an operation mode. The trigger circuit 3 sets the circuit module 2 as an operation mode by an external trigger signal input from a device to which the battery pack 100 is connected. The trigger circuit 3 inputs a switching pulse signal for switching between “High” and “Low” with an external trigger signal to the start terminal 2a of the circuit module 2, and sets the circuit module 2 as the operation mode. The circuit module 2 switched to the operation mode by the external trigger signal switches the circuit module 2 to the power saving mode to reduce the power consumption when a specific condition is satisfied, for example, when the unused state continues for a predetermined time. The circuit module 2 is switched to the power saving mode by a signal from a microcomputer 4 or the like that determines that a specific condition is satisfied. If the start terminal 2a is at the "High" level at the timing of switching to the power saving mode in the microcomputer 4, the circuit module 2 holds the operation mode and cannot switch to the power saving mode. Therefore, the trigger circuit 3 inputs a "High" level switching pulse signal to the start terminal 2a, switches the circuit module 2 to the operation mode, and then controls the switching pulse signal to the "Low" level.
　トリガー回路３は、外部トリガー信号が入力される半導体スイッチング素子５と、この半導体スイッチング素子５の負荷抵抗６と、起動端子２ａに入力する切換パルス信号の”Ｈｉｇｈ”レベルを、あらかじめ設定している時間後に”Ｌｏｗ”レベルに切り換えるワンショットパルス回路７とを備える。ワンショットパルス回路７は、半導体スイッチング素子５の入力側に接続しているカップリングコンデンサ１３と、カップリングコンデンサ１３と電源ライン１１との間に接続している充電抵抗１４からなる。 The trigger circuit 3 presets the semiconductor switching element 5 to which the external trigger signal is input, the load resistance 6 of the semiconductor switching element 5, and the “High” level of the switching pulse signal input to the start terminal 2a. It is provided with a one-shot pulse circuit 7 that switches to the "Low" level after an hour. The one-shot pulse circuit 7 includes a coupling capacitor 13 connected to the input side of the semiconductor switching element 5, and a charging resistor 14 connected between the coupling capacitor 13 and the power supply line 11.
　図１のトリガー回路３は、半導体スイッチング素子５をｐチャンネルのＦＥＴ５Ａとする。ｐチャンネルのＦＥＴ５Ａは、カップリングコンデンサ１３からオン電圧が入力されない状態でオフ、カップリングコンデンサ１３からオン電圧が入力されてオン状態となる。ｐチャンネルのＦＥＴ５Ａは、オン状態に限って負荷抵抗６に通電し、負荷抵抗６は、通電される状態で電圧が発生して”Ｈｉｇｈ”レベルの切換パルス信号を起動端子２ａに入力する。起動端子２ａに入力された”Ｈｉｇｈ”レベルの切換パルス信号は、回路モジュール２を動作モードとする。 In the trigger circuit 3 of FIG. 1, the semiconductor switching element 5 is a p-channel FET 5A. The p-channel FET 5A is turned off when the on-voltage is not input from the coupling capacitor 13, and is turned on when the on-voltage is input from the coupling capacitor 13. The p-channel FET 5A energizes the load resistor 6 only in the on state, and the load resistor 6 generates a voltage in the energized state and inputs a “High” level switching pulse signal to the start terminal 2a. The "High" level switching pulse signal input to the start terminal 2a sets the circuit module 2 as the operation mode.
　ｐチャンネルのＦＥＴ５Ａは、ゲートにマイナスのオン電圧が入力されるタイミングでオン状態となって、回路モジュール２を動作モードとする。外部トリガー信号の”Ｈｉｇｈ”レベルで回路モジュール２を動作モードとするので、このタイミングでｐチャンネルのＦＥＴ５Ａをオン状態とするために、図１のトリガー回路３は、ｐチャンネルのＦＥＴ５Ａの入力側に反転回路８を接続して、外部トリガー信号の”Ｈｉｇｈ”と”Ｌｏｗ”を反転して、ｐチャンネルのＦＥＴ５Ａのゲートに入力している。 The p-channel FET 5A is turned on at the timing when a negative on voltage is input to the gate, and the circuit module 2 is set to the operation mode. Since the circuit module 2 is set to the operation mode at the "High" level of the external trigger signal, the trigger circuit 3 in FIG. 1 is placed on the input side of the p-channel FET 5A in order to turn on the p-channel FET 5A at this timing. An inverting circuit 8 is connected to invert the external trigger signals "High" and "Low", and the signals are input to the gate of the p-channel FET 5A.
　図１の反転回路８は、発光ダイオード１６とフォトトランジスタ１７からなるフォトカップラ１５で、フォトトランジスタ１７のコレクタをプルアップ抵抗１８を介してプラス側の電源ライン１１に接続して、エミッタをグランドライン１２に接続している。この反転回路８のフォトカップラ１５は、発光ダイオード１６が外部トリガー信号の”Ｈｉｇｈ”で点灯して、フォトトランジスタ１７がオン状態となる。オン状態のフォトトランジスタ１７は、プルアップ抵抗１８をグランドライン１２に接続して出力を”Ｌｏｗ”とする。フォトカップラ１５は、発光ダイオード１６が外部トリガー信号の”Ｌｏｗ”信号で点灯しない状態では、フォトトランジスタ１７がオフ状態となって、プルアップ抵抗１８を介して”Ｈｉｇｈ”信号を出力する。図の反転回路はフォトカップラとしているが、反転回路はフォトカップラに限定せず、ＦＥＴ等のスイッチング素子で構成することもできる。 The inverting circuit 8 of FIG. 1 is a photocoupler 15 composed of a light emitting diode 16 and a phototransistor 17, in which a collector of the phototransistor 17 is connected to a power supply line 11 on the positive side via a pull-up resistor 18, and an emitter is a ground line. It is connected to 12. In the photocoupler 15 of the inversion circuit 8, the light emitting diode 16 is turned on by the external trigger signal "High", and the phototransistor 17 is turned on. The phototransistor 17 in the ON state connects the pull-up resistor 18 to the ground line 12 to set the output to “Low”. When the light emitting diode 16 is not lit by the "Low" signal of the external trigger signal, the photocoupler 15 turns off the phototransistor 17 and outputs a "High" signal via the pull-up resistor 18. Although the inverting circuit in the figure is a photocoupler, the inverting circuit is not limited to the photocoupler and may be composed of a switching element such as an FET.
　入力側に反転回路８を接続するトリガー回路３は、外部トリガー信号の”Ｈｉｇｈ”が反転回路８の外部入力端子１９に入力されると、ｐチャンネルのＦＥＴ５Ａのゲートにプラス側の電源ライン１１に対してマイナスのオン電圧が入力されてＦＥＴ５Ａがオン状態となる。オン状態のｐチャンネルのＦＥＴ５Ａは、負荷抵抗６に発生する”Ｈｉｇｈ”信号を起動端子２ａに切換パルス信号として入力して、回路モジュール２を動作モードとする。 In the trigger circuit 3 that connects the inverting circuit 8 to the input side, when the external trigger signal "High" is input to the external input terminal 19 of the inverting circuit 8, the power line 11 on the positive side is connected to the gate of the FET 5A of the p channel. On the other hand, a negative on voltage is input and the FET 5A is turned on. The p-channel FET 5A in the ON state inputs the "High" signal generated in the load resistor 6 to the start terminal 2a as a switching pulse signal, and sets the circuit module 2 as the operation mode.
　回路モジュール２は、動作モードから省電力モードに切り換えられることがある。この状態は、電池パック１００が接続機器に電力を供給しない状態が長く続く状態などで発生する。回路モジュール２は、起動端子２ａが”Ｈｉｇｈ”レベルにあると、動作モードを省電力モードに切り換えできないので、動作モードを省電力モードに切り換えできるように、動作モードに切り換えた後、起動端子２ａを”Ｌｏｗ”レベルとする必要がある。 The circuit module 2 may be switched from the operation mode to the power saving mode. This state occurs when the battery pack 100 does not supply power to the connected device for a long time. When the start terminal 2a is at the "High" level, the circuit module 2 cannot switch the operation mode to the power saving mode. Therefore, after switching to the operation mode so that the operation mode can be switched to the power saving mode, the start terminal 2a Must be at the "Low" level.
　動作モードに切り換えられた後、起動端子２ａを強制的に”Ｈｉｇｈ”から”Ｌｏｗ”に切り換えるために、トリガー回路３は、ワンショットパルス回路７を備える。ワンショットパルス回路７は、”Ｈｉｇｈ”レベルの切換パルス信号を所定の時間後に”Ｌｏｗ”レベルに切り換えて、切換パルス信号を所定のパルス幅のワンショットパルスとする。ワンショットパルス回路７は、ｐチャンネルのＦＥＴ５Ａのオン時間を特定して、起動端子２ａに入力する切換パルス信号をワンショットパルスとする。 The trigger circuit 3 includes a one-shot pulse circuit 7 in order to forcibly switch the start terminal 2a from "High" to "Low" after the operation mode is switched. The one-shot pulse circuit 7 switches the "High" level switching pulse signal to the "Low" level after a predetermined time, and sets the switching pulse signal as a one-shot pulse having a predetermined pulse width. The one-shot pulse circuit 7 specifies the on-time of the p-channel FET 5A, and sets the switching pulse signal input to the start terminal 2a as a one-shot pulse.
　ワンショットパルス回路７は、ＦＥＴ５Ａの入力側に接続しているカップリングコンデンサ１３と、カップリングコンデンサ１３の充電抵抗１４とで構成している。図１の電子回路ユニット１０は、充電抵抗１４を、カップリングコンデンサ１３とＦＥＴ５Ａのゲートとの間に接続している第１の充電抵抗１４Ａと、ＦＥＴ５Ａのゲートと電源ライン１１とを接続している第２の充電抵抗１４Ｂとの直列抵抗で構成している。第２の充電抵抗１４Ｂは、ＦＥＴ５Ａのゲートをプラス側の電源ライン１１に接続してノーマル状態でＦＥＴ５Ａをオフ状態に保持する。カップリングコンデンサ１３と充電抵抗１４の時定数は、第１の充電抵抗１４Ａと第２の充電抵抗１４Ｂの電気抵抗を加算した電気抵抗で特定される。この回路構成は、第２の充電抵抗１４Ｂを、ＦＥＴ５Ａのゲート電圧（ＶＧＳ）をノーマル状態でオフ状態に保持する入力抵抗に併用できる。ＦＥＴ５Ａは、ゲートとソースとの間に入力抵抗があって、この入力抵抗が第２の充電抵抗１４Ｂと並列に接続されて、第２の充電抵抗１４Ｂの電気抵抗を実質的に小さくするが、ＦＥＴ５Ａの入力抵抗は相当に大きいので、これを無視して、第１の充電抵抗１４Ａと第２の充電抵抗１４Ｂの電気抵抗から時定数を特定することができる。ただ、ＦＥＴ５Ａの入力抵抗が大きい状態では、入力抵抗を考慮して第２の充電抵抗１４Ｂの電気抵抗を特定する。 The one-shot pulse circuit 7 is composed of a coupling capacitor 13 connected to the input side of the FET 5A and a charging resistor 14 of the coupling capacitor 13. In the electronic circuit unit 10 of FIG. 1, the charging resistor 14 is connected to the first charging resistor 14A which is connected between the coupling capacitor 13 and the gate of the FET 5A, and the gate of the FET 5A and the power supply line 11 are connected to each other. It is composed of a series resistance with the second charging resistance 14B. The second charging resistor 14B connects the gate of the FET 5A to the power supply line 11 on the positive side and holds the FET 5A in the off state in the normal state. The time constant of the coupling capacitor 13 and the charging resistor 14 is specified by the electrical resistance obtained by adding the electrical resistances of the first charging resistor 14A and the second charging resistor 14B. In this circuit configuration, the second charging resistor 14B can be used in combination with the input resistor that holds the gate voltage (VGS) of the FET 5A in the off state in the normal state. The FET 5A has an input resistor between the gate and the source, and this input resistor is connected in parallel with the second charging resistor 14B to substantially reduce the electrical resistance of the second charging resistor 14B. Since the input resistance of the FET 5A is considerably large, this can be ignored and the time constant can be specified from the electrical resistances of the first charging resistance 14A and the second charging resistance 14B. However, when the input resistance of the FET 5A is large, the electric resistance of the second charging resistance 14B is specified in consideration of the input resistance.
　カップリングコンデンサ１３は、外部トリガー信号の”Ｌｏｗ”状態、すなわち省電力モードにおいて両端の電圧がプラス側の電源ライン１１の電圧となって電圧が０Ｖ、すなわち放電された状態となる。反転回路８からカップリングコンデンサ１３の片側に”Ｌｏｗ”信号が入力されると、カップリングコンデンサ１３は充電抵抗１４を介して充電が開始され、ｐチャンネルのＦＥＴ５Ａのゲートに入力される入力電圧が瞬間的に低下して”Ｌｏｗ”となる。この状態で、ｐチャンネルのＦＥＴ５Ａのゲートにプラス側の電源ライン１１に対してマイナスのオン電圧が入力され、ゲート・ソース間の電位差であるゲート電圧（ＶＧＳ）がカットオフ電圧よりも高くなって、ＦＥＴ５Ａがオン状態となる。充電されるカップリングコンデンサ１３は、両端の電圧が次第に高くなる。カップリングコンデンサ１３の両端の電圧が高くなるにしたがって、ｐチャンネルのＦＥＴ５Ａのゲートに入力される入力電圧が次第に高くなって、やがてプラス側の電源ライン１１の電圧まで復帰する。すなわち、オン状態となったｐチャンネルのＦＥＴ５Ａは、時間の経過と共にゲート電圧（ＶＧＳ）が次第に小さくなり、カットオフ電圧よりも低くなってオフ状態となる。したがって、カップリングコンデンサ１３の電圧変化は、ＦＥＴ５Ａのオン時間、すなわちワンショットパルスのパルス幅を特定する。カップリングコンデンサ１３の電圧変化は、カップリングコンデンサ１３の静電容量と、充電抵抗１４の電気抵抗の積で特定される時定数で特定される。時定数が大きくなるとカップリングコンデンサ１３の電圧変化は緩慢になるので、ワンショットパルスのパルス幅は大きく、すなわちｐチャンネルのＦＥＴ５Ａのオン時間は長くなる。 The coupling capacitor 13 is in the "Low" state of the external trigger signal, that is, in the power saving mode, the voltage at both ends becomes the voltage of the power supply line 11 on the positive side, and the voltage becomes 0V, that is, the state of being discharged. When a "Low" signal is input from the inverting circuit 8 to one side of the coupling capacitor 13, the coupling capacitor 13 starts charging via the charging resistor 14, and the input voltage input to the gate of the p-channel FET 5A becomes. It drops momentarily and becomes "Low". In this state, a negative on-voltage is input to the gate of the p-channel FET 5A with respect to the positive power supply line 11, and the gate voltage (VGS), which is the potential difference between the gate and source, becomes higher than the cutoff voltage. , FET 5A is turned on. The voltage across the coupling capacitor 13 to be charged gradually increases. As the voltage across the coupling capacitor 13 increases, the input voltage input to the gate of the p-channel FET 5A gradually increases, and eventually returns to the voltage of the power supply line 11 on the positive side. That is, the gate voltage (VGS) of the p-channel FET 5A that has been turned on gradually becomes smaller with the passage of time, becomes lower than the cutoff voltage, and is turned off. Therefore, the voltage change of the coupling capacitor 13 specifies the on-time of the FET 5A, that is, the pulse width of the one-shot pulse. The voltage change of the coupling capacitor 13 is specified by a time constant specified by the product of the capacitance of the coupling capacitor 13 and the electric resistance of the charging resistor 14. When the time constant becomes large, the voltage change of the coupling capacitor 13 becomes slow, so that the pulse width of the one-shot pulse becomes large, that is, the on-time of the p-channel FET 5A becomes long.
　カップリングコンデンサ１３と充電抵抗１４の時定数は、ワンショットパルスのパルス幅が、例えば１ｍｓｅｃ以上となるように設定される。このワンショットパルス回路７は、ｐチャンネルのＦＥＴ５Ａのオンタイムを１ｍｓｅｃ以上として、起動端子２ａを”Ｈｉｇｈ”レベルに保持するタイミングを１ｍｓｅｃ以上とする。ワンショットパルスのパルス幅は、カップリングコンデンサ１３と充電抵抗１４の時定数を大きくして、すなわちカップリングコンデンサ１３の静電容量と充電抵抗１４の電気抵抗を大きくして大きくできる。 The time constants of the coupling capacitor 13 and the charging resistor 14 are set so that the pulse width of the one-shot pulse is, for example, 1 msec or more. In this one-shot pulse circuit 7, the on-time of the p-channel FET 5A is set to 1 msec or more, and the timing for holding the start terminal 2a at the “High” level is set to 1 msec or more. The pulse width of the one-shot pulse can be increased by increasing the time constants of the coupling capacitor 13 and the charging resistor 14, that is, increasing the capacitance of the coupling capacitor 13 and the electrical resistance of the charging resistor 14.
　図２は、図１に示す電子回路ユニット１０における、［Ａ］外部トリガー信号、［Ｂ］反転回路出力信号、［Ｃ］ＦＥＴのゲートの入力電圧、及び［Ｄ］切換パルス信号の変化を示すタイミングチャートである。図２の［Ｃ］は、カップリングコンデンサ１３からｐチャンネルのＦＥＴ５Ａのゲートに入力される入力電圧が変化する特性を示している。この図に示すように、ＦＥＴ５Ａのゲートに入力される入力電圧は、外部トリガー信号が”Ｌｏｗ”から”Ｈｉｇｈ”に立ち上がるタイミングで、言い換えると、反転回路８の出力信号が”Ｈｉｇｈ”から”Ｌｏｗ”になって、カップリングコンデンサ１３の充電が開始されるタイミングで瞬間的に低下して”Ｌｏｗ”になり、その後、次第に高くなってプラス側の電源ライン１１の電圧まで復帰する。ｐチャンネルのＦＥＴ５Ａは、ゲートの入力電圧とプラス側の電源ライン１１の電圧との差、すなわちゲート・ソース間の電位差であるゲート電圧（ＶＧＳ）がカットオフ電圧よりも大きい状態でオン状態に保持される。このため、ｐチャンネルのＦＥＴ５Ａは、ゲート電圧（ＶＧＳ）がカットオフ電圧よりも小さくなると、ゲートの入力電圧が”Ｈｉｇｈ”となって、オフ状態に切り換えられる。ｐチャンネルのＦＥＴ５Ａのオン時間は、ゲート電圧（ＶＧＳ）が変化する状態、すなわちカップリングコンデンサ１３と充電抵抗１４の時定数で特定される。時定数を大きくして、ゲート電圧（ＶＧＳ）が小さくなるのを緩慢にして、ｐチャンネルのＦＥＴ５Ａのオン状態は長くなる。したがって、時定数を大きくしてワンショットパルスのパルス幅を長くできる。カップリングコンデンサ１３と充電抵抗１４の時定数は、ワンショットパルスのパルス幅が、たとえば１ｍｓｅｃ以上であって１００ｍｓｅｃ以下、好ましくは１ｍｓｅｃ以上であって１０ｍｓｅｃ以下する。ワンショットパルスのパルス幅を長くすると、カップリングコンデンサ１３の静電容量と充電抵抗１４の電気抵抗が大きくなって部品が大きくてコスト高になり、反対にパルス幅が短すぎると、確実な切り換えが難しくなるので、確実に動作モードに切り換えでき、かつ部品コストを考慮して、以上の範囲に設定する。 FIG. 2 shows changes in the [A] external trigger signal, the [B] inverting circuit output signal, the [C] FET gate input voltage, and the [D] switching pulse signal in the electronic circuit unit 10 shown in FIG. It is a timing chart. [C] of FIG. 2 shows the characteristic that the input voltage input from the coupling capacitor 13 to the gate of the p-channel FET 5A changes. As shown in this figure, the input voltage input to the gate of the FET 5A is the timing at which the external trigger signal rises from "Low" to "High", in other words, the output signal of the inverting circuit 8 changes from "High" to "Low". At the timing when the charging of the coupling capacitor 13 is started, the voltage drops momentarily to "Low", and then gradually rises to the voltage of the power supply line 11 on the positive side. The p-channel FET 5A is held in the ON state when the difference between the input voltage of the gate and the voltage of the power supply line 11 on the positive side, that is, the gate voltage (VGS), which is the potential difference between the gate and the source, is larger than the cutoff voltage. Will be done. Therefore, when the gate voltage (VGS) of the p-channel FET 5A becomes smaller than the cutoff voltage, the gate input voltage becomes "High" and the p-channel FET 5A is switched to the off state. The on-time of the p-channel FET 5A is specified by the state in which the gate voltage (VGS) changes, that is, the time constant of the coupling capacitor 13 and the charging resistor 14. By increasing the time constant and slowing down the gate voltage (VGS), the on-state of the p-channel FET 5A becomes longer. Therefore, the time constant can be increased to lengthen the pulse width of the one-shot pulse. The time constant of the coupling capacitor 13 and the charging resistor 14 is such that the pulse width of the one-shot pulse is, for example, 1 msec or more and 100 msec or less, preferably 1 msec or more and 10 msec or less. If the pulse width of the one-shot pulse is lengthened, the capacitance of the coupling capacitor 13 and the electrical resistance of the charging resistor 14 become large, resulting in large parts and high cost. On the contrary, if the pulse width is too short, reliable switching is performed. Therefore, it is possible to switch to the operation mode without fail, and set the above range in consideration of the component cost.
　図１の電子回路ユニット１０は、以下の動作で省電力モードと動作モードを切り換えて、動作モードを省電力モードに切り換える。 The electronic circuit unit 10 of FIG. 1 switches between a power saving mode and an operation mode by the following operation, and switches the operation mode to the power saving mode.
１．接続機器から外部トリガー信号が電子回路ユニット１０に入力される。外部トリガー信号は、図２の［Ａ］で示すように、省電力モードから動作モードに切り換えるタイミングで、”Ｌｏｗ”から”Ｈｉｇｈ”になる。
　外部トリガー信号は、反転回路８で”Ｈｉｇｈ”と”Ｌｏｗ”を反転してトリガー回路３のカップリングコンデンサ１３に入力される。
　外部トリガー信号は、図２の［Ａ］に示すように、省電力モードを動作モードに切り換えるタイミングで”Ｌｏｗ”レベルから”Ｈｉｇｈ”レベルに立ち上がるので、反転回路８からカップリングコンデンサ１３に入力される信号は、図２の［Ｂ］に示すように、動作モードに切り換えられるタイミングで”Ｈｉｇｈ”から”Ｌｏｗ”になる。 1. 1. An external trigger signal is input to the electronic circuit unit 10 from the connected device. As shown in [A] of FIG. 2, the external trigger signal changes from "Low" to "High" at the timing of switching from the power saving mode to the operation mode.
The external trigger signal is input to the coupling capacitor 13 of the trigger circuit 3 by inverting "High" and "Low" in the inverting circuit 8.
As shown in [A] of FIG. 2, the external trigger signal rises from the “Low” level to the “High” level at the timing of switching the power saving mode to the operation mode, and is therefore input from the inverting circuit 8 to the coupling capacitor 13. The signal changes from "High" to "Low" at the timing of switching to the operation mode, as shown in [B] of FIG.
２．カップリングコンデンサ１３に”Ｌｏｗ”信号が入力されると、ｐチャンネルのＦＥＴ５Ａのゲートの入力される入力電圧は、図２の［Ｃ］に示すように、プラス側の電源ライン１１の電圧に対してマイナス側に大きく低下した電圧となる。この状態で、ｐチャンネルのＦＥＴ５Ａは、ゲートに”Ｌｏｗ”のオン電圧が入力されてオン状態に切り換えられる。
　オン状態のｐチャンネルのＦＥＴ５Ａは、負荷抵抗６に通電して、負荷抵抗６の両端に発生する”Ｈｉｇｈ”信号を切換パルス信号として回路モジュール２の起動端子２ａに入力する。動作モードに入力される”Ｈｉｇｈ”の切換パルス信号は、回路モジュール２を動作モードに切り換える。 2. When a "Low" signal is input to the coupling capacitor 13, the input voltage input to the gate of the FET 5A of the p channel is the voltage of the power supply line 11 on the positive side as shown in [C] of FIG. The voltage drops significantly to the minus side. In this state, the p-channel FET 5A is switched to the on state by inputting a “Low” on voltage to the gate.
The p-channel FET 5A in the ON state energizes the load resistor 6 and inputs "High" signals generated at both ends of the load resistor 6 to the start terminal 2a of the circuit module 2 as a switching pulse signal. The "High" switching pulse signal input to the operation mode switches the circuit module 2 to the operation mode.
３．その後、カップリングコンデンサ１３が充電されて両端の電圧が大きくなるにしたがって、図２の［Ｃ］に示すようにゲートの入力電圧が次第に高くなり、ゲート・ソース間の電位差であるゲート電圧（ＶＧＳ）が次第に小さくなって、カットオフ電圧以下になると、ｐチャンネルのＦＥＴ５Ａはオフ状態に切り換えられる。
　オフ状態となったｐチャンネルのＦＥＴ５Ａは、負荷抵抗６の電流を遮断して、回路モジュール２の起動端子２ａに入力する切換パルス信号を”Ｌｏｗ”に切り換える。
　起動端子２ａに入力される切換パルス信号は、ｐチャンネルのＦＥＴ５Ａがオンになるタイミングからオフに切り換えられるタイミングまでの時間をパルス幅とするワンショットパルスとなる。
　したがって、以上の電子回路ユニット１０は、外部トリガー信号の”Ｈｉｇｈ”信号が外部入力端子１９に入力されて、省電力モードから動作モードに切り換えられた後、所定の時間が経過すると、起動端子２ａを”Ｌｏｗ”として、省電力モードに切り換えできる状態とする。 3. 3. After that, as the coupling capacitor 13 is charged and the voltage across both ends increases, the input voltage of the gate gradually increases as shown in [C] of FIG. 2, and the gate voltage (VGS), which is the potential difference between the gate and the source, gradually increases. ) Gradually becomes smaller and falls below the cutoff voltage, the p-channel FET 5A is switched to the off state.
The p-channel FET 5A that has been turned off cuts off the current of the load resistor 6 and switches the switching pulse signal input to the start terminal 2a of the circuit module 2 to "Low".
The switching pulse signal input to the start terminal 2a is a one-shot pulse having a pulse width of the time from the timing when the p-channel FET 5A is turned on to the timing when it is switched off.
Therefore, in the above electronic circuit unit 10, when a predetermined time elapses after the "High" signal of the external trigger signal is input to the external input terminal 19 and the power saving mode is switched to the operation mode, the activation terminal 2a Is set to "Low" so that the mode can be switched to the power saving mode.
４．起動端子２ａが”Ｌｏｗ”レベルに保持される回路モジュール２は、マイコン４からの信号で、回路モジュール２を省電力モードに切り換えて電力消費を削減できる。 4. The circuit module 2 in which the start terminal 2a is held at the "Low" level can switch the circuit module 2 to the power saving mode by the signal from the microcomputer 4 to reduce the power consumption.
（電池パック１００）　
　図１に示す電池パック１００は、以上の構造の電子回路ユニット１０と、充電できる電池１とを備えている。この電池パック１００は、電子回路ユニット１０を構成する、回路モジュール２、半導体スイッチング素子５、及びマイコン４に対して、内蔵する電池１から動作電力を供給するようにしている。 (Battery pack 100)
The battery pack 100 shown in FIG. 1 includes an electronic circuit unit 10 having the above structure and a rechargeable battery 1. The battery pack 100 supplies operating power from the built-in battery 1 to the circuit module 2, the semiconductor switching element 5, and the microcomputer 4 constituting the electronic circuit unit 10.
　本発明は、動作モードと省電力モードを切り換えて、省電力モードで電力消費を削減できる電池パックに内蔵される電子回路ユニットとして好適に使用できる。 The present invention can be suitably used as an electronic circuit unit built in a battery pack that can switch between an operation mode and a power saving mode to reduce power consumption in the power saving mode.
１００…電池パック
１…電池
２…回路モジュール
２ａ…起動端子
３…トリガー回路
４…マイコン
５…半導体スイッチング素子
５Ａ…ＦＥＴ
６…負荷抵抗
７…ワンショットパルス回路
８…反転回路
１０…電子回路ユニット
１１…電源ライン
１２…グランドライン
１３…カップリングコンデンサ
１４…充電抵抗
１４Ａ…第１の充電抵抗
１４Ｂ…第２の充電抵抗
１５…フォトカップラ
１６…発光ダイオード
１７…フォトトランジスタ
１８…プルアップ抵抗
１９…外部入力端子
８０…電子回路ユニット
８２…回路モジュール
８２ａ…起動端子
８３…トリガー回路
８５…ＦＥＴ
８６…負荷抵抗
８８…反転回路
８９…外部入力端子
９１…電源ライン
９２…グランドライン
９５…ショートＦＥＴ
９６…ショート回路 100 ... Battery pack 1 ... Battery 2 ... Circuit module 2a ... Start terminal 3 ... Trigger circuit 4 ... Microcomputer 5 ... Semiconductor switching element 5A ... FET
6 ... Load resistance 7 ... One-shot pulse circuit 8 ... Inversion circuit 10 ... Electronic circuit unit 11 ... Power supply line 12 ... Ground line 13 ... Coupling capacitor 14 ... Charging resistance 14A ... First charging resistance 14B ... Second charging resistance 15 ... Photocoupler 16 ... Light emitting diode 17 ... Phototransistor 18 ... Pull-up resistor 19 ... External input terminal 80 ... Electronic circuit unit 82 ... Circuit module 82a ... Start terminal 83 ... Trigger circuit 85 ... FET
86 ... Load resistance 88 ... Inverting circuit 89 ... External input terminal 91 ... Power supply line 92 ... Ground line 95 ... Short FET
96 ... Short circuit

Claims (7)

  1. 　外部入力端子に入力される外部トリガー信号で切換パルス信号を出力するトリガー回路と、
    　前記トリガー回路の切換パルス信号が起動端子に入力されて、
    　　前記切換パルス信号で動作モードと省電力モードとを切り換える回路モジュールとを備え、
    　前記トリガー回路は、
    　　外部トリガー信号で制御されて前記起動端子に切換パルス信号を出力する半導体スイッチング素子と、
    　　前記半導体スイッチング素子の負荷抵抗と、
    　前記起動端子に入力される前記切換パルス信号を、
    　　所定のパルス幅のワンショットパルスとするワンショットパルス回路とを備え、
    　前記起動端子は、
    　　前記半導体スイッチング素子と前記負荷抵抗との接続部に接続され、
    　前記ワンショットパルス回路は、
    　　前記半導体スイッチング素子の入力側と前記外部入力端子との間に接続してなるカップリングコンデンサと、
    　　前記カップリングコンデンサの充電抵抗とで構成され、
    　　前記カップリングコンデンサと前記充電抵抗の時定数で、
    　　　前記ワンショットパルスのパルス幅を特定してなることを特徴とする電子回路ユニット。     A trigger circuit that outputs a switching pulse signal with an external trigger signal input to the external input terminal,
    The switching pulse signal of the trigger circuit is input to the start terminal,
    A circuit module for switching between an operation mode and a power saving mode with the switching pulse signal is provided.
    The trigger circuit is
    A semiconductor switching element that is controlled by an external trigger signal and outputs a switching pulse signal to the start terminal.
    The load resistance of the semiconductor switching element and
    The switching pulse signal input to the start terminal is
    It is equipped with a one-shot pulse circuit that makes one-shot pulses with a predetermined pulse width.
    The start terminal is
    It is connected to the connection portion between the semiconductor switching element and the load resistor, and is connected to the connection portion.
    The one-shot pulse circuit is
    A coupling capacitor connected between the input side of the semiconductor switching element and the external input terminal,
    It is composed of the charging resistance of the coupling capacitor.
    With the time constant of the coupling capacitor and the charging resistance,
    An electronic circuit unit characterized in that the pulse width of the one-shot pulse is specified.
  2. 　請求項１に記載する電子回路ユニットであって、
    　前記カップリングコンデンサの静電容量と、
    　前記充電抵抗の電気抵抗が、
    　前記ワンショットパルスのパルス幅を１ｍｓｅｃ以上とする時定数であることを特徴とする電子回路ユニット。     The electronic circuit unit according to claim 1.
    The capacitance of the coupling capacitor and
    The electrical resistance of the charging resistor
    An electronic circuit unit characterized by having a time constant such that the pulse width of the one-shot pulse is 1 msec or more.
  3. 　請求項１または２に記載する電子回路ユニットであって、
    　前記半導体スイッチング素子がＦＥＴであることを特徴とする電子回路ユニット。     The electronic circuit unit according to claim 1 or 2.
    An electronic circuit unit characterized in that the semiconductor switching element is an FET.
  4. 　請求項１ないし３のいずれかに記載する電子回路ユニットであって、
    　前記半導体スイッチング素子の入力側と前記カップリングコンデンサとの間に接続してなる充電抵抗を備え、
    　前記カップリングコンデンサが、
    　　前記充電抵抗と前記充電抵抗の直列抵抗で充電されるようにしてなることを特徴とする電子回路ユニット。     The electronic circuit unit according to any one of claims 1 to 3.
    It is provided with a charging resistor connected between the input side of the semiconductor switching element and the coupling capacitor.
    The coupling capacitor
    An electronic circuit unit characterized in that it is charged by the charging resistance and the series resistance of the charging resistance.
  5. 　請求項１ないし４のいずれかに記載する電子回路ユニットであって、
    　前記充電抵抗が、前記外部入力端子と電源ラインとに接続されてなることを特徴とする電子回路ユニット。     The electronic circuit unit according to any one of claims 1 to 4.
    An electronic circuit unit characterized in that the charging resistor is connected to the external input terminal and a power supply line.
  6. 　請求項１ないし５のいずれかに記載する電子回路ユニットであって、
    　前記回路モジュールが、
    　　Ｈｉｇｈレベルの切換パルス信号で省電力モードを動作モードに切り換えると共に、
    　前記半導体スイッチング素子のオン状態で、
    　　前記起動端子にＨｉｇｈレベルの切換パルス信号が入力され、
    　前記ワンショットパルス回路が、
    　　前記充電抵抗で前記カップリングコンデンサを充電して、
    　　前記起動端子をＨｉｇｈレベルからＬｏｗレベルとすることを特徴とする電子回路ユニット。     The electronic circuit unit according to any one of claims 1 to 5.
    The circuit module
    Along with switching the power saving mode to the operation mode with the high level switching pulse signal,
    With the semiconductor switching element on,
    A high level switching pulse signal is input to the start terminal, and a high level switching pulse signal is input.
    The one-shot pulse circuit
    The coupling capacitor is charged with the charging resistor,
    An electronic circuit unit characterized in that the starting terminal is changed from a high level to a low level.
  7. 　請求項１ないし６のいずれかに記載する電子回路ユニットと、
    　充電できる電池を備える電池パックであって、
    　前記電子回路ユニットと前記半導体スイッチング素子に電池電圧が供給されてなることを特徴とする電池パック。     The electronic circuit unit according to any one of claims 1 to 6 and the electronic circuit unit.
    A battery pack with rechargeable batteries
    A battery pack characterized in that a battery voltage is supplied to the electronic circuit unit and the semiconductor switching element.
PCT/JP2021/012181 2020-03-30 2021-03-24 Electronic circuit unit and battery pack WO2021200442A1 (en)

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JP2020061459A JP2023068210A (en) 2020-03-30 2020-03-30 Electric circuit unit and battery pack

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0764678A (en) * 1993-08-23 1995-03-10 Nippondenso Co Ltd Optical reader
JP2009122934A (en) * 2007-11-14 2009-06-04 Sanyo Electric Co Ltd Power source with connector
JP2017083801A (en) * 2015-10-30 2017-05-18 京セラドキュメントソリューションズ株式会社 Image formation device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0764678A (en) * 1993-08-23 1995-03-10 Nippondenso Co Ltd Optical reader
JP2009122934A (en) * 2007-11-14 2009-06-04 Sanyo Electric Co Ltd Power source with connector
JP2017083801A (en) * 2015-10-30 2017-05-18 京セラドキュメントソリューションズ株式会社 Image formation device

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