WO2021196290A1

WO2021196290A1 - Array substrate

Info

Publication number: WO2021196290A1
Application number: PCT/CN2020/084860
Authority: WO
Inventors: 刘司洋
Original assignee: Tcl华星光电技术有限公司
Priority date: 2020-04-02
Filing date: 2020-04-15
Publication date: 2021-10-07
Also published as: CN111308814A

Abstract

An array substrate, a display panel, and a display device. A pattern of a second metal layer (220) in a non-display region is misaligned with a pattern of a first metal layer (210), and the light transmittance of the non-display region is reduced by non-display region wiring, thereby avoiding the obvious uneven brightness of a frameless display device.

Description

Array substrate

Technical field

This application relates to the field of liquid crystal display technology, and in particular to an array substrate.

Background technique

In the field of liquid crystal display (Liquid Crystal Display, LCD for short), all areas other than the active area (AA) of the liquid crystal display panel are non-display areas (or border areas). A plurality of important metal traces are arranged in the non-display area. These traces include sector traces, array substrate traces, CK signal lines, common electrode lines, etc., specifically labeled A, B, C, and D as shown in FIG. 1A and FIG. 1B. Different functions and different positions of the metal traces have different aperture ratios, so the light transmittance under backlight illumination is also different; in areas with small metal apertures (the metal traces are dense), the light transmittance is low, and it appears black as shown in Figure 1B. The mark D shown, the metal aperture ratio is about 20-30%, which will not transmit light; and the area with large metal aperture ratio (sparse metal traces) has a higher light transmittance. If this area is not covered by foreign objects, the colors of different areas will be inconsistent, resulting in obvious uneven brightness.

In the previous liquid crystal display, the non-display area is usually covered by the frame of the module, so the uneven brightness of the non-display area cannot be observed. With the gradual development of the current borderless display devices (frameless modules refer to the non-display area with no outer frame covering them), the problem of uneven brightness in the non-display area has been paid more and more attention. Related researchers and designers have set out to solve this problem.

technical problem

The purpose of the present application is to provide an array substrate, which proposes a new non-display area wiring design solution to reduce the light transmittance of the non-display area, thereby avoiding obvious uneven brightness of the frameless display device .

Technical solutions

According to one aspect of the present application, an array substrate is provided. The array substrate includes a display area and a non-display area surrounding the display area. A first metal layer is disposed in the non-display area. A second metal layer is arranged on the first metal layer, and the pattern of the second metal layer and the pattern of the first metal layer are arranged in a staggered manner.

In an embodiment of the present application, the first metal layer includes a wiring area and a spacer area, and the wiring area and the spacer area are spaced apart; the second metal layer includes a pattern area and a hollow area, so The pattern area of the second metal layer is located in the spacer area of the first metal layer in the orthographic projection of the first metal layer.

In an embodiment of the present application, when the wiring area is arcuate and the pattern area is strip-shaped, a boundary of the wiring area in the horizontal direction and the boundary of the pattern area in the horizontal direction are The shortest distance between a boundary ranges from 0.5 to 1 μm.

In an embodiment of the present application, when the wiring area is arcuate and the pattern area is strip-shaped, a boundary of the wiring area in the vertical direction and the boundary of the pattern area in the vertical direction are The shortest distance between a boundary ranges from 0.5 to 1 μm.

In an embodiment of the present application, when the wiring area is linear and the pattern area is strip-shaped, a boundary of the wiring area in the horizontal direction and the pattern area are in the horizontal direction. The range of the shortest distance between a boundary of is 0.5~1μm.

In an embodiment of the present application, the length of the pattern area ranges from 50 to 100 μm.

In an embodiment of the present application, the spacing distance between adjacent pattern areas is 5-10 μm.

In an embodiment of the present application, when the wiring area is obliquely shaped and the pattern area is obliquely shaped, the width of the pattern area is smaller than the width of the spacer area by 1-2 μm.

Beneficial effect

Compared with the prior art, the advantage of the present application is that the array substrate of the present application can effectively reduce the light transmittance of the non-display area through a new type of non-display area wiring design, thereby avoiding frameless display devices. Obvious brightness unevenness appears.

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

1A and 1B are schematic diagrams of the wiring of sectors, array wiring, GOA, COM, etc., located in the non-display area of a conventional display panel.

FIG. 2A is a schematic diagram of the structure of an array substrate in an embodiment of the present application.

2B is a partial enlarged schematic diagram of the first metal layer and the second metal layer in the embodiment of the present application.

3A is a schematic diagram of the compensation design of the first metal layer and the second metal layer described in FIG. 2B, wherein the wiring area of the first metal layer is arcuate. Fig. 3B is a partial schematic diagram of Fig. 3A.

4A is a schematic diagram of the compensation design of the first metal layer and the second metal layer described in FIG. 2B, wherein the wiring area of the first metal layer is linear. Fig. 4B is a partial schematic diagram of Fig. 4A.

5 is a schematic diagram of the compensation design of the first metal layer and the second metal layer described in FIG. 2B, wherein the wiring area of the first metal layer is in a diagonal shape.

Embodiments of the present invention

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work shall fall within the protection scope of this application.

The terms "first", "second", "third", etc. (if any) in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and not necessarily used to describe a specific order Or precedence. It should be understood that the objects described in this way can be interchanged under appropriate circumstances. In addition, the terms "including" and "having" and any variations of them are intended to cover non-exclusive inclusions.

In this patent document, the drawings discussed below and various embodiments used to describe the principles disclosed in this application are for illustration only, and should not be construed as limiting the scope of the disclosure of this application. Those skilled in the art will understand that the principles of the present application can be implemented in any suitably arranged system. Exemplary embodiments will be described in detail, and examples of these embodiments are shown in the drawings. In addition, a terminal according to an exemplary embodiment will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings refer to the same elements.

The terms used in the specification of this application are only used to describe specific implementations, and are not intended to show the concept of this application. Unless there is a clearly different meaning in the context, the expression used in the singular form encompasses the expression in the plural form. In the specification of this application, it should be understood that terms such as "including", "having" and "containing" are intended to indicate the possibility of the features, numbers, steps, actions, or combinations thereof disclosed in the specification of this application, but not The possibility that one or more other features, numbers, steps, actions or combinations thereof may exist or may be added is excluded. The same reference numerals in the drawings refer to the same parts.

The embodiments of the present application provide an array substrate, a display panel, and a display device. The detailed description will be given below.

Referring to FIG. 2A, according to an aspect of the present application, an array substrate is provided. The array substrate includes a display area and a non-display area surrounding the display area. A first metal layer 210 is provided in the non-display area, an insulating layer 230 is provided on the first metal layer 210, a second metal layer 220 is provided on the insulating layer 230, and the second metal The pattern of the layer 220 is misaligned with the pattern of the first metal layer 210, as shown in FIG. 2B.

Continuing to refer to FIG. 2A, specifically, the array substrate includes a display area and a non-display area surrounding the display area. The display area is used for screen display, and the non-display area is a shading area to prevent the backlight of the backlight module from leaking out of the non-display area, thereby ensuring the display effect of the display panel using the array substrate. At the same time, the edge wiring of the display panel, such as the sector wiring, is arranged in the non-display area. Of course, in the non-display area, it is not limited to providing sector wiring, for example, array wiring, GOA wiring, common electrode wiring, etc. are also provided in the non-display area, which can ensure the appearance of the display panel. .

The array substrate includes light-emitting components located in the display area and a first metal layer 210 and a second metal layer 220 located in the non-display area of the array substrate. The first metal layer 210 includes a plurality of metal traces arranged at intervals, and the plurality of metal traces arranged at intervals are formed in a certain arrangement (for example, a bow shape, a straight line shape, and an oblique line shape. For details, refer to FIGS. 3A, 4A, and 4A). As shown in 5), the metal trace is connected to the light-emitting element in the display area, so as to realize the display of the display panel. Specifically, the first metal layer 210 includes a wiring area 221 and a spacer area 222, wherein the wiring area 221 is formed by arranging the plurality of metal wirings, and the spacer area 222 is formed by the metal wiring. The gap between the lines is formed.

A second metal layer 220 is provided on the first metal layer 210, and the second metal layer 220 includes a pattern area 221 and a hollow area 222, as shown in FIG. 2B. Wherein, the pattern area 221 of the second metal layer 220 is also formed by metal traces. The pattern of the second metal layer 220 and the pattern of the first metal layer 210 are arranged in a staggered manner. In other words, the pattern area 221 of the second metal layer 220 corresponds to the spacer area 222 of the first metal layer 210. In this embodiment, the orthographic projection of the pattern area 221 of the second metal layer 220 on the first metal layer 210 is located in the spacer area 222 of the first metal layer 210. In other words, the area of the pattern area 221 is smaller than the area of the spacer area 222. Such a design makes the patterns of the first metal layer 210 and the second metal layer 220 of the array substrate match each other, that is, the metal traces of the pattern area 221 of the second metal layer 220 are in the orthographic projection of the first metal layer 210 Fill the gaps in the wiring area 221 of the first metal layer 210, thereby reducing the metal aperture ratio of the non-display area, effectively shielding the backlight generated by the backlight module (that is, reducing the light transmittance), Further avoid light leakage in the non-display area of the display panel.

The routing area 221 has one of an arc shape, a straight line shape, and an oblique line shape.

As shown in FIG. 3A, in an embodiment of the present application, when the wiring area 221 is arcuate, the width of the pattern area 221 is smaller than the width of the spacer area 222 by 1-2 μm, as shown in FIG. 3B The distance between the border of the wiring area 221 and the border of the pattern area 221 (the distance F in the vertical direction or the distance E in the horizontal direction) is 0.5-1 μm. In this embodiment, the wiring area 221 (ie, metal wiring) has an arc shape, and the pattern area 221 has a strip shape, and its projection is located in the arc of the wiring area 221.

As shown in FIG. 4A, in an embodiment of the present application, when the wiring area 221 is linear, the width of the pattern area 221 is smaller than the width of the spacer area 222 by 1-2 μm, and the pattern area The length I of 221 ranges from 50 to 100 μm. Such a design can prevent the metal traces of the pattern region 221 from being too long and causing a large parasitic capacitance with the metal traces of the trace region 221. As shown in FIG. 4B, the distance between the border of the wiring area 221 and the border of the pattern area 221 (the distance G in the horizontal direction) is 0.5-1 μm. In addition, in this embodiment, the separation distance (the distance H in the vertical direction) between adjacent pattern regions 221 is 5-10 μm. Such a design can ensure that the metal aperture ratio of the non-display area is less than 20%, thereby effectively reducing the light leakage of the array traces or sectors in the non-display area.

Referring to FIG. 5, in an embodiment of the present application, when the wiring area 221 is diagonal, the width of the pattern area 221 is smaller than the width of the spacer area 222 by 1˜2 μm. The arrangement of the wiring area 221 in a diagonal shape is basically the same as the arrangement of the wiring area 221 in a linear shape. Wherein, the length of the pattern area 221 ranges from 50 to 100 μm. Such a design can prevent the metal traces of the pattern region 221 from being too long and causing a large parasitic capacitance with the metal traces of the trace region 221.

According to another aspect of the present application, the present application also provides a display panel (not shown in the figure), including the above-mentioned array substrate. The structure of the array substrate is as described above, and will not be repeated here.

According to another aspect of the present application, the present application provides a display device including the above-mentioned display panel. The specific structure of the display panel is as described above, and will not be repeated here. This application can be used for display devices such as liquid crystal televisions, liquid crystal displays, mobile phones, tablet computers, etc., especially those display devices with narrow or even no bezels.

The advantage of the present application is that the array substrate of the present application can effectively reduce the light transmittance of the non-display area through a new non-display area wiring design, thereby avoiding obvious uneven brightness of the frameless display device.

The above are only the preferred embodiments of this application. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of this application, several improvements and modifications can be made, and these improvements and modifications should also be considered The scope of protection of this application.

Claims

An array substrate comprising a display area and a non-display area surrounding the display area, wherein a first metal layer is provided in the non-display area, and a first metal layer is provided on the first metal layer The insulating layer is provided with a second metal layer on the insulating layer, and the pattern of the second metal layer and the pattern of the first metal layer are arranged in an offset manner.
The array substrate according to claim 1, wherein the first metal layer includes a wiring area and a spacer area, and the wiring area and the spacer area are spaced apart; the second metal layer includes a pattern area and a hollow area The pattern area of the second metal layer is located in the spacer area of the first metal layer in the orthographic projection of the first metal layer.
3. The array substrate according to claim 2, wherein when the wiring area is arcuate and the pattern area is strip-shaped, a boundary of the wiring area in the horizontal direction and the pattern area are in the horizontal direction The range of the shortest distance between the upper boundary is 0.5~1μm.
4. The array substrate according to claim 2, wherein when the wiring area is arcuate and the pattern area is strip-shaped, a boundary of the wiring area in a vertical direction and the pattern area are in a vertical direction The range of the shortest distance between the upper boundary is 0.5~1μm.
4. The array substrate according to claim 2, wherein when the wiring area is linear and the pattern area is strip-shaped, a boundary of the wiring area in the horizontal direction is horizontal to the pattern area. The range of the shortest distance between a boundary in the direction is 0.5 to 1 μm.
5. The array substrate according to claim 5, wherein the length of the pattern area ranges from 50 to 100 μm.
5. The array substrate according to claim 5, wherein the spacing distance between adjacent pattern areas is 5-10 μm.
3. The array substrate of claim 2, wherein when the wiring area is oblique and the pattern area is oblique, the width of the pattern area is smaller than the width of the spacer area by 1-2 μm.
8. The array substrate according to claim 8, wherein the length of the pattern area ranges from 50 to 100 μm.
8. The array substrate according to claim 8, wherein the spacing distance between adjacent pattern areas is 5-10 μm.