WO2021196054A1 - 一种极化码的编译码方法及装置 - Google Patents

一种极化码的编译码方法及装置 Download PDF

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Publication number
WO2021196054A1
WO2021196054A1 PCT/CN2020/082639 CN2020082639W WO2021196054A1 WO 2021196054 A1 WO2021196054 A1 WO 2021196054A1 CN 2020082639 W CN2020082639 W CN 2020082639W WO 2021196054 A1 WO2021196054 A1 WO 2021196054A1
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bit
sequence
decoding
subsequence
type
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PCT/CN2020/082639
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English (en)
French (fr)
Inventor
莫晓帆
李楠
李航
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华为技术有限公司
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Priority to PCT/CN2020/082639 priority Critical patent/WO2021196054A1/zh
Priority to CN202080098652.7A priority patent/CN115336202A/zh
Publication of WO2021196054A1 publication Critical patent/WO2021196054A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • This application relates to the field of communication technology, and in particular to a method and device for encoding and decoding polar codes.
  • Communication systems usually use channel coding to improve the reliability of data transmission and ensure the quality of communication.
  • coding methods such as polarization codes and reed-muler (reed-muler, RM) codes can be used.
  • the polarization code is a coding method that can gradually reach the channel capacity, and has excellent decoding performance in a wide working range (such as code length, code rate, or signal-to-noise ratio, etc.).
  • the decoding device divides the bits included in the sequence to be decoded into the following three types: information bits, frozen bits, and parity check. , PC) bits. Among them, information bits are used to carry information, frozen bits refer to fixedly filled bits, and PC bits are used for verification.
  • the decoding device can perform fast decoding based on the type of the bit.
  • the decoding process includes: first dividing the sequence to be decoded to obtain multiple subsequences to be decoded; The combination of bit types determines the decoding algorithm corresponding to each subsequence; then the multiple subsequences are decoded in parallel according to the decoding algorithm corresponding to each subsequence, thereby improving decoding efficiency and realizing fast decoding.
  • the encoding device uses some bits whose values are known to perform redundant filling, and then encodes these bits together with other types of bits and sends them to the decoding device.
  • the type of these bits can be called Known bits (known bits).
  • the encoding device can map the known bit to the starting position of the decoding sequence, so that the decoding device can determine the translation of the known bit according to the decoding result of the known bit at the starting position and the bit value of the known bit.
  • Code reliability, and at least one path is reserved according to the decoding reliability of the known bit, which can improve the decoding reliability.
  • the decoding device cannot determine the subsequence Corresponding decoding algorithm.
  • the decoding device can decode the known bits as information bits, and in Polar code decoding methods such as serial cancellation (successive cancellation, SC), serial cancellation list (successive cancellation list, SCL), etc.
  • SC serial cancellation
  • SCL serial cancellation list
  • the decoding process corresponding to the information bits is complicated, and the algorithm overhead is relatively large, thereby reducing the decoding efficiency. Therefore, how to reduce the overhead and improve the decoding efficiency while ensuring the benefits brought by the known bits is a problem that needs to be solved urgently.
  • the embodiments of the present application provide a polarization code encoding and decoding method and device, which are used to decode subsequences including known bits, so as to reduce overhead and improve decoding while ensuring the benefits of known bits. efficient.
  • a polarization code decoding method includes: receiving a message from an encoding device, the message includes a subsequence to be decoded, the subsequence includes a first bit, and the type of the first bit is already Known bits; take the type of the first bit as the target type, and decode the first bit according to the first decoding algorithm corresponding to the target type.
  • the target type includes parity bits or frozen bits.
  • the method provided in the first aspect described above may be executed by a decoding device or a device capable of supporting the decoding device to implement the functions required by the method, such as a chip system.
  • the first bit is included in the subsequence, and the type of the first bit is a known bit.
  • the type of the first bit is taken as the target type, and the first bit is decoded according to the first decoding algorithm corresponding to the target type, and the target type is a PC bit or a frozen bit.
  • the mapped subsequence does not include the known bits, so the decoding of the subsequence including the known bits can be realized.
  • the bit value of the frozen bit or the PC bit has nothing to do with the soft value
  • the subsequence is decoded according to the decoding algorithm corresponding to the target type, there is no need to perform the soft value calculation on the subsequence, so as to ensure that the known bits bring In the case of profit, the overhead caused by soft value calculation is saved, and the decoding efficiency is improved.
  • the sub-sequence further includes a second bit
  • the type of the second bit includes at least one of a frozen bit, a parity bit, or an information bit
  • the method further includes: corresponding to the type of the second bit
  • the second decoding algorithm decodes the second bit.
  • the type of the first bit is taken as the target type, and the first bit is decoded based on the decoding algorithm corresponding to the target type.
  • the subsequence further includes the second bit
  • the type corresponding to the second bit is The second decoding algorithm decodes the second bit, so as to realize the decoding of the subsequence including the known bits.
  • the message is an uplink control message, or a downlink control message.
  • the uplink control message includes a first field and a second field.
  • the first field is used to indicate whether the first bit is included in the subsequence
  • the second field is used to indicate whether the first bit is in the subsequence. Location.
  • the downlink control message includes the third field and the fourth field, the third field is used to indicate whether the first bit is included in the subsequence, and the fourth field is used to indicate the position of the first bit in the subsequence. Location.
  • setting the type of the first bit as the target type includes: when the value range of the first bit is consistent with the value range of the parity bit, using the type of the first bit as the parity Bit; or, when the value range of the first bit is consistent with the value range of the frozen bit, the type of the first bit is taken as the frozen bit.
  • taking the type of the first bit as the target type includes: mapping the type of the first bit to the target type to obtain a position distribution sequence, which is used to characterize the type of each bit in the subsequence;
  • Decoding the first bit according to the first decoding algorithm corresponding to the target type and decoding the second bit according to the second decoding algorithm corresponding to the type of the second bit includes: respectively determining the first bit according to the position distribution sequence A decoding algorithm and a second decoding algorithm; the subsequence is decoded according to the third decoding algorithm, and the third decoding algorithm includes the first decoding algorithm and the second decoding algorithm.
  • the third decoding algorithm does not include soft value calculation, which is used to determine the bit value of each bit in the subsequence to be 0 or 1. Likelihood probability.
  • the third decoding algorithm when the type of the second bit includes information bits, the third decoding algorithm includes soft value calculation, which is used to determine whether the bit value of each bit in the subsequence is 0 or 1. The probability.
  • soft value calculation when the type of the second bit includes information bits, the subsequence is decoded through soft value calculation, and the subsequence including known bits can be decoded.
  • the method further includes: decoding the sub-sequence according to the third decoding algorithm to obtain a hard-valued sequence, and the hard-valued sequence includes a sequence corresponding to The first hard value of the first bit and the second hard value corresponding to the second bit; the first hard value is extracted from the hard value sequence as the decoding result.
  • the known bits are processed as information bits in the hard value backtracking.
  • the bit value of the known bit can be extracted from the hard value sequence as the decoding result.
  • the method further includes: decoding the sub-sequence according to the third decoding algorithm to obtain a hard-valued sequence, and the hard-valued sequence includes a sequence corresponding to the first The first hard value of one bit, and the second hard value corresponding to the second bit; the first hard value and the third hard value are extracted from the hard value sequence as the decoding result, and the third hard value corresponds to the second bit The hard value of the information bits in.
  • the known bits are processed as information bits in the hard value backtracking.
  • the bit value of the known bit can be extracted from the hard value sequence as the decoding result.
  • a polarization code decoding method includes: receiving a message from an encoding device, the message includes a subsequence to be decoded, the subsequence includes a first bit, and the type of the first bit is already Known bits: The type of the first bit is taken as the PC bit, and the first bit is decoded according to the first decoding algorithm corresponding to the PC bit.
  • the target type includes parity bit or frozen bit.
  • the method provided in the above second aspect may be executed by a decoding device or a device capable of supporting the decoding device to implement the functions required by the method, such as a chip system.
  • the first bit is included in the subsequence, and the type of the first bit is a known bit.
  • the type of the first bit is taken as the PC bit, and the first bit is decoded according to the first decoding algorithm corresponding to the PC bit. After the type of the first bit is mapped to the target type, the mapped subsequence does not include the known bits, so the decoding of the subsequence including the known bits can be realized.
  • the subsequence further includes a second bit
  • the type of the second bit includes at least one of a frozen bit, a parity bit, or an information bit
  • the method further includes: corresponding to the type of the second bit The second decoding algorithm decodes the second bit.
  • the message is an uplink control message, or a downlink control message.
  • the uplink control message includes a first field and a second field.
  • the first field is used to indicate whether the first bit is included in the subsequence
  • the second field is used to indicate whether the first bit is in the subsequence.
  • the downlink control message includes the third field and the fourth field, the third field is used to indicate whether the first bit is included in the subsequence, and the fourth field is used to indicate the position of the first bit in the subsequence. Location.
  • using the type of the first bit as the PC bit includes: mapping the type of the first bit to the PC bit to obtain a position distribution sequence, which is used to characterize the type of each bit in the subsequence; Decoding the first bit according to the first decoding algorithm corresponding to the PC bit, and decoding the second bit according to the second decoding algorithm corresponding to the type of the second bit includes: respectively determining the first bit according to the position distribution sequence A decoding algorithm and a second decoding algorithm; the subsequence is decoded according to the third decoding algorithm, and the third decoding algorithm includes the first decoding algorithm and the second decoding algorithm.
  • the third decoding algorithm does not include soft value calculation, which is used to determine the bit value of each bit in the subsequence to be 0 or 1. Likelihood probability.
  • the third decoding algorithm when the type of the second bit includes information bits, the third decoding algorithm includes soft value calculation, which is used to determine whether the bit value of each bit in the subsequence is 0 or 1. The probability.
  • the method further includes: decoding the sub-sequence according to the third decoding algorithm to obtain a hard-valued sequence, and the hard-valued sequence includes a sequence corresponding to The first hard value of the first bit and the second hard value corresponding to the second bit; the first hard value is extracted from the hard value sequence as the decoding result.
  • the method further includes: decoding the sub-sequence according to the third decoding algorithm to obtain a hard-valued sequence, and the hard-valued sequence includes a sequence corresponding to the first The first hard value of one bit, and the second hard value corresponding to the second bit; the first hard value and the third hard value are extracted from the hard value sequence as the decoding result, and the third hard value corresponds to the second bit The hard value of the information bits in.
  • a polarization code decoding method includes: receiving a message from an encoding device, the message includes a subsequence to be decoded, the subsequence includes a first bit, and the type of the first bit is already Known bits; use the type of the first bit as a frozen bit, and decode the first bit according to the first decoding algorithm corresponding to the frozen bit.
  • the target type includes parity bit or frozen bit.
  • the method provided in the above third aspect may be executed by a decoding device or a device capable of supporting the decoding device to implement the functions required by the method, such as a chip system.
  • the first bit is included in the subsequence, and the type of the first bit is a known bit.
  • the type of the first bit is taken as the frozen bit, and the first bit is decoded according to the first decoding algorithm corresponding to the frozen bit.
  • the mapped subsequence does not include the known bits, so the decoding of the subsequence including the known bits can be realized.
  • the bit value of the frozen bit has nothing to do with the soft value
  • the subsequence is decoded according to the decoding algorithm corresponding to the frozen bit
  • there is no need to perform the soft value calculation on the subsequence so as to ensure the benefit of the known bit Therefore, the overhead caused by soft value calculation is saved, and the decoding efficiency is improved.
  • the sub-sequence further includes a second bit
  • the type of the second bit includes at least one of a frozen bit, a parity bit, or an information bit
  • the method further includes: corresponding to the type of the second bit The second decoding algorithm decodes the second bit.
  • the message is an uplink control message, or a downlink control message.
  • the uplink control message includes a first field and a second field.
  • the first field is used to indicate whether the first bit is included in the subsequence
  • the second field is used to indicate whether the first bit is in the subsequence.
  • the downlink control message includes the third field and the fourth field, the third field is used to indicate whether the first bit is included in the subsequence, and the fourth field is used to indicate the position of the first bit in the subsequence. Location.
  • using the type of the first bit as a frozen bit includes: mapping the type of the first bit to a frozen bit to obtain a position distribution sequence, and the position distribution sequence is used to characterize the type of each bit in the subsequence;
  • Decoding the first bit according to the first decoding algorithm corresponding to the frozen bit, and decoding the second bit according to the second decoding algorithm corresponding to the type of the second bit includes: respectively determining the first bit according to the position distribution sequence A decoding algorithm and a second decoding algorithm; the subsequence is decoded according to the third decoding algorithm, and the third decoding algorithm includes the first decoding algorithm and the second decoding algorithm.
  • the third decoding algorithm does not include soft value calculation, which is used to determine the bit value of each bit in the subsequence to be 0 or 1. Likelihood probability.
  • the third decoding algorithm when the type of the second bit includes information bits, the third decoding algorithm includes soft value calculation, which is used to determine whether the bit value of each bit in the subsequence is 0 or 1. The probability.
  • the method further includes: decoding the sub-sequence according to the third decoding algorithm to obtain a hard-valued sequence, and the hard-valued sequence includes a sequence corresponding to The first hard value of the first bit and the second hard value corresponding to the second bit; the first hard value is extracted from the hard value sequence as the decoding result.
  • the method further includes: decoding the sub-sequence according to the third decoding algorithm to obtain a hard-valued sequence, and the hard-valued sequence includes a sequence corresponding to the first The first hard value of one bit, and the second hard value corresponding to the second bit; the first hard value and the third hard value are extracted from the hard value sequence as the decoding result, and the third hard value corresponds to the second bit The hard value of the information bits in.
  • a polarization code decoding method includes: receiving a message from an encoding device, the message includes a subsequence to be decoded, the subsequence includes a first bit, and the type of the first bit is already Known bit; decode the first bit according to the first decoding algorithm corresponding to the type of the first bit.
  • the method provided by the above-mentioned fourth aspect may be executed by a decoding device or a device capable of supporting the decoding device to implement the functions required by the method, such as a chip system.
  • the first bit is included in the subsequence, and the type of the first bit is a known bit. Decoding the first bit by the first decoding algorithm corresponding to the type of the first bit can realize the decoding of the subsequence including the known bits.
  • the sub-sequence further includes a second bit
  • the type of the second bit includes at least one of a frozen bit, a parity bit, or an information bit
  • the method further includes: corresponding to the type of the second bit The second decoding algorithm decodes the second bit.
  • the message is an uplink control message, or a downlink control message.
  • the uplink control message includes a first field and a second field.
  • the first field is used to indicate whether the first bit is included in the subsequence
  • the second field is used to indicate whether the first bit is in the subsequence.
  • the downlink control message includes the third field and the fourth field, the third field is used to indicate whether the first bit is included in the subsequence, and the fourth field is used to indicate the position of the first bit in the subsequence. Location.
  • the first bit is decoded according to the first decoding algorithm corresponding to the type of the first bit
  • the second bit is decoded according to the second decoding algorithm corresponding to the type of the second bit , Including: respectively determining the first decoding algorithm and the second decoding algorithm according to the position distribution sequence corresponding to the subsequence; decoding the subsequence according to the third decoding algorithm, and the third decoding algorithm includes the first decoding algorithm And the second decoding algorithm.
  • the third decoding algorithm does not include soft value calculation, which is used to determine the bit value of each bit in the subsequence to be 0 or 1. Likelihood probability.
  • the third decoding algorithm when the type of the second bit includes information bits, the third decoding algorithm includes soft value calculation, which is used to determine whether the bit value of each bit in the subsequence is 0 or 1. The probability.
  • the method further includes: decoding the sub-sequence according to the third decoding algorithm to obtain a hard-valued sequence, and the hard-valued sequence includes a sequence corresponding to The first hard value of the first bit and the second hard value corresponding to the second bit; the first hard value is extracted from the hard value sequence as the decoding result.
  • the method further includes: decoding the sub-sequence according to the third decoding algorithm to obtain a hard-valued sequence, and the hard-valued sequence includes a sequence corresponding to the first The first hard value of one bit, and the second hard value corresponding to the second bit; the first hard value and the third hard value are extracted from the hard value sequence as the decoding result, and the third hard value corresponds to the second bit The hard value of the information bits in.
  • a polarization code encoding method includes: obtaining a first bit and a second bit respectively, where the type of the first bit is a known bit, and the type of the second bit includes frozen bit and parity. At least one of a bit or an information bit; generate a pilot sequence based on the first bit; encode the second bit to obtain the first code sequence; when determining to send the pilot sequence, send the second code sequence to the decoding device.
  • the second coding sequence includes a pilot sequence and a coding sequence.
  • the method provided by the above fifth aspect can be executed by an encoding device or a device capable of supporting the encoding device to implement the functions required by the method, such as a chip system.
  • the encoding device can determine whether to use known bits for redundancy filling, that is, whether to send the pilot sequence according to information such as network resource occupancy or decoding performance requirements.
  • the encoding device can send the pilot sequence, so that the decoding performance can be improved, and the demanding decoding performance requirement can be met.
  • the encoding device may not send the pilot sequence, so that the load on the air interface resources can be reduced.
  • the second coding sequence is the first coding sequence.
  • the second coding sequence is an uplink control message or a downlink control message.
  • the second coding sequence includes at least one subsequence.
  • the uplink control message includes the first field and the second field.
  • the first field is used to indicate whether the subsequence includes the first field.
  • Bit the second field is used to indicate the position of the first bit in the subsequence.
  • the second coding sequence includes at least one subsequence.
  • the downlink control message includes a third field and a fourth field, and the third field is used to indicate whether the subsequence includes the first Bit, the fourth field is used to indicate the position of the first bit in the subsequence.
  • the method further includes: determining to send the pilot sequence when the air interface resources are sufficient; or, determining not to send the pilot sequence when the air interface resources are in short supply.
  • a communication device in a sixth aspect, includes a receiver and a decoder:
  • a receiver configured to receive a message from an encoding device, the message includes a subsequence to be decoded, the subsequence includes a first bit, and the type of the first bit is a known bit;
  • the decoder is configured to use the type of the first bit as the target type, and decode the first bit according to the first decoding algorithm corresponding to the target type.
  • the target type includes parity bits or frozen bits.
  • the subsequence further includes a second bit
  • the type of the second bit includes at least one of frozen bits, parity bits, or information bits
  • the decoder is further used for:
  • the second bit is decoded according to the second decoding algorithm corresponding to the type of the second bit.
  • the message is an uplink control message, or a downlink control message.
  • the uplink control message includes a first field and a second field.
  • the first field is used to indicate whether the first bit is included in the subsequence
  • the second field is used to indicate whether the first bit is in the subsequence.
  • the downlink control message includes the third field and the fourth field, the third field is used to indicate whether the first bit is included in the subsequence, and the fourth field is used to indicate the position of the first bit in the subsequence. Location.
  • the decoder is specifically used for:
  • the type of the first bit is used as the parity bit;
  • the type of the first bit is taken as the frozen bit.
  • the decoder is specifically used for:
  • the first decoding algorithm and the second decoding algorithm are determined respectively;
  • the subsequence is decoded according to the third decoding algorithm, which includes the first decoding algorithm and the second decoding algorithm.
  • the third decoding algorithm does not include soft value calculation, which is used to determine the bit value of each bit in the subsequence to be 0 or 1. Likelihood probability.
  • the third decoding algorithm when the type of the second bit includes information bits, the third decoding algorithm includes soft value calculation, which is used to determine whether the bit value of each bit in the subsequence is 0 or 1. The probability.
  • the decoder when information bits are not included in the second bit type, the decoder is further used to:
  • the first hard value is extracted from the hard value sequence as the decoding result.
  • the decoder is further used to:
  • the first hard value and the third hard value are extracted from the hard value sequence as a decoding result, and the third hard value is a hard value corresponding to the information bit in the second bit.
  • a communication device in a seventh aspect, includes a receiver and a decoder:
  • a receiver configured to receive a message from an encoding device, the message includes a subsequence to be decoded, the subsequence includes a first bit, and the type of the first bit is a known bit;
  • the decoder is used to use the type of the first bit as the PC bit, and decode the first bit according to the first decoding algorithm corresponding to the PC bit.
  • the subsequence further includes a second bit
  • the type of the second bit includes at least one of frozen bits, parity bits, or information bits
  • the decoder is further used for:
  • the second bit is decoded according to the second decoding algorithm corresponding to the type of the second bit.
  • the message is an uplink control message, or a downlink control message.
  • the uplink control message includes a first field and a second field.
  • the first field is used to indicate whether the first bit is included in the subsequence
  • the second field is used to indicate whether the first bit is in the subsequence.
  • the downlink control message includes the third field and the fourth field, the third field is used to indicate whether the first bit is included in the subsequence, and the fourth field is used to indicate the position of the first bit in the subsequence. Location.
  • the decoder is specifically used for:
  • the first decoding algorithm and the second decoding algorithm are determined respectively;
  • the subsequence is decoded according to the third decoding algorithm, which includes the first decoding algorithm and the second decoding algorithm.
  • the third decoding algorithm does not include soft value calculation, which is used to determine the bit value of each bit in the subsequence to be 0 or 1. Likelihood probability.
  • the third decoding algorithm when the type of the second bit includes information bits, the third decoding algorithm includes soft value calculation, which is used to determine whether the bit value of each bit in the subsequence is 0 or 1. The probability.
  • the decoder when information bits are not included in the second bit type, the decoder is further used to:
  • the first hard value is extracted from the hard value sequence as the decoding result.
  • the decoder is further used to:
  • the first hard value and the third hard value are extracted from the hard value sequence as a decoding result, and the third hard value is a hard value corresponding to the information bit in the second bit.
  • a communication device which includes a receiver and a decoder:
  • a receiver configured to receive a message from an encoding device, the message includes a subsequence to be decoded, the subsequence includes a first bit, and the type of the first bit is a known bit;
  • the decoder is configured to use the type of the first bit as a frozen bit, and decode the first bit according to the first decoding algorithm corresponding to the frozen bit.
  • the subsequence further includes a second bit
  • the type of the second bit includes at least one of frozen bits, parity bits, or information bits
  • the decoder is further used for:
  • the second bit is decoded according to the second decoding algorithm corresponding to the type of the second bit.
  • the message is an uplink control message, or a downlink control message.
  • the uplink control message includes a first field and a second field.
  • the first field is used to indicate whether the first bit is included in the subsequence
  • the second field is used to indicate whether the first bit is in the subsequence.
  • the downlink control message includes the third field and the fourth field, the third field is used to indicate whether the first bit is included in the subsequence, and the fourth field is used to indicate the position of the first bit in the subsequence. Location.
  • the decoder is specifically used for:
  • the first decoding algorithm and the second decoding algorithm are determined respectively;
  • the subsequence is decoded according to the third decoding algorithm, which includes the first decoding algorithm and the second decoding algorithm.
  • the third decoding algorithm does not include soft value calculation, which is used to determine the bit value of each bit in the subsequence to be 0 or 1. Likelihood probability.
  • the third decoding algorithm when the type of the second bit includes information bits, the third decoding algorithm includes soft value calculation, which is used to determine whether the bit value of each bit in the subsequence is 0 or 1. The probability.
  • the decoder when information bits are not included in the second bit type, the decoder is further used to:
  • the first hard value is extracted from the hard value sequence as the decoding result.
  • the decoder is further used to:
  • the first hard value and the third hard value are extracted from the hard value sequence as a decoding result, and the third hard value is a hard value corresponding to the information bit in the second bit.
  • a communication device in a ninth aspect, includes a receiver and a decoder;
  • a receiver configured to receive a message from an encoding device, the message includes a subsequence to be decoded, the subsequence includes a first bit, and the type of the first bit is a known bit;
  • the decoder is configured to decode the first bit according to the first decoding algorithm corresponding to the type of the first bit.
  • the subsequence further includes a second bit
  • the type of the second bit includes at least one of frozen bits, parity bits, or information bits
  • the decoder is further used for:
  • the second bit is decoded according to the second decoding algorithm corresponding to the type of the second bit.
  • the message is an uplink control message, or a downlink control message.
  • the uplink control message includes a first field and a second field.
  • the first field is used to indicate whether the first bit is included in the subsequence
  • the second field is used to indicate whether the first bit is in the subsequence.
  • the downlink control message includes the third field and the fourth field, the third field is used to indicate whether the first bit is included in the subsequence, and the fourth field is used to indicate the position of the first bit in the subsequence. Location.
  • the decoder is specifically used for:
  • the subsequence is decoded according to the third decoding algorithm, which includes the first decoding algorithm and the second decoding algorithm.
  • the third decoding algorithm does not include soft value calculation, which is used to determine the bit value of each bit in the subsequence to be 0 or 1. Likelihood probability.
  • the third decoding algorithm when the type of the second bit includes information bits, the third decoding algorithm includes soft value calculation, which is used to determine whether the bit value of each bit in the subsequence is 0 or 1. The probability.
  • the decoder when the second bit type does not include information bits, the decoder is specifically used for:
  • the first hard value is extracted from the hard value sequence as the decoding result.
  • the decoder when the type of the second bit includes information bits, the decoder is specifically used for:
  • the first hard value and the third hard value are extracted from the hard value sequence as a decoding result, and the third hard value is a hard value corresponding to the information bit in the second bit.
  • a communication device in a tenth aspect, includes an encoder and a transmitter:
  • the encoder is used to obtain the first bit and the second bit respectively, the type of the first bit is a known bit, and the type of the second bit includes at least one of a frozen bit, a parity bit, or an information bit; based on the first bit Bits generate a pilot sequence; code the second bit to obtain the first code sequence;
  • the transmitter is used to send a second code sequence to the decoding device when determining to send the pilot sequence, the second code sequence includes the pilot sequence and the first code sequence.
  • the second coding sequence is the first coding sequence.
  • the second coding sequence is an uplink control message or a downlink control message.
  • the uplink control message includes a first field and a second field.
  • the first field is used to indicate whether the first bit is included in the subsequence
  • the second field is used to indicate whether the first bit is in the subsequence.
  • the downlink control message includes the third field and the fourth field, the third field is used to indicate whether the first bit is included in the subsequence, and the fourth field is used to indicate the position of the first bit in the subsequence. Location.
  • the encoder is further used for:
  • a communication device including: an input interface circuit and a logic circuit, the input interface circuit is used to receive a message from an encoding device, the message includes a subsequence to be decoded, and the subsequence includes The first bit, the type of the first bit is a known bit; the logic circuit is configured to execute the method according to any one of the first aspect to the fourth aspect 12-21 based on the subsequence.
  • a communication device including: a logic circuit and an output interface circuit, the logic circuit is configured to obtain a first bit and a second bit respectively, the type of the first bit is a known bit, and the The type of the second bit includes at least one of a frozen bit, a parity bit, or an information bit; a pilot sequence is generated based on the first bit; the second bit is encoded to obtain an encoding sequence, and the fifth The method according to any one of the aspects; the output interface circuit is configured to send an encoded message to a decoding device, the encoded message including the pilot sequence and the encoded sequence.
  • a communication device including: a memory, configured to store a program; a processor, configured to execute the program stored in the memory, and when the program is executed, cause the communication device to execute the foregoing The method according to any one of the first aspect to the fifth aspect.
  • the processor includes the memory.
  • the communication device is a chip or an integrated circuit.
  • a computer-readable storage medium is provided, and computer-readable instructions are stored in the computer-readable storage medium.
  • the communication device executes the foregoing The method according to any one of the first aspect to the fifth aspect.
  • a computer program product which when the computer program product runs on a communication device, causes the communication device to execute the method described in any one of the first aspect to the fifth aspect.
  • a chip system in a sixteenth aspect, includes a processor and may also include a memory, configured to implement the method described in any one of the first to fifth aspects.
  • the chip system can be composed of chips, and can also include chips and other discrete devices.
  • FIG. 1A is a schematic diagram of the architecture of a communication system to which an embodiment of this application is applicable;
  • FIG. 1B is a schematic diagram of the architecture of another communication system to which the embodiments of this application are applicable;
  • Figure 2 is a schematic diagram of a parallel decoding process in an embodiment of this application.
  • Fig. 3 is a flowchart of a method for fast decoding of polarization codes in an embodiment of the application
  • FIG. 4 is a flowchart of a polarization code encoding method provided by an embodiment of this application.
  • FIG. 5 is a flowchart of a polarization code decoding method provided by an embodiment of this application.
  • FIG. 6 is a schematic diagram of a known bit mapping method in a parallel decoding process provided by an embodiment of this application;
  • FIG. 7 is a flowchart of another polarization code decoding method provided by an embodiment of the application.
  • FIG. 8 is another schematic diagram of a known bit mapping method in a parallel decoding process provided by an embodiment of this application.
  • FIG. 9 is a flowchart of another polarization code decoding method provided by an embodiment of the application.
  • FIG. 10 is another schematic diagram of a known bit mapping method in a parallel decoding process provided by an embodiment of this application.
  • FIG. 11 is a flowchart of another polarization code decoding method provided by an embodiment of this application.
  • FIG. 12 is a flowchart of another polarization code decoding method provided by an embodiment of this application.
  • FIG. 13 is a flowchart of another polarization code decoding method provided by an embodiment of this application.
  • FIG. 14 is a flowchart of another polarization code decoding method provided by an embodiment of the application.
  • FIG. 16 is a schematic diagram of a polarization code decoding device provided by an embodiment of this application.
  • FIG. 17 is a schematic structural diagram of a communication device provided by an embodiment of this application.
  • FIG. 18 is a schematic structural diagram of another communication device provided by an embodiment of this application.
  • FIG. 19 is a schematic structural diagram of another communication device provided by an embodiment of this application.
  • 20 is a schematic structural diagram of another communication device provided by an embodiment of this application.
  • FIG. 21 is a schematic structural diagram of another communication device provided by an embodiment of this application.
  • the embodiments of the present application provide a method and device for encoding and decoding polarization codes.
  • the method and the device are based on the same technical concept. Since the principles of the method and the device to solve the problem are similar, the implementation of the device and the method can be referred to each other, and the repetition will not be repeated.
  • “and/or” describes the association relationship of the associated objects, indicating that there can be three types of relationships, for example, A and/or B, which can mean: A alone exists, and both A and B exist separately. There are three cases of B.
  • the character "/" generally indicates that the associated objects before and after are in an "or” relationship.
  • At least one involved in this application refers to one or more; multiple refers to two or more.
  • words such as “first”, “second”, and “third” are only used for the purpose of distinguishing description, and cannot be understood as indicating or implying relative importance. Nor can it be understood as indicating or implying order.
  • the encoding and decoding method provided by the embodiments of this application can be applied to the fifth generation (5G) communication system, such as 5G new radio (NR) system, device to device (D2D) communication system, Bluetooth Communication system, WiFi communication system or various communication systems applied in the future.
  • 5G fifth generation
  • NR new radio
  • D2D device to device
  • Bluetooth Communication Bluetooth Communication
  • WiFi Wireless Fidelity
  • FIG. 1A shows the architecture of a possible communication system 100 to which the encoding and decoding method provided by the embodiment of the application is applicable.
  • the communication system 100 includes: a network device 200 and one or more terminals 300 (including 3 terminals in FIG. 1A) located within the coverage of the network device 200.
  • the communication system 100 may also include a core network, and the network device 200 accesses the core network, so as to provide services for the terminals 300 within the coverage area.
  • the network device 200 provides wireless access to one or more terminals 300 within the coverage area of the network device 200.
  • the coverage areas between different network devices 200 may have overlapping areas. In the figure, the overlapped portion of the two elliptical areas and the overlapping area between the network device 200 and the network device 200'.
  • the network device 200 is a node in a radio access network (RAN), which may also be referred to as a base station, or a RAN node (or device).
  • the network device 200 may be: next generation nodeB (gNB), next generation evolved nodeB (Ng-eNB), transmission reception point (TRP), evolved type Node B (evolved Node B, eNB), radio network controller (RNC), Node B (Node B, NB), base station controller (BSC), base transceiver station (base transceiver station, BTS), home base station (for example, home evolved NodeB, or home Node B, HNB), baseband unit (BBU), or wireless fidelity (Wifi) access point (AP),
  • the network device 200 may also be a satellite, and the satellite may also be called a high-altitude platform, a high-altitude aircraft, or a satellite base station.
  • the network device 200 may also be other devices with network device functions.
  • the network device 200 may also be a device
  • the network device 200 may include a centralized unit (CU) and a distributed unit (DU).
  • the network device 200 may further include an active antenna unit (AAU).
  • the CU implements some of the functions of the network device 200
  • the DU implements some of the functions of the network device.
  • the CU is responsible for processing non-real-time protocols and services, implementing radio resource control (RRC), and packet data convergence protocol (packet data convergence protocol). , PDCP) layer function.
  • RRC radio resource control
  • PDCP packet data convergence protocol
  • the DU is responsible for processing the physical layer protocol and real-time services, and realizes the functions of the radio link control (RLC) layer, the media access control (MAC) layer, and the physical (PHY) layer.
  • RLC radio link control
  • MAC media access control
  • PHY physical
  • AAU realizes some physical layer processing functions, radio frequency processing and related functions of active antennas. Since the information of the RRC layer will eventually become the information of the PHY layer, or be transformed from the information of the PHY layer, under this architecture, high-level signaling, such as RRC layer signaling, can also be considered to be sent by the DU , Or, sent by DU+AAU.
  • the network apparatus 200 may be a device including one or more of a CU node, a DU node, and an AAU node. The embodiment of the application does not limit this. It should be noted that the network device 200 may be the network device 200 itself, or may be a chip in the network device 200.
  • the terminal 300 also called user equipment (UE), mobile station (MS), mobile terminal (MT), etc., is a device that provides voice and/or data connectivity to users .
  • the terminal 300 includes a handheld device with a wireless connection function, a vehicle-mounted device, and the like.
  • the terminal 300 may be: a mobile phone (mobile phone), a tablet computer, a notebook computer, a palmtop computer, a mobile internet device (MID), a wearable device (such as a smart watch, a smart bracelet, a pedometer, etc.) , In-vehicle equipment (for example, cars, bicycles, electric vehicles, airplanes, ships, trains, high-speed rail, etc.), virtual reality (VR) equipment, augmented reality (AR) equipment, industrial control (industrial control) Wireless terminals, smart home equipment (for example, refrigerators, TVs, air conditioners, electric meters, etc.), smart robots, wireless terminals in unmanned driving, wireless terminals in remote medical surgery, and smart grids
  • the terminal 300 may also be other devices with terminal functions.
  • the terminal 300 may also be a terminal that functions as a terminal in D2D communication.
  • the terminal 300 may be the terminal 300 itself, or may be a chip in the terminal 300.
  • the terminal 300 may be the mobile phone itself, or a chip in the mobile phone, such as a baseband chip.
  • FIG. 1B shows the architecture of another possible communication system 100 to which the encoding and decoding method provided by the embodiment of the application is applicable.
  • the communication system 100 includes: a network device 200 (including 4 network devices in FIG. 1B) and one or more terminals 300 (including 1 terminal in FIG. 1B) located within the coverage of the network device 200 .
  • the network device 200 may include a first network device 201 and a second network device 202.
  • the first network device 201 may be a macro base station.
  • a macro base station is a base station erected on an iron tower. This type of base station is very large, carries a large amount of user data, and has a wide coverage area, which can generally reach tens of kilometers.
  • the second network device 202 may be a micro base station, or a pico base station, or a femto base station.
  • the micro base station may be a miniaturized base station, which usually refers to a small base station installed in a building or a dense area. Such a base station has a small volume, a small coverage area, and a relatively low number of users carried.
  • the pico base station may be a smaller base station than the micro base station. Compared with the macro base station and the micro base station, the pico base station's single carrier transmission power and coverage capability are further reduced.
  • the femto base station can be accessed by home bandwidth and is a smaller base station than the macro base station, micro base station and pico base station.
  • the communication system 100 may also include a core network 400.
  • the first network device 201 can access the core network 400. Thereby providing services (for example, providing wireless access services) to the terminals 300 within its coverage.
  • the second network device 202 can access the core network 400 to provide services for the terminals 300 within its coverage.
  • the second network device 202 can also access the core network 400 through the first network device 201, so as to provide services for the terminals 300 within its coverage.
  • Communication systems usually use channel coding to improve the reliability of data transmission and ensure the quality of communication.
  • coding methods such as polarization codes and RM codes can be used.
  • the polarization code is a coding method that can gradually reach the channel capacity, and has excellent decoding performance in a wide working range (such as code length, code rate, or signal-to-noise ratio, etc.).
  • the decoding device divides the bits included in the sequence to be decoded into the following three types: information bits, frozen bits, and PC bits.
  • the information bits are used to carry information, and the information bits may include payload (payload) bits and cyclic redundancy check (cyclic redundancy check, CRC) bits.
  • Frozen bits refer to fixedly filled bits, and the bit value of the frozen bits is usually 0.
  • the PC bit is used for checking. For example, the PC bit can assist the CRC bit to check the payload bit.
  • the decoding device can decode the sequence to be decoded based on the type of the bit and use Polar decoding algorithms such as SC or SCL to achieve fast decoding and improve decoding efficiency.
  • the decoding process may include bit type identification, soft value calculation, hard value calculation, and hard value backtracking.
  • the decoding device can divide the sequence to be decoded into multiple subsequences to be decoded in advance according to the degree of parallelism, and perform serial softening on each subsequence of the multiple subsequences.
  • the decoding loop of value calculation and hard value calculation obtains the hard value sequence, and then the decoding device performs hard value backtracking on the hard value sequence, as shown in Figure 2.
  • the soft value calculation is the log-likelihood ratio (LLR) calculation
  • the hard value calculation refers to the decoding based on the LLR calculation result.
  • bit type identification means that the decoding device determines the type of each bit in the sequence to be decoded, and determines the decoding algorithm corresponding to the subsequence according to the combination of the types of bits in each subsequence.
  • Soft value calculation means that the decoding device determines the soft value of each bit in each subsequence.
  • Hard value calculation means that the decoding device uses the maximum likelihood estimation algorithm to determine the hard value of each bit in the sequence to be decoded according to the soft value of each bit in each subsequence to obtain the hard value sequence corresponding to the sequence to be decoded .
  • the hard value backtracking process means that the decoding device extracts the hard values of all information bits from the hard value sequence.
  • the soft value refers to the likelihood that the bit value is 0 or the likelihood that the bit value is 1, and the hard value refers to the bit value of the bit is 0 or 1.
  • the soft value of each bit in the subsequence can be indicated by the encoding device The soft value information is determined.
  • the decoding device when the decoding device decodes the sub-sequence, it may directly perform hard value calculation without performing soft value calculation.
  • the type of the bits in a sub-sequence are all frozen bits, and after the decoding device determines that the type of each bit in the sub-sequence is a frozen bit in the bit type identification, the sub-sequence can be determined according to the bit value of the frozen bit. The bit value of each bit in the sequence, eliminating the need for soft value calculations.
  • FIG. 3 shows a schematic flowchart of a method for rapid decoding of polarization codes.
  • the decoding device receives a sequence to be decoded from the encoding device, where the sequence to be decoded includes at least one bit.
  • sequence to be decoded may also be referred to as information to be decoded, such as a code word to be decoded, a code block to be decoded, a code word or a code block, etc., which are not limited in the embodiment of the present application.
  • the decoding device determines the type of each bit in the sequence to be decoded according to the position distribution sequence corresponding to the sequence to be decoded.
  • the position distribution sequence is used to indicate the type and position of each bit. For example, 00 represents frozen bits, 01 represents information bits, and 10 represents PC bits.
  • the sequence to be decoded is [bit 0 bit 1 bit 2 bit 3]
  • the position distribution sequence corresponding to the sequence to be decoded is [00 10 01 01]
  • the decoding device can determine the sequence to be decoded according to the position distribution sequence
  • the type of the middle bit is [freeze bit PC bit information bit information bit], that is, the type of bit 0 is frozen bit, the type of bit 1 is PC bit, and the types of bit 2 and bit 3 are information bits.
  • the position distribution sequence may be instructed by the encoding device to the decoding device.
  • the decoding device divides the sequence to be decoded to obtain at least one subsequence to be decoded.
  • the decoding device may divide the sequence to be decoded into 16 subsequences to be decoded, and each subsequence includes 8 bits.
  • the decoding device determines a decoding algorithm corresponding to each subsequence according to the type of each bit in each subsequence.
  • the decoding device can determine the decoding algorithm corresponding to each subsequence according to the combination and/or arrangement of the types of bits in each subsequence.
  • the decoding algorithm is based on the number of bits in the subsequence and the number of One or more of the combination of the bit types or the arrangement of the bit types in the subsequence is a simple decoding algorithm with the best profit derived from calculations and experiments.
  • the decoding algorithm can be used to determine the hard value sequence corresponding to the subsequence according to the subsequence.
  • the decoding algorithm can indicate whether to perform soft value calculations.
  • the decoding algorithm may indicate that soft value calculations are not performed; or, when the type of bits in the subsequence includes information bits, the decoding algorithm may indicate that soft value calculations are required. calculate. Further, the decoding algorithm can also indicate at least one of the number of paths that need to be retained when the path is split, the error correction mode, the soft decision mode, or the hard decision mode.
  • the decoding device uses the decoding algorithm corresponding to each subsequence to quickly decode the sequence to be decoded to obtain a hard value sequence corresponding to the sequence to be decoded.
  • the decoding device extracts the hard values of all information bits from the hard value sequence according to the position distribution sequence corresponding to the information bits to obtain a decoding result.
  • the decoding device can extract the hard values of all information bits from the hard value sequence according to the position distribution sequence corresponding to the information bits, namely 01, to obtain the decoding result, namely [1 1].
  • the decoding device completes the fast decoding of the sequence to be decoded.
  • the encoding device uses bits with known bit values to perform redundant filling to obtain decoding gains.
  • This redundancy mainly comes from the following two aspects: fixed filling caused by the ratio of uplink and downlink and feedback window; fixed filling caused by non-scheduling of physical downlink shared channel (Physical Downlink Shared Channel, PDSCH) resources.
  • PDSCH Physical Downlink Shared Channel
  • HARQ hybrid automatic repeat request
  • NACK Non-acknowledge character
  • Dual carrier needs to use 14 bits for feedback.
  • the 14 bits 8 bits are of type information bits, used to carry HARQ information, and the remaining 6 bits are of type known bits used to carry NACK information.
  • the 14 bits are [1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 0], 1 represents an information bit, which is used to carry HARQ information, and 0 represents a known bit, which is used to carry NACK information.
  • the encoding device can use some bits with known bit values to perform redundant filling, and then jointly encode these bits with other types of bits and send them to the decoding device, where the types of these bits can be called known Bits (known bits). Since the bit values of these bits are known, the decoding device can directly determine the bit values of these bits, which can improve the reliability of decoding and bring about decoding gains. For example, the encoding device can map known bits to low-reliability bit positions, so that information bits carrying useful information can be mapped to high-reliability bit positions, thereby improving decoding reliability and also improving broadcast information. Make the efficiency of transmission. For another example, the encoding device may map the known bits to the start position of the decoding sequence.
  • the decoding device can determine the bit value of the known bit according to the decoding result of the known bit at the starting position and the bit value of the known bit.
  • the decoding reliability of the known bit is known, and the path to be retained is selected based on the decoding reliability of the known bit to improve the decoding reliability. For example, 3 bits can split into 8 paths.
  • the decoding device can determine the reliability of the decoding of the known bit according to the decoding result of the known bit at the starting position and the bit value of the known bit. sex. If the decoding device wants to reserve one path, the decoding device can determine the path with the highest decoding reliability of known bits among the eight paths as the path to be reserved.
  • the encoding device can use known bits to perform redundancy filling, and then map the known bits and other types of bits into the resource block of the corresponding subchannel and send it to the decoding device.
  • the filling of known bits will additionally increase the load of the air interface resources.
  • the types of bits adapted by current decoding algorithms only include one or more of information bits, frozen bits, or PC bits
  • the decoding device cannot determine The decoding algorithm for this subsequence.
  • the decoding device can decode the known bits in the sub-sequence as information bits, and the decoding algorithm corresponding to the information bits includes soft value calculation and hard value calculation, which is expensive and decodes, thereby reducing decoding efficiency.
  • a polarization code encoding and decoding method and device provided in the embodiments of the present application are used to decode subsequences including known bits, and reduce overhead while ensuring the benefits of known bits. , Improve decoding efficiency.
  • a coding and decoding method of a polarization code provided by an embodiment of the present application will be introduced from the coding side and the decoding side respectively.
  • FIG. 4 is a schematic flowchart of a polarization code encoding method provided by an embodiment of the application.
  • the method may be applied to the communication system 100 shown in FIG. 1A or FIG. 1B.
  • the execution subject of this method may be an encoding device, which may be the network device 200 or at least one chip in the network device 200, or the terminal 300 or at least one chip in the terminal 300.
  • the encoding device can also be called the transmitting end, and the decoding device is the receiving end.
  • the encoding device is the network device 200
  • the decoding device is the terminal 300
  • the decoding device is the network device 200.
  • the method is applied to the communication system 100 shown in FIG.
  • the decoding device is the second network device 202 or the terminal 300; if the encoding device is the second network device 202, then The decoding device is the first network device 201 or the terminal 300.
  • the method will be introduced by taking the method applied to the communication system 100 shown in FIG. 1A or FIG. 1B as an example.
  • the encoding device obtains the first bit and the second bit respectively, where the type of the first bit is a known bit, and the type of the second bit is at least one of a frozen bit, a PC bit, or an information bit.
  • the encoding device may split the sequence to be encoded to obtain the first bit in the sequence to be encoded and the second bit in the sequence to be encoded respectively. For example, the encoding device may determine the type of each bit in the sequence to be encoded through the position distribution sequence corresponding to the sequence to be encoded, and then obtain the first bit and the second bit according to the type of each bit in the sequence to be encoded. .
  • the sequence to be encoded may be uplink control information (UCI), or downlink control information (DCI), etc.
  • the encoding device can According to the position distribution sequence, determine the type of each bit in the sequence to be coded as [known bit information bit information bit frozen bit PC bit known bit known bit PC bit], that is, bit 0 is a known bit, bit 1 is an information bit, bit 2 is an information bit, bit 3 is a frozen bit, bit 4 is a PC bit, bit 5 is a known bit, bit 6 is a known bit, and bit 7 is a PC bit. Further, the encoding device may separately obtain the first bit and the second bit according to the type of each bit, that is, the first type of bits include bit 0, bit 5, and bit 6, and the second type of bits include bit 1, bit 2. , Bit 3, bit 4, and bit 7.
  • the encoding device generates a pilot sequence based on the first bit.
  • the encoding device After the encoding device generates the pilot sequence based on the first bit, it may not send the pilot sequence. For example, if the encoding device determines not to use known bits for redundant padding, the encoding device does not send the pilot sequence; if the encoding device determines to use known bits for redundant padding, the encoding device sends the pilot sequence.
  • S403 The encoding device encodes the second bit to obtain the first encoding sequence.
  • the encoding device may determine whether to use known bits for redundancy filling according to information such as network resource occupation (for example, air interface resource occupation) or decoding performance requirements. For example, if the encoding device determines to use known bits for redundant filling, S404 is executed; if the encoding device determines not to use known bits for redundant filling, S405 is executed.
  • network resource occupation for example, air interface resource occupation
  • decoding performance requirements For example, if the encoding device determines to use known bits for redundant filling, S404 is executed; if the encoding device determines not to use known bits for redundant filling, S405 is executed.
  • the encoding device sends a second encoding sequence to the decoding device, where the second encoding sequence includes the pilot sequence and the first encoding sequence.
  • the encoding device can use known bits for redundant filling, that is, send the pilot sequence to the decoding device to meet the high requirements of decoding performance and improve the decoding performance. Code performance. Further, after determining to use known bits for redundancy filling (that is, determining to send the pilot sequence to the decoding device), the encoding device may combine the pilot sequence with the first encoding sequence according to the position distribution sequence corresponding to the sequence to be encoded They are respectively mapped to the corresponding resource blocks on the corresponding sub-channels and sent to the decoding device.
  • the encoding device sends a second encoding sequence to the decoding device, where the second encoding sequence is the first encoding sequence.
  • the encoding device may not use known bits for redundant filling, that is, not sending a pilot sequence to the decoding device, so as to reduce the load on the air interface resources. Further, after determining that the known bits are not used for redundancy filling (that is, determining that the pilot sequence is not sent to the decoding device), the encoding device may map the first encoding sequence to the corresponding position distribution sequence according to the position distribution sequence corresponding to the second bit The resource block on the subchannel is sent to the decoding device, and the pilot sequence is deleted.
  • the encoding device determines not to use known bits for redundant padding based on information such as network resource occupancy or decoding performance requirements before S402, the encoding device does not need to generate information based on the first bit.
  • the pilot sequence that is, the encoding device may only perform the steps shown in S401, S403, and S405.
  • the second coding sequence may be a downlink control message or an uplink control message.
  • the second coding sequence may include at least one subsequence.
  • the downlink control information includes a first field and a second field, and the first field is used to indicate whether the subsequence includes The first bit, the second field is used to indicate the position of the first bit in the subsequence; or, if the second coding sequence is an uplink control message, the uplink control message includes a third field and a fourth field.
  • the three fields are used to indicate whether the first bit is included in the subsequence, and the fourth field is used to indicate the position of the first bit in the subsequence.
  • the encoding device separately obtains the first bit and the second bit from the sequence to be encoded, and generates a pilot sequence based on the first bit, and the pilot sequence may not be sent.
  • the encoding device can determine whether to use known bits for redundancy filling, that is, whether to send the pilot sequence according to information such as network resource occupancy or decoding performance requirements.
  • the encoding device can send the pilot sequence, so that the decoding performance can be improved, and the demanding decoding performance requirement can be met.
  • the encoding device may not send the pilot sequence, so that the load on the air interface resources can be reduced.
  • the encoding device sends the second encoding sequence to the decoding device.
  • the decoding device receives the second coded sequence and decodes the second coded sequence.
  • the decoding device may divide the second coding sequence into at least one subsequence to be decoded according to the degree of parallelism, and perform parallel decoding on the at least one subsequence to be decoded.
  • the at least one subsequence to be decoded includes at least one of a first subsequence, a second subsequence or a third subsequence. Only the first bit is included in the first subsequence, and the type of the first bit is a known bit.
  • the second sub-sequence includes a first bit and a second bit, and the type of the second bit is at least one of a frozen bit, a PC bit, or an information bit. Only the second bit is included in the third subsequence.
  • the decoding device can refer to the decoding process shown in FIG. 3 to perform the second code sequence. Decoding. If the at least one subsequence to be decoded includes a third subsequence, the decoding device can decode the third subsequence with reference to the decoding process shown in FIG. 3.
  • the polarization code decoding method provided in the embodiment of the present application can be applied to the communication system 100 shown in FIG. 1A or FIG. 1B.
  • the execution subject of this method may be a decoding device, which may be the network device 200 or at least one chip in the network device 200, or the terminal 300 or at least one chip in the terminal 300.
  • the encoding device can also be called the transmitting end, and the decoding device is the receiving end.
  • the encoding device is the network device 200
  • the decoding device is the terminal 300
  • the decoding device is the network device 200.
  • the decoding device is the second network device 202 or the terminal 300; if the encoding device is the second network device 202, then The decoding device is the first network device 201 or the terminal 300.
  • the method will be introduced by taking the method applied to the communication system 100 shown in FIG. 1A or FIG. 1B as an example.
  • FIG. 5 shows a flowchart of a polarization code decoding method provided by an embodiment of the application.
  • the decoding device uses the type of the first bit as the PC bit, and decodes the first sub-sequence based on the decoding algorithm corresponding to the PC bit, wherein the first sub-sequence only includes the first bit.
  • the decoding device receives a message from the encoding device, the message includes a first subsequence, the first subsequence includes only the first bit, and the value range of the first bit is consistent with the value range of the PC bit.
  • the decoding device receives a message from the encoding device, the message may include a first subsequence, and the first subsequence includes only the first bit.
  • the first subsequence includes 8 bits, and the types of the 8 bits are all known bits.
  • the message can be an uplink control message or a downlink control message.
  • the encoding device is the terminal 300 and the decoding device is the network device 200
  • the message may be an uplink control message.
  • the encoding device is the first network device 201 and the decoding device is the second network device 202
  • the message may be a downlink control message.
  • the uplink control message When the message is an uplink control message, the uplink control message includes a first field and a second field, the first field is used to indicate whether the first subsequence includes the first bit, and the second field is used to indicate the first The position of the bit in the first subsequence.
  • the downlink control message when the message is a downlink control message, the downlink control message includes a third field and a fourth field, the third field is used to indicate whether the first subsequence includes the first bit, and the fourth field is used to indicate The position of the first bit in the first subsequence.
  • the first field and/or the second field may be a predefined field or a reserved field in the uplink control message
  • the third field and/or the fourth field may be a predefined field or a reserved field in the downlink control message.
  • the value range of the first bit is consistent with the value range of the PC bit, which means that the possible value of the first bit after decoding is consistent with the possible value of the PC bit after decoding.
  • the possible value of the PC bit after decoding is 0 or 1
  • the possible value of the first bit after decoding is 0 or 1.
  • the possible value of the first bit may be determined by the position distribution sequence corresponding to the known bit.
  • the position distribution sequence of the known bit may include 100 and 102, where 100 represents a known bit and the bit of the known bit The value is 0, 101 represents a known bit and the bit value of the known bit is 0.
  • the possible value of the PC bit can be determined by the decoding result of the previous subsequence, and the specific implementation process can refer to the prior art, which will not be repeated here.
  • the decoding device uses the type of the first bit as the PC bit, and decodes the first sub-sequence according to the decoding algorithm corresponding to the PC bit to obtain the hard value sequence corresponding to the first sub-sequence. Only the first hard value corresponding to the first bit is included in.
  • the characteristics of different types of bits are shown in Table 1.
  • the decoding result is used to characterize the value range of each type of bit after decoding
  • the value characteristic is used to characterize the calculation method to obtain the decoding result
  • the check and error correction are used to characterize each type of bit.
  • the contribution of the type of bit to the check and error correction in the decoding process, and the carrying content is used to characterize the meaning or function of the value of each type of bit after decoding.
  • the value range of the known bits is consistent with the value range of the PC bit and the information bit, the value range is 0 or 1, and the value range of the frozen bit is fixed to 0 .
  • the value characteristics of known bits are consistent with those of frozen bits.
  • the decoding result is known and does not require soft value calculations.
  • the value of PC bits does not require soft value calculations, it is consistent with Earlier decoding results are related, and the value of information bits not only requires soft value calculation but also related to earlier decoding results.
  • the known bits are consistent with the PC bits and need to participate in the verification but will not be flipped during error correction. The frozen bits do not participate in the verification.
  • the information bits not only need to participate in the verification but also during the error correction.
  • the known bits are consistent with the information bits and are used to carry messages, while the frozen bits are fixed and filled with no practical meaning, and the PC bits are used to carry the check value.
  • the decoding result and the checksum error correction feature are used to determine how to decode, which will be used in bit type identification and hard value calculation; the value feature can be used to determine whether to perform soft value calculation, in soft value It will be used in calculations; the carried content is used to determine whether to extract bits as information, and it will be used in hard value backtracking.
  • Table 1 Comparison table of characteristics of different types of bits
  • the decoding algorithm cannot adapt a subsequence including known bits, but can adapt a subsequence including at least one of frozen bits, PC bits, or information bits.
  • the decoding algorithm is determined in the bit type recognition and used in the hard value calculation. And bit type recognition and hard value calculation are related to the decoding result, checksum and error correction. Considering that the decoding result of the known bit is consistent with the decoding result of the PC bit, and the contribution of the known bit to the checksum error correction is also consistent with the contribution of the PC bit to the checksum error correction. Therefore, the decoding device can process the type of the first bit as the PC bit in bit type identification and hard value calculation.
  • the decoding device can decode the known bits as PC bits in the bit type identification and hard value calculation, so that the decoding algorithm corresponding to the PC bits can be adapted to decode the known bits to obtain the known bits. It also realizes the decoding of known bits while bringing the decoding performance. For example, 000, 110, and 111 represent frozen bits, 001 and 010 represent information bits, 011 represents PC bits, 100 represents a known bit with a value of 0, and 101 represents a known bit with a value of 1.
  • the position distribution sequence corresponding to the first sub-sequence is [100 101 100 100], that is, the types of the four bits in the first sub-sequence are all known bits.
  • the decoding device can map the known bits to PC bits, and the mapped position distribution sequence is [011 011 011 011], that is, the types of the mapped 4 bits are all PC Bits.
  • the decoding device can treat the type of the first bit as a frozen bit in the soft value calculation.
  • the decoding device can process the known bits as frozen bits, and the types of the bits in the first subsequence are all known bits, so the decoding device is decoding the first subsequence.
  • the soft value calculation can be skipped when coding, and the overhead caused by the soft value calculation can be reduced, so that the decoding efficiency can be improved.
  • 000, 110, and 111 represent frozen bits
  • 001 and 010 represent information bits
  • 011 represents PC bits
  • 100 represents a known bit with a value of
  • 101 represents a known bit with a value of 1.
  • the position distribution sequence corresponding to the first subsequence is [100 100 101 101].
  • the decoding device can map the known bits to frozen bits, and the mapped position distribution sequence is [000 000 000 000] , That is, the types of the 4 bits after mapping are all frozen bits.
  • the soft value calculation is only related to the value of the information bit, and has nothing to do with the value of the frozen bit or the PC bit.
  • the decoding device can treat the PC bits as frozen bits when performing soft value calculations on the PC bits, that is, skip soft value calculations. Therefore, in soft value calculation, the decoding device can also process frozen bits as PC bits.
  • the decoding device can process the type of the first bit as an information bit in the hard value backtracking.
  • the decoding device can process the known bits as information bits, so that the bit values of all known bits in the first subsequence can be obtained.
  • 000, 110, and 111 represent frozen bits
  • 001 and 010 represent information bits
  • 011 represents PC bits
  • 100 represents a known bit with a value of
  • 101 represents a known bit with a value of 1.
  • the position distribution sequence corresponding to the first subsequence is [101 101 100 101].
  • the decoding device maps the known bits to information bits, and the mapped position distribution sequence is [001 001 010 010]. That is, the types of the 4 bits after mapping are all information bits.
  • the decoding device may treat the type of the first bit as a PC bit; in soft value calculation, the decoding device may treat the type of the first bit as frozen Bits are processed; in the hard value backtracking, the decoding device can process the type of the first bit as an information bit, as shown in Figure 6. It should be understood that, since the decoding device can process the PC bit as a frozen bit in the soft value calculation, the decoding device can also use the type of the first bit as the PC bit in the soft value calculation.
  • the decoding device uses the type of the first bit as the PC bit, so that the decoding device can decode the first subsequence according to the decoding algorithm corresponding to the PC bit. So as to realize the decoding of known bits.
  • the decoding device may map the type of the first bit in the first subsequence to the PC bit according to the second field in the uplink control message or the fourth field in the downlink control message to obtain the first position distribution sequence .
  • the decoding device may map the type of the first bit in the first subsequence to the PC bit according to the position distribution sequence corresponding to the first subsequence to obtain the first position distribution sequence.
  • the decoding device can determine the decoding algorithm corresponding to the first sub-sequence according to the first position distribution sequence, and correspond to the first sub-sequence.
  • the decoding algorithm decodes the first subsequence to obtain the hard value sequence corresponding to the first subsequence.
  • the decoding algorithm corresponding to the first subsequence may be a decoding algorithm corresponding to the PC bit.
  • the decoding algorithm corresponding to the PC bit may be used to instruct to determine the bit value of the PC bit according to the decoding result of the previous subsequence.
  • the decoding algorithm corresponding to the PC bit can also be used to indicate the contribution of the bit value of the PC bit to the bit value of the information bit.
  • the type of bits indicated by the first position distribution sequence is only PC bits, and the decoding device may not perform soft value calculations on the first subsequence, and directly according to the first subsequence
  • the corresponding position distribution sequence determines the hard value sequence corresponding to the first sub-sequence. For example, 000, 110, and 111 represent frozen bits, 001 and 010 represent information bits, 011 represents PC bits, 100 represents a known bit with a value of 0, and 101 represents a known bit with a value of 1.
  • the position distribution sequence corresponding to the first sub-sequence is [101 101 100 101], and the decoding device may determine that the hard value sequence corresponding to the first sub-sequence is [1 1 0 1] according to the position distribution sequence corresponding to the first sub-sequence .
  • the hard value sequence only includes the first hard value corresponding to the first bit.
  • the decoding device extracts the first hard value from the hard value sequence as the decoding result of the first sub-sequence.
  • the decoding device can process the type of the first bit as an information bit. Since the first subsequence only includes the first bit, the decoding device can use the hard value sequence as the decoding result of the first subsequence. For example, the hard value sequence corresponding to the first subsequence determined by the decoding device is [1 1 0 1], and the decoding result of the first subsequence is [1 1 0 1].
  • the first subsequence includes only the first bit, the type of the first bit is a known bit, and the value range of the first bit is consistent with the value range of the PC bit.
  • the decoding device may use the type of the first bit as the PC bit to obtain the first position distribution sequence. Since the types of bits indicated by the first position distribution sequence are all PC bits, the decoding device can adapt the decoding algorithm (such as the decoding algorithm corresponding to the PC bits) according to the first position distribution sequence, so as to realize the Decoding of subsequences of known bits.
  • the decoding device decodes the first sub-sequence according to the decoding algorithm corresponding to the PC bit, there is no need to perform soft-value calculations on the first sub-sequence, thereby saving time.
  • the overhead generated by the soft value calculation improves the decoding efficiency.
  • FIG. 7 is a flowchart of another polarization code decoding method provided by an embodiment of the present application.
  • the decoding device uses the type of the first bit as the frozen bit, and decodes the first sub-sequence based on the decoding algorithm corresponding to the frozen bit, wherein the first sub-sequence only includes the first bit.
  • the decoding device receives a message from the encoding device, the message includes a first subsequence, the first subsequence includes only the first bit, and the value range of the first bit is consistent with the value range of the frozen bit.
  • the value range of the first bit is consistent with the value range of the frozen bit, which means that the possible value of the first bit after decoding is consistent with the possible value of the frozen bit after decoding.
  • the bit value of the frozen bit is fixed to 0, and the bit value of the first bit is also fixed to 0.
  • the bit value of the first bit may be fixed to zero.
  • the possible value of the first bit can be determined by the position distribution sequence corresponding to the known bit.
  • the position distribution sequence of the known bit may only include 100, where 100 represents a known bit and the bit value of the known bit 0.
  • the decoding device uses the type of the first bit as a frozen bit, and decodes the first sub-sequence according to the decoding algorithm corresponding to the frozen bit to obtain a hard value sequence corresponding to the first sub-sequence. Only the first hard value corresponding to the first bit is included.
  • the characteristics of the different types of bits can be as shown in Table 2.
  • Table 2 in terms of the decoding results, the value range of the known bit is consistent with the value range of the frozen bit, and the value range is fixed at 0, while the value range of the PC bit and the information bit is 0 or 1. .
  • value characteristics the value characteristics of known bits are consistent with those of frozen bits.
  • the decoding result is known and does not require soft value calculations.
  • the value of PC bits does not require soft value calculations, it is consistent with Earlier decoding results are related, and the value of information bits not only requires soft value calculation but also related to earlier decoding results.
  • the known bits are consistent with the PC bits and need to participate in the verification but will not be flipped during error correction.
  • the frozen bits do not participate in the verification.
  • the information bits not only need to participate in the verification but also during the error correction. Was flipped.
  • the known bits are consistent with the information bits and are used to carry messages, while the frozen bits are fixed and filled with no practical meaning, and the PC bits are used to carry the check value.
  • the decoding result and the checksum error correction feature are used to determine how to decode, which will be used in bit type identification and hard value calculation; the value feature can be used to determine whether to perform soft value calculation, in soft value It will be used in calculations; the carried content is used to determine whether to extract bits as information, and it will be used in hard value backtracking.
  • the decoding algorithm cannot adapt a subsequence including known bits, but can adapt a subsequence including at least one of frozen bits, PC bits, or information bits.
  • the decoding algorithm is determined in the bit type recognition and used in the hard value calculation. And bit type recognition and hard value calculation are related to the decoding result, checksum and error correction.
  • the decoding device can process the type of the first bit as the frozen bit in the bit type identification and hard value calculation. Although the type of the first bit is used as the frozen bit, the first bit cannot participate in the verification, but the decoding process can be simplified, more simplified decoding code patterns can be generated, and the decoding parallelism can be improved.
  • the decoding device may treat the type of the first bit as a frozen bit; in soft value calculation, the decoding device may treat the type of the first bit as a frozen bit. Bits are processed; in the hard value backtracking, the decoding device can process the type of the first bit as an information bit, as shown in FIG. 8. It should be understood that, since the decoding device can process the PC bit as a frozen bit in the soft value calculation, the decoding device can also use the type of the first bit as the PC bit in the soft value calculation.
  • the first subsequence includes only the first bit
  • the decoding device uses the type of the first bit as a frozen bit, so that the decoding device can decode the first subsequence according to the decoding algorithm corresponding to the frozen bit. So as to realize the decoding of known bits.
  • the decoding apparatus may map the type of the first bit in the first subsequence to frozen bits according to the second field in the uplink control message or the fourth field in the downlink control message to obtain the first position distribution sequence .
  • the decoding device may map the type of the first bit in the first subsequence to frozen bits according to the position distribution sequence corresponding to the first subsequence to obtain the first position distribution sequence.
  • the decoding device may determine the decoding algorithm corresponding to the first subsequence according to the first position distribution sequence, and decode the first subsequence according to the decoding algorithm corresponding to the first subsequence to obtain the first subsequence The corresponding hard value sequence. Since the first subsequence only includes the first bit, and the type of the bit indicated by the first position distribution sequence is only the frozen bit, the decoding algorithm corresponding to the first subsequence may be the decoding algorithm corresponding to the frozen bit. For example, the decoding algorithm corresponding to the frozen bit can be used to indicate that the bit value of the frozen bit is 0. For another example, the frozen bit may also be used to indicate that it does not participate in the verification of the bit value of the information bit.
  • the type of bits indicated by the first position distribution sequence is only frozen bits, and the decoding device may not perform soft value calculation on the first subsequence, and directly according to the first subsequence
  • the corresponding position distribution sequence determines the hard value sequence corresponding to the first sub-sequence. For example, 000, 110, and 111 represent frozen bits, 001 and 010 represent information bits, 011 represents PC bits, and 100 represents a known bit with a value of 0.
  • the position distribution sequence corresponding to the first sub-sequence is [100 100 100 100], and the decoding device may determine that the hard value sequence corresponding to the first sub-sequence is [0 0 0 0] according to the position distribution sequence corresponding to the first sub-sequence .
  • the hard value sequence only includes the first hard value corresponding to the first bit.
  • the decoding device extracts the first hard value from the hard value sequence as a decoding result.
  • the decoding device can process the type of the first bit as an information bit. Since the first subsequence only includes the first bit, the decoding device can use the hard value sequence as the decoding result of the first subsequence. For example, the hard value sequence corresponding to the first subsequence determined by the decoding device is [0 0 0 0], and the decoding result of the first subsequence is [0 0 0 0].
  • the first subsequence includes only the first bit, the type of the first bit is a known bit, and the value range of the first bit is consistent with the value range of the frozen bit.
  • the decoding device may use the type of the first bit as a frozen bit to obtain the first position distribution sequence. Since the bit types indicated by the first position distribution sequence are all frozen bits, the decoding device can adapt the decoding algorithm (such as the decoding algorithm corresponding to the frozen bit) according to the first position distribution sequence, so as to realize the Decoding of subsequences of known bits.
  • the decoding device decodes the first sub-sequence according to the decoding algorithm corresponding to the frozen bit, there is no need to perform soft-value calculations on the first sub-sequence, thus saving time.
  • the overhead generated by the soft value calculation improves the decoding efficiency.
  • FIG. 9 shows a flowchart of another polarization code decoding method provided by an embodiment of the application.
  • the decoding device uses the type of the first bit as the target type and is based on the target type.
  • the decoding algorithm corresponding to the type decodes the first subsequence, where the first subsequence only includes the first bit, and the target type includes PC bits or frozen bits.
  • the decoding device receives a message from the encoding device, the message includes a first subsequence, and the first subsequence includes only the first bit.
  • the value range of the first bit may be consistent with the value range of the PC bit, that is, the value range is 0 or 1, or the value range of the first bit may be consistent with the value range of the frozen bit, that is, the value range Is 0.
  • the decoding device may use the type of the first bit as the target type according to the value range of the first bit, and decode the first subsequence based on the decoding algorithm corresponding to the target type to obtain the first subsequence.
  • the hard value sequence corresponding to the sequence The hard value sequence only includes the first hard value corresponding to the first bit, and the target type includes PC bits or frozen bits.
  • the decoding device may treat the type of the first bit as the target type; in soft value calculation, the decoding device may treat the type of the first bit as the frozen bit Perform processing; in the hard value backtracking, the decoding device can process the type of the first bit as an information bit, as shown in FIG. 10. It should be understood that, since the decoding device can process the PC bit as a frozen bit in the soft value calculation, the decoding device can also use the type of the first bit as the PC bit in the soft value calculation.
  • the decoding device can execute the content shown in S902 and S904; if the value range of the first bit is the same as If the value range of the frozen bit is consistent, the target type is a frozen bit, and the decoding device can execute the content shown in S903 and S904.
  • the decoding device may use the type of the first bit as the PC bit, and decode the first subsequence according to the decoding algorithm corresponding to the PC bit Code to obtain the hard value sequence corresponding to the first sub-sequence.
  • the decoding device may use the type of the first bit as the frozen bit, and decode the first subsequence according to the decoding algorithm corresponding to the frozen bit Code to obtain the hard value sequence corresponding to the first sub-sequence.
  • S903 is the same as the specific implementation of S702 in FIG. 7, and will not be repeated here.
  • the decoding device extracts the first hard value from the hard value sequence as the decoding result of the first sub-sequence.
  • the decoding device can process the type of the first bit as an information bit. Since the first subsequence only includes the first bit, the decoding device can use the hard value sequence as the decoding result of the first subsequence. For example, the hard value sequence corresponding to the first subsequence determined by the decoding device is [1 1 0 1], and the decoding result of the first subsequence is [1 1 0 1].
  • the decoding device may use the type of the first bit as the target type to obtain the first position distribution sequence, and the target type is a PC bit or a frozen bit. Since the types of the bits indicated by the first position distribution sequence are all PC bits or all frozen bits, the decoding device can adapt the decoding algorithm according to the first position distribution sequence, thereby realizing the correction of the sub-arrays including known bits. Decoding of the sequence.
  • the decoding device decodes the first subsequence according to the decoding algorithm corresponding to the target type, there is no need to perform soft value calculations on the first subsequence, thereby saving The overhead caused by the soft value calculation is improved, and the decoding efficiency is improved.
  • FIG. 11 shows a flowchart of another polarization code decoding method provided by an embodiment of the application.
  • the decoding device decodes the first subsequence according to the decoding algorithm corresponding to the type of the first bit, wherein the first subsequence only includes the first bit.
  • the decoding device receives a message from the encoding device, the message includes a first subsequence, and the first subsequence includes only the first bit.
  • the value range of the first bit may be consistent with the value range of the PC bit, or may be consistent with the value range of the frozen bit, which is not limited in the embodiment of the present application.
  • the specific implementation of S1101 is consistent with the specific implementation of S501 in FIG. 5, or the specific implementation of S701 in FIG. 7, or the specific implementation of S901 in FIG. 9, and will not be repeated here.
  • the decoding device decodes the first subsequence according to the first decoding algorithm corresponding to the known bits to obtain the hard value sequence corresponding to the first subsequence.
  • the hard value sequence includes only the hard value sequence corresponding to the first bit. The first hard value.
  • the first decoding algorithm corresponding to the known bit can be used to decode the first bit. Since the first subsequence only includes the first bit, the first decoding algorithm corresponding to the known bit can also be used to decode the first subsequence.
  • the first decoding algorithm corresponding to the known bit may be used to determine the bit value of the first bit.
  • the position distribution sequence corresponding to the known bit includes 100 and 101, where 100 represents a known bit with a bit value of 0, and 101 represents a known bit with a bit value of 1.
  • the decoding device may determine the hard-valued sequence corresponding to the first sub-sequence according to the position distribution sequence corresponding to the first sub-sequence and the position distribution sequence corresponding to the known bit.
  • the position distribution sequence corresponding to the first subsequence is [100 101 101 100]
  • the hard value sequence corresponding to the first subsequence is [0 1 1 0].
  • the first decoding algorithm corresponding to the known bit can also be used to characterize the contribution to obtaining the bit value of the information bit. For example, a hard value decision is made based on the decoding result of the known bit and the bit value of the known bit.
  • the first decoding algorithm corresponding to the known bit may be referred to as the first decoding algorithm corresponding to the type of the first bit, or the first decoding algorithm corresponding to the type of the first bit.
  • the code algorithm, or called the first decoding algorithm is not limited in the embodiment of the present application.
  • the decoding device extracts the first hard value from the hard value sequence as the decoding result of the first sub-sequence.
  • the decoding device extracts the first hard value of all the first bits from the hard value sequence according to the position distribution sequence corresponding to the first subsequence as the decoding result of the first subsequence.
  • the decoding device may decode the first subsequence according to the decoding algorithm corresponding to the known bit. In the decoding process, there is no need to perform soft value calculations, which realizes the decoding of the subsequences including known bits, reduces the overhead, and can improve the decoding efficiency.
  • the second subsequence includes the first bit and the second bit.
  • the type of the first bit is a known bit, and the type of the second bit is a PC bit. At least one of bits or information bits.
  • FIG. 12 shows a flowchart of another polarization code decoding method provided by an embodiment of the present application.
  • the decoding device uses the type of the first bit as the PC bit, decodes the first bit based on the decoding algorithm corresponding to the PC bit, and decodes the second bit based on the second decoding algorithm corresponding to the second bit type.
  • the bits are decoded, so as to realize the decoding of the second sub-sequence.
  • the second subsequence includes the first bit and the second bit.
  • the decoding device receives a message from the encoding device, the message includes a second subsequence, the second subsequence includes a first bit and a second bit, and the value range of the first bit is the same as the value of the PC bit The scope is consistent.
  • the decoding device receives a message from the encoding device, and the message may include a second subsequence including a first bit and a second bit.
  • the second subsequence includes 8 bits, and the type of the 8 bits is in order [known bit frozen bit PC bit information bit information bit known bit known bit information bit].
  • the message can be an uplink control message or a downlink control message.
  • the encoding device is the terminal 300 and the decoding device is the network device 200
  • the message may be an uplink control message.
  • the encoding device is the first network device 201 and the decoding device is the second network device 202
  • the message may be a downlink control message.
  • the uplink control message When the message is an uplink control message, the uplink control message includes a first field and a second field.
  • the first field is used to indicate whether the second subsequence includes the first bit, and the second field is used to indicate the first field. The position of the bit in the second subsequence.
  • the downlink control message when the message is a downlink control message, the downlink control message includes a third field and a fourth field, the third field is used to indicate whether the second subsequence includes the first bit, and the fourth field is used to indicate The position of the first bit in the second subsequence.
  • the first field and/or the second field may be a predefined field or a reserved field in the uplink control message, and the third field and/or the fourth field may be a predefined field or a reserved field in the downlink control message.
  • the value range of the first bit is consistent with the value range of the PC bit, which means that the possible value of the first bit after decoding is consistent with the possible value of the PC bit after decoding.
  • the possible value of the PC bit after decoding is 0 or 1
  • the possible value of the first bit after decoding is 0 or 1.
  • the possible value of the first bit may be determined by the position distribution sequence corresponding to the known bit.
  • the position distribution sequence of the known bit may include 100 and 102, where 100 represents a known bit and the bit of the known bit The value is 0, 101 represents a known bit and the bit value of the known bit is 0.
  • the possible value of the PC bit can be determined by the decoding result of the previous subsequence, and the specific implementation process can refer to the prior art.
  • the decoding device uses the type of the first bit as the PC bit to obtain the first position distribution sequence.
  • the value range of the first bit is consistent with the value range of the PC bit.
  • the decoding device can process the type of the first bit as the PC bit. For example, in bit type identification and hard value calculation, the decoding device can process the type of the first bit as a PC bit; in soft value calculation, the decoding device can process the type of the first bit as a frozen bit ; In the hard value backtracking, the decoding device can process the type of the first bit as an information bit, as shown in Figure 6.
  • the specific implementation process please refer to the content in S502 in FIG. 5, which will not be repeated here.
  • the decoding device may map the type of the first bit included in the second subsequence to PC bits (that is, map the known bits to PC bits according to the second field in the uplink control message or the fourth field in the downlink control message). PC bits) to obtain the first position distribution sequence.
  • the decoding device may determine the type of each bit in the second subsequence according to the position distribution sequence corresponding to the second subsequence, and the type in the second subsequence is known based on the type of each bit in the second subsequence The type of the first bit of the bit is mapped to the PC bit.
  • 000, 110, and 111 represent frozen bits
  • 001 and 010 represent information bits
  • 011 represents PC bits
  • 100 represents a known bit with a value of
  • 101 represents a known bit with a value of 1.
  • the position distribution sequence corresponding to the second sub-sequence is [011 101 001 010]
  • the decoding device can determine that the type of each bit in the second sub-sequence is [PC bit known bit information bit information bit], and the known bit Mapping to PC bits, the first position distribution sequence is [011 011 001 010].
  • the decoding device determines a third decoding algorithm according to the first position distribution sequence.
  • the third decoding algorithm includes the first decoding algorithm and the second decoding algorithm.
  • the third decoding algorithm can be used to decode the second subsequence to obtain the hard value sequence corresponding to the second subsequence.
  • the third decoding algorithm may include soft value calculation and hard value calculation, or include hard value calculation.
  • the third decoding algorithm may also include a first decoding algorithm and a second decoding algorithm, that is to say, the third decoding algorithm can realize all the functions of the first decoding algorithm and realize the second decoding algorithm. All functions of the code algorithm.
  • the first decoding algorithm can be used to decode the first bit in the second subsequence. For example, when the decoding device processes the type of the first bit as PC bits, the first decoding algorithm is PC bits.
  • the second decoding algorithm may be used to decode the second bit in the second subsequence. For example, when the type of the second bit only includes frozen bits, the second decoding algorithm is a decoding algorithm corresponding to the frozen bits.
  • the decoding device may determine the first decoding algorithm and the second decoding algorithm respectively according to the first position distribution sequence. For example, the decoding device may determine the number of first bits or the position of the first bit in the second subsequence and other information based on the first position distribution sequence and the position distribution sequence corresponding to the second subsequence, and based on the first bit Information such as the number of bits or the position of the first bit in the second subsequence determines the first decoding algorithm for decoding the first bit.
  • the decoding device may determine the type of bits included in the second subsequence according to the first position distribution sequence, and determine the third translation according to the combination and/or arrangement of the types of bits included in the second subsequence. Code algorithm. Taking the combination mode as an example, different combination modes can correspond to the same decoding algorithm.
  • combination method 1 is [freeze bit freeze bit PC bit PC bit], the corresponding decoding algorithm of combination method 1 is decoding algorithm 1; combination method 2 is [information bit information bit PC bit PC bit], and combination method 2 corresponds to The decoding algorithm is decoding algorithm 2; combination method 3 is [PC bit PC bit frozen bit information bit], the corresponding decoding algorithm of combination method 3 is decoding algorithm 3; combination method 4 is [information bit information bit PC bit Freeze bit], the decoding algorithm corresponding to the combination mode 4 is decoding algorithm 2; it will not be listed here.
  • the third decoding algorithm may be calculated and experimentally obtained based on at least one of the number of bits in the subsequence, the combination of the types of bits in the subsequence, or the arrangement of the types of bits in the subsequence in advance. Simple decoding algorithm with the best profit.
  • the decoding device may search for the third decoding algorithm corresponding to the combination mode of the bit type indicated by the first position distribution sequence according to the combination table and the decoding algorithm correspondence table; or according to the first position distribution sequence The identification number of the combination mode of the indicated bit type, searching for the third decoding algorithm corresponding to the combination mode of the bit type indicated by the first position distribution sequence, etc.
  • the decoding device decodes the second sub-sequence according to the third decoding algorithm to obtain the hard value sequence corresponding to the second sub-sequence.
  • the hard value sequence includes the first hard value corresponding to the first bit and the corresponding The second hard value of the second bit.
  • the third decoding algorithm may not include soft value calculation. This means that the decoding device does not need to perform soft value calculation on the second sub-sequence, which can save the overhead caused by soft value calculation, thereby improving decoding efficiency.
  • the decoding device may determine the first bit according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the bit value of the frozen bit, and the bit value of the known bit. The hard value sequence corresponding to the two sub-sequences.
  • the decoding device can determine the second subsequence according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the bit value of the PC bit, and the bit value of the known bit The corresponding hard value sequence. If the type of the second bit includes frozen bits and PC bits, the decoding device can be based on the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the bit value of the PC bit, the bit value of the frozen bit, and the known bit Determine the hard value sequence corresponding to the second sub-sequence.
  • the decoding device can obtain the hard values of the bits in the second subsequence as [0 0 0 0] according to the first position distribution sequence, the decoding algorithm corresponding to the PC bit and the decoding algorithm corresponding to the frozen bit.
  • the decoding device can determine that bit 1 and bit 2 are known bits according to the position distribution sequence corresponding to the second subsequence, and The bit value of bit 1 is 0, and the bit value of bit 2 is 1. Combining with the hard value obtained according to the decoding algorithm corresponding to the frozen bit, it can be determined that the hard value sequence corresponding to the second subsequence is [0 0 1 0].
  • the third decoding algorithm includes soft value calculation. It means that the decoding device needs to perform soft value calculation and hard value calculation on the second sub-sequence. Specifically, if the type of the second bit only includes information bits, the decoding device can be based on the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, and the known For the bit value of the bit, the hard value sequence corresponding to the second subsequence is determined by the maximum likelihood estimation algorithm.
  • the decoding device can be based on the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, and the known bit
  • the bit value of and the bit value of the frozen bit are determined by the maximum likelihood estimation algorithm to determine the hard value sequence corresponding to the second sub-sequence.
  • the decoding device can distribute the sequence according to the position corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, and the known bit
  • the bit value of and the bit value of the PC bit are used to determine the hard value sequence corresponding to the second sub-sequence through the maximum likelihood estimation algorithm.
  • the decoding device may according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, and the soft value of each bit in the second subsequence, Knowing the bit value of the bit, the bit value of the PC bit, and the bit value of the frozen bit, the hard value sequence corresponding to the second subsequence is determined through the maximum likelihood estimation algorithm.
  • the decoding device may determine the decoding result of the second subsequence according to the hard value sequence. Specifically, if the type of the second bit includes information bits, the decoding device executes the content shown in S1205; if the type of the second bit does not include information bits, the decoding device executes the content shown in S1206.
  • the decoding device extracts the first hard value and the third hard value from the hard value sequence as the decoding result of the second subsequence, and the third hard value corresponds to the first The hard value of the information bit in the two bits.
  • the decoding device can map the type of the first bit to the information bit to obtain the mapped position distribution sequence, and based on the mapped position distribution sequence, extract the first hard value and the third hard value from the hard value sequence as the first The decoding result of the two subsequences.
  • 000, 110, and 111 represent frozen bits
  • 001 and 010 represent information bits
  • 011 represents PC bits
  • 100 represents a known bit with a value of
  • 101 represents a known bit with a value of 1.
  • the position distribution sequence corresponding to the second sub-sequence is [100 011 001 001]
  • the hard value sequence corresponding to the second sub-sequence is [0 1 1 1].
  • the decoding device may map the type of the first bit to the information bit, and obtain the mapped position distribution sequence as [001 011 001 001]. Based on the mapped position distribution sequence, the decoding device extracts the hard values of all information bits from the hard value sequence to obtain [0 1 1], and the decoding result is [0 1 1].
  • the decoding result of the first bit in the second subsequence is [0]
  • the decoding result of the information bit in the second subsequence is [1 1].
  • the decoding device extracts the first hard value from the hard value sequence as the decoding result of the second subsequence.
  • the decoding device can map the type of the first bit to the information bit to obtain the mapped position distribution sequence, and based on the mapped position distribution sequence, extract the first hard value from the hard value sequence as the translation of the second subsequence. Code result.
  • the second subsequence includes the first bit and the second bit
  • the type of the first bit is a known bit
  • the value range of the first bit is consistent with the value range of the PC bit
  • the first bit is the same as the PC bit.
  • the type of two bits includes at least one of PC bits, frozen bits, or information bits.
  • the decoding device may use the type of the first bit as the PC bit, decode the first bit based on the decoding algorithm corresponding to the PC bit, and decode the second bit based on the decoding algorithm corresponding to the second bit type , So as to realize the decoding of the sub-sequence including the known bits.
  • the type of the second bit does not include information bits
  • the decoding device does not need to perform soft value calculation on the second sub-sequence, thereby saving overhead caused by performing soft value calculation and improving decoding efficiency.
  • FIG. 13 shows a flowchart of another polarization code decoding method provided by an embodiment of the present application.
  • the decoding device uses the type of the first bit as a frozen bit, decodes the first bit based on the decoding algorithm corresponding to the frozen bit, and decodes the second bit based on the second decoding algorithm corresponding to the second bit type.
  • the bits are decoded, so as to realize the decoding of the second sub-sequence.
  • the second subsequence includes the first bit and the second bit.
  • the decoding device receives a message from the encoding device, the message includes a second subsequence, the second subsequence includes a first bit and a second bit, the value range of the first bit and the value of the frozen bit
  • the scope is consistent.
  • the value range of the first bit is consistent with the value range of the frozen bit, which means that the possible value of the first bit after decoding is consistent with the possible value of the frozen bit after decoding.
  • the bit value of the frozen bit is fixed to 0, and the bit value of the first bit is also fixed to 0.
  • the bit value of the first bit may be fixed to zero.
  • the possible value of the first bit can be determined by the position distribution sequence corresponding to the known bit.
  • the position distribution sequence of the known bit may only include 100, where 100 represents a known bit and the bit value of the known bit 0.
  • the decoding device uses the type of the first bit as a frozen bit to obtain the first position distribution sequence.
  • the value range of the first bit is consistent with the value range of the frozen bit.
  • the decoding device can treat the type of the first bit as the frozen bit. For example, in bit type identification and hard value calculation, the decoding device can process the type of the first bit as a frozen bit; in soft value calculation, the decoding device can process the type of the first bit as a frozen bit ; In the hard value backtracking, the decoding device can treat the type of the first bit as an information bit, as shown in Figure 8. For the specific implementation process, please refer to the content in S702 in FIG. 7, which will not be repeated here.
  • the decoding apparatus may map the type of the first bit included in the second subsequence to frozen bits (that is, map the known bits to frozen bits according to the second field in the uplink control message or the fourth field in the downlink control message) Freeze bits) to obtain the first position distribution sequence.
  • the decoding device may determine the type of each bit in the second subsequence according to the position distribution sequence corresponding to the second subsequence, and the type in the second subsequence is known based on the type of each bit in the second subsequence The type of the first bit of the bit is mapped to a frozen bit.
  • 000, 110, and 111 represent frozen bits
  • 001 and 010 represent information bits
  • 011 represents PC bits
  • 100 represents a known bit with a value of
  • 101 represents a known bit with a value of 1.
  • the position distribution sequence corresponding to the second sub-sequence is [011 101 001 010]
  • the decoding device can determine that the type of each bit in the second sub-sequence is [PC bit known bit information bit information bit], and the known bit Mapping into frozen bits, the first position distribution sequence is [011 000 001 010].
  • the decoding device determines a third decoding algorithm according to the first position distribution sequence.
  • the third decoding algorithm includes the first decoding algorithm and the second decoding algorithm.
  • the third decoding algorithm is used to decode the second subsequence to obtain the hard value sequence corresponding to the second subsequence.
  • the third decoding algorithm may include soft value calculation and hard value calculation, or include hard value calculation.
  • the third decoding algorithm may also include a first decoding algorithm and a second decoding algorithm, that is to say, the third decoding algorithm can realize all the functions of the first decoding algorithm and realize the second decoding algorithm. All functions of the code algorithm.
  • the first decoding algorithm can be used to decode the first bit in the second subsequence. For example, when the decoding device processes the type of the first bit as a frozen bit, the first decoding algorithm is a frozen bit Corresponding decoding algorithm.
  • the second decoding algorithm can be used to decode the second bit in the second subsequence. For example, when the type of the second bit only includes PC bits, the second decoding algorithm is the algorithm corresponding to the PC bits.
  • S1303 is the same as the specific implementation of S1202 in FIG. 12, and will not be repeated here.
  • the decoding device decodes the first subsequence according to the third decoding algorithm to obtain the hard value sequence corresponding to the first subsequence.
  • the hard value sequence includes the first hard value corresponding to the first bit and the corresponding The second hard value of the second bit.
  • the third decoding algorithm may not include soft value calculation. This means that the decoding device does not need to perform soft value calculation on the second sub-sequence, which can save the overhead caused by soft value calculation, thereby improving decoding efficiency.
  • the decoding device may determine the first bit according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the bit value of the frozen bit, and the bit value of the known bit. The hard value sequence corresponding to the two sub-sequences.
  • the decoding device can determine the second subsequence according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the bit value of the PC bit, and the bit value of the known bit The corresponding hard value sequence. If the type of the second bit includes frozen bits and PC bits, the decoding device can be based on the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the bit value of the PC bit, the bit value of the frozen bit, and the known bit Determine the hard value sequence corresponding to the second sub-sequence.
  • the third decoding algorithm includes soft value calculation. It means that the decoding device needs to perform soft value calculation and hard value calculation on the second sub-sequence. Specifically, if the type of the second bit only includes information bits, the decoding device can be based on the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, and the known For the bit value of the bit, the hard value sequence corresponding to the second subsequence is determined by the maximum likelihood estimation algorithm.
  • the decoding device can be based on the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, and the known bit
  • the bit value of and the bit value of the frozen bit are determined by the maximum likelihood estimation algorithm to determine the hard value sequence corresponding to the second sub-sequence.
  • the decoding device can distribute the sequence according to the position corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, and the known bit
  • the bit value of and the bit value of the PC bit are used to determine the hard value sequence corresponding to the second sub-sequence through the maximum likelihood estimation algorithm.
  • the decoding device may according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, and the soft value of each bit in the second subsequence, Knowing the bit value of the bit, the bit value of the PC bit, and the bit value of the frozen bit, the hard value sequence corresponding to the second subsequence is determined through the maximum likelihood estimation algorithm.
  • the decoding device may determine the decoding result of the second subsequence according to the hard value sequence. Specifically, if the type of the second bit includes information bits, the decoding device executes the content shown in S1305; if the type of the second bit does not include information bits, the decoding device executes the content shown in S1306.
  • the decoding device extracts the first hard value and the third hard value from the hard value sequence as the decoding result of the second subsequence, and the third hard value corresponds to the first The hard value of the information bit in the two bits.
  • the decoding device can map the type of the first bit to the information bit to obtain the mapped position distribution sequence, and based on the mapped position distribution sequence, extract the first hard value and the third hard value from the hard value sequence as the first The decoding result of the two subsequences.
  • the decoding device extracts the first hard value from the hard value sequence as the decoding result of the second subsequence.
  • the decoding device can map the type of the first bit to the information bit to obtain the mapped position distribution sequence, and based on the mapped position distribution sequence, extract the first hard value from the hard value sequence as the translation of the second subsequence. Code result.
  • the second subsequence includes the first bit and the second bit
  • the type of the first bit is a known bit
  • the value range of the first bit is consistent with the value range of the frozen bit
  • the first bit is the same as the frozen bit.
  • the type of two bits includes at least one of PC bits, frozen bits, or information bits.
  • the decoding device may use the type of the first bit as a frozen bit, decode the first bit based on the decoding algorithm corresponding to the frozen bit, and decode the second bit based on the decoding algorithm corresponding to the second bit type , So as to realize the decoding of the sub-sequence including the known bits.
  • the type of the second bit does not include information bits
  • the decoding device does not need to perform soft value calculation on the second sub-sequence, thereby saving overhead caused by performing soft value calculation and improving decoding efficiency.
  • FIG. 14 is a flowchart of another polarization code decoding method provided by an embodiment of the application.
  • the decoding device uses the type of the first bit as the target type, decodes the first bit based on the decoding algorithm corresponding to the target type, and decodes the second bit based on the second decoding algorithm corresponding to the second bit type.
  • the bits are decoded, so as to realize the decoding of the second sub-sequence.
  • the second subsequence includes the first bit and the second bit
  • the target type includes PC bit or frozen bit.
  • the decoding device receives a message from the encoding device, the message includes a second subsequence, and the second subsequence includes a first bit and a second bit.
  • S1401 is consistent with the specific implementation of S1201 in FIG. 12 or the specific implementation of S1301 in FIG. 13, and will not be repeated here.
  • the value range of the first bit may be consistent with the value range of the PC bit, that is, the value range is 0 or 1, or the value range of the first bit may be consistent with the value range of the frozen bit, that is, the value range Is 0.
  • the decoding device may use the type of the first bit as the target type according to the value range of the first bit, and decode the first bit based on the first decoding algorithm corresponding to the target type, and based on the second The second decoding algorithm corresponding to the bit type decodes the second bit.
  • the target type includes PC bits or frozen bits.
  • the decoding device may treat the type of the first bit as the target type; in soft value calculation, the decoding device may treat the type of the first bit as the frozen bit Perform processing; in the hard value backtracking, the decoding device can process the type of the first bit as an information bit, as shown in FIG. 10. It should be understood that, since the decoding device can process the PC bit as a frozen bit in the soft value calculation, the decoding device can also use the type of the first bit as the PC bit in the soft value calculation.
  • the decoding device can execute the content shown in S1402 and S1404; if the value range of the first bit is the same as If the value range of the frozen bit is the same, the target type is a frozen bit, and the decoding device can execute the content shown in S1403 and S1404.
  • the decoding device may use the type of the first bit as the PC bit to obtain the first position distribution sequence.
  • the value range of the first bit is consistent with the value range of the PC bit.
  • the decoding device can process the type of the first bit as the PC bit. For example, in bit type identification and hard value calculation, the decoding device can process the type of the first bit as a PC bit; in soft value calculation, the decoding device can process the type of the first bit as a frozen bit ; In the hard value backtracking, the decoding device can process the type of the first bit as an information bit, as shown in Figure 6.
  • the specific implementation process please refer to the content in S1202 in FIG. 12, which will not be repeated here.
  • the decoding device may use the type of the first bit as the frozen bit to obtain the first position distribution sequence.
  • the value range of the first bit is consistent with the value range of the frozen bit.
  • the decoding device can process the type of the first bit as the frozen bit. For example, in bit type identification and hard value calculation, the decoding device can process the type of the first bit as a frozen bit; in soft value calculation, the decoding device can process the type of the first bit as a frozen bit ; In the hard value backtracking, the decoding device can treat the type of the first bit as an information bit, as shown in Figure 8. For the specific implementation process, please refer to the content in S1302 in FIG. 13, which will not be repeated here.
  • the decoding device determines a third decoding algorithm according to the first position distribution sequence, and the third decoding algorithm includes the first decoding algorithm and the second decoding algorithm.
  • S1404 is consistent with the specific implementation process shown in S1203 in FIG. 12, or is consistent with the specific implementation process shown in S1303 in FIG. 13, and will not be repeated here.
  • the decoding device decodes the second sub-sequence according to the third decoding algorithm to obtain the hard value sequence corresponding to the second sub-sequence.
  • the hard value sequence includes the first hard value corresponding to the first bit and the corresponding The second hard value of the second bit.
  • the third decoding algorithm may not include soft value calculation. This means that the decoding device does not need to perform soft value calculation on the second sub-sequence, which can save the overhead caused by soft value calculation, thereby improving decoding efficiency.
  • the decoding device may determine the first bit according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the bit value of the frozen bit, and the bit value of the known bit. The hard value sequence corresponding to the two sub-sequences.
  • the decoding device can determine the second subsequence according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the bit value of the PC bit, and the bit value of the known bit The corresponding hard value sequence. If the type of the second bit includes frozen bits and PC bits, the decoding device can be based on the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the bit value of the PC bit, the bit value of the frozen bit, and the known bit Determine the hard value sequence corresponding to the second sub-sequence.
  • the third decoding algorithm includes soft value calculation. It means that the decoding device needs to perform soft value calculation and hard value calculation on the second sub-sequence. Specifically, if the type of the second bit only includes information bits, the decoding device can be based on the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, and the known For the bit value of the bit, the hard value sequence corresponding to the second subsequence is determined by the maximum likelihood estimation algorithm.
  • the decoding device can be based on the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, and the known bit
  • the bit value of and the bit value of the frozen bit are determined by the maximum likelihood estimation algorithm to determine the hard value sequence corresponding to the second sub-sequence.
  • the decoding device can distribute the sequence according to the position corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, and the known bit
  • the bit value of and the bit value of the PC bit are used to determine the hard value sequence corresponding to the second sub-sequence through the maximum likelihood estimation algorithm.
  • the decoding device may according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, and the soft value of each bit in the second subsequence, Knowing the bit value of the bit, the bit value of the PC bit, and the bit value of the frozen bit, the hard value sequence corresponding to the second subsequence is determined through the maximum likelihood estimation algorithm.
  • the decoding device may determine the decoding result of the second subsequence according to the hard value sequence. Specifically, if the type of the second bit includes an information bit, the decoding device executes the content shown in S1406; if the type of the second bit does not include an information bit, the decoding device executes the content shown in S1407.
  • the decoding device extracts the first hard value and the third hard value from the hard value sequence as the decoding result of the second subsequence, and the third hard value corresponds to the first hard value.
  • the decoding device can map the type of the first bit to the information bit to obtain the mapped position distribution sequence, and based on the mapped position distribution sequence, extract the first hard value and the third hard value from the hard value sequence as the first The decoding result of the two subsequences.
  • the decoding device extracts the first hard value from the hard value sequence as the decoding result of the second subsequence.
  • the decoding device can map the type of the first bit to the information bit to obtain the mapped position distribution sequence, and based on the mapped position distribution sequence, extract the first hard value from the hard value sequence as the translation of the second subsequence. Code result.
  • the second subsequence includes the first bit and the second bit
  • the type of the first bit is a known bit
  • the type of the second bit includes at least one of PC bit, frozen bit, or information bit. kind.
  • the decoding device may use the type of the first bit as the target type, decode the first bit based on the decoding algorithm corresponding to the target type, and decode the second bit based on the decoding algorithm corresponding to the type of the second bit , So as to realize the decoding of the sub-sequence including the known bits.
  • the type of the second bit does not include information bits
  • the decoding device does not need to perform soft value calculation on the second sub-sequence, thereby saving overhead caused by performing soft value calculation and improving decoding efficiency.
  • FIG. 15 is a flowchart of another polarization code decoding method provided by an embodiment of the application.
  • the decoding device can decode the first bit according to the decoding algorithm corresponding to the known bit, and decode the second bit corresponding to the type of the second bit, so as to realize the translation of the second subsequence. code.
  • the second subsequence includes the first bit and the second bit.
  • the decoding device receives a message from the encoding device, the message includes a second subsequence, and the second subsequence includes a first bit and a second bit.
  • the value range of the first bit may be consistent with the value range of the PC bit, or may be consistent with the value range of the frozen bit, which is not limited in the embodiment of the present application.
  • the specific implementation of S1501 is consistent with the specific implementation of S1201 in FIG. 12, or the specific implementation of S1301 in FIG. 13, or the specific implementation of S1401 in FIG. 14, and will not be repeated here.
  • the decoding device respectively decodes the first bit and the second bit in the second subsequence according to the first decoding algorithm corresponding to the known bit and the second decoding algorithm corresponding to the second bit type to obtain the A hard value sequence corresponding to the second sub-sequence, the hard value sequence including a first hard value corresponding to the first bit and a second hard value corresponding to the second bit.
  • the first decoding algorithm can be used to decode the first bit in the second subsequence
  • the second decoding algorithm can be used to decode the second bit in the second subsequence.
  • the third decoding algorithm can be used to decode the second subsequence to obtain the hard value sequence corresponding to the second subsequence.
  • the third decoding algorithm may include soft value calculation and hard value calculation, or include hard value calculation.
  • the third decoding algorithm may also include a first decoding algorithm and a second decoding algorithm, that is to say, the third decoding algorithm can realize all the functions of the first decoding algorithm and realize the second decoding algorithm. All functions of the code algorithm.
  • the third decoding algorithm may not include soft value calculation. This means that the decoding device does not need to perform soft value calculation on the second sub-sequence, which can save the overhead caused by soft value calculation, thereby improving decoding efficiency.
  • the decoding device may determine the first bit according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the bit value of the frozen bit, and the bit value of the known bit. The hard value sequence corresponding to the two sub-sequences.
  • the decoding device can determine the second subsequence according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the bit value of the PC bit, and the bit value of the known bit The corresponding hard value sequence. If the type of the second bit includes frozen bits and PC bits, the decoding device can be based on the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the bit value of the PC bit, the bit value of the frozen bit, and the known bit Determine the hard value sequence corresponding to the second sub-sequence.
  • the decoding device can obtain the hard values of the bits in the second subsequence as [0 0 0 0] according to the first position distribution sequence, the decoding algorithm corresponding to the PC bit and the decoding algorithm corresponding to the frozen bit.
  • the decoding device can determine that bit 1 and bit 2 are known bits according to the position distribution sequence corresponding to the second subsequence, and The bit value of bit 1 is 0, and the bit value of bit 2 is 1. Combining with the hard value obtained according to the decoding algorithm corresponding to the frozen bit, it can be determined that the hard value sequence corresponding to the second subsequence is [0 0 1 0].
  • the third decoding algorithm includes soft value calculation. It means that the decoding device needs to perform soft value calculation and hard value calculation on the second sub-sequence. Specifically, if the type of the second bit only includes information bits, the decoding device can be based on the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, and the known For the bit value of the bit, the hard value sequence corresponding to the second subsequence is determined by the maximum likelihood estimation algorithm.
  • the decoding device can be based on the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, and the known bit
  • the bit value of and the bit value of the frozen bit are determined by the maximum likelihood estimation algorithm to determine the hard value sequence corresponding to the second sub-sequence.
  • the decoding device can distribute the sequence according to the position corresponding to the second subsequence, the first position distribution sequence, the soft value of each bit in the second subsequence, and the known bit
  • the bit value of and the bit value of the PC bit are used to determine the hard value sequence corresponding to the second sub-sequence through the maximum likelihood estimation algorithm.
  • the decoding device may according to the position distribution sequence corresponding to the second subsequence, the first position distribution sequence, and the soft value of each bit in the second subsequence, Knowing the bit value of the bit, the bit value of the PC bit, and the bit value of the frozen bit, the hard value sequence corresponding to the second subsequence is determined through the maximum likelihood estimation algorithm.
  • the decoding device may determine the decoding result of the second subsequence according to the hard value sequence. Specifically, if the type of the second bit includes information bits, the decoding device executes the content shown in S1205; if the type of the second bit does not include information bits, the decoding device executes the content shown in S1206.
  • the decoding device extracts the first hard value and the third hard value from the hard value sequence as the decoding result of the second sub-sequence, and the third hard value corresponds to the first hard value.
  • the decoding device may extract the first hard value of all known bits and the third hard value of all information bits from the hard value sequence according to the position distribution sequence corresponding to the second subsequence, as the decoding result of the second subsequence .
  • the decoding device extracts the first hard value from the hard value sequence as the decoding result of the second subsequence.
  • the decoding device may extract the first hard value of all known bits from the hard value sequence according to the position distribution sequence corresponding to the second subsequence as the decoding result of the second subsequence.
  • the second subsequence includes the first bit and the second bit
  • the type of the first bit is a known bit.
  • the decoding device can decode the first bit according to the decoding algorithm corresponding to the known bit, and decode the second bit according to the second decoding algorithm corresponding to the type of the second bit, so as to realize the Decoding of subsequences of bits.
  • the type of the second bit does not include information bits, there is no need to perform soft value calculations, which can reduce overhead and improve decoding efficiency.
  • FIG. 16 is a schematic structural diagram of a decoding device provided by an embodiment of the application, and the decoding device can be used to implement the process shown in FIG. 11 or FIG. 15.
  • the decoding device 1600 may be applied to the communication system 100 shown in FIG. 1A or FIG. 1B.
  • the decoding device 1600 may be the network device 101 or at least one chip in the network device 101, and may also be the terminal 102 or at least one chip in the terminal 102.
  • the decoding device 1600 includes a lighting calculation unit 1601, a path splitting unit 1602, a path calculation unit 1603, and a likelihood probability calculation unit 1604.
  • the lighting calculation unit 1601 is configured to perform lighting calculations on the lighting sequence, and send the lighting calculation results to the likelihood probability calculation unit 1604.
  • the lighting sequence refers to a sub-sequence including known bits, such as the first sub-sequence in FIG. 11 or the second sub-sequence in FIG. 15.
  • Lighting calculation refers to decoding the first bit according to the decoding algorithm corresponding to the known bit.
  • the lighting calculation unit 1601 can execute the content shown in S1102 in FIG. 11 or part of the content shown in S1502 in FIG. 15.
  • the path splitting unit 1602 is used to determine the bit values of all the information bits in the subsequence according to the decoding algorithm corresponding to the combination of the bit types in the subsequence, and send the bit values of all the information bits in the subsequence to the path
  • the subsequence includes N bits, and N is an integer greater than or equal to 1.
  • the N bits can split up to 2 N decoding results.
  • the path splitting unit 1602 can determine the 2 N decoding results and the 2 N decoding results according to the decoding algorithm corresponding to the combination of different bit types. According to the reliability of the 2 N decoding results, one or more of the decoding results with good reliability are retained, and then all of the N bits are determined according to the one or more decoding results.
  • the bit value of the information bit is used to determine the bit values of all the information bits in the subsequence according to the decoding algorithm corresponding to the combination of the bit types in the subsequence
  • the path calculation unit 1603 is used to determine the path branch metric of N bits and the path branch metric used to decode the next subsequence according to the path metric of the previous subsequence and the bit values of all information bits in the subsequence .
  • the bit value of the information bit obtained by traversal by the path splitting unit 1602 may deviate from its corresponding maximum likelihood probability. For example, the traversal result is 0, but the sign of the maximum likelihood probability is negative. In this case, the path calculation unit 1603 will accumulate the absolute value of the maximum likelihood probability of the information bits with deviations in the N bits to obtain the current path branch metric of N bits, and accumulate the path branch metric of multiple decodings.
  • the accumulated path metrics of different paths are sorted, and the path metrics of one or more paths with the best (for example, the smallest path metric value) are retained for decoding the next subsequence.
  • the path branch metric and the path metric are used to express the reliability of the decoding result. The larger the value, the less reliable the decoding result.
  • the likelihood probability calculation unit 1604 is used to determine the bit value of each of the N bits.
  • the bit value of the known bit is obtained by the lighting calculation unit 1601, and the bit value of the information bit is obtained by the path splitting calculation unit 1602, the path calculation unit 1603, and the likelihood calculation unit 1604.
  • the bit value of the frozen bit is fixed to 0, and the bit value of the PC bit is The bit value is obtained by accumulating the bit value displacement of the information bit in the previous subsequence.
  • the bit value of each bit in the N bits can also be used to determine the bit value of the PC bit in the next subsequence.
  • one or more of the path splitting unit 1602, the path calculation unit 1603, or the likelihood calculation unit 1604 is used to execute the processes shown in S1102 to S1103 or execute the processes shown in S1502 to S1504. For example, if the type of the second bit includes information bits, the path splitting unit 1602, the path calculation unit 1603, and the likelihood calculation unit 1604 are used to execute the process shown in S1502. If the type of the second bit does not include information bits, the likelihood calculation unit 1604 is configured to execute the process shown in S1102.
  • the subsequence is [bit 0 bit 1 bit 2 bit 3], and the position distribution sequence corresponding to the sub sequence is [000 001 001 100].
  • 000, 110, and 111 represent frozen bits
  • 001 and 010 represent information bits
  • 011 represents PC bits
  • 100 represents a known bit with a value of
  • 101 represents a known bit with a value of 1.
  • the maximum likelihood probability of 4 bits is a, b, c, d (b and c are both positive numbers).
  • the types of the 4 bits are frozen bits, information bits, information bits, and known bits in order.
  • the lighting calculation unit 1601 determines that the value of bit 3 is 0, and the likelihood probability calculation unit 1604 determines that the value of bit 0 is 0.
  • the path splitting unit 1602 traverses the values of the two information bits, bit 1 and bit 2, to obtain four decoding results of the 2 bits, and the four decoding results are 0000, 0010, 0100, and 0110 in sequence.
  • the path calculation unit 1603 compares these four decoding results with the maximum likelihood probabilities b, c to obtain the 4-bit path branch metrics of 0, c, b, and b+c, respectively. It can be seen that the decoding reliability is ranked as 0000>0010>0100>0110.
  • the best path obtained by the likelihood calculation unit 1604 is 0000, and according to the path, it can be determined that the value of bit 1 is 0, and the value of bit 2 is 0.
  • the path calculation unit 1603 reserves the best one (for example, the path whose decoding result is 0000) or multiple paths for decoding of the next subsequence.
  • a communication device 1700 provided by an embodiment of this application is used to implement the function of the decoding device in the foregoing method.
  • the communication device 1700 includes a receiver 1701 and a decoder 1702.
  • the communication device 1700 can implement the methods described in the foregoing Embodiment 1 to Embodiment 8.
  • the receiver 1701 is configured to receive a message from an encoding device, the message includes a subsequence to be decoded, the subsequence includes a first bit, and the type of the first bit is a known bit;
  • the decoder 1702 is configured to use the type of the first bit as the target type and decode the first bit according to the first decoding algorithm corresponding to the target type.
  • the target type includes parity bits or frozen bits.
  • the sub-sequence further includes a second bit
  • the type of the second bit includes at least one of a frozen bit, a parity bit, or an information bit
  • the decoder 1702 is further configured to: correspond to the type of the second bit The second decoding algorithm decodes the second bit.
  • the message is an uplink control message or a downlink control message.
  • the uplink control message includes a first field and a second field, the first field is used to indicate whether the first bit is included in the subsequence, and the second field is used to indicate the position of the first bit in the subsequence.
  • the downlink control message includes a third field and a fourth field, the third field is used to indicate whether the first bit is included in the subsequence, and the fourth field is used to indicate the position of the first bit in the subsequence.
  • the decoder 1702 is specifically configured to: when the value range of the first bit is consistent with the value range of the parity bit, use the type of the first bit as the parity bit; or, in the first bit When the value range of one bit is consistent with the value range of the frozen bit, the type of the first bit is taken as the frozen bit.
  • the decoder 1702 is specifically configured to: map the type of the first bit to the target type to obtain a position distribution sequence, which is used to characterize the type of each bit in the subsequence; respectively, according to the position distribution sequence Determine the first decoding algorithm and the second decoding algorithm; decode the subsequence according to the third decoding algorithm, the third decoding algorithm including the first decoding algorithm and the second decoding algorithm.
  • the third decoding algorithm does not include soft value calculation, which is used to determine the likelihood that the bit value of each bit in the subsequence is 0 or 1. .
  • the third decoding algorithm includes soft value calculation, which is used to determine the likelihood that the bit value of each bit in the subsequence is 0 or 1.
  • the decoder 1702 is further configured to: decode the sub-sequence according to the third decoding algorithm to obtain a hard-valued sequence, and the hard-valued sequence includes a sequence corresponding to The first hard value of the first bit and the second hard value corresponding to the second bit; the first hard value is extracted from the hard value sequence as the decoding result.
  • the decoder 1702 is further configured to: decode the sub-sequence according to the third decoding algorithm to obtain a hard-valued sequence, and the hard-valued sequence includes a sequence corresponding to the first The first hard value of one bit, and the second hard value corresponding to the second bit; the first hard value and the third hard value are extracted from the hard value sequence as the decoding result, and the third hard value corresponds to the second bit The hard value of the information bits in.
  • a communication device 1800 provided in an embodiment of this application is used to implement the function of the encoding device in the foregoing method.
  • the communication device 1800 includes an encoder 1801 and a transmitter 1802.
  • the communication device 1800 can implement the method described in FIG. 4 in the foregoing embodiment.
  • the encoder 1801 is configured to obtain the first bit and the second bit respectively, the type of the first bit is a known bit, and the type of the second bit includes at least one of a frozen bit, a parity bit, or an information bit A; generate a pilot sequence based on the first bit; encode the second bit to obtain the first code sequence; the transmitter 1802 is used to send the second code sequence to the decoding device when determining to send the pilot sequence, the second The coding sequence includes the pilot sequence and the first coding sequence.
  • the second coding sequence is the first coding sequence.
  • the second coding sequence is an uplink control message or a downlink control message.
  • the uplink control message includes a first field and a second field, the first field is used to indicate whether the first bit is included in the subsequence, and the second field is used to indicate the position of the first bit in the subsequence.
  • the downlink control message includes a third field and a fourth field, the third field is used to indicate whether the first bit is included in the subsequence, and the fourth field is used to indicate the position of the first bit in the subsequence.
  • the encoder 1801 is further configured to: when the air interface resources are sufficient, determine to send the pilot sequence; or, when the air interface resources are in short supply, determine not to send the pilot sequence.
  • An embodiment of the present application also provides a communication device 1900, and the communication device 1900 may be used to execute the method described in the above-mentioned communication device 1700.
  • the communication device 1900 includes: an input interface circuit 1901 for implementing the functions implemented by the receiver 1701; and a logic circuit 1902 for implementing the functions implemented by the decoder 1702.
  • the communication device may be a chip or an integrated circuit during specific implementation.
  • An embodiment of the present application also provides a communication device 2000, and the communication device 2000 may be used to execute the method described by the above-mentioned communication device 1800.
  • the communication device 2000 includes: a logic circuit 2001 for realizing the functions realized by the encoder 1801; and an output interface circuit 2002 for realizing the functions realized by the transmitter 1802.
  • the communication device may be a chip or an integrated circuit during specific implementation.
  • Figure 21 shows the communication device provided by the embodiment of the application.
  • the device can be a network device or a device in a network device (for example, a chip or a chip system or a chip set or a part of a chip used to perform related method functions). ).
  • the device may be a terminal, or a device in the terminal (for example, a chip or a chip system or a chip set or a part of a chip for performing related method functions).
  • the device may be a chip system.
  • the chip system may be composed of chips, or may include chips and other discrete devices.
  • the device 2100 includes at least one processor 2120, configured to implement the functions of the encoding device or the decoding device in the method provided in the embodiment of the present application.
  • the apparatus 2100 may further include a communication interface 2110.
  • the communication interface 2110 may be a transceiver, a circuit, a bus, a module, or other types of communication interfaces for communicating with other devices through a transmission medium.
  • the communication interface 2110 is used for the device in the device 2100 to communicate with other devices.
  • the other device may be a decoding device.
  • the processor 2120 uses the communication interface 2110 to send and receive data, and is used to implement the method implemented by the encoding device or the decoding device in the foregoing method embodiment.
  • the device 2100 may also include at least one memory 2130 for storing program instructions and/or data.
  • the memory 2130 and the processor 2120 are coupled.
  • the coupling in the embodiments of the present application is an indirect coupling or communication connection between devices, units or modules, and may be in electrical, mechanical or other forms, and is used for information exchange between devices, units or modules.
  • the processor 2120 may cooperate with the memory 2130 to operate.
  • the processor 2120 may execute program instructions stored in the memory 2130. At least one of the at least one memory may be included in the processor.
  • connection medium between the aforementioned communication interface 2110, the processor 2120, and the memory 2130 is not limited in the embodiment of the present application.
  • the memory 2130, the processor 2120, and the communication interface 2110 are connected by a bus 2140.
  • the bus is represented by a thick line in FIG. 21.
  • the connection mode between other components is only for schematic illustration. , Is not limited.
  • the bus can be divided into an address bus, a data bus, a control bus, and so on. For ease of representation, only one thick line is used in FIG. 21 to represent it, but it does not mean that there is only one bus or one type of bus.
  • the processor may be a general-purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, and may implement or Perform the methods, steps, and logic block diagrams disclosed in the embodiments of the present application.
  • the general-purpose processor may be a microprocessor or any conventional processor or the like.
  • the steps of the method disclosed in combination with the embodiments of the present application may be directly embodied as being executed and completed by a hardware processor, or executed and completed by a combination of hardware and software modules in the processor.
  • the memory may be a non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), etc., or a volatile memory (volatile memory), for example Random-access memory (RAM).
  • the memory is any other medium that can be used to carry or store desired program codes in the form of instructions or data structures and that can be accessed by a computer, but is not limited thereto.
  • the memory in the embodiment of the present application may also be a circuit or any other device capable of realizing a storage function for storing program instructions and/or data.
  • this application can be provided as methods, systems, or computer program products. Therefore, this application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, this application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing equipment to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction device.
  • the device implements the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.
  • These computer program instructions can also be loaded on a computer or other programmable data processing equipment, so that a series of operation steps are executed on the computer or other programmable equipment to produce computer-implemented processing, so as to execute on the computer or other programmable equipment.
  • the instructions provide steps for implementing the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.

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Abstract

本申请提供一种极化码的编译码方法及装置，该方法包括：接收来自编码装置的消息，消息中包括待译码的子序列，子序列包括第一比特，第一比特的类型为已知比特；将第一比特的类型作为目标类型，并根据目标类型对应的第一译码算法对第一比特进行译码，目标类型包括奇偶校验比特或冻结比特。由于将第一比特的类型映射为目标类型后，映射后的子序列中不包括已知比特，因此可以实现对包括已知比特的子序列的译码。由于冻结比特或PC比特的比特值与软值无关，因此在根据目标类型对应的译码算法对子序列进行译码时，可以无需对子序列进行软值计算，从而在保证已知比特带来的收益的情况下，节省了因进行软值计算产生的开销，提高了译码效率。

Description

一种极化码的编译码方法及装置 技术领域
本申请涉及通信技术领域，尤其涉及一种极化码(polar code)的编译码方法及装置。
背景技术
通信系统通常采用信道编码提高数据传输的可靠性，保证通信的质量。例如可以采用极化码、里德-穆勒(reed-muler，RM)码等编码方法。其中，极化码是一种可以渐进达到信道容量的编码方法，在广泛的工作区间(如码长、码率或信噪比等)都具有极佳的译码性能。
目前的极化码译码方案中，译码装置将待译码序列中所包括的比特分为如下三个类型：信息比特(information bits)、冻结比特(frozen bits)以及奇偶校验(parity check，PC)比特。其中，信息比特用于承载信息，冻结比特是指固定填充的比特，PC比特用于校验。译码装置可以基于比特的类型进行快速译码，译码过程包括：先对待译码序列进行划分得到多个待译码的子序列；根据该多个待译码的子序列中每个子序列的比特的类型的组合方式，确定每个子序列对应的译码算法；然后根据每个子序列对应的译码算法对该多个子序列进行并行译码，从而提高译码效率，实现快速译码。
目前的极化码编码方案中，编码装置使用一些比特值为已知的比特进行冗余填充，然后将这些比特与其他类型的比特联合编码后发送给译码装置，其中这些比特的类型可以称为已知比特(known bits)。编码装置可以将已知比特映射到译码顺序的起始位置，这样译码装置可以根据起始位置处已知比特的译码结果以及该已知比特的比特值，确定该已知比特的译码可靠性，并根据该已知比特的译码可靠性保留至少一条路径，可以提高译码可靠性。
由于译码算法适配的比特的类型仅包括信息比特、冻结比特或PC比特中的至少一种，因此当子序列中的比特的类型包括已知比特时，译码装置不能确定出该子序列对应的译码算法。现有技术中，译码装置可以将已知比特作为信息比特进行译码，而在诸如串行抵消(successive cancelation，SC)，串行抵消列表(successive cancelation list，SCL)等Polar码译码方法中，信息比特对应的译码过程复杂，算法开销较大，从而降低了译码效率。因此，如何在保证已知比特带来的收益的情况下降低开销，提高译码效率，是亟需解决的问题。
发明内容
本申请实施例提供一种极化码的编译码方法及装置，用以对包括已知比特的子序列进行译码，在保证已知比特带来的收益的情况下，降低开销，提高译码效率。
第一方面，提供一种极化码的译码方法，该方法包括：接收来自编码装置的消息，消息中包括待译码的子序列，子序列包括第一比特，第一比特的类型为已知比特；将第一比特的类型作为目标类型，并根据目标类型对应的第一译码算法对第一比特进行译码，目标 类型包括奇偶校验比特或冻结比特。
上述第一方面提供的方法可由译码装置或能够支持译码装置实现该方法所需的功能的装置执行，该装置例如芯片系统等。
本申请的上述实施例中，子序列中包括第一比特，第一比特的类型为已知比特。将第一比特的类型作为目标类型，并根据该目标类型对应的第一译码算法对第一比特进行译码，该目标类型为PC比特或冻结比特。由于将第一比特的类型映射为目标类型后，映射后的子序列中不包括已知比特，因此可以实现对包括已知比特的子序列的译码。由于冻结比特或PC比特的比特值与软值无关，因此在根据目标类型对应的译码算法对子序列进行译码时，无需对子序列进行软值计算，从而在保证已知比特带来的收益的情况下，节省了因进行软值计算产生的开销，提高了译码效率。
在一种可能的设计中，子序列还包括第二比特，第二比特的类型包括冻结比特、奇偶校验比特或信息比特中的至少一种，该方法还包括：根据第二比特的类型对应的第二译码算法对第二比特进行译码。通过该方法，将第一比特的类型作为目标类型，并基于该目标类型对应的译码算法对第一比特进行译码，在子序列还包括第二比特时，根据第二比特的类型对应的第二译码算法对该第二比特进行译码，从而实现对包括已知比特的子序列进行译码。
在一种可能的设计中，消息为上行控制消息，或下行控制消息。
在一种可能的设计中，上行控制消息中包括第一字段和第二字段，第一字段用于指示子序列中是否包括第一比特，第二字段用于指示第一比特在子序列中的位置。通过该方法，可以确定在子序列中是否包括第一比特，以及在包括第一比特的情况下，该第一比特在子序列中的位置。
在一种可能的设计中，下行控制消息中包括第三字段和第四字段，第三字段用于指示子序列中是否包括第一比特，第四字段用于指示第一比特在子序列中的位置。通过该方法，可以确定在子序列中是否包括第一比特，以及在包括第一比特的情况下，该第一比特在子序列中的位置。
在一种可能的设计中，将第一比特的类型作为目标类型，包括：在第一比特的取值范围与奇偶校验比特的取值范围一致时，将第一比特的类型作为奇偶校验比特；或者，在第一比特的取值范围与冻结比特的取值范围一致时，将第一比特的类型作为冻结比特。
在一种可能的设计中，将第一比特的类型作为目标类型，包括：将第一比特的类型映射为目标类型，得到位置分布序列，位置分布序列用于表征子序列中各个比特的类型；根据目标类型对应的第一译码算法对第一比特进行译码，以及根据第二比特的类型对应的第二译码算法对第二比特进行译码，包括：根据位置分布序列，分别确定第一译码算法和第二译码算法；根据第三译码算法对子序列进行译码，第三译码算法包括第一译码算法和第二译码算法。通过该方法，将第一比特的类型映射为目标类型后，得到位置分布序列。由于该位置分布序列所指示的比特的类型不包括已知比特，因此可以基于该位置分布序列适配译码算法，从而实现对包括已知比特的子序列的译码。
在一种可能的设计中，在第二比特的类型中不包括信息比特时，第三译码算法不包括软值计算，软值计算用于确定子序列中各个比特的比特值为0或1的似然概率。通过该方法，由于PC比特的比特值以及冻结比特的比特值与软值计算无关，因此当第二比特的类型不包括信息比特时，无需进行软值计算，从而可以节省因软值计算带来的开销，提高译 码效率。
在一种可能的设计中，在第二比特的类型中包括信息比特时，第三译码算法包括软值计算，软值计算用于确定子序列中各个比特的比特值为0或1的似然概率。通过该方法，当第二比特的类型包括信息比特时，通过软值计算对子序列进行译码，可以实现对包括已知比特的子序列的译码。
在一种可能的设计中，在第二比特的类型中不包括信息比特时，该方法还包括：根据第三译码算法对子序列进行译码，得到硬值序列，硬值序列包括对应于第一比特的第一硬值，以及对应于第二比特的第二硬值；从硬值序列中抽取第一硬值作为译码结果。通过该方法，在硬值回溯中将已知比特作为信息比特进行处理，在第二比特的类型不包括信息比特时，可以从硬值序列中抽取该已知比特的比特值作为译码结果。
在一种可能的设计中，在第二比特的类型中包括信息比特时，该方法还包括：根据第三译码算法对子序列进行译码，得到硬值序列，硬值序列包括对应于第一比特的第一硬值，以及对应于第二比特的第二硬值；从硬值序列中抽取第一硬值和第三硬值作为译码结果，第三硬值为对应于第二比特中的信息比特的硬值。通过该方法，在硬值回溯中将已知比特作为信息比特进行处理，在第二比特的类型不包括信息比特时，可以从硬值序列中抽取该已知比特的比特值作为译码结果。
第二方面，提供一种极化码的译码方法，该方法包括：接收来自编码装置的消息，消息中包括待译码的子序列，子序列包括第一比特，第一比特的类型为已知比特；将第一比特的类型作为PC比特，并根据PC比特对应的第一译码算法对第一比特进行译码，目标类型包括奇偶校验比特或冻结比特。
上述第二方面提供的方法可由译码装置或能够支持译码装置实现该方法所需的功能的装置执行，该装置例如芯片系统等。
本申请的上述实施例中，子序列中包括第一比特，第一比特的类型为已知比特。将第一比特的类型作为PC比特，并根据该PC比特对应的第一译码算法对第一比特进行译码。由于将第一比特的类型映射为目标类型后，映射后的子序列中不包括已知比特，因此可以实现对包括已知比特的子序列的译码。由于PC比特的比特值与软值无关，因此在根据PC比特对应的译码算法对子序列进行译码时，无需对子序列进行软值计算，从而在保证已知比特带来的收益的情况下，节省了因进行软值计算产生的开销，提高了译码效率。
在一种可能的设计中，子序列还包括第二比特，第二比特的类型包括冻结比特、奇偶校验比特或信息比特中的至少一种，方法还包括：根据第二比特的类型对应的第二译码算法对第二比特进行译码。
在一种可能的设计中，消息为上行控制消息，或下行控制消息。
在一种可能的设计中，上行控制消息中包括第一字段和第二字段，第一字段用于指示子序列中是否包括第一比特，第二字段用于指示第一比特在子序列中的位置。
在一种可能的设计中，下行控制消息中包括第三字段和第四字段，第三字段用于指示子序列中是否包括第一比特，第四字段用于指示第一比特在子序列中的位置。
在一种可能的设计中，将第一比特的类型作为PC比特，包括：将第一比特的类型映射为PC比特，得到位置分布序列，位置分布序列用于表征子序列中各个比特的类型；根据PC比特对应的第一译码算法对第一比特进行译码，以及根据第二比特的类型对应的第 二译码算法对第二比特进行译码，包括：根据位置分布序列，分别确定第一译码算法和第二译码算法；根据第三译码算法对子序列进行译码，第三译码算法包括第一译码算法和第二译码算法。
在一种可能的设计中，在第二比特的类型中不包括信息比特时，第三译码算法不包括软值计算，软值计算用于确定子序列中各个比特的比特值为0或1的似然概率。
在一种可能的设计中，在第二比特的类型中包括信息比特时，第三译码算法包括软值计算，软值计算用于确定子序列中各个比特的比特值为0或1的似然概率。
在一种可能的设计中，在第二比特的类型中不包括信息比特时，该方法还包括：根据第三译码算法对子序列进行译码，得到硬值序列，硬值序列包括对应于第一比特的第一硬值，以及对应于第二比特的第二硬值；从硬值序列中抽取第一硬值作为译码结果。
在一种可能的设计中，在第二比特的类型中包括信息比特时，该方法还包括：根据第三译码算法对子序列进行译码，得到硬值序列，硬值序列包括对应于第一比特的第一硬值，以及对应于第二比特的第二硬值；从硬值序列中抽取第一硬值和第三硬值作为译码结果，第三硬值为对应于第二比特中的信息比特的硬值。
第三方面，提供一种极化码的译码方法，该方法包括：接收来自编码装置的消息，消息中包括待译码的子序列，子序列包括第一比特，第一比特的类型为已知比特；将第一比特的类型作为冻结比特，并根据冻结比特对应的第一译码算法对第一比特进行译码，目标类型包括奇偶校验比特或冻结比特。
上述第三方面提供的方法可由译码装置或能够支持译码装置实现该方法所需的功能的装置执行，该装置例如芯片系统等。
本申请的上述实施例中，子序列中包括第一比特，第一比特的类型为已知比特。将第一比特的类型作为冻结比特，并根据该冻结比特对应的第一译码算法对第一比特进行译码。由于将第一比特的类型映射为目标类型后，映射后的子序列中不包括已知比特，因此可以实现对包括已知比特的子序列的译码。由于冻结比特的比特值与软值无关，因此在根据冻结比特对应的译码算法对子序列进行译码时，无需对子序列进行软值计算，从而在保证已知比特带来的收益的情况下，节省了因进行软值计算产生的开销，提高了译码效率。
在一种可能的设计中，子序列还包括第二比特，第二比特的类型包括冻结比特、奇偶校验比特或信息比特中的至少一种，该方法还包括：根据第二比特的类型对应的第二译码算法对第二比特进行译码。
在一种可能的设计中，消息为上行控制消息，或下行控制消息。
在一种可能的设计中，上行控制消息中包括第一字段和第二字段，第一字段用于指示子序列中是否包括第一比特，第二字段用于指示第一比特在子序列中的位置。
在一种可能的设计中，下行控制消息中包括第三字段和第四字段，第三字段用于指示子序列中是否包括第一比特，第四字段用于指示第一比特在子序列中的位置。
在一种可能的设计中，将第一比特的类型作为冻结比特，包括：将第一比特的类型映射为冻结比特，得到位置分布序列，位置分布序列用于表征子序列中各个比特的类型；根据冻结比特对应的第一译码算法对第一比特进行译码，以及根据第二比特的类型对应的第二译码算法对第二比特进行译码，包括：根据位置分布序列，分别确定第一译码算法和第二译码算法；根据第三译码算法对子序列进行译码，第三译码算法包括第一译码算法和第二译码算法。
在一种可能的设计中，在第二比特的类型中不包括信息比特时，第三译码算法不包括软值计算，软值计算用于确定子序列中各个比特的比特值为0或1的似然概率。
在一种可能的设计中，在第二比特的类型中包括信息比特时，第三译码算法包括软值计算，软值计算用于确定子序列中各个比特的比特值为0或1的似然概率。
在一种可能的设计中，在第二比特的类型中不包括信息比特时，该方法还包括：根据第三译码算法对子序列进行译码，得到硬值序列，硬值序列包括对应于第一比特的第一硬值，以及对应于第二比特的第二硬值；从硬值序列中抽取第一硬值作为译码结果。
在一种可能的设计中，在第二比特的类型中包括信息比特时，该方法还包括：根据第三译码算法对子序列进行译码，得到硬值序列，硬值序列包括对应于第一比特的第一硬值，以及对应于第二比特的第二硬值；从硬值序列中抽取第一硬值和第三硬值作为译码结果，第三硬值为对应于第二比特中的信息比特的硬值。
第四方面，提供一种极化码的译码方法，该方法包括：接收来自编码装置的消息，消息中包括待译码的子序列，子序列包括第一比特，第一比特的类型为已知比特；根据第一比特的类型对应的第一译码算法对第一比特进行译码。
上述第四方面提供的方法可由译码装置或能够支持译码装置实现该方法所需的功能的装置执行，该装置例如芯片系统等。
本申请的上述实施例中，子序列中包括第一比特，第一比特的类型为已知比特。将第一比特的类型对应的第一译码算法对第一比特进行译码，可以实现对包括已知比特的子序列的译码。
在一种可能的设计中，子序列还包括第二比特，第二比特的类型包括冻结比特、奇偶校验比特或信息比特中的至少一种，该方法还包括：根据第二比特的类型对应的第二译码算法对第二比特进行译码。
在一种可能的设计中，消息为上行控制消息，或下行控制消息。
在一种可能的设计中，上行控制消息中包括第一字段和第二字段，第一字段用于指示子序列中是否包括第一比特，第二字段用于指示第一比特在子序列中的位置。
在一种可能的设计中，下行控制消息中包括第三字段和第四字段，第三字段用于指示子序列中是否包括第一比特，第四字段用于指示第一比特在子序列中的位置。
在一种可能的设计中，根据第一比特的类型对应的第一译码算法对第一比特进行译码，以及根据第二比特的类型对应的第二译码算法对第二比特进行译码，包括：根据子序列对应的位置分布序列，分别确定第一译码算法和第二译码算法；根据第三译码算法对子序列进行译码，第三译码算法包括第一译码算法和第二译码算法。
在一种可能的设计中，在第二比特的类型中不包括信息比特时，第三译码算法不包括软值计算，软值计算用于确定子序列中各个比特的比特值为0或1的似然概率。
在一种可能的设计中，在第二比特的类型中包括信息比特时，第三译码算法包括软值计算，软值计算用于确定子序列中各个比特的比特值为0或1的似然概率。
在一种可能的设计中，在第二比特的类型中不包括信息比特时，该方法还包括：根据第三译码算法对子序列进行译码，得到硬值序列，硬值序列包括对应于第一比特的第一硬值，以及对应于第二比特的第二硬值；从硬值序列中抽取第一硬值作为译码结果。
在一种可能的设计中，在第二比特的类型中包括信息比特时，该方法还包括：根据第三译码算法对子序列进行译码，得到硬值序列，硬值序列包括对应于第一比特的第一硬值， 以及对应于第二比特的第二硬值；从硬值序列中抽取第一硬值和第三硬值作为译码结果，第三硬值为对应于第二比特中的信息比特的硬值。
第五方面，提供一种极化码的编码方法，该方法包括：分别获取第一比特和第二比特，第一比特的类型为已知比特，第二比特的类型包括冻结比特、奇偶校验比特或信息比特中的至少一种；基于第一比特生成导频序列；对第二比特进行编码，得到第一编码序列；在确定发送导频序列时，向译码装置第二编码序列，第二编码序列中包括导频序列和编码序列。
上述第五方面提供的方法可由编码装置或能够支持编码装置实现该方法所需的功能的装置执行，该装置例如芯片系统等。
本申请上述实施例中，分别获取第一比特和第二比特，基于该第一比特生成导频序列，该导频序列可以不被发送。从而编码装置可以根据网络资源占用情况或译码性能需求等信息，确定是否使用已知比特进行冗余填充，即是否发送该导频序列。在空口资源充足或译码性能需求高时，编码装置可以发送该导频序列，从而可以提高译码性能，满足高要求的译码性能需求。在空口资源紧张时，编码装置可以不发送该导频序列，从而可以减轻空口资源的负荷。
在一种可能的设计中，在确定不发送导频序列时，第二编码序列为第一编码序列。
在一种可能的设计中，第二编码序列为上行控制消息，或下行控制消息。
在一种可能的设计中，第二编码序列中包括至少一个子序列，针对一子序列，上行控制消息中包括第一字段和第二字段，第一字段用于指示子序列中是否包括第一比特，第二字段用于指示第一比特在子序列中的位置。
在一种可能的设计中，第二编码序列中包括至少一个子序列，针对一子序列，下行控制消息中包括第三字段和第四字段，第三字段用于指示子序列中是否包括第一比特，第四字段用于指示第一比特在子序列中的位置。
在一种可能的设计中，该方法还包括：在空口资源充足时，确定发送导频序列；或者，在空口资源紧张时，确定不发送导频序列。
第六方面，提供一种通信装置，通信装置包括接收机和译码器：
接收机，用于接收来自编码装置的消息，消息中包括待译码的子序列，子序列包括第一比特，第一比特的类型为已知比特；
译码器，用于将第一比特的类型作为目标类型，并根据目标类型对应的第一译码算法对第一比特进行译码，目标类型包括奇偶校验比特或冻结比特。
在一种可能的设计中，子序列还包括第二比特，第二比特的类型包括冻结比特、奇偶校验比特或信息比特中的至少一种，译码器，进一步用于：
根据第二比特的类型对应的第二译码算法对第二比特进行译码。
在一种可能的设计中，消息为上行控制消息，或下行控制消息。
在一种可能的设计中，上行控制消息中包括第一字段和第二字段，第一字段用于指示子序列中是否包括第一比特，第二字段用于指示第一比特在子序列中的位置。
在一种可能的设计中，下行控制消息中包括第三字段和第四字段，第三字段用于指示子序列中是否包括第一比特，第四字段用于指示第一比特在子序列中的位置。
在一种可能的设计中，该译码器，具体用于：
在第一比特的取值范围与奇偶校验比特的取值范围一致时，将第一比特的类型作为奇 偶校验比特；或者，
在第一比特的取值范围与冻结比特的取值范围一致时，将第一比特的类型作为冻结比特。
在一种可能的设计中，该译码器，具体用于：
将第一比特的类型映射为目标类型，得到位置分布序列，位置分布序列用于表征子序列中各个比特的类型；
根据位置分布序列，分别确定第一译码算法和第二译码算法；
根据第三译码算法对子序列进行译码，第三译码算法包括第一译码算法和第二译码算法。
在一种可能的设计中，在第二比特的类型中不包括信息比特时，第三译码算法不包括软值计算，软值计算用于确定子序列中各个比特的比特值为0或1的似然概率。
在一种可能的设计中，在第二比特的类型中包括信息比特时，第三译码算法包括软值计算，软值计算用于确定子序列中各个比特的比特值为0或1的似然概率。
在一种可能的设计中，在第二比特的类型中不包括信息比特时，译码器，进一步用于：
根据第三译码算法对子序列进行译码，得到硬值序列，硬值序列包括对应于第一比特的第一硬值，以及对应于第二比特的第二硬值；
从硬值序列中抽取第一硬值作为译码结果。
在一种可能的设计中，在第二比特的类型中包括信息比特时，译码器，进一步用于：
根据第三译码算法对子序列进行译码，得到硬值序列，硬值序列包括对应于第一比特的第一硬值，以及对应于第二比特的第二硬值；
从硬值序列中抽取第一硬值和第三硬值作为译码结果，第三硬值为对应于第二比特中的信息比特的硬值。
第七方面，提供一种通信装置，该通信装置包括接收机和译码器：
接收机，用于接收来自编码装置的消息，消息中包括待译码的子序列，子序列包括第一比特，第一比特的类型为已知比特；
译码器，用于将第一比特的类型作为PC比特，并根据PC比特对应的第一译码算法对第一比特进行译码。
在一种可能的设计中，子序列还包括第二比特，第二比特的类型包括冻结比特、奇偶校验比特或信息比特中的至少一种，译码器，进一步用于：
根据第二比特的类型对应的第二译码算法对第二比特进行译码。
在一种可能的设计中，消息为上行控制消息，或下行控制消息。
在一种可能的设计中，上行控制消息中包括第一字段和第二字段，第一字段用于指示子序列中是否包括第一比特，第二字段用于指示第一比特在子序列中的位置。
在一种可能的设计中，下行控制消息中包括第三字段和第四字段，第三字段用于指示子序列中是否包括第一比特，第四字段用于指示第一比特在子序列中的位置。
在一种可能的设计中，该译码器，具体用于：
将第一比特的类型映射为PC比特，得到位置分布序列，位置分布序列用于表征子序列中各个比特的类型；
根据位置分布序列，分别确定第一译码算法和第二译码算法；
根据第三译码算法对子序列进行译码，第三译码算法包括第一译码算法和第二译码算 法。
在一种可能的设计中，在第二比特的类型中不包括信息比特时，第三译码算法不包括软值计算，软值计算用于确定子序列中各个比特的比特值为0或1的似然概率。
在一种可能的设计中，在第二比特的类型中包括信息比特时，第三译码算法包括软值计算，软值计算用于确定子序列中各个比特的比特值为0或1的似然概率。
在一种可能的设计中，在第二比特的类型中不包括信息比特时，译码器，进一步用于：
根据第三译码算法对子序列进行译码，得到硬值序列，硬值序列包括对应于第一比特的第一硬值，以及对应于第二比特的第二硬值；
从硬值序列中抽取第一硬值作为译码结果。
在一种可能的设计中，在第二比特的类型中包括信息比特时，译码器，进一步用于：
根据第三译码算法对子序列进行译码，得到硬值序列，硬值序列包括对应于第一比特的第一硬值，以及对应于第二比特的第二硬值；
从硬值序列中抽取第一硬值和第三硬值作为译码结果，第三硬值为对应于第二比特中的信息比特的硬值。
第八方面，提供一种通信装置，该通信装置包括接收机和译码器：
接收机，用于接收来自编码装置的消息，消息中包括待译码的子序列，子序列包括第一比特，第一比特的类型为已知比特；
译码器，用于将第一比特的类型作为冻结比特，并根据冻结比特对应的第一译码算法对第一比特进行译码。
在一种可能的设计中，子序列还包括第二比特，第二比特的类型包括冻结比特、奇偶校验比特或信息比特中的至少一种，译码器，进一步用于：
根据第二比特的类型对应的第二译码算法对第二比特进行译码。
在一种可能的设计中，消息为上行控制消息，或下行控制消息。
在一种可能的设计中，上行控制消息中包括第一字段和第二字段，第一字段用于指示子序列中是否包括第一比特，第二字段用于指示第一比特在子序列中的位置。
在一种可能的设计中，下行控制消息中包括第三字段和第四字段，第三字段用于指示子序列中是否包括第一比特，第四字段用于指示第一比特在子序列中的位置。
在一种可能的设计中，译码器，具体用于：
将第一比特的类型映射为冻结比特，得到位置分布序列，位置分布序列用于表征子序列中各个比特的类型；
根据位置分布序列，分别确定第一译码算法和第二译码算法；
根据第三译码算法对子序列进行译码，第三译码算法包括第一译码算法和第二译码算法。
在一种可能的设计中，在第二比特的类型中不包括信息比特时，第三译码算法不包括软值计算，软值计算用于确定子序列中各个比特的比特值为0或1的似然概率。
在一种可能的设计中，在第二比特的类型中包括信息比特时，第三译码算法包括软值计算，软值计算用于确定子序列中各个比特的比特值为0或1的似然概率。
在一种可能的设计中，在第二比特的类型中不包括信息比特时，译码器，进一步用于：
根据第三译码算法对子序列进行译码，得到硬值序列，硬值序列包括对应于第一比特的第一硬值，以及对应于第二比特的第二硬值；
从硬值序列中抽取第一硬值作为译码结果。
在一种可能的设计中，在第二比特的类型中包括信息比特时，译码器，进一步用于：
根据第三译码算法对子序列进行译码，得到硬值序列，硬值序列包括对应于第一比特的第一硬值，以及对应于第二比特的第二硬值；
从硬值序列中抽取第一硬值和第三硬值作为译码结果，第三硬值为对应于第二比特中的信息比特的硬值。
第九方面，提供一种通信装置，通信装置包括接收机和译码器；
接收机，用于接收来自编码装置的消息，消息中包括待译码的子序列，子序列包括第一比特，第一比特的类型为已知比特；
译码器，用于根据第一比特的类型对应的第一译码算法对第一比特进行译码。
在一种可能的设计中，子序列还包括第二比特，第二比特的类型包括冻结比特、奇偶校验比特或信息比特中的至少一种，译码器，进一步用于：
根据第二比特的类型对应的第二译码算法对第二比特进行译码。
在一种可能的设计中，消息为上行控制消息，或下行控制消息。
在一种可能的设计中，上行控制消息中包括第一字段和第二字段，第一字段用于指示子序列中是否包括第一比特，第二字段用于指示第一比特在子序列中的位置。
在一种可能的设计中，下行控制消息中包括第三字段和第四字段，第三字段用于指示子序列中是否包括第一比特，第四字段用于指示第一比特在子序列中的位置。
在一种可能的设计中，该译码器，具体用于：
根据子序列对应的位置分布序列，分别确定第一译码算法和第二译码算法；
根据第三译码算法对子序列进行译码，第三译码算法包括第一译码算法和第二译码算法。
在一种可能的设计中，在第二比特的类型中不包括信息比特时，第三译码算法不包括软值计算，软值计算用于确定子序列中各个比特的比特值为0或1的似然概率。
在一种可能的设计中，在第二比特的类型中包括信息比特时，第三译码算法包括软值计算，软值计算用于确定子序列中各个比特的比特值为0或1的似然概率。
在一种可能的设计中，在第二比特的类型中不包括信息比特时，译码器，具体用于：
根据第三译码算法对子序列进行译码，得到硬值序列，硬值序列包括对应于第一比特的第一硬值，以及对应于第二比特的第二硬值；
从硬值序列中抽取第一硬值作为译码结果。
在一种可能的设计中，在第二比特的类型中包括信息比特时，译码器，具体用于：
根据第三译码算法对子序列进行译码，得到硬值序列，硬值序列包括对应于第一比特的第一硬值，以及对应于第二比特的第二硬值；
从硬值序列中抽取第一硬值和第三硬值作为译码结果，第三硬值为对应于第二比特中的信息比特的硬值。
第十方面，提供一种通信装置，通信装置包括编码器和发送机：
编码器，用于分别获取第一比特和第二比特，第一比特的类型为已知比特，第二比特的类型包括冻结比特、奇偶校验比特或信息比特中的至少一种；基于第一比特生成导频序列；对第二比特进行编码，得到第一编码序列；
发送机，用于在确定发送导频序列时，向译码装置发送第二编码序列，第二编码序列 中包括导频序列和第一编码序列。
在一种可能的设计中，在确定不发送导频序列时，第二编码序列为第一编码序列。
在一种可能的设计中，第二编码序列为上行控制消息，或下行控制消息。
在一种可能的设计中，上行控制消息中包括第一字段和第二字段，第一字段用于指示子序列中是否包括第一比特，第二字段用于指示第一比特在子序列中的位置。
在一种可能的设计中，下行控制消息中包括第三字段和第四字段，第三字段用于指示子序列中是否包括第一比特，第四字段用于指示第一比特在子序列中的位置。
在一种可能的设计中，该编码器，进一步用于：
在空口资源充足时，确定发送导频序列；或者，
在空口资源紧张时，确定不发送导频序列。
第十一方面，提供一种通信装置，包括：输入接口电路和逻辑电路，该输入接口电路用于接收来自编码装置的消息，所述消息中包括待译码的子序列，所述子序列包括第一比特，所述第一比特的类型为已知比特；该逻辑电路，用于基于所述子序列执行上述第一方面～第四方面12～21任一项所述的方法。
第十二方面，提供一种通信装置，包括：逻辑电路和输出接口电路，该逻辑电路，用于分别获取第一比特和第二比特，所述第一比特的类型为已知比特，所述第二比特的类型包括冻结比特、奇偶校验比特或信息比特中的至少一种；基于所述第一比特生成导频序列；对所述第二比特进行编码，得到编码序列，执行上述第五方面中任一项所述的方法；该输出接口电路，用于向译码装置发送编码消息，所述编码消息包括所述导频序列和所述编码序列。
第十三方面，提供一种通信装置，包括：存储器，用于存储程序；处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，使得所述通信装置执行上述第一方面～第五方面中任一项所述的方法。
在一种可能的设计中，所述处理器包括所述存储器。
在一种可能的设计中，所述通信装置为芯片或集成电路。
第十四方面，提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机可读指令，当所述计算机可读指令在通信装置上运行时，使得所述通信装置执行上述第一方面～第五方面中任一项所述的方法。
第十五方面，提供一种计算机程序产品，当所述计算机程序产品在通信装置上运行时，使得所述通信装置执行上述第一方面～第五方面任一所述的方法。
第十六方面，提供了一种芯片系统，该芯片系统包括处理器，还可以包括存储器，用于实现上述第一方面～第五方面中任一所述的方法。该芯片系统可以由芯片构成，也可以包含芯片和其他分立器件。
附图说明
图1A为本申请实施例适用的一种通信系统的架构示意图；
图1B为本申请实施例适用的另一种通信系统的架构示意图；
图2为本申请实施例中并列译码流程的示意图；
图3为本申请实施例中极化码的快速译码方法的流程图；
图4为本申请实施例提供的一种极化码的编码方法的流程图；
图5为本申请实施例提供的一种极化码的译码方法的流程图；
图6为本申请实施例提供的并行译码流程中已知比特的映射方式的一种示意图；
图7为本申请实施例提供的另一种极化码的译码方法的流程图；
图8为本申请实施例提供的并行译码流程中已知比特的映射方式的另一种示意图；
图9为本申请实施例提供的另一种极化码的译码方法的流程图；
图10为本申请实施例提供的并行译码流程中已知比特的映射方式的另一种示意图；
图11为本申请实施例提供的另一种极化码的译码方法的流程图；
图12为本申请实施例提供的另一种极化码的译码方法的流程图；
图13为本申请实施例提供的另一种极化码的译码方法的流程图；
图14为本申请实施例提供的另一种极化码的译码方法的流程图；
图15为本申请实施例提供的另一种极化码的译码方法的流程图；
图16为本申请实施例提供的一种极化码的译码装置的示意图；
图17为本申请实施例提供的一种通信装置的结构示意图；
图18为本申请实施例提供的另一种通信装置的结构示意图；
图19为本申请实施例提供的另一种通信装置的结构示意图；
图20为本申请实施例提供的另一种通信装置的结构示意图；
图21为本申请实施例提供的另一种通信装置的结构示意图。
具体实施方式
本申请实施例提供一种极化码的编译码方法及装置。其中，方法和装置是基于同一技术构思的，由于方法及装置解决问题的原理相似，因此装置与方法的实施可以相互参见，重复之处不再赘述。本申请实施例的描述中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。本申请中所涉及的至少一个是指一个或多个；多个，是指两个或两个以上。另外，需要理解的是，在本申请的描述中，“第一”、“第二”、“第三”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
本申请实施例提供的编译码方法可以应用于第五代(5th generation，5G)通信系统，例如5G新空口(new radio，NR)系统，设备到设备(device to device，D2D)通信系统，蓝牙通信系统，WiFi通信系统或应用于未来的各种通信系统。
首先，对本申请实施例应用的通信系统进行介绍。
图1A所示为本申请实施例提供的编译码方法所适用的一种可能的通信系统100的架构。如图1A所示，通信系统100中包括：网络装置200和位于网络装置200的覆盖范围内的一个或多个终端300(图1A中包括3个终端)。通信系统100还可以包括核心网，网络装置200接入核心网，从而为覆盖范围内的终端300提供服务。例如，参见图1A所示，网络装置200为网络装置200覆盖范围内的一个或多个终端300提供无线接入。除此之外，不同的网络装置200之间的覆盖范围可以存在重叠的区域，图中两个椭圆区域交叠部分及网络装置200和网络装置200’之间的重叠区域。
网络装置200为无线接入网(radio access network，RAN)中的节点，又可以称为基站，还可以称为RAN节点(或设备)。示例性的，网络装置200可以为：下一代基站(next generation nodeB，gNB)、下一代演进的基站(next generation evolved nodeB，Ng-eNB)、传输接收点(transmission reception point，TRP)、演进型节点B(evolved Node B，eNB)、无线网络控制器(radio network controller，RNC)、节点B(Node B，NB)、基站控制器(base station controller，BSC)、基站收发台(base transceiver station,BTS)、家庭基站(例如，home evolved NodeB，或home Node B，HNB)、基带单元(base band unit，BBU)，或无线保真(wireless fidelity，Wifi)接入点(access point，AP)，网络装置200还可以是卫星，卫星还可以称为高空平台、高空飞行器、或卫星基站。网络装置200还可以是其他具有网络装置功能的设备，例如，网络装置200还可以是D2D通信中担任网络装置功能的设备。网络装置200还可以是未来可能的通信系统中的网络装置。
在一些部署中，网络装置200可以包括集中式单元(centralized unit，CU)和(distributed unit，DU)。网络装置200还可以包括有源天线单元(active antenna unit，AAU)。CU实现网络装置200的部分功能，DU实现网络装置的部分功能，比如，CU负责处理非实时协议和服务，实现无线资源控制(radio resource control，RRC)，分组数据汇聚层协议(packet data convergence protocol，PDCP)层的功能。DU负责处理物理层协议和实时服务，实现无线链路控制(radio link control，RLC)层、媒体接入控制(media access control，MAC)层和物理(physical，PHY)层的功能。AAU实现部分物理层处理功能、射频处理及有源天线的相关功能。由于RRC层的信息最终会变成PHY层的信息，或者，由PHY层的信息转变而来，因而，在这种架构下，高层信令，如RRC层信令，也可以认为是由DU发送的，或者，由DU+AAU发送的。可以理解的是，网络装置200可以为包括CU节点、DU节点、AAU节点中一项或多项的设备。本申请实施例对此不做限定。需要说明的是，网络装置200可以是网络装置200本身，也可以是网络装置200中的芯片。
终端300，又称之为用户设备(user equipment，UE)、移动台(mobile station，MS)、移动终端(mobile terminal，MT)等，是一种向用户提供语音和/或数据连通性的设备。例如，终端300包括具有无线连接功能的手持式设备、车载设备等。目前，终端300可以是：手机(mobile phone)、平板电脑、笔记本电脑、掌上电脑、移动互联网设备(mobile internet device，MID)、可穿戴设备(例如智能手表、智能手环、计步器等)，车载设备(例如，汽车、自行车、电动车、飞机、船舶、火车、高铁等)、虚拟现实(virtual reality，VR)设备、增强现实(augmented reality，AR)设备、工业控制(industrial control)中的无线终端、智能家居设备(例如，冰箱、电视、空调、电表等)、智能机器人、无人驾驶中的无线终端、远程手术(remote medical surgery)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端，或智慧家庭(smart home)中的无线终端、飞行设备(例如，智能机器人、热气球、无人机、飞机)等。终端300还可以是其他具有终端功能的设备，例如，终端300还可以是D2D通信中担任终端功能的终端。需要说明的是，终端300可以是终端300本身，也可以是终端300中的芯片。以手机为例，终端300可以是手机本身，也可以是手机中的芯片，如基带芯片。
图1B所示为本申请实施例提供的编译码方法所适用的另一种可能的通信系统100的架构。如图1B所示，通信系统100中包括：网络装置200(图1B中包括4个网络装置) 和位于网络装置200的覆盖范围内的一个或多个终端300(图1B中包括1个终端)。进一步地，该网络装置200可以包括第一网络装置201和第二网络装置202。第一网络装置201可以是宏基站。宏基站是架设在铁塔上的基站，这种基站的体很大，承载的用户数据很大，覆盖面积很广，一般都能达到数十公里。第二网络装置202可以是微基站，或者是皮基站，或者飞基站。其中，该微基站可以是微型化的基站，通常指在楼宇中或密集区安装的小型基站，这种基站的体积小，覆盖面积小，承载的用户量比较低。该皮基站可以是比微基站更小型的基站，相较于宏基站和微基站，该皮基站的单载波发射功率和覆盖能力进一步减小。该飞基站可以由家庭带宽接入，是比宏基站、微基站和皮基站更小型的基站。
通信系统100还可以包括核心网400。第一网络装置201可以接入该核心网400。从而为其覆盖范围内的终端300提供服务(例如提供无线接入服务)。第二网络装置202可以接入该核心网400，从而为其覆盖范围内的终端300提供服务。第二网络装置202还可以通过第一网络装置201接入该核心网400，从而为其覆盖范围内的终端300提供服务。
下面对本申请实施例中的技术特征进行介绍。
通信系统通常采用信道编码提高数据传输的可靠性，保证通信的质量。例如可以采用极化码、RM码等编码方法。其中，极化码是一种可以渐进达到信道容量的编码方法，在广泛的工作区间(如码长、码率或信噪比等)都具有极佳的译码性能。
目前的极化码译码方案中，译码装置将待译码序列中所包括的比特分为如下三个类型：信息比特、冻结比特以及PC比特。其中，信息比特用于承载信息，信息比特可以包括净荷(payload)比特和循环冗余校验(cyclic redundancy check，CRC)比特。冻结比特是指固定填充的比特，通常冻结比特的比特值为0。PC比特用于校验，例如PC比特可辅助CRC比特对净荷比特进行校验。译码装置可以基于比特的类型对待译码序列，利用SC或者SCL等Polar译码算法进行译码，实现快速译码，提高译码效率。该译码流程可以包括比特的类型识别、软值计算、硬值计算以及硬值回溯。在对待译码序列进行比特的类型识别时，译码装置可以按照并行度提前将待译码序列划分为多个待译码的子序列，对该多个子序列中每个子序列进行串行的软值计算和硬值计算的译码循环得到硬值序列，然后译码装置对硬值序列进行硬值回溯，如图2所示。以SC译码算法为例，软值计算即对数似然比(LLR)计算，硬值计算则是指基于LLR计算结果进行译码。
其中，比特的类型识别是指译码装置确定待译码序列中每个比特的类型，以及根据每个子序列中比特的类型的组合方式，确定该子序列对应的译码算法。软值计算是指译码装置确定每个子序列中每个比特的软值。硬值计算是指译码装置根据每个子序列中每个比特的软值通过最大似然估计算法确定该待译码序列中每个比特的硬值，得到该待译码序列对应的硬值序列。硬值回溯过程是指译码装置从硬值序列中抽取所有信息比特的硬值。软值是指比特的比特值为0的似然概率或者为1的似然概率，硬值是指比特的比特值为0或1，子序列中每个比特的软值可以由编码装置指示的软值信息确定的。
需要说明的是，对于一个子序列，译码装置在对该子序列进行译码时，可以不进行软值计算，直接进行硬值计算。例如，一个子序列中的比特的类型皆为冻结比特，译码装置在比特的类型识别中确定该子序列中每个比特的类型皆为冻结比特后，可以根据冻结比特的比特值确定该子序列中每个比特的比特值，从而无需进行软值计算。
为了便于理解，请参见图3，图3所示为极化码的快速译码方法的流程示意图。
S301：译码装置接收来自编码装置的待译码序列，该待译码序列中包括至少一个比特。
需要说明的是，待译码序列又可以称为待译码信息，待译码码字、待译码码块、码字或码块等，本申请实施例对此不做限定。
S302：译码装置根据待译码序列对应的位置分布序列，确定该待译码序列中每个比特的类型。
需要说明的是，位置分布序列用于指示每个比特的类型和位置。例如00表示冻结比特，01表示信息比特，10表示PC比特。例如，待译码序列为[比特0比特1比特2比特3]，待译码序列对应的位置分布序列为[00 10 01 01]，则译码装置可以根据位置分布序列确定该待译码序列中比特的类型依次为[冻结比特PC比特信息比特信息比特]，即比特0的类型为冻结比特，比特1的类型为PC比特，比特2和比特3的类型皆为信息比特。该位置分布序列可以是由编码装置指示给译码装置的。
S303：译码装置对待译码序列进行划分得到至少一个待译码的子序列。
例如，待译码序列中包括128个比特，译码装置可以将待译码序列划分为16个待译码的子序列，每个子序列中包括8个比特。
S304：译码装置根据每个子序列中每个比特的类型，确定与每个子序列对应的译码算法。
译码装置可以根据每个子序列中比特的类型的组合方式和/或排列方式，确定与该每个子序列对应的译码算法，该译码算法为预先根据子序列中比特的数量、子序列中比特的类型的组合方式或子序列中比特的类型的排列方式中的一项或多项，推算并实验得出的收益最佳的简易译码算法。该译码算法可以用于根据子序列确定该子序列对应的硬值序列。该译码算法可以指示是否进行软值计算。例如，在子序列中比特的类型不包括信息比特时，译码算法可以指示不进行软值计算；或者，在子序列中比特的类型包括信息比特时，该译码算法可以指示需要进行软值计算。进一步地，该译码算法还可以指示路径分裂时需要保留的路径的数量、纠错方式、软判决方式或硬判决方式等信息中的至少一种。
S305：译码装置利用每个子序列对应的译码算法对待译码序列进行快速译码，得到该待译码序列对应的硬值序列。
S306：译码装置根据信息比特对应的位置分布序列，从硬值序列中抽取所有信息比特的硬值，得到译码结果。
例如，00表示冻结比特，01表示信息比特，10表示PC比特。待译码序列为[比特0比特1比特2比特3]，待译码序列对应的位置分布序列为[00 10 01 01]，待译码序列对应的硬值序列为[0 1 1 1]。译码装置可以根据信息比特对应的位置分布序列，即01，从该硬值序列中抽取所有信息比特的硬值，得到译码结果，即[1 1]。
至此，译码装置完成对待译码序列的快速译码。
目前的极化码编码方案中，编码装置使用一些比特值为已知的比特进行冗余填充，以获取译码收益。该冗余主要来自以下两个方面：上下行配比和反馈窗口导致的固定填充；物理下行共享信道(Physical Downlink Shared Channel，PDSCH)资源不调度导致的固定填充。以单载波为例，单载波使用7个比特进行反馈，但实际最多有4个比特会真实反馈混合自动重传请求(hybrid automatic repeat request，HARQ)信息，其余3个进行冗余填充，例如填充非确认字符(non acknowledge character，NACK)信息。双载波需要使用14个比特进行反馈，14个比特中的8个比特的类型为信息比特，用于承载HARQ信息，剩余的6个比特的类型为已知比特，用于承载NACK信息。例如该14个比特为[1 1 1 1 0 0 0 1 1 1 1  0 0 0 0]，1表示信息比特，用于承载HARQ信息，0表示已知比特，用于承载NACK信息。
在具体实施时，编码装置可以使用一些比特值为已知的比特进行冗余填充，然后将这些比特与其他类型的比特联合编码后发送给译码装置，其中这些比特的类型可以称为已知比特(known bits)。由于这些比特的比特值是已知的，因此译码装置可以直接确定这些比特的比特值，从而可以提高译码可靠性，带来译码收益。例如，编码装置可以将已知比特映射到可靠性低的比特位置上，这样携带有用信息的信息比特就可以映射到可靠性高的比特位置上，从而提高译码可靠性，还可以提高广播信令传输的效率。再例如，编码装置可以将已知比特映射到译码顺序的起始位置。在路径分裂后需要保留至少一条路径时，由于已知比特的比特值是已知的，译码装置可以根据起始位置处已知比特的译码结果以及该已知比特的比特值，确定该已知比特的译码可靠性，并基于该已知比特的译码可靠性选择要保留的路径，以提高译码可靠性。例如，3个比特可以分裂出8条路径，对于每条路径，译码装置可以根据起始位置处的已知比特的译码结果和已知比特的比特值，确定已知比特的译码可靠性。如果译码装置要保留1条路径，则译码装置可以确定该8条路径中、已知比特的译码可靠性最高的路径为要保留的路径。
在编码侧，编码装置可以使用已知比特进行冗余填充，然后将已知比特与其他类型的比特一起映射到对应子信道的资源块内发送给译码装置。当空口资源比较紧张时，已知比特的填充会额外增加空口资源的负荷。另外，由于目前的译码算法适配的比特的类型仅包括信息比特、冻结比特或PC比特中的一项或多项，当子序列中比特的类型包括已知比特时，译码装置不能确定针对该子序列的译码算法。译码装置可以将该子序列中的已知比特作为信息比特进行译码，而信息比特对应的译码算法包括软值计算和硬值计算，开销较大，译码，从而降低译码效率。
鉴于此，本申请实施例提供的一种极化码的编译码方法及装置，用于对包括已知比特的子序列进行译码，在保证已知比特带来的收益的情况下，降低开销，提高译码效率。
下面分别从编码侧和译码侧介绍本申请实施例提供的一种极化码的编译码方法。
图4所示为本申请实施例提供的一种极化码的编码方法的流程示意图，该方法可以应用于图1A或图1B所示的通信系统100。该方法的执行主体可以为编码装置，编码装置可以是网络装置200或网络装置200中的至少一个芯片，也可以是终端300或终端300中的至少一个芯片。编码装置也可以称为发送端，译码装置为接收端。当编码装置是网络装置200时，译码装置为终端300，当编码装置为终端300时，译码装置为网络装置200。当该方法应用于图1B所示的通信系统100时，如果编码装置是第一网络装置201，则译码装置为第二网络装置202或终端300；如果编码装置是第二网络装置202，则译码装置为第一网络装置201或终端300。下面以该方法应用于图1A或图1B所示的通信系统100为例，对该方法进行介绍。
S401：编码装置分别获取第一比特和第二比特，第一比特的类型为已知比特，第二比特的类型为冻结比特、PC比特或信息比特中的至少一种。
编码装置可以对待编码的序列进行拆分，分别得到该待编码的序列中的第一比特和该待编码的序列中的第二比特。例如，编码装置可以通过待编码的序列对应的位置分布序列，确定待编码的序列中每个比特的类型，然后根据待编码的序列中每个比特的类型，分别获取第一比特和第二比特。其中，该待编码的序列可以为上行控制信息(uplink control  information，UCI)，或为下行控制信息(downlink control information，DCI)等。
举例而言，00表示冻结比特，01表示信息比特，10表示PC比特，11表示已知比特。如果待编码的序列为[比特0比特1比特2比特3比特4比特5比特6比特7]，待编码的序列对应的位置分布序列为[11 01 01 00 10 11 11 10]，则编码装置可以根据该位置分布序列确定该待编码的序列中每个比特的类型依次为[已知比特信息比特信息比特冻结比特PC比特已知比特已知比特PC比特]，即比特0为已知比特，比特1为信息比特，比特2为信息比特，比特3为冻结比特，比特4为PC比特，比特5为已知比特，比特6位已知比特以及比特7为PC比特。进一步地，编码装置可以根据每个比特的类型，分别获取第一比特和第二比特，即第一类型的比特包括比特0、比特5和比特6，第二类型的比特包括比特1、比特2、比特3、比特4和比特7。
S402：编码装置基于第一比特生成导频序列。
编码装置基于第一比特生成导频序列后，可以不发送该导频序列。例如，如果编码装置确定不使用已知比特进行冗余填充，则编码装置不发送该导频序列；如果编码装置确定使用已知比特进行冗余填充，则编码装置发送该导频序列。
S403：编码装置对第二比特进行编码，得到第一编码序列。
进一步地，编码装置可以根据网络资源占用情况(例如空口资源占用情况)或译码性能需求等信息，确定是否使用已知比特进行冗余填充。例如，如果编码装置确定使用已知比特进行冗余填充，则执行S404；如果编码装置确定不使用已知比特进行冗余填充，则执行S405。
S404：在确定使用已知比特进行冗余填充时，编码装置向译码装置发送第二编码序列，该第二编码序列中包括导频序列和第一编码序列。
例如，在空口资源充足或者译码性能需求高的场景下，编码装置可以使用已知比特进行冗余填充，即向译码装置发送该导频序列以满足高要求的译码性能需求，提高译码性能。进一步地，在确定使用已知比特进行冗余填充(即确定向译码装置发送导频序列)后，编码装置可以根据待编码的序列对应的位置分布序列，将导频序列和第一编码序列分别映射至对应子信道上的对应资源块内发送给译码装置。
S405：在确定不使用已知比特进行冗余填充时，编码装置向译码装置发送第二编码序列，该第二编码序列为第一编码序列。
例如，在空口资源紧张的场景下，编码装置可以不使用已知比特进行冗余填充，即不向译码装置发送导频序列，以减轻空口资源的负荷。进一步地，在确定不使用已知比特进行冗余填充(即确定不向译码装置发送导频序列)后，编码装置可以根据第二比特对应的位置分布序列，将第一编码序列映射至对应子信道上的资源块内发送给译码装置，并删除导频序列。
在一种可能的实施方式中，如果编码装置在S402之前根据网络资源占用情况，或译码性能需求等信息，确定不使用已知比特进行冗余填充，则编码装置不需要基于第一比特生成导频序列，即编码装置可以仅执行S401、S403以及S405所示的步骤。
在一种可能的实现方式中，第二编码序列可以是下行控制消息，或者是上行控制消息。该第二编码序列可以包括至少一个子序列。针对该至少一个子序列中的任一子序列，如果第二编码序列是下行控制消息，则该下行控制信息包括第一字段和第二字段，该第一字段用于指示该子序列中是否包括第一比特，该第二字段用于指示第一比特在该子序列中的位 置；或者，如果第二编码序列是上行控制消息，则该上行控制消息包括第三字段和第四字段，该第三字段用于指示该子序列中是否包括第一比特，该第四字段用于指示第一比特在该子序列中的位置。
本申请上述实施例中，编码装置从待编码的序列中分别获取第一比特和第二比特，并，基于该第一比特生成导频序列，该导频序列可以不被发送。编码装置可以根据网络资源占用情况或译码性能需求等信息，确定是否使用已知比特进行冗余填充，即是否发送该导频序列。在空口资源充足或译码性能需求高时，编码装置可以发送该导频序列，从而可以提高译码性能，满足高要求的译码性能需求。在空口资源紧张时，编码装置可以不发送该导频序列，从而可以减轻空口资源的负荷。
编码装置向译码装置发送第二编码序列。译码装置接收该第二编码序列，并对该第二编码序列进行译码。具体地，译码装置可以根据并行度将第二编码序列划分为至少一个待译码的子序列，并对该至少一个待译码的子序列进行并行译码。其中，该至少一个待译码的子序列中包括第一子序列，第二子序列或第三子序列中的至少一种。第一子序列中仅包括第一比特，该第一比特的类型为已知比特。第二子序列中包括第一比特和第二比特，该第二比特的类型为冻结比特、PC比特或信息比特中的至少一种。第三子序列中仅包括第二比特。
需要说明的是，如果第二编码序列中不包括第一比特，即该第二编码序列为第一编码序列，则译码装置可以参照图3所示的译码流程对该第二编码序列进行译码。如果该至少一个待译码的子序列中包括第三子序列，则译码装置可以参照图3所示的译码流程对该第三子序列进行译码。
下面分别对第一子序列和第二子序列进行译码的具体流程进行介绍，下文中的图5、图7、图9以及图11所示的流程图为对第一子序列进行译码的流程图，图12～图15所示的流程图为对第二子序列进行译码的流程图。
需要说明的是，本申请实施例提供的极化码的译码方法，可以应用于图1A或图1B所示的通信系统100。该方法的执行主体可以为译码装置，译码装置可以是网络装置200或网络装置200中的至少一个芯片，也可以是终端300或终端300中的至少一个芯片。编码装置也可以称为发送端，译码装置为接收端。当编码装置是网络装置200时，译码装置为终端300，当编码装置为终端300时，译码装置为网络装置200。当该方法应用于图1B所示的通信系统100时，如果编码装置是第一网络装置201，则译码装置为第二网络装置202或终端300；如果编码装置是第二网络装置202，则译码装置为第一网络装置201或终端300。下文中将以该方法应用于图1A或图1B所示的通信系统100为例，对该方法进行介绍。
实施例1
请参考图5，图5所示为本申请实施例提供的一种极化码的译码方法的流程图。该方法中，译码装置将第一比特的类型作为PC比特，并基于PC比特对应的译码算法对第一子序列进行译码，其中第一子序列仅包括第一比特。
S501：译码装置接收来自编码装置的消息，该消息中包括第一子序列，该第一子序列中仅包括第一比特，该第一比特的取值范围与PC比特的取值范围一致。
译码装置接收来自编码装置的消息，该消息可以包括第一子序列，该第一子序列中仅包括第一比特。例如，第一子序列包括8个比特，该8个比特的类型皆为已知比特。该消 息可以是上行控制消息，也可以是下行控制消息。例如在编码装置为终端300，译码装置为网络装置200时，该消息可以是上行控制消息。再例如，在编码装置为第一网络装置201，译码装置为第二网络装置202时，该消息可以是下行控制消息。在该消息为上行控制消息时，该上行控制消息中包括第一字段和第二字段，该第一字段用于指示第一子序列中是否包括第一比特，该第二字段用于指示第一比特在该第一子序列中的位置。或者，在该消息为下行控制消息时，该下行控制消息中包括第三字段和第四字段，该第三字段用于指示第一子序列中是否包括第一比特，该第四字段用于指示第一比特在该第一子序列中的位置。其中，第一字段和/或第二字段可以是上行控制消息中预定义的字段或预留字段，第三字段和/或第四字段可以是下行控制消息中预定义的字段或预留字段。
第一比特的取值范围与PC比特的取值范围一致，是指译码后第一比特的可能取值与译码后PC比特的可能取值一致。例如，译码后PC比特的可能取值为0或1，译码后第一比特的可能取值为0或1。再例如，第一比特携带信息时，该第一比特的可能取值为0或1。其中，第一比特的可能取值可以由已知比特对应的位置分布序列确定的，例如，已知比特的位置分布序列可以包括100和102，其中100表示已知比特且该已知比特的比特值为0，101表示已知比特且该已知比特的比特值为0。PC比特的可能取值可以由上一个子序列的译码结果确定的，其具体实现过程可参考现有技术，在此不再赘述。
S502：译码装置将第一比特的类型作为PC比特，并根据该PC比特对应的译码算法对第一子序列进行译码，得到该第一子序列对应的硬值序列，该硬值序列中仅包括对应于第一比特的第一硬值。
当第一比特的取值范围与PC比特的取值范围一致时，不同类型的比特的特性如表1所示。如表1所示，译码结果用于表征对各个类型的比特进行译码后的取值范围，取值特性用于表征获取该译码结果的计算方式，校验和纠错用于表征各个类型的比特对译码过程中的校验和纠错的贡献，承载内容用于表征各个类型的比特译码后取值的含义或作用。如表1所示，就译码结果而言，已知比特的取值范围与PC比特、信息比特的取值范围一致，取值范围为0或1，而冻结比特的取值范围固定为0。就取值特性而言，已知比特的取值特性与冻结比特的取值特性一致，译码结果已知且不需要进行软值计算，而PC比特的取值虽然不需要软值计算但与更早的译码结果有关，信息比特的取值不仅需要软值计算还与更早的译码结果有关。就校验和纠错而言，已知比特与PC比特一致，需要参与校验但纠错时不会被翻转，而冻结比特不参加校验，信息比特不仅需要参与校验而且纠错时还会被翻转。就承载内容而言，已知比特与信息比特一致，用于承载消息，而冻结比特为固定填充无实际含义，PC比特用于承载校验值。其中，译码结果与校验和纠错特性用于决定如何进行译码，在比特的类型识别和硬值计算中会被使用；取值特性可以用于决定是否进行软值计算，在软值计算中会被使用；承载内容用于判断是否要将比特作为信息进行抽取，在硬值回溯中会被使用。
表1：不同类型的比特的特性对比表
Figure PCTCN2020082639-appb-000001
Figure PCTCN2020082639-appb-000002
译码算法不能适配包括已知比特的子序列，但可以适配包括冻结比特、PC比特或信息比特中的至少一种的子序列。译码算法是在比特的类型识别中确定的，并用于硬值计算中。而比特的类型识别以及硬值计算，与译码结果、校验和纠错有关。考虑到已知比特的译码结果与PC比特的译码结果一致，且已知比特对校验和纠错的贡献与PC比特对校验和纠错的贡献也一致。因此，译码装置可以在比特的类型识别和硬值计算中将第一比特的类型作为PC比特进行处理。这样，译码装置在比特的类型识别和硬值计算中可以将已知比特作为PC比特进行译码，从而可以适配PC比特对应的译码算法对已知比特进行译码，获得已知比特带来的译码性能的同时，实现对已知比特的译码。例如，000、110以及111表示冻结比特，001和010表示信息比特，011表示PC比特，100表示取值为0的已知比特，101表示取值为1的已知比特。第一子序列对应的位置分布序列为[100 101 100 100]，即该第一子序列中的四个比特的类型皆为已知比特。在比特的类型识别和硬值计算中，译码装置可以将已知比特映射为PC比特，得到映射后的位置分布序列为[011 011 011 011]，即映射后4个比特的类型皆为PC比特。
就取值特性而言，比特的取值特性与软值计算相关，而已知比特的取值特性与冻结比特的取值特性一致，意味着已知比特在软值计算中可以获得冻结比特等同的译码效率收益。因此，译码装置可以在软值计算中将第一比特的类型作为冻结比特进行处理。由于在软值计算中，译码装置可以将已知比特作为冻结比特进行处理，而该第一子序列中的比特的类型皆为已知比特，因此译码装置在对第一子序列进行译码时可以跳过软值计算，减少因软值计算带来的开销，从而可以提高译码效率。例如，000、110以及111表示冻结比特，001和010表示信息比特，011表示PC比特，100表示取值为0的已知比特，101表示取值为1的已知比特。第一子序列对应的位置分布序列为[100 100 101 101]，在软值计算中，译码装置可以将已知比特映射为冻结比特，得到映射后的位置分布序列为[000 000 000 000]，即映射后该4个比特的类型皆为冻结比特。
软值计算仅与信息比特的取值有关，对冻结比特或PC比特的取值无关。在实际应用时，在对PC比特进行软值计算时译码装置可以将PC比特作为冻结比特进行处理，即跳过软值计算。因此，在软值计算中，译码装置还可以将冻结比特作为PC比特进行处理。
就承载内容而言，比特的承载内容与硬值回溯相关，而已知比特的承载内容与信息比特的承载内容一致。因此，译码装置可以在硬值回溯中将第一比特的类型作为信息比特进行处理。这样，在硬值回溯时，译码装置可以将已知比特作为信息比特进行处理，从而可以获取第一子序列中所有已知比特的比特值。例如，000、110以及111表示冻结比特，001和010表示信息比特，011表示PC比特，100表示取值为0的已知比特，101表示取值为1的已知比特。第一子序列对应的位置分布序列为[101 101 100 101]，在硬值回溯中，译码装置将已知比特映射为信息比特，得到映射后的位置分布序列为[001 001 010 010]，即映射后该4个比特的类型皆为信息比特。
作为一种示例，在比特的类型识别和硬值计算中，译码装置可以将第一比特的类型作 为PC比特进行处理；在软值计算中，译码装置可以将第一比特的类型作为冻结比特进行处理；在硬值回溯中，译码装置可以将第一比特的类型作为信息比特进行处理，如图6所示。应理解的是，由于软值计算中译码装置可以将PC比特作为冻结比特进行处理，因此，在软值计算中，译码装置还可以将第一比特的类型作为PC比特。
在S502中，第一子序列中仅包括第一比特，译码装置将第一比特的类型作为PC比特，可以使得译码装置按照PC比特对应的译码算法对第一子序列进行译码，从而实现了对已知比特的译码。具体地，译码装置可以根据上行控制消息中的第二字段或下行控制消息中的第四字段，将该第一子序列中的第一比特的类型映射为PC比特，得到第一位置分布序列。或者，译码装置可以根据第一子序列对应的位置分布序列，将该第一子序列中的第一比特的类型映射为PC比特，得到该第一位置分布序列。由于第一位置分布序列所指示的比特的类型不包括已知比特，因此译码装置可以根据该第一位置分布序列，确定第一子序列对应的译码算法，并根据该第一子序列对应的译码算法对第一子序列进行译码，得到第一子序列对应的硬值序列。由于第一子序列中仅包括第一比特，因此该第一子序列对应的译码算法可以为PC比特对应的译码算法。例如该PC比特对应的译码算法可以用于指示根据前一个子序列的译码结果确定PC比特的比特值。再例如该PC比特对应的译码算法还可以用于指示PC比特的比特值对获取信息比特的比特值的贡献。
在对该第一子序列进行译码时，该第一位置分布序列所指示的比特的类型仅为PC比特，译码装置可以不对该第一子序列进行软值计算，直接根据第一子序列对应的位置分布序列，确定该第一子序列对应的硬值序列。例如，000、110以及111表示冻结比特，001和010表示信息比特，011表示PC比特，100表示取值为0的已知比特，101表示取值为1的已知比特。第一子序列对应的位置分布序列为[101 101 100 101]，译码装置可以根据该第一子序列对应的位置分布序列确定该第一子序列对应的硬值序列为[1 1 0 1]。其中，该硬值序列中仅包括对应于第一比特的第一硬值。
S503：译码装置从硬值序列中抽取第一硬值作为该第一子序列的译码结果。
在硬值回溯过程中，译码装置可以将第一比特的类型作为信息比特进行处理。由于第一子序列仅包括第一比特，因此译码装置可以该硬值序列作为第一子序列的译码结果。例如，译码装置确定出的第一子序列对应的硬值序列为[1 1 0 1]，该第一子序列的译码结果为[1 1 0 1]。
本申请的上述实施例中，第一子序列中仅包括第一比特，第一比特的类型为已知比特，该第一比特的取值范围与PC比特的取值范围一致。译码装置可以将第一比特的类型作为PC比特，得到第一位置分布序列。由于该第一位置分布序列所指示的比特的类型皆为PC比特，因此译码装置可以根据该第一位置分布序列适配译码算法(如PC比特对应的译码算法)，从而实现对包括已知比特的子序列的译码。由于PC比特的比特值与软值无关，因此译码装置在根据PC比特对应的译码算法对第一子序列进行译码时，无需对第一子序列进行软值计算，从而节省了因进行软值计算产生的开销，提高了译码效率。
实施例2
请参见图7，图7所示为本申请实施例提供的另一种极化码的译码方法的流程图。该方法中，译码装置将第一比特的类型作为冻结比特，并基于冻结比特对应的译码算法对第一子序列进行译码，其中第一子序列仅包括第一比特。
S701：译码装置接收来自编码装置的消息，该消息中包括第一子序列，该第一子序列 中仅包括第一比特，该第一比特的取值范围与冻结比特的取值范围一致。
第一比特的取值范围与冻结比特的取值范围一致，是指译码后第一比特的可能取值与译码后冻结比特的可能取值一致。例如，冻结比特的比特值固定为0，第一比特的比特值也固定为0。再例如，第一比特没有携带信息时，该第一比特的比特值可以固定为0。其中，第一比特的可能取值可以由已知比特对应的位置分布序列确定，例如，已知比特的位置分布序列可以仅包括100，该100表示已知比特且该已知比特的比特值为0。
其中，S701的具体实现方式与图5中S501的具体实现方法一致，在此不再赘述。
S702：译码装置将第一比特的类型作为冻结比特，并根据该冻结比特对应的译码算法对第一子序列进行译码，得到该第一子序列对应的硬值序列，该硬值序列仅包括对应于第一比特的第一硬值。
当第一比特的取值范围与冻结比特的取值范围一致时，不同类型的比特的特性可以如表2所示。如表2所示，就译码结果而言，已知比特的取值范围与冻结比特的取值范围一致，取值范围固定为0，而PC比特、信息比特的取值范围为0或1。就取值特性而言，已知比特的取值特性与冻结比特的取值特性一致，译码结果已知且不需要进行软值计算，而PC比特的取值虽然不需要软值计算但与更早的译码结果有关，信息比特的取值不仅需要软值计算还与更早的译码结果有关。就校验和纠错而言，已知比特与PC比特一致，需要参与校验但纠错时不会被翻转，而冻结比特不参加校验，信息比特不仅需要参与校验而且纠错时还会被翻转。就承载内容而言，已知比特与信息比特一致，用于承载消息，而冻结比特为固定填充无实际含义，PC比特用于承载校验值。其中，译码结果与校验和纠错特性用于决定如何进行译码，在比特的类型识别和硬值计算中会被使用；取值特性可以用于决定是否进行软值计算，在软值计算中会被使用；承载内容用于判断是否要将比特作为信息进行抽取，在硬值回溯中会被使用。
表2：不同类型的比特的特性对比表
Figure PCTCN2020082639-appb-000003
译码算法不能适配包括已知比特的子序列，但可以适配包括冻结比特、PC比特或信息比特中的至少一种的子序列。译码算法是在比特的类型识别中确定的，并用于硬值计算中。而比特的类型识别以及硬值计算，与译码结果、校验和纠错有关。考虑到已知比特的译码结果与冻结比特的译码结果一致，译码装置可以在比特的类型识别和硬值计算中将第一比特的类型作为冻结比特进行处理。虽然将第一比特的类型作为冻结比特后，该第一比特不能参与校验，但可以简化译码流程，产生更多可简化(simplify)的译码码型，可以提高译码并行度。
作为一种示例，在比特的类型识别和硬值计算中，译码装置可以将第一比特的类型作为冻结比特进行处理；在软值计算中，译码装置可以将第一比特的类型作为冻结比特进行处理；在硬值回溯中，译码装置可以将第一比特的类型作为信息比特进行处理，如图8所示。应理解的是，由于软值计算中译码装置可以将PC比特作为冻结比特进行处理，因此，在软值计算中，译码装置还可以将第一比特的类型作为PC比特。
在S702中，第一子序列中仅包括第一比特，译码装置将第一比特的类型作为冻结比特，可以使得译码装置按照冻结比特对应的译码算法对第一子序列进行译码，从而实现了对已知比特的译码。具体地，译码装置可以根据上行控制消息中的第二字段或下行控制消息中的第四字段，将该第一子序列中的第一比特的类型映射为冻结比特，得到第一位置分布序列。或者，译码装置可以根据第一子序列对应的位置分布序列，将该第一子序列中的第一比特的类型映射为冻结比特，得到该第一位置分布序列。译码装置可以根据该第一位置分布序列，确定第一子序列对应的译码算法，并根据该第一子序列对应的译码算法对第一子序列进行译码，从而得到第一子序列对应的硬值序列。由于第一子序列中仅包括第一比特，该第一位置分布序列所指示的比特的类型仅为冻结比特，因此该第一子序列对应的译码算法可以为冻结比特对应的译码算法。例如该冻结比特对应的译码算法可以用于指示冻结比特的比特值为0。再例如，该冻结比特还可以用于指示不参与获取信息比特的比特值的校验。
在对该第一子序列进行译码时，该第一位置分布序列所指示的比特的类型仅为冻结比特，译码装置可以不对该第一子序列进行软值计算，直接根据第一子序列对应的位置分布序列，确定该第一子序列对应的硬值序列。例如，000、110以及111表示冻结比特，001和010表示信息比特，011表示PC比特，100表示取值为0的已知比特。第一子序列对应的位置分布序列为[100 100 100 100]，译码装置可以根据该第一子序列对应的位置分布序列确定该第一子序列对应的硬值序列为[0 0 0 0]。其中，该硬值序列中仅包括对应于第一比特的第一硬值。
S703：译码装置从硬值序列中抽取第一硬值作为译码结果。
在硬值回溯过程中，译码装置可以将第一比特的类型作为信息比特进行处理。由于第一子序列仅包括第一比特，因此译码装置可以该硬值序列作为第一子序列的译码结果。例如，译码装置确定出的第一子序列对应的硬值序列为[0 0 0 0]，该第一子序列的译码结果为[0 0 0 0]。
本申请的上述实施例中，第一子序列中仅包括第一比特，第一比特的类型为已知比特，该第一比特的取值范围与冻结比特的取值范围一致。译码装置可以将第一比特的类型作为冻结比特，得到第一位置分布序列。由于该第一位置分布序列所指示的比特的类型皆为冻结比特，因此译码装置可以根据该第一位置分布序列适配译码算法(如冻结比特对应的译码算法)，从而实现对包括已知比特的子序列的译码。由于冻结比特的比特值与软值无关，因此译码装置在根据冻结比特对应的译码算法对第一子序列进行译码时，无需对第一子序列进行软值计算，从而节省了因进行软值计算产生的开销，提高了译码效率。
实施例3
请参见图9，图9所示为本申请实施例提供的另一种极化码的译码方法的流程图，该方法中，译码装置将第一比特的类型作为目标类型，并基于目标类型对应的译码算法对第一子序列进行译码，其中第一子序列仅包括第一比特，目标类型包括PC比特或冻结比特。
S901：译码装置接收来自编码装置的消息，该消息中包括第一子序列，该第一子序列中仅包括第一比特。
其中，S901的具体实现方式与图5中S501的具体实现方式或图7中S701的具体实现方式一致，在此不再赘述。
该第一比特的取值范围可以与PC比特的取值范围一致，即取值范围为0或1；或者该第一比特的取值范围可以与冻结比特的取值范围一致，即取值范围为0。
进一步地，译码装置可以根据第一比特的取值范围，将第一比特的类型作为目标类型，并基于该目标类型对应的译码算法对第一子序列进行译码，得到该第一子序对应的硬值序列。其中硬值序列仅包括对应于第一比特的第一硬值，该目标类型包括PC比特或冻结比特。
示例性地，在比特的类型识别和硬值计算中，译码装置可以将第一比特的类型作为目标类型进行处理；在软值计算中，译码装置可以将第一比特的类型作为冻结比特进行处理；在硬值回溯中，译码装置可以将第一比特的类型作为信息比特进行处理，如图10所示。应理解的是，由于软值计算中译码装置可以将PC比特作为冻结比特进行处理，因此，在软值计算中，译码装置还可以将第一比特的类型作为PC比特。
具体地，如果第一比特的取值范围与PC比特的取值范围一致，则该目标类型为PC比特，译码装置可以执行S902和S904所示的内容；如果第一比特的取值范围与冻结比特的取值范围一致，则该目标类型为冻结比特，译码装置可以执行S903和S904所示的内容。
S902：在第一比特的取值范围与PC比特的取值范围一致时，译码装置可以将第一比特的类型作为PC比特，并根据PC比特对应的译码算法对第一子序列进行译码，得到该第一子序列对应的硬值序列。
其中，S902的具体实现方式与图5中S502的具体实现方式一致，在此不再赘述。
S903：在第一比特的取值范围与冻结比特的取值范围一致时，译码装置可以将第一比特的类型作为冻结比特，并根据冻结比特对应的译码算法对第一子序列进行译码，得到该第一子序列对应的硬值序列。
其中S903的具体实现方式与图7中S702的具体实现方式一致，在此不再赘述。
S904：译码装置从硬值序列中抽取第一硬值作为该第一子序列的译码结果。
在硬值回溯过程中，译码装置可以将第一比特的类型作为信息比特进行处理。由于第一子序列仅包括第一比特，因此译码装置可以该硬值序列作为第一子序列的译码结果。例如，译码装置确定出的第一子序列对应的硬值序列为[1 1 0 1]，该第一子序列的译码结果为[1 1 0 1]。
本申请的上述实施例中，第一子序列中仅包括第一比特，第一比特的类型为已知比特。译码装置可以将第一比特的类型作为目标类型，得到第一位置分布序列，该目标类型为PC比特或冻结比特。由于该第一位置分布序列所指示的比特的类型皆为PC比特或皆为冻结比特，因此译码装置可以根据该第一位置分布序列适配译码算法，从而实现对包括已知比特的子序列的译码。由于冻结比特或PC比特的比特值与软值无关，因此译码装置在根据目标类型对应的译码算法对第一子序列进行译码时，无需对第一子序列进行软值计算，从而节省了因进行软值计算产生的开销，提高了译码效率。
实施例4
请参见图11，图11所示为本申请实施例提供的另一种极化码的译码方法的流程图。 该方法中，译码装置根据第一比特的类型对应的译码算法对第一子序列进行译码，其中第一子序列仅包括第一比特。
S1101：译码装置接收来自编码装置的消息，该消息中包括第一子序列，该第一子序列中仅包括第一比特。
该第一比特的取值范围可以与PC比特的取值范围一致，也可以与冻结比特的取值范围一致，本申请实施例对此不作限定。其中S1101的具体实现方式与图5中S501的具体实现方式，或与图7中S701的具体实现方式，或与图9中S901的具体实现方式一致，在此不再赘述。
S1102：译码装置根据已知比特对应的第一译码算法，对第一子序列进行译码，得到第一子序列对应的硬值序列，该硬值序列中仅包括对应于第一比特的第一硬值。
该已知比特对应的第一译码算法可以用于对第一比特进行译码。由于第一子序列仅包括第一比特，因此该已知比特对应的第一译码算法还可以用于对第一子序列进行译码。
示例性地，该已知比特对应的第一译码算法可以用于确定第一比特的比特值。例如，已知比特对应的位置分布序列包括100和101，其中100表示比特值为0的已知比特，101表示比特值为1的已知比特。译码装置可以根据第一子序列对应的位置分布序列，以及已知比特对应的位置分布序列，确定第一子序列对应的硬值序列。例如，第一子序列对应的位置分布序列为[100 101 101 100]，该第一子序列对应的硬值序列为[0 1 1 0]。该已知比特对应的第一译码算法还可以用于表征对获取信息比特的比特值的贡献。例如，根据已知比特的译码结果以及该已知比特的比特值进行硬值判决。
在不作特殊说明的情况下，下文中该已知比特对应的第一译码算法可以称为第一比特的类型对应的第一译码算法，或者称为第一比特的类型对应的第一译码算法，或者称为第一译码算法，本申请实施例对此不作限定。
S1103：译码装置从硬值序列中抽取第一硬值作为该第一子序列的译码结果。
在硬值回溯过程中，译码装置根据第一子序列对应的位置分布序列，从硬值序列中抽取所有第一比特的第一硬值作为该第一子序列的译码结果。
在本申请的上述实施例中，第一子序列中仅包括第一比特，第一比特的类型为已知比特。译码装置可以根据已知比特对应的译码算法对该第一子序列进行译码。在译码过程中，无需进行软值计算，实现了对包括已知比特的子序列的译码，减少了开销，可以提高译码效率。
下面对第二子序列进行译码的具体流程进行介绍，该第二子序列包括第一比特和第二比特，第一比特的类型为已知比特，第二比特的类型为PC比特，冻结比特或信息比特中的至少一种。
实施例5
请参见图12，图12所示为本申请实施例提供的另一种极化码的译码方法的流程图。该方法中，译码装置将第一比特的类型作为PC比特，基于PC比特对应的译码算法对第一比特进行译码，并基于第二比特的类型对应的第二译码算法对第二比特进行译码，从而实现对第二子序列的译码。其中第二子序列包括第一比特和第二比特。
S1201：译码装置接收来自编码装置的消息，该消息中包括第二子序列，该第二子序列中包括第一比特和第二比特，该第一比特的取值范围与PC比特的取值范围一致。
译码装置接收来自编码装置的消息，该消息可以包括第二子序列，该第二子序列中包 括第一比特和第二比特。例如，第二子序列包括8个比特，该8个比特的类型依次为[已知比特冻结比特PC比特信息比特信息比特已知比特已知比特信息比特]。该消息可以是上行控制消息，也可以是下行控制消息。例如在编码装置为终端300，译码装置为网络装置200时，该消息可以是上行控制消息。再例如，在编码装置为第一网络装置201，译码装置为第二网络装置202时，该消息可以是下行控制消息。在该消息为上行控制消息时，该上行控制消息中包括第一字段和第二字段，该第一字段用于指示第二子序列中是否包括第一比特，该第二字段用于指示第一比特在该第二子序列中的位置。或者，在该消息为下行控制消息时，该下行控制消息中包括第三字段和第四字段，该第三字段用于指示第二子序列中是否包括第一比特，该第四字段用于指示第一比特在该第二子序列中的位置。其中，第一字段和/或第二字段可以是上行控制消息中预定义的字段或预留字段，第三字段和/或第四字段可以是下行控制消息中预定义的字段或预留字段。
第一比特的取值范围与PC比特的取值范围一致，是指译码后第一比特的可能取值与译码后PC比特的可能取值一致。例如，译码后PC比特的可能取值为0或1，译码后第一比特的可能取值为0或1。再例如，第一比特携带信息时，该第一比特的可能取值为0或1。其中，第一比特的可能取值可以由已知比特对应的位置分布序列确定的，例如，已知比特的位置分布序列可以包括100和102，其中100表示已知比特且该已知比特的比特值为0，101表示已知比特且该已知比特的比特值为0。PC比特的可能取值可以由上一个子序列的译码结果确定的，其具体实现过程可参考现有技术。
S1202：译码装置将第一比特的类型作为PC比特，得到第一位置分布序列。
第一比特的取值范围与PC比特的取值范围一致，根据表1中不同类型的比特的特性，译码装置可以将第一比特的类型作为PC比特进行处理。例如，在比特的类型识别和硬值计算中，译码装置可以将第一比特的类型作为PC比特进行处理；在软值计算中，译码装置可以将第一比特的类型作为冻结比特进行处理；在硬值回溯中，译码装置可以将第一比特的类型作为信息比特进行处理，如图6所示。其具体实施过程可以参见图5中S502中的内容，在此不再赘述。
具体地，译码装置可以根据上行控制消息中的第二字段或下行控制消息中的第四字段，将第二子序列中包括的第一比特的类型映射为PC比特(即将已知比特映射为PC比特)，得到第一位置分布序列。或者，译码装置可以根据第二子序列对应的位置分布序列，确定第二子序列中各个比特的类型，基于该第二子序列中各个比特的类型将该第二子序列中类型为已知比特的第一比特的类型映射为PC比特。例如，000、110以及111表示冻结比特，001和010表示信息比特，011表示PC比特，100表示取值为0的已知比特，101表示取值为1的已知比特。第二子序列对应的位置分布序列为[011 101 001 010]，译码装置可以确定该第二子序列中各个比特的类型依次为[PC比特已知比特信息比特信息比特]，将已知比特映射为PC比特，得到第一位置分布序列为[011 011 001 010]。
S1203：译码装置根据第一位置分布序列，确定第三译码算法，第三译码算法包括第一译码算法和第二译码算法。
该第三译码算法可以用于对第二子序列进行译码，得到该第二子序列对应的硬值序列。在具体实施时，该第三译码算法可以包括软值计算和硬值计算，或者包括硬值计算。进一步地，该第三译码算法还可以包括第一译码算法和第二译码算法，也即是说该第三译码算法可以实现第一译码算法的全部功能，以及实现第二译码算法的全部功能。其中第一译码 算法可以用于对第二子序列中的第一比特进行译码，例如，译码装置将第一比特的类型作为PC比特进行处理时，该第一译码算法为PC比特对应的译码算法。第二译码算法可以用于对第二子序列中的第二比特进行译码，例如第二比特的类型仅包括冻结比特时，该第二译码算法为冻结比特对应的译码算法。
在一种可能的实现方式中，译码装置可以根据第一位置分布序列，分别确定第一译码算法和第二译码算法。例如，译码装置可以根据第一位置分布序列以及第二子序列对应的位置的分布序列，确定第一比特的数量或第一比特在第二子序列中的位置等信息，并基于第一比特的数量或第一比特在第二子序列中的位置等信息，确定对第一比特进行译码的第一译码算法。
译码装置可以根据第一位置分布序列确定该第二子序列所包括的比特的类型，并根据该第二子序列所包括的比特的类型的组合方式和/或排列方式，确定该第三译码算法。以组合方式为例，不同组合方式可以对应同一种译码算法。例如，组合方式1为[冻结比特冻结比特PC比特PC比特]，组合方式1对应的译码算法为译码算法1；组合方式2为[信息比特信息比特PC比特PC比特]，组合方式2对应的译码算法为译码算法2；组合方式3为[PC比特PC比特冻结比特信息比特]，组合方式3对应的译码算法为译码算法3；组合方式4为[信息比特信息比特PC比特冻结比特]，组合方式4对应的译码算法为译码算法2；在此不再一一列举。其中，该第三译码算法可以为预先根据子序列中比特的数量、子序中比特的类型的组合方式或子序列中比特的类型的排列方式中的至少一种，推算并实验得出的收益最佳的简易译码算法。
进一步地，译码装置可以根据组合方式与译码算法对应表，查找该第一位置分布序列所指示的比特的类型的组合方式所对应的第三译码算法；或者根据该第一位置分布序列所指示的比特的类型的组合方式的标识号，查找该第一位置分布序列所指示的比特的类型的组合方式所对应的第三译码算法等。
S1204：译码装置根据第三译码算法对第二子序列进行译码，得到该第二子序列对应的硬值序列，该硬值序列中包括对应于第一比特的第一硬值和对应于第二比特的第二硬值。
在一种示例中，当第二比特的类型中不包括信息比特时，第三译码算法可以不包括软值计算。意味着译码装置无需对第二子序进行软值计算，可以节省因软值计算产生的开销，从而提高译码效率。具体地，如果第二比特的类型包括冻结比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，冻结比特的比特值以及已知比特的比特值，确定第二子序列对应的硬值序列。如果第二比特的类型包括PC比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，PC比特的比特值以及已知比特的比特值，确定第二子序列对应的硬值序列。如果第二比特的类型包括冻结比特和PC比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，PC比特的比特值，冻结比特的比特值以及已知比特的比特值，确定第二子序列对应的硬值序列。
以第二比特的类型包括冻结比特为例，000、110以及111表示冻结比特，001和010表示信息比特，011表示PC比特，100表示取值为0的已知比特，101表示取值为1的已知比特。第二子序列对应的位置分布序列为[111 100 101 000]，第一位置分布序列为[111 011 011 000]。译码装置可以根据第一位置分布序列，按照PC比特对应的译码算法和冻结比特对应的译码算法，得到第二子序列中比特的硬值依次为[0 0 0 0]。由于已知比特的硬值是按照PC比特对应的译码算法获取的，可能存在误差，因此译码装置可以根据第二子序列对 应的位置分布序列确定比特1和比特2为已知比特，且比特1的比特值为0，比特2的比特值为1，结合根据冻结比特对应的译码算法得出的硬值，可以确定第二子序列对应的硬值序列为[0 0 1 0]。
在另一种示例中，当第二比特的类型中包括信息比特时，第三译码算法包括软值计算。意味着译码装置需要对第二子序进行软值计算和硬值计算。具体地，如果第二比特的类型仅包括信息比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，第二子序列中每个比特的软值以及已知比特的比特值，通过最大似然估计算法确定第二子序列对应的硬值序列。如果第二比特的类型包括信息比特和冻结比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，第二子序列中每个比特的软值，已知比特的比特值以及冻结比特的比特值，通过最大似然估计算法确定第二子序列对应的硬值序列。如果第二比特的类型包括信息比特和PC比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，第二子序列中每个比特的软值，已知比特的比特值以及PC比特的比特值，通过最大似然估计算法确定第二子序列对应的硬值序列。如果第二比特的类型包括信息比特、PC比特和冻结比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，第二子序列中每个比特的软值，已知比特的比特值，PC比特的比特值以及冻结比特的比特值，通过最大似然估计算法确定第二子序列对应的硬值序列。
进一步地，译码装置可以根据硬值序列，确定第二子序列的译码结果。具体地，如果第二比特的类型包括信息比特，则译码装置执行S1205所示的内容；如果第二比特的类型不包括信息比特，则译码装置执行S1206所示的内容。
S1205：在第二比特的类型包括信息比特时，译码装置从硬值序列中抽取第一硬值和第三硬值作为第二子序列的译码结果，该第三硬值为对应于第二比特中的信息比特的硬值。
译码装置可以将第一比特的类型映射为信息比特，得到映射后的位置分布序列，并基于该映射后的位置分布序列，从硬值序列中抽取第一硬值和第三硬值作为第二子序列的译码结果。
例如，000、110以及111表示冻结比特，001和010表示信息比特，011表示PC比特，100表示取值为0的已知比特，101表示取值为1的已知比特。第二子序列对应的位置分布序列为[100 011 001 001]，第二子序对应的硬值序列为[0 1 1 1]。译码装置可以将第一比特的类型映射为信息比特，得到映射后的位置分布序列为[001 011 001 001]。译码装置基于该映射后的位置分布序列，从硬值序列中抽取所有信息比特的硬值，得到[0 1 1]，该译码结果为[0 1 1]。其中第二子序列中第一比特的译码结果为[0]，第二子序列中信息比特的译码结果为[1 1]。
S1206：在第二比特的类型不包括信息比特时，译码装置从硬值序列中抽取第一硬值作为第二子序列的译码结果。
译码装置可以将第一比特的类型映射为信息比特，得到映射后的位置分布序列，并基于该映射后的位置分布序列，从硬值序列中抽取第一硬值作为第二子序列的译码结果。
本申请的上述实施例中，第二子序列中包括第一比特和第二比特，第一比特的类型为已知比特，该第一比特的取值范围与PC比特的取值范围一致，第二比特的类型包括PC比特、冻结比特或信息比特中的至少一种。译码装置可以将第一比特的类型作为PC比特，基于PC比特对应的译码算法对第一比特进行译码，并基于该第二比特的类型对应的译码 算法对第二比特进行译码，从而实现对包括已知比特的子序列进行译码。在第二比特的类型不包括信息比特时，译码装置无需对第二子序列进行软值计算，从而节省了因进行软值计算产生的开销，提高了译码效率。
实施例6
请参见图13，图13所示为本申请实施例提供的另一种极化码的译码方法的流程图。该方法中，译码装置将第一比特的类型作为冻结比特，基于冻结比特对应的译码算法对第一比特进行译码，并基于第二比特的类型对应的第二译码算法对第二比特进行译码，从而实现对第二子序列的译码。其中第二子序列包括第一比特和第二比特。
S1301：译码装置接收来自编码装置的消息，该消息中包括第二子序列，该第二子序列中包括第一比特和第二比特，该第一比特的取值范围与冻结比特的取值范围一致。
第一比特的取值范围与冻结比特的取值范围一致，是指译码后第一比特的可能取值与译码后冻结比特的可能取值一致。例如，冻结比特的比特值固定为0，第一比特的比特值也固定为0。再例如，第一比特没有携带信息时，该第一比特的比特值可以固定为0。其中，第一比特的可能取值可以由已知比特对应的位置分布序列确定，例如，已知比特的位置分布序列可以仅包括100，该100表示已知比特且该已知比特的比特值为0。
其中，S1301的具体实现方式与图12中S1201的具体实现方法一致，在此不再赘述。
S1302：译码装置将第一比特的类型作为冻结比特，得到第一位置分布序列。
第一比特的取值范围与冻结比特的取值范围一致，根据表2中不同类型的比特的特性，译码装置可以将第一比特的类型作为冻结比特进行处理。例如，在比特的类型识别和硬值计算中，译码装置可以将第一比特的类型作为冻结比特进行处理；在软值计算中，译码装置可以将第一比特的类型作为冻结比特进行处理；在硬值回溯中，译码装置可以将第一比特的类型作为信息比特进行处理，如图8所示。其具体实施过程可以参见图7中S702中的内容，在此不再赘述。
具体地，译码装置可以根据上行控制消息中的第二字段或下行控制消息中的第四字段，将第二子序列中包括的第一比特的类型映射为冻结比特(即将已知比特映射为冻结比特)，得到第一位置分布序列。或者，译码装置可以根据第二子序列对应的位置分布序列，确定第二子序列中各个比特的类型，基于该第二子序列中各个比特的类型将该第二子序列中类型为已知比特的第一比特的类型映射为冻结比特。例如，000、110以及111表示冻结比特，001和010表示信息比特，011表示PC比特，100表示取值为0的已知比特，101表示取值为1的已知比特。第二子序列对应的位置分布序列为[011 101 001 010]，译码装置可以确定该第二子序列中各个比特的类型依次为[PC比特已知比特信息比特信息比特]，将已知比特映射为冻结比特，得到第一位置分布序列为[011 000 001 010]。
S1303：译码装置根据第一位置分布序列，确定第三译码算法，第三译码算法包括第一译码算法和第二译码算法。
该第三译码算法用于对第二子序列进行译码，得到该第二子序列对应的硬值序列。该第三译码算法可以包括软值计算和硬值计算，或者包括硬值计算。进一步地，该第三译码算法还可以包括第一译码算法和第二译码算法，也即是说该第三译码算法可以实现第一译码算法的全部功能，以及实现第二译码算法的全部功能。其中第一译码算法可以用于对第二子序列中的第一比特进行译码，例如，译码装置将第一比特的类型作为冻结比特进行处理时，该第一译码算法为冻结比特对应的译码算法。第二译码算法可以用于对第二子序列 中的第二比特进行译码，例如第二比特的类型仅包括PC比特时，该第二译码算法为PC比特对应的算法。
其中S1303的具体实现方式与图12中S1202的具体实现方式一致，在此不再赘述。
S1304：译码装置根据第三译码算法对第一子序列进行译码，得到该第一子序列对应的硬值序列，该硬值序列中包括对应于第一比特的第一硬值和对应于第二比特的第二硬值。
在一种示例中，当第二比特的类型中不包括信息比特时，第三译码算法可以不包括软值计算。意味着译码装置无需对第二子序进行软值计算，可以节省因软值计算产生的开销，从而提高译码效率。具体地，如果第二比特的类型包括冻结比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，冻结比特的比特值以及已知比特的比特值，确定第二子序列对应的硬值序列。如果第二比特的类型包括PC比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，PC比特的比特值以及已知比特的比特值，确定第二子序列对应的硬值序列。如果第二比特的类型包括冻结比特和PC比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，PC比特的比特值，冻结比特的比特值以及已知比特的比特值，确定第二子序列对应的硬值序列。
在另一种示例中，当第二比特的类型中包括信息比特时，第三译码算法包括软值计算。意味着译码装置需要对第二子序进行软值计算和硬值计算。具体地，如果第二比特的类型仅包括信息比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，第二子序列中每个比特的软值以及已知比特的比特值，通过最大似然估计算法确定第二子序列对应的硬值序列。如果第二比特的类型包括信息比特和冻结比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，第二子序列中每个比特的软值，已知比特的比特值以及冻结比特的比特值，通过最大似然估计算法确定第二子序列对应的硬值序列。如果第二比特的类型包括信息比特和PC比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，第二子序列中每个比特的软值，已知比特的比特值以及PC比特的比特值，通过最大似然估计算法确定第二子序列对应的硬值序列。如果第二比特的类型包括信息比特、PC比特和冻结比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，第二子序列中每个比特的软值，已知比特的比特值，PC比特的比特值以及冻结比特的比特值，通过最大似然估计算法确定第二子序列对应的硬值序列。
进一步地，译码装置可以根据硬值序列，确定第二子序列的译码结果。具体地，如果第二比特的类型包括信息比特，则译码装置执行S1305所示的内容；如果第二比特的类型不包括信息比特，则译码装置执行S1306所示的内容。
S1305：在第二比特的类型包括信息比特时，译码装置从硬值序列中抽取第一硬值和第三硬值作为第二子序列的译码结果，该第三硬值为对应于第二比特中的信息比特的硬值。
译码装置可以将第一比特的类型映射为信息比特，得到映射后的位置分布序列，并基于该映射后的位置分布序列，从硬值序列中抽取第一硬值和第三硬值作为第二子序列的译码结果。
S1306：在第二比特的类型不包括信息比特时，译码装置从硬值序列中抽取第一硬值作为第二子序列的译码结果。
译码装置可以将第一比特的类型映射为信息比特，得到映射后的位置分布序列，并基于该映射后的位置分布序列，从硬值序列中抽取第一硬值作为第二子序列的译码结果。
本申请的上述实施例中，第二子序列中包括第一比特和第二比特，第一比特的类型为已知比特，该第一比特的取值范围与冻结比特的取值范围一致，第二比特的类型包括PC比特、冻结比特或信息比特中的至少一种。译码装置可以将第一比特的类型作为冻结比特，基于冻结比特对应的译码算法对第一比特进行译码，并基于该第二比特的类型对应的译码算法对第二比特进行译码，从而实现对包括已知比特的子序列进行译码。在第二比特的类型不包括信息比特时，译码装置无需对第二子序列进行软值计算，从而节省了因进行软值计算产生的开销，提高了译码效率。
实施例7
请参见图14，图14所示为本申请实施例提供的另一种极化码的译码方法的流程图。该方法中，译码装置将第一比特的类型作为目标类型，基于目标类型对应的译码算法对第一比特进行译码，并基于第二比特的类型对应的第二译码算法对第二比特进行译码，从而实现对第二子序列的译码。其中第二子序列包括第一比特和第二比特，该目标类型包括PC比特或冻结比特。
S1401：译码装置接收来自编码装置的消息，该消息中包括第二子序列，该第二子序列中包括第一比特和第二比特。
其中，S1401的具体实现方式与图12中S1201的具体实现方式或图13中S1301的具体实现方式一致，在此不再赘述。
该第一比特的取值范围可以与PC比特的取值范围一致，即取值范围为0或1；或者该第一比特的取值范围可以与冻结比特的取值范围一致，即取值范围为0。
进一步地，译码装置可以根据第一比特的取值范围，将第一比特的类型作为目标类型，并基于该目标类型对应的第一译码算法对第一比特进行译码，以及基于第二比特的类型对应的第二译码算法对第二比特进行译码。其中该目标类型包括PC比特或冻结比特。
示例性地，在比特的类型识别和硬值计算中，译码装置可以将第一比特的类型作为目标类型进行处理；在软值计算中，译码装置可以将第一比特的类型作为冻结比特进行处理；在硬值回溯中，译码装置可以将第一比特的类型作为信息比特进行处理，如图10所示。应理解的是，由于软值计算中译码装置可以将PC比特作为冻结比特进行处理，因此，在软值计算中，译码装置还可以将第一比特的类型作为PC比特。
具体地，如果第一比特的取值范围与PC比特的取值范围一致，则该目标类型为PC比特，译码装置可以执行S1402和S1404所示的内容；如果第一比特的取值范围与冻结比特的取值范围一致，则该目标类型为冻结比特，译码装置可以执行S1403和S1404所示的内容。
S1402：在第一比特的取值范围与PC比特的取值范围一致时，译码装置可以将第一比特的类型作为PC比特，得到第一位置分布序列。
第一比特的取值范围与PC比特的取值范围一致，根据表1中不同类型的比特的特性，译码装置可以将第一比特的类型作为PC比特进行处理。例如，在比特的类型识别和硬值计算中，译码装置可以将第一比特的类型作为PC比特进行处理；在软值计算中，译码装置可以将第一比特的类型作为冻结比特进行处理；在硬值回溯中，译码装置可以将第一比特的类型作为信息比特进行处理，如图6所示。其具体实施过程可以参见图12中S1202中的内容，在此不再赘述。
S1403：在第一比特的取值范围与冻结比特的取值范围一致时，译码装置可以将第一 比特的类型作为冻结比特，得到第一位置分布序列。
第一比特的取值范围与冻结比特的取值范围一致，根据表1中不同类型的比特的特性，译码装置可以将第一比特的类型作为冻结比特进行处理。例如，在比特的类型识别和硬值计算中，译码装置可以将第一比特的类型作为冻结比特进行处理；在软值计算中，译码装置可以将第一比特的类型作为冻结比特进行处理；在硬值回溯中，译码装置可以将第一比特的类型作为信息比特进行处理，如图8所示。其具体实施过程可以参见图13中S1302中的内容，在此不再赘述。
S1404：译码装置根据第一位置分布序列，确定第三译码算法，该第三译码算法包括第一译码算法和第二译码算法。
其中S1404的具体实现过程与图12中S1203所示的具体实现过程，或与图13中S1303的所示具体实现过程一致，在此不再赘述。
S1405：译码装置根据第三译码算法对第二子序列进行译码，得到该第二子序列对应的硬值序列，该硬值序列中包括对应于第一比特的第一硬值和对应于第二比特的第二硬值。
在一种示例中，当第二比特的类型中不包括信息比特时，第三译码算法可以不包括软值计算。意味着译码装置无需对第二子序进行软值计算，可以节省因软值计算产生的开销，从而提高译码效率。具体地，如果第二比特的类型包括冻结比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，冻结比特的比特值以及已知比特的比特值，确定第二子序列对应的硬值序列。如果第二比特的类型包括PC比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，PC比特的比特值以及已知比特的比特值，确定第二子序列对应的硬值序列。如果第二比特的类型包括冻结比特和PC比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，PC比特的比特值，冻结比特的比特值以及已知比特的比特值，确定第二子序列对应的硬值序列。
在另一种示例中，当第二比特的类型中包括信息比特时，第三译码算法包括软值计算。意味着译码装置需要对第二子序进行软值计算和硬值计算。具体地，如果第二比特的类型仅包括信息比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，第二子序列中每个比特的软值以及已知比特的比特值，通过最大似然估计算法确定第二子序列对应的硬值序列。如果第二比特的类型包括信息比特和冻结比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，第二子序列中每个比特的软值，已知比特的比特值以及冻结比特的比特值，通过最大似然估计算法确定第二子序列对应的硬值序列。如果第二比特的类型包括信息比特和PC比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，第二子序列中每个比特的软值，已知比特的比特值以及PC比特的比特值，通过最大似然估计算法确定第二子序列对应的硬值序列。如果第二比特的类型包括信息比特、PC比特和冻结比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，第二子序列中每个比特的软值，已知比特的比特值，PC比特的比特值以及冻结比特的比特值，通过最大似然估计算法确定第二子序列对应的硬值序列。
进一步地，译码装置可以根据硬值序列，确定第二子序列的译码结果。具体地，如果第二比特的类型包括信息比特，则译码装置执行S1406所示的内容；如果第二比特的二类型不包括信息比特，则译码装置执行S1407所示的内容。
S1406：在第二比特的类型包括信息比特时，译码装置从硬值序列中抽取第一硬值和 第三硬值作为第二子序列的译码结果，该第三硬值为对应于第二比特中的信息比特的硬值。
译码装置可以将第一比特的类型映射为信息比特，得到映射后的位置分布序列，并基于该映射后的位置分布序列，从硬值序列中抽取第一硬值和第三硬值作为第二子序列的译码结果。
S1407：在第二比特的类型不包括信息比特时，译码装置从硬值序列中抽取第一硬值作为第二子序列的译码结果。
译码装置可以将第一比特的类型映射为信息比特，得到映射后的位置分布序列，并基于该映射后的位置分布序列，从硬值序列中抽取第一硬值作为第二子序列的译码结果。
本申请的上述实施例中，第二子序列中包括第一比特和第二比特，第一比特的类型为已知比特，第二比特的类型包括PC比特、冻结比特或信息比特中的至少一种。译码装置可以将第一比特的类型作为目标类型，基于目标类型对应的译码算法对第一比特进行译码，并基于该第二比特的类型对应的译码算法对第二比特进行译码，从而实现对包括已知比特的子序列进行译码。在第二比特的类型不包括信息比特时，译码装置无需对第二子序列进行软值计算，从而节省了因进行软值计算产生的开销，提高了译码效率。
实施例8
请参见图15，图15所示为本申请实施例提供的另一种极化码的译码方法的流程图。该方法中，译码装置可以根据已知比特对应的译码算法对第一比特进行译码，并根据第二比特的类型对应的第二比特进行译码，从而实现对第二子序列的译码。其中第二子序列包括第一比特和第二比特。
S1501：译码装置接收来自编码装置的消息，该消息中包括第二子序列，该第二子序列中包括第一比特和第二比特。
该第一比特的取值范围可以与PC比特的取值范围一致，也可以与冻结比特的取值范围一致，本申请实施例对此不作限定。其中S1501的具体实现方式与图12中S1201的具体实现方式，或与图13中S1301的具体实现方式，或与图14中S1401的具体实现方式一致，在此不再赘述。
S1502：译码装置根据已知比特对应的第一译码算法以及第二比特类型对应的第二译码算法，分别对第二子序列中的第一比特和第二比特进行译码，得到该第二子序列对应的硬值序列，该硬值序列中包括对应于第一比特的第一硬值和对应于第二比特的第二硬值。
其中，第一译码算法可以用于对第二子序列中的第一比特进行译码，第二译码算法可以用于对第二子序列中的第二比特进行译码。第三译码算法可以用于对第二子序列进行译码，得到该第二子序列对应的硬值序列。在具体实施时，该第三译码算法可以包括软值计算和硬值计算，或者包括硬值计算。进一步地，该第三译码算法还可以包括第一译码算法和第二译码算法，也即是说该第三译码算法可以实现第一译码算法的全部功能，以及实现第二译码算法的全部功能。
在一种示例中，当第二比特的类型中不包括信息比特时，第三译码算法可以不包括软值计算。意味着译码装置无需对第二子序进行软值计算，可以节省因软值计算产生的开销，从而提高译码效率。具体地，如果第二比特的类型包括冻结比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，冻结比特的比特值以及已知比特的比特值，确定第二子序列对应的硬值序列。如果第二比特的类型包括PC比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，PC比特的比特值以及已知 比特的比特值，确定第二子序列对应的硬值序列。如果第二比特的类型包括冻结比特和PC比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，PC比特的比特值，冻结比特的比特值以及已知比特的比特值，确定第二子序列对应的硬值序列。
以第二比特的类型包括冻结比特为例，000、110以及111表示冻结比特，001和010表示信息比特，011表示PC比特，100表示取值为0的已知比特，101表示取值为1的已知比特。第二子序列对应的位置分布序列为[111 100 101 000]，第一位置分布序列为[111 011 011 000]。译码装置可以根据第一位置分布序列，按照PC比特对应的译码算法和冻结比特对应的译码算法，得到第二子序列中比特的硬值依次为[0 0 0 0]。由于已知比特的硬值是按照PC比特对应的译码算法获取的，可能存在误差，因此译码装置可以根据第二子序列对应的位置分布序列确定比特1和比特2为已知比特，且比特1的比特值为0，比特2的比特值为1，结合根据冻结比特对应的译码算法得出的硬值，可以确定第二子序列对应的硬值序列为[0 0 1 0]。
在另一种示例中，当第二比特的类型中包括信息比特时，第三译码算法包括软值计算。意味着译码装置需要对第二子序进行软值计算和硬值计算。具体地，如果第二比特的类型仅包括信息比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，第二子序列中每个比特的软值以及已知比特的比特值，通过最大似然估计算法确定第二子序列对应的硬值序列。如果第二比特的类型包括信息比特和冻结比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，第二子序列中每个比特的软值，已知比特的比特值以及冻结比特的比特值，通过最大似然估计算法确定第二子序列对应的硬值序列。如果第二比特的类型包括信息比特和PC比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，第二子序列中每个比特的软值，已知比特的比特值以及PC比特的比特值，通过最大似然估计算法确定第二子序列对应的硬值序列。如果第二比特的类型包括信息比特、PC比特和冻结比特，则译码装置可以根据第二子序列对应的位置分布序列，第一位置分布序列，第二子序列中每个比特的软值，已知比特的比特值，PC比特的比特值以及冻结比特的比特值，通过最大似然估计算法确定第二子序列对应的硬值序列。
进一步地，译码装置可以根据硬值序列，确定第二子序列的译码结果。具体地，如果第二比特的类型包括信息比特，则译码装置执行S1205所示的内容；如果第二比特的二类型不包括信息比特，则译码装置执行S1206所示的内容。
S1503：在第二比特的类型包括信息比特时，译码装置从硬值序列中抽取第一硬值和第三硬值作为第二子序列的译码结果，该第三硬值为对应于第二比特中的信息比特的硬值。
译码装置可以根据第二子序列对应的位置分布序列，从硬值序列中抽取所有已知比特的第一硬值以及所有信息比特的第三硬值，作为该第二子序列的译码结果。
S1504：在第二比特的类型不包括信息比特时，译码装置从硬值序列中抽取第一硬值作为第二子序列的译码结果。
译码装置可以根据第二子序列对应的位置分布序列，从硬值序列中抽取所有已知比特的第一硬值作为该第二子序列的译码结果。
在本申请的上述实施例中，第二子序列中包括第一比特和第二比特，第一比特的类型为已知比特。译码装置可以根据已知比特对应的译码算法对该第一比特进行译码，并根据第二比特的类型对应的第二译码算法对第二比特进行译码，从而实现对包括已知比特的子 序列的译码。在译码过程中，如果第二比特的类型不包括信息比特，则无需进行软值计算，可以减少开销，提高译码效率。
下面对图11或图15所示的译码方法对应的译码装置进行介绍。请参见图16，图16所示为本申请实施例提供的一种译码装置的结构示意图，该译码装置可以用以实现图11或图15所示的流程。译码装置1600可以应用于图1A或图1B所示的通信系统100。该译码装置1600可以是网络装置101或网络装置101中的至少一个芯片，也可以是终端102或终端102中的至少一个芯片。如图16所示，该译码装置1600包括点灯计算单元1601，路径分裂单元1602，路径计算单元1603以及似然概率计算单元1604。
点灯计算单元1601，用于对点灯序列进行点灯计算，并将点灯计算结果发送给似然概率计算单元1604。其中，点灯序列是指包括已知比特的子序列，例如图11中的第一子序列或图15中的第二子序列。点灯计算是指根据已知比特对应的译码算法对第一比特进行译码。该点灯计算单元1601可以执行图11中的S1102所示的内容或图15中的S1502所示的部分内容。
路径分裂单元1602，用于根据子序列中比特的类型的组合方式对应的译码算法，确定该子序列中所有信息比特的比特值，并将该子序列中所有信息比特的比特值发送给路径计算单元1603和似然概率计算单元1604。例如，子序列包括N个比特，N为大于或等于1的整数。该N个比特最多可以分裂出2 N个译码结果，在实际应用时，路径分裂单元1602可以根据不同比特的类型的组合方式对应的译码算法确定2 N个译码结果、以及该2 N个译码结果的可靠性，并根据该2 N个译码结果的可靠性保留其中可靠性好的一个或多个译码结果，然后根据这一个或多个译码结果确定N个比特中所有信息比特的比特值。
路径计算单元1603，用于根据上一个子序列的路径度量以及该子序列中所有信息比特的比特值，确定N个比特的路径分支度量以及用于对下一个子序列进行译码的路径分支度量。路径分裂单元1602遍历得到的信息比特的比特值和其对应的最大似然概率可能存在偏差，例如遍历结果为0，但是最大似然概率的符号为负。在这种情况下，路径计算单元1603会将N个比特内存在偏差的信息比特的最大似然概率进行绝对值累加，得到当前N个比特的路径分支度量，多次译码的路径分支度量累加得到当前路径(不同的路径间的信息比特的遍历取值不同，路径分支度量也不同)累加的路径度量。并将不同路径累加的路径度量进行排序，保留最好(例如路径度量值最小)的一条或多条路径的路径度量用于对下一个子序列进行译码。
其中，路径分支度量和路径度量用于表示译码结果可靠性，其值越大，表示译码结果越不可靠。
似然概率计算单元1604，用于确定N个比特中每个比特的比特值。已知比特的比特值由点灯计算单元1601获得，信息比特的比特值由路径分裂计算单元1602、路径计算单元1603以及似然概率计算单元1604获得，冻结比特的比特值固定为0，PC比特的比特值根据上一个子序列中信息比特的比特值位移累加得到。N个比特中每个比特的比特值还可以用于下一个子序列中PC比特的比特值的确定。
其中，路径分裂单元1602、路径计算单元1603或似然计算单元1604中的一项或多项用于执行S1102～S1103所示的流程或执行S1502～S1504所示的流程。例如，第二比特的类型包括信息比特，则路径分裂单元1602、路径计算单元1603以及似然计算单元1604用于 执行S1502所示的流程。如果第二比特的类型不包括信息比特，则似然计算单元1604用于执行S1102所示的流程。
举例而言，子序列为[比特0比特1比特2比特3]，子序列对应的位置分布序列为[000 001 001 100]。000、110以及111表示冻结比特，001和010表示信息比特，011表示PC比特，100表示取值为0的已知比特，101表示取值为1的已知比特。4个比特的最大似然概率依次为a，b，c，d(b，c均为正数)。4个比特的类型依次为冻结比特、信息比特、信息比特和已知比特。点灯计算单元1601确定比特3的取值为0，似然概率计算单元1604确定比特0的取值为0。路径分裂单元1602对比特1和比特2这两个信息比特的取值进行遍历，得到该2个比特的四个译码结果，该四个译码结果依次为0000、0010、0100以及0110。路径计算单元1603，将这四个译码结果与最大似然概率b，c进行比对得到4个比特的路径分支度量分别为0、c、b以及b+c，可知译码可靠度排序为0000>0010>0100>0110。似然概率计算单元1604得到的最好的路径为0000，并根据该路径可以确定比特1的取值为0，比特2的取值为0，结合前面比特0和比特3的取值，从而可以得到该4个比特的取值依次为0，0，0，0。进一步地，路径计算单元1603保留最好的一条(例如译码结果为0000的路径)或者多条路径用于下一个子序列的译码。
如图17所示为本申请实施例提供的通信装置1700，用于实现上述方法中译码装置功能。该通信装置1700包括接收机1701和译码器1702。该通信装置1700可以实现前述实施例1～实施例8所述的方法。
作为一个示例，接收机1701，用于接收来自编码装置的消息，消息中包括待译码的子序列，子序列包括第一比特，第一比特的类型为已知比特；
译码器1702，用于将第一比特的类型作为目标类型，并根据目标类型对应的第一译码算法对第一比特进行译码，目标类型包括奇偶校验比特或冻结比特。
可选地，子序列还包括第二比特，第二比特的类型包括冻结比特、奇偶校验比特或信息比特中的至少一种，译码器1702，进一步用于：根据第二比特的类型对应的第二译码算法对第二比特进行译码。
可选地，消息为上行控制消息，或下行控制消息。
可选地，上行控制消息中包括第一字段和第二字段，第一字段用于指示子序列中是否包括第一比特，第二字段用于指示第一比特在子序列中的位置。
可选地，下行控制消息中包括第三字段和第四字段，第三字段用于指示子序列中是否包括第一比特，第四字段用于指示第一比特在子序列中的位置。
可选地，该译码器1702，具体用于：在第一比特的取值范围与奇偶校验比特的取值范围一致时，将第一比特的类型作为奇偶校验比特；或者，在第一比特的取值范围与冻结比特的取值范围一致时，将第一比特的类型作为冻结比特。
可选地，该译码器1702，具体用于：将第一比特的类型映射为目标类型，得到位置分布序列，位置分布序列用于表征子序列中各个比特的类型；根据位置分布序列，分别确定第一译码算法和第二译码算法；根据第三译码算法对子序列进行译码，第三译码算法包括第一译码算法和第二译码算法。
可选地，在第二比特的类型中不包括信息比特时，第三译码算法不包括软值计算，软值计算用于确定子序列中各个比特的比特值为0或1的似然概率。
可选地，在第二比特的类型中包括信息比特时，第三译码算法包括软值计算，软值计 算用于确定子序列中各个比特的比特值为0或1的似然概率。
可选地，在第二比特的类型中不包括信息比特时，译码器1702，进一步用于：根据第三译码算法对子序列进行译码，得到硬值序列，硬值序列包括对应于第一比特的第一硬值，以及对应于第二比特的第二硬值；从硬值序列中抽取第一硬值作为译码结果。
可选地，在第二比特的类型中包括信息比特时，译码器1702，进一步用于：根据第三译码算法对子序列进行译码，得到硬值序列，硬值序列包括对应于第一比特的第一硬值，以及对应于第二比特的第二硬值；从硬值序列中抽取第一硬值和第三硬值作为译码结果，第三硬值为对应于第二比特中的信息比特的硬值。
如图18所示为本申请实施例提供的通信装置1800，用于实现上述方法中编码装置功能。该通信装置1800包括编码器1801和发送机1802。该通信装置1800可以实现前述实施例中图4所述的方法。
作为一个示例，编码器1801，用于分别获取第一比特和第二比特，第一比特的类型为已知比特，第二比特的类型包括冻结比特、奇偶校验比特或信息比特中的至少一种；基于第一比特生成导频序列；对第二比特进行编码，得到第一编码序列；发送机1802，用于在确定发送导频序列时，向译码装置发送第二编码序列，第二编码序列中包括导频序列和第一编码序列。
可选地，在确定不发送导频序列时，第二编码序列为第一编码序列。
可选地，第二编码序列为上行控制消息，或下行控制消息。
可选地，上行控制消息中包括第一字段和第二字段，第一字段用于指示子序列中是否包括第一比特，第二字段用于指示第一比特在子序列中的位置。
可选地，下行控制消息中包括第三字段和第四字段，第三字段用于指示子序列中是否包括第一比特，第四字段用于指示第一比特在子序列中的位置。
可选地，该编码器1801，进一步用于：在空口资源充足时，确定发送导频序列；或者，在空口资源紧张时，确定不发送导频序列。
本申请实施例中还提供一种通信装置1900，该通信装置1900可以用于执行上述通信装置1700所述的方法。
上述方法中的部分或全部可以通过硬件来实现也可以通过软件来实现。当通过硬件实现时，如图19所示，通信装置1900包括：输入接口电路1901，用于实现接收机1701所实现的功能；逻辑电路1902，用于实现译码器1702所实现的功能。
可选的，通信装置在具体实现时可以是芯片或者集成电路。
本申请实施例中还提供一种通信装置2000，该通信装置2000可以用于执行上述通信装置1800所述的方法。
上述方法中的部分或全部可以通过硬件来实现也可以通过软件来实现。当通过硬件实现时，如图20所示，通信装置2000包括：逻辑电路2001，用于实现编码器1801所实现的功能；输出接口电路2002，用于实现发送机1802所实现的功能。
可选的，通信装置在具体实现时可以是芯片或者集成电路。
如图21所示为本申请实施例提供的通信装置该装置可以是网络设备，也可以是网络设备中的装置(例如，芯片或者芯片系统或芯片组或芯片中用于执行相关方法功能的一部分)。或者，该装置可以是终端，也可以是终端中的装置(例如，芯片或者芯片系统或芯片组或芯片中用于执行相关方法功能的一部分)。其中，该装置可以为芯片系统。本申请 实施例中，芯片系统可以由芯片构成，也可以包含芯片和其他分立器件。装置2100包括至少一个处理器2120，用于实现本申请实施例提供的方法中编码装置或译码装置的功能。装置2100还可以包括通信接口2110。在本申请实施例中，通信接口2110可以是收发器、电路、总线、模块或其它类型的通信接口，用于通过传输介质和其它设备进行通信。例如，在实现编码装置的功能时，通信接口2110用于装置2100中的装置可以和其它设备进行通信。示例性地，该其它设备可以是译码装置。处理器2120利用通信接口2110收发数据，并用于实现上述方法实施例编码装置或译码装置所实现的方法。
装置2100还可以包括至少一个存储器2130，用于存储程序指令和/或数据。存储器2130和处理器2120耦合。本申请实施例中的耦合是装置、单元或模块之间的间接耦合或通信连接，可以是电性，机械或其它的形式，用于装置、单元或模块之间的信息交互。处理器2120可能和存储器2130协同操作。处理器2120可能执行存储器2130中存储的程序指令。所述至少一个存储器中的至少一个可以包括于处理器中。
本申请实施例中不限定上述通信接口2110、处理器2120以及存储器2130之间的具体连接介质。本申请实施例在图21中以存储器2130、处理器2120以及通信接口2110之间通过总线2140连接，总线在图21中以粗线表示，其它部件之间的连接方式，仅是进行示意性说明，并不引以为限。所述总线可以分为地址总线、数据总线、控制总线等。为便于表示，图21中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
在本申请实施例中，处理器可以是通用处理器、数字信号处理器、专用集成电路、现场可编程门阵列或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件，可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。
在本申请实施例中，存储器可以是非易失性存储器，比如硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)等，还可以是易失性存储器(volatile memory)，例如随机存取存储器(random-access memory，RAM)。存储器是能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。本申请实施例中的存储器还可以是电路或者其它任意能够实现存储功能的装置，用于存储程序指令和/或数据。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的精神和范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (41)

  1. 一种极化码的译码方法，其特征在于，所述方法包括：
    接收来自编码装置的消息，所述消息中包括待译码的子序列，所述子序列包括第一比特，所述第一比特的类型为已知比特；
    将所述第一比特的类型作为目标类型，并根据所述目标类型对应的第一译码算法对所述第一比特进行译码，所述目标类型包括奇偶校验比特或冻结比特。
  2. 根据权利要求1所述的方法，其特征在于，所述子序列还包括第二比特，所述第二比特的类型包括所述冻结比特、所述奇偶校验比特或信息比特中的至少一种，所述方法还包括：
    根据所述第二比特的类型对应的第二译码算法对所述第二比特进行译码。
  3. 根据权利要求1或2所述的方法，其特征在于，所述消息为上行控制消息，或下行控制消息。
  4. 根据权利要求3所述的方法，其特征在于，所述上行控制消息中包括第一字段和第二字段，所述第一字段用于指示所述子序列中是否包括所述第一比特，所述第二字段用于指示所述第一比特在所述子序列中的位置。
  5. 根据权利要求3所述的方法，其特征在于，所述下行控制消息中包括第三字段和第四字段，所述第三字段用于指示所述子序列中是否包括所述第一比特，所述第四字段用于指示所述第一比特在所述子序列中的位置。
  6. 根据权利要求1～5中任一项所述的方法，其特征在于，将所述第一比特的类型作为目标类型，包括：
    在所述第一比特的取值范围与所述奇偶校验比特的取值范围一致时，将所述第一比特的类型作为所述奇偶校验比特；或者，
    在所述第一比特的取值范围与所述冻结比特的取值范围一致时，将所述第一比特的类型作为所述冻结比特。
  7. 根据权利要求2～6中任一项所述的方法，其特征在于，将所述第一比特的类型作为目标类型，包括：
    将所述第一比特的类型映射为所述目标类型，得到位置分布序列，所述位置分布序列用于表征所述子序列中各个比特的类型；
    根据所述目标类型对应的第一译码算法对所述第一比特进行译码，以及根据所述第二比特的类型对应的第二译码算法对所述第二比特进行译码，包括：
    根据所述位置分布序列，分别确定所述第一译码算法和所述第二译码算法；
    根据第三译码算法对所述子序列进行译码，所述第三译码算法包括所述第一译码算法和所述第二译码算法。
  8. 根据权利要求7所述的方法，其特征在于，在所述第二比特的类型中不包括所述信息比特时，所述第三译码算法不包括软值计算，所述软值计算用于确定所述子序列中各个比特的比特值为0或1的似然概率。
  9. 根据权利要求7所述的方法，其特征在于，在所述第二比特的类型中包括所述信息比特时，所述第三译码算法包括软值计算，所述软值计算用于确定所述子序列中各个比特的比特值为0或1的似然概率。
  10. 根据权利要求7或8所述的方法，其特征在于，在所述第二比特的类型中不包括 所述信息比特时，所述方法还包括：
    根据所述第三译码算法对所述子序列进行译码，得到硬值序列，所述硬值序列包括对应于所述第一比特的第一硬值，以及对应于所述第二比特的第二硬值；
    从所述硬值序列中抽取所述第一硬值作为译码结果。
  11. 根据权利要求7或9所述的方法，其特征在于，在所述第二比特的类型中包括所述信息比特时，所述方法还包括：
    根据所述第三译码算法对所述子序列进行译码，得到硬值序列，所述硬值序列包括对应于所述第一比特的第一硬值，以及对应于所述第二比特的第二硬值；
    从所述硬值序列中抽取所述第一硬值和第三硬值作为译码结果，所述第三硬值为对应于所述第二比特中的信息比特的硬值。
  12. 一种极化码的编码方法，其特征在于，所述方法包括：
    分别获取第一比特和第二比特，所述第一比特的类型为已知比特，所述第二比特的类型包括冻结比特、奇偶校验比特或信息比特中的至少一种；
    基于所述第一比特生成导频序列；
    对所述第二比特进行编码，得到第一编码序列；
    在确定发送所述导频序列时，向译码装置第二编码序列，所述第二编码序列中包括所述导频序列和所述编码序列。
  13. 根据权利要求12所述的方法，其特征在于，在确定不发送所述导频序列时，所述第二编码序列为所述第一编码序列。
  14. 根据权利要求12或13所述的方法，其特征在于，所述第二编码序列为上行控制消息，或下行控制消息。
  15. 根据权利要求14所述的方法，其特征在于，所述第二编码序列中包括至少一个子序列，针对一子序列，所述上行控制消息中包括第一字段和第二字段，所述第一字段用于指示所述子序列中是否包括所述第一比特，所述第二字段用于指示所述第一比特在所述子序列中的位置。
  16. 根据权利要求14所述的方法，其特征在于，所述第二编码序列中包括至少一个子序列，针对一子序列，所述下行控制消息中包括第三字段和第四字段，所述第三字段用于指示所述子序列中是否包括所述第一比特，所述第四字段用于指示所述第一比特在所述子序列中的位置。
  17. 根据权利要求12～16中任一项所述的方法，其特征在于，所述方法还包括：
    在空口资源充足时，确定发送所述导频序列；或者，
    在空口资源紧张时，确定不发送所述导频序列。
  18. 一种通信装置，其特征在于，所述通信装置包括接收机和译码器：
    所述接收机，用于接收来自编码装置的消息，所述消息中包括待译码的子序列，所述子序列包括第一比特，所述第一比特的类型为已知比特；
    所述译码器，用于将所述第一比特的类型作为目标类型，并根据所述目标类型对应的第一译码算法对所述第一比特进行译码，所述目标类型包括奇偶校验比特或冻结比特。
  19. 根据权利要求18所述的装置，其特征在于，所述子序列还包括第二比特，所述第二比特的类型包括所述冻结比特、所述奇偶校验比特或信息比特中的至少一种，所述译码器，进一步用于：
    根据所述第二比特的类型对应的第二译码算法对所述第二比特进行译码。
  20. 根据权利要求18或19所述的装置，其特征在于，所述消息为上行控制消息，或下行控制消息。
  21. 根据权利要求20所述的装置，其特征在于，所述上行控制消息中包括第一字段和第二字段，所述第一字段用于指示所述子序列中是否包括所述第一比特，所述第二字段用于指示所述第一比特在所述子序列中的位置。
  22. 根据权利要求20所述的装置，其特征在于，所述下行控制消息中包括第三字段和第四字段，所述第三字段用于指示所述子序列中是否包括所述第一比特，所述第四字段用于指示所述第一比特在所述子序列中的位置。
  23. 根据权利要求18～22中任一项所述的装置，其特征在于，所述译码器，具体用于：
    在所述第一比特的取值范围与所述奇偶校验比特的取值范围一致时，将所述第一比特的类型作为所述奇偶校验比特；或者，
    在所述第一比特的取值范围与所述冻结比特的取值范围一致时，将所述第一比特的类型作为所述冻结比特。
  24. 根据权利要求19～23中任一项所述的装置，其特征在于，所述译码器，具体用于：
    将所述第一比特的类型映射为所述目标类型，得到位置分布序列，所述位置分布序列用于表征所述子序列中各个比特的类型；
    根据所述位置分布序列，分别确定所述第一译码算法和所述第二译码算法；
    根据第三译码算法对所述子序列进行译码，所述第三译码算法包括所述第一译码算法和所述第二译码算法。
  25. 根据权利要求24所述的装置，其特征在于，在所述第二比特的类型中不包括所述信息比特时，所述第三译码算法不包括软值计算，所述软值计算用于确定所述子序列中各个比特的比特值为0或1的似然概率。
  26. 根据权利要求24所述的装置，其特征在于，在所述第二比特的类型中包括所述信息比特时，所述第三译码算法包括软值计算，所述软值计算用于确定所述子序列中各个比特的比特值为0或1的似然概率。
  27. 根据权利要求24或25所述的装置，其特征在于，在所述第二比特的类型中不包括所述信息比特时，所述译码器，进一步用于：
    根据所述第三译码算法对所述子序列进行译码，得到硬值序列，所述硬值序列包括对应于所述第一比特的第一硬值，以及对应于所述第二比特的第二硬值；
    从所述硬值序列中抽取所述第一硬值作为译码结果。
  28. 根据权利要求24或26所述的装置，其特征在于，在所述第二比特的类型中包括所述信息比特时，所述译码器，进一步用于：
    根据所述第三译码算法对所述子序列进行译码，得到硬值序列，所述硬值序列包括对应于所述第一比特的第一硬值，以及对应于所述第二比特的第二硬值；
    从所述硬值序列中抽取所述第一硬值和第三硬值作为译码结果，所述第三硬值为对应于所述第二比特中的信息比特的硬值。
  29. 一种通信装置，其特征在于，所述通信装置包括编码器和发送机：
    所述编码器，用于分别获取第一比特和第二比特，所述第一比特的类型为已知比特，所述第二比特的类型包括冻结比特、奇偶校验比特或信息比特中的至少一种；基于所述第 一比特生成导频序列；对所述第二比特进行编码，得到第一编码序列；
    所述发送机，用于在确定发送所述导频序列时，向译码装置发送第二编码序列，所述第二编码序列中包括所述导频序列和所述第一编码序列。
  30. 根据权利要求29所述的装置，其特征在于，在确定不发送所述导频序列时，所述第二编码序列为所述第一编码序列。
  31. 根据权利要求29或30所述的装置，其特征在于，所述第二编码序列为上行控制消息，或下行控制消息。
  32. 根据权利要求31所述的装置，其特征在于，所述上行控制消息中包括第一字段和第二字段，所述第一字段用于指示所述子序列中是否包括所述第一比特，所述第二字段用于指示所述第一比特在所述子序列中的位置。
  33. 根据权利要求31所述的装置，其特征在于，所述下行控制消息中包括第三字段和第四字段，所述第三字段用于指示所述子序列中是否包括所述第一比特，所述第四字段用于指示所述第一比特在所述子序列中的位置。
  34. 根据权利要求29～33中任一项所述的装置，其特征在于，所述编码器，进一步用于：
    在空口资源充足时，确定发送所述导频序列；或者，
    在空口资源紧张时，确定不发送所述导频序列。
  35. 一种通信装置，其特征在于，包括：
    输入接口电路，用于接收来自编码装置的消息，所述消息中包括待译码的子序列，所述子序列包括第一比特，所述第一比特的类型为已知比特；
    逻辑电路，用于基于所述子序列执行所述权利要求1～11任一项所述的方法。
  36. 一种通信装置，其特征在于，包括：
    逻辑电路，用于分别获取第一比特和第二比特，所述第一比特的类型为已知比特，所述第二比特的类型包括冻结比特、奇偶校验比特或信息比特中的至少一种；基于所述第一比特生成导频序列；对所述第二比特进行编码，得到编码序列，执行所述权利要求12～17中任一项所述的方法；
    输出接口电路，用于向译码装置发送编码消息，所述编码消息包括所述导频序列和所述编码序列。
  37. 一种通信装置，其特征在于，包括：
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，使得所述通信装置执行如权利要求1～11或12～17中任一项所述的方法。
  38. 根据权利要求37所述的装置，其特征在于，所述处理器包括所述存储器。
  39. 根据权利要求37或38所述的装置，其特征在于，所述通信装置为芯片或集成电路。
  40. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有计算机可读指令，当所述计算机可读指令在通信装置上运行时，使得所述通信装置执行权利要求1～11或12～17中任一项所述的方法。
  41. 一种计算机程序产品，其特征在于，当所述计算机程序产品在通信装置上运行时，使得所述通信装置执行权利要求1～11或12～17任一所述的方法。
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