WO2021196012A1

WO2021196012A1 - Chip package and preparation method therefor

Info

Publication number: WO2021196012A1
Application number: PCT/CN2020/082565
Authority: WO
Inventors: 陆斌; 沈健
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2020-03-31
Filing date: 2020-03-31
Publication date: 2021-10-07
Also published as: CN113811991A

Abstract

Provided in the present application are a chip package and a preparation method therefor. The chip package comprises: a chip, the upper surface of the chip being provided with at least one first pad and at least one second pad; a device layer, which comprises a first insulating layer, at least one conductive column, and an integrated passive device (IPD), the first insulating layer being provided above the chip, the at least one conductive column penetrating the first insulating layer and being provided above the at least one first pad, and the IPD penetrating the first insulating layer and being provided above the at least one second pad; a wiring layer, which is provided above the device layer; and at least one third pad, which is provided above the wiring layer, the at least one conductive column being connected to the at least one third pad by means of the wiring layer. The described chip package can ensure the yield of chips on the basis of reducing parasitic capacitance.

Description

Chip packaging body and preparation method thereof

Technical field

The embodiments of the present application relate to the field of chips, and more specifically, to a chip package and a manufacturing method thereof.

Background technique

The processors of mobile phones and computers need to be equipped with a large number of decoupling capacitors, which are used to filter noise in the circuit, thereby improving the integrity of power and signals.

Decoupling capacitors usually use low-equivalent series inductance (ESL) Multiplayer Ceramic Chip Capacitors (MLCC) and are placed close to the processor to reduce parasitic inductance in the entire circuit. For example, reverse geometry MLCC or multi-terminal MLCC.

On the one hand, the parasitic inductance contributed by the low ESL model MLCC is small.

On the other hand, the parasitic inductance caused by the wires in the circuit is proportional to the length of the wire used to connect the decoupling capacitor to the processor (that is, the longer the wire, the greater the parasitic inductance).

For existing high-performance processors, the decoupling capacitor is usually directly mounted on the side of the packaged chip where the pad is provided to reduce the parasitic inductance caused by the wire. For example, as shown in FIG. 1, the processor 100 includes a chip 110 and a decoupling capacitor 160, wherein the decoupling capacitor 160 is directly mounted on the back of the package structure 120 of the packaged chip 110, and the back is One side of the chip 110 where the pads are provided, that is, a part of the pads 140 of the wiring layer 130 is used for connecting the decoupling capacitor 160, and the other part of the pads 140 is used for setting the solder balls 150. However, even with the most advanced packaging technology, the vertical distance between the decoupling capacitor 160 and the chip 110 is about 60-200 microns, and the resulting parasitic inductance is about tens to hundreds of picofarads (pF).

In order to further reduce the vertical distance between the decoupling capacitor and the chip, and further reduce the parasitic inductance of the processor. In the process of packaging the chip 110, a metal-insulator-metal (MIM) capacitor may be directly fabricated near the pad 140 of the chip 110. That is, the decoupling capacitor is used as a part of the package of the chip 110. However, the capacitance of the MIM capacitor is usually on the order of pF, which is much smaller than the actual demand of the processor for the capacitance of the decoupling capacitor. In addition, the yield rate of the MIM capacitor will affect the yield rate of the processor, thereby increasing the manufacturing cost of the processor or functional chip.

Therefore, there is an urgent need in the art for a processor or functional chip that can have both low parasitic inductance and low manufacturing cost.

Summary of the invention

The present application provides a chip package and a preparation method thereof, which can ensure the yield of the chip on the basis of reducing parasitic capacitance.

In the first aspect, a chip package is provided, including:

A chip, the upper surface of the chip is provided with at least one first pad and at least one second pad;

A device layer, the device layer includes a first insulating layer, at least one conductive pillar and an integrated passive device IPD, the first insulating layer is disposed above the chip, and the at least one conductive pillar penetrates the first insulating layer The layer is disposed above the at least one first pad, and the IPD penetrates the first insulating layer and is disposed above the at least one second pad;

A wiring layer, the wiring layer is arranged above the device layer;

At least one third pad, the at least one third pad is disposed above the wiring layer, and the at least one conductive pillar is connected to the at least one third pad through the wiring layer.

Directly soldering a separately manufactured integrated passive device (IPD) to the chip before packaging, and after packaging the IPD and the chip, the wiring layer and the at least one third pad are arranged, Compared with the solution in which the IPD is arranged on the back surface of the package structure of the individually packaged chip, the vertical distance between the IPD and the chip can be reduced, thereby reducing the parasitic inductance of the processor. In addition, compared with the solution of preparing the IPD in the process of preparing the chip (for example, preparing the IPD in the process of preparing the wiring layer of the chip), the IPD with good performance and the chip with good performance can be compared. Direct packaging to form the chip package can prevent the yield of the IPD and the chip from affecting the yield of the chip package. Accordingly, the manufacturing cost of the chip package is ensured .

In addition, compared with the solution in which the IPD is arranged on the pad of the wiring layer of the packaged chip, the IPD and the chip are packaged to prepare at least one third pad of the chip package, which avoids The IPD occupies the space of the pads of the packaged chip, that is, because the IPD does not need to occupy an additional position, the chip package body that can meet the high input/output (Input/Output, I/O) requirements is relatively large, In order to set the defect of insufficient pad space.

In some possible implementation manners, the chip package further includes:

At least one of the adhesion layer, the barrier layer and the seed layer, and at least one of the adhesion layer, the barrier layer and the seed layer is disposed between the at least one first pad and the at least one conductive pillar.

On the one hand, during the preparation process, the seed layer in at least one of the adhesion layer, the barrier layer and the seed layer can be used to grow the at least one conductive pillar. On the other hand, the adhesion layer, the barrier layer and the seed layer The adhesion layer and/or the barrier layer in at least one of the layers can increase the stability between the at least one first pad and the at least one conductive pillar, and accordingly, ensure the performance of the chip package .

In some possible implementation manners, at least one conductive bump is provided on a side of the IPD close to the chip, and the at least one conductive bump is respectively connected to the at least one second pad.

Connecting the at least one conductive bump of the IPD directly to the at least one second pad of the chip is equivalent to directly connecting the IPD and the chip face-to-face, which can reduce as much as possible. The vertical distance between the IPD and the chip is small, and accordingly, the parasitic inductance of the chip package can be reduced as much as possible.

In some possible implementations, a non-conductive material is provided at the connection between the at least one conductive bump and the at least one second pad.

The connection between the at least one conductive bump and the at least one second pad can be sealed by the non-conductive material, and accordingly, the performance of the chip package can be ensured.

In some possible implementation manners, the chip package further includes:

The first adhesive layer is arranged under the chip.

In some possible implementation manners, the chip package further includes:

The molding compound is arranged under the wiring layer and located in the surrounding area of the chip, and the molding compound is used to mold the chip, the device layer and the first adhesive layer.

In some possible implementation manners, the chip includes an interconnection layer and a substrate, and the at least one first pad and the at least one second pad are embedded in the interconnection layer.

Configuring the at least one first pad and the at least one second pad to be embedded in the interconnection layer can shorten the vertical distance between the chip and the IPD as much as possible. Accordingly, The integrated inductance of the chip package can be reduced as much as possible.

In some possible implementations, the plane where the upper surface of the at least one first pad is located, the plane where the upper surface of the at least one second pad is located, and the plane where the upper surface of the interconnection layer is located are the same. flat.

In some possible implementation manners, the chip package further includes at least one metal ball respectively disposed on the at least one third pad.

In some possible implementation manners, the wiring layer includes a second insulating layer and metal wiring arranged in the second insulating layer, and the at least one conductive pillar is respectively connected to the at least one first insulating layer through the metal wiring. Three pads.

In a second aspect, a method for preparing a chip package is provided, including:

A device layer is prepared above the chip. The upper surface of the chip is provided with at least one first pad and at least one second pad. The device layer includes a first insulating layer, at least one conductive pillar and an integrated passive device IPD The first insulating layer is arranged above the chip, the at least one conductive pillar penetrates the first insulating layer and is arranged above the at least one first pad, and the IPD penetrates the first The insulating layer is arranged above the at least one second pad;

Preparing a wiring layer above the device layer;

At least one third pad is prepared on the wiring layer, and the at least one conductive pillar is connected to the at least one third pad through the wiring layer.

In some possible implementation manners, the preparing a device layer above the chip includes:

Preparing a dry film layer above the chip;

Forming at least one groove penetrating the dry film layer above the at least one first pad;

Preparing the at least one conductive pillar in the at least one groove;

Removing the dry film layer;

Disposing the IPD above the at least one second pad;

A first insulating layer is prepared above the chip, so that the first insulating layer covers the at least one conductive layer and the IPD.

In some possible implementation manners, the preparing a dry film layer above the chip includes:

Preparing at least one of an adhesion layer, a barrier layer and a seed layer above the chip;

The dry film layer is prepared above at least one of the adhesion layer, the barrier layer, and the seed layer, so that the at least one conductive pillar is grown on at least one of the adhesion layer, the barrier layer, and the seed layer ；

Wherein, the removing the dry film layer includes:

Removing at least one of the dry film layer and the adhesion layer, the barrier layer, and the seed layer under the dry film layer.

Preparing the IPD above the at least one second pad;

Preparing the first insulating layer above the chip;

Forming at least one groove penetrating the first insulating layer above the at least one first pad;

The at least one conductive pillar is prepared in the at least one groove, so that the first insulating layer covers the at least one conductive layer and the IPD.

In some possible implementation manners, the preparing the at least one conductive pillar in the at least one groove includes:

Preparing at least one of an adhesion layer, a barrier layer and a seed layer on the inner wall of each groove in the at least one groove;

The conductive layer is grown on at least one of the adhesion layer, the barrier layer, and the seed layer to form the at least one conductive pillar.

In some possible implementation manners, the preparing at least one of an adhesion layer, a barrier layer, and a seed layer on the inner wall of each groove in the at least one groove includes:

Preparing at least one of an adhesion layer, a barrier layer and a seed layer above the at least one first pad and the inner wall of each groove in the at least one groove;

Wherein, the growing the conductive layer on at least one of the adhesion layer, the barrier layer and the seed layer to form the at least one conductive pillar includes:

Growing the conductive layer on at least one of the adhesion layer, the barrier layer and the seed layer;

The conductive layer is thinned to expose the at least one conductive pillar.

Preparing a device layer on top of the first wafer;

Preparing a first adhesive layer under the first wafer to form chips to be cut;

The chip to be cut is cut to form at least one chip, and each chip of the at least one chip is a chip integrated with the IPD.

In some possible implementation manners, the method further includes:

Before preparing the first adhesive layer under the first wafer, the substrate of the first wafer is thinned.

In some possible implementation manners, the preparing a wiring layer above the device layer includes:

Sticking the at least one chip to the second adhesive layer of the carrier;

Forming a molding compound on the carrier sheet, and the molding compound is used to mold the chip, the device layer and the first adhesive layer;

Thinning the molding compound to expose the at least one conductive pillar;

On the molding compound and the chip, the wiring layer is prepared.

In some possible implementation manners, the preparing at least one third pad on the wiring layer includes:

Preparing the at least one third pad on the wiring layer;

Removing the second adhesive layer and the carrier sheet to form a package to be cut;

Cutting the package to be cut to form at least one chip package.

In some possible implementation manners, the method further includes:

At least one metal ball is prepared above the at least one third pad.

In a third aspect, a chip package is provided, including:

A chip package prepared according to the method described in the second aspect or any possible implementation manner of the second aspect.

Description of the drawings

Fig. 1 is a schematic structural diagram of a processor in the prior art.

Fig. 2 is a schematic structural diagram of a chip package according to an embodiment of the present application.

FIG. 3 is a schematic flowchart of a method for preparing the chip package shown in FIG. 2 according to an embodiment of the present application.

4 to 14 are schematic diagrams of structures formed in various stages of preparing the chip package shown in FIG. 2 according to an embodiment of the present application.

15 to 21 are schematic diagrams of structures formed in various stages of preparing the deformed structure of the chip package shown in FIG. 2 according to an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings.

It should be understood that, for the chip package and the preparation method thereof related to the present application, the chip package may be any structure formed after chip packaging, especially a chip containing active devices. For example, the chip package may be a processor or a processor chip of an electronic device. The chip package can be applied to various electronic devices. For example, portable or mobile computing devices such as smartphones, notebook computers, tablet computers, and gaming devices, as well as other electronic devices such as electronic databases, automobiles, and bank automated teller machines (ATM).

It should be noted that, for ease of description, in the embodiments of the present application, the same reference numerals denote the same components, and for brevity, detailed descriptions of the same components are omitted in different embodiments. It should be understood that the thickness, length and width of the various components in the embodiments of the application shown in the drawings, as well as the overall thickness, length and width of the integrated device, are only exemplary descriptions, and should not constitute any limitation to the application. .

In addition, for ease of understanding, in the embodiments shown below, for the structures shown in different embodiments, the same structures are given the same reference numerals, and for the sake of brevity, detailed descriptions of the same structures are omitted.

As shown in FIG. 2, the chip package 200 may include a chip 210, a device layer 220, a wiring layer 230 and at least one third pad 240. Wherein, the upper surface of the chip 210 is provided with at least one first pad 213 and at least one second pad 214. The device layer 220 may include a first insulating layer 223, at least one conductive pillar 221 and an integrated passive device IPD 222, the first insulating layer 223 is disposed above the chip 210, and the at least one conductive pillar 221 penetrates The first insulating layer 223 is disposed above the at least one first pad 213, and the IPD 222 penetrates the first insulating layer 223 and is disposed above the at least one second pad 214. The wiring layer 230 is disposed above the device layer 220. The at least one third pad 240 is disposed above the wiring layer 230, and the at least one conductive pillar 221 is connected to the at least one third pad 240 through the wiring layer 230.

Wherein, the chip 210 may be an unpackaged chip. For example, the chip 210 may be a wafer or a die. For example, the chip 210 may be an unpackaged chip body with specific functions. The IPD 222 includes but is not limited to at least one of the following: capacitors, resistors, inductors, transformers, antennas, transducers, piezoelectric devices, crystal oscillators, and memristors. In other words, the IPD may be a single device or a combined device formed by multiple devices. The IPD may be a passive device. The IPD can also be called a passive device or a passive component. The capacitor may be any capacitor that can be independently prepared. For example, the capacitor may be a low equivalent series inductance (ESL) type of multilayer ceramic chip capacitors (Multiplayer Ceramic Chip Capacitors, MLCC). For example, reverse geometry MLCC or multi-terminal MLCC. The at least one third pad 240 may also be referred to as at least one Under Bump Metalization (UBM).

The separately manufactured integrated passive device (IPD) 222 is directly soldered to the chip 210 and then packaged, and the wiring layer 230 and the at least one are formed after the IPD and the chip 210 are packaged. The third pad 240 can reduce the IPD 222 and the chip 210 compared with the solution shown in FIG. 1 (that is, the decoupling capacitor 160 is mounted on the back of the package structure 120 of the individually packaged chip 110). The vertical distance between the two, thereby reducing the parasitic inductance of the processor.

In addition, compared with the solution of preparing the IPD 222 in the process of preparing the chip 210 (for example, preparing the IPD 222 in the process of preparing the wiring layer of the chip 210), the IPD 222 with good performance and performance can be compared. A good chip 210 is directly packaged to form the chip package 200, which can prevent the yield rate of the IPD 222 and the yield rate of the chip 210 from affecting the yield rate of the chip package 200. Accordingly, it is ensured The manufacturing cost of the chip package 200.

In addition, compared with the solution shown in FIG. 1 in which the IPD 222 is disposed on the pad of the wiring layer 230 of the packaged chip 210, the chip package 200 is prepared after the IPD 222 and the chip 210 are packaged. The at least one third pad 240 of the IPD 222 prevents the IPD 222 from occupying the space of the pad of the packaged chip 210. That is, because the IPD 222 does not need to occupy an additional position, it can solve the problem of high input/output (Input/Output). , The chip package 200 required by the I/O) has a larger package size in order to set up the defect of insufficient pad space.

As shown in FIG. 2, in some embodiments of the present application, the chip package 200 further includes:

At least one layer 250 of the adhesion layer, the barrier layer, and the seed layer 250 is provided on the at least one first pad 213 and the at least one conductive pillar 221 between.

For example, at least one layer 250 of the adhesion layer, barrier layer and seed layer may include a layer of titanium (Ti) and a layer of copper (Cu), wherein the layer of Ti serves as the adhesion layer and the barrier layer, The layer of copper (Cu) as a seed layer can be used to grow the at least one conductive pillar 221.

On the one hand, during the preparation process, the seed layer in at least one layer 250 of the adhesion layer, the barrier layer and the seed layer can be used to grow the at least one conductive pillar 221. On the other hand, the adhesion layer, the barrier layer And the adhesion layer and/or adhesion layer in at least one layer 250 in the seed layer can increase the stability between the at least one first pad 213 and the at least one conductive pillar 221, and accordingly, ensure the The performance of the chip package 200.

As shown in FIG. 2, in some embodiments of the present application, at least one conductive bump 2221 is provided on a side of the IPD 222 close to the chip 210, and the at least one conductive bump 2221 is respectively connected to the At least one second pad 214.

Directly connect the at least one conductive bump 2221 of the IPD 222 to the at least one second pad 214 of the chip 210 respectively, which is equivalent to directly connect the IPD 222 and the chip 210 face to face Therefore, the vertical distance between the IPD 222 and the chip 210 can be reduced as much as possible, and accordingly, the parasitic inductance of the chip package 200 can be reduced as much as possible.

As shown in FIG. 2, in some embodiments of the present application, a non-conductive material 2223 is provided at the connection between the at least one conductive bump 2221 and the at least one second pad 214.

The non-conductive material 2223 can seal the connection between the at least one conductive bump 2221 and the at least one second pad 214, and accordingly, the performance of the chip package 200 can be ensured.

As shown in FIG. 2, in some embodiments of the present application, the at least one conductive bump 2221 and the at least one second pad 214 are connected by a conductive material 2222. For example, during the preparation process, a layer of conductive material 2222 may be prepared on the surface of the at least one conductive bump 2221, and then the conductive material 2222 is soldered to the at least one second pad 214. Optionally, the conductive material 2222 may be used to prevent corrosion of the at least one conductive bump 2221, so as to ensure the performance stability of the IPD 222.

For example, the main material of the at least one second pad 214 is aluminum (Al), and a layer of nickel-gold (Ni-Au) material may also be formed on the at least one second pad 214. Optionally, each of the at least one conductive bump 2221 may be a copper (Cu) bump, the conductive material 2222 may be tin (Sn), and the non-conductive material may be a non-conductive film (non-conductive film, NCF) or non-conductive paste (NCP).

The first adhesive layer 260 is disposed under the chip 210.

It should be understood that the first adhesive layer 260 may be any adhesive layer used for dicing wafers in the chip preparation process. For example, the first adhesive layer 260 may be a die attach film. , DAF).

The molding compound 270 is arranged around the chip 210 for molding the chip 210, the device layer 220 and the first adhesive layer 260, and the molding compound 270 is located on the wiring layer Below 230, that is, the molding compound 270 does not plastic-encapsulate the wiring layer 230.

Wherein, the material of the molding compound 270 may be an organic polymer. For example, epoxy resin, polyimide (PI), benzocyclobutene (BCB), polyparaphenylene benzodioxazole (PBO), and Parylene. Optionally, the molding compound 270 may also include a filler of inorganic material. For example, the filler includes but is not limited to silica pellets, and the filler is used to adjust and match the thermal expansion coefficient.

As shown in FIG. 2, in some embodiments of the present application, the chip 210 includes an interconnection layer 212 and a substrate 211, and the at least one first pad 213 and the at least one second pad 214 are embedded in Inside the interconnection layer 212.

Wherein, the substrate 211 may be silicon or other semiconductor materials. The interconnection layer 212 may be a back-end-of-line (BEOL) layer fabricated in a fab, or may include a rewiring layer (RDL) layer fabricated directly on the BEOL layer. The interconnection layer 212 includes the at least one first pad 213 and the at least one second pad 214. The interconnection layer may include a semiconductor circuit. For example, the semiconductor circuit includes, but is not limited to, a capacitor and/or a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). For example, "N-type" MOS tube (NMOSFET) and "P-type" MOS tube (PMOSFET). The substrate 211 and the interconnection layer are used to form a chip main body, that is, a chip capable of realizing specific functions. For example, the substrate 211 may be a processor body without a wiring layer. The chip main body can also be understood as an unpackaged chip. The main material of the at least one first pad 213 and the at least one second pad 214 includes but is not limited to at least one of aluminum (Al) and copper (Cu). Further, the additive material of the at least one first pad 213 and the at least one second pad 214 includes but is not limited to one or more of the following materials: silicon (Si), titanium (Ti), tantalum (Ta) , Titanium nitride (TiN), tantalum nitride (TaN), nickel (Ni), zinc (Zn), tungsten (W), tin (Sn), silver (Ag), palladium (Pd) and gold (Au).

The at least one first pad 213 and the at least one second pad 214 are configured to be embedded in the interconnection layer 212, which can shorten the vertical distance between the chip 210 and the IPD 222 as much as possible. The distance, correspondingly, can reduce the integrated inductance of the chip package 200 as much as possible.

As shown in FIG. 2, in some embodiments of the present application, the plane on which the upper surface of the at least one first pad 213 is located, the plane on which the upper surface of the at least one second pad 214 is located, and the interconnection The plane on which the upper surface of the layer 212 is located is the same plane.

As shown in FIG. 2, in some embodiments of the present application, the chip package 200 further includes at least one metal ball 280 respectively disposed on the at least one third pad 240. The at least one metal ball 280 is used to electrically connect to and communicate with other devices or components in the electronic device in which the chip package 200 is installed. For example, if the chip package 200 is a processor of an electronic device, the at least one metal ball 280 can be used as a connection pad with the memory, camera, antenna and other devices of the electronic device. Optionally, the at least one metal ball 280 may be at least one solder ball.

As shown in FIG. 2, in some embodiments of the present application, the wiring layer 230 includes a second insulating layer 231 and a metal wiring 232 disposed in the second insulating layer 231, and the at least one conductive pillar 221 passes The metal wiring 232 is connected to the at least one third pad 240 respectively. The metal wiring 232 may include at least one layer of wiring.

It should be understood that FIG. 2 is only an example of the embodiment of the present application, and should not be construed as a limitation to the embodiment of the present application. For example, in other alternative embodiments, the chip package may include multiple IPDs. For another example, in other alternative embodiments, the chip package may further include multiple chips. Various combinations of components and simple deformed structures involved in the embodiments of the present application all fall within the protection scope of the present application.

FIG. 3 is a schematic flowchart of a method for preparing the chip package 200 shown in FIG. 2 according to an embodiment of the present application. 4 to 14 are schematic diagrams of structures formed in various stages of preparing the chip package 200 shown in FIG. 2 according to an embodiment of the present application. FIGS. 15 to 21 are schematic diagrams of another structure formed in various stages of preparing the chip package 200 shown in FIG. 2 according to an embodiment of the present application. The method for preparing the chip package of the present application will be described below in conjunction with FIG. 3 to FIG. 21. In order to avoid repetition, the relevant descriptions involved in the product embodiment part will not be repeated in the method embodiment part.

As shown in FIG. 3, the method 300 for preparing a chip package includes:

S310. A device layer is prepared above the chip. The upper surface of the chip is provided with at least one first pad and at least one second pad. The device layer includes a first insulating layer, at least one conductive pillar and an integrated passive In the device IPD, the first insulating layer is arranged above the chip, the at least one conductive pillar penetrates the first insulating layer and is arranged above the at least one first pad, and the IPD penetrates the The first insulating layer is disposed above the at least one second pad.

S320, preparing a wiring layer above the device layer. Optionally, the wiring layer includes a second insulating layer and metal wiring arranged in the second insulating layer, and the at least one conductive pillar is respectively connected to the at least one third pad through the metal wiring.

S330, preparing at least one third pad on the wiring layer, and the at least one conductive pillar is connected to the at least one third pad through the wiring layer.

In other words, before the chip is packaged, the IPD is integrated on the chip, and then the chip integrated with the IPD is packaged, thereby not only reducing the parasitic inductance between the chip and the IPD, but also avoiding The yield of the IPD and the yield of the chip affect the yield of the chip package, and accordingly, the yield of the chip package can be improved and the manufacturing cost can be reduced.

It should be noted that the IPD may be a device with good performance that has been prepared before the chip package is prepared, such as a silicon capacitor bare chip. For example, at least one conductive bump is provided on a side of the IPD close to the chip, and the at least one conductive bump is respectively connected to the at least one second pad. For another example, the surface of the at least one conductive bump is provided with a non-conductive material, so that when the at least one conductive bump is soldered to the at least one second pad, the non-conductive material can be used to plastically seal the at least one conductive bump. A junction between a conductive bump and the at least one second pad.

Similarly, the chip may be a chip prepared in advance. For example, the chip includes an interconnection layer and a substrate, and the at least one first pad and the at least one second pad are embedded in the interconnection layer. Optionally, in some embodiments of the present application, the plane on which the upper surface of the at least one first pad is located, the plane on which the upper surface of the at least one second pad is located, and the upper surface of the interconnection layer The plane is the same plane, so that the device layer is prepared above the chip.

In some embodiments of the present application, the S310 may include:

A dry film layer is prepared above the chip; at least one groove penetrating the dry film layer is formed above the at least one first pad; the at least one conductive pillar is prepared in the at least one groove Removing the dry film layer; disposing the IPD above the at least one second pad; preparing a first insulating layer above the chip, so that the first insulating layer covers the at least one conductive Layer and the IPD.

For example, in the process of preparing at least one of the adhesion layer, the barrier layer, and the seed layer on the chip, the dry layer may be prepared on the at least one of the adhesion layer, the barrier layer, and the seed layer. A film layer to grow the at least one conductive pillar on at least one of the adhesion layer, the barrier layer, and the seed layer; at this time, in the process of removing the dry film layer, the dry film layer may be removed And at least one of the adhesion layer, the barrier layer and the seed layer under the dry film layer.

In some embodiments of the present application, the S310 may include:

The IPD is prepared above the at least one second pad; the first insulating layer is prepared above the chip; and the first insulating layer is formed above the at least one first pad. At least one groove; the at least one conductive pillar is prepared in the at least one groove, so that the first insulating layer covers the at least one conductive layer and the IPD.

For example, in the process of preparing the at least one conductive pillar in the at least one groove, at least one of an adhesion layer, a barrier layer, and a seed layer may be prepared on the inner wall of each groove in the at least one groove. Layer; then the conductive layer is grown on at least one of the adhesion layer, the barrier layer and the seed layer to form the at least one conductive pillar. Optionally, at least one of an adhesion layer, a barrier layer and a seed layer may be prepared above the at least one first pad and on the inner wall of each groove in the at least one groove; The conductive layer is grown on at least one of the adhesion layer, the barrier layer and the seed layer; finally, the conductive layer is thinned to expose the at least one conductive pillar.

In some embodiments of the present application, the method 300 may further include:

At least one metal ball is prepared above the at least one third pad.

It should be noted that in the process of preparing the chip package, a single chip package can be prepared, or the chip package can be prepared in batches. Compared with the preparation of a single chip package, the preparation of chip packages in batches can improve production efficiency and reduce manufacturing cost. Correspondingly, the above-mentioned preparation method can also be integrated into the method of preparing chip packages in batches.

The method for preparing chip packages in batches is described below.

In some embodiments of the present application, the S310 may include:

A device layer is prepared above the first wafer; a first adhesive layer is prepared below the first wafer to form a chip to be cut; the chip to be cut is cut to form at least one chip, the at least one Each chip in the chip is a chip integrated with the IPD. Optionally, before the first adhesive layer is prepared under the first wafer, the substrate of the first wafer may be thinned.

In some embodiments of the present application, the S320 may include:

Sticking the at least one chip to the second adhesive layer of the carrier; forming a molding compound on the carrier, and the molding compound is used to mold the chip, the device layer, and the first adhesive layer; The plastic molding compound is thinned to expose the at least one conductive pillar; the wiring layer is prepared on the molding compound and the chip.

In some embodiments of the present application, the S330 may include:

Preparing the at least one third pad on the wiring layer; removing the second adhesive layer and the carrier sheet to form a package to be cut; cutting the package to be cut to form at least one述chip package.

In summary, in S310, the IPD with a smaller size can be directly soldered to the specific pad of the first wafer with a larger size (that is, the at least A second pad); and on the remaining pads (that is, the at least one first pad), a copper pillar of a certain height is made; then, a first adhesive is prepared on the substrate of the first wafer Layer to form the chip to be cut; finally, the back side (ie, the substrate) of the chip to be cut is thinned, and die saw is used to form at least one chip. In S320, first paste the at least one chip on the second adhesive layer of the carrier, and encapsulate the upper and side surfaces of the at least one chip with a plastic molding compound to form a reconstituted wafer; then, use mechanical grinding The plastic packaging material of the reconstructed wafer is thinned to expose the copper pillars and ground to eliminate the influence of the wafer thinning tolerance and the thickness tolerance of the adhesive layer, so as to facilitate the subsequent photolithographic production of the rewiring layer. In S330, a wiring layer and solder balls are first fabricated on the surface of the reconstructed wafer, wherein the metal traces in the wiring layer are electrically connected to the copper pillars; then, the reconstructed wafer is removed from the carrier And dicing to obtain at least one chip package.

Hereinafter, the structures formed in each stage of preparing the chip package 200 shown in FIG. 2 in batches will be described with reference to FIGS. 4 to 14.

step 1:

Select the wafer used to prepare the chip package.

For example, as shown in FIG. 4, the first wafer 400 is selected. Wherein, the first wafer 400 may include a plurality of chips 210, and each chip 210 of the plurality of chips 210 includes a substrate 211 and an interconnection layer 212, and the interconnection layer 212 is provided with at least one first solder. The pad 213 and at least one second pad 214.

Step 2:

First, a deposition process is used to deposit at least one layer 250 of an adhesion layer, a barrier layer, and a seed layer on the surface of the first wafer 400 (for example, at least one layer 250 of the adhesion layer, a barrier layer, and a seed layer). It may include a layer of Ti and a layer of Cu); then, a dry film layer 411 is covered on the surface of the first wafer 400; The at least one groove 412 of the dry film layer 411 further forms the structure 410 shown in FIG. 5.

Wherein, the deposition process includes but is not limited to:

Physical Vapor Deposition (PVD) process and/or Chemical Vapor Deposition (CVD) process. For example, thermal oxidation, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc.), atomic layer deposition (ALD) ), electroplating, spin coating or spraying.

Step 3:

At least one conductive pillar 221 (for example, a copper pillar) is grown in the at least one groove 412 by an electroplating process to form the structure 420 shown in FIG. 6.

Step 4:

The dry film layer 411 is first removed, and then at least one layer 250 of the excess adhesion layer, barrier layer and seed layer is removed by a wet etching process to form the structure 430 shown in FIG. 7.

Step 5:

The oxide and contamination on the surface of the at least one second pad 214 are removed.

It should be noted that if the main material of the at least one second pad 214 is aluminum (Al), optionally, an electroless plating process may be used to deposit nickel and gold on the at least one second pad 214. (Ni-Au) material; then, the fabricated IPD 222 with at least one conductive bump 2221 (for example, copper (Cu) bump) and coated with a non-conductive material 2223, is welded in the form of an inverted pile The at least one second pad 214 is formed to form the structure 440 shown in FIG. 8. Optionally, a conductive material 2222 may be further provided on the at least one conductive bump 2221. For example, the conductive material 2222 may be tin. Optionally, the non-conductive material may be a non-conductive film (NCF) or a non-conductive paste (NCP).

Step 6:

A first insulating layer 223 is provided on the upper surface of the first wafer 400 to form the structure 450 shown in FIG. 9. Wherein, the first insulating layer 223 may be used to cover and fix the at least one conductive pillar 221 and the IPD 222.

Step 7:

First, the substrate 211 of the first wafer 400 is thinned to an appropriate thickness, and the thinned surface is polished; then, a first adhesive layer 260 (such as DAF) is provided as an adhesive layer on the polished surface of the substrate 211; , Dicing according to the dicing lane to obtain at least one chip 210; finally, the at least one chip 210 is pasted on the second adhesive layer 452 of the carrier 451 at a certain interval to form the structure 460 shown in FIG. 10. Optionally, the second adhesive layer 452 may be used as a temporary adhesive layer, and the second adhesive layer 452 may be a light-to-heat-conversion (LTHC) layer produced by 3M Company. Optionally, the carrier 451 includes but is not limited to glass, silicon wafer, and metal plate. It should be noted that the second adhesive layer 452 can be any type of adhesive layer that can be selectively removed or made to lose its viscosity later.

Step 8:

Using a molding process, at least one chip 210 placed on the carrier sheet 451 is covered with a molding compound 270 to form the structure 470 shown in FIG. 11. Optionally, the material of the molding compound 270 includes but not limited to epoxy molding compound (EMC).

Step 9:

Using mechanical grinding, the front surface of the molding compound 270 is ground flat, and the at least one conductive pillar 221 is exposed to form the structure 480 shown in FIG. 12.

Step 10:

The wiring layer 230 of one or more metal traces, at least one third pad 240 and at least one metal ball 280 are fabricated on the ground surface to form the structure 490 shown in FIG. 13. Optionally, the at least one third pad 240 may be referred to as at least one Under Bump Metalization (UBM), and the at least one metal ball may also be referred to as at least one solder ball.

Step 11:

The carrier sheet 451 and the second adhesive layer 452 are removed to form the structure 4100 shown in FIG. 14, and the mechanism shown in FIG. 14 is diced along the dicing path to obtain at least one chip package including an IPD and a chip.

It should be understood that the structures shown in FIG. 4 to FIG. 14 are only examples of the present application, and should not be construed as limiting the present application. For example, in the process of preparing the device layer, at least one conductive pillar 221 may be prepared first and then the IPD 222 may be integrated into the chip 210, or the IPD 222 may be integrated into the chip 210 first, and then the at least one conductive pillar may be prepared. One conductive pillar 221, the implementation manner of first integrating the IPD 222 and then preparing the at least one conductive pillar 221 will be described below with reference to FIGS. 15 to 21.

For example, first select the first wafer 400, and integrate the IPD 222 on at least one second pad 214 of the first wafer 400 to form the structure 500 shown in FIG. A first insulating layer 223 is formed above the circle 400 to form the structure 510 shown in FIG. A groove 521 to form the structure 520 shown in FIG. 17; then a conductive layer 531 is prepared on the at least one first pad 213 and the first insulating layer 223 to form the structure 530 shown in FIG. 18; Then, a first adhesive layer 260 is formed under the first wafer 400 to form a chip to be diced. After the chip to be diced is cut into at least one chip, the second adhesive layer is attached to the carrier 451 at a certain interval. On the adhesive layer 452, the structure 540 shown in FIG. 19 is formed; then the conductive layer 531 is flattened to expose the at least one conductive pillar 221, thereby forming the structure 550 shown in FIG. 20; then, on the device layer A wiring layer 230, at least one third pad 240, and one less metal ball 280 are prepared above 220 to form the structure 560 shown in FIG. 21.

The application also provides a chip package prepared according to the method 300.

A person of ordinary skill in the art may realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraint conditions of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.

In addition, the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.

If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solution of the present application essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks or optical disks and other media that can store program codes. .

The above are only specific implementations of this application, but the protection scope of this application is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application. Should be covered within the scope of protection of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.

Claims

A chip package is characterized in that it comprises:

A chip, the upper surface of the chip is provided with at least one first pad and at least one second pad;

A device layer, the device layer includes a first insulating layer, at least one conductive pillar and an integrated passive device IPD, the first insulating layer is disposed above the chip, and the at least one conductive pillar penetrates the first insulating layer The layer is disposed above the at least one first pad, and the IPD penetrates the first insulating layer and is disposed above the at least one second pad;

A wiring layer, the wiring layer is arranged above the device layer;

At least one third pad, the at least one third pad is disposed above the wiring layer, and the at least one conductive pillar is connected to the at least one third pad through the wiring layer.
The chip package of claim 1, wherein the chip package further comprises:

At least one of the adhesion layer, the barrier layer, and the seed layer, and at least one of the adhesion layer, the barrier layer, and the seed layer is disposed between the at least one first pad and the at least one conductive pillar.
The chip package according to claim 1 or 2, wherein at least one conductive bump is provided on a side of the IPD close to the chip, and the at least one conductive bump is connected to the at least one The second pad.
The chip package according to claim 3, wherein a non-conductive material is provided at a connection between the at least one conductive bump and the at least one second pad.
The chip package according to any one of claims 1 to 4, wherein the chip package further comprises:

The first adhesive layer is arranged under the chip.
The chip package of claim 5, wherein the chip package further comprises:

The molding compound is arranged under the wiring layer and located in the surrounding area of the chip, and the molding compound is used to mold the chip, the device layer and the first adhesive layer.
The chip package according to any one of claims 1 to 6, wherein the chip comprises an interconnection layer and a substrate, and the at least one first pad and the at least one second pad are embedded and arranged In the interconnection layer.
The chip package according to claim 7, wherein the plane on which the upper surface of the at least one first pad is located, the plane on which the upper surface of the at least one second pad is located, and the plane of the interconnect layer The plane where the upper surface is located is the same plane.
8. The chip package according to any one of claims 1 to 8, wherein the chip package further comprises at least one metal ball respectively arranged on the at least one third pad.
The chip package according to any one of claims 1 to 9, wherein the wiring layer comprises a second insulating layer and metal wiring arranged in the second insulating layer, and the at least one conductive pillar They are respectively connected to the at least one third pad through the metal wiring.
The chip package according to any one of claims 1 to 10, wherein the IPD includes at least one of the following:

Capacitors, resistors, inductors, transformers, antennas, transducers, piezoelectric devices, crystal oscillators and memristors.
A method for preparing a chip package, which is characterized in that:

A device layer is prepared above the chip. The upper surface of the chip is provided with at least one first pad and at least one second pad. The device layer includes a first insulating layer, at least one conductive pillar and an integrated passive device IPD The first insulating layer is arranged above the chip, the at least one conductive pillar penetrates the first insulating layer and is arranged above the at least one first pad, and the IPD penetrates the first The insulating layer is arranged above the at least one second pad;

Preparing a wiring layer above the device layer;

At least one third pad is prepared on the wiring layer, and the at least one conductive pillar is connected to the at least one third pad through the wiring layer.
The method of claim 12, wherein the preparing a device layer above the chip comprises:

Preparing a dry film layer above the chip;

Forming at least one groove penetrating the dry film layer above the at least one first pad;

Preparing the at least one conductive pillar in the at least one groove;

Removing the dry film layer;

Disposing the IPD above the at least one second pad;

A first insulating layer is prepared above the chip, so that the first insulating layer covers the at least one conductive layer and the IPD.
The method according to claim 13, wherein the preparing a dry film layer above the chip comprises:

Preparing at least one of an adhesion layer, a barrier layer and a seed layer above the chip;

The dry film layer is prepared above at least one of the adhesion layer, the barrier layer, and the seed layer, so that the at least one conductive pillar is grown on at least one of the adhesion layer, the barrier layer, and the seed layer ；

Wherein, the removing the dry film layer includes:

Removing at least one of the dry film layer and the adhesion layer, the barrier layer, and the seed layer under the dry film layer.
The method of claim 12, wherein the preparing a device layer above the chip comprises:

Preparing the IPD above the at least one second pad;

Preparing the first insulating layer above the chip;

Forming at least one groove penetrating the first insulating layer above the at least one first pad;

The at least one conductive pillar is prepared in the at least one groove, so that the first insulating layer covers the at least one conductive layer and the IPD.
The method according to claim 15, wherein the preparing the at least one conductive pillar in the at least one groove comprises:

Preparing at least one of an adhesion layer, a barrier layer and a seed layer on the inner wall of each groove in the at least one groove;

The conductive layer is grown on at least one of the adhesion layer, the barrier layer, and the seed layer to form the at least one conductive pillar.
The method according to claim 16, wherein the preparing at least one of an adhesion layer, a barrier layer and a seed layer on the inner wall of each groove in the at least one groove comprises:

Preparing at least one of an adhesion layer, a barrier layer and a seed layer above the at least one first pad and the inner wall of each groove in the at least one groove;

Wherein, the growing the conductive layer on at least one of the adhesion layer, the barrier layer and the seed layer to form the at least one conductive pillar includes:

Growing the conductive layer on at least one of the adhesion layer, the barrier layer and the seed layer;

The conductive layer is thinned to expose the at least one conductive pillar.
The method according to any one of claims 12 to 17, wherein at least one conductive bump is provided on a side of the IPD close to the chip, and the at least one conductive bump is respectively connected to the At least one second pad.
The method according to claim 18, wherein a non-conductive material is provided at a connection between the at least one conductive bump and the at least one second pad.
The method according to any one of claims 12 to 19, wherein the preparing a device layer above the chip comprises:

Preparing a device layer on top of the first wafer;

Preparing a first adhesive layer under the first wafer to form chips to be cut;

The chip to be cut is cut to form at least one chip, and each chip of the at least one chip is a chip integrated with the IPD.
The method according to claim 20, wherein the method further comprises:

Before preparing the first adhesive layer under the first wafer, the substrate of the first wafer is thinned.
The method according to claim 20 or 21, wherein the preparing a wiring layer above the device layer comprises:

Sticking the at least one chip to the second adhesive layer of the carrier;

Forming a molding compound on the carrier sheet, and the molding compound is used to mold the chip, the device layer and the first adhesive layer;

Thinning the molding compound to expose the at least one conductive pillar;

On the molding compound and the chip, the wiring layer is prepared.
The method according to claim 22, wherein the preparing at least one third pad on the wiring layer comprises:

Preparing the at least one third pad on the wiring layer;

Removing the second adhesive layer and the carrier sheet to form a package to be cut;

Cutting the package to be cut to form at least one chip package.
The method according to any one of claims 12 to 23, wherein the chip comprises an interconnection layer and a substrate, and the at least one first pad and the at least one second pad are embedded in the In the interconnection layer.
The method according to claim 24, wherein the plane where the upper surface of the at least one first pad is located, the plane where the upper surface of the at least one second pad is located, and the upper surface of the interconnect layer The plane is the same plane.
The method according to any one of claims 12 to 25, wherein the method further comprises:

At least one metal ball is prepared above the at least one third pad.
The method according to any one of claims 12 to 26, wherein the wiring layer comprises a second insulating layer and a metal wiring arranged in the second insulating layer, and the at least one conductive pillar passes through the The metal wirings are respectively connected to the at least one third pad.
The method according to any one of claims 12 to 27, wherein the IPD includes at least one of the following:

Capacitors, resistors, inductors, transformers, antennas, transducers, piezoelectric devices, crystal oscillators and memristors.
A chip package is characterized in that it comprises:

A chip package prepared according to the method of any one of claims 12 to 28.